arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/slab.h>
  21 #include <linux/cpu.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdebug.h>
  26 #include <linux/delay.h>
  27 #include <linux/crash_dump.h>
  28 #include <linux/reboot.h>
  29
  30 #include <asm/uv/uv_mmrs.h>
  31 #include <asm/uv/uv_hub.h>
  32 #include <asm/current.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/uv/bios.h>
  35 #include <asm/uv/uv.h>
  36 #include <asm/apic.h>
  37 #include <asm/ipi.h>
  38 #include <asm/smp.h>
  39 #include <asm/x86_init.h>
  40 #include <asm/nmi.h>
  41
  42 DEFINE_PER_CPU(int, x2apic_extra_bits);
  43
  44 #define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
  45
  46 static enum uv_system_type uv_system_type;
  47 static u64 gru_start_paddr, gru_end_paddr;
  48 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
  49 static u64 gru_dist_lmask, gru_dist_umask;
  50 static union uvh_apicid uvh_apicid;
  51 int uv_min_hub_revision_id;
  52 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  53 unsigned int uv_apicid_hibits;
  54 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
  55
  56 static struct apic apic_x2apic_uv_x;
  57
  58 static unsigned long __init uv_early_read_mmr(unsigned long addr)
  59 {
  60         unsigned long val, *mmr;
  61
  62         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
  63         val = *mmr;
  64         early_iounmap(mmr, sizeof(*mmr));
  65         return val;
  66 }
  67
  68 static inline bool is_GRU_range(u64 start, u64 end)
  69 {
  70         if (gru_dist_base) {
  71                 u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */
  72                 u64 sl = start & gru_dist_lmask; /* base offset bits */
  73                 u64 eu = end & gru_dist_umask;
  74                 u64 el = end & gru_dist_lmask;
  75
  76                 /* Must reside completely within a single GRU range */
  77                 return (sl == gru_dist_base && el == gru_dist_base &&
  78                         su >= gru_first_node_paddr &&
  79                         su <= gru_last_node_paddr &&
  80                         eu == su);
  81         } else {
  82                 return start >= gru_start_paddr && end <= gru_end_paddr;
  83         }
  84 }
  85
  86 static bool uv_is_untracked_pat_range(u64 start, u64 end)
  87 {
  88         return is_ISA_range(start, end) || is_GRU_range(start, end);
  89 }
  90
  91 static int __init early_get_pnodeid(void)
  92 {
  93         union uvh_node_id_u node_id;
  94         union uvh_rh_gam_config_mmr_u  m_n_config;
  95         int pnode;
  96
  97         /* Currently, all blades have same revision number */
  98         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
  99         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
 100         uv_min_hub_revision_id = node_id.s.revision;
 101
 102         switch (node_id.s.part_number) {
 103         case UV2_HUB_PART_NUMBER:
 104         case UV2_HUB_PART_NUMBER_X:
 105                 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
 106                 break;
 107         case UV3_HUB_PART_NUMBER:
 108         case UV3_HUB_PART_NUMBER_X:
 109                 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
 110                 break;
 111         }
 112
 113         uv_hub_info->hub_revision = uv_min_hub_revision_id;
 114         pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
 115         return pnode;
 116 }
 117
 118 static void __init early_get_apic_pnode_shift(void)
 119 {
 120         uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
 121         if (!uvh_apicid.v)
 122                 /*
 123                  * Old bios, use default value
 124                  */
 125                 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
 126 }
 127
 128 /*
 129  * Add an extra bit as dictated by bios to the destination apicid of
 130  * interrupts potentially passing through the UV HUB.  This prevents
 131  * a deadlock between interrupts and IO port operations.
 132  */
 133 static void __init uv_set_apicid_hibit(void)
 134 {
 135         union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
 136
 137         if (is_uv1_hub()) {
 138                 apicid_mask.v =
 139                         uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
 140                 uv_apicid_hibits =
 141                         apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
 142         }
 143 }
 144
 145 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 146 {
 147         int pnodeid;
 148         int uv_apic;
 149
 150         if (strncmp(oem_id, "SGI", 3) != 0)
 151                 return 0;
 152
 153         /*
 154          * Determine UV arch type.
 155          *   SGI: UV100/1000
 156          *   SGI2: UV2000/3000
 157          *   SGI3: UV300 (truncated to 4 chars because of different varieties)
 158          */
 159         uv_hub_info->hub_revision =
 160                 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
 161                 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
 162                 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
 163
 164         if (uv_hub_info->hub_revision == 0)
 165                 goto badbios;
 166
 167         pnodeid = early_get_pnodeid();
 168         early_get_apic_pnode_shift();
 169         x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
 170         x86_platform.nmi_init = uv_nmi_init;
 171
 172         if (!strcmp(oem_table_id, "UVX")) {             /* most common */
 173                 uv_system_type = UV_X2APIC;
 174                 uv_apic = 0;
 175
 176         } else if (!strcmp(oem_table_id, "UVH")) {      /* only UV1 systems */
 177                 uv_system_type = UV_NON_UNIQUE_APIC;
 178                 __this_cpu_write(x2apic_extra_bits,
 179                         pnodeid << uvh_apicid.s.pnode_shift);
 180                 uv_set_apicid_hibit();
 181                 uv_apic = 1;
 182
 183         } else  if (!strcmp(oem_table_id, "UVL")) {     /* only used for */
 184                 uv_system_type = UV_LEGACY_APIC;        /* very small systems */
 185                 uv_apic = 0;
 186
 187         } else {
 188                 goto badbios;
 189         }
 190
 191         pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n",
 192                 oem_id, oem_table_id, uv_system_type,
 193                 uv_min_hub_revision_id, uv_apic);
 194
 195         return uv_apic;
 196
 197 badbios:
 198         pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
 199         pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
 200         BUG();
 201 }
 202
 203 enum uv_system_type get_uv_system_type(void)
 204 {
 205         return uv_system_type;
 206 }
 207
 208 int is_uv_system(void)
 209 {
 210         return uv_system_type != UV_NONE;
 211 }
 212 EXPORT_SYMBOL_GPL(is_uv_system);
 213
 214 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 215 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
 216
 217 struct uv_blade_info *uv_blade_info;
 218 EXPORT_SYMBOL_GPL(uv_blade_info);
 219
 220 short *uv_node_to_blade;
 221 EXPORT_SYMBOL_GPL(uv_node_to_blade);
 222
 223 short *uv_cpu_to_blade;
 224 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
 225
 226 short uv_possible_blades;
 227 EXPORT_SYMBOL_GPL(uv_possible_blades);
 228
 229 unsigned long sn_rtc_cycles_per_second;
 230 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 231
 232 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 233 {
 234         unsigned long val;
 235         int pnode;
 236
 237         pnode = uv_apicid_to_pnode(phys_apicid);
 238         phys_apicid |= uv_apicid_hibits;
 239         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 240             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 241             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 242             APIC_DM_INIT;
 243         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 244
 245         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 246             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 247             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 248             APIC_DM_STARTUP;
 249         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 250
 251         return 0;
 252 }
 253
 254 static void uv_send_IPI_one(int cpu, int vector)
 255 {
 256         unsigned long apicid;
 257         int pnode;
 258
 259         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 260         pnode = uv_apicid_to_pnode(apicid);
 261         uv_hub_send_ipi(pnode, apicid, vector);
 262 }
 263
 264 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 265 {
 266         unsigned int cpu;
 267
 268         for_each_cpu(cpu, mask)
 269                 uv_send_IPI_one(cpu, vector);
 270 }
 271
 272 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 273 {
 274         unsigned int this_cpu = smp_processor_id();
 275         unsigned int cpu;
 276
 277         for_each_cpu(cpu, mask) {
 278                 if (cpu != this_cpu)
 279                         uv_send_IPI_one(cpu, vector);
 280         }
 281 }
 282
 283 static void uv_send_IPI_allbutself(int vector)
 284 {
 285         unsigned int this_cpu = smp_processor_id();
 286         unsigned int cpu;
 287
 288         for_each_online_cpu(cpu) {
 289                 if (cpu != this_cpu)
 290                         uv_send_IPI_one(cpu, vector);
 291         }
 292 }
 293
 294 static void uv_send_IPI_all(int vector)
 295 {
 296         uv_send_IPI_mask(cpu_online_mask, vector);
 297 }
 298
 299 static int uv_apic_id_valid(int apicid)
 300 {
 301         return 1;
 302 }
 303
 304 static int uv_apic_id_registered(void)
 305 {
 306         return 1;
 307 }
 308
 309 static void uv_init_apic_ldr(void)
 310 {
 311 }
 312
 313 static int
 314 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 315                           const struct cpumask *andmask,
 316                           unsigned int *apicid)
 317 {
 318         int unsigned cpu;
 319
 320         /*
 321          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 322          * May as well be the first.
 323          */
 324         for_each_cpu_and(cpu, cpumask, andmask) {
 325                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 326                         break;
 327         }
 328
 329         if (likely(cpu < nr_cpu_ids)) {
 330                 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
 331                 return 0;
 332         }
 333
 334         return -EINVAL;
 335 }
 336
 337 static unsigned int x2apic_get_apic_id(unsigned long x)
 338 {
 339         unsigned int id;
 340
 341         WARN_ON(preemptible() && num_online_cpus() > 1);
 342         id = x | __this_cpu_read(x2apic_extra_bits);
 343
 344         return id;
 345 }
 346
 347 static unsigned long set_apic_id(unsigned int id)
 348 {
 349         unsigned long x;
 350
 351         /* maskout x2apic_extra_bits ? */
 352         x = id;
 353         return x;
 354 }
 355
 356 static unsigned int uv_read_apic_id(void)
 357 {
 358
 359         return x2apic_get_apic_id(apic_read(APIC_ID));
 360 }
 361
 362 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 363 {
 364         return uv_read_apic_id() >> index_msb;
 365 }
 366
 367 static void uv_send_IPI_self(int vector)
 368 {
 369         apic_write(APIC_SELF_IPI, vector);
 370 }
 371
 372 static int uv_probe(void)
 373 {
 374         return apic == &apic_x2apic_uv_x;
 375 }
 376
 377 static struct apic __refdata apic_x2apic_uv_x = {
 378
 379         .name                           = "UV large system",
 380         .probe                          = uv_probe,
 381         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 382         .apic_id_valid                  = uv_apic_id_valid,
 383         .apic_id_registered             = uv_apic_id_registered,
 384
 385         .irq_delivery_mode              = dest_Fixed,
 386         .irq_dest_mode                  = 0, /* physical */
 387
 388         .target_cpus                    = online_target_cpus,
 389         .disable_esr                    = 0,
 390         .dest_logical                   = APIC_DEST_LOGICAL,
 391         .check_apicid_used              = NULL,
 392
 393         .vector_allocation_domain       = default_vector_allocation_domain,
 394         .init_apic_ldr                  = uv_init_apic_ldr,
 395
 396         .ioapic_phys_id_map             = NULL,
 397         .setup_apic_routing             = NULL,
 398         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 399         .apicid_to_cpu_present          = NULL,
 400         .check_phys_apicid_present      = default_check_phys_apicid_present,
 401         .phys_pkg_id                    = uv_phys_pkg_id,
 402
 403         .get_apic_id                    = x2apic_get_apic_id,
 404         .set_apic_id                    = set_apic_id,
 405         .apic_id_mask                   = 0xFFFFFFFFu,
 406
 407         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 408
 409         .send_IPI                       = uv_send_IPI_one,
 410         .send_IPI_mask                  = uv_send_IPI_mask,
 411         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 412         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 413         .send_IPI_all                   = uv_send_IPI_all,
 414         .send_IPI_self                  = uv_send_IPI_self,
 415
 416         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 417         .inquire_remote_apic            = NULL,
 418
 419         .read                           = native_apic_msr_read,
 420         .write                          = native_apic_msr_write,
 421         .eoi_write                      = native_apic_msr_eoi_write,
 422         .icr_read                       = native_x2apic_icr_read,
 423         .icr_write                      = native_x2apic_icr_write,
 424         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 425         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 426 };
 427
 428 static void set_x2apic_extra_bits(int pnode)
 429 {
 430         __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
 431 }
 432
 433 /*
 434  * Called on boot cpu.
 435  */
 436 static __init int boot_pnode_to_blade(int pnode)
 437 {
 438         int blade;
 439
 440         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 441                 if (pnode == uv_blade_info[blade].pnode)
 442                         return blade;
 443         BUG();
 444 }
 445
 446 struct redir_addr {
 447         unsigned long redirect;
 448         unsigned long alias;
 449 };
 450
 451 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 452
 453 static __initdata struct redir_addr redir_addrs[] = {
 454         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
 455         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
 456         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
 457 };
 458
 459 static unsigned char get_n_lshift(int m_val)
 460 {
 461         union uv3h_gr0_gam_gr_config_u m_gr_config;
 462
 463         if (is_uv1_hub())
 464                 return m_val;
 465
 466         if (is_uv2_hub())
 467                 return m_val == 40 ? 40 : 39;
 468
 469         m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
 470         return m_gr_config.s3.m_skt;
 471 }
 472
 473 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 474 {
 475         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
 476         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 477         int i;
 478
 479         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 480                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 481                 if (alias.s.enable && alias.s.base == 0) {
 482                         *size = (1UL << alias.s.m_alias);
 483                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 484                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 485                         return;
 486                 }
 487         }
 488         *base = *size = 0;
 489 }
 490
 491 enum map_type {map_wb, map_uc};
 492
 493 static __init void map_high(char *id, unsigned long base, int pshift,
 494                         int bshift, int max_pnode, enum map_type map_type)
 495 {
 496         unsigned long bytes, paddr;
 497
 498         paddr = base << pshift;
 499         bytes = (1UL << bshift) * (max_pnode + 1);
 500         if (!paddr) {
 501                 pr_info("UV: Map %s_HI base address NULL\n", id);
 502                 return;
 503         }
 504         pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
 505         if (map_type == map_uc)
 506                 init_extra_mapping_uc(paddr, bytes);
 507         else
 508                 init_extra_mapping_wb(paddr, bytes);
 509 }
 510
 511 static __init void map_gru_distributed(unsigned long c)
 512 {
 513         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 514         u64 paddr;
 515         unsigned long bytes;
 516         int nid;
 517
 518         gru.v = c;
 519         /* only base bits 42:28 relevant in dist mode */
 520         gru_dist_base = gru.v & 0x000007fff0000000UL;
 521         if (!gru_dist_base) {
 522                 pr_info("UV: Map GRU_DIST base address NULL\n");
 523                 return;
 524         }
 525         bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 526         gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
 527         gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
 528         gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
 529         for_each_online_node(nid) {
 530                 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
 531                                 gru_dist_base;
 532                 init_extra_mapping_wb(paddr, bytes);
 533                 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
 534                 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
 535         }
 536         /* Save upper (63:M) bits of address only for is_GRU_range */
 537         gru_first_node_paddr &= gru_dist_umask;
 538         gru_last_node_paddr &= gru_dist_umask;
 539         pr_debug("UV: Map GRU_DIST base 0x%016llx  0x%016llx - 0x%016llx\n",
 540                 gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
 541 }
 542
 543 static __init void map_gru_high(int max_pnode)
 544 {
 545         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 546         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 547
 548         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 549         if (!gru.s.enable) {
 550                 pr_info("UV: GRU disabled\n");
 551                 return;
 552         }
 553
 554         if (is_uv3_hub() && gru.s3.mode) {
 555                 map_gru_distributed(gru.v);
 556                 return;
 557         }
 558         map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
 559         gru_start_paddr = ((u64)gru.s.base << shift);
 560         gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 561 }
 562
 563 static __init void map_mmr_high(int max_pnode)
 564 {
 565         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 566         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 567
 568         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 569         if (mmr.s.enable)
 570                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 571         else
 572                 pr_info("UV: MMR disabled\n");
 573 }
 574
 575 /*
 576  * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
 577  * and REDIRECT MMR regs are exactly the same on UV3.
 578  */
 579 struct mmioh_config {
 580         unsigned long overlay;
 581         unsigned long redirect;
 582         char *id;
 583 };
 584
 585 static __initdata struct mmioh_config mmiohs[] = {
 586         {
 587                 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
 588                 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
 589                 "MMIOH0"
 590         },
 591         {
 592                 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
 593                 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
 594                 "MMIOH1"
 595         },
 596 };
 597
 598 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
 599 {
 600         union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
 601         unsigned long mmr;
 602         unsigned long base;
 603         int i, n, shift, m_io, max_io;
 604         int nasid, lnasid, fi, li;
 605         char *id;
 606
 607         id = mmiohs[index].id;
 608         overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
 609         pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n",
 610                 id, overlay.v, overlay.s3.base, overlay.s3.m_io);
 611         if (!overlay.s3.enable) {
 612                 pr_info("UV: %s disabled\n", id);
 613                 return;
 614         }
 615
 616         shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
 617         base = (unsigned long)overlay.s3.base;
 618         m_io = overlay.s3.m_io;
 619         mmr = mmiohs[index].redirect;
 620         n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
 621         min_pnode *= 2;                         /* convert to NASID */
 622         max_pnode *= 2;
 623         max_io = lnasid = fi = li = -1;
 624
 625         for (i = 0; i < n; i++) {
 626                 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
 627
 628                 redirect.v = uv_read_local_mmr(mmr + i * 8);
 629                 nasid = redirect.s3.nasid;
 630                 if (nasid < min_pnode || max_pnode < nasid)
 631                         nasid = -1;             /* invalid NASID */
 632
 633                 if (nasid == lnasid) {
 634                         li = i;
 635                         if (i != n-1)           /* last entry check */
 636                                 continue;
 637                 }
 638
 639                 /* check if we have a cached (or last) redirect to print */
 640                 if (lnasid != -1 || (i == n-1 && nasid != -1))  {
 641                         unsigned long addr1, addr2;
 642                         int f, l;
 643
 644                         if (lnasid == -1) {
 645                                 f = l = i;
 646                                 lnasid = nasid;
 647                         } else {
 648                                 f = fi;
 649                                 l = li;
 650                         }
 651                         addr1 = (base << shift) +
 652                                 f * (unsigned long)(1 << m_io);
 653                         addr2 = (base << shift) +
 654                                 (l + 1) * (unsigned long)(1 << m_io);
 655                         pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
 656                                 id, fi, li, lnasid, addr1, addr2);
 657                         if (max_io < l)
 658                                 max_io = l;
 659                 }
 660                 fi = li = i;
 661                 lnasid = nasid;
 662         }
 663
 664         pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
 665                 id, base, shift, m_io, max_io);
 666
 667         if (max_io >= 0)
 668                 map_high(id, base, shift, m_io, max_io, map_uc);
 669 }
 670
 671 static __init void map_mmioh_high(int min_pnode, int max_pnode)
 672 {
 673         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 674         unsigned long mmr, base;
 675         int shift, enable, m_io, n_io;
 676
 677         if (is_uv3_hub()) {
 678                 /* Map both MMIOH Regions */
 679                 map_mmioh_high_uv3(0, min_pnode, max_pnode);
 680                 map_mmioh_high_uv3(1, min_pnode, max_pnode);
 681                 return;
 682         }
 683
 684         if (is_uv1_hub()) {
 685                 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 686                 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 687                 mmioh.v = uv_read_local_mmr(mmr);
 688                 enable = !!mmioh.s1.enable;
 689                 base = mmioh.s1.base;
 690                 m_io = mmioh.s1.m_io;
 691                 n_io = mmioh.s1.n_io;
 692         } else if (is_uv2_hub()) {
 693                 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 694                 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 695                 mmioh.v = uv_read_local_mmr(mmr);
 696                 enable = !!mmioh.s2.enable;
 697                 base = mmioh.s2.base;
 698                 m_io = mmioh.s2.m_io;
 699                 n_io = mmioh.s2.n_io;
 700         } else
 701                 return;
 702
 703         if (enable) {
 704                 max_pnode &= (1 << n_io) - 1;
 705                 pr_info(
 706                     "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
 707                         base, shift, m_io, n_io, max_pnode);
 708                 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
 709         } else {
 710                 pr_info("UV: MMIOH disabled\n");
 711         }
 712 }
 713
 714 static __init void map_low_mmrs(void)
 715 {
 716         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 717         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 718 }
 719
 720 static __init void uv_rtc_init(void)
 721 {
 722         long status;
 723         u64 ticks_per_sec;
 724
 725         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 726                                         &ticks_per_sec);
 727         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 728                 printk(KERN_WARNING
 729                         "unable to determine platform RTC clock frequency, "
 730                         "guessing.\n");
 731                 /* BIOS gives wrong value for clock freq. so guess */
 732                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 733         } else
 734                 sn_rtc_cycles_per_second = ticks_per_sec;
 735 }
 736
 737 /*
 738  * percpu heartbeat timer
 739  */
 740 static void uv_heartbeat(unsigned long ignored)
 741 {
 742         struct timer_list *timer = &uv_hub_info->scir.timer;
 743         unsigned char bits = uv_hub_info->scir.state;
 744
 745         /* flip heartbeat bit */
 746         bits ^= SCIR_CPU_HEARTBEAT;
 747
 748         /* is this cpu idle? */
 749         if (idle_cpu(raw_smp_processor_id()))
 750                 bits &= ~SCIR_CPU_ACTIVITY;
 751         else
 752                 bits |= SCIR_CPU_ACTIVITY;
 753
 754         /* update system controller interface reg */
 755         uv_set_scir_bits(bits);
 756
 757         /* enable next timer period */
 758         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 759 }
 760
 761 static void uv_heartbeat_enable(int cpu)
 762 {
 763         while (!uv_cpu_hub_info(cpu)->scir.enabled) {
 764                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 765
 766                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 767                 setup_timer(timer, uv_heartbeat, cpu);
 768                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 769                 add_timer_on(timer, cpu);
 770                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 771
 772                 /* also ensure that boot cpu is enabled */
 773                 cpu = 0;
 774         }
 775 }
 776
 777 #ifdef CONFIG_HOTPLUG_CPU
 778 static void uv_heartbeat_disable(int cpu)
 779 {
 780         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 781                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 782                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 783         }
 784         uv_set_cpu_scir_bits(cpu, 0xff);
 785 }
 786
 787 /*
 788  * cpu hotplug notifier
 789  */
 790 static int uv_scir_cpu_notify(struct notifier_block *self, unsigned long action,
 791                               void *hcpu)
 792 {
 793         long cpu = (long)hcpu;
 794
 795         switch (action & ~CPU_TASKS_FROZEN) {
 796         case CPU_DOWN_FAILED:
 797         case CPU_ONLINE:
 798                 uv_heartbeat_enable(cpu);
 799                 break;
 800         case CPU_DOWN_PREPARE:
 801                 uv_heartbeat_disable(cpu);
 802                 break;
 803         default:
 804                 break;
 805         }
 806         return NOTIFY_OK;
 807 }
 808
 809 static __init void uv_scir_register_cpu_notifier(void)
 810 {
 811         hotcpu_notifier(uv_scir_cpu_notify, 0);
 812 }
 813
 814 #else /* !CONFIG_HOTPLUG_CPU */
 815
 816 static __init void uv_scir_register_cpu_notifier(void)
 817 {
 818 }
 819
 820 static __init int uv_init_heartbeat(void)
 821 {
 822         int cpu;
 823
 824         if (is_uv_system())
 825                 for_each_online_cpu(cpu)
 826                         uv_heartbeat_enable(cpu);
 827         return 0;
 828 }
 829
 830 late_initcall(uv_init_heartbeat);
 831
 832 #endif /* !CONFIG_HOTPLUG_CPU */
 833
 834 /* Direct Legacy VGA I/O traffic to designated IOH */
 835 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
 836                       unsigned int command_bits, u32 flags)
 837 {
 838         int domain, bus, rc;
 839
 840         PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
 841                         pdev->devfn, decode, command_bits, flags);
 842
 843         if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
 844                 return 0;
 845
 846         if ((command_bits & PCI_COMMAND_IO) == 0)
 847                 return 0;
 848
 849         domain = pci_domain_nr(pdev->bus);
 850         bus = pdev->bus->number;
 851
 852         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
 853         PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
 854
 855         return rc;
 856 }
 857
 858 /*
 859  * Called on each cpu to initialize the per_cpu UV data area.
 860  * FIXME: hotplug not supported yet
 861  */
 862 void uv_cpu_init(void)
 863 {
 864         /* CPU 0 initialization will be done via uv_system_init. */
 865         if (!uv_blade_info)
 866                 return;
 867
 868         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 869
 870         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 871                 set_x2apic_extra_bits(uv_hub_info->pnode);
 872 }
 873
 874 void __init uv_system_init(void)
 875 {
 876         union uvh_rh_gam_config_mmr_u  m_n_config;
 877         union uvh_node_id_u node_id;
 878         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 879         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 880         int gnode_extra, min_pnode = 999999, max_pnode = -1;
 881         unsigned long mmr_base, present, paddr;
 882         unsigned short pnode_mask;
 883         unsigned char n_lshift;
 884         char *hub = (is_uv1_hub() ? "UV100/1000" :
 885                     (is_uv2_hub() ? "UV2000/3000" :
 886                     (is_uv3_hub() ? "UV300" : NULL)));
 887
 888         if (!hub) {
 889                 pr_err("UV: Unknown/unsupported UV hub\n");
 890                 return;
 891         }
 892         pr_info("UV: Found %s hub\n", hub);
 893
 894         /* We now only need to map the MMRs on UV1 */
 895         if (is_uv1_hub())
 896                 map_low_mmrs();
 897
 898         m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
 899         m_val = m_n_config.s.m_skt;
 900         n_val = m_n_config.s.n_skt;
 901         pnode_mask = (1 << n_val) - 1;
 902         n_lshift = get_n_lshift(m_val);
 903         mmr_base =
 904             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 905             ~UV_MMR_ENABLE;
 906
 907         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 908         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
 909         gnode_upper = ((unsigned long)gnode_extra  << m_val);
 910         pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x n_lshift 0x%x\n",
 911                         n_val, m_val, pnode_mask, gnode_upper, gnode_extra,
 912                         n_lshift);
 913
 914         pr_info("UV: global MMR base 0x%lx\n", mmr_base);
 915
 916         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 917                 uv_possible_blades +=
 918                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 919
 920         /* uv_num_possible_blades() is really the hub count */
 921         pr_info("UV: Found %d blades, %d hubs\n",
 922                         is_uv1_hub() ? uv_num_possible_blades() :
 923                         (uv_num_possible_blades() + 1) / 2,
 924                         uv_num_possible_blades());
 925
 926         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 927         uv_blade_info = kzalloc(bytes, GFP_KERNEL);
 928         BUG_ON(!uv_blade_info);
 929
 930         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 931                 uv_blade_info[blade].memory_nid = -1;
 932
 933         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 934
 935         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 936         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 937         BUG_ON(!uv_node_to_blade);
 938         memset(uv_node_to_blade, 255, bytes);
 939
 940         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 941         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 942         BUG_ON(!uv_cpu_to_blade);
 943         memset(uv_cpu_to_blade, 255, bytes);
 944
 945         blade = 0;
 946         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 947                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 948                 for (j = 0; j < 64; j++) {
 949                         if (!test_bit(j, &present))
 950                                 continue;
 951                         pnode = (i * 64 + j) & pnode_mask;
 952                         uv_blade_info[blade].pnode = pnode;
 953                         uv_blade_info[blade].nr_possible_cpus = 0;
 954                         uv_blade_info[blade].nr_online_cpus = 0;
 955                         spin_lock_init(&uv_blade_info[blade].nmi_lock);
 956                         min_pnode = min(pnode, min_pnode);
 957                         max_pnode = max(pnode, max_pnode);
 958                         blade++;
 959                 }
 960         }
 961
 962         uv_bios_init();
 963         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
 964                             &sn_region_size, &system_serial_number);
 965         uv_rtc_init();
 966
 967         for_each_present_cpu(cpu) {
 968                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
 969
 970                 nid = cpu_to_node(cpu);
 971                 /*
 972                  * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
 973                  */
 974                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
 975                 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
 976                 uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
 977
 978                 uv_cpu_hub_info(cpu)->m_shift = 64 - m_val;
 979                 uv_cpu_hub_info(cpu)->n_lshift = n_lshift;
 980
 981                 pnode = uv_apicid_to_pnode(apicid);
 982                 blade = boot_pnode_to_blade(pnode);
 983                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 984                 uv_blade_info[blade].nr_possible_cpus++;
 985
 986                 /* Any node on the blade, else will contain -1. */
 987                 uv_blade_info[blade].memory_nid = nid;
 988
 989                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 990                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 991                 uv_cpu_hub_info(cpu)->m_val = m_val;
 992                 uv_cpu_hub_info(cpu)->n_val = n_val;
 993                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 994                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 995                 uv_cpu_hub_info(cpu)->pnode = pnode;
 996                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
 997                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 998                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
 999                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
1000                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
1001                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
1002                 uv_node_to_blade[nid] = blade;
1003                 uv_cpu_to_blade[cpu] = blade;
1004         }
1005
1006         /* Add blade/pnode info for nodes without cpus */
1007         for_each_online_node(nid) {
1008                 if (uv_node_to_blade[nid] >= 0)
1009                         continue;
1010                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
1011                 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1012                 blade = boot_pnode_to_blade(pnode);
1013                 uv_node_to_blade[nid] = blade;
1014         }
1015
1016         map_gru_high(max_pnode);
1017         map_mmr_high(max_pnode);
1018         map_mmioh_high(min_pnode, max_pnode);
1019
1020         uv_nmi_setup();
1021         uv_cpu_init();
1022         uv_scir_register_cpu_notifier();
1023         proc_mkdir("sgi_uv", NULL);
1024
1025         /* register Legacy VGA I/O redirection handler */
1026         pci_register_set_vga_state(uv_set_vga_state);
1027
1028         /*
1029          * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
1030          * EFI is not enabled in the kdump kernel.
1031          */
1032         if (is_kdump_kernel())
1033                 reboot_type = BOOT_ACPI;
1034 }
1035
1036 apic_driver(apic_x2apic_uv_x);