2 * arch/sh/kernel/cpu/sh4/clock-shx3.c
4 * SH-X3 support for the clock framework
6 * Copyright (C) 2006-2007 Renesas Technology Corp.
7 * Copyright (C) 2006-2007 Renesas Solutions Corp.
8 * Copyright (C) 2006-2007 Paul Mundt
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/init.h>
15 #include <linux/kernel.h>
17 #include <asm/clkdev.h>
18 #include <asm/clock.h>
21 static int ifc_divisors[] = { 1, 2, 4 ,6 };
22 static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };
23 static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 };
24 static int cfc_divisors[] = { 1, 1, 4, 6 };
27 #define IFC_MSK 0x0003
28 #define BFC_MSK 0x000f
29 #define PFC_MSK 0x000f
30 #define CFC_MSK 0x0003
35 static void master_clk_init(struct clk *clk)
37 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK];
40 static struct clk_ops shx3_master_clk_ops = {
41 .init = master_clk_init,
44 static unsigned long module_clk_recalc(struct clk *clk)
46 int idx = ((__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK);
47 return clk->parent->rate / pfc_divisors[idx];
50 static struct clk_ops shx3_module_clk_ops = {
51 .recalc = module_clk_recalc,
54 static unsigned long bus_clk_recalc(struct clk *clk)
56 int idx = ((__raw_readl(FRQCR) >> BFC_POS) & BFC_MSK);
57 return clk->parent->rate / bfc_divisors[idx];
60 static struct clk_ops shx3_bus_clk_ops = {
61 .recalc = bus_clk_recalc,
64 static unsigned long cpu_clk_recalc(struct clk *clk)
66 int idx = ((__raw_readl(FRQCR) >> IFC_POS) & IFC_MSK);
67 return clk->parent->rate / ifc_divisors[idx];
70 static struct clk_ops shx3_cpu_clk_ops = {
71 .recalc = cpu_clk_recalc,
74 static struct clk_ops *shx3_clk_ops[] = {
81 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
83 if (idx < ARRAY_SIZE(shx3_clk_ops))
84 *ops = shx3_clk_ops[idx];
87 static unsigned long shyway_clk_recalc(struct clk *clk)
89 int idx = ((__raw_readl(FRQCR) >> CFC_POS) & CFC_MSK);
90 return clk->parent->rate / cfc_divisors[idx];
93 static struct clk_ops shx3_shyway_clk_ops = {
94 .recalc = shyway_clk_recalc,
97 static struct clk shx3_shyway_clk = {
98 .flags = CLK_ENABLE_ON_INIT,
99 .ops = &shx3_shyway_clk_ops,
103 * Additional SHx3-specific on-chip clocks that aren't already part of the
106 static struct clk *shx3_onchip_clocks[] = {
110 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
112 static struct clk_lookup lookups[] = {
114 CLKDEV_CON_ID("shyway_clk", &shx3_shyway_clk),
117 int __init arch_clk_init(void)
124 clk = clk_get(NULL, "master_clk");
125 for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) {
126 struct clk *clkp = shx3_onchip_clocks[i];
129 ret |= clk_register(clkp);
134 clkdev_add_table(lookups, ARRAY_SIZE(lookups));