arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
   4  *
   5  * Copyright 2016 Freescale Semiconductor, Inc.
   6  * Copyright 2018 NXP
   7  *
   8  * Mingkai Hu <mingkai.hu@nxp.com>
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "fsl,ls1046a";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 crypto = &crypto;
  22                 fman0 = &fman0;
  23                 ethernet0 = &enet0;
  24                 ethernet1 = &enet1;
  25                 ethernet2 = &enet2;
  26                 ethernet3 = &enet3;
  27                 ethernet4 = &enet4;
  28                 ethernet5 = &enet5;
  29                 ethernet6 = &enet6;
  30                 ethernet7 = &enet7;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu0: cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a72";
  40                         reg = <0x0>;
  41                         clocks = <&clockgen 1 0>;
  42                         next-level-cache = <&l2>;
  43                         cpu-idle-states = <&CPU_PH20>;
  44                         #cooling-cells = <2>;
  45                 };
  46
  47                 cpu1: cpu@1 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a72";
  50                         reg = <0x1>;
  51                         clocks = <&clockgen 1 0>;
  52                         next-level-cache = <&l2>;
  53                         cpu-idle-states = <&CPU_PH20>;
  54                         #cooling-cells = <2>;
  55                 };
  56
  57                 cpu2: cpu@2 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a72";
  60                         reg = <0x2>;
  61                         clocks = <&clockgen 1 0>;
  62                         next-level-cache = <&l2>;
  63                         cpu-idle-states = <&CPU_PH20>;
  64                         #cooling-cells = <2>;
  65                 };
  66
  67                 cpu3: cpu@3 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a72";
  70                         reg = <0x3>;
  71                         clocks = <&clockgen 1 0>;
  72                         next-level-cache = <&l2>;
  73                         cpu-idle-states = <&CPU_PH20>;
  74                         #cooling-cells = <2>;
  75                 };
  76
  77                 l2: l2-cache {
  78                         compatible = "cache";
  79                 };
  80         };
  81
  82         idle-states {
  83                 /*
  84                  * PSCI node is not added default, U-boot will add missing
  85                  * parts if it determines to use PSCI.
  86                  */
  87                 entry-method = "psci";
  88
  89                 CPU_PH20: cpu-ph20 {
  90                         compatible = "arm,idle-state";
  91                         idle-state-name = "PH20";
  92                         arm,psci-suspend-param = <0x0>;
  93                         entry-latency-us = <1000>;
  94                         exit-latency-us = <1000>;
  95                         min-residency-us = <3000>;
  96                 };
  97         };
  98
  99         memory@80000000 {
 100                 device_type = "memory";
 101                 /* Real size will be filled by bootloader */
 102                 reg = <0x0 0x80000000 0x0 0x0>;
 103         };
 104
 105         sysclk: sysclk {
 106                 compatible = "fixed-clock";
 107                 #clock-cells = <0>;
 108                 clock-frequency = <100000000>;
 109                 clock-output-names = "sysclk";
 110         };
 111
 112         reboot {
 113                 compatible ="syscon-reboot";
 114                 regmap = <&dcfg>;
 115                 offset = <0xb0>;
 116                 mask = <0x02>;
 117         };
 118
 119         thermal-zones {
 120                 cpu_thermal: cpu-thermal {
 121                         polling-delay-passive = <1000>;
 122                         polling-delay = <5000>;
 123                         thermal-sensors = <&tmu 3>;
 124
 125                         trips {
 126                                 cpu_alert: cpu-alert {
 127                                         temperature = <85000>;
 128                                         hysteresis = <2000>;
 129                                         type = "passive";
 130                                 };
 131
 132                                 cpu_crit: cpu-crit {
 133                                         temperature = <95000>;
 134                                         hysteresis = <2000>;
 135                                         type = "critical";
 136                                 };
 137                         };
 138
 139                         cooling-maps {
 140                                 map0 {
 141                                         trip = <&cpu_alert>;
 142                                         cooling-device =
 143                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 144                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 145                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 146                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 147                                 };
 148                         };
 149                 };
 150         };
 151
 152         timer {
 153                 compatible = "arm,armv8-timer";
 154                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
 155                                           IRQ_TYPE_LEVEL_LOW)>,
 156                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
 157                                           IRQ_TYPE_LEVEL_LOW)>,
 158                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
 159                                           IRQ_TYPE_LEVEL_LOW)>,
 160                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
 161                                           IRQ_TYPE_LEVEL_LOW)>;
 162         };
 163
 164         pmu {
 165                 compatible = "arm,cortex-a72-pmu";
 166                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 170                 interrupt-affinity = <&cpu0>,
 171                                      <&cpu1>,
 172                                      <&cpu2>,
 173                                      <&cpu3>;
 174         };
 175
 176         gic: interrupt-controller@1400000 {
 177                 compatible = "arm,gic-400";
 178                 #interrupt-cells = <3>;
 179                 interrupt-controller;
 180                 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
 181                       <0x0 0x1420000 0 0x20000>, /* GICC */
 182                       <0x0 0x1440000 0 0x20000>, /* GICH */
 183                       <0x0 0x1460000 0 0x20000>; /* GICV */
 184                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 185                                          IRQ_TYPE_LEVEL_LOW)>;
 186         };
 187
 188         soc: soc {
 189                 compatible = "simple-bus";
 190                 #address-cells = <2>;
 191                 #size-cells = <2>;
 192                 ranges;
 193
 194                 ddr: memory-controller@1080000 {
 195                         compatible = "fsl,qoriq-memory-controller";
 196                         reg = <0x0 0x1080000 0x0 0x1000>;
 197                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 198                         big-endian;
 199                 };
 200
 201                 ifc: ifc@1530000 {
 202                         compatible = "fsl,ifc", "simple-bus";
 203                         reg = <0x0 0x1530000 0x0 0x10000>;
 204                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 205                 };
 206
 207                 qspi: spi@1550000 {
 208                         compatible = "fsl,ls1021a-qspi";
 209                         #address-cells = <1>;
 210                         #size-cells = <0>;
 211                         reg = <0x0 0x1550000 0x0 0x10000>,
 212                                 <0x0 0x40000000 0x0 0x10000000>;
 213                         reg-names = "QuadSPI", "QuadSPI-memory";
 214                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 215                         clock-names = "qspi_en", "qspi";
 216                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 217                         big-endian;
 218                         fsl,qspi-has-second-chip;
 219                         status = "disabled";
 220                 };
 221
 222                 esdhc: esdhc@1560000 {
 223                         compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
 224                         reg = <0x0 0x1560000 0x0 0x10000>;
 225                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 226                         clocks = <&clockgen 2 1>;
 227                         voltage-ranges = <1800 1800 3300 3300>;
 228                         sdhci,auto-cmd12;
 229                         big-endian;
 230                         bus-width = <4>;
 231                 };
 232
 233                 scfg: scfg@1570000 {
 234                         compatible = "fsl,ls1046a-scfg", "syscon";
 235                         reg = <0x0 0x1570000 0x0 0x10000>;
 236                         big-endian;
 237                 };
 238
 239                 crypto: crypto@1700000 {
 240                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 241                                      "fsl,sec-v4.0";
 242                         fsl,sec-era = <8>;
 243                         #address-cells = <1>;
 244                         #size-cells = <1>;
 245                         ranges = <0x0 0x00 0x1700000 0x100000>;
 246                         reg = <0x00 0x1700000 0x0 0x100000>;
 247                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 248
 249                         sec_jr0: jr@10000 {
 250                                 compatible = "fsl,sec-v5.4-job-ring",
 251                                              "fsl,sec-v5.0-job-ring",
 252                                              "fsl,sec-v4.0-job-ring";
 253                                 reg        = <0x10000 0x10000>;
 254                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 255                         };
 256
 257                         sec_jr1: jr@20000 {
 258                                 compatible = "fsl,sec-v5.4-job-ring",
 259                                              "fsl,sec-v5.0-job-ring",
 260                                              "fsl,sec-v4.0-job-ring";
 261                                 reg        = <0x20000 0x10000>;
 262                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 263                         };
 264
 265                         sec_jr2: jr@30000 {
 266                                 compatible = "fsl,sec-v5.4-job-ring",
 267                                              "fsl,sec-v5.0-job-ring",
 268                                              "fsl,sec-v4.0-job-ring";
 269                                 reg        = <0x30000 0x10000>;
 270                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 271                         };
 272
 273                         sec_jr3: jr@40000 {
 274                                 compatible = "fsl,sec-v5.4-job-ring",
 275                                              "fsl,sec-v5.0-job-ring",
 276                                              "fsl,sec-v4.0-job-ring";
 277                                 reg        = <0x40000 0x10000>;
 278                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 279                         };
 280                 };
 281
 282                 qman: qman@1880000 {
 283                         compatible = "fsl,qman";
 284                         reg = <0x0 0x1880000 0x0 0x10000>;
 285                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 286                         memory-region = <&qman_fqd &qman_pfdr>;
 287
 288                 };
 289
 290                 bman: bman@1890000 {
 291                         compatible = "fsl,bman";
 292                         reg = <0x0 0x1890000 0x0 0x10000>;
 293                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 294                         memory-region = <&bman_fbpr>;
 295
 296                 };
 297
 298                 qportals: qman-portals@500000000 {
 299                         ranges = <0x0 0x5 0x00000000 0x8000000>;
 300                 };
 301
 302                 bportals: bman-portals@508000000 {
 303                         ranges = <0x0 0x5 0x08000000 0x8000000>;
 304                 };
 305
 306                 dcfg: dcfg@1ee0000 {
 307                         compatible = "fsl,ls1046a-dcfg", "syscon";
 308                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 309                         big-endian;
 310                 };
 311
 312                 clockgen: clocking@1ee1000 {
 313                         compatible = "fsl,ls1046a-clockgen";
 314                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 315                         #clock-cells = <2>;
 316                         clocks = <&sysclk>;
 317                 };
 318
 319                 tmu: tmu@1f00000 {
 320                         compatible = "fsl,qoriq-tmu";
 321                         reg = <0x0 0x1f00000 0x0 0x10000>;
 322                         interrupts = <0 33 0x4>;
 323                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 324                         fsl,tmu-calibration =
 325                                 /* Calibration data group 1 */
 326                                 <0x00000000 0x00000026
 327                                 0x00000001 0x0000002d
 328                                 0x00000002 0x00000032
 329                                 0x00000003 0x00000039
 330                                 0x00000004 0x0000003f
 331                                 0x00000005 0x00000046
 332                                 0x00000006 0x0000004d
 333                                 0x00000007 0x00000054
 334                                 0x00000008 0x0000005a
 335                                 0x00000009 0x00000061
 336                                 0x0000000a 0x0000006a
 337                                 0x0000000b 0x00000071
 338                                 /* Calibration data group 2 */
 339                                 0x00010000 0x00000025
 340                                 0x00010001 0x0000002c
 341                                 0x00010002 0x00000035
 342                                 0x00010003 0x0000003d
 343                                 0x00010004 0x00000045
 344                                 0x00010005 0x0000004e
 345                                 0x00010006 0x00000057
 346                                 0x00010007 0x00000061
 347                                 0x00010008 0x0000006b
 348                                 0x00010009 0x00000076
 349                                 /* Calibration data group 3 */
 350                                 0x00020000 0x00000029
 351                                 0x00020001 0x00000033
 352                                 0x00020002 0x0000003d
 353                                 0x00020003 0x00000049
 354                                 0x00020004 0x00000056
 355                                 0x00020005 0x00000061
 356                                 0x00020006 0x0000006d
 357                                 /* Calibration data group 4 */
 358                                 0x00030000 0x00000021
 359                                 0x00030001 0x0000002a
 360                                 0x00030002 0x0000003c
 361                                 0x00030003 0x0000004e>;
 362                         big-endian;
 363                         #thermal-sensor-cells = <1>;
 364                 };
 365
 366                 dspi: spi@2100000 {
 367                         compatible = "fsl,ls1021a-v1.0-dspi";
 368                         #address-cells = <1>;
 369                         #size-cells = <0>;
 370                         reg = <0x0 0x2100000 0x0 0x10000>;
 371                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 372                         clock-names = "dspi";
 373                         clocks = <&clockgen 4 1>;
 374                         spi-num-chipselects = <5>;
 375                         big-endian;
 376                         status = "disabled";
 377                 };
 378
 379                 i2c0: i2c@2180000 {
 380                         compatible = "fsl,vf610-i2c";
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                         reg = <0x0 0x2180000 0x0 0x10000>;
 384                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 385                         clocks = <&clockgen 4 1>;
 386                         dmas = <&edma0 1 39>,
 387                                <&edma0 1 38>;
 388                         dma-names = "tx", "rx";
 389                         status = "disabled";
 390                 };
 391
 392                 i2c1: i2c@2190000 {
 393                         compatible = "fsl,vf610-i2c";
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                         reg = <0x0 0x2190000 0x0 0x10000>;
 397                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 398                         clocks = <&clockgen 4 1>;
 399                         status = "disabled";
 400                 };
 401
 402                 i2c2: i2c@21a0000 {
 403                         compatible = "fsl,vf610-i2c";
 404                         #address-cells = <1>;
 405                         #size-cells = <0>;
 406                         reg = <0x0 0x21a0000 0x0 0x10000>;
 407                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 408                         clocks = <&clockgen 4 1>;
 409                         status = "disabled";
 410                 };
 411
 412                 i2c3: i2c@21b0000 {
 413                         compatible = "fsl,vf610-i2c";
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416                         reg = <0x0 0x21b0000 0x0 0x10000>;
 417                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 418                         clocks = <&clockgen 4 1>;
 419                         status = "disabled";
 420                 };
 421
 422                 duart0: serial@21c0500 {
 423                         compatible = "fsl,ns16550", "ns16550a";
 424                         reg = <0x00 0x21c0500 0x0 0x100>;
 425                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 426                         clocks = <&clockgen 4 1>;
 427                 };
 428
 429                 duart1: serial@21c0600 {
 430                         compatible = "fsl,ns16550", "ns16550a";
 431                         reg = <0x00 0x21c0600 0x0 0x100>;
 432                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 433                         clocks = <&clockgen 4 1>;
 434                 };
 435
 436                 duart2: serial@21d0500 {
 437                         compatible = "fsl,ns16550", "ns16550a";
 438                         reg = <0x0 0x21d0500 0x0 0x100>;
 439                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 440                         clocks = <&clockgen 4 1>;
 441                 };
 442
 443                 duart3: serial@21d0600 {
 444                         compatible = "fsl,ns16550", "ns16550a";
 445                         reg = <0x0 0x21d0600 0x0 0x100>;
 446                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 447                         clocks = <&clockgen 4 1>;
 448                 };
 449
 450                 gpio0: gpio@2300000 {
 451                         compatible = "fsl,qoriq-gpio";
 452                         reg = <0x0 0x2300000 0x0 0x10000>;
 453                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 454                         gpio-controller;
 455                         #gpio-cells = <2>;
 456                         interrupt-controller;
 457                         #interrupt-cells = <2>;
 458                 };
 459
 460                 gpio1: gpio@2310000 {
 461                         compatible = "fsl,qoriq-gpio";
 462                         reg = <0x0 0x2310000 0x0 0x10000>;
 463                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 464                         gpio-controller;
 465                         #gpio-cells = <2>;
 466                         interrupt-controller;
 467                         #interrupt-cells = <2>;
 468                 };
 469
 470                 gpio2: gpio@2320000 {
 471                         compatible = "fsl,qoriq-gpio";
 472                         reg = <0x0 0x2320000 0x0 0x10000>;
 473                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 474                         gpio-controller;
 475                         #gpio-cells = <2>;
 476                         interrupt-controller;
 477                         #interrupt-cells = <2>;
 478                 };
 479
 480                 gpio3: gpio@2330000 {
 481                         compatible = "fsl,qoriq-gpio";
 482                         reg = <0x0 0x2330000 0x0 0x10000>;
 483                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 484                         gpio-controller;
 485                         #gpio-cells = <2>;
 486                         interrupt-controller;
 487                         #interrupt-cells = <2>;
 488                 };
 489
 490                 lpuart0: serial@2950000 {
 491                         compatible = "fsl,ls1021a-lpuart";
 492                         reg = <0x0 0x2950000 0x0 0x1000>;
 493                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 494                         clocks = <&clockgen 4 0>;
 495                         clock-names = "ipg";
 496                         status = "disabled";
 497                 };
 498
 499                 lpuart1: serial@2960000 {
 500                         compatible = "fsl,ls1021a-lpuart";
 501                         reg = <0x0 0x2960000 0x0 0x1000>;
 502                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 503                         clocks = <&clockgen 4 1>;
 504                         clock-names = "ipg";
 505                         status = "disabled";
 506                 };
 507
 508                 lpuart2: serial@2970000 {
 509                         compatible = "fsl,ls1021a-lpuart";
 510                         reg = <0x0 0x2970000 0x0 0x1000>;
 511                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 512                         clocks = <&clockgen 4 1>;
 513                         clock-names = "ipg";
 514                         status = "disabled";
 515                 };
 516
 517                 lpuart3: serial@2980000 {
 518                         compatible = "fsl,ls1021a-lpuart";
 519                         reg = <0x0 0x2980000 0x0 0x1000>;
 520                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 521                         clocks = <&clockgen 4 1>;
 522                         clock-names = "ipg";
 523                         status = "disabled";
 524                 };
 525
 526                 lpuart4: serial@2990000 {
 527                         compatible = "fsl,ls1021a-lpuart";
 528                         reg = <0x0 0x2990000 0x0 0x1000>;
 529                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 530                         clocks = <&clockgen 4 1>;
 531                         clock-names = "ipg";
 532                         status = "disabled";
 533                 };
 534
 535                 lpuart5: serial@29a0000 {
 536                         compatible = "fsl,ls1021a-lpuart";
 537                         reg = <0x0 0x29a0000 0x0 0x1000>;
 538                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 539                         clocks = <&clockgen 4 1>;
 540                         clock-names = "ipg";
 541                         status = "disabled";
 542                 };
 543
 544                 wdog0: watchdog@2ad0000 {
 545                         compatible = "fsl,imx21-wdt";
 546                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 547                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 548                         clocks = <&clockgen 4 1>;
 549                         big-endian;
 550                 };
 551
 552                 edma0: edma@2c00000 {
 553                         #dma-cells = <2>;
 554                         compatible = "fsl,vf610-edma";
 555                         reg = <0x0 0x2c00000 0x0 0x10000>,
 556                               <0x0 0x2c10000 0x0 0x10000>,
 557                               <0x0 0x2c20000 0x0 0x10000>;
 558                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 559                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 560                         interrupt-names = "edma-tx", "edma-err";
 561                         dma-channels = <32>;
 562                         big-endian;
 563                         clock-names = "dmamux0", "dmamux1";
 564                         clocks = <&clockgen 4 1>,
 565                                  <&clockgen 4 1>;
 566                 };
 567
 568                 usb0: usb@2f00000 {
 569                         compatible = "snps,dwc3";
 570                         reg = <0x0 0x2f00000 0x0 0x10000>;
 571                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 572                         dr_mode = "host";
 573                         snps,quirk-frame-length-adjustment = <0x20>;
 574                         snps,dis_rxdet_inp3_quirk;
 575                 };
 576
 577                 usb1: usb@3000000 {
 578                         compatible = "snps,dwc3";
 579                         reg = <0x0 0x3000000 0x0 0x10000>;
 580                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 581                         dr_mode = "host";
 582                         snps,quirk-frame-length-adjustment = <0x20>;
 583                         snps,dis_rxdet_inp3_quirk;
 584                 };
 585
 586                 usb2: usb@3100000 {
 587                         compatible = "snps,dwc3";
 588                         reg = <0x0 0x3100000 0x0 0x10000>;
 589                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 590                         dr_mode = "host";
 591                         snps,quirk-frame-length-adjustment = <0x20>;
 592                         snps,dis_rxdet_inp3_quirk;
 593                 };
 594
 595                 sata: sata@3200000 {
 596                         compatible = "fsl,ls1046a-ahci";
 597                         reg = <0x0 0x3200000 0x0 0x10000>,
 598                                 <0x0 0x20140520 0x0 0x4>;
 599                         reg-names = "ahci", "sata-ecc";
 600                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 601                         clocks = <&clockgen 4 1>;
 602                 };
 603
 604                 msi1: msi-controller@1580000 {
 605                         compatible = "fsl,ls1046a-msi";
 606                         msi-controller;
 607                         reg = <0x0 0x1580000 0x0 0x10000>;
 608                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 609                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 610                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 611                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 612                 };
 613
 614                 msi2: msi-controller@1590000 {
 615                         compatible = "fsl,ls1046a-msi";
 616                         msi-controller;
 617                         reg = <0x0 0x1590000 0x0 0x10000>;
 618                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 619                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 620                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 621                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 622                 };
 623
 624                 msi3: msi-controller@15a0000 {
 625                         compatible = "fsl,ls1046a-msi";
 626                         msi-controller;
 627                         reg = <0x0 0x15a0000 0x0 0x10000>;
 628                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 629                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 630                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 631                                      <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 632                 };
 633
 634                 pcie@3400000 {
 635                         compatible = "fsl,ls1046a-pcie";
 636                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 637                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 638                         reg-names = "regs", "config";
 639                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 640                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
 641                         interrupt-names = "aer", "pme";
 642                         #address-cells = <3>;
 643                         #size-cells = <2>;
 644                         device_type = "pci";
 645                         dma-coherent;
 646                         num-lanes = <4>;
 647                         bus-range = <0x0 0xff>;
 648                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 649                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 650                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 651                         #interrupt-cells = <1>;
 652                         interrupt-map-mask = <0 0 0 7>;
 653                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 654                                         <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 655                                         <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 656                                         <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 657                         status = "disabled";
 658                 };
 659
 660                 pcie@3500000 {
 661                         compatible = "fsl,ls1046a-pcie";
 662                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 663                                0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 664                         reg-names = "regs", "config";
 665                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 666                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
 667                         interrupt-names = "aer", "pme";
 668                         #address-cells = <3>;
 669                         #size-cells = <2>;
 670                         device_type = "pci";
 671                         dma-coherent;
 672                         num-lanes = <2>;
 673                         bus-range = <0x0 0xff>;
 674                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 675                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 676                         msi-parent = <&msi2>, <&msi3>, <&msi1>;
 677                         #interrupt-cells = <1>;
 678                         interrupt-map-mask = <0 0 0 7>;
 679                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 680                                         <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 681                                         <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 682                                         <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 683                         status = "disabled";
 684                 };
 685
 686                 pcie@3600000 {
 687                         compatible = "fsl,ls1046a-pcie";
 688                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 689                                0x50 0x00000000 0x0 0x00002000>; /* configuration space */
 690                         reg-names = "regs", "config";
 691                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 692                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
 693                         interrupt-names = "aer", "pme";
 694                         #address-cells = <3>;
 695                         #size-cells = <2>;
 696                         device_type = "pci";
 697                         dma-coherent;
 698                         num-lanes = <2>;
 699                         bus-range = <0x0 0xff>;
 700                         ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
 701                                   0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 702                         msi-parent = <&msi3>, <&msi1>, <&msi2>;
 703                         #interrupt-cells = <1>;
 704                         interrupt-map-mask = <0 0 0 7>;
 705                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 706                                         <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 707                                         <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 708                                         <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 709                         status = "disabled";
 710                 };
 711
 712         };
 713
 714         reserved-memory {
 715                 #address-cells = <2>;
 716                 #size-cells = <2>;
 717                 ranges;
 718
 719                 bman_fbpr: bman-fbpr {
 720                         compatible = "shared-dma-pool";
 721                         size = <0 0x1000000>;
 722                         alignment = <0 0x1000000>;
 723                         no-map;
 724                 };
 725
 726                 qman_fqd: qman-fqd {
 727                         compatible = "shared-dma-pool";
 728                         size = <0 0x800000>;
 729                         alignment = <0 0x800000>;
 730                         no-map;
 731                 };
 732
 733                 qman_pfdr: qman-pfdr {
 734                         compatible = "shared-dma-pool";
 735                         size = <0 0x2000000>;
 736                         alignment = <0 0x2000000>;
 737                         no-map;
 738                 };
 739         };
 740
 741         firmware {
 742                 optee {
 743                         compatible = "linaro,optee-tz";
 744                         method = "smc";
 745                 };
 746         };
 747 };
 748
 749 #include "qoriq-qman-portals.dtsi"
 750 #include "qoriq-bman-portals.dtsi"