arch/arm64/boot/dts/broadcom/ns2.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright (c) 2015 Broadcom.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34 #include <dt-bindings/clock/bcm-ns2.h>
  35
  36 / {
  37         compatible = "brcm,ns2";
  38         interrupt-parent = <&gic>;
  39         #address-cells = <2>;
  40         #size-cells = <2>;
  41
  42         cpus {
  43                 #address-cells = <2>;
  44                 #size-cells = <0>;
  45
  46                 A57_0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a57", "arm,armv8";
  49                         reg = <0 0>;
  50                         enable-method = "psci";
  51                         next-level-cache = <&CLUSTER0_L2>;
  52                 };
  53
  54                 A57_1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a57", "arm,armv8";
  57                         reg = <0 1>;
  58                         enable-method = "psci";
  59                         next-level-cache = <&CLUSTER0_L2>;
  60                 };
  61
  62                 A57_2: cpu@2 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a57", "arm,armv8";
  65                         reg = <0 2>;
  66                         enable-method = "psci";
  67                         next-level-cache = <&CLUSTER0_L2>;
  68                 };
  69
  70                 A57_3: cpu@3 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a57", "arm,armv8";
  73                         reg = <0 3>;
  74                         enable-method = "psci";
  75                         next-level-cache = <&CLUSTER0_L2>;
  76                 };
  77
  78                 CLUSTER0_L2: l2-cache@000 {
  79                         compatible = "cache";
  80                 };
  81         };
  82
  83         psci {
  84                 compatible = "arm,psci-1.0";
  85                 method = "smc";
  86         };
  87
  88         timer {
  89                 compatible = "arm,armv8-timer";
  90                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
  91                               IRQ_TYPE_EDGE_RISING)>,
  92                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
  93                               IRQ_TYPE_EDGE_RISING)>,
  94                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
  95                               IRQ_TYPE_EDGE_RISING)>,
  96                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
  97                               IRQ_TYPE_EDGE_RISING)>;
  98         };
  99
 100         pmu {
 101                 compatible = "arm,armv8-pmuv3";
 102                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 103                              <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 104                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 105                              <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 106                 interrupt-affinity = <&A57_0>,
 107                                      <&A57_1>,
 108                                      <&A57_2>,
 109                                      <&A57_3>;
 110         };
 111
 112         pcie0: pcie@20020000 {
 113                 compatible = "brcm,iproc-pcie";
 114                 reg = <0 0x20020000 0 0x1000>;
 115
 116                 #interrupt-cells = <1>;
 117                 interrupt-map-mask = <0 0 0 0>;
 118                 interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
 119
 120                 linux,pci-domain = <0>;
 121
 122                 bus-range = <0x00 0xff>;
 123
 124                 #address-cells = <3>;
 125                 #size-cells = <2>;
 126                 device_type = "pci";
 127                 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
 128
 129                 brcm,pcie-ob;
 130                 brcm,pcie-ob-oarr-size;
 131                 brcm,pcie-ob-axi-offset = <0x00000000>;
 132                 brcm,pcie-ob-window-size = <256>;
 133
 134                 status = "disabled";
 135
 136                 msi-parent = <&msi0>;
 137                 msi0: msi@20020000 {
 138                         compatible = "brcm,iproc-msi";
 139                         msi-controller;
 140                         interrupt-parent = <&gic>;
 141                         interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
 142                                      <GIC_SPI 278 IRQ_TYPE_NONE>,
 143                                      <GIC_SPI 279 IRQ_TYPE_NONE>,
 144                                      <GIC_SPI 280 IRQ_TYPE_NONE>;
 145                         brcm,num-eq-region = <1>;
 146                         brcm,num-msi-msg-region = <1>;
 147                 };
 148         };
 149
 150         pcie4: pcie@50020000 {
 151                 compatible = "brcm,iproc-pcie";
 152                 reg = <0 0x50020000 0 0x1000>;
 153
 154                 #interrupt-cells = <1>;
 155                 interrupt-map-mask = <0 0 0 0>;
 156                 interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
 157
 158                 linux,pci-domain = <4>;
 159
 160                 bus-range = <0x00 0xff>;
 161
 162                 #address-cells = <3>;
 163                 #size-cells = <2>;
 164                 device_type = "pci";
 165                 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
 166
 167                 brcm,pcie-ob;
 168                 brcm,pcie-ob-oarr-size;
 169                 brcm,pcie-ob-axi-offset = <0x30000000>;
 170                 brcm,pcie-ob-window-size = <256>;
 171
 172                 status = "disabled";
 173
 174                 msi-parent = <&msi4>;
 175                 msi4: msi@50020000 {
 176                         compatible = "brcm,iproc-msi";
 177                         msi-controller;
 178                         interrupt-parent = <&gic>;
 179                         interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
 180                                      <GIC_SPI 302 IRQ_TYPE_NONE>,
 181                                      <GIC_SPI 303 IRQ_TYPE_NONE>,
 182                                      <GIC_SPI 304 IRQ_TYPE_NONE>;
 183                 };
 184         };
 185
 186         soc: soc {
 187                 compatible = "simple-bus";
 188                 #address-cells = <1>;
 189                 #size-cells = <1>;
 190                 ranges = <0 0 0 0xffffffff>;
 191
 192                 #include "ns2-clock.dtsi"
 193
 194                 dma0: dma@61360000 {
 195                         compatible = "arm,pl330", "arm,primecell";
 196                         reg = <0x61360000 0x1000>;
 197                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 198                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 201                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 202                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 203                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 204                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 206                         #dma-cells = <1>;
 207                         #dma-channels = <8>;
 208                         #dma-requests = <32>;
 209                         clocks = <&iprocslow>;
 210                         clock-names = "apb_pclk";
 211                 };
 212
 213                 smmu: mmu@64000000 {
 214                         compatible = "arm,mmu-500";
 215                         reg = <0x64000000 0x40000>;
 216                         #global-interrupts = <2>;
 217                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 218                                      <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
 219                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
 220                                      <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
 221                                      <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
 222                                      <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
 223                                      <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
 224                                      <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
 225                                      <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 226                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 227                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 228                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
 229                                      <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 230                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 231                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 232                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 233                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 234                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 236                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 239                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 240                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 241                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 242                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 243                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 245                                      <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 247                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 248                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 249                                      <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 250                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
 251                         mmu-masters;
 252                 };
 253
 254                 gic: interrupt-controller@65210000 {
 255                         compatible = "arm,gic-400";
 256                         #interrupt-cells = <3>;
 257                         interrupt-controller;
 258                         reg = <0x65210000 0x1000>,
 259                               <0x65220000 0x1000>,
 260                               <0x65240000 0x2000>,
 261                               <0x65260000 0x1000>;
 262                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 263                                       IRQ_TYPE_LEVEL_HIGH)>;
 264                 };
 265
 266                 mdio_mux_iproc: mdio-mux@6602023c {
 267                         compatible = "brcm,mdio-mux-iproc";
 268                         reg = <0x6602023c 0x14>;
 269                         #address-cells = <1>;
 270                         #size-cells = <0>;
 271
 272                         mdio@0 {
 273                                 reg = <0x0>;
 274                                 #address-cells = <1>;
 275                                 #size-cells = <0>;
 276
 277                                 pci_phy0: pci-phy@0 {
 278                                         compatible = "brcm,ns2-pcie-phy";
 279                                         reg = <0x0>;
 280                                         #phy-cells = <0>;
 281                                         status = "disabled";
 282                                 };
 283                         };
 284
 285                         mdio@7 {
 286                                 reg = <0x7>;
 287                                 #address-cells = <1>;
 288                                 #size-cells = <0>;
 289
 290                                 pci_phy1: pci-phy@0 {
 291                                         compatible = "brcm,ns2-pcie-phy";
 292                                         reg = <0x0>;
 293                                         #phy-cells = <0>;
 294                                         status = "disabled";
 295                                 };
 296                         };
 297
 298                         mdio@10 {
 299                                 reg = <0x10>;
 300                                 #address-cells = <1>;
 301                                 #size-cells = <0>;
 302                         };
 303                 };
 304
 305                 timer0: timer@66030000 {
 306                         compatible = "arm,sp804", "arm,primecell";
 307                         reg = <0x66030000 0x1000>;
 308                         interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
 309                         clocks = <&iprocslow>,
 310                                  <&iprocslow>,
 311                                  <&iprocslow>;
 312                         clock-names = "timer1", "timer2", "apb_pclk";
 313                 };
 314
 315                 timer1: timer@66040000 {
 316                         compatible = "arm,sp804", "arm,primecell";
 317                         reg = <0x66040000 0x1000>;
 318                         interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 319                         clocks = <&iprocslow>,
 320                                  <&iprocslow>,
 321                                  <&iprocslow>;
 322                         clock-names = "timer1", "timer2", "apb_pclk";
 323                 };
 324
 325                 timer2: timer@66050000 {
 326                         compatible = "arm,sp804", "arm,primecell";
 327                         reg = <0x66050000 0x1000>;
 328                         interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
 329                         clocks = <&iprocslow>,
 330                                  <&iprocslow>,
 331                                  <&iprocslow>;
 332                         clock-names = "timer1", "timer2", "apb_pclk";
 333                 };
 334
 335                 timer3: timer@66060000 {
 336                         compatible = "arm,sp804", "arm,primecell";
 337                         reg = <0x66060000 0x1000>;
 338                         interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
 339                         clocks = <&iprocslow>,
 340                                  <&iprocslow>,
 341                                  <&iprocslow>;
 342                         clock-names = "timer1", "timer2", "apb_pclk";
 343                 };
 344
 345                 i2c0: i2c@66080000 {
 346                         compatible = "brcm,iproc-i2c";
 347                         reg = <0x66080000 0x100>;
 348                         #address-cells = <1>;
 349                         #size-cells = <0>;
 350                         interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
 351                         clock-frequency = <100000>;
 352                         status = "disabled";
 353                 };
 354
 355                 wdt0: watchdog@66090000 {
 356                         compatible = "arm,sp805", "arm,primecell";
 357                         reg = <0x66090000 0x1000>;
 358                         interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
 359                         clocks = <&iprocslow>, <&iprocslow>;
 360                         clock-names = "wdogclk", "apb_pclk";
 361                 };
 362
 363                 i2c1: i2c@660b0000 {
 364                         compatible = "brcm,iproc-i2c";
 365                         reg = <0x660b0000 0x100>;
 366                         #address-cells = <1>;
 367                         #size-cells = <0>;
 368                         interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
 369                         clock-frequency = <100000>;
 370                         status = "disabled";
 371                 };
 372
 373                 uart3: serial@66130000 {
 374                         compatible = "snps,dw-apb-uart";
 375                         reg = <0x66130000 0x100>;
 376                         interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
 377                         reg-shift = <2>;
 378                         reg-io-width = <4>;
 379                         clocks = <&osc>;
 380                         status = "disabled";
 381                 };
 382
 383                 ssp0: ssp@66180000 {
 384                         compatible = "arm,pl022", "arm,primecell";
 385                         reg = <0x66180000 0x1000>;
 386                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
 387                         clocks = <&iprocslow>, <&iprocslow>;
 388                         clock-names = "spiclk", "apb_pclk";
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         status = "disabled";
 392                 };
 393
 394                 ssp1: ssp@66190000 {
 395                         compatible = "arm,pl022", "arm,primecell";
 396                         reg = <0x66190000 0x1000>;
 397                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 398                         clocks = <&iprocslow>, <&iprocslow>;
 399                         clock-names = "spiclk", "apb_pclk";
 400                         #address-cells = <1>;
 401                         #size-cells = <0>;
 402                         status = "disabled";
 403                 };
 404
 405                 hwrng: hwrng@66220000 {
 406                         compatible = "brcm,iproc-rng200";
 407                         reg = <0x66220000 0x28>;
 408                 };
 409
 410                 sdio0: sdhci@66420000 {
 411                         compatible = "brcm,sdhci-iproc-cygnus";
 412                         reg = <0x66420000 0x100>;
 413                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
 414                         bus-width = <8>;
 415                         clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
 416                         status = "disabled";
 417                 };
 418
 419                 sdio1: sdhci@66430000 {
 420                         compatible = "brcm,sdhci-iproc-cygnus";
 421                         reg = <0x66430000 0x100>;
 422                         interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
 423                         bus-width = <8>;
 424                         clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
 425                         status = "disabled";
 426                 };
 427
 428                 nand: nand@66460000 {
 429                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 430                         reg = <0x66460000 0x600>,
 431                               <0x67015408 0x600>,
 432                               <0x66460f00 0x20>;
 433                         reg-names = "nand", "iproc-idm", "iproc-ext";
 434                         interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
 435
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438
 439                         brcm,nand-has-wp;
 440                 };
 441         };
 442 };