arch/arm/mach-s3c2440/mach-osiris.c

   1 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
   2  *
   3  * Copyright (c) 2005-2008 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/gpio.h>
  19 #include <linux/device.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/clk.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25
  26 #include <linux/i2c/tps65010.h>
  27
  28 #include <asm/mach/arch.h>
  29 #include <asm/mach/map.h>
  30 #include <asm/mach/irq.h>
  31
  32 #include <mach/osiris-map.h>
  33 #include <mach/osiris-cpld.h>
  34
  35 #include <mach/hardware.h>
  36 #include <asm/irq.h>
  37 #include <asm/mach-types.h>
  38
  39 #include <plat/cpu-freq.h>
  40 #include <plat/regs-serial.h>
  41 #include <mach/regs-gpio.h>
  42 #include <mach/regs-mem.h>
  43 #include <mach/regs-lcd.h>
  44 #include <plat/nand.h>
  45 #include <plat/iic.h>
  46
  47 #include <linux/mtd/mtd.h>
  48 #include <linux/mtd/nand.h>
  49 #include <linux/mtd/nand_ecc.h>
  50 #include <linux/mtd/partitions.h>
  51
  52 #include <plat/clock.h>
  53 #include <plat/devs.h>
  54 #include <plat/cpu.h>
  55
  56 /* onboard perihperal map */
  57
  58 static struct map_desc osiris_iodesc[] __initdata = {
  59   /* ISA IO areas (may be over-written later) */
  60
  61   {
  62           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  63           .pfn          = __phys_to_pfn(S3C2410_CS5),
  64           .length       = SZ_16M,
  65           .type         = MT_DEVICE,
  66   }, {
  67           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  68           .pfn          = __phys_to_pfn(S3C2410_CS5),
  69           .length       = SZ_16M,
  70           .type         = MT_DEVICE,
  71   },
  72
  73   /* CPLD control registers */
  74
  75   {
  76           .virtual      = (u32)OSIRIS_VA_CTRL0,
  77           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL0),
  78           .length       = SZ_16K,
  79           .type         = MT_DEVICE,
  80   }, {
  81           .virtual      = (u32)OSIRIS_VA_CTRL1,
  82           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL1),
  83           .length       = SZ_16K,
  84           .type         = MT_DEVICE,
  85   }, {
  86           .virtual      = (u32)OSIRIS_VA_CTRL2,
  87           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL2),
  88           .length       = SZ_16K,
  89           .type         = MT_DEVICE,
  90   }, {
  91           .virtual      = (u32)OSIRIS_VA_IDREG,
  92           .pfn          = __phys_to_pfn(OSIRIS_PA_IDREG),
  93           .length       = SZ_16K,
  94           .type         = MT_DEVICE,
  95   },
  96 };
  97
  98 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  99 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 100 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 101
 102 static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
 103         [0] = {
 104                 .name           = "uclk",
 105                 .divisor        = 1,
 106                 .min_baud       = 0,
 107                 .max_baud       = 0,
 108         },
 109         [1] = {
 110                 .name           = "pclk",
 111                 .divisor        = 1,
 112                 .min_baud       = 0,
 113                 .max_baud       = 0,
 114         }
 115 };
 116
 117 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
 118         [0] = {
 119                 .hwport      = 0,
 120                 .flags       = 0,
 121                 .ucon        = UCON,
 122                 .ulcon       = ULCON,
 123                 .ufcon       = UFCON,
 124                 .clocks      = osiris_serial_clocks,
 125                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 126         },
 127         [1] = {
 128                 .hwport      = 1,
 129                 .flags       = 0,
 130                 .ucon        = UCON,
 131                 .ulcon       = ULCON,
 132                 .ufcon       = UFCON,
 133                 .clocks      = osiris_serial_clocks,
 134                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 135         },
 136         [2] = {
 137                 .hwport      = 2,
 138                 .flags       = 0,
 139                 .ucon        = UCON,
 140                 .ulcon       = ULCON,
 141                 .ufcon       = UFCON,
 142                 .clocks      = osiris_serial_clocks,
 143                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 144         }
 145 };
 146
 147 /* NAND Flash on Osiris board */
 148
 149 static int external_map[]   = { 2 };
 150 static int chip0_map[]      = { 0 };
 151 static int chip1_map[]      = { 1 };
 152
 153 static struct mtd_partition __initdata osiris_default_nand_part[] = {
 154         [0] = {
 155                 .name   = "Boot Agent",
 156                 .size   = SZ_16K,
 157                 .offset = 0,
 158         },
 159         [1] = {
 160                 .name   = "/boot",
 161                 .size   = SZ_4M - SZ_16K,
 162                 .offset = SZ_16K,
 163         },
 164         [2] = {
 165                 .name   = "user1",
 166                 .offset = SZ_4M,
 167                 .size   = SZ_32M - SZ_4M,
 168         },
 169         [3] = {
 170                 .name   = "user2",
 171                 .offset = SZ_32M,
 172                 .size   = MTDPART_SIZ_FULL,
 173         }
 174 };
 175
 176 static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
 177         [0] = {
 178                 .name   = "Boot Agent",
 179                 .size   = SZ_128K,
 180                 .offset = 0,
 181         },
 182         [1] = {
 183                 .name   = "/boot",
 184                 .size   = SZ_4M - SZ_128K,
 185                 .offset = SZ_128K,
 186         },
 187         [2] = {
 188                 .name   = "user1",
 189                 .offset = SZ_4M,
 190                 .size   = SZ_32M - SZ_4M,
 191         },
 192         [3] = {
 193                 .name   = "user2",
 194                 .offset = SZ_32M,
 195                 .size   = MTDPART_SIZ_FULL,
 196         }
 197 };
 198
 199 /* the Osiris has 3 selectable slots for nand-flash, the two
 200  * on-board chip areas, as well as the external slot.
 201  *
 202  * Note, there is no current hot-plug support for the External
 203  * socket.
 204 */
 205
 206 static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
 207         [1] = {
 208                 .name           = "External",
 209                 .nr_chips       = 1,
 210                 .nr_map         = external_map,
 211                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 212                 .partitions     = osiris_default_nand_part,
 213         },
 214         [0] = {
 215                 .name           = "chip0",
 216                 .nr_chips       = 1,
 217                 .nr_map         = chip0_map,
 218                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 219                 .partitions     = osiris_default_nand_part,
 220         },
 221         [2] = {
 222                 .name           = "chip1",
 223                 .nr_chips       = 1,
 224                 .nr_map         = chip1_map,
 225                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 226                 .partitions     = osiris_default_nand_part,
 227         },
 228 };
 229
 230 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
 231 {
 232         unsigned int tmp;
 233
 234         slot = set->nr_map[slot] & 3;
 235
 236         pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
 237                  slot, set, set->nr_map);
 238
 239         tmp = __raw_readb(OSIRIS_VA_CTRL0);
 240         tmp &= ~OSIRIS_CTRL0_NANDSEL;
 241         tmp |= slot;
 242
 243         pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
 244
 245         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 246 }
 247
 248 static struct s3c2410_platform_nand __initdata osiris_nand_info = {
 249         .tacls          = 25,
 250         .twrph0         = 60,
 251         .twrph1         = 60,
 252         .nr_sets        = ARRAY_SIZE(osiris_nand_sets),
 253         .sets           = osiris_nand_sets,
 254         .select_chip    = osiris_nand_select,
 255 };
 256
 257 /* PCMCIA control and configuration */
 258
 259 static struct resource osiris_pcmcia_resource[] = {
 260         [0] = {
 261                 .start  = 0x0f000000,
 262                 .end    = 0x0f100000,
 263                 .flags  = IORESOURCE_MEM,
 264         },
 265         [1] = {
 266                 .start  = 0x0c000000,
 267                 .end    = 0x0c100000,
 268                 .flags  = IORESOURCE_MEM,
 269         }
 270 };
 271
 272 static struct platform_device osiris_pcmcia = {
 273         .name           = "osiris-pcmcia",
 274         .id             = -1,
 275         .num_resources  = ARRAY_SIZE(osiris_pcmcia_resource),
 276         .resource       = osiris_pcmcia_resource,
 277 };
 278
 279 /* Osiris power management device */
 280
 281 #ifdef CONFIG_PM
 282 static unsigned char pm_osiris_ctrl0;
 283
 284 static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
 285 {
 286         unsigned int tmp;
 287
 288         pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
 289         tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
 290
 291         /* ensure correct NAND slot is selected on resume */
 292         if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
 293                 tmp |= 2;
 294
 295         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 296
 297         /* ensure that an nRESET is not generated on resume. */
 298         s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
 299         s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
 300
 301         return 0;
 302 }
 303
 304 static int osiris_pm_resume(struct sys_device *sd)
 305 {
 306         if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
 307                 __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
 308
 309         __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
 310
 311         s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 312
 313         return 0;
 314 }
 315
 316 #else
 317 #define osiris_pm_suspend NULL
 318 #define osiris_pm_resume NULL
 319 #endif
 320
 321 static struct sysdev_class osiris_pm_sysclass = {
 322         .name           = "mach-osiris",
 323         .suspend        = osiris_pm_suspend,
 324         .resume         = osiris_pm_resume,
 325 };
 326
 327 static struct sys_device osiris_pm_sysdev = {
 328         .cls            = &osiris_pm_sysclass,
 329 };
 330
 331 /* Link for DVS driver to TPS65011 */
 332
 333 static void osiris_tps_release(struct device *dev)
 334 {
 335         /* static device, do not need to release anything */
 336 }
 337
 338 static struct platform_device osiris_tps_device = {
 339         .name   = "osiris-dvs",
 340         .id     = -1,
 341         .dev.release = osiris_tps_release,
 342 };
 343
 344 static int osiris_tps_setup(struct i2c_client *client, void *context)
 345 {
 346         osiris_tps_device.dev.parent = &client->dev;
 347         return platform_device_register(&osiris_tps_device);
 348 }
 349
 350 static int osiris_tps_remove(struct i2c_client *client, void *context)
 351 {
 352         platform_device_unregister(&osiris_tps_device);
 353         return 0;
 354 }
 355
 356 static struct tps65010_board osiris_tps_board = {
 357         .base           = -1,   /* GPIO can go anywhere at the moment */
 358         .setup          = osiris_tps_setup,
 359         .teardown       = osiris_tps_remove,
 360 };
 361
 362 /* I2C devices fitted. */
 363
 364 static struct i2c_board_info osiris_i2c_devs[] __initdata = {
 365         {
 366                 I2C_BOARD_INFO("tps65011", 0x48),
 367                 .irq    = IRQ_EINT20,
 368                 .platform_data = &osiris_tps_board,
 369         },
 370 };
 371
 372 /* Standard Osiris devices */
 373
 374 static struct platform_device *osiris_devices[] __initdata = {
 375         &s3c_device_i2c0,
 376         &s3c_device_wdt,
 377         &s3c_device_nand,
 378         &osiris_pcmcia,
 379 };
 380
 381 static struct clk *osiris_clocks[] __initdata = {
 382         &s3c24xx_dclk0,
 383         &s3c24xx_dclk1,
 384         &s3c24xx_clkout0,
 385         &s3c24xx_clkout1,
 386         &s3c24xx_uclk,
 387 };
 388
 389 static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
 390         .refresh        = 7800, /* refresh period is 7.8usec */
 391         .auto_io        = 1,
 392         .need_io        = 1,
 393 };
 394
 395 static void __init osiris_map_io(void)
 396 {
 397         unsigned long flags;
 398
 399         /* initialise the clocks */
 400
 401         s3c24xx_dclk0.parent = &clk_upll;
 402         s3c24xx_dclk0.rate   = 12*1000*1000;
 403
 404         s3c24xx_dclk1.parent = &clk_upll;
 405         s3c24xx_dclk1.rate   = 24*1000*1000;
 406
 407         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 408         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 409
 410         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 411
 412         s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
 413
 414         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
 415         s3c24xx_init_clocks(0);
 416         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
 417
 418         /* check for the newer revision boards with large page nand */
 419
 420         if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
 421                 printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
 422                        __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
 423                 osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
 424                 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
 425         } else {
 426                 /* write-protect line to the NAND */
 427                 s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
 428         }
 429
 430         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
 431
 432         local_irq_save(flags);
 433         __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
 434         local_irq_restore(flags);
 435 }
 436
 437 static void __init osiris_init(void)
 438 {
 439         sysdev_class_register(&osiris_pm_sysclass);
 440         sysdev_register(&osiris_pm_sysdev);
 441
 442         s3c_i2c0_set_platdata(NULL);
 443         s3c_nand_set_platdata(&osiris_nand_info);
 444
 445         s3c_cpufreq_setboard(&osiris_cpufreq);
 446
 447         i2c_register_board_info(0, osiris_i2c_devs,
 448                                 ARRAY_SIZE(osiris_i2c_devs));
 449
 450         platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
 451 };
 452
 453 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
 454         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 455         .phys_io        = S3C2410_PA_UART,
 456         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 457         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 458         .map_io         = osiris_map_io,
 459         .init_irq       = s3c24xx_init_irq,
 460         .init_machine   = osiris_init,
 461         .timer          = &s3c24xx_timer,
 462 MACHINE_END