arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49
  50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
  51 #include <dt-bindings/reset/sun6i-a31-ccu.h>
  52
  53 / {
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58         };
  59
  60         chosen {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 ranges;
  64
  65                 simplefb_hdmi: framebuffer@0 {
  66                         compatible = "allwinner,simple-framebuffer",
  67                                      "simple-framebuffer";
  68                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  69                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  70                                  <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
  71                                  <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
  72                                  <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
  73                         status = "disabled";
  74                 };
  75
  76                 simplefb_lcd: framebuffer@1 {
  77                         compatible = "allwinner,simple-framebuffer",
  78                                      "simple-framebuffer";
  79                         allwinner,pipeline = "de_be0-lcd0";
  80                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  81                                  <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
  82                                  <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
  83                         status = "disabled";
  84                 };
  85         };
  86
  87         timer {
  88                 compatible = "arm,armv7-timer";
  89                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  93                 clock-frequency = <24000000>;
  94                 arm,cpu-registers-not-fw-configured;
  95         };
  96
  97         cpus {
  98                 enable-method = "allwinner,sun6i-a31";
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101
 102                 cpu0: cpu@0 {
 103                         compatible = "arm,cortex-a7";
 104                         device_type = "cpu";
 105                         reg = <0>;
 106                         clocks = <&ccu CLK_CPU>;
 107                         clock-latency = <244144>; /* 8 32k periods */
 108                         operating-points = <
 109                                 /* kHz    uV */
 110                                 1008000 1200000
 111                                 864000  1200000
 112                                 720000  1100000
 113                                 480000  1000000
 114                                 >;
 115                         #cooling-cells = <2>;
 116                 };
 117
 118                 cpu1: cpu@1 {
 119                         compatible = "arm,cortex-a7";
 120                         device_type = "cpu";
 121                         reg = <1>;
 122                         clocks = <&ccu CLK_CPU>;
 123                         clock-latency = <244144>; /* 8 32k periods */
 124                         operating-points = <
 125                                 /* kHz    uV */
 126                                 1008000 1200000
 127                                 864000  1200000
 128                                 720000  1100000
 129                                 480000  1000000
 130                                 >;
 131                         #cooling-cells = <2>;
 132                 };
 133
 134                 cpu2: cpu@2 {
 135                         compatible = "arm,cortex-a7";
 136                         device_type = "cpu";
 137                         reg = <2>;
 138                         clocks = <&ccu CLK_CPU>;
 139                         clock-latency = <244144>; /* 8 32k periods */
 140                         operating-points = <
 141                                 /* kHz    uV */
 142                                 1008000 1200000
 143                                 864000  1200000
 144                                 720000  1100000
 145                                 480000  1000000
 146                                 >;
 147                         #cooling-cells = <2>;
 148                 };
 149
 150                 cpu3: cpu@3 {
 151                         compatible = "arm,cortex-a7";
 152                         device_type = "cpu";
 153                         reg = <3>;
 154                         clocks = <&ccu CLK_CPU>;
 155                         clock-latency = <244144>; /* 8 32k periods */
 156                         operating-points = <
 157                                 /* kHz    uV */
 158                                 1008000 1200000
 159                                 864000  1200000
 160                                 720000  1100000
 161                                 480000  1000000
 162                                 >;
 163                         #cooling-cells = <2>;
 164                 };
 165         };
 166
 167         thermal-zones {
 168                 cpu_thermal {
 169                         /* milliseconds */
 170                         polling-delay-passive = <250>;
 171                         polling-delay = <1000>;
 172                         thermal-sensors = <&rtp>;
 173
 174                         cooling-maps {
 175                                 map0 {
 176                                         trip = <&cpu_alert0>;
 177                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 178                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 179                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 180                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 181                                 };
 182                         };
 183
 184                         trips {
 185                                 cpu_alert0: cpu_alert0 {
 186                                         /* milliCelsius */
 187                                         temperature = <70000>;
 188                                         hysteresis = <2000>;
 189                                         type = "passive";
 190                                 };
 191
 192                                 cpu_crit: cpu_crit {
 193                                         /* milliCelsius */
 194                                         temperature = <100000>;
 195                                         hysteresis = <2000>;
 196                                         type = "critical";
 197                                 };
 198                         };
 199                 };
 200         };
 201
 202         memory {
 203                 reg = <0x40000000 0x80000000>;
 204         };
 205
 206         pmu {
 207                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 208                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 209                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 212         };
 213
 214         clocks {
 215                 #address-cells = <1>;
 216                 #size-cells = <1>;
 217                 ranges;
 218
 219                 osc24M: osc24M {
 220                         #clock-cells = <0>;
 221                         compatible = "fixed-clock";
 222                         clock-frequency = <24000000>;
 223                 };
 224
 225                 osc32k: clk@0 {
 226                         #clock-cells = <0>;
 227                         compatible = "fixed-clock";
 228                         clock-frequency = <32768>;
 229                         clock-output-names = "osc32k";
 230                 };
 231
 232                 /*
 233                  * The following two are dummy clocks, placeholders
 234                  * used in the gmac_tx clock. The gmac driver will
 235                  * choose one parent depending on the PHY interface
 236                  * mode, using clk_set_rate auto-reparenting.
 237                  *
 238                  * The actual TX clock rate is not controlled by the
 239                  * gmac_tx clock.
 240                  */
 241                 mii_phy_tx_clk: clk@1 {
 242                         #clock-cells = <0>;
 243                         compatible = "fixed-clock";
 244                         clock-frequency = <25000000>;
 245                         clock-output-names = "mii_phy_tx";
 246                 };
 247
 248                 gmac_int_tx_clk: clk@2 {
 249                         #clock-cells = <0>;
 250                         compatible = "fixed-clock";
 251                         clock-frequency = <125000000>;
 252                         clock-output-names = "gmac_int_tx";
 253                 };
 254
 255                 gmac_tx_clk: clk@1c200d0 {
 256                         #clock-cells = <0>;
 257                         compatible = "allwinner,sun7i-a20-gmac-clk";
 258                         reg = <0x01c200d0 0x4>;
 259                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 260                         clock-output-names = "gmac_tx";
 261                 };
 262         };
 263
 264         de: display-engine {
 265                 compatible = "allwinner,sun6i-a31-display-engine";
 266                 allwinner,pipelines = <&fe0>, <&fe1>;
 267                 status = "disabled";
 268         };
 269
 270         soc@1c00000 {
 271                 compatible = "simple-bus";
 272                 #address-cells = <1>;
 273                 #size-cells = <1>;
 274                 ranges;
 275
 276                 dma: dma-controller@1c02000 {
 277                         compatible = "allwinner,sun6i-a31-dma";
 278                         reg = <0x01c02000 0x1000>;
 279                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 280                         clocks = <&ccu CLK_AHB1_DMA>;
 281                         resets = <&ccu RST_AHB1_DMA>;
 282                         #dma-cells = <1>;
 283                 };
 284
 285                 tcon0: lcd-controller@1c0c000 {
 286                         compatible = "allwinner,sun6i-a31-tcon";
 287                         reg = <0x01c0c000 0x1000>;
 288                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 289                         resets = <&ccu RST_AHB1_LCD0>;
 290                         reset-names = "lcd";
 291                         clocks = <&ccu CLK_AHB1_LCD0>,
 292                                  <&ccu CLK_LCD0_CH0>,
 293                                  <&ccu CLK_LCD0_CH1>;
 294                         clock-names = "ahb",
 295                                       "tcon-ch0",
 296                                       "tcon-ch1";
 297                         clock-output-names = "tcon0-pixel-clock";
 298
 299                         ports {
 300                                 #address-cells = <1>;
 301                                 #size-cells = <0>;
 302
 303                                 tcon0_in: port@0 {
 304                                         #address-cells = <1>;
 305                                         #size-cells = <0>;
 306                                         reg = <0>;
 307
 308                                         tcon0_in_drc0: endpoint@0 {
 309                                                 reg = <0>;
 310                                                 remote-endpoint = <&drc0_out_tcon0>;
 311                                         };
 312
 313                                         tcon0_in_drc1: endpoint@1 {
 314                                                 reg = <1>;
 315                                                 remote-endpoint = <&drc1_out_tcon0>;
 316                                         };
 317                                 };
 318
 319                                 tcon0_out: port@1 {
 320                                         #address-cells = <1>;
 321                                         #size-cells = <0>;
 322                                         reg = <1>;
 323
 324                                         tcon0_out_hdmi: endpoint@1 {
 325                                                 reg = <1>;
 326                                                 remote-endpoint = <&hdmi_in_tcon0>;
 327                                                 allwinner,tcon-channel = <1>;
 328                                         };
 329                                 };
 330                         };
 331                 };
 332
 333                 tcon1: lcd-controller@1c0d000 {
 334                         compatible = "allwinner,sun6i-a31-tcon";
 335                         reg = <0x01c0d000 0x1000>;
 336                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 337                         resets = <&ccu RST_AHB1_LCD1>;
 338                         reset-names = "lcd";
 339                         clocks = <&ccu CLK_AHB1_LCD1>,
 340                                  <&ccu CLK_LCD1_CH0>,
 341                                  <&ccu CLK_LCD1_CH1>;
 342                         clock-names = "ahb",
 343                                       "tcon-ch0",
 344                                       "tcon-ch1";
 345                         clock-output-names = "tcon1-pixel-clock";
 346
 347                         ports {
 348                                 #address-cells = <1>;
 349                                 #size-cells = <0>;
 350
 351                                 tcon1_in: port@0 {
 352                                         #address-cells = <1>;
 353                                         #size-cells = <0>;
 354                                         reg = <0>;
 355
 356                                         tcon1_in_drc0: endpoint@0 {
 357                                                 reg = <0>;
 358                                                 remote-endpoint = <&drc0_out_tcon1>;
 359                                         };
 360
 361                                         tcon1_in_drc1: endpoint@1 {
 362                                                 reg = <1>;
 363                                                 remote-endpoint = <&drc1_out_tcon1>;
 364                                         };
 365                                 };
 366
 367                                 tcon1_out: port@1 {
 368                                         #address-cells = <1>;
 369                                         #size-cells = <0>;
 370                                         reg = <1>;
 371
 372                                         tcon1_out_hdmi: endpoint@1 {
 373                                                 reg = <1>;
 374                                                 remote-endpoint = <&hdmi_in_tcon1>;
 375                                                 allwinner,tcon-channel = <1>;
 376                                         };
 377                                 };
 378                         };
 379                 };
 380
 381                 mmc0: mmc@1c0f000 {
 382                         compatible = "allwinner,sun7i-a20-mmc";
 383                         reg = <0x01c0f000 0x1000>;
 384                         clocks = <&ccu CLK_AHB1_MMC0>,
 385                                  <&ccu CLK_MMC0>,
 386                                  <&ccu CLK_MMC0_OUTPUT>,
 387                                  <&ccu CLK_MMC0_SAMPLE>;
 388                         clock-names = "ahb",
 389                                       "mmc",
 390                                       "output",
 391                                       "sample";
 392                         resets = <&ccu RST_AHB1_MMC0>;
 393                         reset-names = "ahb";
 394                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 395                         status = "disabled";
 396                         #address-cells = <1>;
 397                         #size-cells = <0>;
 398                 };
 399
 400                 mmc1: mmc@1c10000 {
 401                         compatible = "allwinner,sun7i-a20-mmc";
 402                         reg = <0x01c10000 0x1000>;
 403                         clocks = <&ccu CLK_AHB1_MMC1>,
 404                                  <&ccu CLK_MMC1>,
 405                                  <&ccu CLK_MMC1_OUTPUT>,
 406                                  <&ccu CLK_MMC1_SAMPLE>;
 407                         clock-names = "ahb",
 408                                       "mmc",
 409                                       "output",
 410                                       "sample";
 411                         resets = <&ccu RST_AHB1_MMC1>;
 412                         reset-names = "ahb";
 413                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 414                         status = "disabled";
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                 };
 418
 419                 mmc2: mmc@1c11000 {
 420                         compatible = "allwinner,sun7i-a20-mmc";
 421                         reg = <0x01c11000 0x1000>;
 422                         clocks = <&ccu CLK_AHB1_MMC2>,
 423                                  <&ccu CLK_MMC2>,
 424                                  <&ccu CLK_MMC2_OUTPUT>,
 425                                  <&ccu CLK_MMC2_SAMPLE>;
 426                         clock-names = "ahb",
 427                                       "mmc",
 428                                       "output",
 429                                       "sample";
 430                         resets = <&ccu RST_AHB1_MMC2>;
 431                         reset-names = "ahb";
 432                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 433                         status = "disabled";
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                 };
 437
 438                 mmc3: mmc@1c12000 {
 439                         compatible = "allwinner,sun7i-a20-mmc";
 440                         reg = <0x01c12000 0x1000>;
 441                         clocks = <&ccu CLK_AHB1_MMC3>,
 442                                  <&ccu CLK_MMC3>,
 443                                  <&ccu CLK_MMC3_OUTPUT>,
 444                                  <&ccu CLK_MMC3_SAMPLE>;
 445                         clock-names = "ahb",
 446                                       "mmc",
 447                                       "output",
 448                                       "sample";
 449                         resets = <&ccu RST_AHB1_MMC3>;
 450                         reset-names = "ahb";
 451                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 452                         status = "disabled";
 453                         #address-cells = <1>;
 454                         #size-cells = <0>;
 455                 };
 456
 457                 hdmi: hdmi@1c16000 {
 458                         compatible = "allwinner,sun6i-a31-hdmi";
 459                         reg = <0x01c16000 0x1000>;
 460                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 461                         clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
 462                                  <&ccu CLK_HDMI_DDC>,
 463                                  <&ccu CLK_PLL_VIDEO0_2X>,
 464                                  <&ccu CLK_PLL_VIDEO1_2X>;
 465                         clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
 466                         resets = <&ccu RST_AHB1_HDMI>;
 467                         reset-names = "ahb";
 468                         dma-names = "ddc-tx", "ddc-rx", "audio-tx";
 469                         dmas = <&dma 13>, <&dma 13>, <&dma 14>;
 470                         status = "disabled";
 471
 472                         ports {
 473                                 #address-cells = <1>;
 474                                 #size-cells = <0>;
 475
 476                                 hdmi_in: port@0 {
 477                                         #address-cells = <1>;
 478                                         #size-cells = <0>;
 479                                         reg = <0>;
 480
 481                                         hdmi_in_tcon0: endpoint@0 {
 482                                                 reg = <0>;
 483                                                 remote-endpoint = <&tcon0_out_hdmi>;
 484                                         };
 485
 486                                         hdmi_in_tcon1: endpoint@1 {
 487                                                 reg = <1>;
 488                                                 remote-endpoint = <&tcon1_out_hdmi>;
 489                                         };
 490                                 };
 491
 492                                 hdmi_out: port@1 {
 493                                         #address-cells = <1>;
 494                                         #size-cells = <0>;
 495                                         reg = <1>;
 496                                 };
 497                         };
 498                 };
 499
 500                 usb_otg: usb@1c19000 {
 501                         compatible = "allwinner,sun6i-a31-musb";
 502                         reg = <0x01c19000 0x0400>;
 503                         clocks = <&ccu CLK_AHB1_OTG>;
 504                         resets = <&ccu RST_AHB1_OTG>;
 505                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 506                         interrupt-names = "mc";
 507                         phys = <&usbphy 0>;
 508                         phy-names = "usb";
 509                         extcon = <&usbphy 0>;
 510                         status = "disabled";
 511                 };
 512
 513                 usbphy: phy@1c19400 {
 514                         compatible = "allwinner,sun6i-a31-usb-phy";
 515                         reg = <0x01c19400 0x10>,
 516                               <0x01c1a800 0x4>,
 517                               <0x01c1b800 0x4>;
 518                         reg-names = "phy_ctrl",
 519                                     "pmu1",
 520                                     "pmu2";
 521                         clocks = <&ccu CLK_USB_PHY0>,
 522                                  <&ccu CLK_USB_PHY1>,
 523                                  <&ccu CLK_USB_PHY2>;
 524                         clock-names = "usb0_phy",
 525                                       "usb1_phy",
 526                                       "usb2_phy";
 527                         resets = <&ccu RST_USB_PHY0>,
 528                                  <&ccu RST_USB_PHY1>,
 529                                  <&ccu RST_USB_PHY2>;
 530                         reset-names = "usb0_reset",
 531                                       "usb1_reset",
 532                                       "usb2_reset";
 533                         status = "disabled";
 534                         #phy-cells = <1>;
 535                 };
 536
 537                 ehci0: usb@1c1a000 {
 538                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 539                         reg = <0x01c1a000 0x100>;
 540                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 541                         clocks = <&ccu CLK_AHB1_EHCI0>;
 542                         resets = <&ccu RST_AHB1_EHCI0>;
 543                         phys = <&usbphy 1>;
 544                         phy-names = "usb";
 545                         status = "disabled";
 546                 };
 547
 548                 ohci0: usb@1c1a400 {
 549                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 550                         reg = <0x01c1a400 0x100>;
 551                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 552                         clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
 553                         resets = <&ccu RST_AHB1_OHCI0>;
 554                         phys = <&usbphy 1>;
 555                         phy-names = "usb";
 556                         status = "disabled";
 557                 };
 558
 559                 ehci1: usb@1c1b000 {
 560                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 561                         reg = <0x01c1b000 0x100>;
 562                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 563                         clocks = <&ccu CLK_AHB1_EHCI1>;
 564                         resets = <&ccu RST_AHB1_EHCI1>;
 565                         phys = <&usbphy 2>;
 566                         phy-names = "usb";
 567                         status = "disabled";
 568                 };
 569
 570                 ohci1: usb@1c1b400 {
 571                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 572                         reg = <0x01c1b400 0x100>;
 573                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 574                         clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
 575                         resets = <&ccu RST_AHB1_OHCI1>;
 576                         phys = <&usbphy 2>;
 577                         phy-names = "usb";
 578                         status = "disabled";
 579                 };
 580
 581                 ohci2: usb@1c1c400 {
 582                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 583                         reg = <0x01c1c400 0x100>;
 584                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 585                         clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
 586                         resets = <&ccu RST_AHB1_OHCI2>;
 587                         status = "disabled";
 588                 };
 589
 590                 ccu: clock@1c20000 {
 591                         compatible = "allwinner,sun6i-a31-ccu";
 592                         reg = <0x01c20000 0x400>;
 593                         clocks = <&osc24M>, <&osc32k>;
 594                         clock-names = "hosc", "losc";
 595                         #clock-cells = <1>;
 596                         #reset-cells = <1>;
 597                 };
 598
 599                 pio: pinctrl@1c20800 {
 600                         compatible = "allwinner,sun6i-a31-pinctrl";
 601                         reg = <0x01c20800 0x400>;
 602                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 603                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 604                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 605                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 606                         clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
 607                         clock-names = "apb", "hosc", "losc";
 608                         gpio-controller;
 609                         interrupt-controller;
 610                         #interrupt-cells = <3>;
 611                         #gpio-cells = <3>;
 612
 613                         gmac_pins_gmii_a: gmac_gmii@0 {
 614                                 pins = "PA0", "PA1", "PA2", "PA3",
 615                                                 "PA4", "PA5", "PA6", "PA7",
 616                                                 "PA8", "PA9", "PA10", "PA11",
 617                                                 "PA12", "PA13", "PA14", "PA15",
 618                                                 "PA16", "PA17", "PA18", "PA19",
 619                                                 "PA20", "PA21", "PA22", "PA23",
 620                                                 "PA24", "PA25", "PA26", "PA27";
 621                                 function = "gmac";
 622                                 /*
 623                                  * data lines in GMII mode run at 125MHz and
 624                                  * might need a higher signal drive strength
 625                                  */
 626                                 drive-strength = <30>;
 627                         };
 628
 629                         gmac_pins_mii_a: gmac_mii@0 {
 630                                 pins = "PA0", "PA1", "PA2", "PA3",
 631                                                 "PA8", "PA9", "PA11",
 632                                                 "PA12", "PA13", "PA14", "PA19",
 633                                                 "PA20", "PA21", "PA22", "PA23",
 634                                                 "PA24", "PA26", "PA27";
 635                                 function = "gmac";
 636                         };
 637
 638                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 639                                 pins = "PA0", "PA1", "PA2", "PA3",
 640                                                 "PA9", "PA10", "PA11",
 641                                                 "PA12", "PA13", "PA14", "PA19",
 642                                                 "PA20", "PA25", "PA26", "PA27";
 643                                 function = "gmac";
 644                                 /*
 645                                  * data lines in RGMII mode use DDR mode
 646                                  * and need a higher signal drive strength
 647                                  */
 648                                 drive-strength = <40>;
 649                         };
 650
 651                         i2c0_pins_a: i2c0@0 {
 652                                 pins = "PH14", "PH15";
 653                                 function = "i2c0";
 654                         };
 655
 656                         i2c1_pins_a: i2c1@0 {
 657                                 pins = "PH16", "PH17";
 658                                 function = "i2c1";
 659                         };
 660
 661                         i2c2_pins_a: i2c2@0 {
 662                                 pins = "PH18", "PH19";
 663                                 function = "i2c2";
 664                         };
 665
 666                         lcd0_rgb888_pins: lcd0_rgb888 {
 667                                 pins = "PD0", "PD1", "PD2", "PD3",
 668                                                  "PD4", "PD5", "PD6", "PD7",
 669                                                  "PD8", "PD9", "PD10", "PD11",
 670                                                  "PD12", "PD13", "PD14", "PD15",
 671                                                  "PD16", "PD17", "PD18", "PD19",
 672                                                  "PD20", "PD21", "PD22", "PD23",
 673                                                  "PD24", "PD25", "PD26", "PD27";
 674                                 function = "lcd0";
 675                         };
 676
 677                         mmc0_pins_a: mmc0@0 {
 678                                 pins = "PF0", "PF1", "PF2",
 679                                                  "PF3", "PF4", "PF5";
 680                                 function = "mmc0";
 681                                 drive-strength = <30>;
 682                                 bias-pull-up;
 683                         };
 684
 685                         mmc1_pins_a: mmc1@0 {
 686                                 pins = "PG0", "PG1", "PG2", "PG3",
 687                                                  "PG4", "PG5";
 688                                 function = "mmc1";
 689                                 drive-strength = <30>;
 690                                 bias-pull-up;
 691                         };
 692
 693                         mmc2_pins_a: mmc2@0 {
 694                                 pins = "PC6", "PC7", "PC8", "PC9",
 695                                                  "PC10", "PC11";
 696                                 function = "mmc2";
 697                                 drive-strength = <30>;
 698                                 bias-pull-up;
 699                         };
 700
 701                         mmc2_8bit_emmc_pins: mmc2@1 {
 702                                 pins = "PC6", "PC7", "PC8", "PC9",
 703                                                  "PC10", "PC11", "PC12",
 704                                                  "PC13", "PC14", "PC15",
 705                                                  "PC24";
 706                                 function = "mmc2";
 707                                 drive-strength = <30>;
 708                                 bias-pull-up;
 709                         };
 710
 711                         mmc3_8bit_emmc_pins: mmc3@1 {
 712                                 pins = "PC6", "PC7", "PC8", "PC9",
 713                                                  "PC10", "PC11", "PC12",
 714                                                  "PC13", "PC14", "PC15",
 715                                                  "PC24";
 716                                 function = "mmc3";
 717                                 drive-strength = <40>;
 718                                 bias-pull-up;
 719                         };
 720
 721                         spdif_pins_a: spdif@0 {
 722                                 pins = "PH28";
 723                                 function = "spdif";
 724                         };
 725
 726                         uart0_pins_a: uart0@0 {
 727                                 pins = "PH20", "PH21";
 728                                 function = "uart0";
 729                         };
 730                 };
 731
 732                 timer@1c20c00 {
 733                         compatible = "allwinner,sun4i-a10-timer";
 734                         reg = <0x01c20c00 0xa0>;
 735                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 736                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 737                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 738                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 739                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 740                         clocks = <&osc24M>;
 741                 };
 742
 743                 wdt1: watchdog@1c20ca0 {
 744                         compatible = "allwinner,sun6i-a31-wdt";
 745                         reg = <0x01c20ca0 0x20>;
 746                 };
 747
 748                 spdif: spdif@1c21000 {
 749                         #sound-dai-cells = <0>;
 750                         compatible = "allwinner,sun6i-a31-spdif";
 751                         reg = <0x01c21000 0x400>;
 752                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 753                         clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
 754                         resets = <&ccu RST_APB1_SPDIF>;
 755                         clock-names = "apb", "spdif";
 756                         dmas = <&dma 2>, <&dma 2>;
 757                         dma-names = "rx", "tx";
 758                         status = "disabled";
 759                 };
 760
 761                 i2s0: i2s@1c22000 {
 762                         #sound-dai-cells = <0>;
 763                         compatible = "allwinner,sun6i-a31-i2s";
 764                         reg = <0x01c22000 0x400>;
 765                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 766                         clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
 767                         resets = <&ccu RST_APB1_DAUDIO0>;
 768                         clock-names = "apb", "mod";
 769                         dmas = <&dma 3>, <&dma 3>;
 770                         dma-names = "rx", "tx";
 771                         status = "disabled";
 772                 };
 773
 774                 i2s1: i2s@1c22400 {
 775                         #sound-dai-cells = <0>;
 776                         compatible = "allwinner,sun6i-a31-i2s";
 777                         reg = <0x01c22400 0x400>;
 778                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 779                         clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
 780                         resets = <&ccu RST_APB1_DAUDIO1>;
 781                         clock-names = "apb", "mod";
 782                         dmas = <&dma 4>, <&dma 4>;
 783                         dma-names = "rx", "tx";
 784                         status = "disabled";
 785                 };
 786
 787                 lradc: lradc@1c22800 {
 788                         compatible = "allwinner,sun4i-a10-lradc-keys";
 789                         reg = <0x01c22800 0x100>;
 790                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 791                         status = "disabled";
 792                 };
 793
 794                 rtp: rtp@1c25000 {
 795                         compatible = "allwinner,sun6i-a31-ts";
 796                         reg = <0x01c25000 0x100>;
 797                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 798                         #thermal-sensor-cells = <0>;
 799                 };
 800
 801                 uart0: serial@1c28000 {
 802                         compatible = "snps,dw-apb-uart";
 803                         reg = <0x01c28000 0x400>;
 804                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 805                         reg-shift = <2>;
 806                         reg-io-width = <4>;
 807                         clocks = <&ccu CLK_APB2_UART0>;
 808                         resets = <&ccu RST_APB2_UART0>;
 809                         dmas = <&dma 6>, <&dma 6>;
 810                         dma-names = "rx", "tx";
 811                         status = "disabled";
 812                 };
 813
 814                 uart1: serial@1c28400 {
 815                         compatible = "snps,dw-apb-uart";
 816                         reg = <0x01c28400 0x400>;
 817                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 818                         reg-shift = <2>;
 819                         reg-io-width = <4>;
 820                         clocks = <&ccu CLK_APB2_UART1>;
 821                         resets = <&ccu RST_APB2_UART1>;
 822                         dmas = <&dma 7>, <&dma 7>;
 823                         dma-names = "rx", "tx";
 824                         status = "disabled";
 825                 };
 826
 827                 uart2: serial@1c28800 {
 828                         compatible = "snps,dw-apb-uart";
 829                         reg = <0x01c28800 0x400>;
 830                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 831                         reg-shift = <2>;
 832                         reg-io-width = <4>;
 833                         clocks = <&ccu CLK_APB2_UART2>;
 834                         resets = <&ccu RST_APB2_UART2>;
 835                         dmas = <&dma 8>, <&dma 8>;
 836                         dma-names = "rx", "tx";
 837                         status = "disabled";
 838                 };
 839
 840                 uart3: serial@1c28c00 {
 841                         compatible = "snps,dw-apb-uart";
 842                         reg = <0x01c28c00 0x400>;
 843                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 844                         reg-shift = <2>;
 845                         reg-io-width = <4>;
 846                         clocks = <&ccu CLK_APB2_UART3>;
 847                         resets = <&ccu RST_APB2_UART3>;
 848                         dmas = <&dma 9>, <&dma 9>;
 849                         dma-names = "rx", "tx";
 850                         status = "disabled";
 851                 };
 852
 853                 uart4: serial@1c29000 {
 854                         compatible = "snps,dw-apb-uart";
 855                         reg = <0x01c29000 0x400>;
 856                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 857                         reg-shift = <2>;
 858                         reg-io-width = <4>;
 859                         clocks = <&ccu CLK_APB2_UART4>;
 860                         resets = <&ccu RST_APB2_UART4>;
 861                         dmas = <&dma 10>, <&dma 10>;
 862                         dma-names = "rx", "tx";
 863                         status = "disabled";
 864                 };
 865
 866                 uart5: serial@1c29400 {
 867                         compatible = "snps,dw-apb-uart";
 868                         reg = <0x01c29400 0x400>;
 869                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 870                         reg-shift = <2>;
 871                         reg-io-width = <4>;
 872                         clocks = <&ccu CLK_APB2_UART5>;
 873                         resets = <&ccu RST_APB2_UART5>;
 874                         dmas = <&dma 22>, <&dma 22>;
 875                         dma-names = "rx", "tx";
 876                         status = "disabled";
 877                 };
 878
 879                 i2c0: i2c@1c2ac00 {
 880                         compatible = "allwinner,sun6i-a31-i2c";
 881                         reg = <0x01c2ac00 0x400>;
 882                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 883                         clocks = <&ccu CLK_APB2_I2C0>;
 884                         resets = <&ccu RST_APB2_I2C0>;
 885                         status = "disabled";
 886                         #address-cells = <1>;
 887                         #size-cells = <0>;
 888                 };
 889
 890                 i2c1: i2c@1c2b000 {
 891                         compatible = "allwinner,sun6i-a31-i2c";
 892                         reg = <0x01c2b000 0x400>;
 893                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 894                         clocks = <&ccu CLK_APB2_I2C1>;
 895                         resets = <&ccu RST_APB2_I2C1>;
 896                         status = "disabled";
 897                         #address-cells = <1>;
 898                         #size-cells = <0>;
 899                 };
 900
 901                 i2c2: i2c@1c2b400 {
 902                         compatible = "allwinner,sun6i-a31-i2c";
 903                         reg = <0x01c2b400 0x400>;
 904                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 905                         clocks = <&ccu CLK_APB2_I2C2>;
 906                         resets = <&ccu RST_APB2_I2C2>;
 907                         status = "disabled";
 908                         #address-cells = <1>;
 909                         #size-cells = <0>;
 910                 };
 911
 912                 i2c3: i2c@1c2b800 {
 913                         compatible = "allwinner,sun6i-a31-i2c";
 914                         reg = <0x01c2b800 0x400>;
 915                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 916                         clocks = <&ccu CLK_APB2_I2C3>;
 917                         resets = <&ccu RST_APB2_I2C3>;
 918                         status = "disabled";
 919                         #address-cells = <1>;
 920                         #size-cells = <0>;
 921                 };
 922
 923                 gmac: ethernet@1c30000 {
 924                         compatible = "allwinner,sun7i-a20-gmac";
 925                         reg = <0x01c30000 0x1054>;
 926                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 927                         interrupt-names = "macirq";
 928                         clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
 929                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 930                         resets = <&ccu RST_AHB1_EMAC>;
 931                         reset-names = "stmmaceth";
 932                         snps,pbl = <2>;
 933                         snps,fixed-burst;
 934                         snps,force_sf_dma_mode;
 935                         status = "disabled";
 936                         #address-cells = <1>;
 937                         #size-cells = <0>;
 938                 };
 939
 940                 crypto: crypto-engine@1c15000 {
 941                         compatible = "allwinner,sun6i-a31-crypto",
 942                                      "allwinner,sun4i-a10-crypto";
 943                         reg = <0x01c15000 0x1000>;
 944                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 945                         clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
 946                         clock-names = "ahb", "mod";
 947                         resets = <&ccu RST_AHB1_SS>;
 948                         reset-names = "ahb";
 949                 };
 950
 951                 codec: codec@1c22c00 {
 952                         #sound-dai-cells = <0>;
 953                         compatible = "allwinner,sun6i-a31-codec";
 954                         reg = <0x01c22c00 0x400>;
 955                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 956                         clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
 957                         clock-names = "apb", "codec";
 958                         resets = <&ccu RST_APB1_CODEC>;
 959                         dmas = <&dma 15>, <&dma 15>;
 960                         dma-names = "rx", "tx";
 961                         status = "disabled";
 962                 };
 963
 964                 timer@1c60000 {
 965                         compatible = "allwinner,sun6i-a31-hstimer",
 966                                      "allwinner,sun7i-a20-hstimer";
 967                         reg = <0x01c60000 0x1000>;
 968                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 969                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 970                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 971                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 972                         clocks = <&ccu CLK_AHB1_HSTIMER>;
 973                         resets = <&ccu RST_AHB1_HSTIMER>;
 974                 };
 975
 976                 spi0: spi@1c68000 {
 977                         compatible = "allwinner,sun6i-a31-spi";
 978                         reg = <0x01c68000 0x1000>;
 979                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 980                         clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
 981                         clock-names = "ahb", "mod";
 982                         dmas = <&dma 23>, <&dma 23>;
 983                         dma-names = "rx", "tx";
 984                         resets = <&ccu RST_AHB1_SPI0>;
 985                         status = "disabled";
 986                 };
 987
 988                 spi1: spi@1c69000 {
 989                         compatible = "allwinner,sun6i-a31-spi";
 990                         reg = <0x01c69000 0x1000>;
 991                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 992                         clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
 993                         clock-names = "ahb", "mod";
 994                         dmas = <&dma 24>, <&dma 24>;
 995                         dma-names = "rx", "tx";
 996                         resets = <&ccu RST_AHB1_SPI1>;
 997                         status = "disabled";
 998                 };
 999
1000                 spi2: spi@1c6a000 {
1001                         compatible = "allwinner,sun6i-a31-spi";
1002                         reg = <0x01c6a000 0x1000>;
1003                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1004                         clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1005                         clock-names = "ahb", "mod";
1006                         dmas = <&dma 25>, <&dma 25>;
1007                         dma-names = "rx", "tx";
1008                         resets = <&ccu RST_AHB1_SPI2>;
1009                         status = "disabled";
1010                 };
1011
1012                 spi3: spi@1c6b000 {
1013                         compatible = "allwinner,sun6i-a31-spi";
1014                         reg = <0x01c6b000 0x1000>;
1015                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1016                         clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1017                         clock-names = "ahb", "mod";
1018                         dmas = <&dma 26>, <&dma 26>;
1019                         dma-names = "rx", "tx";
1020                         resets = <&ccu RST_AHB1_SPI3>;
1021                         status = "disabled";
1022                 };
1023
1024                 gic: interrupt-controller@1c81000 {
1025                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1026                         reg = <0x01c81000 0x1000>,
1027                               <0x01c82000 0x2000>,
1028                               <0x01c84000 0x2000>,
1029                               <0x01c86000 0x2000>;
1030                         interrupt-controller;
1031                         #interrupt-cells = <3>;
1032                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1033                 };
1034
1035                 fe0: display-frontend@1e00000 {
1036                         compatible = "allwinner,sun6i-a31-display-frontend";
1037                         reg = <0x01e00000 0x20000>;
1038                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1039                         clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1040                                  <&ccu CLK_DRAM_FE0>;
1041                         clock-names = "ahb", "mod",
1042                                       "ram";
1043                         resets = <&ccu RST_AHB1_FE0>;
1044
1045                         ports {
1046                                 #address-cells = <1>;
1047                                 #size-cells = <0>;
1048
1049                                 fe0_out: port@1 {
1050                                         #address-cells = <1>;
1051                                         #size-cells = <0>;
1052                                         reg = <1>;
1053
1054                                         fe0_out_be0: endpoint@0 {
1055                                                 reg = <0>;
1056                                                 remote-endpoint = <&be0_in_fe0>;
1057                                         };
1058
1059                                         fe0_out_be1: endpoint@1 {
1060                                                 reg = <1>;
1061                                                 remote-endpoint = <&be1_in_fe0>;
1062                                         };
1063                                 };
1064                         };
1065                 };
1066
1067                 fe1: display-frontend@1e20000 {
1068                         compatible = "allwinner,sun6i-a31-display-frontend";
1069                         reg = <0x01e20000 0x20000>;
1070                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1071                         clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1072                                  <&ccu CLK_DRAM_FE1>;
1073                         clock-names = "ahb", "mod",
1074                                       "ram";
1075                         resets = <&ccu RST_AHB1_FE1>;
1076
1077                         ports {
1078                                 #address-cells = <1>;
1079                                 #size-cells = <0>;
1080
1081                                 fe1_out: port@1 {
1082                                         #address-cells = <1>;
1083                                         #size-cells = <0>;
1084                                         reg = <1>;
1085
1086                                         fe1_out_be0: endpoint@0 {
1087                                                 reg = <0>;
1088                                                 remote-endpoint = <&be0_in_fe1>;
1089                                         };
1090
1091                                         fe1_out_be1: endpoint@1 {
1092                                                 reg = <1>;
1093                                                 remote-endpoint = <&be1_in_fe1>;
1094                                         };
1095                                 };
1096                         };
1097                 };
1098
1099                 be1: display-backend@1e40000 {
1100                         compatible = "allwinner,sun6i-a31-display-backend";
1101                         reg = <0x01e40000 0x10000>;
1102                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1103                         clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1104                                  <&ccu CLK_DRAM_BE1>;
1105                         clock-names = "ahb", "mod",
1106                                       "ram";
1107                         resets = <&ccu RST_AHB1_BE1>;
1108
1109                         assigned-clocks = <&ccu CLK_BE1>;
1110                         assigned-clock-rates = <300000000>;
1111
1112                         ports {
1113                                 #address-cells = <1>;
1114                                 #size-cells = <0>;
1115
1116                                 be1_in: port@0 {
1117                                         #address-cells = <1>;
1118                                         #size-cells = <0>;
1119                                         reg = <0>;
1120
1121                                         be1_in_fe0: endpoint@0 {
1122                                                 reg = <0>;
1123                                                 remote-endpoint = <&fe0_out_be1>;
1124                                         };
1125
1126                                         be1_in_fe1: endpoint@1 {
1127                                                 reg = <1>;
1128                                                 remote-endpoint = <&fe1_out_be1>;
1129                                         };
1130                                 };
1131
1132                                 be1_out: port@1 {
1133                                         #address-cells = <1>;
1134                                         #size-cells = <0>;
1135                                         reg = <1>;
1136
1137                                         be1_out_drc1: endpoint@1 {
1138                                                 reg = <1>;
1139                                                 remote-endpoint = <&drc1_in_be1>;
1140                                         };
1141                                 };
1142                         };
1143                 };
1144
1145                 drc1: drc@1e50000 {
1146                         compatible = "allwinner,sun6i-a31-drc";
1147                         reg = <0x01e50000 0x10000>;
1148                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1149                         clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1150                                  <&ccu CLK_DRAM_DRC1>;
1151                         clock-names = "ahb", "mod",
1152                                       "ram";
1153                         resets = <&ccu RST_AHB1_DRC1>;
1154
1155                         assigned-clocks = <&ccu CLK_IEP_DRC1>;
1156                         assigned-clock-rates = <300000000>;
1157
1158                         ports {
1159                                 #address-cells = <1>;
1160                                 #size-cells = <0>;
1161
1162                                 drc1_in: port@0 {
1163                                         #address-cells = <1>;
1164                                         #size-cells = <0>;
1165                                         reg = <0>;
1166
1167                                         drc1_in_be1: endpoint@1 {
1168                                                 reg = <1>;
1169                                                 remote-endpoint = <&be1_out_drc1>;
1170                                         };
1171                                 };
1172
1173                                 drc1_out: port@1 {
1174                                         #address-cells = <1>;
1175                                         #size-cells = <0>;
1176                                         reg = <1>;
1177
1178                                         drc1_out_tcon0: endpoint@0 {
1179                                                 reg = <0>;
1180                                                 remote-endpoint = <&tcon0_in_drc1>;
1181                                         };
1182
1183                                         drc1_out_tcon1: endpoint@1 {
1184                                                 reg = <1>;
1185                                                 remote-endpoint = <&tcon1_in_drc1>;
1186                                         };
1187                                 };
1188                         };
1189                 };
1190
1191                 be0: display-backend@1e60000 {
1192                         compatible = "allwinner,sun6i-a31-display-backend";
1193                         reg = <0x01e60000 0x10000>;
1194                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1195                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1196                                  <&ccu CLK_DRAM_BE0>;
1197                         clock-names = "ahb", "mod",
1198                                       "ram";
1199                         resets = <&ccu RST_AHB1_BE0>;
1200
1201                         assigned-clocks = <&ccu CLK_BE0>;
1202                         assigned-clock-rates = <300000000>;
1203
1204                         ports {
1205                                 #address-cells = <1>;
1206                                 #size-cells = <0>;
1207
1208                                 be0_in: port@0 {
1209                                         #address-cells = <1>;
1210                                         #size-cells = <0>;
1211                                         reg = <0>;
1212
1213                                         be0_in_fe0: endpoint@0 {
1214                                                 reg = <0>;
1215                                                 remote-endpoint = <&fe0_out_be0>;
1216                                         };
1217
1218                                         be0_in_fe1: endpoint@1 {
1219                                                 reg = <1>;
1220                                                 remote-endpoint = <&fe1_out_be0>;
1221                                         };
1222                                 };
1223
1224                                 be0_out: port@1 {
1225                                         #address-cells = <1>;
1226                                         #size-cells = <0>;
1227                                         reg = <1>;
1228
1229                                         be0_out_drc0: endpoint@0 {
1230                                                 reg = <0>;
1231                                                 remote-endpoint = <&drc0_in_be0>;
1232                                         };
1233                                 };
1234                         };
1235                 };
1236
1237                 drc0: drc@1e70000 {
1238                         compatible = "allwinner,sun6i-a31-drc";
1239                         reg = <0x01e70000 0x10000>;
1240                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1241                         clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1242                                  <&ccu CLK_DRAM_DRC0>;
1243                         clock-names = "ahb", "mod",
1244                                       "ram";
1245                         resets = <&ccu RST_AHB1_DRC0>;
1246
1247                         assigned-clocks = <&ccu CLK_IEP_DRC0>;
1248                         assigned-clock-rates = <300000000>;
1249
1250                         ports {
1251                                 #address-cells = <1>;
1252                                 #size-cells = <0>;
1253
1254                                 drc0_in: port@0 {
1255                                         #address-cells = <1>;
1256                                         #size-cells = <0>;
1257                                         reg = <0>;
1258
1259                                         drc0_in_be0: endpoint@0 {
1260                                                 reg = <0>;
1261                                                 remote-endpoint = <&be0_out_drc0>;
1262                                         };
1263                                 };
1264
1265                                 drc0_out: port@1 {
1266                                         #address-cells = <1>;
1267                                         #size-cells = <0>;
1268                                         reg = <1>;
1269
1270                                         drc0_out_tcon0: endpoint@0 {
1271                                                 reg = <0>;
1272                                                 remote-endpoint = <&tcon0_in_drc0>;
1273                                         };
1274
1275                                         drc0_out_tcon1: endpoint@1 {
1276                                                 reg = <1>;
1277                                                 remote-endpoint = <&tcon1_in_drc0>;
1278                                         };
1279                                 };
1280                         };
1281                 };
1282
1283                 rtc: rtc@1f00000 {
1284                         compatible = "allwinner,sun6i-a31-rtc";
1285                         reg = <0x01f00000 0x54>;
1286                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1287                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1288                 };
1289
1290                 nmi_intc: interrupt-controller@1f00c00 {
1291                         compatible = "allwinner,sun6i-a31-r-intc";
1292                         interrupt-controller;
1293                         #interrupt-cells = <2>;
1294                         reg = <0x01f00c00 0x400>;
1295                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1296                 };
1297
1298                 prcm@1f01400 {
1299                         compatible = "allwinner,sun6i-a31-prcm";
1300                         reg = <0x01f01400 0x200>;
1301
1302                         ar100: ar100_clk {
1303                                 compatible = "allwinner,sun6i-a31-ar100-clk";
1304                                 #clock-cells = <0>;
1305                                 clocks = <&osc32k>, <&osc24M>,
1306                                          <&ccu CLK_PLL_PERIPH>,
1307                                          <&ccu CLK_PLL_PERIPH>;
1308                                 clock-output-names = "ar100";
1309                         };
1310
1311                         ahb0: ahb0_clk {
1312                                 compatible = "fixed-factor-clock";
1313                                 #clock-cells = <0>;
1314                                 clock-div = <1>;
1315                                 clock-mult = <1>;
1316                                 clocks = <&ar100>;
1317                                 clock-output-names = "ahb0";
1318                         };
1319
1320                         apb0: apb0_clk {
1321                                 compatible = "allwinner,sun6i-a31-apb0-clk";
1322                                 #clock-cells = <0>;
1323                                 clocks = <&ahb0>;
1324                                 clock-output-names = "apb0";
1325                         };
1326
1327                         apb0_gates: apb0_gates_clk {
1328                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1329                                 #clock-cells = <1>;
1330                                 clocks = <&apb0>;
1331                                 clock-output-names = "apb0_pio", "apb0_ir",
1332                                                 "apb0_timer", "apb0_p2wi",
1333                                                 "apb0_uart", "apb0_1wire",
1334                                                 "apb0_i2c";
1335                         };
1336
1337                         ir_clk: ir_clk {
1338                                 #clock-cells = <0>;
1339                                 compatible = "allwinner,sun4i-a10-mod0-clk";
1340                                 clocks = <&osc32k>, <&osc24M>;
1341                                 clock-output-names = "ir";
1342                         };
1343
1344                         apb0_rst: apb0_rst {
1345                                 compatible = "allwinner,sun6i-a31-clock-reset";
1346                                 #reset-cells = <1>;
1347                         };
1348                 };
1349
1350                 cpucfg@1f01c00 {
1351                         compatible = "allwinner,sun6i-a31-cpuconfig";
1352                         reg = <0x01f01c00 0x300>;
1353                 };
1354
1355                 ir: ir@1f02000 {
1356                         compatible = "allwinner,sun5i-a13-ir";
1357                         clocks = <&apb0_gates 1>, <&ir_clk>;
1358                         clock-names = "apb", "ir";
1359                         resets = <&apb0_rst 1>;
1360                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1361                         reg = <0x01f02000 0x40>;
1362                         status = "disabled";
1363                 };
1364
1365                 r_pio: pinctrl@1f02c00 {
1366                         compatible = "allwinner,sun6i-a31-r-pinctrl";
1367                         reg = <0x01f02c00 0x400>;
1368                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1369                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1370                         clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1371                         clock-names = "apb", "hosc", "losc";
1372                         resets = <&apb0_rst 0>;
1373                         gpio-controller;
1374                         interrupt-controller;
1375                         #interrupt-cells = <3>;
1376                         #size-cells = <0>;
1377                         #gpio-cells = <3>;
1378
1379                         ir_pins_a: ir@0 {
1380                                 pins = "PL4";
1381                                 function = "s_ir";
1382                         };
1383
1384                         p2wi_pins: p2wi {
1385                                 pins = "PL0", "PL1";
1386                                 function = "s_p2wi";
1387                         };
1388                 };
1389
1390                 p2wi: i2c@1f03400 {
1391                         compatible = "allwinner,sun6i-a31-p2wi";
1392                         reg = <0x01f03400 0x400>;
1393                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1394                         clocks = <&apb0_gates 3>;
1395                         clock-frequency = <100000>;
1396                         resets = <&apb0_rst 3>;
1397                         pinctrl-names = "default";
1398                         pinctrl-0 = <&p2wi_pins>;
1399                         status = "disabled";
1400                         #address-cells = <1>;
1401                         #size-cells = <0>;
1402                 };
1403         };
1404 };