arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 / {
  10         model = "Qualcomm APQ8064";
  11         compatible = "qcom,apq8064";
  12         interrupt-parent = <&intc>;
  13
  14         reserved-memory {
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges;
  18
  19                 smem_region: smem@80000000 {
  20                         reg = <0x80000000 0x200000>;
  21                         no-map;
  22                 };
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu@0 {
  30                         compatible = "qcom,krait";
  31                         enable-method = "qcom,kpss-acc-v1";
  32                         device_type = "cpu";
  33                         reg = <0>;
  34                         next-level-cache = <&L2>;
  35                         qcom,acc = <&acc0>;
  36                         qcom,saw = <&saw0>;
  37                         cpu-idle-states = <&CPU_SPC>;
  38                 };
  39
  40                 cpu@1 {
  41                         compatible = "qcom,krait";
  42                         enable-method = "qcom,kpss-acc-v1";
  43                         device_type = "cpu";
  44                         reg = <1>;
  45                         next-level-cache = <&L2>;
  46                         qcom,acc = <&acc1>;
  47                         qcom,saw = <&saw1>;
  48                         cpu-idle-states = <&CPU_SPC>;
  49                 };
  50
  51                 cpu@2 {
  52                         compatible = "qcom,krait";
  53                         enable-method = "qcom,kpss-acc-v1";
  54                         device_type = "cpu";
  55                         reg = <2>;
  56                         next-level-cache = <&L2>;
  57                         qcom,acc = <&acc2>;
  58                         qcom,saw = <&saw2>;
  59                         cpu-idle-states = <&CPU_SPC>;
  60                 };
  61
  62                 cpu@3 {
  63                         compatible = "qcom,krait";
  64                         enable-method = "qcom,kpss-acc-v1";
  65                         device_type = "cpu";
  66                         reg = <3>;
  67                         next-level-cache = <&L2>;
  68                         qcom,acc = <&acc3>;
  69                         qcom,saw = <&saw3>;
  70                         cpu-idle-states = <&CPU_SPC>;
  71                 };
  72
  73                 L2: l2-cache {
  74                         compatible = "cache";
  75                         cache-level = <2>;
  76                 };
  77
  78                 idle-states {
  79                         CPU_SPC: spc {
  80                                 compatible = "qcom,idle-state-spc",
  81                                                 "arm,idle-state";
  82                                 entry-latency-us = <400>;
  83                                 exit-latency-us = <900>;
  84                                 min-residency-us = <3000>;
  85                         };
  86                 };
  87         };
  88
  89         cpu-pmu {
  90                 compatible = "qcom,krait-pmu";
  91                 interrupts = <1 10 0x304>;
  92         };
  93
  94         clocks {
  95                 cxo_board {
  96                         compatible = "fixed-clock";
  97                         #clock-cells = <0>;
  98                         clock-frequency = <19200000>;
  99                 };
 100
 101                 pxo_board {
 102                         compatible = "fixed-clock";
 103                         #clock-cells = <0>;
 104                         clock-frequency = <27000000>;
 105                 };
 106
 107                 sleep_clk {
 108                         compatible = "fixed-clock";
 109                         #clock-cells = <0>;
 110                         clock-frequency = <32768>;
 111                 };
 112         };
 113
 114         sfpb_mutex: hwmutex {
 115                 compatible = "qcom,sfpb-mutex";
 116                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
 117                 #hwlock-cells = <1>;
 118         };
 119
 120         smem {
 121                 compatible = "qcom,smem";
 122                 memory-region = <&smem_region>;
 123
 124                 hwlocks = <&sfpb_mutex 3>;
 125         };
 126
 127         soc: soc {
 128                 #address-cells = <1>;
 129                 #size-cells = <1>;
 130                 ranges;
 131                 compatible = "simple-bus";
 132
 133                 tlmm_pinmux: pinctrl@800000 {
 134                         compatible = "qcom,apq8064-pinctrl";
 135                         reg = <0x800000 0x4000>;
 136
 137                         gpio-controller;
 138                         #gpio-cells = <2>;
 139                         interrupt-controller;
 140                         #interrupt-cells = <2>;
 141                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 142
 143                         pinctrl-names = "default";
 144                         pinctrl-0 = <&ps_hold>;
 145                 };
 146
 147                 sfpb_wrapper_mutex: syscon@1200000 {
 148                         compatible = "syscon";
 149                         reg = <0x01200000 0x8000>;
 150                 };
 151
 152                 intc: interrupt-controller@2000000 {
 153                         compatible = "qcom,msm-qgic2";
 154                         interrupt-controller;
 155                         #interrupt-cells = <3>;
 156                         reg = <0x02000000 0x1000>,
 157                               <0x02002000 0x1000>;
 158                 };
 159
 160                 timer@200a000 {
 161                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 162                         interrupts = <1 1 0x301>,
 163                                      <1 2 0x301>,
 164                                      <1 3 0x301>;
 165                         reg = <0x0200a000 0x100>;
 166                         clock-frequency = <27000000>,
 167                                           <32768>;
 168                         cpu-offset = <0x80000>;
 169                 };
 170
 171                 acc0: clock-controller@2088000 {
 172                         compatible = "qcom,kpss-acc-v1";
 173                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 174                 };
 175
 176                 acc1: clock-controller@2098000 {
 177                         compatible = "qcom,kpss-acc-v1";
 178                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 179                 };
 180
 181                 acc2: clock-controller@20a8000 {
 182                         compatible = "qcom,kpss-acc-v1";
 183                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 184                 };
 185
 186                 acc3: clock-controller@20b8000 {
 187                         compatible = "qcom,kpss-acc-v1";
 188                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 189                 };
 190
 191                 saw0: power-controller@2089000 {
 192                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 193                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 194                         regulator;
 195                 };
 196
 197                 saw1: power-controller@2099000 {
 198                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 199                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 200                         regulator;
 201                 };
 202
 203                 saw2: power-controller@20a9000 {
 204                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 205                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 206                         regulator;
 207                 };
 208
 209                 saw3: power-controller@20b9000 {
 210                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 211                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 212                         regulator;
 213                 };
 214
 215                 gsbi1: gsbi@12440000 {
 216                         status = "disabled";
 217                         compatible = "qcom,gsbi-v1.0.0";
 218                         cell-index = <1>;
 219                         reg = <0x12440000 0x100>;
 220                         clocks = <&gcc GSBI1_H_CLK>;
 221                         clock-names = "iface";
 222                         #address-cells = <1>;
 223                         #size-cells = <1>;
 224                         ranges;
 225
 226                         syscon-tcsr = <&tcsr>;
 227
 228                         gsbi1_i2c: i2c@12460000 {
 229                                 compatible = "qcom,i2c-qup-v1.1.1";
 230                                 pinctrl-0 = <&i2c1_pins &i2c1_pins_sleep>;
 231                                 pinctrl-names = "default", "sleep";
 232                                 reg = <0x12460000 0x1000>;
 233                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 234                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 235                                 clock-names = "core", "iface";
 236                                 #address-cells = <1>;
 237                                 #size-cells = <0>;
 238                         };
 239
 240                 };
 241
 242                 gsbi2: gsbi@12480000 {
 243                         status = "disabled";
 244                         compatible = "qcom,gsbi-v1.0.0";
 245                         cell-index = <2>;
 246                         reg = <0x12480000 0x100>;
 247                         clocks = <&gcc GSBI2_H_CLK>;
 248                         clock-names = "iface";
 249                         #address-cells = <1>;
 250                         #size-cells = <1>;
 251                         ranges;
 252
 253                         syscon-tcsr = <&tcsr>;
 254
 255                         gsbi2_i2c: i2c@124a0000 {
 256                                 compatible = "qcom,i2c-qup-v1.1.1";
 257                                 reg = <0x124a0000 0x1000>;
 258                                 pinctrl-0 = <&i2c2_pins &i2c2_pins_sleep>;
 259                                 pinctrl-names = "default", "sleep";
 260                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 261                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 262                                 clock-names = "core", "iface";
 263                                 #address-cells = <1>;
 264                                 #size-cells = <0>;
 265                         };
 266                 };
 267
 268                 gsbi3: gsbi@16200000 {
 269                         status = "disabled";
 270                         compatible = "qcom,gsbi-v1.0.0";
 271                         cell-index = <3>;
 272                         reg = <0x16200000 0x100>;
 273                         clocks = <&gcc GSBI3_H_CLK>;
 274                         clock-names = "iface";
 275                         #address-cells = <1>;
 276                         #size-cells = <1>;
 277                         ranges;
 278                         gsbi3_i2c: i2c@16280000 {
 279                                 compatible = "qcom,i2c-qup-v1.1.1";
 280                                 pinctrl-0 = <&i2c3_pins &i2c3_pins_sleep>;
 281                                 pinctrl-names = "default", "sleep";
 282                                 reg = <0x16280000 0x1000>;
 283                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 284                                 clocks = <&gcc GSBI3_QUP_CLK>,
 285                                          <&gcc GSBI3_H_CLK>;
 286                                 clock-names = "core", "iface";
 287                                 #address-cells = <1>;
 288                                 #size-cells = <0>;
 289                         };
 290                 };
 291
 292                 gsbi4: gsbi@16300000 {
 293                         status = "disabled";
 294                         compatible = "qcom,gsbi-v1.0.0";
 295                         cell-index = <4>;
 296                         reg = <0x16300000 0x03>;
 297                         clocks = <&gcc GSBI4_H_CLK>;
 298                         clock-names = "iface";
 299                         #address-cells = <1>;
 300                         #size-cells = <1>;
 301                         ranges;
 302
 303                         gsbi4_i2c: i2c@16380000 {
 304                                 compatible = "qcom,i2c-qup-v1.1.1";
 305                                 pinctrl-0 = <&i2c4_pins &i2c4_pins_sleep>;
 306                                 pinctrl-names = "default", "sleep";
 307                                 reg = <0x16380000 0x1000>;
 308                                 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
 309                                 clocks = <&gcc GSBI4_QUP_CLK>,
 310                                          <&gcc GSBI4_H_CLK>;
 311                                 clock-names = "core", "iface";
 312                         };
 313                 };
 314
 315                 gsbi5: gsbi@1a200000 {
 316                         status = "disabled";
 317                         compatible = "qcom,gsbi-v1.0.0";
 318                         cell-index = <5>;
 319                         reg = <0x1a200000 0x03>;
 320                         clocks = <&gcc GSBI5_H_CLK>;
 321                         clock-names = "iface";
 322                         #address-cells = <1>;
 323                         #size-cells = <1>;
 324                         ranges;
 325
 326                         gsbi5_serial: serial@1a240000 {
 327                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 328                                 reg = <0x1a240000 0x100>,
 329                                       <0x1a200000 0x03>;
 330                                 interrupts = <0 154 0x0>;
 331                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 332                                 clock-names = "core", "iface";
 333                                 status = "disabled";
 334                         };
 335
 336                         gsbi5_spi: spi@1a280000 {
 337                                 compatible = "qcom,spi-qup-v1.1.1";
 338                                 reg = <0x1a280000 0x1000>;
 339                                 interrupts = <0 155 0>;
 340                                 pinctrl-0 = <&spi5_default &spi5_sleep>;
 341                                 pinctrl-names = "default", "sleep";
 342                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 343                                 clock-names = "core", "iface";
 344                                 status = "disabled";
 345                                 #address-cells = <1>;
 346                                 #size-cells = <0>;
 347                         };
 348                 };
 349
 350                 gsbi6: gsbi@16500000 {
 351                         status = "disabled";
 352                         compatible = "qcom,gsbi-v1.0.0";
 353                         cell-index = <6>;
 354                         reg = <0x16500000 0x03>;
 355                         clocks = <&gcc GSBI6_H_CLK>;
 356                         clock-names = "iface";
 357                         #address-cells = <1>;
 358                         #size-cells = <1>;
 359                         ranges;
 360
 361                         gsbi6_serial: serial@16540000 {
 362                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 363                                 reg = <0x16540000 0x100>,
 364                                       <0x16500000 0x03>;
 365                                 interrupts = <0 156 0x0>;
 366                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 367                                 clock-names = "core", "iface";
 368                                 status = "disabled";
 369                         };
 370
 371                         gsbi6_i2c: i2c@16580000 {
 372                                 compatible = "qcom,i2c-qup-v1.1.1";
 373                                 pinctrl-0 = <&i2c6_pins &i2c6_pins_sleep>;
 374                                 pinctrl-names = "default", "sleep";
 375                                 reg = <0x16580000 0x1000>;
 376                                 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
 377                                 clocks = <&gcc GSBI6_QUP_CLK>,
 378                                          <&gcc GSBI6_H_CLK>;
 379                                 clock-names = "core", "iface";
 380                         };
 381                 };
 382
 383                 gsbi7: gsbi@16600000 {
 384                         status = "disabled";
 385                         compatible = "qcom,gsbi-v1.0.0";
 386                         cell-index = <7>;
 387                         reg = <0x16600000 0x100>;
 388                         clocks = <&gcc GSBI7_H_CLK>;
 389                         clock-names = "iface";
 390                         #address-cells = <1>;
 391                         #size-cells = <1>;
 392                         ranges;
 393                         syscon-tcsr = <&tcsr>;
 394
 395                         gsbi7_serial: serial@16640000 {
 396                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 397                                 reg = <0x16640000 0x1000>,
 398                                       <0x16600000 0x1000>;
 399                                 interrupts = <0 158 0x0>;
 400                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 401                                 clock-names = "core", "iface";
 402                                 status = "disabled";
 403                         };
 404                 };
 405
 406                 rng@1a500000 {
 407                         compatible = "qcom,prng";
 408                         reg = <0x1a500000 0x200>;
 409                         clocks = <&gcc PRNG_CLK>;
 410                         clock-names = "core";
 411                 };
 412
 413                 qcom,ssbi@500000 {
 414                         compatible = "qcom,ssbi";
 415                         reg = <0x00500000 0x1000>;
 416                         qcom,controller-type = "pmic-arbiter";
 417
 418                         pmicintc: pmic@0 {
 419                                 compatible = "qcom,pm8921";
 420                                 interrupt-parent = <&tlmm_pinmux>;
 421                                 interrupts = <74 8>;
 422                                 #interrupt-cells = <2>;
 423                                 interrupt-controller;
 424                                 #address-cells = <1>;
 425                                 #size-cells = <0>;
 426
 427                                 pm8921_gpio: gpio@150 {
 428
 429                                         compatible = "qcom,pm8921-gpio",
 430                                                      "qcom,ssbi-gpio";
 431                                         reg = <0x150>;
 432                                         interrupts = <192 1>, <193 1>, <194 1>,
 433                                                      <195 1>, <196 1>, <197 1>,
 434                                                      <198 1>, <199 1>, <200 1>,
 435                                                      <201 1>, <202 1>, <203 1>,
 436                                                      <204 1>, <205 1>, <206 1>,
 437                                                      <207 1>, <208 1>, <209 1>,
 438                                                      <210 1>, <211 1>, <212 1>,
 439                                                      <213 1>, <214 1>, <215 1>,
 440                                                      <216 1>, <217 1>, <218 1>,
 441                                                      <219 1>, <220 1>, <221 1>,
 442                                                      <222 1>, <223 1>, <224 1>,
 443                                                      <225 1>, <226 1>, <227 1>,
 444                                                      <228 1>, <229 1>, <230 1>,
 445                                                      <231 1>, <232 1>, <233 1>,
 446                                                      <234 1>, <235 1>;
 447
 448                                         gpio-controller;
 449                                         #gpio-cells = <2>;
 450
 451                                 };
 452
 453                                 pm8921_mpps: mpps@50 {
 454                                         compatible = "qcom,pm8921-mpp",
 455                                                      "qcom,ssbi-mpp";
 456                                         reg = <0x50>;
 457                                         gpio-controller;
 458                                         #gpio-cells = <2>;
 459                                         interrupts =
 460                                         <128 1>, <129 1>, <130 1>, <131 1>,
 461                                         <132 1>, <133 1>, <134 1>, <135 1>,
 462                                         <136 1>, <137 1>, <138 1>, <139 1>;
 463                                 };
 464
 465                                 rtc@11d {
 466                                         compatible = "qcom,pm8921-rtc";
 467                                         interrupt-parent = <&pmicintc>;
 468                                         interrupts = <39 1>;
 469                                         reg = <0x11d>;
 470                                         allow-set-time;
 471                                 };
 472
 473                                 pwrkey@1c {
 474                                         compatible = "qcom,pm8921-pwrkey";
 475                                         reg = <0x1c>;
 476                                         interrupt-parent = <&pmicintc>;
 477                                         interrupts = <50 1>, <51 1>;
 478                                         debounce = <15625>;
 479                                         pull-up;
 480                                 };
 481                         };
 482                 };
 483
 484                 gcc: clock-controller@900000 {
 485                         compatible = "qcom,gcc-apq8064";
 486                         reg = <0x00900000 0x4000>;
 487                         #clock-cells = <1>;
 488                         #reset-cells = <1>;
 489                 };
 490
 491                 lcc: clock-controller@28000000 {
 492                         compatible = "qcom,lcc-apq8064";
 493                         reg = <0x28000000 0x1000>;
 494                         #clock-cells = <1>;
 495                         #reset-cells = <1>;
 496                 };
 497
 498                 mmcc: clock-controller@4000000 {
 499                         compatible = "qcom,mmcc-apq8064";
 500                         reg = <0x4000000 0x1000>;
 501                         #clock-cells = <1>;
 502                         #reset-cells = <1>;
 503                 };
 504
 505                 l2cc: clock-controller@2011000 {
 506                         compatible      = "syscon";
 507                         reg             = <0x2011000 0x1000>;
 508                 };
 509
 510                 rpm@108000 {
 511                         compatible      = "qcom,rpm-apq8064";
 512                         reg             = <0x108000 0x1000>;
 513                         qcom,ipc        = <&l2cc 0x8 2>;
 514
 515                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 516                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 517                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 518                         interrupt-names = "ack", "err", "wakeup";
 519
 520                         rpmcc: clock-controller {
 521                                 compatible      = "qcom,rpmcc-apq8064", "qcom,rpmcc";
 522                                 #clock-cells = <1>;
 523                         };
 524
 525                         regulators {
 526                                 compatible = "qcom,rpm-pm8921-regulators";
 527
 528                                 pm8921_s1: s1 {};
 529                                 pm8921_s2: s2 {};
 530                                 pm8921_s3: s3 {};
 531                                 pm8921_s4: s4 {};
 532                                 pm8921_s7: s7 {};
 533                                 pm8921_s8: s8 {};
 534
 535                                 pm8921_l1: l1 {};
 536                                 pm8921_l2: l2 {};
 537                                 pm8921_l3: l3 {};
 538                                 pm8921_l4: l4 {};
 539                                 pm8921_l5: l5 {};
 540                                 pm8921_l6: l6 {};
 541                                 pm8921_l7: l7 {};
 542                                 pm8921_l8: l8 {};
 543                                 pm8921_l9: l9 {};
 544                                 pm8921_l10: l10 {};
 545                                 pm8921_l11: l11 {};
 546                                 pm8921_l12: l12 {};
 547                                 pm8921_l14: l14 {};
 548                                 pm8921_l15: l15 {};
 549                                 pm8921_l16: l16 {};
 550                                 pm8921_l17: l17 {};
 551                                 pm8921_l18: l18 {};
 552                                 pm8921_l21: l21 {};
 553                                 pm8921_l22: l22 {};
 554                                 pm8921_l23: l23 {};
 555                                 pm8921_l24: l24 {};
 556                                 pm8921_l25: l25 {};
 557                                 pm8921_l26: l26 {};
 558                                 pm8921_l27: l27 {};
 559                                 pm8921_l28: l28 {};
 560                                 pm8921_l29: l29 {};
 561
 562                                 pm8921_lvs1: lvs1 {};
 563                                 pm8921_lvs2: lvs2 {};
 564                                 pm8921_lvs3: lvs3 {};
 565                                 pm8921_lvs4: lvs4 {};
 566                                 pm8921_lvs5: lvs5 {};
 567                                 pm8921_lvs6: lvs6 {};
 568                                 pm8921_lvs7: lvs7 {};
 569
 570                                 pm8921_usb_switch: usb-switch {};
 571
 572                                 pm8921_hdmi_switch: hdmi-switch {
 573                                         bias-pull-down;
 574                                 };
 575
 576                                 pm8921_ncp: ncp {};
 577                         };
 578                 };
 579
 580                 usb1_phy: phy@12500000 {
 581                         compatible      = "qcom,usb-otg-ci";
 582                         reg             = <0x12500000 0x400>;
 583                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 584                         status          = "disabled";
 585                         dr_mode         = "host";
 586
 587                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
 588                                           <&gcc USB_HS1_H_CLK>;
 589                         clock-names     = "core", "iface";
 590
 591                         resets          = <&gcc USB_HS1_RESET>;
 592                         reset-names     = "link";
 593                 };
 594
 595                 usb3_phy: phy@12520000 {
 596                         compatible      = "qcom,usb-otg-ci";
 597                         reg             = <0x12520000 0x400>;
 598                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 599                         status          = "disabled";
 600                         dr_mode         = "host";
 601
 602                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
 603                                           <&gcc USB_HS3_H_CLK>;
 604                         clock-names     = "core", "iface";
 605
 606                         resets          = <&gcc USB_HS3_RESET>;
 607                         reset-names     = "link";
 608                 };
 609
 610                 usb4_phy: phy@12530000 {
 611                         compatible      = "qcom,usb-otg-ci";
 612                         reg             = <0x12530000 0x400>;
 613                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 614                         status          = "disabled";
 615                         dr_mode         = "host";
 616
 617                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
 618                                           <&gcc USB_HS4_H_CLK>;
 619                         clock-names     = "core", "iface";
 620
 621                         resets          = <&gcc USB_HS4_RESET>;
 622                         reset-names     = "link";
 623                 };
 624
 625                 gadget1: gadget@12500000 {
 626                         compatible      = "qcom,ci-hdrc";
 627                         reg             = <0x12500000 0x400>;
 628                         status          = "disabled";
 629                         dr_mode         = "peripheral";
 630                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 631                         usb-phy         = <&usb1_phy>;
 632                 };
 633
 634                 usb1: usb@12500000 {
 635                         compatible      = "qcom,ehci-host";
 636                         reg             = <0x12500000 0x400>;
 637                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 638                         status          = "disabled";
 639                         usb-phy         = <&usb1_phy>;
 640                 };
 641
 642                 usb3: usb@12520000 {
 643                         compatible      = "qcom,ehci-host";
 644                         reg             = <0x12520000 0x400>;
 645                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 646                         status          = "disabled";
 647                         usb-phy         = <&usb3_phy>;
 648                 };
 649
 650                 usb4: usb@12530000 {
 651                         compatible      = "qcom,ehci-host";
 652                         reg             = <0x12530000 0x400>;
 653                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 654                         status          = "disabled";
 655                         usb-phy         = <&usb4_phy>;
 656                 };
 657
 658                 sata_phy0: phy@1b400000 {
 659                         compatible      = "qcom,apq8064-sata-phy";
 660                         status          = "disabled";
 661                         reg             = <0x1b400000 0x200>;
 662                         reg-names       = "phy_mem";
 663                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
 664                         clock-names     = "cfg";
 665                         #phy-cells      = <0>;
 666                 };
 667
 668                 sata0: sata@29000000 {
 669                         compatible              = "generic-ahci";
 670                         status                  = "disabled";
 671                         reg                     = <0x29000000 0x180>;
 672                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
 673
 674                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
 675                                                 <&gcc SATA_H_CLK>,
 676                                                 <&gcc SATA_A_CLK>,
 677                                                 <&gcc SATA_RXOOB_CLK>,
 678                                                 <&gcc SATA_PMALIVE_CLK>;
 679                         clock-names             = "slave_iface",
 680                                                 "iface",
 681                                                 "bus",
 682                                                 "rxoob",
 683                                                 "core_pmalive";
 684
 685                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
 686                                                 <&gcc SATA_PMALIVE_CLK>;
 687                         assigned-clock-rates    = <100000000>, <100000000>;
 688
 689                         phys                    = <&sata_phy0>;
 690                         phy-names               = "sata-phy";
 691                 };
 692
 693                 /* Temporary fixed regulator */
 694                 sdcc1bam:dma@12402000{
 695                         compatible = "qcom,bam-v1.3.0";
 696                         reg = <0x12402000 0x8000>;
 697                         interrupts = <0 98 0>;
 698                         clocks = <&gcc SDC1_H_CLK>;
 699                         clock-names = "bam_clk";
 700                         #dma-cells = <1>;
 701                         qcom,ee = <0>;
 702                 };
 703
 704                 sdcc3bam:dma@12182000{
 705                         compatible = "qcom,bam-v1.3.0";
 706                         reg = <0x12182000 0x8000>;
 707                         interrupts = <0 96 0>;
 708                         clocks = <&gcc SDC3_H_CLK>;
 709                         clock-names = "bam_clk";
 710                         #dma-cells = <1>;
 711                         qcom,ee = <0>;
 712                 };
 713
 714                 sdcc4bam:dma@121c2000{
 715                         compatible = "qcom,bam-v1.3.0";
 716                         reg = <0x121c2000 0x8000>;
 717                         interrupts = <0 95 0>;
 718                         clocks = <&gcc SDC4_H_CLK>;
 719                         clock-names = "bam_clk";
 720                         #dma-cells = <1>;
 721                         qcom,ee = <0>;
 722                 };
 723
 724                 amba {
 725                         compatible = "simple-bus";
 726                         #address-cells = <1>;
 727                         #size-cells = <1>;
 728                         ranges;
 729                         sdcc1: sdcc@12400000 {
 730                                 status          = "disabled";
 731                                 compatible      = "arm,pl18x", "arm,primecell";
 732                                 arm,primecell-periphid = <0x00051180>;
 733                                 reg             = <0x12400000 0x2000>;
 734                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 735                                 interrupt-names = "cmd_irq";
 736                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 737                                 clock-names     = "mclk", "apb_pclk";
 738                                 bus-width       = <8>;
 739                                 max-frequency   = <96000000>;
 740                                 non-removable;
 741                                 cap-sd-highspeed;
 742                                 cap-mmc-highspeed;
 743                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 744                                 dma-names = "tx", "rx";
 745                         };
 746
 747                         sdcc3: sdcc@12180000 {
 748                                 compatible      = "arm,pl18x", "arm,primecell";
 749                                 arm,primecell-periphid = <0x00051180>;
 750                                 status          = "disabled";
 751                                 reg             = <0x12180000 0x2000>;
 752                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 753                                 interrupt-names = "cmd_irq";
 754                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 755                                 clock-names     = "mclk", "apb_pclk";
 756                                 bus-width       = <4>;
 757                                 cap-sd-highspeed;
 758                                 cap-mmc-highspeed;
 759                                 max-frequency   = <192000000>;
 760                                 no-1-8-v;
 761                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 762                                 dma-names = "tx", "rx";
 763                         };
 764
 765                         sdcc4: sdcc@121c0000 {
 766                                 compatible      = "arm,pl18x", "arm,primecell";
 767                                 arm,primecell-periphid = <0x00051180>;
 768                                 status          = "disabled";
 769                                 reg             = <0x121c0000 0x2000>;
 770                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 771                                 interrupt-names = "cmd_irq";
 772                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 773                                 clock-names     = "mclk", "apb_pclk";
 774                                 bus-width       = <4>;
 775                                 cap-sd-highspeed;
 776                                 cap-mmc-highspeed;
 777                                 max-frequency   = <48000000>;
 778                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
 779                                 dma-names = "tx", "rx";
 780                                 pinctrl-names = "default";
 781                                 pinctrl-0 = <&sdc4_gpios>;
 782                         };
 783                 };
 784
 785                 tcsr: syscon@1a400000 {
 786                         compatible = "qcom,tcsr-apq8064", "syscon";
 787                         reg = <0x1a400000 0x100>;
 788                 };
 789
 790                 pcie: pci@1b500000 {
 791                         compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
 792                         reg = <0x1b500000 0x1000
 793                                0x1b502000 0x80
 794                                0x1b600000 0x100
 795                                0x0ff00000 0x100000>;
 796                         reg-names = "dbi", "elbi", "parf", "config";
 797                         device_type = "pci";
 798                         linux,pci-domain = <0>;
 799                         bus-range = <0x00 0xff>;
 800                         num-lanes = <1>;
 801                         #address-cells = <3>;
 802                         #size-cells = <2>;
 803                         ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
 804                                   0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
 805                         interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
 806                         interrupt-names = "msi";
 807                         #interrupt-cells = <1>;
 808                         interrupt-map-mask = <0 0 0 0x7>;
 809                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 810                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 811                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 812                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 813                         clocks = <&gcc PCIE_A_CLK>,
 814                                  <&gcc PCIE_H_CLK>,
 815                                  <&gcc PCIE_PHY_REF_CLK>;
 816                         clock-names = "core", "iface", "phy";
 817                         resets = <&gcc PCIE_ACLK_RESET>,
 818                                  <&gcc PCIE_HCLK_RESET>,
 819                                  <&gcc PCIE_POR_RESET>,
 820                                  <&gcc PCIE_PCI_RESET>,
 821                                  <&gcc PCIE_PHY_RESET>;
 822                         reset-names = "axi", "ahb", "por", "pci", "phy";
 823                         status = "disabled";
 824                 };
 825         };
 826 };
 827 #include "qcom-apq8064-pins.dtsi"