arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Device Tree file for SolidRun Armada 38x Microsom
   4  *
   5  *  Copyright (C) 2015 Russell King
   6  *
   7  * This board is in development; the contents of this file work with
   8  * the A1 rev 2.0 of the board, which does not represent final
   9  * production board.  Things will change, don't expect this file to
  10  * remain compatible info the future.
  11  */
  12 #include <dt-bindings/input/input.h>
  13 #include <dt-bindings/gpio/gpio.h>
  14
  15 / {
  16         memory {
  17                 device_type = "memory";
  18                 reg = <0x00000000 0x10000000>; /* 256 MB */
  19         };
  20
  21         soc {
  22                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  23                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
  24                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
  25                           MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
  26                           MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
  27
  28                 internal-regs {
  29                         rtc@a3800 {
  30                                 /*
  31                                  * If the rtc doesn't work, run "date reset"
  32                                  * twice in u-boot.
  33                                  */
  34                                 status = "okay";
  35                         };
  36                 };
  37         };
  38 };
  39
  40 &bm {
  41         status = "okay";
  42 };
  43
  44 &bm_bppi {
  45         status = "okay";
  46 };
  47
  48 &eth0 {
  49         /* ethernet@70000 */
  50         pinctrl-0 = <&ge0_rgmii_pins>;
  51         pinctrl-names = "default";
  52         phy = <&phy_dedicated>;
  53         phy-mode = "rgmii-id";
  54         buffer-manager = <&bm>;
  55         bm,pool-long = <0>;
  56         bm,pool-short = <1>;
  57         status = "okay";
  58 };
  59
  60 &mdio {
  61         /*
  62          * Add the phy clock here, so the phy can be accessed to read its
  63          * IDs prior to binding with the driver.
  64          */
  65         pinctrl-0 = <&mdio_pins &microsom_phy_clk_pins>;
  66         pinctrl-names = "default";
  67
  68         phy_dedicated: ethernet-phy@0 {
  69                 /*
  70                  * Annoyingly, the marvell phy driver configures the LED
  71                  * register, rather than preserving reset-loaded setting.
  72                  * We undo that rubbish here.
  73                  */
  74                 marvell,reg-init = <3 16 0 0x101e>;
  75                 reg = <0>;
  76         };
  77 };
  78
  79 &pinctrl {
  80         microsom_phy_clk_pins: microsom-phy-clk-pins {
  81                 marvell,pins = "mpp45";
  82                 marvell,function = "ref";
  83         };
  84         /* Optional eMMC */
  85         microsom_sdhci_pins: microsom-sdhci-pins {
  86                 marvell,pins = "mpp21", "mpp28", "mpp37",
  87                                "mpp38", "mpp39", "mpp40";
  88                 marvell,function = "sd0";
  89         };
  90 };
  91
  92 &spi1 {
  93         /* The microsom has an optional W25Q32 on board, connected to CS0 */
  94         pinctrl-0 = <&spi1_pins>;
  95
  96         w25q32: spi-flash@0 {
  97                 #address-cells = <1>;
  98                 #size-cells = <1>;
  99                 compatible = "w25q32", "jedec,spi-nor";
 100                 reg = <0>; /* Chip select 0 */
 101                 spi-max-frequency = <3000000>;
 102         };
 103 };
 104
 105 &uart0 {
 106         pinctrl-0 = <&uart0_pins>;
 107         pinctrl-names = "default";
 108         status = "okay";
 109 };