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nvme.h: don't use uuid_be
[linux-2.6-block.git] / include / linux / nvme.h
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b60503ba
MW		 1/*
2 * Definitions for the NVM Express interface
8757ad65 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#ifndef _LINUX_NVME_H
16#define _LINUX_NVME_H
17
2812dfe3 18#include <linux/types.h>
eb793e2c
CH		 19
20/* NQN names in commands fields specified one size */
21#define NVMF_NQN_FIELD_LEN 256
22
23/* However the max length of a qualified name is another size */
24#define NVMF_NQN_SIZE 223
25
26#define NVMF_TRSVCID_SIZE 32
27#define NVMF_TRADDR_SIZE 256
28#define NVMF_TSAS_SIZE 256
29
30#define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
31
32#define NVME_RDMA_IP_PORT 4420
33
34enum nvme_subsys_type {
35 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
36 NVME_NQN_NVME = 2, /* NVME type target subsystem */
37};
38
39/* Address Family codes for Discovery Log Page entry ADRFAM field */
40enum {
41 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
42 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
43 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
44 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
45 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
46};
47
48/* Transport Type codes for Discovery Log Page entry TRTYPE field */
49enum {
50 NVMF_TRTYPE_RDMA = 1, /* RDMA */
51 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
52 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
53 NVMF_TRTYPE_MAX,
54};
55
56/* Transport Requirements codes for Discovery Log Page entry TREQ field */
57enum {
58 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
59 NVMF_TREQ_REQUIRED = 1, /* Required */
60 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
61};
62
63/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
64 * RDMA_QPTYPE field
65 */
66enum {
67 NVMF_RDMA_QPTYPE_CONNECTED = 0, /* Reliable Connected */
68 NVMF_RDMA_QPTYPE_DATAGRAM = 1, /* Reliable Datagram */
69};
70
71/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
72 * RDMA_QPTYPE field
73 */
74enum {
75 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 0, /* No Provider Specified */
76 NVMF_RDMA_PRTYPE_IB = 1, /* InfiniBand */
77 NVMF_RDMA_PRTYPE_ROCE = 2, /* InfiniBand RoCE */
78 NVMF_RDMA_PRTYPE_ROCEV2 = 3, /* InfiniBand RoCEV2 */
79 NVMF_RDMA_PRTYPE_IWARP = 4, /* IWARP */
80};
81
82/* RDMA Connection Management Service Type codes for Discovery Log Page
83 * entry TSAS RDMA_CMS field
84 */
85enum {
86 NVMF_RDMA_CMS_RDMA_CM = 0, /* Sockets based enpoint addressing */
87};
88
89#define NVMF_AQ_DEPTH 32
2812dfe3 90
7a67cbea
CH		 91enum {
92 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
93 NVME_REG_VS = 0x0008, /* Version */
94 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
a5b714ad 95 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
7a67cbea
CH		 96 NVME_REG_CC = 0x0014, /* Controller Configuration */
97 NVME_REG_CSTS = 0x001c, /* Controller Status */
98 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
99 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
100 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
a5b714ad 101 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
7a67cbea
CH		 102 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
103 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
b60503ba
MW		 104};
105
a0cadb85 106#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
22605f96 107#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e 108#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
dfbac8c7 109#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
8fc23e03 110#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
1d090624 111#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
22605f96 112
8ffaadf7
JD		 113#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
114#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
115#define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
116#define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
117
118#define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
119#define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
120#define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
121#define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
122#define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
123
69cd27e2
CH		 124/*
125 * Submission and Completion Queue Entry Sizes for the NVM command set.
126 * (In bytes and specified as a power of two (2^n)).
127 */
128#define NVME_NVM_IOSQES 6
129#define NVME_NVM_IOCQES 4
130
b60503ba
MW		 131enum {
132 NVME_CC_ENABLE = 1 << 0,
133 NVME_CC_CSS_NVM = 0 << 4,
134 NVME_CC_MPS_SHIFT = 7,
135 NVME_CC_ARB_RR = 0 << 11,
136 NVME_CC_ARB_WRRU = 1 << 11,
7f53f9d2
MW		 137 NVME_CC_ARB_VS = 7 << 11,
138 NVME_CC_SHN_NONE = 0 << 14,
139 NVME_CC_SHN_NORMAL = 1 << 14,
140 NVME_CC_SHN_ABRUPT = 2 << 14,
1894d8f1 141 NVME_CC_SHN_MASK = 3 << 14,
69cd27e2
CH		 142 NVME_CC_IOSQES = NVME_NVM_IOSQES << 16,
143 NVME_CC_IOCQES = NVME_NVM_IOCQES << 20,
b60503ba
MW		 144 NVME_CSTS_RDY = 1 << 0,
145 NVME_CSTS_CFS = 1 << 1,
dfbac8c7 146 NVME_CSTS_NSSRO = 1 << 4,
b60503ba
MW		 147 NVME_CSTS_SHST_NORMAL = 0 << 2,
148 NVME_CSTS_SHST_OCCUR = 1 << 2,
149 NVME_CSTS_SHST_CMPLT = 2 << 2,
1894d8f1 150 NVME_CSTS_SHST_MASK = 3 << 2,
b60503ba
MW		 151};
152
9d99a8dd
CH		 153struct nvme_id_power_state {
154 __le16 max_power; /* centiwatts */
155 __u8 rsvd2;
156 __u8 flags;
157 __le32 entry_lat; /* microseconds */
158 __le32 exit_lat; /* microseconds */
159 __u8 read_tput;
160 __u8 read_lat;
161 __u8 write_tput;
162 __u8 write_lat;
163 __le16 idle_power;
164 __u8 idle_scale;
165 __u8 rsvd19;
166 __le16 active_power;
167 __u8 active_work_scale;
168 __u8 rsvd23[9];
169};
170
171enum {
172 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
173 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
174};
175
176struct nvme_id_ctrl {
177 __le16 vid;
178 __le16 ssvid;
179 char sn[20];
180 char mn[40];
181 char fr[8];
182 __u8 rab;
183 __u8 ieee[3];
a446c084 184 __u8 cmic;
9d99a8dd 185 __u8 mdts;
08c69640
CH		 186 __le16 cntlid;
187 __le32 ver;
14e974a8
CH		 188 __le32 rtd3r;
189 __le32 rtd3e;
190 __le32 oaes;
eb793e2c
CH		 191 __le32 ctratt;
192 __u8 rsvd100[156];
9d99a8dd
CH		 193 __le16 oacs;
194 __u8 acl;
195 __u8 aerl;
196 __u8 frmw;
197 __u8 lpa;
198 __u8 elpe;
199 __u8 npss;
200 __u8 avscc;
201 __u8 apsta;
202 __le16 wctemp;
203 __le16 cctemp;
a446c084
CH		 204 __le16 mtfa;
205 __le32 hmpre;
206 __le32 hmmin;
207 __u8 tnvmcap[16];
208 __u8 unvmcap[16];
209 __le32 rpmbs;
210 __u8 rsvd316[4];
7b89eae2
SG		 211 __le16 kas;
212 __u8 rsvd322[190];
9d99a8dd
CH		 213 __u8 sqes;
214 __u8 cqes;
eb793e2c 215 __le16 maxcmd;
9d99a8dd
CH		 216 __le32 nn;
217 __le16 oncs;
218 __le16 fuses;
219 __u8 fna;
220 __u8 vwc;
221 __le16 awun;
222 __le16 awupf;
223 __u8 nvscc;
224 __u8 rsvd531;
225 __le16 acwu;
226 __u8 rsvd534[2];
227 __le32 sgls;
eb793e2c
CH		 228 __u8 rsvd540[228];
229 char subnqn[256];
230 __u8 rsvd1024[768];
231 __le32 ioccsz;
232 __le32 iorcsz;
233 __le16 icdoff;
234 __u8 ctrattr;
235 __u8 msdbd;
236 __u8 rsvd1804[244];
9d99a8dd
CH		 237 struct nvme_id_power_state psd[32];
238 __u8 vs[1024];
239};
240
241enum {
242 NVME_CTRL_ONCS_COMPARE = 1 << 0,
243 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
244 NVME_CTRL_ONCS_DSM = 1 << 2,
245 NVME_CTRL_VWC_PRESENT = 1 << 0,
246};
247
248struct nvme_lbaf {
249 __le16 ms;
250 __u8 ds;
251 __u8 rp;
252};
253
254struct nvme_id_ns {
255 __le64 nsze;
256 __le64 ncap;
257 __le64 nuse;
258 __u8 nsfeat;
259 __u8 nlbaf;
260 __u8 flbas;
261 __u8 mc;
262 __u8 dpc;
263 __u8 dps;
264 __u8 nmic;
265 __u8 rescap;
266 __u8 fpi;
267 __u8 rsvd33;
268 __le16 nawun;
269 __le16 nawupf;
270 __le16 nacwu;
271 __le16 nabsn;
272 __le16 nabo;
273 __le16 nabspf;
274 __u16 rsvd46;
a446c084 275 __u8 nvmcap[16];
9d99a8dd
CH		 276 __u8 rsvd64[40];
277 __u8 nguid[16];
278 __u8 eui64[8];
279 struct nvme_lbaf lbaf[16];
280 __u8 rsvd192[192];
281 __u8 vs[3712];
282};
283
284enum {
285 NVME_NS_FEAT_THIN = 1 << 0,
286 NVME_NS_FLBAS_LBA_MASK = 0xf,
287 NVME_NS_FLBAS_META_EXT = 0x10,
288 NVME_LBAF_RP_BEST = 0,
289 NVME_LBAF_RP_BETTER = 1,
290 NVME_LBAF_RP_GOOD = 2,
291 NVME_LBAF_RP_DEGRADED = 3,
292 NVME_NS_DPC_PI_LAST = 1 << 4,
293 NVME_NS_DPC_PI_FIRST = 1 << 3,
294 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
295 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
296 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
297 NVME_NS_DPS_PI_FIRST = 1 << 3,
298 NVME_NS_DPS_PI_MASK = 0x7,
299 NVME_NS_DPS_PI_TYPE1 = 1,
300 NVME_NS_DPS_PI_TYPE2 = 2,
301 NVME_NS_DPS_PI_TYPE3 = 3,
302};
303
304struct nvme_smart_log {
305 __u8 critical_warning;
306 __u8 temperature[2];
307 __u8 avail_spare;
308 __u8 spare_thresh;
309 __u8 percent_used;
310 __u8 rsvd6[26];
311 __u8 data_units_read[16];
312 __u8 data_units_written[16];
313 __u8 host_reads[16];
314 __u8 host_writes[16];
315 __u8 ctrl_busy_time[16];
316 __u8 power_cycles[16];
317 __u8 power_on_hours[16];
318 __u8 unsafe_shutdowns[16];
319 __u8 media_errors[16];
320 __u8 num_err_log_entries[16];
321 __le32 warning_temp_time;
322 __le32 critical_comp_time;
323 __le16 temp_sensor[8];
324 __u8 rsvd216[296];
325};
326
327enum {
328 NVME_SMART_CRIT_SPARE = 1 << 0,
329 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
330 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
331 NVME_SMART_CRIT_MEDIA = 1 << 3,
332 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
333};
334
335enum {
336 NVME_AER_NOTICE_NS_CHANGED = 0x0002,
337};
338
339struct nvme_lba_range_type {
340 __u8 type;
341 __u8 attributes;
342 __u8 rsvd2[14];
343 __u64 slba;
344 __u64 nlb;
345 __u8 guid[16];
346 __u8 rsvd48[16];
347};
348
349enum {
350 NVME_LBART_TYPE_FS = 0x01,
351 NVME_LBART_TYPE_RAID = 0x02,
352 NVME_LBART_TYPE_CACHE = 0x03,
353 NVME_LBART_TYPE_SWAP = 0x04,
354
355 NVME_LBART_ATTRIB_TEMP = 1 << 0,
356 NVME_LBART_ATTRIB_HIDE = 1 << 1,
357};
358
359struct nvme_reservation_status {
360 __le32 gen;
361 __u8 rtype;
362 __u8 regctl[2];
363 __u8 resv5[2];
364 __u8 ptpls;
365 __u8 resv10[13];
366 struct {
367 __le16 cntlid;
368 __u8 rcsts;
369 __u8 resv3[5];
370 __le64 hostid;
371 __le64 rkey;
372 } regctl_ds[];
373};
374
79f370ea
CH		 375enum nvme_async_event_type {
376 NVME_AER_TYPE_ERROR = 0,
377 NVME_AER_TYPE_SMART = 1,
378 NVME_AER_TYPE_NOTICE = 2,
379};
380
9d99a8dd
CH		 381/* I/O commands */
382
383enum nvme_opcode {
384 nvme_cmd_flush = 0x00,
385 nvme_cmd_write = 0x01,
386 nvme_cmd_read = 0x02,
387 nvme_cmd_write_uncor = 0x04,
388 nvme_cmd_compare = 0x05,
389 nvme_cmd_write_zeroes = 0x08,
390 nvme_cmd_dsm = 0x09,
391 nvme_cmd_resv_register = 0x0d,
392 nvme_cmd_resv_report = 0x0e,
393 nvme_cmd_resv_acquire = 0x11,
394 nvme_cmd_resv_release = 0x15,
395};
396
eb793e2c
CH		 397/*
398 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
399 *
400 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
401 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
402 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
403 * request subtype
404 */
405enum {
406 NVME_SGL_FMT_ADDRESS = 0x00,
407 NVME_SGL_FMT_OFFSET = 0x01,
408 NVME_SGL_FMT_INVALIDATE = 0x0f,
409};
410
411/*
412 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
413 *
414 * For struct nvme_sgl_desc:
415 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
416 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
417 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
418 *
419 * For struct nvme_keyed_sgl_desc:
420 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
421 */
422enum {
423 NVME_SGL_FMT_DATA_DESC = 0x00,
424 NVME_SGL_FMT_SEG_DESC = 0x02,
425 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
426 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
427};
428
429struct nvme_sgl_desc {
430 __le64 addr;
431 __le32 length;
432 __u8 rsvd[3];
433 __u8 type;
434};
435
436struct nvme_keyed_sgl_desc {
437 __le64 addr;
438 __u8 length[3];
439 __u8 key[4];
440 __u8 type;
441};
442
443union nvme_data_ptr {
444 struct {
445 __le64 prp1;
446 __le64 prp2;
447 };
448 struct nvme_sgl_desc sgl;
449 struct nvme_keyed_sgl_desc ksgl;
450};
451
3972be23
JS		 452/*
453 * Lowest two bits of our flags field (FUSE field in the spec):
454 *
455 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
456 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
457 *
458 * Highest two bits in our flags field (PSDT field in the spec):
459 *
460 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
461 * If used, MPTR contains addr of single physical buffer (byte aligned).
462 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
463 * If used, MPTR contains an address of an SGL segment containing
464 * exactly 1 SGL descriptor (qword aligned).
465 */
466enum {
467 NVME_CMD_FUSE_FIRST = (1 << 0),
468 NVME_CMD_FUSE_SECOND = (1 << 1),
469
470 NVME_CMD_SGL_METABUF = (1 << 6),
471 NVME_CMD_SGL_METASEG = (1 << 7),
472 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
473};
474
9d99a8dd
CH		 475struct nvme_common_command {
476 __u8 opcode;
477 __u8 flags;
478 __u16 command_id;
479 __le32 nsid;
480 __le32 cdw2[2];
481 __le64 metadata;
eb793e2c 482 union nvme_data_ptr dptr;
9d99a8dd
CH		 483 __le32 cdw10[6];
484};
485
486struct nvme_rw_command {
487 __u8 opcode;
488 __u8 flags;
489 __u16 command_id;
490 __le32 nsid;
491 __u64 rsvd2;
492 __le64 metadata;
eb793e2c 493 union nvme_data_ptr dptr;
9d99a8dd
CH		 494 __le64 slba;
495 __le16 length;
496 __le16 control;
497 __le32 dsmgmt;
498 __le32 reftag;
499 __le16 apptag;
500 __le16 appmask;
501};
502
503enum {
504 NVME_RW_LR = 1 << 15,
505 NVME_RW_FUA = 1 << 14,
506 NVME_RW_DSM_FREQ_UNSPEC = 0,
507 NVME_RW_DSM_FREQ_TYPICAL = 1,
508 NVME_RW_DSM_FREQ_RARE = 2,
509 NVME_RW_DSM_FREQ_READS = 3,
510 NVME_RW_DSM_FREQ_WRITES = 4,
511 NVME_RW_DSM_FREQ_RW = 5,
512 NVME_RW_DSM_FREQ_ONCE = 6,
513 NVME_RW_DSM_FREQ_PREFETCH = 7,
514 NVME_RW_DSM_FREQ_TEMP = 8,
515 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
516 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
517 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
518 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
519 NVME_RW_DSM_SEQ_REQ = 1 << 6,
520 NVME_RW_DSM_COMPRESSED = 1 << 7,
521 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
522 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
523 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
524 NVME_RW_PRINFO_PRACT = 1 << 13,
525};
526
527struct nvme_dsm_cmd {
528 __u8 opcode;
529 __u8 flags;
530 __u16 command_id;
531 __le32 nsid;
532 __u64 rsvd2[2];
eb793e2c 533 union nvme_data_ptr dptr;
9d99a8dd
CH		 534 __le32 nr;
535 __le32 attributes;
536 __u32 rsvd12[4];
537};
538
539enum {
540 NVME_DSMGMT_IDR = 1 << 0,
541 NVME_DSMGMT_IDW = 1 << 1,
542 NVME_DSMGMT_AD = 1 << 2,
543};
544
545struct nvme_dsm_range {
546 __le32 cattr;
547 __le32 nlb;
548 __le64 slba;
549};
550
551/* Admin commands */
552
553enum nvme_admin_opcode {
554 nvme_admin_delete_sq = 0x00,
555 nvme_admin_create_sq = 0x01,
556 nvme_admin_get_log_page = 0x02,
557 nvme_admin_delete_cq = 0x04,
558 nvme_admin_create_cq = 0x05,
559 nvme_admin_identify = 0x06,
560 nvme_admin_abort_cmd = 0x08,
561 nvme_admin_set_features = 0x09,
562 nvme_admin_get_features = 0x0a,
563 nvme_admin_async_event = 0x0c,
a446c084 564 nvme_admin_ns_mgmt = 0x0d,
9d99a8dd
CH		 565 nvme_admin_activate_fw = 0x10,
566 nvme_admin_download_fw = 0x11,
a446c084 567 nvme_admin_ns_attach = 0x15,
7b89eae2 568 nvme_admin_keep_alive = 0x18,
9d99a8dd
CH		 569 nvme_admin_format_nvm = 0x80,
570 nvme_admin_security_send = 0x81,
571 nvme_admin_security_recv = 0x82,
572};
573
574enum {
575 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
576 NVME_CQ_IRQ_ENABLED = (1 << 1),
577 NVME_SQ_PRIO_URGENT = (0 << 1),
578 NVME_SQ_PRIO_HIGH = (1 << 1),
579 NVME_SQ_PRIO_MEDIUM = (2 << 1),
580 NVME_SQ_PRIO_LOW = (3 << 1),
581 NVME_FEAT_ARBITRATION = 0x01,
582 NVME_FEAT_POWER_MGMT = 0x02,
583 NVME_FEAT_LBA_RANGE = 0x03,
584 NVME_FEAT_TEMP_THRESH = 0x04,
585 NVME_FEAT_ERR_RECOVERY = 0x05,
586 NVME_FEAT_VOLATILE_WC = 0x06,
587 NVME_FEAT_NUM_QUEUES = 0x07,
588 NVME_FEAT_IRQ_COALESCE = 0x08,
589 NVME_FEAT_IRQ_CONFIG = 0x09,
590 NVME_FEAT_WRITE_ATOMIC = 0x0a,
591 NVME_FEAT_ASYNC_EVENT = 0x0b,
592 NVME_FEAT_AUTO_PST = 0x0c,
a446c084 593 NVME_FEAT_HOST_MEM_BUF = 0x0d,
7b89eae2 594 NVME_FEAT_KATO = 0x0f,
9d99a8dd
CH		 595 NVME_FEAT_SW_PROGRESS = 0x80,
596 NVME_FEAT_HOST_ID = 0x81,
597 NVME_FEAT_RESV_MASK = 0x82,
598 NVME_FEAT_RESV_PERSIST = 0x83,
599 NVME_LOG_ERROR = 0x01,
600 NVME_LOG_SMART = 0x02,
601 NVME_LOG_FW_SLOT = 0x03,
eb793e2c 602 NVME_LOG_DISC = 0x70,
9d99a8dd
CH		 603 NVME_LOG_RESERVATION = 0x80,
604 NVME_FWACT_REPL = (0 << 3),
605 NVME_FWACT_REPL_ACTV = (1 << 3),
606 NVME_FWACT_ACTV = (2 << 3),
607};
608
609struct nvme_identify {
610 __u8 opcode;
611 __u8 flags;
612 __u16 command_id;
613 __le32 nsid;
614 __u64 rsvd2[2];
eb793e2c 615 union nvme_data_ptr dptr;
9d99a8dd
CH		 616 __le32 cns;
617 __u32 rsvd11[5];
618};
619
620struct nvme_features {
621 __u8 opcode;
622 __u8 flags;
623 __u16 command_id;
624 __le32 nsid;
625 __u64 rsvd2[2];
eb793e2c 626 union nvme_data_ptr dptr;
9d99a8dd
CH		 627 __le32 fid;
628 __le32 dword11;
629 __u32 rsvd12[4];
630};
631
632struct nvme_create_cq {
633 __u8 opcode;
634 __u8 flags;
635 __u16 command_id;
636 __u32 rsvd1[5];
637 __le64 prp1;
638 __u64 rsvd8;
639 __le16 cqid;
640 __le16 qsize;
641 __le16 cq_flags;
642 __le16 irq_vector;
643 __u32 rsvd12[4];
644};
645
646struct nvme_create_sq {
647 __u8 opcode;
648 __u8 flags;
649 __u16 command_id;
650 __u32 rsvd1[5];
651 __le64 prp1;
652 __u64 rsvd8;
653 __le16 sqid;
654 __le16 qsize;
655 __le16 sq_flags;
656 __le16 cqid;
657 __u32 rsvd12[4];
658};
659
660struct nvme_delete_queue {
661 __u8 opcode;
662 __u8 flags;
663 __u16 command_id;
664 __u32 rsvd1[9];
665 __le16 qid;
666 __u16 rsvd10;
667 __u32 rsvd11[5];
668};
669
670struct nvme_abort_cmd {
671 __u8 opcode;
672 __u8 flags;
673 __u16 command_id;
674 __u32 rsvd1[9];
675 __le16 sqid;
676 __u16 cid;
677 __u32 rsvd11[5];
678};
679
680struct nvme_download_firmware {
681 __u8 opcode;
682 __u8 flags;
683 __u16 command_id;
684 __u32 rsvd1[5];
eb793e2c 685 union nvme_data_ptr dptr;
9d99a8dd
CH		 686 __le32 numd;
687 __le32 offset;
688 __u32 rsvd12[4];
689};
690
691struct nvme_format_cmd {
692 __u8 opcode;
693 __u8 flags;
694 __u16 command_id;
695 __le32 nsid;
696 __u64 rsvd2[4];
697 __le32 cdw10;
698 __u32 rsvd11[5];
699};
700
725b3588
AB		 701struct nvme_get_log_page_command {
702 __u8 opcode;
703 __u8 flags;
704 __u16 command_id;
705 __le32 nsid;
706 __u64 rsvd2[2];
eb793e2c 707 union nvme_data_ptr dptr;
725b3588
AB		 708 __u8 lid;
709 __u8 rsvd10;
710 __le16 numdl;
711 __le16 numdu;
712 __u16 rsvd11;
713 __le32 lpol;
714 __le32 lpou;
715 __u32 rsvd14[2];
716};
717
eb793e2c
CH		 718/*
719 * Fabrics subcommands.
720 */
721enum nvmf_fabrics_opcode {
722 nvme_fabrics_command = 0x7f,
723};
724
725enum nvmf_capsule_command {
726 nvme_fabrics_type_property_set = 0x00,
727 nvme_fabrics_type_connect = 0x01,
728 nvme_fabrics_type_property_get = 0x04,
729};
730
731struct nvmf_common_command {
732 __u8 opcode;
733 __u8 resv1;
734 __u16 command_id;
735 __u8 fctype;
736 __u8 resv2[35];
737 __u8 ts[24];
738};
739
740/*
741 * The legal cntlid range a NVMe Target will provide.
742 * Note that cntlid of value 0 is considered illegal in the fabrics world.
743 * Devices based on earlier specs did not have the subsystem concept;
744 * therefore, those devices had their cntlid value set to 0 as a result.
745 */
746#define NVME_CNTLID_MIN 1
747#define NVME_CNTLID_MAX 0xffef
748#define NVME_CNTLID_DYNAMIC 0xffff
749
750#define MAX_DISC_LOGS 255
751
752/* Discovery log page entry */
753struct nvmf_disc_rsp_page_entry {
754 __u8 trtype;
755 __u8 adrfam;
a446c084 756 __u8 subtype;
eb793e2c
CH		 757 __u8 treq;
758 __le16 portid;
759 __le16 cntlid;
760 __le16 asqsz;
761 __u8 resv8[22];
762 char trsvcid[NVMF_TRSVCID_SIZE];
763 __u8 resv64[192];
764 char subnqn[NVMF_NQN_FIELD_LEN];
765 char traddr[NVMF_TRADDR_SIZE];
766 union tsas {
767 char common[NVMF_TSAS_SIZE];
768 struct rdma {
769 __u8 qptype;
770 __u8 prtype;
771 __u8 cms;
772 __u8 resv3[5];
773 __u16 pkey;
774 __u8 resv10[246];
775 } rdma;
776 } tsas;
777};
778
779/* Discovery log page header */
780struct nvmf_disc_rsp_page_hdr {
781 __le64 genctr;
782 __le64 numrec;
783 __le16 recfmt;
784 __u8 resv14[1006];
785 struct nvmf_disc_rsp_page_entry entries[0];
786};
787
788struct nvmf_connect_command {
789 __u8 opcode;
790 __u8 resv1;
791 __u16 command_id;
792 __u8 fctype;
793 __u8 resv2[19];
794 union nvme_data_ptr dptr;
795 __le16 recfmt;
796 __le16 qid;
797 __le16 sqsize;
798 __u8 cattr;
799 __u8 resv3;
800 __le32 kato;
801 __u8 resv4[12];
802};
803
804struct nvmf_connect_data {
8d63687a 805 __u8 hostid[16];
eb793e2c
CH		 806 __le16 cntlid;
807 char resv4[238];
808 char subsysnqn[NVMF_NQN_FIELD_LEN];
809 char hostnqn[NVMF_NQN_FIELD_LEN];
810 char resv5[256];
811};
812
813struct nvmf_property_set_command {
814 __u8 opcode;
815 __u8 resv1;
816 __u16 command_id;
817 __u8 fctype;
818 __u8 resv2[35];
819 __u8 attrib;
820 __u8 resv3[3];
821 __le32 offset;
822 __le64 value;
823 __u8 resv4[8];
824};
825
826struct nvmf_property_get_command {
827 __u8 opcode;
828 __u8 resv1;
829 __u16 command_id;
830 __u8 fctype;
831 __u8 resv2[35];
832 __u8 attrib;
833 __u8 resv3[3];
834 __le32 offset;
835 __u8 resv4[16];
836};
837
9d99a8dd
CH		 838struct nvme_command {
839 union {
840 struct nvme_common_command common;
841 struct nvme_rw_command rw;
842 struct nvme_identify identify;
843 struct nvme_features features;
844 struct nvme_create_cq create_cq;
845 struct nvme_create_sq create_sq;
846 struct nvme_delete_queue delete_queue;
847 struct nvme_download_firmware dlfw;
848 struct nvme_format_cmd format;
849 struct nvme_dsm_cmd dsm;
850 struct nvme_abort_cmd abort;
725b3588 851 struct nvme_get_log_page_command get_log_page;
eb793e2c
CH		 852 struct nvmf_common_command fabrics;
853 struct nvmf_connect_command connect;
854 struct nvmf_property_set_command prop_set;
855 struct nvmf_property_get_command prop_get;
9d99a8dd
CH		 856 };
857};
858
7a5abb4b
CH		 859static inline bool nvme_is_write(struct nvme_command *cmd)
860{
eb793e2c
CH		 861 /*
862 * What a mess...
863 *
864 * Why can't we simply have a Fabrics In and Fabrics out command?
865 */
866 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
867 return cmd->fabrics.opcode & 1;
7a5abb4b
CH		 868 return cmd->common.opcode & 1;
869}
870
9d99a8dd 871enum {
eb793e2c
CH		 872 /*
873 * Generic Command Status:
874 */
9d99a8dd
CH		 875 NVME_SC_SUCCESS = 0x0,
876 NVME_SC_INVALID_OPCODE = 0x1,
877 NVME_SC_INVALID_FIELD = 0x2,
878 NVME_SC_CMDID_CONFLICT = 0x3,
879 NVME_SC_DATA_XFER_ERROR = 0x4,
880 NVME_SC_POWER_LOSS = 0x5,
881 NVME_SC_INTERNAL = 0x6,
882 NVME_SC_ABORT_REQ = 0x7,
883 NVME_SC_ABORT_QUEUE = 0x8,
884 NVME_SC_FUSED_FAIL = 0x9,
885 NVME_SC_FUSED_MISSING = 0xa,
886 NVME_SC_INVALID_NS = 0xb,
887 NVME_SC_CMD_SEQ_ERROR = 0xc,
888 NVME_SC_SGL_INVALID_LAST = 0xd,
889 NVME_SC_SGL_INVALID_COUNT = 0xe,
890 NVME_SC_SGL_INVALID_DATA = 0xf,
891 NVME_SC_SGL_INVALID_METADATA = 0x10,
892 NVME_SC_SGL_INVALID_TYPE = 0x11,
eb793e2c
CH		 893
894 NVME_SC_SGL_INVALID_OFFSET = 0x16,
895 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
896
9d99a8dd
CH		 897 NVME_SC_LBA_RANGE = 0x80,
898 NVME_SC_CAP_EXCEEDED = 0x81,
899 NVME_SC_NS_NOT_READY = 0x82,
900 NVME_SC_RESERVATION_CONFLICT = 0x83,
eb793e2c
CH		 901
902 /*
903 * Command Specific Status:
904 */
9d99a8dd
CH		 905 NVME_SC_CQ_INVALID = 0x100,
906 NVME_SC_QID_INVALID = 0x101,
907 NVME_SC_QUEUE_SIZE = 0x102,
908 NVME_SC_ABORT_LIMIT = 0x103,
909 NVME_SC_ABORT_MISSING = 0x104,
910 NVME_SC_ASYNC_LIMIT = 0x105,
911 NVME_SC_FIRMWARE_SLOT = 0x106,
912 NVME_SC_FIRMWARE_IMAGE = 0x107,
913 NVME_SC_INVALID_VECTOR = 0x108,
914 NVME_SC_INVALID_LOG_PAGE = 0x109,
915 NVME_SC_INVALID_FORMAT = 0x10a,
a446c084 916 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
9d99a8dd
CH		 917 NVME_SC_INVALID_QUEUE = 0x10c,
918 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
919 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
920 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
a446c084
CH		 921 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
922 NVME_SC_FW_NEEDS_RESET = 0x111,
923 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
924 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
925 NVME_SC_OVERLAPPING_RANGE = 0x114,
926 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
927 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
928 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
929 NVME_SC_NS_IS_PRIVATE = 0x119,
930 NVME_SC_NS_NOT_ATTACHED = 0x11a,
931 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
932 NVME_SC_CTRL_LIST_INVALID = 0x11c,
eb793e2c
CH		 933
934 /*
935 * I/O Command Set Specific - NVM commands:
936 */
9d99a8dd
CH		 937 NVME_SC_BAD_ATTRIBUTES = 0x180,
938 NVME_SC_INVALID_PI = 0x181,
939 NVME_SC_READ_ONLY = 0x182,
eb793e2c
CH		 940
941 /*
942 * I/O Command Set Specific - Fabrics commands:
943 */
944 NVME_SC_CONNECT_FORMAT = 0x180,
945 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
946 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
947 NVME_SC_CONNECT_RESTART_DISC = 0x183,
948 NVME_SC_CONNECT_INVALID_HOST = 0x184,
949
950 NVME_SC_DISCOVERY_RESTART = 0x190,
951 NVME_SC_AUTH_REQUIRED = 0x191,
952
953 /*
954 * Media and Data Integrity Errors:
955 */
9d99a8dd
CH		 956 NVME_SC_WRITE_FAULT = 0x280,
957 NVME_SC_READ_ERROR = 0x281,
958 NVME_SC_GUARD_CHECK = 0x282,
959 NVME_SC_APPTAG_CHECK = 0x283,
960 NVME_SC_REFTAG_CHECK = 0x284,
961 NVME_SC_COMPARE_FAILED = 0x285,
962 NVME_SC_ACCESS_DENIED = 0x286,
a446c084 963 NVME_SC_UNWRITTEN_BLOCK = 0x287,
eb793e2c 964
9d99a8dd
CH		 965 NVME_SC_DNR = 0x4000,
966};
967
968struct nvme_completion {
eb793e2c
CH		 969 /*
970 * Used by Admin and Fabrics commands to return data:
971 */
972 union {
973 __le16 result16;
974 __le32 result;
975 __le64 result64;
976 };
9d99a8dd
CH		 977 __le16 sq_head; /* how much of this queue may be reclaimed */
978 __le16 sq_id; /* submission queue that generated this entry */
979 __u16 command_id; /* of the command which completed */
980 __le16 status; /* did the command fail, and if so, why? */
981};
982
8ef2074d
GKB		 983#define NVME_VS(major, minor, tertiary) \
984 (((major) << 16) | ((minor) << 8) | (tertiary))
9d99a8dd 985
b60503ba 986#endif /* _LINUX_NVME_H */
Linux 6.x block layer and io_uring tree(s)