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scsi: qla2xxx: Enable type checking for the SRB free and done callback functions
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
726b8548 33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
1da177e4 34static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 35
4d4df193
HK		 36static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
37static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 38static int qla25xx_init_queues(struct qla_hw_data *);
a5d42f4c 39static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *);
726b8548
QT		 40static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *,
41 struct event_arg *);
a5d42f4c
DG		 42static void qla24xx_handle_prli_done_event(struct scsi_qla_host *,
43 struct event_arg *);
a4239945 44static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *);
4d4df193 45
ac280b67
AV		 46/* SRB Extensions ---------------------------------------------------------- */
47
9ba56b95 48void
8e5f4ba0 49qla2x00_sp_timeout(struct timer_list *t)
ac280b67 50{
8e5f4ba0 51 srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer);
4916392b 52 struct srb_iocb *iocb;
ac280b67
AV		 53 struct req_que *req;
54 unsigned long flags;
bcc71cc3 55 struct qla_hw_data *ha = sp->vha->hw;
ac280b67 56
ef801f07 57 WARN_ON_ONCE(irqs_disabled());
bcc71cc3 58 spin_lock_irqsave(&ha->hardware_lock, flags);
f6145e86 59 req = sp->qpair->req;
ac280b67 60 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 61 iocb = &sp->u.iocb_cmd;
bcc71cc3 62 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4916392b 63 iocb->timeout(sp);
ac280b67
AV		 64}
65
6c18a43e 66void qla2x00_sp_free(srb_t *sp)
ac280b67 67{
9ba56b95 68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
ac280b67 69
4d97cc53 70 del_timer(&iocb->timer);
25ff6af1 71 qla2x00_rel_sp(sp);
ac280b67
AV		 72}
73
ac280b67
AV		 74/* Asynchronous Login/Logout Routines -------------------------------------- */
75
a9b6f722 76unsigned long
5b91490e
AV		 77qla2x00_get_async_timeout(struct scsi_qla_host *vha)
78{
79 unsigned long tmo;
80 struct qla_hw_data *ha = vha->hw;
81
82 /* Firmware should use switch negotiated r_a_tov for timeout. */
83 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 84 if (IS_QLAFX00(ha)) {
85 tmo = FX00_DEF_RATOV * 2;
86 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 87 /*
88 * Except for earlier ISPs where the timeout is seeded from the
89 * initialization control block.
90 */
91 tmo = ha->login_timeout;
92 }
93 return tmo;
94}
ac280b67 95
1956eee5
BVA		 96static void qla24xx_abort_iocb_timeout(void *data)
97{
98 srb_t *sp = data;
99 struct srb_iocb *abt = &sp->u.iocb_cmd;
0c6df590
QT		 100 struct qla_qpair *qpair = sp->qpair;
101 u32 handle;
102 unsigned long flags;
103
104 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
105 for (handle = 1; handle < qpair->req->num_outstanding_cmds; handle++) {
106 /* removing the abort */
107 if (qpair->req->outstanding_cmds[handle] == sp) {
108 qpair->req->outstanding_cmds[handle] = NULL;
109 break;
110 }
111 }
112 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1956eee5
BVA		 113
114 abt->u.abt.comp_status = CS_TIMEOUT;
0c6df590 115 sp->done(sp, QLA_OS_TIMER_EXPIRED);
1956eee5
BVA		 116}
117
6c18a43e 118static void qla24xx_abort_sp_done(srb_t *sp, int res)
1956eee5 119{
1956eee5
BVA		 120 struct srb_iocb *abt = &sp->u.iocb_cmd;
121
f1333c48
BVA		 122 del_timer(&sp->u.iocb_cmd.timer);
123 if (sp->flags & SRB_WAKEUP_ON_COMP)
124 complete(&abt->u.abt.comp);
125 else
126 sp->free(sp);
1956eee5
BVA		 127}
128
129static int qla24xx_async_abort_cmd(srb_t *cmd_sp, bool wait)
130{
131 scsi_qla_host_t *vha = cmd_sp->vha;
132 struct srb_iocb *abt_iocb;
133 srb_t *sp;
134 int rval = QLA_FUNCTION_FAILED;
135
136 sp = qla2xxx_get_qpair_sp(cmd_sp->vha, cmd_sp->qpair, cmd_sp->fcport,
137 GFP_ATOMIC);
138 if (!sp)
139 goto done;
140
141 abt_iocb = &sp->u.iocb_cmd;
142 sp->type = SRB_ABT_CMD;
143 sp->name = "abort";
144 sp->qpair = cmd_sp->qpair;
145 if (wait)
146 sp->flags = SRB_WAKEUP_ON_COMP;
147
148 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
149 init_completion(&abt_iocb->u.abt.comp);
150 /* FW can send 2 x ABTS's timeout/20s */
151 qla2x00_init_timer(sp, 42);
152
153 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
154 abt_iocb->u.abt.req_que_no = cpu_to_le16(cmd_sp->qpair->req->id);
155
156 sp->done = qla24xx_abort_sp_done;
157
158 ql_dbg(ql_dbg_async, vha, 0x507c,
159 "Abort command issued - hdl=%x, type=%x\n", cmd_sp->handle,
160 cmd_sp->type);
161
162 rval = qla2x00_start_sp(sp);
163 if (rval != QLA_SUCCESS)
164 goto done_free_sp;
165
166 if (wait) {
167 wait_for_completion(&abt_iocb->u.abt.comp);
168 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
169 QLA_SUCCESS : QLA_FUNCTION_FAILED;
170 } else {
171 goto done;
172 }
173
174done_free_sp:
175 sp->free(sp);
176done:
177 return rval;
178}
179
726b8548 180void
9ba56b95 181qla2x00_async_iocb_timeout(void *data)
ac280b67 182{
25ff6af1 183 srb_t *sp = data;
ac280b67 184 fc_port_t *fcport = sp->fcport;
726b8548 185 struct srb_iocb *lio = &sp->u.iocb_cmd;
f6145e86
QT		 186 int rc, h;
187 unsigned long flags;
ac280b67 188
5c25d451
QT		 189 if (fcport) {
190 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
191 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
192 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
193
6d674927 194 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
5c25d451
QT		 195 } else {
196 pr_info("Async-%s timeout - hdl=%x.\n",
197 sp->name, sp->handle);
198 }
726b8548
QT		 199
200 switch (sp->type) {
201 case SRB_LOGIN_CMD:
f6145e86
QT		 202 rc = qla24xx_async_abort_cmd(sp, false);
203 if (rc) {
204 /* Retry as needed. */
205 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
206 lio->u.logio.data[1] =
207 lio->u.logio.flags & SRB_LOGIN_RETRIED ?
208 QLA_LOGIO_LOGIN_RETRIED : 0;
209 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
210 for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
211 h++) {
212 if (sp->qpair->req->outstanding_cmds[h] ==
213 sp) {
214 sp->qpair->req->outstanding_cmds[h] =
215 NULL;
216 break;
217 }
218 }
219 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
220 sp->done(sp, QLA_FUNCTION_TIMEOUT);
221 }
726b8548
QT		 222 break;
223 case SRB_LOGOUT_CMD:
726b8548
QT		 224 case SRB_CT_PTHRU_CMD:
225 case SRB_MB_IOCB:
226 case SRB_NACK_PLOGI:
227 case SRB_NACK_PRLI:
228 case SRB_NACK_LOGO:
2853192e 229 case SRB_CTRL_VP:
f6145e86
QT		 230 rc = qla24xx_async_abort_cmd(sp, false);
231 if (rc) {
232 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
233 for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
234 h++) {
235 if (sp->qpair->req->outstanding_cmds[h] ==
236 sp) {
237 sp->qpair->req->outstanding_cmds[h] =
238 NULL;
239 break;
240 }
241 }
242 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
243 sp->done(sp, QLA_FUNCTION_TIMEOUT);
244 }
726b8548 245 break;
6ac52608 246 }
ac280b67
AV		 247}
248
6c18a43e 249static void qla2x00_async_login_sp_done(srb_t *sp, int res)
99b0bec7 250{
25ff6af1 251 struct scsi_qla_host *vha = sp->vha;
9ba56b95 252 struct srb_iocb *lio = &sp->u.iocb_cmd;
726b8548 253 struct event_arg ea;
9ba56b95 254
83548fe2 255 ql_dbg(ql_dbg_disc, vha, 0x20dd,
25ff6af1 256 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
726b8548 257
6d674927
QT		 258 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
259
726b8548
QT		 260 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
261 memset(&ea, 0, sizeof(ea));
262 ea.event = FCME_PLOGI_DONE;
263 ea.fcport = sp->fcport;
264 ea.data[0] = lio->u.logio.data[0];
265 ea.data[1] = lio->u.logio.data[1];
266 ea.iop[0] = lio->u.logio.iop[0];
267 ea.iop[1] = lio->u.logio.iop[1];
268 ea.sp = sp;
269 qla2x00_fcport_event_handler(vha, &ea);
270 }
9ba56b95 271
25ff6af1 272 sp->free(sp);
99b0bec7
AV		 273}
274
48acad09
QT		 275static inline bool
276fcport_is_smaller(fc_port_t *fcport)
277{
278 if (wwn_to_u64(fcport->port_name) <
279 wwn_to_u64(fcport->vha->port_name))
280 return true;
281 else
282 return false;
283}
284
285static inline bool
286fcport_is_bigger(fc_port_t *fcport)
287{
288 return !fcport_is_smaller(fcport);
289}
290
ac280b67
AV		 291int
292qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
293 uint16_t *data)
294{
ac280b67 295 srb_t *sp;
4916392b 296 struct srb_iocb *lio;
726b8548
QT		 297 int rval = QLA_FUNCTION_FAILED;
298
8b5292bc
QT		 299 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) ||
300 fcport->loop_id == FC_NO_LOOP_ID) {
301 ql_log(ql_log_warn, vha, 0xffff,
302 "%s: %8phC - not sending command.\n",
303 __func__, fcport->port_name);
304 return rval;
305 }
726b8548 306
9ba56b95 307 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 308 if (!sp)
309 goto done;
310
726b8548
QT		 311 fcport->flags |= FCF_ASYNC_SENT;
312 fcport->logout_completed = 0;
313
a4239945 314 fcport->disc_state = DSC_LOGIN_PEND;
9ba56b95
GM		 315 sp->type = SRB_LOGIN_CMD;
316 sp->name = "login";
a4239945
QT		 317 sp->gen1 = fcport->rscn_gen;
318 sp->gen2 = fcport->login_gen;
9ba56b95
GM		 319
320 lio = &sp->u.iocb_cmd;
3822263e 321 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 322 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
323
9ba56b95 324 sp->done = qla2x00_async_login_sp_done;
835aa4f2 325 if (N2N_TOPO(fcport->vha->hw) && fcport_is_bigger(fcport))
48acad09 326 lio->u.logio.flags |= SRB_LOGIN_PRLI_ONLY;
835aa4f2 327 else
48acad09 328 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
a5d42f4c 329
835aa4f2
GM		 330 if (fcport->fc4f_nvme)
331 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI;
a5d42f4c 332
9fe278f4
GM		 333 ql_dbg(ql_dbg_disc, vha, 0x2072,
334 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
335 "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
336 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
337 fcport->login_retry);
338
ac280b67 339 rval = qla2x00_start_sp(sp);
080c9517 340 if (rval != QLA_SUCCESS) {
080c9517
CD		 341 fcport->flags |= FCF_LOGIN_NEEDED;
342 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 343 goto done_free_sp;
080c9517 344 }
ac280b67 345
ac280b67
AV		 346 return rval;
347
348done_free_sp:
25ff6af1 349 sp->free(sp);
726b8548 350 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 351done:
fa83e658 352 fcport->flags &= ~FCF_ASYNC_ACTIVE;
ac280b67
AV		 353 return rval;
354}
355
6c18a43e 356static void qla2x00_async_logout_sp_done(srb_t *sp, int res)
99b0bec7 357{
6d674927 358 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
eaf75d18
QT		 359 sp->fcport->login_gen++;
360 qlt_logo_completion_handler(sp->fcport, res);
25ff6af1 361 sp->free(sp);
99b0bec7
AV		 362}
363
ac280b67
AV		 364int
365qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
366{
ac280b67 367 srb_t *sp;
4916392b 368 struct srb_iocb *lio;
3dbec59b
QT		 369 int rval = QLA_FUNCTION_FAILED;
370
726b8548 371 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 372 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 373 if (!sp)
374 goto done;
375
9ba56b95
GM		 376 sp->type = SRB_LOGOUT_CMD;
377 sp->name = "logout";
9ba56b95
GM		 378
379 lio = &sp->u.iocb_cmd;
3822263e 380 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 381 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
382
9ba56b95 383 sp->done = qla2x00_async_logout_sp_done;
ac280b67 384
7c3df132 385 ql_dbg(ql_dbg_disc, vha, 0x2070,
726b8548 386 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
cfb0919c 387 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
726b8548
QT		 388 fcport->d_id.b.area, fcport->d_id.b.al_pa,
389 fcport->port_name);
9fe278f4
GM		 390
391 rval = qla2x00_start_sp(sp);
392 if (rval != QLA_SUCCESS)
393 goto done_free_sp;
ac280b67
AV		 394 return rval;
395
396done_free_sp:
25ff6af1 397 sp->free(sp);
ac280b67 398done:
fa83e658 399 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
ac280b67
AV		 400 return rval;
401}
11aea16a
QT		 402
403void
404qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport,
405 uint16_t *data)
406{
fa83e658 407 fcport->flags &= ~FCF_ASYNC_ACTIVE;
11aea16a
QT		 408 /* Don't re-login in target mode */
409 if (!fcport->tgt_session)
410 qla2x00_mark_device_lost(vha, fcport, 1, 0);
411 qlt_logo_completion_handler(fcport, data[0]);
412}
413
6c18a43e 414static void qla2x00_async_prlo_sp_done(srb_t *sp, int res)
11aea16a 415{
11aea16a
QT		 416 struct srb_iocb *lio = &sp->u.iocb_cmd;
417 struct scsi_qla_host *vha = sp->vha;
418
fa83e658 419 sp->fcport->flags &= ~FCF_ASYNC_ACTIVE;
11aea16a
QT		 420 if (!test_bit(UNLOADING, &vha->dpc_flags))
421 qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport,
422 lio->u.logio.data);
423 sp->free(sp);
424}
425
426int
427qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport)
428{
429 srb_t *sp;
430 struct srb_iocb *lio;
431 int rval;
432
433 rval = QLA_FUNCTION_FAILED;
434 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
435 if (!sp)
436 goto done;
437
438 sp->type = SRB_PRLO_CMD;
439 sp->name = "prlo";
11aea16a
QT		 440
441 lio = &sp->u.iocb_cmd;
442 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 443 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
444
11aea16a 445 sp->done = qla2x00_async_prlo_sp_done;
11aea16a
QT		 446
447 ql_dbg(ql_dbg_disc, vha, 0x2070,
448 "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
449 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
450 fcport->d_id.b.area, fcport->d_id.b.al_pa);
f233e8c0
BK		 451
452 rval = qla2x00_start_sp(sp);
453 if (rval != QLA_SUCCESS)
454 goto done_free_sp;
455
11aea16a
QT		 456 return rval;
457
458done_free_sp:
459 sp->free(sp);
460done:
fa83e658 461 fcport->flags &= ~FCF_ASYNC_ACTIVE;
11aea16a
QT		 462 return rval;
463}
464
f13515ac
QT		 465static
466void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea)
467{
0616e965
QT		 468 struct fc_port *fcport = ea->fcport;
469
470 ql_dbg(ql_dbg_disc, vha, 0x20d2,
471 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n",
472 __func__, fcport->port_name, fcport->disc_state,
473 fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2,
474 fcport->rscn_gen, ea->sp->gen1, fcport->loop_id);
475
476 if (ea->data[0] != MBS_COMMAND_COMPLETE) {
a4239945
QT		 477 ql_dbg(ql_dbg_disc, vha, 0x2066,
478 "%s %8phC: adisc fail: post delete\n",
479 __func__, ea->fcport->port_name);
2d3fdbeb
QT		 480 /* deleted = 0 & logout_on_delete = force fw cleanup */
481 fcport->deleted = 0;
482 fcport->logout_on_delete = 1;
94cff6e1 483 qlt_schedule_sess_for_deletion(ea->fcport);
a4239945
QT		 484 return;
485 }
a4239945
QT		 486
487 if (ea->fcport->disc_state == DSC_DELETE_PEND)
488 return;
489
490 if (ea->sp->gen2 != ea->fcport->login_gen) {
491 /* target side must have changed it. */
492 ql_dbg(ql_dbg_disc, vha, 0x20d3,
0616e965
QT		 493 "%s %8phC generation changed\n",
494 __func__, ea->fcport->port_name);
a4239945
QT		 495 return;
496 } else if (ea->sp->gen1 != ea->fcport->rscn_gen) {
d4f7a16a 497 qla_rscn_replay(fcport);
861d483d 498 qlt_schedule_sess_for_deletion(fcport);
a4239945
QT		 499 return;
500 }
501
502 __qla24xx_handle_gpdb_event(vha, ea);
f13515ac 503}
ac280b67 504
8f9a2148 505static int qla_post_els_plogi_work(struct scsi_qla_host *vha, fc_port_t *fcport)
8777e431
QT		 506{
507 struct qla_work_evt *e;
508
509 e = qla2x00_alloc_work(vha, QLA_EVT_ELS_PLOGI);
510 if (!e)
511 return QLA_FUNCTION_FAILED;
512
513 e->u.fcport.fcport = fcport;
514 fcport->flags |= FCF_ASYNC_ACTIVE;
515 return qla2x00_post_work(vha, e);
516}
517
6c18a43e 518static void qla2x00_async_adisc_sp_done(srb_t *sp, int res)
5ff1d584 519{
25ff6af1 520 struct scsi_qla_host *vha = sp->vha;
f13515ac 521 struct event_arg ea;
0616e965 522 struct srb_iocb *lio = &sp->u.iocb_cmd;
f13515ac
QT		 523
524 ql_dbg(ql_dbg_disc, vha, 0x2066,
525 "Async done-%s res %x %8phC\n",
526 sp->name, res, sp->fcport->port_name);
527
15b6c3c9 528 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
fa83e658 529
f13515ac
QT		 530 memset(&ea, 0, sizeof(ea));
531 ea.event = FCME_ADISC_DONE;
532 ea.rc = res;
0616e965
QT		 533 ea.data[0] = lio->u.logio.data[0];
534 ea.data[1] = lio->u.logio.data[1];
535 ea.iop[0] = lio->u.logio.iop[0];
536 ea.iop[1] = lio->u.logio.iop[1];
f13515ac
QT		 537 ea.fcport = sp->fcport;
538 ea.sp = sp;
539
540 qla2x00_fcport_event_handler(vha, &ea);
9ba56b95 541
25ff6af1 542 sp->free(sp);
5ff1d584
AV		 543}
544
545int
546qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
547 uint16_t *data)
548{
5ff1d584 549 srb_t *sp;
4916392b 550 struct srb_iocb *lio;
192c4e9b
QT		 551 int rval = QLA_FUNCTION_FAILED;
552
553 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
554 return rval;
5ff1d584 555
726b8548 556 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 557 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 558 if (!sp)
559 goto done;
560
9ba56b95
GM		 561 sp->type = SRB_ADISC_CMD;
562 sp->name = "adisc";
9ba56b95
GM		 563
564 lio = &sp->u.iocb_cmd;
3822263e 565 lio->timeout = qla2x00_async_iocb_timeout;
8777e431
QT		 566 sp->gen1 = fcport->rscn_gen;
567 sp->gen2 = fcport->login_gen;
e74e7d95
BH		 568 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
569
9ba56b95 570 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 571 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 572 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584 573
7c3df132 574 ql_dbg(ql_dbg_disc, vha, 0x206f,
f13515ac
QT		 575 "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n",
576 sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name);
9fe278f4
GM		 577
578 rval = qla2x00_start_sp(sp);
579 if (rval != QLA_SUCCESS)
580 goto done_free_sp;
581
5ff1d584
AV		 582 return rval;
583
584done_free_sp:
25ff6af1 585 sp->free(sp);
5ff1d584 586done:
fa83e658 587 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
f13515ac 588 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548
QT		 589 return rval;
590}
591
0c6660b2
BVA		 592static bool qla2x00_is_reserved_id(scsi_qla_host_t *vha, uint16_t loop_id)
593{
594 struct qla_hw_data *ha = vha->hw;
595
596 if (IS_FWI2_CAPABLE(ha))
597 return loop_id > NPH_LAST_HANDLE;
598
599 return (loop_id > ha->max_loop_id && loop_id < SNS_FIRST_LOOP_ID) ||
600 loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST;
601}
602
94f5b916
BVA		 603/**
604 * qla2x00_find_new_loop_id - scan through our port list and find a new usable loop ID
605 * @vha: adapter state pointer.
606 * @dev: port structure pointer.
607 *
608 * Returns:
609 * qla2x00 local function return status code.
610 *
611 * Context:
612 * Kernel context.
613 */
614static int qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
615{
616 int rval;
617 struct qla_hw_data *ha = vha->hw;
618 unsigned long flags = 0;
619
620 rval = QLA_SUCCESS;
621
622 spin_lock_irqsave(&ha->vport_slock, flags);
623
624 dev->loop_id = find_first_zero_bit(ha->loop_id_map, LOOPID_MAP_SIZE);
625 if (dev->loop_id >= LOOPID_MAP_SIZE ||
626 qla2x00_is_reserved_id(vha, dev->loop_id)) {
627 dev->loop_id = FC_NO_LOOP_ID;
628 rval = QLA_FUNCTION_FAILED;
629 } else {
630 set_bit(dev->loop_id, ha->loop_id_map);
631 }
632 spin_unlock_irqrestore(&ha->vport_slock, flags);
633
634 if (rval == QLA_SUCCESS)
635 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
636 "Assigning new loopid=%x, portid=%x.\n",
637 dev->loop_id, dev->d_id.b24);
638 else
639 ql_log(ql_log_warn, dev->vha, 0x2087,
640 "No loop_id's available, portid=%x.\n",
641 dev->d_id.b24);
642
643 return rval;
644}
645
ef1eb688
BVA		 646void qla2x00_clear_loop_id(fc_port_t *fcport)
647{
648 struct qla_hw_data *ha = fcport->vha->hw;
649
650 if (fcport->loop_id == FC_NO_LOOP_ID ||
651 qla2x00_is_reserved_id(fcport->vha, fcport->loop_id))
652 return;
653
654 clear_bit(fcport->loop_id, ha->loop_id_map);
655 fcport->loop_id = FC_NO_LOOP_ID;
656}
657
726b8548
QT		 658static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
659 struct event_arg *ea)
660{
661 fc_port_t *fcport, *conflict_fcport;
662 struct get_name_list_extended *e;
663 u16 i, n, found = 0, loop_id;
664 port_id_t id;
665 u64 wwn;
a4239945
QT		 666 u16 data[2];
667 u8 current_login_state;
726b8548
QT		 668
669 fcport = ea->fcport;
f352eeb7
QT		 670 ql_dbg(ql_dbg_disc, vha, 0xffff,
671 "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d\n",
672 __func__, fcport->port_name, fcport->disc_state,
673 fcport->fw_login_state, ea->rc,
674 fcport->login_gen, fcport->last_login_gen,
675 fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id);
726b8548 676
a4239945
QT		 677 if (fcport->disc_state == DSC_DELETE_PEND)
678 return;
679
726b8548
QT		 680 if (ea->rc) { /* rval */
681 if (fcport->login_retry == 0) {
83548fe2
QT		 682 ql_dbg(ql_dbg_disc, vha, 0x20de,
683 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
684 fcport->port_name, fcport->login_retry);
726b8548
QT		 685 }
686 return;
687 }
688
689 if (fcport->last_rscn_gen != fcport->rscn_gen) {
d4f7a16a 690 qla_rscn_replay(fcport);
861d483d 691 qlt_schedule_sess_for_deletion(fcport);
726b8548
QT		 692 return;
693 } else if (fcport->last_login_gen != fcport->login_gen) {
83548fe2 694 ql_dbg(ql_dbg_disc, vha, 0x20e0,
f352eeb7
QT		 695 "%s %8phC login gen changed\n",
696 __func__, fcport->port_name);
726b8548
QT		 697 return;
698 }
699
700 n = ea->data[0] / sizeof(struct get_name_list_extended);
701
83548fe2 702 ql_dbg(ql_dbg_disc, vha, 0x20e1,
726b8548
QT		 703 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
704 __func__, __LINE__, fcport->port_name, n,
705 fcport->d_id.b.domain, fcport->d_id.b.area,
706 fcport->d_id.b.al_pa, fcport->loop_id);
707
708 for (i = 0; i < n; i++) {
709 e = &vha->gnl.l[i];
710 wwn = wwn_to_u64(e->port_name);
48acad09
QT		 711 id.b.domain = e->port_id[2];
712 id.b.area = e->port_id[1];
713 id.b.al_pa = e->port_id[0];
714 id.b.rsvd_1 = 0;
726b8548
QT		 715
716 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
717 continue;
718
48acad09
QT		 719 if (IS_SW_RESV_ADDR(id))
720 continue;
721
726b8548 722 found = 1;
726b8548
QT		 723
724 loop_id = le16_to_cpu(e->nport_handle);
725 loop_id = (loop_id & 0x7fff);
8777e431
QT		 726 if (fcport->fc4f_nvme)
727 current_login_state = e->current_login_state >> 4;
728 else
729 current_login_state = e->current_login_state & 0xf;
730
726b8548 731
83548fe2 732 ql_dbg(ql_dbg_disc, vha, 0x20e2,
8777e431 733 "%s found %8phC CLS [%x|%x] nvme %d ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n",
83548fe2
QT		 734 __func__, fcport->port_name,
735 e->current_login_state, fcport->fw_login_state,
8777e431 736 fcport->fc4f_nvme, id.b.domain, id.b.area, id.b.al_pa,
83548fe2
QT		 737 fcport->d_id.b.domain, fcport->d_id.b.area,
738 fcport->d_id.b.al_pa, loop_id, fcport->loop_id);
726b8548 739
48acad09
QT		 740 switch (fcport->disc_state) {
741 case DSC_DELETE_PEND:
742 case DSC_DELETED:
743 break;
744 default:
8777e431
QT		 745 if ((id.b24 != fcport->d_id.b24 &&
746 fcport->d_id.b24) ||
747 (fcport->loop_id != FC_NO_LOOP_ID &&
748 fcport->loop_id != loop_id)) {
749 ql_dbg(ql_dbg_disc, vha, 0x20e3,
750 "%s %d %8phC post del sess\n",
751 __func__, __LINE__, fcport->port_name);
48acad09
QT		 752 qlt_schedule_sess_for_deletion(fcport);
753 return;
754 }
755 break;
726b8548
QT		 756 }
757
758 fcport->loop_id = loop_id;
759
760 wwn = wwn_to_u64(fcport->port_name);
761 qlt_find_sess_invalidate_other(vha, wwn,
762 id, loop_id, &conflict_fcport);
763
764 if (conflict_fcport) {
765 /*
766 * Another share fcport share the same loop_id &
767 * nport id. Conflict fcport needs to finish
768 * cleanup before this fcport can proceed to login.
769 */
770 conflict_fcport->conflict = fcport;
771 fcport->login_pause = 1;
772 }
773
48acad09
QT		 774 switch (vha->hw->current_topology) {
775 default:
776 switch (current_login_state) {
777 case DSC_LS_PRLI_COMP:
778 ql_dbg(ql_dbg_disc + ql_dbg_verbose,
779 vha, 0x20e4, "%s %d %8phC post gpdb\n",
780 __func__, __LINE__, fcport->port_name);
a4239945 781
48acad09
QT		 782 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
783 fcport->port_type = FCT_INITIATOR;
784 else
785 fcport->port_type = FCT_TARGET;
786 data[0] = data[1] = 0;
787 qla2x00_post_async_adisc_work(vha, fcport,
788 data);
789 break;
790 case DSC_LS_PORT_UNAVAIL:
791 default:
ec322937
HM		 792 if (fcport->loop_id == FC_NO_LOOP_ID) {
793 qla2x00_find_new_loop_id(vha, fcport);
794 fcport->fw_login_state =
795 DSC_LS_PORT_UNAVAIL;
796 }
797 ql_dbg(ql_dbg_disc, vha, 0x20e5,
798 "%s %d %8phC\n", __func__, __LINE__,
799 fcport->port_name);
48acad09
QT		 800 qla24xx_fcport_handle_login(vha, fcport);
801 break;
726b8548 802 }
726b8548 803 break;
48acad09 804 case ISP_CFG_N:
8777e431
QT		 805 fcport->fw_login_state = current_login_state;
806 fcport->d_id = id;
48acad09
QT		 807 switch (current_login_state) {
808 case DSC_LS_PRLI_COMP:
809 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
810 fcport->port_type = FCT_INITIATOR;
811 else
812 fcport->port_type = FCT_TARGET;
813
814 data[0] = data[1] = 0;
815 qla2x00_post_async_adisc_work(vha, fcport,
816 data);
817 break;
818 case DSC_LS_PLOGI_COMP:
819 if (fcport_is_bigger(fcport)) {
820 /* local adapter is smaller */
821 if (fcport->loop_id != FC_NO_LOOP_ID)
822 qla2x00_clear_loop_id(fcport);
823
824 fcport->loop_id = loop_id;
825 qla24xx_fcport_handle_login(vha,
826 fcport);
827 break;
828 }
50435d42 829 /* fall through */
48acad09
QT		 830 default:
831 if (fcport_is_smaller(fcport)) {
832 /* local adapter is bigger */
833 if (fcport->loop_id != FC_NO_LOOP_ID)
834 qla2x00_clear_loop_id(fcport);
835
836 fcport->loop_id = loop_id;
837 qla24xx_fcport_handle_login(vha,
838 fcport);
839 }
840 break;
841 }
842 break;
843 } /* switch (ha->current_topology) */
726b8548
QT		 844 }
845
846 if (!found) {
48acad09
QT		 847 switch (vha->hw->current_topology) {
848 case ISP_CFG_F:
849 case ISP_CFG_FL:
850 for (i = 0; i < n; i++) {
851 e = &vha->gnl.l[i];
852 id.b.domain = e->port_id[0];
853 id.b.area = e->port_id[1];
854 id.b.al_pa = e->port_id[2];
855 id.b.rsvd_1 = 0;
856 loop_id = le16_to_cpu(e->nport_handle);
857
858 if (fcport->d_id.b24 == id.b24) {
859 conflict_fcport =
860 qla2x00_find_fcport_by_wwpn(vha,
861 e->port_name, 0);
72f02ba6
LT		 862 if (conflict_fcport) {
863 ql_dbg(ql_dbg_disc + ql_dbg_verbose,
864 vha, 0x20e5,
865 "%s %d %8phC post del sess\n",
866 __func__, __LINE__,
867 conflict_fcport->port_name);
868 qlt_schedule_sess_for_deletion
869 (conflict_fcport);
870 }
36eb8ff6 871 }
48acad09
QT		 872 /*
873 * FW already picked this loop id for
874 * another fcport
875 */
876 if (fcport->loop_id == loop_id)
877 fcport->loop_id = FC_NO_LOOP_ID;
726b8548 878 }
48acad09
QT		 879 qla24xx_fcport_handle_login(vha, fcport);
880 break;
881 case ISP_CFG_N:
8777e431
QT		 882 fcport->disc_state = DSC_DELETED;
883 if (time_after_eq(jiffies, fcport->dm_login_expire)) {
884 if (fcport->n2n_link_reset_cnt < 2) {
885 fcport->n2n_link_reset_cnt++;
886 /*
887 * remote port is not sending PLOGI.
888 * Reset link to kick start his state
889 * machine
890 */
891 set_bit(N2N_LINK_RESET,
892 &vha->dpc_flags);
893 } else {
894 if (fcport->n2n_chip_reset < 1) {
895 ql_log(ql_log_info, vha, 0x705d,
896 "Chip reset to bring laser down");
897 set_bit(ISP_ABORT_NEEDED,
898 &vha->dpc_flags);
899 fcport->n2n_chip_reset++;
900 } else {
901 ql_log(ql_log_info, vha, 0x705d,
902 "Remote port %8ph is not coming back\n",
903 fcport->port_name);
904 fcport->scan_state = 0;
905 }
906 }
907 qla2xxx_wake_dpc(vha);
908 } else {
909 /*
910 * report port suppose to do PLOGI. Give him
911 * more time. FW will catch it.
912 */
913 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
914 }
48acad09
QT		 915 break;
916 default:
917 break;
726b8548 918 }
726b8548
QT		 919 }
920} /* gnl_event */
921
6c18a43e 922static void qla24xx_async_gnl_sp_done(srb_t *sp, int res)
726b8548 923{
25ff6af1 924 struct scsi_qla_host *vha = sp->vha;
726b8548
QT		 925 unsigned long flags;
926 struct fc_port *fcport = NULL, *tf;
927 u16 i, n = 0, loop_id;
928 struct event_arg ea;
929 struct get_name_list_extended *e;
930 u64 wwn;
931 struct list_head h;
a4239945 932 bool found = false;
726b8548 933
83548fe2 934 ql_dbg(ql_dbg_disc, vha, 0x20e7,
726b8548
QT		 935 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
936 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
937 sp->u.iocb_cmd.u.mbx.in_mb[2]);
938
ef801f07
HM		 939 if (res == QLA_FUNCTION_TIMEOUT)
940 return;
941
0aca7784 942 sp->fcport->flags &= ~(FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE);
726b8548
QT		 943 memset(&ea, 0, sizeof(ea));
944 ea.sp = sp;
945 ea.rc = res;
946 ea.event = FCME_GNL_DONE;
947
948 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
949 sizeof(struct get_name_list_extended)) {
950 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
951 sizeof(struct get_name_list_extended);
952 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
953 }
954
955 for (i = 0; i < n; i++) {
956 e = &vha->gnl.l[i];
957 loop_id = le16_to_cpu(e->nport_handle);
958 /* mask out reserve bit */
959 loop_id = (loop_id & 0x7fff);
960 set_bit(loop_id, vha->hw->loop_id_map);
961 wwn = wwn_to_u64(e->port_name);
962
83548fe2 963 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20e8,
726b8548
QT		 964 "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n",
965 __func__, (void *)&wwn, e->port_id[2], e->port_id[1],
966 e->port_id[0], e->current_login_state, e->last_login_state,
967 (loop_id & 0x7fff));
968 }
969
0aca7784 970 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 971
972 INIT_LIST_HEAD(&h);
973 fcport = tf = NULL;
974 if (!list_empty(&vha->gnl.fcports))
975 list_splice_init(&vha->gnl.fcports, &h);
0aca7784 976 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 977
978 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
979 list_del_init(&fcport->gnl_entry);
0aca7784 980 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
6d674927 981 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
0aca7784 982 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 983 ea.fcport = fcport;
984
985 qla2x00_fcport_event_handler(vha, &ea);
986 }
987
a4239945
QT		 988 /* create new fcport if fw has knowledge of new sessions */
989 for (i = 0; i < n; i++) {
990 port_id_t id;
991 u64 wwnn;
992
993 e = &vha->gnl.l[i];
994 wwn = wwn_to_u64(e->port_name);
995
996 found = false;
997 list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) {
998 if (!memcmp((u8 *)&wwn, fcport->port_name,
999 WWN_SIZE)) {
1000 found = true;
1001 break;
1002 }
1003 }
1004
cf055fb0 1005 id.b.domain = e->port_id[2];
a4239945 1006 id.b.area = e->port_id[1];
cf055fb0 1007 id.b.al_pa = e->port_id[0];
a4239945
QT		 1008 id.b.rsvd_1 = 0;
1009
1010 if (!found && wwn && !IS_SW_RESV_ADDR(id)) {
1011 ql_dbg(ql_dbg_disc, vha, 0x2065,
cf055fb0
QT		 1012 "%s %d %8phC %06x post new sess\n",
1013 __func__, __LINE__, (u8 *)&wwn, id.b24);
a4239945
QT		 1014 wwnn = wwn_to_u64(e->node_name);
1015 qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn,
1016 (u8 *)&wwnn, NULL, FC4_TYPE_UNKNOWN);
1017 }
1018 }
1019
0aca7784
QT		 1020 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1021 vha->gnl.sent = 0;
726b8548
QT		 1022 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1023
25ff6af1 1024 sp->free(sp);
726b8548
QT		 1025}
1026
1027int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
1028{
1029 srb_t *sp;
1030 struct srb_iocb *mbx;
1031 int rval = QLA_FUNCTION_FAILED;
1032 unsigned long flags;
1033 u16 *mb;
1034
3dbec59b
QT		 1035 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
1036 return rval;
726b8548 1037
83548fe2 1038 ql_dbg(ql_dbg_disc, vha, 0x20d9,
726b8548
QT		 1039 "Async-gnlist WWPN %8phC \n", fcport->port_name);
1040
0aca7784
QT		 1041 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1042 fcport->flags |= FCF_ASYNC_SENT;
726b8548
QT		 1043 fcport->disc_state = DSC_GNL;
1044 fcport->last_rscn_gen = fcport->rscn_gen;
1045 fcport->last_login_gen = fcport->login_gen;
1046
1047 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
0aca7784
QT		 1048 if (vha->gnl.sent) {
1049 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1050 return QLA_SUCCESS;
1051 }
1052 vha->gnl.sent = 1;
1053 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 1054
1055 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1056 if (!sp)
1057 goto done;
3dbec59b 1058
726b8548
QT		 1059 sp->type = SRB_MB_IOCB;
1060 sp->name = "gnlist";
1061 sp->gen1 = fcport->rscn_gen;
1062 sp->gen2 = fcport->login_gen;
1063
e74e7d95
BH		 1064 mbx = &sp->u.iocb_cmd;
1065 mbx->timeout = qla2x00_async_iocb_timeout;
726b8548
QT		 1066 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
1067
1068 mb = sp->u.iocb_cmd.u.mbx.out_mb;
1069 mb[0] = MBC_PORT_NODE_NAME_LIST;
1070 mb[1] = BIT_2 | BIT_3;
1071 mb[2] = MSW(vha->gnl.ldma);
1072 mb[3] = LSW(vha->gnl.ldma);
1073 mb[6] = MSW(MSD(vha->gnl.ldma));
1074 mb[7] = LSW(MSD(vha->gnl.ldma));
1075 mb[8] = vha->gnl.size;
1076 mb[9] = vha->vp_idx;
1077
726b8548
QT		 1078 sp->done = qla24xx_async_gnl_sp_done;
1079
83548fe2
QT		 1080 ql_dbg(ql_dbg_disc, vha, 0x20da,
1081 "Async-%s - OUT WWPN %8phC hndl %x\n",
1082 sp->name, fcport->port_name, sp->handle);
726b8548 1083
f233e8c0
BK		 1084 rval = qla2x00_start_sp(sp);
1085 if (rval != QLA_SUCCESS)
1086 goto done_free_sp;
1087
726b8548
QT		 1088 return rval;
1089
1090done_free_sp:
25ff6af1 1091 sp->free(sp);
726b8548 1092 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 1093done:
726b8548
QT		 1094 return rval;
1095}
1096
1097int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
1098{
1099 struct qla_work_evt *e;
1100
1101 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
1102 if (!e)
1103 return QLA_FUNCTION_FAILED;
1104
1105 e->u.fcport.fcport = fcport;
6d674927 1106 fcport->flags |= FCF_ASYNC_ACTIVE;
726b8548
QT		 1107 return qla2x00_post_work(vha, e);
1108}
1109
6c18a43e 1110static void qla24xx_async_gpdb_sp_done(srb_t *sp, int res)
726b8548 1111{
25ff6af1 1112 struct scsi_qla_host *vha = sp->vha;
726b8548 1113 struct qla_hw_data *ha = vha->hw;
726b8548
QT		 1114 fc_port_t *fcport = sp->fcport;
1115 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
726b8548
QT		 1116 struct event_arg ea;
1117
83548fe2 1118 ql_dbg(ql_dbg_disc, vha, 0x20db,
726b8548
QT		 1119 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
1120 sp->name, res, fcport->port_name, mb[1], mb[2]);
1121
bcc71cc3
GM		 1122 if (res == QLA_FUNCTION_TIMEOUT) {
1123 dma_pool_free(sp->vha->hw->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
1124 sp->u.iocb_cmd.u.mbx.in_dma);
1125 return;
1126 }
1127
ef801f07 1128 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
726b8548
QT		 1129 memset(&ea, 0, sizeof(ea));
1130 ea.event = FCME_GPDB_DONE;
726b8548
QT		 1131 ea.fcport = fcport;
1132 ea.sp = sp;
1133
1134 qla2x00_fcport_event_handler(vha, &ea);
1135
1136 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
1137 sp->u.iocb_cmd.u.mbx.in_dma);
1138
25ff6af1 1139 sp->free(sp);
726b8548
QT		 1140}
1141
a5d42f4c
DG		 1142static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport)
1143{
1144 struct qla_work_evt *e;
1145
1146 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI);
1147 if (!e)
1148 return QLA_FUNCTION_FAILED;
1149
1150 e->u.fcport.fcport = fcport;
1151
1152 return qla2x00_post_work(vha, e);
1153}
1154
6c18a43e 1155static void qla2x00_async_prli_sp_done(srb_t *sp, int res)
a5d42f4c 1156{
a5d42f4c
DG		 1157 struct scsi_qla_host *vha = sp->vha;
1158 struct srb_iocb *lio = &sp->u.iocb_cmd;
1159 struct event_arg ea;
1160
1161 ql_dbg(ql_dbg_disc, vha, 0x2129,
1162 "%s %8phC res %d \n", __func__,
1163 sp->fcport->port_name, res);
1164
1165 sp->fcport->flags &= ~FCF_ASYNC_SENT;
1166
1167 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
1168 memset(&ea, 0, sizeof(ea));
1169 ea.event = FCME_PRLI_DONE;
1170 ea.fcport = sp->fcport;
1171 ea.data[0] = lio->u.logio.data[0];
1172 ea.data[1] = lio->u.logio.data[1];
1173 ea.iop[0] = lio->u.logio.iop[0];
1174 ea.iop[1] = lio->u.logio.iop[1];
1175 ea.sp = sp;
1176
1177 qla2x00_fcport_event_handler(vha, &ea);
1178 }
1179
1180 sp->free(sp);
1181}
1182
1183int
1184qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport)
1185{
1186 srb_t *sp;
1187 struct srb_iocb *lio;
1188 int rval = QLA_FUNCTION_FAILED;
1189
1190 if (!vha->flags.online)
1191 return rval;
1192
1193 if (fcport->fw_login_state == DSC_LS_PLOGI_PEND ||
a5d42f4c
DG		 1194 fcport->fw_login_state == DSC_LS_PRLI_PEND)
1195 return rval;
1196
1197 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1198 if (!sp)
1199 return rval;
1200
1201 fcport->flags |= FCF_ASYNC_SENT;
1202 fcport->logout_completed = 0;
1203
1204 sp->type = SRB_PRLI_CMD;
1205 sp->name = "prli";
a5d42f4c
DG		 1206
1207 lio = &sp->u.iocb_cmd;
1208 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 1209 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
1210
a5d42f4c
DG		 1211 sp->done = qla2x00_async_prli_sp_done;
1212 lio->u.logio.flags = 0;
1213
1214 if (fcport->fc4f_nvme)
1215 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI;
1216
f233e8c0
BK		 1217 ql_dbg(ql_dbg_disc, vha, 0x211b,
1218 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d %s.\n",
1219 fcport->port_name, sp->handle, fcport->loop_id, fcport->d_id.b24,
1220 fcport->login_retry, fcport->fc4f_nvme ? "nvme" : "fc");
1221
a5d42f4c
DG		 1222 rval = qla2x00_start_sp(sp);
1223 if (rval != QLA_SUCCESS) {
a5d42f4c
DG		 1224 fcport->flags |= FCF_LOGIN_NEEDED;
1225 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1226 goto done_free_sp;
1227 }
1228
a5d42f4c
DG		 1229 return rval;
1230
1231done_free_sp:
1232 sp->free(sp);
1233 fcport->flags &= ~FCF_ASYNC_SENT;
1234 return rval;
1235}
1236
a07fc0a4 1237int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
726b8548
QT		 1238{
1239 struct qla_work_evt *e;
1240
1241 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
1242 if (!e)
1243 return QLA_FUNCTION_FAILED;
1244
1245 e->u.fcport.fcport = fcport;
1246 e->u.fcport.opt = opt;
6d674927 1247 fcport->flags |= FCF_ASYNC_ACTIVE;
726b8548
QT		 1248 return qla2x00_post_work(vha, e);
1249}
1250
1251int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
1252{
1253 srb_t *sp;
1254 struct srb_iocb *mbx;
1255 int rval = QLA_FUNCTION_FAILED;
1256 u16 *mb;
1257 dma_addr_t pd_dma;
1258 struct port_database_24xx *pd;
1259 struct qla_hw_data *ha = vha->hw;
1260
8b5292bc
QT		 1261 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) ||
1262 fcport->loop_id == FC_NO_LOOP_ID) {
1263 ql_log(ql_log_warn, vha, 0xffff,
1264 "%s: %8phC - not sending command.\n",
1265 __func__, fcport->port_name);
3dbec59b 1266 return rval;
8b5292bc 1267 }
726b8548 1268
726b8548
QT		 1269 fcport->disc_state = DSC_GPDB;
1270
1271 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1272 if (!sp)
1273 goto done;
1274
3dbec59b 1275 fcport->flags |= FCF_ASYNC_SENT;
e0824e69
JC		 1276 sp->type = SRB_MB_IOCB;
1277 sp->name = "gpdb";
1278 sp->gen1 = fcport->rscn_gen;
1279 sp->gen2 = fcport->login_gen;
e74e7d95
BH		 1280
1281 mbx = &sp->u.iocb_cmd;
1282 mbx->timeout = qla2x00_async_iocb_timeout;
e0824e69
JC		 1283 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
1284
08eb7f45 1285 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
726b8548 1286 if (pd == NULL) {
83548fe2
QT		 1287 ql_log(ql_log_warn, vha, 0xd043,
1288 "Failed to allocate port database structure.\n");
726b8548
QT		 1289 goto done_free_sp;
1290 }
726b8548 1291
726b8548
QT		 1292 mb = sp->u.iocb_cmd.u.mbx.out_mb;
1293 mb[0] = MBC_GET_PORT_DATABASE;
1294 mb[1] = fcport->loop_id;
1295 mb[2] = MSW(pd_dma);
1296 mb[3] = LSW(pd_dma);
1297 mb[6] = MSW(MSD(pd_dma));
1298 mb[7] = LSW(MSD(pd_dma));
1299 mb[9] = vha->vp_idx;
1300 mb[10] = opt;
1301
726b8548
QT		 1302 mbx->u.mbx.in = (void *)pd;
1303 mbx->u.mbx.in_dma = pd_dma;
1304
1305 sp->done = qla24xx_async_gpdb_sp_done;
1306
83548fe2
QT		 1307 ql_dbg(ql_dbg_disc, vha, 0x20dc,
1308 "Async-%s %8phC hndl %x opt %x\n",
1309 sp->name, fcport->port_name, sp->handle, opt);
726b8548 1310
9fe278f4
GM		 1311 rval = qla2x00_start_sp(sp);
1312 if (rval != QLA_SUCCESS)
1313 goto done_free_sp;
726b8548
QT		 1314 return rval;
1315
1316done_free_sp:
1317 if (pd)
1318 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1319
25ff6af1 1320 sp->free(sp);
726b8548 1321 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 1322done:
726b8548 1323 qla24xx_post_gpdb_work(vha, fcport, opt);
5ff1d584
AV		 1324 return rval;
1325}
1326
726b8548 1327static
a4239945 1328void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1329{
726b8548
QT		 1330 unsigned long flags;
1331
726b8548 1332 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
f13515ac 1333 ea->fcport->login_gen++;
726b8548
QT		 1334 ea->fcport->deleted = 0;
1335 ea->fcport->logout_on_delete = 1;
1336
1337 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
1338 vha->fcport_count++;
1339 ea->fcport->login_succ = 1;
1340
0aca7784 1341 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
cd4ed6b4 1342 qla24xx_sched_upd_fcport(ea->fcport);
0aca7784 1343 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
414d9ff3
QT		 1344 } else if (ea->fcport->login_succ) {
1345 /*
1346 * We have an existing session. A late RSCN delivery
1347 * must have triggered the session to be re-validate.
a4239945 1348 * Session is still valid.
414d9ff3 1349 */
5ef696aa
QT		 1350 ql_dbg(ql_dbg_disc, vha, 0x20d6,
1351 "%s %d %8phC session revalidate success\n",
a4239945 1352 __func__, __LINE__, ea->fcport->port_name);
8a7eac2f 1353 ea->fcport->disc_state = DSC_LOGIN_COMPLETE;
726b8548
QT		 1354 }
1355 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
a4239945
QT		 1356}
1357
1358static
1359void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
1360{
a4239945
QT		 1361 fc_port_t *fcport = ea->fcport;
1362 struct port_database_24xx *pd;
1363 struct srb *sp = ea->sp;
2b5b9647 1364 uint8_t ls;
a4239945
QT		 1365
1366 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
1367
1368 fcport->flags &= ~FCF_ASYNC_SENT;
1369
1370 ql_dbg(ql_dbg_disc, vha, 0x20d2,
8777e431
QT		 1371 "%s %8phC DS %d LS %d nvme %x rc %d\n", __func__, fcport->port_name,
1372 fcport->disc_state, pd->current_login_state, fcport->fc4f_nvme,
1373 ea->rc);
a4239945
QT		 1374
1375 if (fcport->disc_state == DSC_DELETE_PEND)
1376 return;
726b8548 1377
2b5b9647
DT		 1378 if (fcport->fc4f_nvme)
1379 ls = pd->current_login_state >> 4;
1380 else
1381 ls = pd->current_login_state & 0xf;
1382
d4f7a16a
HM		 1383 if (ea->sp->gen2 != fcport->login_gen) {
1384 /* target side must have changed it. */
1385
1386 ql_dbg(ql_dbg_disc, vha, 0x20d3,
1387 "%s %8phC generation changed\n",
1388 __func__, fcport->port_name);
1389 return;
1390 } else if (ea->sp->gen1 != fcport->rscn_gen) {
1391 qla_rscn_replay(fcport);
861d483d 1392 qlt_schedule_sess_for_deletion(fcport);
d4f7a16a
HM		 1393 return;
1394 }
1395
2b5b9647 1396 switch (ls) {
a4239945
QT		 1397 case PDS_PRLI_COMPLETE:
1398 __qla24xx_parse_gpdb(vha, fcport, pd);
1399 break;
1400 case PDS_PLOGI_PENDING:
1401 case PDS_PLOGI_COMPLETE:
1402 case PDS_PRLI_PENDING:
1403 case PDS_PRLI2_PENDING:
8fde6977
QT		 1404 /* Set discovery state back to GNL to Relogin attempt */
1405 if (qla_dual_mode_enabled(vha) ||
1406 qla_ini_mode_enabled(vha)) {
1407 fcport->disc_state = DSC_GNL;
1408 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1409 }
a4239945
QT		 1410 return;
1411 case PDS_LOGO_PENDING:
1412 case PDS_PORT_UNAVAILABLE:
1413 default:
1414 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n",
1415 __func__, __LINE__, fcport->port_name);
d8630bb9 1416 qlt_schedule_sess_for_deletion(fcport);
a4239945
QT		 1417 return;
1418 }
1419 __qla24xx_handle_gpdb_event(vha, ea);
1420} /* gpdb event */
9cd883f0
QT		 1421
1422static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1423{
1424 u8 login = 0;
040036bb 1425 int rc;
9cd883f0
QT		 1426
1427 if (qla_tgt_mode_enabled(vha))
1428 return;
1429
1430 if (qla_dual_mode_enabled(vha)) {
1431 if (N2N_TOPO(vha->hw)) {
1432 u64 mywwn, wwn;
1433
1434 mywwn = wwn_to_u64(vha->port_name);
1435 wwn = wwn_to_u64(fcport->port_name);
1436 if (mywwn > wwn)
1437 login = 1;
1438 else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1439 && time_after_eq(jiffies,
1440 fcport->plogi_nack_done_deadline))
1441 login = 1;
1442 } else {
1443 login = 1;
1444 }
1445 } else {
1446 /* initiator mode */
1447 login = 1;
1448 }
1449
0754d5e0
QT		 1450 if (login && fcport->login_retry) {
1451 fcport->login_retry--;
040036bb
QT		 1452 if (fcport->loop_id == FC_NO_LOOP_ID) {
1453 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
1454 rc = qla2x00_find_new_loop_id(vha, fcport);
1455 if (rc) {
1456 ql_dbg(ql_dbg_disc, vha, 0x20e6,
1457 "%s %d %8phC post del sess - out of loopid\n",
1458 __func__, __LINE__, fcport->port_name);
1459 fcport->scan_state = 0;
94cff6e1 1460 qlt_schedule_sess_for_deletion(fcport);
040036bb
QT		 1461 return;
1462 }
1463 }
9cd883f0
QT		 1464 ql_dbg(ql_dbg_disc, vha, 0x20bf,
1465 "%s %d %8phC post login\n",
1466 __func__, __LINE__, fcport->port_name);
9cd883f0
QT		 1467 qla2x00_post_async_login_work(vha, fcport, NULL);
1468 }
1469}
1470
726b8548
QT		 1471int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1472{
f13515ac 1473 u16 data[2];
a4239945 1474 u64 wwn;
cd4ed6b4 1475 u16 sec;
726b8548 1476
0754d5e0
QT		 1477 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20d8,
1478 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d lid %d scan %d\n",
726b8548
QT		 1479 __func__, fcport->port_name, fcport->disc_state,
1480 fcport->fw_login_state, fcport->login_pause, fcport->flags,
1481 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
0754d5e0 1482 fcport->login_gen, fcport->loop_id, fcport->scan_state);
726b8548 1483
a4239945
QT		 1484 if (fcport->scan_state != QLA_FCPORT_FOUND)
1485 return 0;
726b8548 1486
07ea4b60
HR		 1487 if ((fcport->loop_id != FC_NO_LOOP_ID) &&
1488 ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
1489 (fcport->fw_login_state == DSC_LS_PRLI_PEND)))
726b8548
QT		 1490 return 0;
1491
5b33469a 1492 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
9cd883f0
QT		 1493 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1494 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5b33469a 1495 return 0;
9cd883f0 1496 }
5b33469a
QT		 1497 }
1498
726b8548
QT		 1499 /* for pure Target Mode. Login will not be initiated */
1500 if (vha->host->active_mode == MODE_TARGET)
1501 return 0;
1502
1503 if (fcport->flags & FCF_ASYNC_SENT) {
1504 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1505 return 0;
1506 }
1507
1508 switch (fcport->disc_state) {
1509 case DSC_DELETED:
a4239945 1510 wwn = wwn_to_u64(fcport->node_name);
8777e431
QT		 1511 switch (vha->hw->current_topology) {
1512 case ISP_CFG_N:
1513 if (fcport_is_smaller(fcport)) {
1514 /* this adapter is bigger */
1515 if (fcport->login_retry) {
1516 if (fcport->loop_id == FC_NO_LOOP_ID) {
1517 qla2x00_find_new_loop_id(vha,
1518 fcport);
1519 fcport->fw_login_state =
1520 DSC_LS_PORT_UNAVAIL;
1521 }
1522 fcport->login_retry--;
1523 qla_post_els_plogi_work(vha, fcport);
1524 } else {
1525 ql_log(ql_log_info, vha, 0x705d,
1526 "Unable to reach remote port %8phC",
1527 fcport->port_name);
1528 }
1529 } else {
1530 qla24xx_post_gnl_work(vha, fcport);
1531 }
1532 break;
1533 default:
1534 if (wwn == 0) {
1535 ql_dbg(ql_dbg_disc, vha, 0xffff,
1536 "%s %d %8phC post GNNID\n",
1537 __func__, __LINE__, fcport->port_name);
1538 qla24xx_post_gnnid_work(vha, fcport);
1539 } else if (fcport->loop_id == FC_NO_LOOP_ID) {
1540 ql_dbg(ql_dbg_disc, vha, 0x20bd,
1541 "%s %d %8phC post gnl\n",
1542 __func__, __LINE__, fcport->port_name);
1543 qla24xx_post_gnl_work(vha, fcport);
1544 } else {
1545 qla_chk_n2n_b4_login(vha, fcport);
1546 }
1547 break;
726b8548
QT		 1548 }
1549 break;
1550
1551 case DSC_GNL:
8777e431
QT		 1552 switch (vha->hw->current_topology) {
1553 case ISP_CFG_N:
1554 if ((fcport->current_login_state & 0xf) == 0x6) {
1555 ql_dbg(ql_dbg_disc, vha, 0x2118,
1556 "%s %d %8phC post GPDB work\n",
1557 __func__, __LINE__, fcport->port_name);
1558 fcport->chip_reset =
1559 vha->hw->base_qpair->chip_reset;
1560 qla24xx_post_gpdb_work(vha, fcport, 0);
1561 } else {
1562 ql_dbg(ql_dbg_disc, vha, 0x2118,
1563 "%s %d %8phC post NVMe PRLI\n",
1564 __func__, __LINE__, fcport->port_name);
1565 qla24xx_post_prli_work(vha, fcport);
1566 }
1567 break;
1568 default:
1569 if (fcport->login_pause) {
1570 fcport->last_rscn_gen = fcport->rscn_gen;
1571 fcport->last_login_gen = fcport->login_gen;
1572 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1573 break;
1574 }
1575 qla_chk_n2n_b4_login(vha, fcport);
726b8548
QT		 1576 break;
1577 }
726b8548
QT		 1578 break;
1579
1580 case DSC_LOGIN_FAILED:
9cd883f0
QT		 1581 if (N2N_TOPO(vha->hw))
1582 qla_chk_n2n_b4_login(vha, fcport);
1583 else
d4f7a16a 1584 qlt_schedule_sess_for_deletion(fcport);
726b8548
QT		 1585 break;
1586
1587 case DSC_LOGIN_COMPLETE:
1588 /* recheck login state */
f13515ac
QT		 1589 data[0] = data[1] = 0;
1590 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548
QT		 1591 break;
1592
1cbc0efc
DT		 1593 case DSC_LOGIN_PEND:
1594 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1595 qla24xx_post_prli_work(vha, fcport);
1596 break;
1597
cd4ed6b4
QT		 1598 case DSC_UPD_FCPORT:
1599 sec = jiffies_to_msecs(jiffies -
1600 fcport->jiffies_at_registration)/1000;
1601 if (fcport->sec_since_registration < sec && sec &&
1602 !(sec % 60)) {
1603 fcport->sec_since_registration = sec;
1604 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
1605 "%s %8phC - Slow Rport registration(%d Sec)\n",
1606 __func__, fcport->port_name, sec);
1607 }
1608
1609 if (fcport->next_disc_state != DSC_DELETE_PEND)
1610 fcport->next_disc_state = DSC_ADISC;
1611 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1612 break;
1613
726b8548
QT		 1614 default:
1615 break;
1616 }
1617
1618 return 0;
1619}
1620
726b8548 1621int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
a4239945 1622 u8 *port_name, u8 *node_name, void *pla, u8 fc4_type)
726b8548
QT		 1623{
1624 struct qla_work_evt *e;
bd432bb5 1625
726b8548
QT		 1626 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
1627 if (!e)
1628 return QLA_FUNCTION_FAILED;
1629
1630 e->u.new_sess.id = *id;
1631 e->u.new_sess.pla = pla;
a4239945 1632 e->u.new_sess.fc4_type = fc4_type;
726b8548 1633 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
a4239945
QT		 1634 if (node_name)
1635 memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE);
726b8548
QT		 1636
1637 return qla2x00_post_work(vha, e);
1638}
1639
726b8548
QT		 1640static
1641void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
1642 struct event_arg *ea)
1643{
1644 fc_port_t *fcport = ea->fcport;
1645
83548fe2
QT		 1646 ql_dbg(ql_dbg_disc, vha, 0x2102,
1647 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
1648 __func__, fcport->port_name, fcport->disc_state,
1649 fcport->fw_login_state, fcport->login_pause,
1650 fcport->deleted, fcport->conflict,
1651 fcport->last_rscn_gen, fcport->rscn_gen,
1652 fcport->last_login_gen, fcport->login_gen,
1653 fcport->flags);
726b8548
QT		 1654
1655 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1656 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1657 return;
1658
5b33469a 1659 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
9cd883f0
QT		 1660 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1661 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5b33469a 1662 return;
9cd883f0 1663 }
5b33469a
QT		 1664 }
1665
726b8548 1666 if (fcport->last_rscn_gen != fcport->rscn_gen) {
9e744591 1667 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gnl\n",
726b8548 1668 __func__, __LINE__, fcport->port_name);
9e744591 1669 qla24xx_post_gnl_work(vha, fcport);
726b8548
QT		 1670 return;
1671 }
1672
1673 qla24xx_fcport_handle_login(vha, fcport);
1674}
1675
8777e431 1676
8f9a2148
BVA		 1677static void qla_handle_els_plogi_done(scsi_qla_host_t *vha,
1678 struct event_arg *ea)
8777e431
QT		 1679{
1680 ql_dbg(ql_dbg_disc, vha, 0x2118,
1681 "%s %d %8phC post PRLI\n",
1682 __func__, __LINE__, ea->fcport->port_name);
1683 qla24xx_post_prli_work(vha, ea->fcport);
1684}
1685
41dc529a 1686void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1687{
bee8b846 1688 fc_port_t *fcport;
726b8548
QT		 1689
1690 switch (ea->event) {
1691 case FCME_RELOGIN:
1692 if (test_bit(UNLOADING, &vha->dpc_flags))
1693 return;
5ff1d584 1694
726b8548
QT		 1695 qla24xx_handle_relogin_event(vha, ea);
1696 break;
1697 case FCME_RSCN:
1698 if (test_bit(UNLOADING, &vha->dpc_flags))
1699 return;
d4f7a16a
HM		 1700 {
1701 unsigned long flags;
bd432bb5 1702
bee8b846
QT		 1703 fcport = qla2x00_find_fcport_by_nportid
1704 (vha, &ea->id, 1);
cd4ed6b4 1705 if (fcport) {
cb873ba4 1706 fcport->scan_needed = 1;
cd4ed6b4
QT		 1707 fcport->rscn_gen++;
1708 }
bee8b846 1709
f352eeb7
QT		 1710 spin_lock_irqsave(&vha->work_lock, flags);
1711 if (vha->scan.scan_flags == 0) {
1712 ql_dbg(ql_dbg_disc, vha, 0xffff,
1713 "%s: schedule\n", __func__);
1714 vha->scan.scan_flags |= SF_QUEUED;
1715 schedule_delayed_work(&vha->scan.scan_work, 5);
41dc529a 1716 }
f352eeb7 1717 spin_unlock_irqrestore(&vha->work_lock, flags);
d4f7a16a 1718 }
726b8548 1719 break;
726b8548
QT		 1720 case FCME_GNL_DONE:
1721 qla24xx_handle_gnl_done_event(vha, ea);
1722 break;
1723 case FCME_GPSC_DONE:
a4239945 1724 qla24xx_handle_gpsc_event(vha, ea);
726b8548
QT		 1725 break;
1726 case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */
1727 qla24xx_handle_plogi_done_event(vha, ea);
1728 break;
a5d42f4c
DG		 1729 case FCME_PRLI_DONE:
1730 qla24xx_handle_prli_done_event(vha, ea);
1731 break;
726b8548
QT		 1732 case FCME_GPDB_DONE:
1733 qla24xx_handle_gpdb_event(vha, ea);
1734 break;
1735 case FCME_GPNID_DONE:
1736 qla24xx_handle_gpnid_event(vha, ea);
1737 break;
d3bae931
DG		 1738 case FCME_GFFID_DONE:
1739 qla24xx_handle_gffid_event(vha, ea);
1740 break;
f13515ac
QT		 1741 case FCME_ADISC_DONE:
1742 qla24xx_handle_adisc_event(vha, ea);
1743 break;
a4239945
QT		 1744 case FCME_GNNID_DONE:
1745 qla24xx_handle_gnnid_event(vha, ea);
1746 break;
1747 case FCME_GFPNID_DONE:
1748 qla24xx_handle_gfpnid_event(vha, ea);
1749 break;
8777e431
QT		 1750 case FCME_ELS_PLOGI_DONE:
1751 qla_handle_els_plogi_done(vha, ea);
1752 break;
726b8548
QT		 1753 default:
1754 BUG_ON(1);
1755 break;
1756 }
5ff1d584
AV		 1757}
1758
d4f7a16a
HM		 1759/*
1760 * RSCN(s) came in for this fcport, but the RSCN(s) was not able
1761 * to be consumed by the fcport
1762 */
1763void qla_rscn_replay(fc_port_t *fcport)
1764{
2703eaaf
BVA		 1765 struct event_arg ea;
1766
1767 switch (fcport->disc_state) {
1768 case DSC_DELETE_PEND:
1769 return;
1770 default:
1771 break;
1772 }
1773
1774 if (fcport->scan_needed) {
1775 memset(&ea, 0, sizeof(ea));
1776 ea.event = FCME_RSCN;
1777 ea.id = fcport->d_id;
1778 ea.id.b.rsvd_1 = RSCN_PORT_ADDR;
1779 qla2x00_fcport_event_handler(fcport->vha, &ea);
861d483d 1780 }
d4f7a16a
HM		 1781}
1782
3822263e 1783static void
faef62d1 1784qla2x00_tmf_iocb_timeout(void *data)
3822263e 1785{
25ff6af1 1786 srb_t *sp = data;
faef62d1 1787 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 1788
faef62d1
AB		 1789 tmf->u.tmf.comp_status = CS_TIMEOUT;
1790 complete(&tmf->u.tmf.comp);
1791}
9ba56b95 1792
6c18a43e 1793static void qla2x00_tmf_sp_done(srb_t *sp, int res)
faef62d1 1794{
faef62d1 1795 struct srb_iocb *tmf = &sp->u.iocb_cmd;
25ff6af1 1796
faef62d1 1797 complete(&tmf->u.tmf.comp);
3822263e
MI		 1798}
1799
1800int
faef62d1 1801qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 1802 uint32_t tag)
1803{
1804 struct scsi_qla_host *vha = fcport->vha;
faef62d1 1805 struct srb_iocb *tm_iocb;
3822263e 1806 srb_t *sp;
faef62d1 1807 int rval = QLA_FUNCTION_FAILED;
3822263e 1808
9ba56b95 1809 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 1810 if (!sp)
1811 goto done;
1812
faef62d1 1813 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 1814 sp->type = SRB_TM_CMD;
1815 sp->name = "tmf";
e74e7d95
BH		 1816
1817 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1818 init_completion(&tm_iocb->u.tmf.comp);
faef62d1 1819 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
e74e7d95 1820
faef62d1
AB		 1821 tm_iocb->u.tmf.flags = flags;
1822 tm_iocb->u.tmf.lun = lun;
1823 tm_iocb->u.tmf.data = tag;
1824 sp->done = qla2x00_tmf_sp_done;
3822263e 1825
7c3df132 1826 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 1827 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1828 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1829 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1 1830
9fe278f4
GM		 1831 rval = qla2x00_start_sp(sp);
1832 if (rval != QLA_SUCCESS)
1833 goto done_free_sp;
faef62d1
AB		 1834 wait_for_completion(&tm_iocb->u.tmf.comp);
1835
b4146c49 1836 rval = tm_iocb->u.tmf.data;
faef62d1 1837
b4146c49
AG		 1838 if (rval != QLA_SUCCESS) {
1839 ql_log(ql_log_warn, vha, 0x8030,
faef62d1
AB		 1840 "TM IOCB failed (%x).\n", rval);
1841 }
1842
1843 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1844 flags = tm_iocb->u.tmf.flags;
1845 lun = (uint16_t)tm_iocb->u.tmf.lun;
1846
1847 /* Issue Marker IOCB */
9eb9c6dc 1848 qla2x00_marker(vha, vha->hw->base_qpair,
92fff53b 1849 fcport->loop_id, lun,
faef62d1
AB		 1850 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1851 }
3822263e
MI		 1852
1853done_free_sp:
25ff6af1 1854 sp->free(sp);
388a4995 1855 fcport->flags &= ~FCF_ASYNC_SENT;
3822263e
MI		 1856done:
1857 return rval;
1858}
1859
4440e46d
AB		 1860int
1861qla24xx_async_abort_command(srb_t *sp)
1862{
1863 unsigned long flags = 0;
1864
1865 uint32_t handle;
1866 fc_port_t *fcport = sp->fcport;
585def9b 1867 struct qla_qpair *qpair = sp->qpair;
4440e46d 1868 struct scsi_qla_host *vha = fcport->vha;
585def9b 1869 struct req_que *req = qpair->req;
b027a5ac 1870
585def9b 1871 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
4440e46d
AB		 1872 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1873 if (req->outstanding_cmds[handle] == sp)
1874 break;
1875 }
585def9b
QT		 1876 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1877
4440e46d
AB		 1878 if (handle == req->num_outstanding_cmds) {
1879 /* Command not found. */
1880 return QLA_FUNCTION_FAILED;
1881 }
1882 if (sp->type == SRB_FXIOCB_DCMD)
1883 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1884 FXDISC_ABORT_IOCTL);
1885
f6145e86 1886 return qla24xx_async_abort_cmd(sp, true);
4440e46d
AB		 1887}
1888
a5d42f4c
DG		 1889static void
1890qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
1891{
1892 switch (ea->data[0]) {
1893 case MBS_COMMAND_COMPLETE:
1894 ql_dbg(ql_dbg_disc, vha, 0x2118,
1895 "%s %d %8phC post gpdb\n",
1896 __func__, __LINE__, ea->fcport->port_name);
1897
1898 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1899 ea->fcport->logout_on_delete = 1;
03aaa89f
DT		 1900 ea->fcport->nvme_prli_service_param = ea->iop[0];
1901 if (ea->iop[0] & NVME_PRLI_SP_FIRST_BURST)
1902 ea->fcport->nvme_first_burst_size =
1903 (ea->iop[1] & 0xffff) * 512;
1904 else
1905 ea->fcport->nvme_first_burst_size = 0;
a5d42f4c
DG		 1906 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1907 break;
1908 default:
1cbc0efc
DT		 1909 if ((ea->iop[0] == LSC_SCODE_ELS_REJECT) &&
1910 (ea->iop[1] == 0x50000)) { /* reson 5=busy expl:0x0 */
1911 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1912 ea->fcport->fw_login_state = DSC_LS_PLOGI_COMP;
1913 break;
1914 }
1915
edd05de1
DG		 1916 if (ea->fcport->n2n_flag) {
1917 ql_dbg(ql_dbg_disc, vha, 0x2118,
1918 "%s %d %8phC post fc4 prli\n",
1919 __func__, __LINE__, ea->fcport->port_name);
1920 ea->fcport->fc4f_nvme = 0;
1921 ea->fcport->n2n_flag = 0;
1922 qla24xx_post_prli_work(vha, ea->fcport);
1923 }
a5d42f4c
DG		 1924 ql_dbg(ql_dbg_disc, vha, 0x2119,
1925 "%s %d %8phC unhandle event of %x\n",
1926 __func__, __LINE__, ea->fcport->port_name, ea->data[0]);
1927 break;
1928 }
1929}
1930
726b8548
QT		 1931static void
1932qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
ac280b67 1933{
726b8548 1934 port_id_t cid; /* conflict Nport id */
a084fd68
QT		 1935 u16 lid;
1936 struct fc_port *conflict_fcport;
82abdcaf 1937 unsigned long flags;
a4239945
QT		 1938 struct fc_port *fcport = ea->fcport;
1939
f352eeb7
QT		 1940 ql_dbg(ql_dbg_disc, vha, 0xffff,
1941 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n",
1942 __func__, fcport->port_name, fcport->disc_state,
1943 fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen,
861d483d 1944 ea->sp->gen1, fcport->rscn_gen,
f352eeb7
QT		 1945 ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]);
1946
a4239945
QT		 1947 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
1948 (fcport->fw_login_state == DSC_LS_PRLI_PEND)) {
1949 ql_dbg(ql_dbg_disc, vha, 0x20ea,
1950 "%s %d %8phC Remote is trying to login\n",
1951 __func__, __LINE__, fcport->port_name);
1952 return;
1953 }
1954
8b5292bc
QT		 1955 if ((fcport->disc_state == DSC_DELETE_PEND) ||
1956 (fcport->disc_state == DSC_DELETED)) {
1957 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
a4239945 1958 return;
8b5292bc 1959 }
a4239945
QT		 1960
1961 if (ea->sp->gen2 != fcport->login_gen) {
1962 /* target side must have changed it. */
1963 ql_dbg(ql_dbg_disc, vha, 0x20d3,
f352eeb7
QT		 1964 "%s %8phC generation changed\n",
1965 __func__, fcport->port_name);
1966 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
a4239945
QT		 1967 return;
1968 } else if (ea->sp->gen1 != fcport->rscn_gen) {
861d483d
QT		 1969 ql_dbg(ql_dbg_disc, vha, 0x20d3,
1970 "%s %8phC RSCN generation changed\n",
1971 __func__, fcport->port_name);
d4f7a16a 1972 qla_rscn_replay(fcport);
861d483d 1973 qlt_schedule_sess_for_deletion(fcport);
a4239945
QT		 1974 return;
1975 }
ac280b67 1976
726b8548 1977 switch (ea->data[0]) {
ac280b67 1978 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 1979 /*
1980 * Driver must validate login state - If PRLI not complete,
1981 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
1982 * requests.
1983 */
a5d42f4c
DG		 1984 if (ea->fcport->fc4f_nvme) {
1985 ql_dbg(ql_dbg_disc, vha, 0x2117,
1986 "%s %d %8phC post prli\n",
1987 __func__, __LINE__, ea->fcport->port_name);
1988 qla24xx_post_prli_work(vha, ea->fcport);
1989 } else {
1990 ql_dbg(ql_dbg_disc, vha, 0x20ea,
a084fd68
QT		 1991 "%s %d %8phC LoopID 0x%x in use with %06x. post gnl\n",
1992 __func__, __LINE__, ea->fcport->port_name,
1993 ea->fcport->loop_id, ea->fcport->d_id.b24);
1994
1995 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
82abdcaf 1996 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a5d42f4c
DG		 1997 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1998 ea->fcport->logout_on_delete = 1;
3515832c 1999 ea->fcport->send_els_logo = 0;
82abdcaf
QT		 2000 ea->fcport->fw_login_state = DSC_LS_PRLI_COMP;
2001 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
2002
a5d42f4c
DG		 2003 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
2004 }
ac280b67
AV		 2005 break;
2006 case MBS_COMMAND_ERROR:
83548fe2 2007 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n",
726b8548
QT		 2008 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
2009
2010 ea->fcport->flags &= ~FCF_ASYNC_SENT;
2011 ea->fcport->disc_state = DSC_LOGIN_FAILED;
2012 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
ac280b67
AV		 2013 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
2014 else
726b8548 2015 qla2x00_mark_device_lost(vha, ea->fcport, 1, 0);
ac280b67
AV		 2016 break;
2017 case MBS_LOOP_ID_USED:
726b8548
QT		 2018 /* data[1] = IO PARAM 1 = nport ID */
2019 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
2020 cid.b.area = (ea->iop[1] >> 8) & 0xff;
2021 cid.b.al_pa = ea->iop[1] & 0xff;
2022 cid.b.rsvd_1 = 0;
2023
83548fe2 2024 ql_dbg(ql_dbg_disc, vha, 0x20ec,
5c640053 2025 "%s %d %8phC lid %#x in use with pid %06x post gnl\n",
83548fe2 2026 __func__, __LINE__, ea->fcport->port_name,
5c640053 2027 ea->fcport->loop_id, cid.b24);
726b8548 2028
5c640053
QT		 2029 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
2030 ea->fcport->loop_id = FC_NO_LOOP_ID;
726b8548
QT		 2031 qla24xx_post_gnl_work(vha, ea->fcport);
2032 break;
2033 case MBS_PORT_ID_USED:
a084fd68
QT		 2034 lid = ea->iop[1] & 0xffff;
2035 qlt_find_sess_invalidate_other(vha,
2036 wwn_to_u64(ea->fcport->port_name),
2037 ea->fcport->d_id, lid, &conflict_fcport);
2038
2039 if (conflict_fcport) {
2040 /*
2041 * Another fcport share the same loop_id/nport id.
2042 * Conflict fcport needs to finish cleanup before this
2043 * fcport can proceed to login.
2044 */
2045 conflict_fcport->conflict = ea->fcport;
2046 ea->fcport->login_pause = 1;
2047
2048 ql_dbg(ql_dbg_disc, vha, 0x20ed,
2049 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. post gidpn\n",
2050 __func__, __LINE__, ea->fcport->port_name,
2051 ea->fcport->d_id.b24, lid);
a084fd68
QT		 2052 } else {
2053 ql_dbg(ql_dbg_disc, vha, 0x20ed,
2054 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n",
2055 __func__, __LINE__, ea->fcport->port_name,
2056 ea->fcport->d_id.b24, lid);
2057
2058 qla2x00_clear_loop_id(ea->fcport);
2059 set_bit(lid, vha->hw->loop_id_map);
2060 ea->fcport->loop_id = lid;
2061 ea->fcport->keep_nport_handle = 0;
94cff6e1 2062 qlt_schedule_sess_for_deletion(ea->fcport);
a084fd68 2063 }
ac280b67
AV		 2064 break;
2065 }
4916392b 2066 return;
ac280b67
AV		 2067}
2068
4916392b 2069void
ac280b67
AV		 2070qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
2071 uint16_t *data)
2072{
a6ca8878 2073 qlt_logo_completion_handler(fcport, data[0]);
726b8548 2074 fcport->login_gen++;
fa83e658 2075 fcport->flags &= ~FCF_ASYNC_ACTIVE;
4916392b 2076 return;
ac280b67
AV		 2077}
2078
1da177e4
LT		 2079/****************************************************************************/
2080/* QLogic ISP2x00 Hardware Support Functions. */
2081/****************************************************************************/
2082
fa492630 2083static int
7d613ac6
SV		 2084qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
2085{
2086 int rval = QLA_SUCCESS;
2087 struct qla_hw_data *ha = vha->hw;
2088 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 2089 uint16_t config[4];
7d613ac6
SV		 2090
2091 qla83xx_idc_lock(vha, 0);
2092
2093 /* SV: TODO: Assign initialization timeout from
2094 * flash-info / other param
2095 */
2096 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
2097 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
2098
2099 /* Set our fcoe function presence */
2100 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
2101 ql_dbg(ql_dbg_p3p, vha, 0xb077,
2102 "Error while setting DRV-Presence.\n");
2103 rval = QLA_FUNCTION_FAILED;
2104 goto exit;
2105 }
2106
2107 /* Decide the reset ownership */
2108 qla83xx_reset_ownership(vha);
2109
2110 /*
2111 * On first protocol driver load:
2112 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
2113 * register.
2114 * Others: Check compatibility with current IDC Major version.
2115 */
2116 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
2117 if (ha->flags.nic_core_reset_owner) {
2118 /* Set IDC Major version */
2119 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
2120 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
2121
2122 /* Clearing IDC-Lock-Recovery register */
2123 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
2124 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
2125 /*
2126 * Clear further IDC participation if we are not compatible with
2127 * the current IDC Major Version.
2128 */
2129 ql_log(ql_log_warn, vha, 0xb07d,
2130 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
2131 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
2132 __qla83xx_clear_drv_presence(vha);
2133 rval = QLA_FUNCTION_FAILED;
2134 goto exit;
2135 }
2136 /* Each function sets its supported Minor version. */
2137 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
2138 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
2139 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
2140
711aa7f7
SK		 2141 if (ha->flags.nic_core_reset_owner) {
2142 memset(config, 0, sizeof(config));
2143 if (!qla81xx_get_port_config(vha, config))
2144 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
2145 QLA8XXX_DEV_READY);
2146 }
2147
7d613ac6
SV		 2148 rval = qla83xx_idc_state_handler(vha);
2149
2150exit:
2151 qla83xx_idc_unlock(vha, 0);
2152
2153 return rval;
2154}
2155
1da177e4
LT		 2156/*
2157* qla2x00_initialize_adapter
2158* Initialize board.
2159*
2160* Input:
2161* ha = adapter block pointer.
2162*
2163* Returns:
2164* 0 = success
2165*/
2166int
e315cd28 2167qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 2168{
2169 int rval;
e315cd28 2170 struct qla_hw_data *ha = vha->hw;
73208dfd 2171 struct req_que *req = ha->req_q_map[0];
3f006ac3 2172 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2533cf67 2173
fc90adaf
JC		 2174 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
2175 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
2176
1da177e4 2177 /* Clear adapter flags. */
e315cd28 2178 vha->flags.online = 0;
2533cf67 2179 ha->flags.chip_reset_done = 0;
e315cd28 2180 vha->flags.reset_active = 0;
85880801
AV		 2181 ha->flags.pci_channel_io_perm_failure = 0;
2182 ha->flags.eeh_busy = 0;
fabbb8df 2183 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 2184 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
2185 atomic_set(&vha->loop_state, LOOP_DOWN);
2186 vha->device_flags = DFLG_NO_CABLE;
2187 vha->dpc_flags = 0;
2188 vha->flags.management_server_logged_in = 0;
2189 vha->marker_needed = 0;
1da177e4
LT		 2190 ha->isp_abort_cnt = 0;
2191 ha->beacon_blink_led = 0;
2192
73208dfd
AC		 2193 set_bit(0, ha->req_qid_map);
2194 set_bit(0, ha->rsp_qid_map);
2195
cfb0919c 2196 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 2197 "Configuring PCI space...\n");
e315cd28 2198 rval = ha->isp_ops->pci_config(vha);
1da177e4 2199 if (rval) {
7c3df132
SK		 2200 ql_log(ql_log_warn, vha, 0x0044,
2201 "Unable to configure PCI space.\n");
1da177e4
LT		 2202 return (rval);
2203 }
2204
e315cd28 2205 ha->isp_ops->reset_chip(vha);
1da177e4 2206
3f006ac3
MH		 2207 /* Check for secure flash support */
2208 if (IS_QLA28XX(ha)) {
2209 if (RD_REG_DWORD(&reg->mailbox12) & BIT_0) {
2210 ql_log(ql_log_info, vha, 0xffff, "Adapter is Secure\n");
2211 ha->flags.secure_adapter = 1;
2212 }
2213 }
2214
2215
e315cd28 2216 rval = qla2xxx_get_flash_info(vha);
c00d8994 2217 if (rval) {
7c3df132
SK		 2218 ql_log(ql_log_fatal, vha, 0x004f,
2219 "Unable to validate FLASH data.\n");
7ec0effd
AD		 2220 return rval;
2221 }
2222
2223 if (IS_QLA8044(ha)) {
2224 qla8044_read_reset_template(vha);
2225
2226 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
2227 * If DONRESET_BIT0 is set, drivers should not set dev_state
2228 * to NEED_RESET. But if NEED_RESET is set, drivers should
2229 * should honor the reset. */
2230 if (ql2xdontresethba == 1)
2231 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 2232 }
2233
73208dfd 2234 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 2235 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 2236 "Configure NVRAM parameters...\n");
0107109e 2237
e315cd28 2238 ha->isp_ops->nvram_config(vha);
1da177e4 2239
d4c760c2
AV		 2240 if (ha->flags.disable_serdes) {
2241 /* Mask HBA via NVRAM settings? */
7c3df132 2242 ql_log(ql_log_info, vha, 0x0077,
7b833558 2243 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 2244 return QLA_FUNCTION_FAILED;
2245 }
2246
cfb0919c 2247 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 2248 "Verifying loaded RISC code...\n");
1da177e4 2249
e315cd28
AC		 2250 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
2251 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 2252 if (rval)
2253 return (rval);
e315cd28 2254 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 2255 if (rval)
2256 return (rval);
1da177e4 2257 }
a9083016 2258
4d4df193 2259 if (IS_QLA84XX(ha)) {
e315cd28 2260 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 2261 if (!ha->cs84xx) {
7c3df132 2262 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 2263 "Unable to configure ISP84XX.\n");
2264 return QLA_FUNCTION_FAILED;
2265 }
2266 }
2d70c103 2267
ead03855 2268 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2d70c103
NB		 2269 rval = qla2x00_init_rings(vha);
2270
26a77799
AV		 2271 /* No point in continuing if firmware initialization failed. */
2272 if (rval != QLA_SUCCESS)
2273 return rval;
2274
2533cf67 2275 ha->flags.chip_reset_done = 1;
1da177e4 2276
9a069e19 2277 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 2278 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 2279 rval = qla84xx_init_chip(vha);
2280 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2281 ql_log(ql_log_warn, vha, 0x00d4,
2282 "Unable to initialize ISP84XX.\n");
8d2b21db 2283 qla84xx_put_chip(vha);
9a069e19
GM		 2284 }
2285 }
2286
7d613ac6
SV		 2287 /* Load the NIC Core f/w if we are the first protocol driver. */
2288 if (IS_QLA8031(ha)) {
2289 rval = qla83xx_nic_core_fw_load(vha);
2290 if (rval)
2291 ql_log(ql_log_warn, vha, 0x0124,
2292 "Error in initializing NIC Core f/w.\n");
2293 }
2294
2f0f3f4f
MI		 2295 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
2296 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 2297
c46e65c7
JC		 2298 if (IS_P3P_TYPE(ha))
2299 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
2300 else
2301 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
2302
1da177e4
LT		 2303 return (rval);
2304}
2305
2306/**
abbd8870 2307 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
2db6228d 2308 * @vha: HA context
1da177e4
LT		 2309 *
2310 * Returns 0 on success.
2311 */
abbd8870 2312int
e315cd28 2313qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 2314{
a157b101 2315 uint16_t w;
abbd8870 2316 unsigned long flags;
e315cd28 2317 struct qla_hw_data *ha = vha->hw;
3d71644c 2318 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2319
1da177e4 2320 pci_set_master(ha->pdev);
af6177d8 2321 pci_try_set_mwi(ha->pdev);
1da177e4 2322
1da177e4 2323 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2324 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 2325 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2326
737faece 2327 pci_disable_rom(ha->pdev);
1da177e4
LT		 2328
2329 /* Get PCI bus information. */
2330 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 2331 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 2332 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2333
abbd8870
AV		 2334 return QLA_SUCCESS;
2335}
1da177e4 2336
abbd8870
AV		 2337/**
2338 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
2db6228d 2339 * @vha: HA context
abbd8870
AV		 2340 *
2341 * Returns 0 on success.
2342 */
2343int
e315cd28 2344qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 2345{
a157b101 2346 uint16_t w;
abbd8870
AV		 2347 unsigned long flags = 0;
2348 uint32_t cnt;
e315cd28 2349 struct qla_hw_data *ha = vha->hw;
3d71644c 2350 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2351
abbd8870 2352 pci_set_master(ha->pdev);
af6177d8 2353 pci_try_set_mwi(ha->pdev);
1da177e4 2354
abbd8870 2355 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2356 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 2357
abbd8870
AV		 2358 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2359 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 2360 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 2361
abbd8870
AV		 2362 /*
2363 * If this is a 2300 card and not 2312, reset the
2364 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
2365 * the 2310 also reports itself as a 2300 so we need to get the
2366 * fb revision level -- a 6 indicates it really is a 2300 and
2367 * not a 2310.
2368 */
2369 if (IS_QLA2300(ha)) {
2370 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 2371
abbd8870 2372 /* Pause RISC. */
3d71644c 2373 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 2374 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 2375 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 2376 break;
1da177e4 2377
abbd8870
AV		 2378 udelay(10);
2379 }
1da177e4 2380
abbd8870 2381 /* Select FPM registers. */
3d71644c
AV		 2382 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2383 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2384
2385 /* Get the fb rev level */
3d71644c 2386 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 2387
2388 if (ha->fb_rev == FPM_2300)
a157b101 2389 pci_clear_mwi(ha->pdev);
abbd8870
AV		 2390
2391 /* Deselect FPM registers. */
3d71644c
AV		 2392 WRT_REG_WORD(&reg->ctrl_status, 0x0);
2393 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2394
2395 /* Release RISC module. */
3d71644c 2396 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 2397 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 2398 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 2399 break;
2400
2401 udelay(10);
1da177e4 2402 }
1da177e4 2403
abbd8870
AV		 2404 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2405 }
1da177e4 2406
abbd8870
AV		 2407 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2408
737faece 2409 pci_disable_rom(ha->pdev);
1da177e4 2410
abbd8870
AV		 2411 /* Get PCI bus information. */
2412 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 2413 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2414 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2415
2416 return QLA_SUCCESS;
1da177e4
LT		 2417}
2418
0107109e
AV		 2419/**
2420 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
2db6228d 2421 * @vha: HA context
0107109e
AV		 2422 *
2423 * Returns 0 on success.
2424 */
2425int
e315cd28 2426qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 2427{
a157b101 2428 uint16_t w;
0107109e 2429 unsigned long flags = 0;
e315cd28 2430 struct qla_hw_data *ha = vha->hw;
0107109e 2431 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 2432
2433 pci_set_master(ha->pdev);
af6177d8 2434 pci_try_set_mwi(ha->pdev);
0107109e
AV		 2435
2436 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2437 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 2438 w &= ~PCI_COMMAND_INTX_DISABLE;
2439 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2440
2441 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2442
2443 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 2444 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
2445 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 2446
2447 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 2448 if (pci_is_pcie(ha->pdev))
5ffd3a52 2449 pcie_set_readrq(ha->pdev, 4096);
0107109e 2450
737faece 2451 pci_disable_rom(ha->pdev);
0107109e 2452
44c10138 2453 ha->chip_revision = ha->pdev->revision;
a8488abe 2454
0107109e
AV		 2455 /* Get PCI bus information. */
2456 spin_lock_irqsave(&ha->hardware_lock, flags);
2457 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
2458 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2459
2460 return QLA_SUCCESS;
2461}
2462
c3a2f0df
AV		 2463/**
2464 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
2db6228d 2465 * @vha: HA context
c3a2f0df
AV		 2466 *
2467 * Returns 0 on success.
2468 */
2469int
e315cd28 2470qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 2471{
2472 uint16_t w;
e315cd28 2473 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 2474
2475 pci_set_master(ha->pdev);
2476 pci_try_set_mwi(ha->pdev);
2477
2478 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2479 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2480 w &= ~PCI_COMMAND_INTX_DISABLE;
2481 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2482
2483 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 2484 if (pci_is_pcie(ha->pdev))
5ffd3a52 2485 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 2486
737faece 2487 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 2488
2489 ha->chip_revision = ha->pdev->revision;
2490
2491 return QLA_SUCCESS;
2492}
2493
1da177e4
LT		 2494/**
2495 * qla2x00_isp_firmware() - Choose firmware image.
2db6228d 2496 * @vha: HA context
1da177e4
LT		 2497 *
2498 * Returns 0 on success.
2499 */
2500static int
e315cd28 2501qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 2502{
2503 int rval;
42e421b1
AV		 2504 uint16_t loop_id, topo, sw_cap;
2505 uint8_t domain, area, al_pa;
e315cd28 2506 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2507
2508 /* Assume loading risc code */
fa2a1ce5 2509 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 2510
2511 if (ha->flags.disable_risc_code_load) {
7c3df132 2512 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 2513
2514 /* Verify checksum of loaded RISC code. */
e315cd28 2515 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 2516 if (rval == QLA_SUCCESS) {
2517 /* And, verify we are not in ROM code. */
e315cd28 2518 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 2519 &area, &domain, &topo, &sw_cap);
2520 }
1da177e4
LT		 2521 }
2522
7c3df132
SK		 2523 if (rval)
2524 ql_dbg(ql_dbg_init, vha, 0x007a,
2525 "**** Load RISC code ****.\n");
1da177e4
LT		 2526
2527 return (rval);
2528}
2529
2530/**
2531 * qla2x00_reset_chip() - Reset ISP chip.
2db6228d 2532 * @vha: HA context
1da177e4
LT		 2533 *
2534 * Returns 0 on success.
2535 */
3f006ac3 2536int
e315cd28 2537qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 2538{
2539 unsigned long flags = 0;
e315cd28 2540 struct qla_hw_data *ha = vha->hw;
3d71644c 2541 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2542 uint32_t cnt;
1da177e4 2543 uint16_t cmd;
3f006ac3 2544 int rval = QLA_FUNCTION_FAILED;
1da177e4 2545
85880801 2546 if (unlikely(pci_channel_offline(ha->pdev)))
3f006ac3 2547 return rval;
85880801 2548
fd34f556 2549 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 2550
2551 spin_lock_irqsave(&ha->hardware_lock, flags);
2552
2553 /* Turn off master enable */
2554 cmd = 0;
2555 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
2556 cmd &= ~PCI_COMMAND_MASTER;
2557 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2558
2559 if (!IS_QLA2100(ha)) {
2560 /* Pause RISC. */
2561 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2562 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
2563 for (cnt = 0; cnt < 30000; cnt++) {
2564 if ((RD_REG_WORD(&reg->hccr) &
2565 HCCR_RISC_PAUSE) != 0)
2566 break;
2567 udelay(100);
2568 }
2569 } else {
2570 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2571 udelay(10);
2572 }
2573
2574 /* Select FPM registers. */
2575 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2576 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2577
2578 /* FPM Soft Reset. */
2579 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
2580 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2581
2582 /* Toggle Fpm Reset. */
2583 if (!IS_QLA2200(ha)) {
2584 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
2585 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2586 }
2587
2588 /* Select frame buffer registers. */
2589 WRT_REG_WORD(&reg->ctrl_status, 0x10);
2590 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2591
2592 /* Reset frame buffer FIFOs. */
2593 if (IS_QLA2200(ha)) {
2594 WRT_FB_CMD_REG(ha, reg, 0xa000);
2595 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
2596 } else {
2597 WRT_FB_CMD_REG(ha, reg, 0x00fc);
2598
2599 /* Read back fb_cmd until zero or 3 seconds max */
2600 for (cnt = 0; cnt < 3000; cnt++) {
2601 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
2602 break;
2603 udelay(100);
2604 }
2605 }
2606
2607 /* Select RISC module registers. */
2608 WRT_REG_WORD(&reg->ctrl_status, 0);
2609 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2610
2611 /* Reset RISC processor. */
2612 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2613 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2614
2615 /* Release RISC processor. */
2616 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2617 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2618 }
2619
2620 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
2621 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
2622
2623 /* Reset ISP chip. */
2624 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2625
2626 /* Wait for RISC to recover from reset. */
2627 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2628 /*
2629 * It is necessary to for a delay here since the card doesn't
2630 * respond to PCI reads during a reset. On some architectures
2631 * this will result in an MCA.
2632 */
2633 udelay(20);
2634 for (cnt = 30000; cnt; cnt--) {
2635 if ((RD_REG_WORD(&reg->ctrl_status) &
2636 CSR_ISP_SOFT_RESET) == 0)
2637 break;
2638 udelay(100);
2639 }
2640 } else
2641 udelay(10);
2642
2643 /* Reset RISC processor. */
2644 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2645
2646 WRT_REG_WORD(&reg->semaphore, 0);
2647
2648 /* Release RISC processor. */
2649 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2650 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2651
2652 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2653 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 2654 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 2655 break;
1da177e4
LT		 2656
2657 udelay(100);
2658 }
2659 } else
2660 udelay(100);
2661
2662 /* Turn on master enable */
2663 cmd |= PCI_COMMAND_MASTER;
2664 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2665
2666 /* Disable RISC pause on FPM parity error. */
2667 if (!IS_QLA2100(ha)) {
2668 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
2669 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2670 }
2671
2672 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3f006ac3
MH		 2673
2674 return QLA_SUCCESS;
1da177e4
LT		 2675}
2676
b1d46989
MI		 2677/**
2678 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
2db6228d 2679 * @vha: HA context
b1d46989
MI		 2680 *
2681 * Returns 0 on success.
2682 */
fa492630 2683static int
b1d46989
MI		 2684qla81xx_reset_mpi(scsi_qla_host_t *vha)
2685{
2686 uint16_t mb[4] = {0x1010, 0, 1, 0};
2687
6246b8a1
GM		 2688 if (!IS_QLA81XX(vha->hw))
2689 return QLA_SUCCESS;
2690
b1d46989
MI		 2691 return qla81xx_write_mpi_register(vha, mb);
2692}
2693
0107109e 2694/**
88c26663 2695 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
2db6228d 2696 * @vha: HA context
0107109e
AV		 2697 *
2698 * Returns 0 on success.
2699 */
d14e72fb 2700static inline int
e315cd28 2701qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 2702{
2703 unsigned long flags = 0;
e315cd28 2704 struct qla_hw_data *ha = vha->hw;
0107109e 2705 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 2706 uint32_t cnt;
335a1cc9 2707 uint16_t wd;
b1d46989 2708 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 2709 int rval = QLA_SUCCESS;
0107109e 2710
0107109e
AV		 2711 spin_lock_irqsave(&ha->hardware_lock, flags);
2712
2713 /* Reset RISC. */
2714 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2715 for (cnt = 0; cnt < 30000; cnt++) {
2716 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2717 break;
2718
2719 udelay(10);
2720 }
2721
d14e72fb
HM		 2722 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
2723 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2724
2725 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2726 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2727 RD_REG_DWORD(&reg->hccr),
2728 RD_REG_DWORD(&reg->ctrl_status),
2729 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
2730
0107109e
AV		 2731 WRT_REG_DWORD(&reg->ctrl_status,
2732 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 2733 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 2734
335a1cc9 2735 udelay(100);
d14e72fb 2736
88c26663 2737 /* Wait for firmware to complete NVRAM accesses. */
52c82823 2738 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 2739 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2740 rval == QLA_SUCCESS; cnt--) {
88c26663 2741 barrier();
d14e72fb
HM		 2742 if (cnt)
2743 udelay(5);
2744 else
2745 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 2746 }
2747
d14e72fb
HM		 2748 if (rval == QLA_SUCCESS)
2749 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2750
2751 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2752 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2753 RD_REG_DWORD(&reg->hccr),
2754 RD_REG_DWORD(&reg->mailbox0));
2755
335a1cc9 2756 /* Wait for soft-reset to complete. */
52c82823 2757 RD_REG_DWORD(&reg->ctrl_status);
200ffb15 2758 for (cnt = 0; cnt < 60; cnt++) {
0107109e 2759 barrier();
d14e72fb
HM		 2760 if ((RD_REG_DWORD(&reg->ctrl_status) &
2761 CSRX_ISP_SOFT_RESET) == 0)
2762 break;
2763
2764 udelay(5);
0107109e 2765 }
d14e72fb
HM		 2766 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
2767 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2768
2769 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2770 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2771 RD_REG_DWORD(&reg->hccr),
2772 RD_REG_DWORD(&reg->ctrl_status));
0107109e 2773
b1d46989
MI		 2774 /* If required, do an MPI FW reset now */
2775 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2776 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2777 if (++abts_cnt < 5) {
2778 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2779 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2780 } else {
2781 /*
2782 * We exhausted the ISP abort retries. We have to
2783 * set the board offline.
2784 */
2785 abts_cnt = 0;
2786 vha->flags.online = 0;
2787 }
2788 }
2789 }
2790
0107109e
AV		 2791 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2792 RD_REG_DWORD(&reg->hccr);
2793
2794 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2795 RD_REG_DWORD(&reg->hccr);
2796
2797 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2798 RD_REG_DWORD(&reg->hccr);
2799
52c82823 2800 RD_REG_WORD(&reg->mailbox0);
200ffb15 2801 for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
d14e72fb 2802 rval == QLA_SUCCESS; cnt--) {
0107109e 2803 barrier();
d14e72fb
HM		 2804 if (cnt)
2805 udelay(5);
2806 else
2807 rval = QLA_FUNCTION_TIMEOUT;
0107109e 2808 }
d14e72fb
HM		 2809 if (rval == QLA_SUCCESS)
2810 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2811
2812 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2813 "Host Risc 0x%x, mailbox0 0x%x\n",
2814 RD_REG_DWORD(&reg->hccr),
2815 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 2816
2817 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 2818
d14e72fb
HM		 2819 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2820 "Driver in %s mode\n",
2821 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2822
124f85e6
AV		 2823 if (IS_NOPOLLING_TYPE(ha))
2824 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 2825
2826 return rval;
0107109e
AV		 2827}
2828
4ea2c9c7
JC		 2829static void
2830qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2831{
2832 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2833
2834 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2835 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
2836
2837}
2838
2839static void
2840qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2841{
2842 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2843
2844 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2845 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
2846}
2847
2848static void
2849qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2850{
4ea2c9c7
JC		 2851 uint32_t wd32 = 0;
2852 uint delta_msec = 100;
2853 uint elapsed_msec = 0;
2854 uint timeout_msec;
2855 ulong n;
2856
cc790764
JC		 2857 if (vha->hw->pdev->subsystem_device != 0x0175 &&
2858 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 2859 return;
2860
8dd7e3a5
JC		 2861 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2862 udelay(100);
2863
4ea2c9c7
JC		 2864attempt:
2865 timeout_msec = TIMEOUT_SEMAPHORE;
2866 n = timeout_msec / delta_msec;
2867 while (n--) {
2868 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
2869 qla25xx_read_risc_sema_reg(vha, &wd32);
2870 if (wd32 & RISC_SEMAPHORE)
2871 break;
2872 msleep(delta_msec);
2873 elapsed_msec += delta_msec;
2874 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2875 goto force;
2876 }
2877
2878 if (!(wd32 & RISC_SEMAPHORE))
2879 goto force;
2880
2881 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2882 goto acquired;
2883
2884 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
2885 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
2886 n = timeout_msec / delta_msec;
2887 while (n--) {
2888 qla25xx_read_risc_sema_reg(vha, &wd32);
2889 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2890 break;
2891 msleep(delta_msec);
2892 elapsed_msec += delta_msec;
2893 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2894 goto force;
2895 }
2896
2897 if (wd32 & RISC_SEMAPHORE_FORCE)
2898 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
2899
2900 goto attempt;
2901
2902force:
2903 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
2904
2905acquired:
2906 return;
2907}
2908
88c26663
AV		 2909/**
2910 * qla24xx_reset_chip() - Reset ISP24xx chip.
2db6228d 2911 * @vha: HA context
88c26663
AV		 2912 *
2913 * Returns 0 on success.
2914 */
3f006ac3 2915int
e315cd28 2916qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 2917{
e315cd28 2918 struct qla_hw_data *ha = vha->hw;
3f006ac3 2919 int rval = QLA_FUNCTION_FAILED;
85880801
AV		 2920
2921 if (pci_channel_offline(ha->pdev) &&
2922 ha->flags.pci_channel_io_perm_failure) {
3f006ac3 2923 return rval;
85880801
AV		 2924 }
2925
fd34f556 2926 ha->isp_ops->disable_intrs(ha);
88c26663 2927
4ea2c9c7
JC		 2928 qla25xx_manipulate_risc_semaphore(vha);
2929
88c26663 2930 /* Perform RISC reset. */
3f006ac3
MH		 2931 rval = qla24xx_reset_risc(vha);
2932
2933 return rval;
88c26663
AV		 2934}
2935
1da177e4
LT		 2936/**
2937 * qla2x00_chip_diag() - Test chip for proper operation.
2db6228d 2938 * @vha: HA context
1da177e4
LT		 2939 *
2940 * Returns 0 on success.
2941 */
abbd8870 2942int
e315cd28 2943qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 2944{
2945 int rval;
e315cd28 2946 struct qla_hw_data *ha = vha->hw;
3d71644c 2947 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 2948 unsigned long flags = 0;
2949 uint16_t data;
2950 uint32_t cnt;
2951 uint16_t mb[5];
73208dfd 2952 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 2953
2954 /* Assume a failed state */
2955 rval = QLA_FUNCTION_FAILED;
2956
da4704d9
BVA		 2957 ql_dbg(ql_dbg_init, vha, 0x007b, "Testing device at %p.\n",
2958 &reg->flash_address);
1da177e4
LT		 2959
2960 spin_lock_irqsave(&ha->hardware_lock, flags);
2961
2962 /* Reset ISP chip. */
2963 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2964
2965 /*
2966 * We need to have a delay here since the card will not respond while
2967 * in reset causing an MCA on some architectures.
2968 */
2969 udelay(20);
2970 data = qla2x00_debounce_register(&reg->ctrl_status);
2971 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
2972 udelay(5);
2973 data = RD_REG_WORD(&reg->ctrl_status);
2974 barrier();
2975 }
2976
2977 if (!cnt)
2978 goto chip_diag_failed;
2979
7c3df132
SK		 2980 ql_dbg(ql_dbg_init, vha, 0x007c,
2981 "Reset register cleared by chip reset.\n");
1da177e4
LT		 2982
2983 /* Reset RISC processor. */
2984 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2985 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2986
2987 /* Workaround for QLA2312 PCI parity error */
2988 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2989 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
2990 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
2991 udelay(5);
2992 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 2993 barrier();
1da177e4
LT		 2994 }
2995 } else
2996 udelay(10);
2997
2998 if (!cnt)
2999 goto chip_diag_failed;
3000
3001 /* Check product ID of chip */
5a68a1c2 3002 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
1da177e4
LT		 3003
3004 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
3005 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
3006 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
3007 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
3008 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
3009 mb[3] != PROD_ID_3) {
7c3df132
SK		 3010 ql_log(ql_log_warn, vha, 0x0062,
3011 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
3012 mb[1], mb[2], mb[3]);
1da177e4
LT		 3013
3014 goto chip_diag_failed;
3015 }
3016 ha->product_id[0] = mb[1];
3017 ha->product_id[1] = mb[2];
3018 ha->product_id[2] = mb[3];
3019 ha->product_id[3] = mb[4];
3020
3021 /* Adjust fw RISC transfer size */
73208dfd 3022 if (req->length > 1024)
1da177e4
LT		 3023 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
3024 else
3025 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 3026 req->length;
1da177e4
LT		 3027
3028 if (IS_QLA2200(ha) &&
3029 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
3030 /* Limit firmware transfer size with a 2200A */
7c3df132 3031 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 3032
ea5b6382 3033 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 3034 ha->fw_transfer_size = 128;
3035 }
3036
3037 /* Wrap Incoming Mailboxes Test. */
3038 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3039
7c3df132 3040 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 3041 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 3042 if (rval)
3043 ql_log(ql_log_warn, vha, 0x0080,
3044 "Failed mailbox send register test.\n");
3045 else
1da177e4
LT		 3046 /* Flag a successful rval */
3047 rval = QLA_SUCCESS;
1da177e4
LT		 3048 spin_lock_irqsave(&ha->hardware_lock, flags);
3049
3050chip_diag_failed:
3051 if (rval)
7c3df132
SK		 3052 ql_log(ql_log_info, vha, 0x0081,
3053 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 3054
3055 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3056
3057 return (rval);
3058}
3059
0107109e
AV		 3060/**
3061 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
2db6228d 3062 * @vha: HA context
0107109e
AV		 3063 *
3064 * Returns 0 on success.
3065 */
3066int
e315cd28 3067qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 3068{
3069 int rval;
e315cd28 3070 struct qla_hw_data *ha = vha->hw;
73208dfd 3071 struct req_que *req = ha->req_q_map[0];
0107109e 3072
7ec0effd 3073 if (IS_P3P_TYPE(ha))
a9083016
GM		 3074 return QLA_SUCCESS;
3075
73208dfd 3076 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 3077
e315cd28 3078 rval = qla2x00_mbx_reg_test(vha);
0107109e 3079 if (rval) {
7c3df132
SK		 3080 ql_log(ql_log_warn, vha, 0x0082,
3081 "Failed mailbox send register test.\n");
0107109e
AV		 3082 } else {
3083 /* Flag a successful rval */
3084 rval = QLA_SUCCESS;
3085 }
3086
3087 return rval;
3088}
3089
ad0a0b01
QT		 3090static void
3091qla2x00_alloc_offload_mem(scsi_qla_host_t *vha)
0107109e 3092{
a7a167bf 3093 int rval;
df613b96
AV		 3094 dma_addr_t tc_dma;
3095 void *tc;
e315cd28 3096 struct qla_hw_data *ha = vha->hw;
a7a167bf 3097
ad0a0b01 3098 if (ha->eft) {
7c3df132 3099 ql_dbg(ql_dbg_init, vha, 0x00bd,
ad0a0b01
QT		 3100 "%s: Offload Mem is already allocated.\n",
3101 __func__);
a7a167bf
AV		 3102 return;
3103 }
d4e3e04d 3104
ad0a0b01 3105 if (IS_FWI2_CAPABLE(ha)) {
df613b96 3106 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695 3107 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
ecc89f25 3108 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
436a7b11 3109 goto try_eft;
df613b96 3110
f73cb695
CD		 3111 if (ha->fce)
3112 dma_free_coherent(&ha->pdev->dev,
3113 FCE_SIZE, ha->fce, ha->fce_dma);
3114
3115 /* Allocate memory for Fibre Channel Event Buffer. */
750afb08
LC		 3116 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
3117 GFP_KERNEL);
df613b96 3118 if (!tc) {
7c3df132
SK		 3119 ql_log(ql_log_warn, vha, 0x00be,
3120 "Unable to allocate (%d KB) for FCE.\n",
3121 FCE_SIZE / 1024);
17d98630 3122 goto try_eft;
df613b96
AV		 3123 }
3124
e315cd28 3125 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 3126 ha->fce_mb, &ha->fce_bufs);
3127 if (rval) {
7c3df132
SK		 3128 ql_log(ql_log_warn, vha, 0x00bf,
3129 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 3130 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
3131 tc_dma);
3132 ha->flags.fce_enabled = 0;
17d98630 3133 goto try_eft;
df613b96 3134 }
cfb0919c 3135 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 3136 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 3137
df613b96
AV		 3138 ha->flags.fce_enabled = 1;
3139 ha->fce_dma = tc_dma;
3140 ha->fce = tc;
f73cb695 3141
436a7b11 3142try_eft:
f73cb695
CD		 3143 if (ha->eft)
3144 dma_free_coherent(&ha->pdev->dev,
3145 EFT_SIZE, ha->eft, ha->eft_dma);
3146
436a7b11 3147 /* Allocate memory for Extended Trace Buffer. */
750afb08
LC		 3148 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
3149 GFP_KERNEL);
436a7b11 3150 if (!tc) {
7c3df132
SK		 3151 ql_log(ql_log_warn, vha, 0x00c1,
3152 "Unable to allocate (%d KB) for EFT.\n",
3153 EFT_SIZE / 1024);
ad0a0b01 3154 goto eft_err;
436a7b11
AV		 3155 }
3156
e315cd28 3157 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 3158 if (rval) {
7c3df132
SK		 3159 ql_log(ql_log_warn, vha, 0x00c2,
3160 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 3161 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
3162 tc_dma);
ad0a0b01 3163 goto eft_err;
436a7b11 3164 }
cfb0919c 3165 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 3166 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11 3167
436a7b11
AV		 3168 ha->eft_dma = tc_dma;
3169 ha->eft = tc;
d4e3e04d 3170 }
f73cb695 3171
ad0a0b01
QT		 3172eft_err:
3173 return;
3174}
3175
3176void
3177qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
3178{
a28d9e4e 3179 int rval;
ad0a0b01
QT		 3180 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
3181 eft_size, fce_size, mq_size;
3182 struct qla_hw_data *ha = vha->hw;
3183 struct req_que *req = ha->req_q_map[0];
3184 struct rsp_que *rsp = ha->rsp_q_map[0];
3185 struct qla2xxx_fw_dump *fw_dump;
a28d9e4e
JC		 3186 dma_addr_t tc_dma;
3187 void *tc;
ad0a0b01
QT		 3188
3189 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
3190 req_q_size = rsp_q_size = 0;
3191
3192 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3193 fixed_size = sizeof(struct qla2100_fw_dump);
3194 } else if (IS_QLA23XX(ha)) {
3195 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
3196 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
3197 sizeof(uint16_t);
3198 } else if (IS_FWI2_CAPABLE(ha)) {
ecc89f25 3199 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
ad0a0b01
QT		 3200 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
3201 else if (IS_QLA81XX(ha))
3202 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
3203 else if (IS_QLA25XX(ha))
3204 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
3205 else
3206 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
3207
3208 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
3209 sizeof(uint32_t);
3210 if (ha->mqenable) {
ecc89f25
JC		 3211 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) &&
3212 !IS_QLA28XX(ha))
ad0a0b01
QT		 3213 mq_size = sizeof(struct qla2xxx_mq_chain);
3214 /*
a4226ec3 3215 * Allocate maximum buffer size for all queues - Q0.
ad0a0b01
QT		 3216 * Resizing must be done at end-of-dump processing.
3217 */
a4226ec3 3218 mq_size += (ha->max_req_queues - 1) *
ad0a0b01 3219 (req->length * sizeof(request_t));
a4226ec3 3220 mq_size += (ha->max_rsp_queues - 1) *
ad0a0b01
QT		 3221 (rsp->length * sizeof(response_t));
3222 }
3223 if (ha->tgt.atio_ring)
3224 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
3225 /* Allocate memory for Fibre Channel Event Buffer. */
3226 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
ecc89f25 3227 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
ad0a0b01
QT		 3228 goto try_eft;
3229
3230 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
3231try_eft:
a28d9e4e
JC		 3232 if (ha->eft)
3233 dma_free_coherent(&ha->pdev->dev,
3234 EFT_SIZE, ha->eft, ha->eft_dma);
3235
3236 /* Allocate memory for Extended Trace Buffer. */
3237 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
3238 GFP_KERNEL);
3239 if (!tc) {
3240 ql_log(ql_log_warn, vha, 0x00c1,
3241 "Unable to allocate (%d KB) for EFT.\n",
3242 EFT_SIZE / 1024);
3243 goto allocate;
3244 }
3245
3246 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
3247 if (rval) {
3248 ql_log(ql_log_warn, vha, 0x00c2,
3249 "Unable to initialize EFT (%d).\n", rval);
3250 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
3251 tc_dma);
3252 }
ad0a0b01
QT		 3253 ql_dbg(ql_dbg_init, vha, 0x00c3,
3254 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
3255 eft_size = EFT_SIZE;
3256 }
3257
ecc89f25 3258 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
a28d9e4e
JC		 3259 struct fwdt *fwdt = ha->fwdt;
3260 uint j;
3261
3262 for (j = 0; j < 2; j++, fwdt++) {
3263 if (!fwdt->template) {
3264 ql_log(ql_log_warn, vha, 0x00ba,
3265 "-> fwdt%u no template\n", j);
3266 continue;
3267 }
3268 ql_dbg(ql_dbg_init, vha, 0x00fa,
3269 "-> fwdt%u calculating fwdump size...\n", j);
3270 fwdt->dump_size = qla27xx_fwdt_calculate_dump_size(
3271 vha, fwdt->template);
3272 ql_dbg(ql_dbg_init, vha, 0x00fa,
3273 "-> fwdt%u calculated fwdump size = %#lx bytes\n",
3274 j, fwdt->dump_size);
3275 dump_size += fwdt->dump_size;
f73cb695 3276 }
f73cb695
CD		 3277 goto allocate;
3278 }
3279
73208dfd
AC		 3280 req_q_size = req->length * sizeof(request_t);
3281 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 3282 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 3283 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 3284 ha->chain_offset = dump_size;
3285 dump_size += mq_size + fce_size;
d4e3e04d 3286
b945e777
QT		 3287 if (ha->exchoffld_buf)
3288 dump_size += sizeof(struct qla2xxx_offld_chain) +
3289 ha->exchoffld_size;
3290 if (ha->exlogin_buf)
3291 dump_size += sizeof(struct qla2xxx_offld_chain) +
3292 ha->exlogin_size;
3293
f73cb695 3294allocate:
a4226ec3
QT		 3295 if (!ha->fw_dump_len || dump_size > ha->fw_dump_alloc_len) {
3296
3297 ql_dbg(ql_dbg_init, vha, 0x00c5,
3298 "%s dump_size %d fw_dump_len %d fw_dump_alloc_len %d\n",
3299 __func__, dump_size, ha->fw_dump_len,
3300 ha->fw_dump_alloc_len);
3301
ad0a0b01
QT		 3302 fw_dump = vmalloc(dump_size);
3303 if (!fw_dump) {
3304 ql_log(ql_log_warn, vha, 0x00c4,
3305 "Unable to allocate (%d KB) for firmware dump.\n",
3306 dump_size / 1024);
3307 } else {
a6b95d1c 3308 mutex_lock(&ha->optrom_mutex);
a4226ec3
QT		 3309 if (ha->fw_dumped) {
3310 memcpy(fw_dump, ha->fw_dump, ha->fw_dump_len);
ad0a0b01 3311 vfree(ha->fw_dump);
a4226ec3
QT		 3312 ha->fw_dump = fw_dump;
3313 ha->fw_dump_alloc_len = dump_size;
3314 ql_dbg(ql_dbg_init, vha, 0x00c5,
3315 "Re-Allocated (%d KB) and save firmware dump.\n",
3316 dump_size / 1024);
3317 } else {
3318 if (ha->fw_dump)
3319 vfree(ha->fw_dump);
3320 ha->fw_dump = fw_dump;
3321
3322 ha->fw_dump_len = ha->fw_dump_alloc_len =
3323 dump_size;
3324 ql_dbg(ql_dbg_init, vha, 0x00c5,
3325 "Allocated (%d KB) for firmware dump.\n",
3326 dump_size / 1024);
3327
a6b95d1c
QT		 3328 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
3329 mutex_unlock(&ha->optrom_mutex);
a4226ec3 3330 return;
a6b95d1c 3331 }
a4226ec3
QT		 3332
3333 ha->fw_dump->signature[0] = 'Q';
3334 ha->fw_dump->signature[1] = 'L';
3335 ha->fw_dump->signature[2] = 'G';
3336 ha->fw_dump->signature[3] = 'C';
3337 ha->fw_dump->version = htonl(1);
3338
3339 ha->fw_dump->fixed_size = htonl(fixed_size);
3340 ha->fw_dump->mem_size = htonl(mem_size);
3341 ha->fw_dump->req_q_size = htonl(req_q_size);
3342 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
3343
3344 ha->fw_dump->eft_size = htonl(eft_size);
3345 ha->fw_dump->eft_addr_l =
3346 htonl(LSD(ha->eft_dma));
3347 ha->fw_dump->eft_addr_h =
3348 htonl(MSD(ha->eft_dma));
3349
3350 ha->fw_dump->header_size =
3351 htonl(offsetof
3352 (struct qla2xxx_fw_dump, isp));
3353 }
a6b95d1c 3354 mutex_unlock(&ha->optrom_mutex);
a7a167bf 3355 }
a7a167bf 3356 }
0107109e
AV		 3357}
3358
18e7555a
AV		 3359static int
3360qla81xx_mpi_sync(scsi_qla_host_t *vha)
3361{
3362#define MPS_MASK 0xe0
3363 int rval;
3364 uint16_t dc;
3365 uint32_t dw;
18e7555a
AV		 3366
3367 if (!IS_QLA81XX(vha->hw))
3368 return QLA_SUCCESS;
3369
3370 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
3371 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3372 ql_log(ql_log_warn, vha, 0x0105,
3373 "Unable to acquire semaphore.\n");
18e7555a
AV		 3374 goto done;
3375 }
3376
3377 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
3378 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
3379 if (rval != QLA_SUCCESS) {
7c3df132 3380 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 3381 goto done_release;
3382 }
3383
3384 dc &= MPS_MASK;
3385 if (dc == (dw & MPS_MASK))
3386 goto done_release;
3387
3388 dw &= ~MPS_MASK;
3389 dw |= dc;
3390 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
3391 if (rval != QLA_SUCCESS) {
7c3df132 3392 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 3393 }
3394
3395done_release:
3396 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
3397 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3398 ql_log(ql_log_warn, vha, 0x006d,
3399 "Unable to release semaphore.\n");
18e7555a
AV		 3400 }
3401
3402done:
3403 return rval;
3404}
3405
8d93f550
CD		 3406int
3407qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
3408{
3409 /* Don't try to reallocate the array */
3410 if (req->outstanding_cmds)
3411 return QLA_SUCCESS;
3412
d7459527 3413 if (!IS_FWI2_CAPABLE(ha))
8d93f550
CD		 3414 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
3415 else {
03e8c680
QT		 3416 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
3417 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 3418 else
03e8c680 3419 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 3420 }
3421
6396bb22
KC		 3422 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds,
3423 sizeof(srb_t *),
3424 GFP_KERNEL);
8d93f550
CD		 3425
3426 if (!req->outstanding_cmds) {
3427 /*
3428 * Try to allocate a minimal size just so we can get through
3429 * initialization.
3430 */
3431 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
6396bb22
KC		 3432 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds,
3433 sizeof(srb_t *),
3434 GFP_KERNEL);
8d93f550
CD		 3435
3436 if (!req->outstanding_cmds) {
3437 ql_log(ql_log_fatal, NULL, 0x0126,
3438 "Failed to allocate memory for "
3439 "outstanding_cmds for req_que %p.\n", req);
3440 req->num_outstanding_cmds = 0;
3441 return QLA_FUNCTION_FAILED;
3442 }
3443 }
3444
3445 return QLA_SUCCESS;
3446}
3447
e4e3a2ce
QT		 3448#define PRINT_FIELD(_field, _flag, _str) { \
3449 if (a0->_field & _flag) {\
3450 if (p) {\
3451 strcat(ptr, "|");\
3452 ptr++;\
3453 leftover--;\
3454 } \
3455 len = snprintf(ptr, leftover, "%s", _str); \
3456 p = 1;\
3457 leftover -= len;\
3458 ptr += len; \
3459 } \
3460}
3461
3462static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha)
3463{
3464#define STR_LEN 64
3465 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data;
3466 u8 str[STR_LEN], *ptr, p;
3467 int leftover, len;
3468
3469 memset(str, 0, STR_LEN);
3470 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name);
3471 ql_dbg(ql_dbg_init, vha, 0x015a,
3472 "SFP MFG Name: %s\n", str);
3473
3474 memset(str, 0, STR_LEN);
3475 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn);
3476 ql_dbg(ql_dbg_init, vha, 0x015c,
3477 "SFP Part Name: %s\n", str);
3478
3479 /* media */
3480 memset(str, 0, STR_LEN);
3481 ptr = str;
3482 leftover = STR_LEN;
3483 p = len = 0;
3484 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX");
3485 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair");
3486 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax");
3487 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax");
3488 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um");
3489 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um");
3490 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode");
3491 ql_dbg(ql_dbg_init, vha, 0x0160,
3492 "SFP Media: %s\n", str);
3493
3494 /* link length */
3495 memset(str, 0, STR_LEN);
3496 ptr = str;
3497 leftover = STR_LEN;
3498 p = len = 0;
3499 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long");
3500 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short");
3501 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate");
3502 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long");
3503 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium");
3504 ql_dbg(ql_dbg_init, vha, 0x0196,
3505 "SFP Link Length: %s\n", str);
3506
3507 memset(str, 0, STR_LEN);
3508 ptr = str;
3509 leftover = STR_LEN;
3510 p = len = 0;
3511 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)");
3512 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)");
3513 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)");
3514 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)");
3515 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)");
3516 ql_dbg(ql_dbg_init, vha, 0x016e,
3517 "SFP FC Link Tech: %s\n", str);
3518
3519 if (a0->length_km)
3520 ql_dbg(ql_dbg_init, vha, 0x016f,
3521 "SFP Distant: %d km\n", a0->length_km);
3522 if (a0->length_100m)
3523 ql_dbg(ql_dbg_init, vha, 0x0170,
3524 "SFP Distant: %d m\n", a0->length_100m*100);
3525 if (a0->length_50um_10m)
3526 ql_dbg(ql_dbg_init, vha, 0x0189,
3527 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10);
3528 if (a0->length_62um_10m)
3529 ql_dbg(ql_dbg_init, vha, 0x018a,
3530 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10);
3531 if (a0->length_om4_10m)
3532 ql_dbg(ql_dbg_init, vha, 0x0194,
3533 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10);
3534 if (a0->length_om3_10m)
3535 ql_dbg(ql_dbg_init, vha, 0x0195,
3536 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10);
3537}
3538
3539
3540/*
3541 * Return Code:
3542 * QLA_SUCCESS: no action
3543 * QLA_INTERFACE_ERROR: SFP is not there.
3544 * QLA_FUNCTION_FAILED: detected New SFP
3545 */
3546int
3547qla24xx_detect_sfp(scsi_qla_host_t *vha)
3548{
3549 int rc = QLA_SUCCESS;
3550 struct sff_8247_a0 *a;
3551 struct qla_hw_data *ha = vha->hw;
3552
3553 if (!AUTO_DETECT_SFP_SUPPORT(vha))
3554 goto out;
3555
3556 rc = qla2x00_read_sfp_dev(vha, NULL, 0);
3557 if (rc)
3558 goto out;
3559
3560 a = (struct sff_8247_a0 *)vha->hw->sfp_data;
3561 qla2xxx_print_sfp_info(vha);
3562
3563 if (a->fc_ll_cc7 & FC_LL_VL || a->fc_ll_cc7 & FC_LL_L) {
3564 /* long range */
3565 ha->flags.detected_lr_sfp = 1;
3566
3567 if (a->length_km > 5 || a->length_100m > 50)
3568 ha->long_range_distance = LR_DISTANCE_10K;
3569 else
3570 ha->long_range_distance = LR_DISTANCE_5K;
3571
3572 if (ha->flags.detected_lr_sfp != ha->flags.using_lr_setting)
3573 ql_dbg(ql_dbg_async, vha, 0x507b,
3574 "Detected Long Range SFP.\n");
3575 } else {
3576 /* short range */
3577 ha->flags.detected_lr_sfp = 0;
3578 if (ha->flags.using_lr_setting)
3579 ql_dbg(ql_dbg_async, vha, 0x5084,
3580 "Detected Short Range SFP.\n");
3581 }
3582
3583 if (!vha->flags.init_done)
3584 rc = QLA_SUCCESS;
3585out:
3586 return rc;
3587}
3588
1da177e4
LT		 3589/**
3590 * qla2x00_setup_chip() - Load and start RISC firmware.
2db6228d 3591 * @vha: HA context
1da177e4
LT		 3592 *
3593 * Returns 0 on success.
3594 */
3595static int
e315cd28 3596qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 3597{
0107109e
AV		 3598 int rval;
3599 uint32_t srisc_address = 0;
e315cd28 3600 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 3601 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
3602 unsigned long flags;
dda772e8 3603 uint16_t fw_major_version;
3db0652e 3604
7ec0effd 3605 if (IS_P3P_TYPE(ha)) {
a9083016 3606 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 3607 if (rval == QLA_SUCCESS) {
3608 qla2x00_stop_firmware(vha);
a9083016 3609 goto enable_82xx_npiv;
14e303d9 3610 } else
b963752f 3611 goto failed;
a9083016
GM		 3612 }
3613
3db0652e
AV		 3614 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3615 /* Disable SRAM, Instruction RAM and GP RAM parity. */
3616 spin_lock_irqsave(&ha->hardware_lock, flags);
3617 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
3618 RD_REG_WORD(&reg->hccr);
3619 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3620 }
1da177e4 3621
18e7555a
AV		 3622 qla81xx_mpi_sync(vha);
3623
1da177e4 3624 /* Load firmware sequences */
e315cd28 3625 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 3626 if (rval == QLA_SUCCESS) {
7c3df132
SK		 3627 ql_dbg(ql_dbg_init, vha, 0x00c9,
3628 "Verifying Checksum of loaded RISC code.\n");
1da177e4 3629
e315cd28 3630 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 3631 if (rval == QLA_SUCCESS) {
3632 /* Start firmware execution. */
7c3df132
SK		 3633 ql_dbg(ql_dbg_init, vha, 0x00ca,
3634 "Starting firmware.\n");
1da177e4 3635
b0d6cabd
HM		 3636 if (ql2xexlogins)
3637 ha->flags.exlogins_enabled = 1;
3638
99e1b683 3639 if (qla_is_exch_offld_enabled(vha))
2f56a7f1
HM		 3640 ha->flags.exchoffld_enabled = 1;
3641
e315cd28 3642 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 3643 /* Retrieve firmware information. */
dda772e8 3644 if (rval == QLA_SUCCESS) {
e4e3a2ce
QT		 3645 qla24xx_detect_sfp(vha);
3646
ecc89f25
JC		 3647 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3648 IS_QLA28XX(ha)) &&
8b4673ba
QT		 3649 (ha->zio_mode == QLA_ZIO_MODE_6))
3650 qla27xx_set_zio_threshold(vha,
3651 ha->last_zio_threshold);
3652
b0d6cabd
HM		 3653 rval = qla2x00_set_exlogins_buffer(vha);
3654 if (rval != QLA_SUCCESS)
3655 goto failed;
3656
2f56a7f1
HM		 3657 rval = qla2x00_set_exchoffld_buffer(vha);
3658 if (rval != QLA_SUCCESS)
3659 goto failed;
3660
a9083016 3661enable_82xx_npiv:
dda772e8 3662 fw_major_version = ha->fw_major_version;
7ec0effd 3663 if (IS_P3P_TYPE(ha))
3173167f 3664 qla82xx_check_md_needed(vha);
6246b8a1
GM		 3665 else
3666 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 3667 if (rval != QLA_SUCCESS)
3668 goto failed;
2c3dfe3f 3669 ha->flags.npiv_supported = 0;
e315cd28 3670 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 3671 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 3672 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 3673 if ((!ha->max_npiv_vports) ||
3674 ((ha->max_npiv_vports + 1) %
eb66dc60 3675 MIN_MULTI_ID_FABRIC))
4d0ea247 3676 ha->max_npiv_vports =
eb66dc60 3677 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 3678 }
03e8c680 3679 qla2x00_get_resource_cnts(vha);
d743de66 3680
8d93f550
CD		 3681 /*
3682 * Allocate the array of outstanding commands
3683 * now that we know the firmware resources.
3684 */
3685 rval = qla2x00_alloc_outstanding_cmds(ha,
3686 vha->req);
3687 if (rval != QLA_SUCCESS)
3688 goto failed;
3689
ad0a0b01
QT		 3690 if (!fw_major_version && !(IS_P3P_TYPE(ha)))
3691 qla2x00_alloc_offload_mem(vha);
3692
3693 if (ql2xallocfwdump && !(IS_P3P_TYPE(ha)))
08de2844 3694 qla2x00_alloc_fw_dump(vha);
ad0a0b01 3695
3b6e5b9d
CD		 3696 } else {
3697 goto failed;
1da177e4
LT		 3698 }
3699 } else {
7c3df132
SK		 3700 ql_log(ql_log_fatal, vha, 0x00cd,
3701 "ISP Firmware failed checksum.\n");
3702 goto failed;
1da177e4 3703 }
c74d88a4
AV		 3704 } else
3705 goto failed;
1da177e4 3706
3db0652e
AV		 3707 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3708 /* Enable proper parity. */
3709 spin_lock_irqsave(&ha->hardware_lock, flags);
3710 if (IS_QLA2300(ha))
3711 /* SRAM parity */
3712 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
3713 else
3714 /* SRAM, Instruction RAM and GP RAM parity */
3715 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
3716 RD_REG_WORD(&reg->hccr);
3717 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3718 }
3719
ecc89f25 3720 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
f3982d89
CD		 3721 ha->flags.fac_supported = 1;
3722 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 3723 uint32_t size;
3724
3725 rval = qla81xx_fac_get_sector_size(vha, &size);
3726 if (rval == QLA_SUCCESS) {
3727 ha->flags.fac_supported = 1;
3728 ha->fdt_block_size = size << 2;
3729 } else {
7c3df132 3730 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 3731 "Unsupported FAC firmware (%d.%02d.%02d).\n",
3732 ha->fw_major_version, ha->fw_minor_version,
3733 ha->fw_subminor_version);
1ca60e3b 3734
ecc89f25
JC		 3735 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3736 IS_QLA28XX(ha)) {
6246b8a1
GM		 3737 ha->flags.fac_supported = 0;
3738 rval = QLA_SUCCESS;
3739 }
1d2874de
JC		 3740 }
3741 }
ca9e9c3e 3742failed:
1da177e4 3743 if (rval) {
7c3df132
SK		 3744 ql_log(ql_log_fatal, vha, 0x00cf,
3745 "Setup chip ****FAILED****.\n");
1da177e4
LT		 3746 }
3747
3748 return (rval);
3749}
3750
3751/**
3752 * qla2x00_init_response_q_entries() - Initializes response queue entries.
2db6228d 3753 * @rsp: response queue
1da177e4
LT		 3754 *
3755 * Beginning of request ring has initialization control block already built
3756 * by nvram config routine.
3757 *
3758 * Returns 0 on success.
3759 */
73208dfd
AC		 3760void
3761qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 3762{
3763 uint16_t cnt;
3764 response_t *pkt;
3765
2afa19a9
AC		 3766 rsp->ring_ptr = rsp->ring;
3767 rsp->ring_index = 0;
3768 rsp->status_srb = NULL;
e315cd28
AC		 3769 pkt = rsp->ring_ptr;
3770 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 3771 pkt->signature = RESPONSE_PROCESSED;
3772 pkt++;
3773 }
1da177e4
LT		 3774}
3775
3776/**
3777 * qla2x00_update_fw_options() - Read and process firmware options.
2db6228d 3778 * @vha: HA context
1da177e4
LT		 3779 *
3780 * Returns 0 on success.
3781 */
abbd8870 3782void
e315cd28 3783qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 3784{
3785 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 3786 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3787
3788 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 3789 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 3790
3791 if (IS_QLA2100(ha) || IS_QLA2200(ha))
3792 return;
3793
3794 /* Serial Link options. */
7c3df132
SK		 3795 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
3796 "Serial link options.\n");
3797 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
f8f97b0c 3798 ha->fw_seriallink_options, sizeof(ha->fw_seriallink_options));
1da177e4
LT		 3799
3800 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
3801 if (ha->fw_seriallink_options[3] & BIT_2) {
3802 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
3803
3804 /* 1G settings */
3805 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
3806 emphasis = (ha->fw_seriallink_options[2] &
3807 (BIT_4 | BIT_3)) >> 3;
3808 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 3809 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3810 rx_sens = (ha->fw_seriallink_options[0] &
3811 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3812 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
3813 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3814 if (rx_sens == 0x0)
3815 rx_sens = 0x3;
3816 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
3817 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3818 ha->fw_options[10] |= BIT_5 |
3819 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3820 (tx_sens & (BIT_1 | BIT_0));
3821
3822 /* 2G settings */
3823 swing = (ha->fw_seriallink_options[2] &
3824 (BIT_7 | BIT_6 | BIT_5)) >> 5;
3825 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
3826 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 3827 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3828 rx_sens = (ha->fw_seriallink_options[1] &
3829 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3830 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
3831 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3832 if (rx_sens == 0x0)
3833 rx_sens = 0x3;
3834 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
3835 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3836 ha->fw_options[11] |= BIT_5 |
3837 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3838 (tx_sens & (BIT_1 | BIT_0));
3839 }
3840
3841 /* FCP2 options. */
3842 /* Return command IOCBs without waiting for an ABTS to complete. */
3843 ha->fw_options[3] |= BIT_13;
3844
3845 /* LED scheme. */
3846 if (ha->flags.enable_led_scheme)
3847 ha->fw_options[2] |= BIT_12;
3848
48c02fde 3849 /* Detect ISP6312. */
3850 if (IS_QLA6312(ha))
3851 ha->fw_options[2] |= BIT_13;
3852
088d09d4
GM		 3853 /* Set Retry FLOGI in case of P2P connection */
3854 if (ha->operating_mode == P2P) {
3855 ha->fw_options[2] |= BIT_3;
3856 ql_dbg(ql_dbg_disc, vha, 0x2100,
3857 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3858 __func__, ha->fw_options[2]);
3859 }
3860
1da177e4 3861 /* Update firmware options. */
e315cd28 3862 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 3863}
3864
0107109e 3865void
e315cd28 3866qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 3867{
3868 int rval;
e315cd28 3869 struct qla_hw_data *ha = vha->hw;
0107109e 3870
7ec0effd 3871 if (IS_P3P_TYPE(ha))
a9083016
GM		 3872 return;
3873
f198cafa
HM		 3874 /* Hold status IOCBs until ABTS response received. */
3875 if (ql2xfwholdabts)
3876 ha->fw_options[3] |= BIT_12;
3877
088d09d4
GM		 3878 /* Set Retry FLOGI in case of P2P connection */
3879 if (ha->operating_mode == P2P) {
3880 ha->fw_options[2] |= BIT_3;
3881 ql_dbg(ql_dbg_disc, vha, 0x2101,
3882 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3883 __func__, ha->fw_options[2]);
3884 }
3885
41dc529a 3886 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
3c4810ff 3887 if (ql2xmvasynctoatio &&
ecc89f25 3888 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
41dc529a
QT		 3889 if (qla_tgt_mode_enabled(vha) ||
3890 qla_dual_mode_enabled(vha))
3891 ha->fw_options[2] |= BIT_11;
3892 else
3893 ha->fw_options[2] &= ~BIT_11;
3894 }
3895
ecc89f25
JC		 3896 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3897 IS_QLA28XX(ha)) {
f7e761f5
QT		 3898 /*
3899 * Tell FW to track each exchange to prevent
3900 * driver from using stale exchange.
3901 */
3902 if (qla_tgt_mode_enabled(vha) ||
3903 qla_dual_mode_enabled(vha))
3904 ha->fw_options[2] |= BIT_4;
3905 else
3906 ha->fw_options[2] &= ~BIT_4;
9ecf0b0d
QT		 3907
3908 /* Reserve 1/2 of emergency exchanges for ELS.*/
3909 if (qla2xuseresexchforels)
3910 ha->fw_options[2] |= BIT_8;
3911 else
3912 ha->fw_options[2] &= ~BIT_8;
f7e761f5
QT		 3913 }
3914
83548fe2
QT		 3915 ql_dbg(ql_dbg_init, vha, 0x00e8,
3916 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
3917 __func__, ha->fw_options[1], ha->fw_options[2],
3918 ha->fw_options[3], vha->host->active_mode);
3c4810ff
QT		 3919
3920 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
3921 qla2x00_set_fw_options(vha, ha->fw_options);
41dc529a 3922
0107109e 3923 /* Update Serial Link options. */
f94097ed 3924 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 3925 return;
3926
e315cd28 3927 rval = qla2x00_set_serdes_params(vha,
f94097ed 3928 le16_to_cpu(ha->fw_seriallink_options24[1]),
3929 le16_to_cpu(ha->fw_seriallink_options24[2]),
3930 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 3931 if (rval != QLA_SUCCESS) {
7c3df132 3932 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 3933 "Unable to update Serial Link options (%x).\n", rval);
3934 }
3935}
3936
abbd8870 3937void
e315cd28 3938qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 3939{
e315cd28 3940 struct qla_hw_data *ha = vha->hw;
3d71644c 3941 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 3942 struct req_que *req = ha->req_q_map[0];
3943 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 3944
3945 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 3946 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
3947 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3948 ha->init_cb->request_q_length = cpu_to_le16(req->length);
3949 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
d4556a49
BVA		 3950 put_unaligned_le64(req->dma, &ha->init_cb->request_q_address);
3951 put_unaligned_le64(rsp->dma, &ha->init_cb->response_q_address);
abbd8870
AV		 3952
3953 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
3954 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
3955 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
3956 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
3957 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
3958}
3959
0107109e 3960void
e315cd28 3961qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 3962{
e315cd28 3963 struct qla_hw_data *ha = vha->hw;
118e2ef9 3964 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 3965 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
3966 struct qla_msix_entry *msix;
0107109e 3967 struct init_cb_24xx *icb;
73208dfd
AC		 3968 uint16_t rid = 0;
3969 struct req_que *req = ha->req_q_map[0];
3970 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 3971
6246b8a1 3972 /* Setup ring parameters in initialization control block. */
0107109e 3973 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 3974 icb->request_q_outpointer = cpu_to_le16(0);
3975 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3976 icb->request_q_length = cpu_to_le16(req->length);
3977 icb->response_q_length = cpu_to_le16(rsp->length);
d4556a49
BVA		 3978 put_unaligned_le64(req->dma, &icb->request_q_address);
3979 put_unaligned_le64(rsp->dma, &icb->response_q_address);
0107109e 3980
2d70c103 3981 /* Setup ATIO queue dma pointers for target mode */
ad950360 3982 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103 3983 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
d4556a49 3984 put_unaligned_le64(ha->tgt.atio_dma, &icb->atio_q_address);
2d70c103 3985
7c6300e3 3986 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 3987 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 3988
ecc89f25
JC		 3989 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3990 IS_QLA28XX(ha)) {
ad950360
BVA		 3991 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
3992 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 3993 if (ha->flags.msix_enabled) {
3994 msix = &ha->msix_entries[1];
83548fe2 3995 ql_dbg(ql_dbg_init, vha, 0x0019,
7c3df132
SK		 3996 "Registering vector 0x%x for base que.\n",
3997 msix->entry);
73208dfd
AC		 3998 icb->msix = cpu_to_le16(msix->entry);
3999 }
4000 /* Use alternate PCI bus number */
4001 if (MSB(rid))
ad950360 4002 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 4003 /* Use alternate PCI devfn */
4004 if (LSB(rid))
ad950360 4005 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 4006
3155754a 4007 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 4008 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
4009 (ha->flags.msix_enabled)) {
ad950360 4010 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 4011 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 4012 ql_dbg(ql_dbg_init, vha, 0x00fe,
4013 "MSIX Handshake Disable Mode turned on.\n");
3155754a 4014 } else {
ad950360 4015 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 4016 }
ad950360 4017 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 4018
4019 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
4020 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
4021 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
4022 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
4023 } else {
4024 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
4025 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
4026 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
4027 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
4028 }
4910b524 4029
aa230bc5 4030 qlt_24xx_config_rings(vha);
2d70c103 4031
4910b524
AG		 4032 /* If the user has configured the speed, set it here */
4033 if (ha->set_data_rate) {
4034 ql_dbg(ql_dbg_init, vha, 0x00fd,
4035 "Speed set by user : %s Gbps \n",
4036 qla2x00_get_link_speed_str(ha, ha->set_data_rate));
4037 icb->firmware_options_3 = (ha->set_data_rate << 13);
4038 }
4039
73208dfd
AC		 4040 /* PCI posting */
4041 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 4042}
4043
1da177e4
LT		 4044/**
4045 * qla2x00_init_rings() - Initializes firmware.
2db6228d 4046 * @vha: HA context
1da177e4
LT		 4047 *
4048 * Beginning of request ring has initialization control block already built
4049 * by nvram config routine.
4050 *
4051 * Returns 0 on success.
4052 */
8ae6d9c7 4053int
e315cd28 4054qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 4055{
4056 int rval;
4057 unsigned long flags = 0;
29bdccbe 4058 int cnt, que;
e315cd28 4059 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 4060 struct req_que *req;
4061 struct rsp_que *rsp;
2c3dfe3f
SJ		 4062 struct mid_init_cb_24xx *mid_init_cb =
4063 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 4064
4065 spin_lock_irqsave(&ha->hardware_lock, flags);
4066
4067 /* Clear outstanding commands array. */
2afa19a9 4068 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 4069 req = ha->req_q_map[que];
cb43285f 4070 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 4071 continue;
7c6300e3
JC		 4072 req->out_ptr = (void *)(req->ring + req->length);
4073 *req->out_ptr = 0;
8d93f550 4074 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 4075 req->outstanding_cmds[cnt] = NULL;
1da177e4 4076
2afa19a9 4077 req->current_outstanding_cmd = 1;
1da177e4 4078
29bdccbe
AC		 4079 /* Initialize firmware. */
4080 req->ring_ptr = req->ring;
4081 req->ring_index = 0;
4082 req->cnt = req->length;
4083 }
1da177e4 4084
2afa19a9 4085 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 4086 rsp = ha->rsp_q_map[que];
cb43285f 4087 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 4088 continue;
7c6300e3
JC		 4089 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
4090 *rsp->in_ptr = 0;
29bdccbe 4091 /* Initialize response queue entries */
8ae6d9c7
GM		 4092 if (IS_QLAFX00(ha))
4093 qlafx00_init_response_q_entries(rsp);
4094 else
4095 qla2x00_init_response_q_entries(rsp);
29bdccbe 4096 }
1da177e4 4097
2d70c103
NB		 4098 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
4099 ha->tgt.atio_ring_index = 0;
4100 /* Initialize ATIO queue entries */
4101 qlt_init_atio_q_entries(vha);
4102
e315cd28 4103 ha->isp_ops->config_rings(vha);
1da177e4
LT		 4104
4105 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4106
8ae6d9c7
GM		 4107 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
4108
4109 if (IS_QLAFX00(ha)) {
4110 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
4111 goto next_check;
4112 }
4113
1da177e4 4114 /* Update any ISP specific firmware options before initialization. */
e315cd28 4115 ha->isp_ops->update_fw_options(vha);
1da177e4 4116
605aa2bc 4117 if (ha->flags.npiv_supported) {
45980cc2 4118 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 4119 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 4120 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 4121 }
4122
24a08138 4123 if (IS_FWI2_CAPABLE(ha)) {
ad950360 4124 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 4125 mid_init_cb->init_cb.execution_throttle =
03e8c680 4126 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 4127 ha->flags.dport_enabled =
4128 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
4129 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
4130 (ha->flags.dport_enabled) ? "enabled" : "disabled");
4131 /* FA-WWPN Status */
2486c627 4132 ha->flags.fawwpn_enabled =
40f3862b 4133 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
83548fe2 4134 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n",
2486c627 4135 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 4136 }
2c3dfe3f 4137
e315cd28 4138 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 4139next_check:
1da177e4 4140 if (rval) {
7c3df132
SK		 4141 ql_log(ql_log_fatal, vha, 0x00d2,
4142 "Init Firmware **** FAILED ****.\n");
1da177e4 4143 } else {
7c3df132
SK		 4144 ql_dbg(ql_dbg_init, vha, 0x00d3,
4145 "Init Firmware -- success.\n");
4b60c827 4146 QLA_FW_STARTED(ha);
0645cb83 4147 vha->u_ql2xexchoffld = vha->u_ql2xiniexchg = 0;
1da177e4
LT		 4148 }
4149
4150 return (rval);
4151}
4152
4153/**
4154 * qla2x00_fw_ready() - Waits for firmware ready.
2db6228d 4155 * @vha: HA context
1da177e4
LT		 4156 *
4157 * Returns 0 on success.
4158 */
4159static int
e315cd28 4160qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 4161{
4162 int rval;
4d4df193 4163 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 4164 uint16_t min_wait; /* Minimum wait time if loop is down */
4165 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 4166 uint16_t state[6];
e315cd28 4167 struct qla_hw_data *ha = vha->hw;
1da177e4 4168
8ae6d9c7
GM		 4169 if (IS_QLAFX00(vha->hw))
4170 return qlafx00_fw_ready(vha);
4171
1da177e4
LT		 4172 rval = QLA_SUCCESS;
4173
33461491
CD		 4174 /* Time to wait for loop down */
4175 if (IS_P3P_TYPE(ha))
4176 min_wait = 30;
4177 else
4178 min_wait = 20;
1da177e4
LT		 4179
4180 /*
4181 * Firmware should take at most one RATOV to login, plus 5 seconds for
4182 * our own processing.
4183 */
4184 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
4185 wait_time = min_wait;
4186 }
4187
4188 /* Min wait time if loop down */
4189 mtime = jiffies + (min_wait * HZ);
4190
4191 /* wait time before firmware ready */
4192 wtime = jiffies + (wait_time * HZ);
4193
4194 /* Wait for ISP to finish LIP */
e315cd28 4195 if (!vha->flags.init_done)
7c3df132
SK		 4196 ql_log(ql_log_info, vha, 0x801e,
4197 "Waiting for LIP to complete.\n");
1da177e4
LT		 4198
4199 do {
5b939038 4200 memset(state, -1, sizeof(state));
e315cd28 4201 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 4202 if (rval == QLA_SUCCESS) {
4d4df193 4203 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 4204 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 4205 }
4d4df193 4206 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 4207 ql_dbg(ql_dbg_taskm, vha, 0x801f,
4208 "fw_state=%x 84xx=%x.\n", state[0],
4209 state[2]);
4d4df193
HK		 4210 if ((state[2] & FSTATE_LOGGED_IN) &&
4211 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 4212 ql_dbg(ql_dbg_taskm, vha, 0x8028,
4213 "Sending verify iocb.\n");
4d4df193
HK		 4214
4215 cs84xx_time = jiffies;
e315cd28 4216 rval = qla84xx_init_chip(vha);
7c3df132
SK		 4217 if (rval != QLA_SUCCESS) {
4218 ql_log(ql_log_warn,
cfb0919c 4219 vha, 0x8007,
7c3df132 4220 "Init chip failed.\n");
4d4df193 4221 break;
7c3df132 4222 }
4d4df193
HK		 4223
4224 /* Add time taken to initialize. */
4225 cs84xx_time = jiffies - cs84xx_time;
4226 wtime += cs84xx_time;
4227 mtime += cs84xx_time;
cfb0919c 4228 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 4229 "Increasing wait time by %ld. "
4230 "New time %ld.\n", cs84xx_time,
4231 wtime);
4d4df193
HK		 4232 }
4233 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 4234 ql_dbg(ql_dbg_taskm, vha, 0x8037,
4235 "F/W Ready - OK.\n");
1da177e4 4236
e315cd28 4237 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 4238 &ha->login_timeout, &ha->r_a_tov);
4239
4240 rval = QLA_SUCCESS;
4241 break;
4242 }
4243
4244 rval = QLA_FUNCTION_FAILED;
4245
e315cd28 4246 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 4247 state[0] != FSTATE_READY) {
1da177e4 4248 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 4249 * other than Wait for Login.
4250 */
1da177e4 4251 if (time_after_eq(jiffies, mtime)) {
7c3df132 4252 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 4253 "Cable is unplugged...\n");
4254
e315cd28 4255 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 4256 break;
4257 }
4258 }
4259 } else {
4260 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 4261 if (time_after_eq(jiffies, mtime) ||
7190575f 4262 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 4263 break;
4264 }
4265
4266 if (time_after_eq(jiffies, wtime))
4267 break;
4268
4269 /* Delay for a while */
4270 msleep(500);
1da177e4
LT		 4271 } while (1);
4272
7c3df132 4273 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 4274 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
4275 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 4276
cfb0919c 4277 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 4278 ql_log(ql_log_warn, vha, 0x803b,
4279 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 4280 }
4281
4282 return (rval);
4283}
4284
4285/*
4286* qla2x00_configure_hba
4287* Setup adapter context.
4288*
4289* Input:
4290* ha = adapter state pointer.
4291*
4292* Returns:
4293* 0 = success
4294*
4295* Context:
4296* Kernel context.
4297*/
4298static int
e315cd28 4299qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 4300{
4301 int rval;
4302 uint16_t loop_id;
4303 uint16_t topo;
2c3dfe3f 4304 uint16_t sw_cap;
1da177e4
LT		 4305 uint8_t al_pa;
4306 uint8_t area;
4307 uint8_t domain;
4308 char connect_type[22];
e315cd28 4309 struct qla_hw_data *ha = vha->hw;
61e1b269 4310 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
482c9dc7 4311 port_id_t id;
9d1aa4e1 4312 unsigned long flags;
1da177e4
LT		 4313
4314 /* Get host addresses. */
e315cd28 4315 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 4316 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 4317 if (rval != QLA_SUCCESS) {
e315cd28 4318 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 4319 IS_CNA_CAPABLE(ha) ||
33135aa2 4320 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 4321 ql_dbg(ql_dbg_disc, vha, 0x2008,
4322 "Loop is in a transition state.\n");
33135aa2 4323 } else {
7c3df132
SK		 4324 ql_log(ql_log_warn, vha, 0x2009,
4325 "Unable to get host loop ID.\n");
61e1b269
JC		 4326 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
4327 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
4328 ql_log(ql_log_warn, vha, 0x1151,
4329 "Doing link init.\n");
4330 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
4331 return rval;
4332 }
e315cd28 4333 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 4334 }
1da177e4
LT		 4335 return (rval);
4336 }
4337
4338 if (topo == 4) {
7c3df132
SK		 4339 ql_log(ql_log_info, vha, 0x200a,
4340 "Cannot get topology - retrying.\n");
1da177e4
LT		 4341 return (QLA_FUNCTION_FAILED);
4342 }
4343
e315cd28 4344 vha->loop_id = loop_id;
1da177e4
LT		 4345
4346 /* initialize */
4347 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
4348 ha->operating_mode = LOOP;
2c3dfe3f 4349 ha->switch_cap = 0;
1da177e4
LT		 4350
4351 switch (topo) {
4352 case 0:
7c3df132 4353 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 4354 ha->current_topology = ISP_CFG_NL;
4355 strcpy(connect_type, "(Loop)");
4356 break;
4357
4358 case 1:
7c3df132 4359 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 4360 ha->switch_cap = sw_cap;
1da177e4
LT		 4361 ha->current_topology = ISP_CFG_FL;
4362 strcpy(connect_type, "(FL_Port)");
4363 break;
4364
4365 case 2:
7c3df132 4366 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 4367 ha->operating_mode = P2P;
4368 ha->current_topology = ISP_CFG_N;
4369 strcpy(connect_type, "(N_Port-to-N_Port)");
4370 break;
4371
4372 case 3:
7c3df132 4373 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 4374 ha->switch_cap = sw_cap;
1da177e4
LT		 4375 ha->operating_mode = P2P;
4376 ha->current_topology = ISP_CFG_F;
4377 strcpy(connect_type, "(F_Port)");
4378 break;
4379
4380 default:
7c3df132
SK		 4381 ql_dbg(ql_dbg_disc, vha, 0x200f,
4382 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 4383 ha->current_topology = ISP_CFG_NL;
4384 strcpy(connect_type, "(Loop)");
4385 break;
4386 }
4387
4388 /* Save Host port and loop ID. */
4389 /* byte order - Big Endian */
482c9dc7
QT		 4390 id.b.domain = domain;
4391 id.b.area = area;
4392 id.b.al_pa = al_pa;
4393 id.b.rsvd_1 = 0;
9d1aa4e1 4394 spin_lock_irqsave(&ha->hardware_lock, flags);
8777e431
QT		 4395 if (!(topo == 2 && ha->flags.n2n_bigger))
4396 qlt_update_host_map(vha, id);
9d1aa4e1 4397 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2d70c103 4398
e315cd28 4399 if (!vha->flags.init_done)
7c3df132
SK		 4400 ql_log(ql_log_info, vha, 0x2010,
4401 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 4402 connect_type, vha->loop_id);
1da177e4 4403
1da177e4
LT		 4404 return(rval);
4405}
4406
a9083016 4407inline void
e315cd28 4408qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
bc97c948 4409 const char *def)
9bb9fcf2
AV		 4410{
4411 char *st, *en;
4412 uint16_t index;
a28d9e4e 4413 uint64_t zero[2] = { 0 };
e315cd28 4414 struct qla_hw_data *ha = vha->hw;
ab671149 4415 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 4416 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2 4417
a28d9e4e
JC		 4418 if (len > sizeof(zero))
4419 len = sizeof(zero);
4420 if (memcmp(model, &zero, len) != 0) {
527e9b70 4421 memcpy(ha->model_number, model, len);
9bb9fcf2
AV		 4422 st = en = ha->model_number;
4423 en += len - 1;
4424 while (en > st) {
4425 if (*en != 0x20 && *en != 0x00)
4426 break;
4427 *en-- = '\0';
4428 }
4429
4430 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 4431 if (use_tbl &&
4432 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 4433 index < QLA_MODEL_NAMES)
527e9b70 4434 strlcpy(ha->model_desc,
1ee27146 4435 qla2x00_model_name[index * 2 + 1],
527e9b70 4436 sizeof(ha->model_desc));
9bb9fcf2
AV		 4437 } else {
4438 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 4439 if (use_tbl &&
4440 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 4441 index < QLA_MODEL_NAMES) {
527e9b70
BVA		 4442 strlcpy(ha->model_number,
4443 qla2x00_model_name[index * 2],
4444 sizeof(ha->model_number));
4445 strlcpy(ha->model_desc,
1ee27146 4446 qla2x00_model_name[index * 2 + 1],
527e9b70 4447 sizeof(ha->model_desc));
9bb9fcf2 4448 } else {
527e9b70
BVA		 4449 strlcpy(ha->model_number, def,
4450 sizeof(ha->model_number));
9bb9fcf2
AV		 4451 }
4452 }
1ee27146 4453 if (IS_FWI2_CAPABLE(ha))
e315cd28 4454 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 4455 sizeof(ha->model_desc));
9bb9fcf2
AV		 4456}
4457
4e08df3f
DM		 4458/* On sparc systems, obtain port and node WWN from firmware
4459 * properties.
4460 */
e315cd28 4461static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 4462{
4463#ifdef CONFIG_SPARC
e315cd28 4464 struct qla_hw_data *ha = vha->hw;
4e08df3f 4465 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4466 struct device_node *dp = pci_device_to_OF_node(pdev);
4467 const u8 *val;
4e08df3f
DM		 4468 int len;
4469
4470 val = of_get_property(dp, "port-wwn", &len);
4471 if (val && len >= WWN_SIZE)
4472 memcpy(nv->port_name, val, WWN_SIZE);
4473
4474 val = of_get_property(dp, "node-wwn", &len);
4475 if (val && len >= WWN_SIZE)
4476 memcpy(nv->node_name, val, WWN_SIZE);
4477#endif
4478}
4479
1da177e4
LT		 4480/*
4481* NVRAM configuration for ISP 2xxx
4482*
4483* Input:
4484* ha = adapter block pointer.
4485*
4486* Output:
4487* initialization control block in response_ring
4488* host adapters parameters in host adapter block
4489*
4490* Returns:
4491* 0 = success.
4492*/
abbd8870 4493int
e315cd28 4494qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 4495{
4e08df3f 4496 int rval;
0107109e
AV		 4497 uint8_t chksum = 0;
4498 uint16_t cnt;
4499 uint8_t *dptr1, *dptr2;
e315cd28 4500 struct qla_hw_data *ha = vha->hw;
0107109e 4501 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 4502 nvram_t *nv = ha->nvram;
4503 uint8_t *ptr = ha->nvram;
3d71644c 4504 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4505
4e08df3f
DM		 4506 rval = QLA_SUCCESS;
4507
1da177e4 4508 /* Determine NVRAM starting address. */
f8f97b0c 4509 ha->nvram_size = sizeof(*nv);
1da177e4
LT		 4510 ha->nvram_base = 0;
4511 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
4512 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
4513 ha->nvram_base = 0x80;
4514
4515 /* Get NVRAM data and calculate checksum. */
e315cd28 4516 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 4517 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
4518 chksum += *ptr++;
1da177e4 4519
7c3df132
SK		 4520 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
4521 "Contents of NVRAM.\n");
4522 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
f8f97b0c 4523 nv, ha->nvram_size);
1da177e4
LT		 4524
4525 /* Bad NVRAM data, set defaults parameters. */
a28d9e4e
JC		 4526 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
4527 nv->nvram_version < 1) {
1da177e4 4528 /* Reset NVRAM data. */
7c3df132 4529 ql_log(ql_log_warn, vha, 0x0064,
3695310e
JC		 4530 "Inconsistent NVRAM detected: checksum=%#x id=%.4s version=%#x.\n",
4531 chksum, nv->id, nv->nvram_version);
7c3df132
SK		 4532 ql_log(ql_log_warn, vha, 0x0065,
4533 "Falling back to "
4534 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 4535
4536 /*
4537 * Set default initialization control block.
4538 */
4539 memset(nv, 0, ha->nvram_size);
4540 nv->parameter_block_version = ICB_VERSION;
4541
4542 if (IS_QLA23XX(ha)) {
4543 nv->firmware_options[0] = BIT_2 | BIT_1;
4544 nv->firmware_options[1] = BIT_7 | BIT_5;
4545 nv->add_firmware_options[0] = BIT_5;
4546 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 4547 nv->frame_payload_size = 2048;
4e08df3f
DM		 4548 nv->special_options[1] = BIT_7;
4549 } else if (IS_QLA2200(ha)) {
4550 nv->firmware_options[0] = BIT_2 | BIT_1;
4551 nv->firmware_options[1] = BIT_7 | BIT_5;
4552 nv->add_firmware_options[0] = BIT_5;
4553 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 4554 nv->frame_payload_size = 1024;
4e08df3f
DM		 4555 } else if (IS_QLA2100(ha)) {
4556 nv->firmware_options[0] = BIT_3 | BIT_1;
4557 nv->firmware_options[1] = BIT_5;
98aee70d 4558 nv->frame_payload_size = 1024;
4e08df3f
DM		 4559 }
4560
ad950360
BVA		 4561 nv->max_iocb_allocation = cpu_to_le16(256);
4562 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 4563 nv->retry_count = 8;
4564 nv->retry_delay = 1;
4565
4566 nv->port_name[0] = 33;
4567 nv->port_name[3] = 224;
4568 nv->port_name[4] = 139;
4569
e315cd28 4570 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4571
4572 nv->login_timeout = 4;
4573
4574 /*
4575 * Set default host adapter parameters
4576 */
4577 nv->host_p[1] = BIT_2;
4578 nv->reset_delay = 5;
4579 nv->port_down_retry_count = 8;
ad950360 4580 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 4581 nv->link_down_timeout = 60;
4582
4583 rval = 1;
1da177e4
LT		 4584 }
4585
4586#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
4587 /*
4588 * The SN2 does not provide BIOS emulation which means you can't change
4589 * potentially bogus BIOS settings. Force the use of default settings
4590 * for link rate and frame size. Hope that the rest of the settings
4591 * are valid.
4592 */
4593 if (ia64_platform_is("sn2")) {
98aee70d 4594 nv->frame_payload_size = 2048;
1da177e4
LT		 4595 if (IS_QLA23XX(ha))
4596 nv->special_options[1] = BIT_7;
4597 }
4598#endif
4599
4600 /* Reset Initialization control block */
0107109e 4601 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 4602
4603 /*
4604 * Setup driver NVRAM options.
4605 */
4606 nv->firmware_options[0] |= (BIT_6 | BIT_1);
4607 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
4608 nv->firmware_options[1] |= (BIT_5 | BIT_0);
4609 nv->firmware_options[1] &= ~BIT_4;
4610
4611 if (IS_QLA23XX(ha)) {
4612 nv->firmware_options[0] |= BIT_2;
4613 nv->firmware_options[0] &= ~BIT_3;
2d70c103 4614 nv->special_options[0] &= ~BIT_6;
0107109e 4615 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 4616
4617 if (IS_QLA2300(ha)) {
4618 if (ha->fb_rev == FPM_2310) {
4619 strcpy(ha->model_number, "QLA2310");
4620 } else {
4621 strcpy(ha->model_number, "QLA2300");
4622 }
4623 } else {
e315cd28 4624 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 4625 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 4626 }
4627 } else if (IS_QLA2200(ha)) {
4628 nv->firmware_options[0] |= BIT_2;
4629 /*
4630 * 'Point-to-point preferred, else loop' is not a safe
4631 * connection mode setting.
4632 */
4633 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
4634 (BIT_5 | BIT_4)) {
4635 /* Force 'loop preferred, else point-to-point'. */
4636 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
4637 nv->add_firmware_options[0] |= BIT_5;
4638 }
4639 strcpy(ha->model_number, "QLA22xx");
4640 } else /*if (IS_QLA2100(ha))*/ {
4641 strcpy(ha->model_number, "QLA2100");
4642 }
4643
4644 /*
4645 * Copy over NVRAM RISC parameter block to initialization control block.
4646 */
4647 dptr1 = (uint8_t *)icb;
4648 dptr2 = (uint8_t *)&nv->parameter_block_version;
4649 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
4650 while (cnt--)
4651 *dptr1++ = *dptr2++;
4652
4653 /* Copy 2nd half. */
4654 dptr1 = (uint8_t *)icb->add_firmware_options;
4655 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
4656 while (cnt--)
4657 *dptr1++ = *dptr2++;
0eaaca4c 4658 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
5341e868
AV		 4659 /* Use alternate WWN? */
4660 if (nv->host_p[1] & BIT_7) {
4661 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4662 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4663 }
4664
1da177e4
LT		 4665 /* Prepare nodename */
4666 if ((icb->firmware_options[1] & BIT_6) == 0) {
4667 /*
4668 * Firmware will apply the following mask if the nodename was
4669 * not provided.
4670 */
4671 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4672 icb->node_name[0] &= 0xF0;
4673 }
4674
4675 /*
4676 * Set host adapter parameters.
4677 */
3ce8866c
SK		 4678
4679 /*
4680 * BIT_7 in the host-parameters section allows for modification to
4681 * internal driver logging.
4682 */
0181944f 4683 if (nv->host_p[0] & BIT_7)
cfb0919c 4684 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 4685 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
4686 /* Always load RISC code on non ISP2[12]00 chips. */
4687 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
4688 ha->flags.disable_risc_code_load = 0;
4689 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
4690 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
4691 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 4692 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 4693 ha->flags.disable_serdes = 0;
1da177e4
LT		 4694
4695 ha->operating_mode =
4696 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
4697
4698 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
4699 sizeof(ha->fw_seriallink_options));
4700
4701 /* save HBA serial number */
4702 ha->serial0 = icb->port_name[5];
4703 ha->serial1 = icb->port_name[6];
4704 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4705 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4706 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 4707
ad950360 4708 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 4709
4710 ha->retry_count = nv->retry_count;
4711
4712 /* Set minimum login_timeout to 4 seconds. */
5b91490e 4713 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 4714 nv->login_timeout = ql2xlogintimeout;
4715 if (nv->login_timeout < 4)
4716 nv->login_timeout = 4;
4717 ha->login_timeout = nv->login_timeout;
1da177e4 4718
00a537b8
AV		 4719 /* Set minimum RATOV to 100 tenths of a second. */
4720 ha->r_a_tov = 100;
1da177e4 4721
1da177e4
LT		 4722 ha->loop_reset_delay = nv->reset_delay;
4723
1da177e4
LT		 4724 /* Link Down Timeout = 0:
4725 *
4726 * When Port Down timer expires we will start returning
4727 * I/O's to OS with "DID_NO_CONNECT".
4728 *
4729 * Link Down Timeout != 0:
4730 *
4731 * The driver waits for the link to come up after link down
4732 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 4733 */
1da177e4
LT		 4734 if (nv->link_down_timeout == 0) {
4735 ha->loop_down_abort_time =
354d6b21 4736 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 4737 } else {
4738 ha->link_down_timeout = nv->link_down_timeout;
4739 ha->loop_down_abort_time =
4740 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 4741 }
1da177e4 4742
1da177e4
LT		 4743 /*
4744 * Need enough time to try and get the port back.
4745 */
4746 ha->port_down_retry_count = nv->port_down_retry_count;
4747 if (qlport_down_retry)
4748 ha->port_down_retry_count = qlport_down_retry;
4749 /* Set login_retry_count */
4750 ha->login_retry_count = nv->retry_count;
4751 if (ha->port_down_retry_count == nv->port_down_retry_count &&
4752 ha->port_down_retry_count > 3)
4753 ha->login_retry_count = ha->port_down_retry_count;
4754 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4755 ha->login_retry_count = ha->port_down_retry_count;
4756 if (ql2xloginretrycount)
4757 ha->login_retry_count = ql2xloginretrycount;
4758
ad950360 4759 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 4760 icb->command_resource_count = 0;
4761 icb->immediate_notify_resource_count = 0;
ad950360 4762 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 4763
4764 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4765 /* Enable RIO */
4766 icb->firmware_options[0] &= ~BIT_3;
4767 icb->add_firmware_options[0] &=
4768 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
4769 icb->add_firmware_options[0] |= BIT_2;
4770 icb->response_accumulation_timer = 3;
4771 icb->interrupt_delay_timer = 5;
4772
e315cd28 4773 vha->flags.process_response_queue = 1;
1da177e4 4774 } else {
4fdfefe5 4775 /* Enable ZIO. */
e315cd28 4776 if (!vha->flags.init_done) {
4fdfefe5
AV		 4777 ha->zio_mode = icb->add_firmware_options[0] &
4778 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4779 ha->zio_timer = icb->interrupt_delay_timer ?
58e2753c 4780 icb->interrupt_delay_timer : 2;
4fdfefe5 4781 }
1da177e4
LT		 4782 icb->add_firmware_options[0] &=
4783 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 4784 vha->flags.process_response_queue = 0;
4fdfefe5 4785 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 4786 ha->zio_mode = QLA_ZIO_MODE_6;
4787
7c3df132 4788 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 4789 "ZIO mode %d enabled; timer delay (%d us).\n",
4790 ha->zio_mode, ha->zio_timer * 100);
1da177e4 4791
4fdfefe5
AV		 4792 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
4793 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 4794 vha->flags.process_response_queue = 1;
1da177e4
LT		 4795 }
4796 }
4797
4e08df3f 4798 if (rval) {
7c3df132
SK		 4799 ql_log(ql_log_warn, vha, 0x0069,
4800 "NVRAM configuration failed.\n");
4e08df3f
DM		 4801 }
4802 return (rval);
1da177e4
LT		 4803}
4804
19a7b4ae
JSEC		 4805static void
4806qla2x00_rport_del(void *data)
4807{
4808 fc_port_t *fcport = data;
d97994dc 4809 struct fc_rport *rport;
044d78e1 4810 unsigned long flags;
d97994dc 4811
044d78e1 4812 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
58e2753c 4813 rport = fcport->drport ? fcport->drport : fcport->rport;
d97994dc 4814 fcport->drport = NULL;
044d78e1 4815 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
726b8548 4816 if (rport) {
83548fe2
QT		 4817 ql_dbg(ql_dbg_disc, fcport->vha, 0x210b,
4818 "%s %8phN. rport %p roles %x\n",
4819 __func__, fcport->port_name, rport,
4820 rport->roles);
726b8548 4821
d97994dc 4822 fc_remote_port_delete(rport);
726b8548 4823 }
19a7b4ae
JSEC		 4824}
4825
a630bdc5
BVA		 4826void qla2x00_set_fcport_state(fc_port_t *fcport, int state)
4827{
4828 int old_state;
4829
4830 old_state = atomic_read(&fcport->state);
4831 atomic_set(&fcport->state, state);
4832
4833 /* Don't print state transitions during initial allocation of fcport */
4834 if (old_state && old_state != state) {
4835 ql_dbg(ql_dbg_disc, fcport->vha, 0x207d,
4836 "FCPort %8phC state transitioned from %s to %s - portid=%02x%02x%02x.\n",
4837 fcport->port_name, port_state_str[old_state],
4838 port_state_str[state], fcport->d_id.b.domain,
4839 fcport->d_id.b.area, fcport->d_id.b.al_pa);
4840 }
4841}
4842
1da177e4
LT		 4843/**
4844 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2db6228d 4845 * @vha: HA context
1da177e4
LT		 4846 * @flags: allocation flags
4847 *
4848 * Returns a pointer to the allocated fcport, or NULL, if none available.
4849 */
9a069e19 4850fc_port_t *
e315cd28 4851qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 4852{
4853 fc_port_t *fcport;
4854
bbfbbbc1
MK		 4855 fcport = kzalloc(sizeof(fc_port_t), flags);
4856 if (!fcport)
4857 return NULL;
1da177e4 4858
9ecd6564
QT		 4859 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
4860 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
4861 flags);
4862 if (!fcport->ct_desc.ct_sns) {
4863 ql_log(ql_log_warn, vha, 0xd049,
4864 "Failed to allocate ct_sns request.\n");
4865 kfree(fcport);
4866 return NULL;
4867 }
4868
1da177e4 4869 /* Setup fcport template structure. */
e315cd28 4870 fcport->vha = vha;
1da177e4
LT		 4871 fcport->port_type = FCT_UNKNOWN;
4872 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 4873 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 4874 fcport->supported_classes = FC_COS_UNSPECIFIED;
f635e48e 4875 fcport->fp_speed = PORT_SPEED_UNKNOWN;
1da177e4 4876
726b8548
QT		 4877 fcport->disc_state = DSC_DELETED;
4878 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
4879 fcport->deleted = QLA_SESS_DELETED;
4880 fcport->login_retry = vha->hw->login_retry_count;
9ecd6564 4881 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
726b8548
QT		 4882 fcport->logout_on_delete = 1;
4883
4884 if (!fcport->ct_desc.ct_sns) {
83548fe2 4885 ql_log(ql_log_warn, vha, 0xd049,
726b8548
QT		 4886 "Failed to allocate ct_sns request.\n");
4887 kfree(fcport);
4888 fcport = NULL;
4889 }
9ecd6564 4890
726b8548 4891 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
cd4ed6b4 4892 INIT_WORK(&fcport->reg_work, qla_register_fcport_fn);
726b8548
QT		 4893 INIT_LIST_HEAD(&fcport->gnl_entry);
4894 INIT_LIST_HEAD(&fcport->list);
4895
bbfbbbc1 4896 return fcport;
1da177e4
LT		 4897}
4898
726b8548
QT		 4899void
4900qla2x00_free_fcport(fc_port_t *fcport)
4901{
4902 if (fcport->ct_desc.ct_sns) {
4903 dma_free_coherent(&fcport->vha->hw->pdev->dev,
4904 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
4905 fcport->ct_desc.ct_sns_dma);
4906
4907 fcport->ct_desc.ct_sns = NULL;
4908 }
ffbc6476
QT		 4909 list_del(&fcport->list);
4910 qla2x00_clear_loop_id(fcport);
726b8548
QT		 4911 kfree(fcport);
4912}
4913
1da177e4
LT		 4914/*
4915 * qla2x00_configure_loop
4916 * Updates Fibre Channel Device Database with what is actually on loop.
4917 *
4918 * Input:
4919 * ha = adapter block pointer.
4920 *
4921 * Returns:
4922 * 0 = success.
4923 * 1 = error.
4924 * 2 = database was full and device was not configured.
4925 */
4926static int
e315cd28 4927qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4928{
4929 int rval;
4930 unsigned long flags, save_flags;
e315cd28 4931 struct qla_hw_data *ha = vha->hw;
bd432bb5 4932
1da177e4
LT		 4933 rval = QLA_SUCCESS;
4934
4935 /* Get Initiator ID */
e315cd28
AC		 4936 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
4937 rval = qla2x00_configure_hba(vha);
1da177e4 4938 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4939 ql_dbg(ql_dbg_disc, vha, 0x2013,
4940 "Unable to configure HBA.\n");
1da177e4
LT		 4941 return (rval);
4942 }
4943 }
4944
e315cd28 4945 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 4946 ql_dbg(ql_dbg_disc, vha, 0x2014,
4947 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 4948
4949 /*
4950 * If we have both an RSCN and PORT UPDATE pending then handle them
4951 * both at the same time.
4952 */
e315cd28
AC		 4953 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
4954 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 4955
3064ff39
MH		 4956 qla2x00_get_data_rate(vha);
4957
1da177e4
LT		 4958 /* Determine what we need to do */
4959 if (ha->current_topology == ISP_CFG_FL &&
4960 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4961
1da177e4
LT		 4962 set_bit(RSCN_UPDATE, &flags);
4963
4964 } else if (ha->current_topology == ISP_CFG_F &&
4965 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4966
1da177e4
LT		 4967 set_bit(RSCN_UPDATE, &flags);
4968 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 4969
4970 } else if (ha->current_topology == ISP_CFG_N) {
4971 clear_bit(RSCN_UPDATE, &flags);
48acad09
QT		 4972 if (qla_tgt_mode_enabled(vha)) {
4973 /* allow the other side to start the login */
9cd883f0
QT		 4974 clear_bit(LOCAL_LOOP_UPDATE, &flags);
4975 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
9cd883f0 4976 }
41dc529a
QT		 4977 } else if (ha->current_topology == ISP_CFG_NL) {
4978 clear_bit(RSCN_UPDATE, &flags);
4979 set_bit(LOCAL_LOOP_UPDATE, &flags);
e315cd28 4980 } else if (!vha->flags.online ||
1da177e4 4981 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
1da177e4
LT		 4982 set_bit(RSCN_UPDATE, &flags);
4983 set_bit(LOCAL_LOOP_UPDATE, &flags);
4984 }
4985
4986 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 4987 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
4988 ql_dbg(ql_dbg_disc, vha, 0x2015,
4989 "Loop resync needed, failing.\n");
1da177e4 4990 rval = QLA_FUNCTION_FAILED;
642ef983 4991 } else
e315cd28 4992 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 4993 }
4994
4995 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132 4996 if (LOOP_TRANSITION(vha)) {
83548fe2 4997 ql_dbg(ql_dbg_disc, vha, 0x2099,
7c3df132 4998 "Needs RSCN update and loop transition.\n");
1da177e4 4999 rval = QLA_FUNCTION_FAILED;
7c3df132 5000 }
e315cd28
AC		 5001 else
5002 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 5003 }
5004
5005 if (rval == QLA_SUCCESS) {
e315cd28
AC		 5006 if (atomic_read(&vha->loop_down_timer) ||
5007 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 5008 rval = QLA_FUNCTION_FAILED;
5009 } else {
e315cd28 5010 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 5011 ql_dbg(ql_dbg_disc, vha, 0x2069,
5012 "LOOP READY.\n");
ec7193e2 5013 ha->flags.fw_init_done = 1;
3bb67df5
DKU		 5014
5015 /*
5016 * Process any ATIO queue entries that came in
5017 * while we weren't online.
5018 */
ead03855
QT		 5019 if (qla_tgt_mode_enabled(vha) ||
5020 qla_dual_mode_enabled(vha)) {
1073daa4
QT		 5021 spin_lock_irqsave(&ha->tgt.atio_lock, flags);
5022 qlt_24xx_process_atio_queue(vha, 0);
5023 spin_unlock_irqrestore(&ha->tgt.atio_lock,
5024 flags);
3bb67df5 5025 }
1da177e4
LT		 5026 }
5027 }
5028
5029 if (rval) {
7c3df132
SK		 5030 ql_dbg(ql_dbg_disc, vha, 0x206a,
5031 "%s *** FAILED ***.\n", __func__);
1da177e4 5032 } else {
7c3df132
SK		 5033 ql_dbg(ql_dbg_disc, vha, 0x206b,
5034 "%s: exiting normally.\n", __func__);
1da177e4
LT		 5035 }
5036
cc3ef7bc 5037 /* Restore state if a resync event occurred during processing */
e315cd28 5038 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 5039 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 5040 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 5041 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 5042 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 5043 }
1da177e4
LT		 5044 }
5045
5046 return (rval);
5047}
5048
1da177e4
LT		 5049/*
5050 * qla2x00_configure_local_loop
5051 * Updates Fibre Channel Device Database with local loop devices.
5052 *
5053 * Input:
5054 * ha = adapter block pointer.
5055 *
5056 * Returns:
5057 * 0 = success.
5058 */
5059static int
e315cd28 5060qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 5061{
5062 int rval, rval2;
5063 int found_devs;
5064 int found;
5065 fc_port_t *fcport, *new_fcport;
5066
5067 uint16_t index;
5068 uint16_t entries;
9c17c3b1 5069 struct gid_list_info *gid;
1da177e4
LT		 5070 uint16_t loop_id;
5071 uint8_t domain, area, al_pa;
e315cd28 5072 struct qla_hw_data *ha = vha->hw;
41dc529a 5073 unsigned long flags;
1da177e4 5074
8777e431
QT		 5075 /* Inititae N2N login. */
5076 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags)) {
5077 /* borrowing */
5078 u32 *bp, i, sz;
5079
5080 memset(ha->init_cb, 0, ha->init_cb_size);
5081 sz = min_t(int, sizeof(struct els_plogi_payload),
5082 ha->init_cb_size);
5083 rval = qla24xx_get_port_login_templ(vha, ha->init_cb_dma,
5084 (void *)ha->init_cb, sz);
5085 if (rval == QLA_SUCCESS) {
5086 bp = (uint32_t *)ha->init_cb;
5087 for (i = 0; i < sz/4 ; i++, bp++)
5088 *bp = cpu_to_be32(*bp);
5089
5090 memcpy(&ha->plogi_els_payld.data, (void *)ha->init_cb,
5091 sizeof(ha->plogi_els_payld.data));
5092 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5093 } else {
5094 ql_dbg(ql_dbg_init, vha, 0x00d1,
5095 "PLOGI ELS param read fail.\n");
5096 }
5097 return QLA_SUCCESS;
5098 }
5099
1da177e4
LT		 5100 found_devs = 0;
5101 new_fcport = NULL;
642ef983 5102 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 5103
1da177e4 5104 /* Get list of logged in devices. */
642ef983 5105 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 5106 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 5107 &entries);
5108 if (rval != QLA_SUCCESS)
5109 goto cleanup_allocation;
5110
83548fe2 5111 ql_dbg(ql_dbg_disc, vha, 0x2011,
7c3df132
SK		 5112 "Entries in ID list (%d).\n", entries);
5113 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
f8f97b0c 5114 ha->gid_list, entries * sizeof(*ha->gid_list));
1da177e4 5115
0e324e94
QT		 5116 if (entries == 0) {
5117 spin_lock_irqsave(&vha->work_lock, flags);
5118 vha->scan.scan_retry++;
5119 spin_unlock_irqrestore(&vha->work_lock, flags);
5120
5121 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) {
5122 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5123 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5124 }
5125 } else {
5126 vha->scan.scan_retry = 0;
5127 }
5128
9cd883f0
QT		 5129 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5130 fcport->scan_state = QLA_FCPORT_SCAN;
5131 }
5132
1da177e4 5133 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 5134 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5135 if (new_fcport == NULL) {
83548fe2 5136 ql_log(ql_log_warn, vha, 0x2012,
7c3df132 5137 "Memory allocation failed for fcport.\n");
1da177e4
LT		 5138 rval = QLA_MEMORY_ALLOC_FAILED;
5139 goto cleanup_allocation;
5140 }
5141 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
5142
1da177e4 5143 /* Add devices to port list. */
9c17c3b1 5144 gid = ha->gid_list;
1da177e4 5145 for (index = 0; index < entries; index++) {
9c17c3b1
BVA		 5146 domain = gid->domain;
5147 area = gid->area;
5148 al_pa = gid->al_pa;
abbd8870 5149 if (IS_QLA2100(ha) || IS_QLA2200(ha))
9c17c3b1 5150 loop_id = gid->loop_id_2100;
abbd8870 5151 else
9c17c3b1
BVA		 5152 loop_id = le16_to_cpu(gid->loop_id);
5153 gid = (void *)gid + ha->gid_list_info_size;
1da177e4
LT		 5154
5155 /* Bypass reserved domain fields. */
5156 if ((domain & 0xf0) == 0xf0)
5157 continue;
5158
4705f10e
QT		 5159 /* Bypass if not same domain and area of adapter. */
5160 if (area && domain && ((area != vha->d_id.b.area) ||
5161 (domain != vha->d_id.b.domain)) &&
5162 (ha->current_topology == ISP_CFG_NL))
5163 continue;
5164
5165
1da177e4
LT		 5166 /* Bypass invalid local loop ID. */
5167 if (loop_id > LAST_LOCAL_LOOP_ID)
5168 continue;
5169
41dc529a 5170 memset(new_fcport->port_name, 0, WWN_SIZE);
370d550e 5171
1da177e4
LT		 5172 /* Fill in member data. */
5173 new_fcport->d_id.b.domain = domain;
5174 new_fcport->d_id.b.area = area;
5175 new_fcport->d_id.b.al_pa = al_pa;
5176 new_fcport->loop_id = loop_id;
9cd883f0 5177 new_fcport->scan_state = QLA_FCPORT_FOUND;
41dc529a 5178
e315cd28 5179 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 5180 if (rval2 != QLA_SUCCESS) {
83548fe2 5181 ql_dbg(ql_dbg_disc, vha, 0x2097,
7c3df132
SK		 5182 "Failed to retrieve fcport information "
5183 "-- get_port_database=%x, loop_id=0x%04x.\n",
5184 rval2, new_fcport->loop_id);
edd05de1
DG		 5185 /* Skip retry if N2N */
5186 if (ha->current_topology != ISP_CFG_N) {
5187 ql_dbg(ql_dbg_disc, vha, 0x2105,
5188 "Scheduling resync.\n");
5189 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5190 continue;
5191 }
1da177e4
LT		 5192 }
5193
41dc529a 5194 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 5195 /* Check for matching device in port list. */
5196 found = 0;
5197 fcport = NULL;
e315cd28 5198 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 5199 if (memcmp(new_fcport->port_name, fcport->port_name,
5200 WWN_SIZE))
5201 continue;
5202
ddb9b126 5203 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 5204 fcport->loop_id = new_fcport->loop_id;
5205 fcport->port_type = new_fcport->port_type;
5206 fcport->d_id.b24 = new_fcport->d_id.b24;
5207 memcpy(fcport->node_name, new_fcport->node_name,
5208 WWN_SIZE);
9cd883f0 5209 fcport->scan_state = QLA_FCPORT_FOUND;
1da177e4
LT		 5210 found++;
5211 break;
5212 }
5213
5214 if (!found) {
5215 /* New device, add to fcports list. */
e315cd28 5216 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 5217
5218 /* Allocate a new replacement fcport. */
5219 fcport = new_fcport;
41dc529a
QT		 5220
5221 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5222
e315cd28 5223 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
41dc529a 5224
1da177e4 5225 if (new_fcport == NULL) {
83548fe2 5226 ql_log(ql_log_warn, vha, 0xd031,
7c3df132 5227 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 5228 rval = QLA_MEMORY_ALLOC_FAILED;
5229 goto cleanup_allocation;
5230 }
41dc529a 5231 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 5232 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
5233 }
5234
41dc529a
QT		 5235 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5236
d8b45213 5237 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 5238 fcport->fp_speed = ha->link_data_rate;
d8b45213 5239
1da177e4
LT		 5240 found_devs++;
5241 }
5242
9cd883f0
QT		 5243 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5244 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5245 break;
5246
5247 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5248 if ((qla_dual_mode_enabled(vha) ||
5249 qla_ini_mode_enabled(vha)) &&
5250 atomic_read(&fcport->state) == FCS_ONLINE) {
5251 qla2x00_mark_device_lost(vha, fcport,
5252 ql2xplogiabsentdevice, 0);
5253 if (fcport->loop_id != FC_NO_LOOP_ID &&
5254 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5255 fcport->port_type != FCT_INITIATOR &&
5256 fcport->port_type != FCT_BROADCAST) {
5257 ql_dbg(ql_dbg_disc, vha, 0x20f0,
5258 "%s %d %8phC post del sess\n",
5259 __func__, __LINE__,
5260 fcport->port_name);
5261
d8630bb9 5262 qlt_schedule_sess_for_deletion(fcport);
9cd883f0
QT		 5263 continue;
5264 }
5265 }
5266 }
5267
5268 if (fcport->scan_state == QLA_FCPORT_FOUND)
5269 qla24xx_fcport_handle_login(vha, fcport);
5270 }
5271
1da177e4 5272cleanup_allocation:
c9475cb0 5273 kfree(new_fcport);
1da177e4
LT		 5274
5275 if (rval != QLA_SUCCESS) {
83548fe2 5276 ql_dbg(ql_dbg_disc, vha, 0x2098,
7c3df132 5277 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 5278 }
5279
1da177e4
LT		 5280 return (rval);
5281}
5282
d8b45213 5283static void
e315cd28 5284qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 5285{
d8b45213 5286 int rval;
93f2bd67 5287 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 5288 struct qla_hw_data *ha = vha->hw;
d8b45213 5289
c76f2c01 5290 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 5291 return;
5292
c9afb9a2
GM		 5293 if (atomic_read(&fcport->state) != FCS_ONLINE)
5294 return;
5295
39bd9622 5296 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
413c2f33
HM		 5297 fcport->fp_speed > ha->link_data_rate ||
5298 !ha->flags.gpsc_supported)
d8b45213
AV		 5299 return;
5300
e315cd28 5301 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 5302 mb);
d8b45213 5303 if (rval != QLA_SUCCESS) {
7c3df132 5304 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 5305 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
5306 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 5307 } else {
7c3df132 5308 ql_dbg(ql_dbg_disc, vha, 0x2005,
33b28357 5309 "iIDMA adjusted to %s GB/s (%X) on %8phN.\n",
d0297c9a 5310 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
33b28357 5311 fcport->fp_speed, fcport->port_name);
d8b45213
AV		 5312 }
5313}
5314
cc28e0ac
QT		 5315void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
5316{
5317 qla2x00_iidma_fcport(vha, fcport);
5318 qla24xx_update_fcport_fcp_prio(vha, fcport);
5319}
5320
5321int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
5322{
5323 struct qla_work_evt *e;
5324
5325 e = qla2x00_alloc_work(vha, QLA_EVT_IIDMA);
5326 if (!e)
5327 return QLA_FUNCTION_FAILED;
5328
5329 e->u.fcport.fcport = fcport;
5330 return qla2x00_post_work(vha, e);
5331}
5332
726b8548 5333/* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
23be331d 5334static void
e315cd28 5335qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 5336{
5337 struct fc_rport_identifiers rport_ids;
bdf79621 5338 struct fc_rport *rport;
044d78e1 5339 unsigned long flags;
8482e118 5340
b63d8b89
QT		 5341 if (atomic_read(&fcport->state) == FCS_ONLINE)
5342 return;
5343
f8b02a85
AV		 5344 rport_ids.node_name = wwn_to_u64(fcport->node_name);
5345 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 5346 rport_ids.port_id = fcport->d_id.b.domain << 16 |
5347 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 5348 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 5349 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 5350 if (!rport) {
7c3df132
SK		 5351 ql_log(ql_log_warn, vha, 0x2006,
5352 "Unable to allocate fc remote port.\n");
77d74143
AV		 5353 return;
5354 }
2d70c103 5355
044d78e1 5356 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 5357 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 5358 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 5359
ad3e0eda 5360 rport->supported_classes = fcport->supported_classes;
77d74143 5361
a6a6d058 5362 rport_ids.roles = FC_PORT_ROLE_UNKNOWN;
8482e118 5363 if (fcport->port_type == FCT_INITIATOR)
a6a6d058 5364 rport_ids.roles |= FC_PORT_ROLE_FCP_INITIATOR;
8482e118 5365 if (fcport->port_type == FCT_TARGET)
a6a6d058
HR		 5366 rport_ids.roles |= FC_PORT_ROLE_FCP_TARGET;
5367 if (fcport->port_type & FCT_NVME_INITIATOR)
5368 rport_ids.roles |= FC_PORT_ROLE_NVME_INITIATOR;
5369 if (fcport->port_type & FCT_NVME_TARGET)
5370 rport_ids.roles |= FC_PORT_ROLE_NVME_TARGET;
5371 if (fcport->port_type & FCT_NVME_DISCOVERY)
5372 rport_ids.roles |= FC_PORT_ROLE_NVME_DISCOVERY;
726b8548 5373
83548fe2
QT		 5374 ql_dbg(ql_dbg_disc, vha, 0x20ee,
5375 "%s %8phN. rport %p is %s mode\n",
5376 __func__, fcport->port_name, rport,
a6a6d058 5377 (fcport->port_type == FCT_TARGET) ? "tgt" :
c1c7178c 5378 ((fcport->port_type & FCT_NVME) ? "nvme" : "ini"));
726b8548 5379
77d74143 5380 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 5381}
5382
23be331d
AB		 5383/*
5384 * qla2x00_update_fcport
5385 * Updates device on list.
5386 *
5387 * Input:
5388 * ha = adapter block pointer.
5389 * fcport = port structure pointer.
5390 *
5391 * Return:
5392 * 0 - Success
5393 * BIT_0 - error
5394 *
5395 * Context:
5396 * Kernel context.
5397 */
5398void
e315cd28 5399qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 5400{
726b8548
QT		 5401 if (IS_SW_RESV_ADDR(fcport->d_id))
5402 return;
5403
cd4ed6b4
QT		 5404 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n",
5405 __func__, fcport->port_name);
5406
5407 fcport->disc_state = DSC_UPD_FCPORT;
5408 fcport->login_retry = vha->hw->login_retry_count;
b63d8b89 5409 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
b63d8b89
QT		 5410 fcport->deleted = 0;
5411 fcport->logout_on_delete = 1;
8777e431 5412 fcport->n2n_chip_reset = fcport->n2n_link_reset_cnt = 0;
23be331d 5413
8777e431
QT		 5414 switch (vha->hw->current_topology) {
5415 case ISP_CFG_N:
5416 case ISP_CFG_NL:
5417 fcport->keep_nport_handle = 1;
5418 break;
5419 default:
5420 break;
5421 }
5422
aecf0434
QT		 5423 qla2x00_iidma_fcport(vha, fcport);
5424
e84067d7
DG		 5425 if (fcport->fc4f_nvme) {
5426 qla_nvme_register_remote(vha, fcport);
b63d8b89
QT		 5427 fcport->disc_state = DSC_LOGIN_COMPLETE;
5428 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e84067d7
DG		 5429 return;
5430 }
5431
21090cbe 5432 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b 5433
726b8548
QT		 5434 switch (vha->host->active_mode) {
5435 case MODE_INITIATOR:
d20ed91b 5436 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 5437 break;
5438 case MODE_TARGET:
5439 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5440 !vha->vha_tgt.qla_tgt->tgt_stopped)
5441 qlt_fc_port_added(vha, fcport);
5442 break;
5443 case MODE_DUAL:
d20ed91b 5444 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 5445 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5446 !vha->vha_tgt.qla_tgt->tgt_stopped)
5447 qlt_fc_port_added(vha, fcport);
5448 break;
5449 default:
5450 break;
d20ed91b 5451 }
cc28e0ac 5452
aecf0434
QT		 5453 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
5454
cc28e0ac
QT		 5455 if (IS_IIDMA_CAPABLE(vha->hw) && vha->hw->flags.gpsc_supported) {
5456 if (fcport->id_changed) {
5457 fcport->id_changed = 0;
5458 ql_dbg(ql_dbg_disc, vha, 0x20d7,
5459 "%s %d %8phC post gfpnid fcp_cnt %d\n",
5460 __func__, __LINE__, fcport->port_name,
5461 vha->fcport_count);
5462 qla24xx_post_gfpnid_work(vha, fcport);
5463 } else {
5464 ql_dbg(ql_dbg_disc, vha, 0x20d7,
5465 "%s %d %8phC post gpsc fcp_cnt %d\n",
5466 __func__, __LINE__, fcport->port_name,
5467 vha->fcport_count);
5468 qla24xx_post_gpsc_work(vha, fcport);
5469 }
5470 }
cd4ed6b4
QT		 5471
5472 fcport->disc_state = DSC_LOGIN_COMPLETE;
5473}
5474
5475void qla_register_fcport_fn(struct work_struct *work)
5476{
5477 fc_port_t *fcport = container_of(work, struct fc_port, reg_work);
5478 u32 rscn_gen = fcport->rscn_gen;
5479 u16 data[2];
5480
5481 if (IS_SW_RESV_ADDR(fcport->d_id))
5482 return;
5483
5484 qla2x00_update_fcport(fcport->vha, fcport);
5485
5486 if (rscn_gen != fcport->rscn_gen) {
5487 /* RSCN(s) came in while registration */
5488 switch (fcport->next_disc_state) {
5489 case DSC_DELETE_PEND:
5490 qlt_schedule_sess_for_deletion(fcport);
5491 break;
5492 case DSC_ADISC:
5493 data[0] = data[1] = 0;
5494 qla2x00_post_async_adisc_work(fcport->vha, fcport,
5495 data);
5496 break;
5497 default:
5498 break;
5499 }
5500 }
23be331d
AB		 5501}
5502
1da177e4
LT		 5503/*
5504 * qla2x00_configure_fabric
5505 * Setup SNS devices with loop ID's.
5506 *
5507 * Input:
5508 * ha = adapter block pointer.
5509 *
5510 * Returns:
5511 * 0 = success.
5512 * BIT_0 = error
5513 */
5514static int
e315cd28 5515qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 5516{
b3b02e6e 5517 int rval;
726b8548 5518 fc_port_t *fcport;
1da177e4 5519 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 5520 uint16_t loop_id;
1da177e4 5521 LIST_HEAD(new_fcports);
e315cd28 5522 struct qla_hw_data *ha = vha->hw;
df673274 5523 int discovery_gen;
1da177e4
LT		 5524
5525 /* If FL port exists, then SNS is present */
e428924c 5526 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 5527 loop_id = NPH_F_PORT;
5528 else
5529 loop_id = SNS_FL_PORT;
e315cd28 5530 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 5531 if (rval != QLA_SUCCESS) {
83548fe2 5532 ql_dbg(ql_dbg_disc, vha, 0x20a0,
7c3df132 5533 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 5534
e315cd28 5535 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 5536 return (QLA_SUCCESS);
5537 }
e315cd28 5538 vha->device_flags |= SWITCH_FOUND;
1da177e4 5539
41dc529a
QT		 5540
5541 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
5542 rval = qla2x00_send_change_request(vha, 0x3, 0);
5543 if (rval != QLA_SUCCESS)
5544 ql_log(ql_log_warn, vha, 0x121,
5545 "Failed to enable receiving of RSCN requests: 0x%x.\n",
5546 rval);
5547 }
5548
5549
1da177e4 5550 do {
726b8548
QT		 5551 qla2x00_mgmt_svr_login(vha);
5552
cca5335c
AV		 5553 /* FDMI support. */
5554 if (ql2xfdmienable &&
e315cd28
AC		 5555 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
5556 qla2x00_fdmi_register(vha);
cca5335c 5557
1da177e4 5558 /* Ensure we are logged into the SNS. */
a14c7711 5559 loop_id = NPH_SNS_LID(ha);
0b91d116
CD		 5560 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
5561 0xfc, mb, BIT_1|BIT_0);
a14c7711
JC		 5562 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5563 ql_dbg(ql_dbg_disc, vha, 0x20a1,
5564 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n",
5565 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval);
0b91d116 5566 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 5567 return rval;
0b91d116 5568 }
e315cd28
AC		 5569 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
5570 if (qla2x00_rft_id(vha)) {
1da177e4 5571 /* EMPTY */
83548fe2 5572 ql_dbg(ql_dbg_disc, vha, 0x20a2,
7c3df132 5573 "Register FC-4 TYPE failed.\n");
b98ae0d7
QT		 5574 if (test_bit(LOOP_RESYNC_NEEDED,
5575 &vha->dpc_flags))
5576 break;
1da177e4 5577 }
d3bae931 5578 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) {
1da177e4 5579 /* EMPTY */
83548fe2 5580 ql_dbg(ql_dbg_disc, vha, 0x209a,
7c3df132 5581 "Register FC-4 Features failed.\n");
b98ae0d7
QT		 5582 if (test_bit(LOOP_RESYNC_NEEDED,
5583 &vha->dpc_flags))
5584 break;
1da177e4 5585 }
d3bae931
DG		 5586 if (vha->flags.nvme_enabled) {
5587 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) {
5588 ql_dbg(ql_dbg_disc, vha, 0x2049,
5589 "Register NVME FC Type Features failed.\n");
5590 }
5591 }
e315cd28 5592 if (qla2x00_rnn_id(vha)) {
1da177e4 5593 /* EMPTY */
83548fe2 5594 ql_dbg(ql_dbg_disc, vha, 0x2104,
7c3df132 5595 "Register Node Name failed.\n");
b98ae0d7
QT		 5596 if (test_bit(LOOP_RESYNC_NEEDED,
5597 &vha->dpc_flags))
5598 break;
e315cd28 5599 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 5600 /* EMPTY */
83548fe2 5601 ql_dbg(ql_dbg_disc, vha, 0x209b,
0bf0efa1 5602 "Register Symbolic Node Name failed.\n");
b98ae0d7
QT		 5603 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5604 break;
1da177e4
LT		 5605 }
5606 }
5607
827210ba 5608
df673274
AP		 5609 /* Mark the time right before querying FW for connected ports.
5610 * This process is long, asynchronous and by the time it's done,
5611 * collected information might not be accurate anymore. E.g.
5612 * disconnected port might have re-connected and a brand new
5613 * session has been created. In this case session's generation
5614 * will be newer than discovery_gen. */
5615 qlt_do_generation_tick(vha, &discovery_gen);
5616
a4239945 5617 if (USE_ASYNC_SCAN(ha)) {
33b28357
QT		 5618 rval = qla24xx_async_gpnft(vha, FC4_TYPE_FCP_SCSI,
5619 NULL);
a4239945
QT		 5620 if (rval)
5621 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5622 } else {
f352eeb7
QT		 5623 list_for_each_entry(fcport, &vha->vp_fcports, list)
5624 fcport->scan_state = QLA_FCPORT_SCAN;
5625
a4239945
QT		 5626 rval = qla2x00_find_all_fabric_devs(vha);
5627 }
1da177e4
LT		 5628 if (rval != QLA_SUCCESS)
5629 break;
1da177e4
LT		 5630 } while (0);
5631
e84067d7
DG		 5632 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
5633 qla_nvme_register_hba(vha);
5634
726b8548 5635 if (rval)
7c3df132
SK		 5636 ql_dbg(ql_dbg_disc, vha, 0x2068,
5637 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 5638
5639 return (rval);
5640}
5641
1da177e4
LT		 5642/*
5643 * qla2x00_find_all_fabric_devs
5644 *
5645 * Input:
5646 * ha = adapter block pointer.
5647 * dev = database device entry pointer.
5648 *
5649 * Returns:
5650 * 0 = success.
5651 *
5652 * Context:
5653 * Kernel context.
5654 */
5655static int
726b8548 5656qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
1da177e4
LT		 5657{
5658 int rval;
5659 uint16_t loop_id;
726b8548 5660 fc_port_t *fcport, *new_fcport;
1da177e4
LT		 5661 int found;
5662
5663 sw_info_t *swl;
5664 int swl_idx;
5665 int first_dev, last_dev;
1516ef44 5666 port_id_t wrap = {}, nxt_d_id;
e315cd28 5667 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 5668 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
726b8548 5669 unsigned long flags;
1da177e4
LT		 5670
5671 rval = QLA_SUCCESS;
5672
5673 /* Try GID_PT to get device list, else GAN. */
7a67735b 5674 if (!ha->swl)
642ef983 5675 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 5676 GFP_KERNEL);
5677 swl = ha->swl;
bbfbbbc1 5678 if (!swl) {
1da177e4 5679 /*EMPTY*/
83548fe2 5680 ql_dbg(ql_dbg_disc, vha, 0x209c,
7c3df132 5681 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 5682 } else {
642ef983 5683 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 5684 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 5685 swl = NULL;
b98ae0d7
QT		 5686 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5687 return rval;
e315cd28 5688 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5689 swl = NULL;
b98ae0d7
QT		 5690 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5691 return rval;
e315cd28 5692 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5693 swl = NULL;
b98ae0d7
QT		 5694 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5695 return rval;
726b8548
QT		 5696 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
5697 swl = NULL;
b98ae0d7
QT		 5698 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5699 return rval;
1da177e4 5700 }
e8c72ba5
CD		 5701
5702 /* If other queries succeeded probe for FC-4 type */
b98ae0d7 5703 if (swl) {
e8c72ba5 5704 qla2x00_gff_id(vha, swl);
b98ae0d7
QT		 5705 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5706 return rval;
5707 }
1da177e4
LT		 5708 }
5709 swl_idx = 0;
5710
5711 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 5712 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5713 if (new_fcport == NULL) {
83548fe2 5714 ql_log(ql_log_warn, vha, 0x209d,
7c3df132 5715 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 5716 return (QLA_MEMORY_ALLOC_FAILED);
5717 }
5718 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 5719 /* Set start port ID scan at adapter ID. */
5720 first_dev = 1;
5721 last_dev = 0;
5722
5723 /* Starting free loop ID. */
e315cd28
AC		 5724 loop_id = ha->min_external_loopid;
5725 for (; loop_id <= ha->max_loop_id; loop_id++) {
5726 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 5727 continue;
5728
3a6478df
GM		 5729 if (ha->current_topology == ISP_CFG_FL &&
5730 (atomic_read(&vha->loop_down_timer) ||
5731 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 5732 atomic_set(&vha->loop_down_timer, 0);
5733 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5734 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 5735 break;
bb2d52b2 5736 }
1da177e4
LT		 5737
5738 if (swl != NULL) {
5739 if (last_dev) {
5740 wrap.b24 = new_fcport->d_id.b24;
5741 } else {
5742 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
5743 memcpy(new_fcport->node_name,
5744 swl[swl_idx].node_name, WWN_SIZE);
5745 memcpy(new_fcport->port_name,
5746 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 5747 memcpy(new_fcport->fabric_port_name,
5748 swl[swl_idx].fabric_port_name, WWN_SIZE);
5749 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 5750 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4 5751
a5d42f4c 5752 new_fcport->nvme_flag = 0;
1a28faa0 5753 new_fcport->fc4f_nvme = 0;
a5d42f4c
DG		 5754 if (vha->flags.nvme_enabled &&
5755 swl[swl_idx].fc4f_nvme) {
5756 new_fcport->fc4f_nvme =
5757 swl[swl_idx].fc4f_nvme;
5758 ql_log(ql_log_info, vha, 0x2131,
5759 "FOUND: NVME port %8phC as FC Type 28h\n",
5760 new_fcport->port_name);
5761 }
5762
1da177e4
LT		 5763 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
5764 last_dev = 1;
5765 }
5766 swl_idx++;
5767 }
5768 } else {
5769 /* Send GA_NXT to the switch */
e315cd28 5770 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 5771 if (rval != QLA_SUCCESS) {
83548fe2 5772 ql_log(ql_log_warn, vha, 0x209e,
7c3df132
SK		 5773 "SNS scan failed -- assuming "
5774 "zero-entry result.\n");
1da177e4
LT		 5775 rval = QLA_SUCCESS;
5776 break;
5777 }
5778 }
5779
5780 /* If wrap on switch device list, exit. */
5781 if (first_dev) {
5782 wrap.b24 = new_fcport->d_id.b24;
5783 first_dev = 0;
5784 } else if (new_fcport->d_id.b24 == wrap.b24) {
83548fe2 5785 ql_dbg(ql_dbg_disc, vha, 0x209f,
7c3df132
SK		 5786 "Device wrap (%02x%02x%02x).\n",
5787 new_fcport->d_id.b.domain,
5788 new_fcport->d_id.b.area,
5789 new_fcport->d_id.b.al_pa);
1da177e4
LT		 5790 break;
5791 }
5792
2c3dfe3f 5793 /* Bypass if same physical adapter. */
e315cd28 5794 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 5795 continue;
5796
2c3dfe3f 5797 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 5798 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
5799 continue;
2c3dfe3f 5800
f7d289f6
AV		 5801 /* Bypass if same domain and area of adapter. */
5802 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 5803 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 5804 ISP_CFG_FL)
5805 continue;
5806
1da177e4
LT		 5807 /* Bypass reserved domain fields. */
5808 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
5809 continue;
5810
e8c72ba5 5811 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 5812 if (ql2xgffidenable &&
5813 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
5814 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 5815 continue;
5816
726b8548
QT		 5817 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5818
1da177e4
LT		 5819 /* Locate matching device in database. */
5820 found = 0;
e315cd28 5821 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 5822 if (memcmp(new_fcport->port_name, fcport->port_name,
5823 WWN_SIZE))
5824 continue;
5825
827210ba 5826 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 5827
1da177e4
LT		 5828 found++;
5829
d8b45213
AV		 5830 /* Update port state. */
5831 memcpy(fcport->fabric_port_name,
5832 new_fcport->fabric_port_name, WWN_SIZE);
5833 fcport->fp_speed = new_fcport->fp_speed;
5834
1da177e4 5835 /*
b2032fd5
RD		 5836 * If address the same and state FCS_ONLINE
5837 * (or in target mode), nothing changed.
1da177e4
LT		 5838 */
5839 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5 5840 (atomic_read(&fcport->state) == FCS_ONLINE ||
726b8548 5841 (vha->host->active_mode == MODE_TARGET))) {
1da177e4
LT		 5842 break;
5843 }
5844
5845 /*
5846 * If device was not a fabric device before.
5847 */
5848 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
5849 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 5850 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 5851 fcport->flags |= (FCF_FABRIC_DEVICE |
5852 FCF_LOGIN_NEEDED);
1da177e4
LT		 5853 break;
5854 }
5855
5856 /*
5857 * Port ID changed or device was marked to be updated;
5858 * Log it out if still logged in and mark it for
5859 * relogin later.
5860 */
726b8548 5861 if (qla_tgt_mode_enabled(base_vha)) {
b2032fd5
RD		 5862 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
5863 "port changed FC ID, %8phC"
5864 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
5865 fcport->port_name,
5866 fcport->d_id.b.domain,
5867 fcport->d_id.b.area,
5868 fcport->d_id.b.al_pa,
5869 fcport->loop_id,
5870 new_fcport->d_id.b.domain,
5871 new_fcport->d_id.b.area,
5872 new_fcport->d_id.b.al_pa);
5873 fcport->d_id.b24 = new_fcport->d_id.b24;
5874 break;
5875 }
5876
1da177e4
LT		 5877 fcport->d_id.b24 = new_fcport->d_id.b24;
5878 fcport->flags |= FCF_LOGIN_NEEDED;
1da177e4
LT		 5879 break;
5880 }
5881
9dd9686b
DT		 5882 if (fcport->fc4f_nvme) {
5883 if (fcport->disc_state == DSC_DELETE_PEND) {
5884 fcport->disc_state = DSC_GNL;
5885 vha->fcport_count--;
5886 fcport->login_succ = 0;
5887 }
5888 }
5889
726b8548
QT		 5890 if (found) {
5891 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1da177e4 5892 continue;
726b8548 5893 }
1da177e4 5894 /* If device was not in our fcports list, then add it. */
b2032fd5 5895 new_fcport->scan_state = QLA_FCPORT_FOUND;
726b8548
QT		 5896 list_add_tail(&new_fcport->list, &vha->vp_fcports);
5897
5898 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5899
1da177e4
LT		 5900
5901 /* Allocate a new replacement fcport. */
5902 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 5903 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5904 if (new_fcport == NULL) {
83548fe2 5905 ql_log(ql_log_warn, vha, 0xd032,
7c3df132 5906 "Memory allocation failed for fcport.\n");
1da177e4
LT		 5907 return (QLA_MEMORY_ALLOC_FAILED);
5908 }
5909 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
5910 new_fcport->d_id.b24 = nxt_d_id.b24;
5911 }
5912
726b8548
QT		 5913 qla2x00_free_fcport(new_fcport);
5914
5915 /*
5916 * Logout all previous fabric dev marked lost, except FCP2 devices.
5917 */
5918 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5919 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5920 break;
5921
5922 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
5923 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
5924 continue;
5925
5926 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5927 if ((qla_dual_mode_enabled(vha) ||
5928 qla_ini_mode_enabled(vha)) &&
5929 atomic_read(&fcport->state) == FCS_ONLINE) {
5930 qla2x00_mark_device_lost(vha, fcport,
5931 ql2xplogiabsentdevice, 0);
5932 if (fcport->loop_id != FC_NO_LOOP_ID &&
5933 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5934 fcport->port_type != FCT_INITIATOR &&
5935 fcport->port_type != FCT_BROADCAST) {
83548fe2 5936 ql_dbg(ql_dbg_disc, vha, 0x20f0,
726b8548
QT		 5937 "%s %d %8phC post del sess\n",
5938 __func__, __LINE__,
5939 fcport->port_name);
d8630bb9 5940 qlt_schedule_sess_for_deletion(fcport);
726b8548
QT		 5941 continue;
5942 }
5943 }
5944 }
1da177e4 5945
726b8548
QT		 5946 if (fcport->scan_state == QLA_FCPORT_FOUND)
5947 qla24xx_fcport_handle_login(vha, fcport);
5948 }
1da177e4
LT		 5949 return (rval);
5950}
5951
f6602f3b
QT		 5952/* FW does not set aside Loop id for MGMT Server/FFFFFAh */
5953int
5954qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *vha)
5955{
5956 int loop_id = FC_NO_LOOP_ID;
5957 int lid = NPH_MGMT_SERVER - vha->vp_idx;
5958 unsigned long flags;
5959 struct qla_hw_data *ha = vha->hw;
5960
5961 if (vha->vp_idx == 0) {
5962 set_bit(NPH_MGMT_SERVER, ha->loop_id_map);
5963 return NPH_MGMT_SERVER;
5964 }
5965
5966 /* pick id from high and work down to low */
5967 spin_lock_irqsave(&ha->vport_slock, flags);
5968 for (; lid > 0; lid--) {
5969 if (!test_bit(lid, vha->hw->loop_id_map)) {
5970 set_bit(lid, vha->hw->loop_id_map);
5971 loop_id = lid;
5972 break;
5973 }
5974 }
5975 spin_unlock_irqrestore(&ha->vport_slock, flags);
5976
5977 return loop_id;
5978}
5979
1da177e4
LT		 5980/*
5981 * qla2x00_fabric_login
5982 * Issue fabric login command.
5983 *
5984 * Input:
5985 * ha = adapter block pointer.
5986 * device = pointer to FC device type structure.
5987 *
5988 * Returns:
5989 * 0 - Login successfully
5990 * 1 - Login failed
5991 * 2 - Initiator device
5992 * 3 - Fatal error
5993 */
5994int
e315cd28 5995qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 5996 uint16_t *next_loopid)
5997{
5998 int rval;
5999 int retry;
6000 uint16_t tmp_loopid;
6001 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 6002 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 6003
6004 retry = 0;
6005 tmp_loopid = 0;
6006
6007 for (;;) {
7c3df132
SK		 6008 ql_dbg(ql_dbg_disc, vha, 0x2000,
6009 "Trying Fabric Login w/loop id 0x%04x for port "
6010 "%02x%02x%02x.\n",
6011 fcport->loop_id, fcport->d_id.b.domain,
6012 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 6013
6014 /* Login fcport on switch. */
0b91d116 6015 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 6016 fcport->d_id.b.domain, fcport->d_id.b.area,
6017 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 6018 if (rval != QLA_SUCCESS) {
6019 return rval;
6020 }
1da177e4
LT		 6021 if (mb[0] == MBS_PORT_ID_USED) {
6022 /*
6023 * Device has another loop ID. The firmware team
0107109e
AV		 6024 * recommends the driver perform an implicit login with
6025 * the specified ID again. The ID we just used is save
6026 * here so we return with an ID that can be tried by
6027 * the next login.
1da177e4
LT		 6028 */
6029 retry++;
6030 tmp_loopid = fcport->loop_id;
6031 fcport->loop_id = mb[1];
6032
7c3df132
SK		 6033 ql_dbg(ql_dbg_disc, vha, 0x2001,
6034 "Fabric Login: port in use - next loop "
6035 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 6036 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 6037 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 6038
6039 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
6040 /*
6041 * Login succeeded.
6042 */
6043 if (retry) {
6044 /* A retry occurred before. */
6045 *next_loopid = tmp_loopid;
6046 } else {
6047 /*
6048 * No retry occurred before. Just increment the
6049 * ID value for next login.
6050 */
6051 *next_loopid = (fcport->loop_id + 1);
6052 }
6053
6054 if (mb[1] & BIT_0) {
6055 fcport->port_type = FCT_INITIATOR;
6056 } else {
6057 fcport->port_type = FCT_TARGET;
6058 if (mb[1] & BIT_1) {
8474f3a0 6059 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 6060 }
6061 }
6062
ad3e0eda
AV		 6063 if (mb[10] & BIT_0)
6064 fcport->supported_classes |= FC_COS_CLASS2;
6065 if (mb[10] & BIT_1)
6066 fcport->supported_classes |= FC_COS_CLASS3;
6067
2d70c103
NB		 6068 if (IS_FWI2_CAPABLE(ha)) {
6069 if (mb[10] & BIT_7)
6070 fcport->flags |=
6071 FCF_CONF_COMP_SUPPORTED;
6072 }
6073
1da177e4
LT		 6074 rval = QLA_SUCCESS;
6075 break;
6076 } else if (mb[0] == MBS_LOOP_ID_USED) {
6077 /*
6078 * Loop ID already used, try next loop ID.
6079 */
6080 fcport->loop_id++;
e315cd28 6081 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 6082 if (rval != QLA_SUCCESS) {
6083 /* Ran out of loop IDs to use */
6084 break;
6085 }
6086 } else if (mb[0] == MBS_COMMAND_ERROR) {
6087 /*
6088 * Firmware possibly timed out during login. If NO
6089 * retries are left to do then the device is declared
6090 * dead.
6091 */
6092 *next_loopid = fcport->loop_id;
e315cd28 6093 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 6094 fcport->d_id.b.domain, fcport->d_id.b.area,
6095 fcport->d_id.b.al_pa);
e315cd28 6096 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 6097
6098 rval = 1;
6099 break;
6100 } else {
6101 /*
6102 * unrecoverable / not handled error
6103 */
7c3df132
SK		 6104 ql_dbg(ql_dbg_disc, vha, 0x2002,
6105 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
6106 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
6107 fcport->d_id.b.area, fcport->d_id.b.al_pa,
6108 fcport->loop_id, jiffies);
1da177e4
LT		 6109
6110 *next_loopid = fcport->loop_id;
e315cd28 6111 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 6112 fcport->d_id.b.domain, fcport->d_id.b.area,
6113 fcport->d_id.b.al_pa);
5f16b331 6114 qla2x00_clear_loop_id(fcport);
0eedfcf0 6115 fcport->login_retry = 0;
1da177e4
LT		 6116
6117 rval = 3;
6118 break;
6119 }
6120 }
6121
6122 return (rval);
6123}
6124
6125/*
6126 * qla2x00_local_device_login
6127 * Issue local device login command.
6128 *
6129 * Input:
6130 * ha = adapter block pointer.
6131 * loop_id = loop id of device to login to.
6132 *
6133 * Returns (Where's the #define!!!!):
6134 * 0 - Login successfully
6135 * 1 - Login failed
6136 * 3 - Fatal error
6137 */
6138int
e315cd28 6139qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 6140{
6141 int rval;
6142 uint16_t mb[MAILBOX_REGISTER_COUNT];
6143
6144 memset(mb, 0, sizeof(mb));
e315cd28 6145 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 6146 if (rval == QLA_SUCCESS) {
6147 /* Interrogate mailbox registers for any errors */
6148 if (mb[0] == MBS_COMMAND_ERROR)
6149 rval = 1;
6150 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
6151 /* device not in PCB table */
6152 rval = 3;
6153 }
6154
6155 return (rval);
6156}
6157
6158/*
6159 * qla2x00_loop_resync
6160 * Resync with fibre channel devices.
6161 *
6162 * Input:
6163 * ha = adapter block pointer.
6164 *
6165 * Returns:
6166 * 0 = success
6167 */
6168int
e315cd28 6169qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 6170{
73208dfd 6171 int rval = QLA_SUCCESS;
1da177e4 6172 uint32_t wait_time;
1da177e4 6173
e315cd28
AC		 6174 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6175 if (vha->flags.online) {
6176 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 6177 /* Wait at most MAX_TARGET RSCNs for a stable link. */
6178 wait_time = 256;
6179 do {
8ae6d9c7
GM		 6180 if (!IS_QLAFX00(vha->hw)) {
6181 /*
6182 * Issue a marker after FW becomes
6183 * ready.
6184 */
9eb9c6dc
QT		 6185 qla2x00_marker(vha, vha->hw->base_qpair,
6186 0, 0, MK_SYNC_ALL);
8ae6d9c7
GM		 6187 vha->marker_needed = 0;
6188 }
1da177e4
LT		 6189
6190 /* Remap devices on Loop. */
e315cd28 6191 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 6192
8ae6d9c7
GM		 6193 if (IS_QLAFX00(vha->hw))
6194 qlafx00_configure_devices(vha);
6195 else
6196 qla2x00_configure_loop(vha);
6197
1da177e4 6198 wait_time--;
e315cd28
AC		 6199 } while (!atomic_read(&vha->loop_down_timer) &&
6200 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
6201 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
6202 &vha->dpc_flags)));
1da177e4 6203 }
1da177e4
LT		 6204 }
6205
e315cd28 6206 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 6207 return (QLA_FUNCTION_FAILED);
1da177e4 6208
e315cd28 6209 if (rval)
7c3df132
SK		 6210 ql_dbg(ql_dbg_disc, vha, 0x206c,
6211 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 6212
6213 return (rval);
6214}
6215
579d12b5
SK		 6216/*
6217* qla2x00_perform_loop_resync
6218* Description: This function will set the appropriate flags and call
6219* qla2x00_loop_resync. If successful loop will be resynced
6220* Arguments : scsi_qla_host_t pointer
6221* returm : Success or Failure
6222*/
6223
6224int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
6225{
6226 int32_t rval = 0;
6227
6228 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
6229 /*Configure the flags so that resync happens properly*/
6230 atomic_set(&ha->loop_down_timer, 0);
6231 if (!(ha->device_flags & DFLG_NO_CABLE)) {
6232 atomic_set(&ha->loop_state, LOOP_UP);
6233 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
6234 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
6235 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
6236
6237 rval = qla2x00_loop_resync(ha);
6238 } else
6239 atomic_set(&ha->loop_state, LOOP_DEAD);
6240
6241 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
6242 }
6243
6244 return rval;
6245}
6246
d97994dc 6247void
67becc00 6248qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 6249{
6250 fc_port_t *fcport;
feafb7b1
AE		 6251 struct scsi_qla_host *vha;
6252 struct qla_hw_data *ha = base_vha->hw;
6253 unsigned long flags;
d97994dc 6254
feafb7b1 6255 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 6256 /* Go with deferred removal of rport references. */
feafb7b1
AE		 6257 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
6258 atomic_inc(&vha->vref_count);
6259 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 6260 if (fcport->drport &&
feafb7b1
AE		 6261 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
6262 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 6263 qla2x00_rport_del(fcport);
df673274 6264
feafb7b1
AE		 6265 spin_lock_irqsave(&ha->vport_slock, flags);
6266 }
6267 }
6268 atomic_dec(&vha->vref_count);
c4a9b538 6269 wake_up(&vha->vref_waitq);
feafb7b1
AE		 6270 }
6271 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 6272}
6273
7d613ac6
SV		 6274/* Assumes idc_lock always held on entry */
6275void
6276qla83xx_reset_ownership(scsi_qla_host_t *vha)
6277{
6278 struct qla_hw_data *ha = vha->hw;
6279 uint32_t drv_presence, drv_presence_mask;
6280 uint32_t dev_part_info1, dev_part_info2, class_type;
6281 uint32_t class_type_mask = 0x3;
6282 uint16_t fcoe_other_function = 0xffff, i;
6283
7ec0effd
AD		 6284 if (IS_QLA8044(ha)) {
6285 drv_presence = qla8044_rd_direct(vha,
6286 QLA8044_CRB_DRV_ACTIVE_INDEX);
6287 dev_part_info1 = qla8044_rd_direct(vha,
6288 QLA8044_CRB_DEV_PART_INFO_INDEX);
6289 dev_part_info2 = qla8044_rd_direct(vha,
6290 QLA8044_CRB_DEV_PART_INFO2);
6291 } else {
6292 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6293 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
6294 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
6295 }
7d613ac6
SV		 6296 for (i = 0; i < 8; i++) {
6297 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
6298 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
6299 (i != ha->portnum)) {
6300 fcoe_other_function = i;
6301 break;
6302 }
6303 }
6304 if (fcoe_other_function == 0xffff) {
6305 for (i = 0; i < 8; i++) {
6306 class_type = ((dev_part_info2 >> (i * 4)) &
6307 class_type_mask);
6308 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
6309 ((i + 8) != ha->portnum)) {
6310 fcoe_other_function = i + 8;
6311 break;
6312 }
6313 }
6314 }
6315 /*
6316 * Prepare drv-presence mask based on fcoe functions present.
6317 * However consider only valid physical fcoe function numbers (0-15).
6318 */
6319 drv_presence_mask = ~((1 << (ha->portnum)) |
6320 ((fcoe_other_function == 0xffff) ?
6321 0 : (1 << (fcoe_other_function))));
6322
6323 /* We are the reset owner iff:
6324 * - No other protocol drivers present.
6325 * - This is the lowest among fcoe functions. */
6326 if (!(drv_presence & drv_presence_mask) &&
6327 (ha->portnum < fcoe_other_function)) {
6328 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
6329 "This host is Reset owner.\n");
6330 ha->flags.nic_core_reset_owner = 1;
6331 }
6332}
6333
fa492630 6334static int
7d613ac6
SV		 6335__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
6336{
6337 int rval = QLA_SUCCESS;
6338 struct qla_hw_data *ha = vha->hw;
6339 uint32_t drv_ack;
6340
6341 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6342 if (rval == QLA_SUCCESS) {
6343 drv_ack |= (1 << ha->portnum);
6344 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6345 }
6346
6347 return rval;
6348}
6349
fa492630 6350static int
7d613ac6
SV		 6351__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
6352{
6353 int rval = QLA_SUCCESS;
6354 struct qla_hw_data *ha = vha->hw;
6355 uint32_t drv_ack;
6356
6357 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6358 if (rval == QLA_SUCCESS) {
6359 drv_ack &= ~(1 << ha->portnum);
6360 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6361 }
6362
6363 return rval;
6364}
6365
fa492630 6366static const char *
7d613ac6
SV		 6367qla83xx_dev_state_to_string(uint32_t dev_state)
6368{
6369 switch (dev_state) {
6370 case QLA8XXX_DEV_COLD:
6371 return "COLD/RE-INIT";
6372 case QLA8XXX_DEV_INITIALIZING:
6373 return "INITIALIZING";
6374 case QLA8XXX_DEV_READY:
6375 return "READY";
6376 case QLA8XXX_DEV_NEED_RESET:
6377 return "NEED RESET";
6378 case QLA8XXX_DEV_NEED_QUIESCENT:
6379 return "NEED QUIESCENT";
6380 case QLA8XXX_DEV_FAILED:
6381 return "FAILED";
6382 case QLA8XXX_DEV_QUIESCENT:
6383 return "QUIESCENT";
6384 default:
6385 return "Unknown";
6386 }
6387}
6388
6389/* Assumes idc-lock always held on entry */
6390void
6391qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
6392{
6393 struct qla_hw_data *ha = vha->hw;
6394 uint32_t idc_audit_reg = 0, duration_secs = 0;
6395
6396 switch (audit_type) {
6397 case IDC_AUDIT_TIMESTAMP:
6398 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
6399 idc_audit_reg = (ha->portnum) |
6400 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
6401 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6402 break;
6403
6404 case IDC_AUDIT_COMPLETION:
6405 duration_secs = ((jiffies_to_msecs(jiffies) -
6406 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
6407 idc_audit_reg = (ha->portnum) |
6408 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
6409 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6410 break;
6411
6412 default:
6413 ql_log(ql_log_warn, vha, 0xb078,
6414 "Invalid audit type specified.\n");
6415 break;
6416 }
6417}
6418
6419/* Assumes idc_lock always held on entry */
fa492630 6420static int
7d613ac6
SV		 6421qla83xx_initiating_reset(scsi_qla_host_t *vha)
6422{
6423 struct qla_hw_data *ha = vha->hw;
6424 uint32_t idc_control, dev_state;
6425
6426 __qla83xx_get_idc_control(vha, &idc_control);
6427 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
6428 ql_log(ql_log_info, vha, 0xb080,
6429 "NIC Core reset has been disabled. idc-control=0x%x\n",
6430 idc_control);
6431 return QLA_FUNCTION_FAILED;
6432 }
6433
6434 /* Set NEED-RESET iff in READY state and we are the reset-owner */
6435 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6436 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
6437 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
6438 QLA8XXX_DEV_NEED_RESET);
6439 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
6440 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
6441 } else {
6442 const char *state = qla83xx_dev_state_to_string(dev_state);
bd432bb5 6443
7d613ac6
SV		 6444 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
6445
6446 /* SV: XXX: Is timeout required here? */
6447 /* Wait for IDC state change READY -> NEED_RESET */
6448 while (dev_state == QLA8XXX_DEV_READY) {
6449 qla83xx_idc_unlock(vha, 0);
6450 msleep(200);
6451 qla83xx_idc_lock(vha, 0);
6452 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6453 }
6454 }
6455
6456 /* Send IDC ack by writing to drv-ack register */
6457 __qla83xx_set_drv_ack(vha);
6458
6459 return QLA_SUCCESS;
6460}
6461
6462int
6463__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
6464{
6465 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6466}
6467
7d613ac6
SV		 6468int
6469__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
6470{
6471 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6472}
6473
fa492630 6474static int
7d613ac6
SV		 6475qla83xx_check_driver_presence(scsi_qla_host_t *vha)
6476{
6477 uint32_t drv_presence = 0;
6478 struct qla_hw_data *ha = vha->hw;
6479
6480 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6481 if (drv_presence & (1 << ha->portnum))
6482 return QLA_SUCCESS;
6483 else
6484 return QLA_TEST_FAILED;
6485}
6486
6487int
6488qla83xx_nic_core_reset(scsi_qla_host_t *vha)
6489{
6490 int rval = QLA_SUCCESS;
6491 struct qla_hw_data *ha = vha->hw;
6492
6493 ql_dbg(ql_dbg_p3p, vha, 0xb058,
6494 "Entered %s().\n", __func__);
6495
6496 if (vha->device_flags & DFLG_DEV_FAILED) {
6497 ql_log(ql_log_warn, vha, 0xb059,
6498 "Device in unrecoverable FAILED state.\n");
6499 return QLA_FUNCTION_FAILED;
6500 }
6501
6502 qla83xx_idc_lock(vha, 0);
6503
6504 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
6505 ql_log(ql_log_warn, vha, 0xb05a,
6506 "Function=0x%x has been removed from IDC participation.\n",
6507 ha->portnum);
6508 rval = QLA_FUNCTION_FAILED;
6509 goto exit;
6510 }
6511
6512 qla83xx_reset_ownership(vha);
6513
6514 rval = qla83xx_initiating_reset(vha);
6515
6516 /*
6517 * Perform reset if we are the reset-owner,
6518 * else wait till IDC state changes to READY/FAILED.
6519 */
6520 if (rval == QLA_SUCCESS) {
6521 rval = qla83xx_idc_state_handler(vha);
6522
6523 if (rval == QLA_SUCCESS)
6524 ha->flags.nic_core_hung = 0;
6525 __qla83xx_clear_drv_ack(vha);
6526 }
6527
6528exit:
6529 qla83xx_idc_unlock(vha, 0);
6530
6531 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
6532
6533 return rval;
6534}
6535
81178772
SK		 6536int
6537qla2xxx_mctp_dump(scsi_qla_host_t *vha)
6538{
6539 struct qla_hw_data *ha = vha->hw;
6540 int rval = QLA_FUNCTION_FAILED;
6541
6542 if (!IS_MCTP_CAPABLE(ha)) {
6543 /* This message can be removed from the final version */
6544 ql_log(ql_log_info, vha, 0x506d,
6545 "This board is not MCTP capable\n");
6546 return rval;
6547 }
6548
6549 if (!ha->mctp_dump) {
6550 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
6551 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
6552
6553 if (!ha->mctp_dump) {
6554 ql_log(ql_log_warn, vha, 0x506e,
6555 "Failed to allocate memory for mctp dump\n");
6556 return rval;
6557 }
6558 }
6559
6560#define MCTP_DUMP_STR_ADDR 0x00000000
6561 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
6562 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
6563 if (rval != QLA_SUCCESS) {
6564 ql_log(ql_log_warn, vha, 0x506f,
6565 "Failed to capture mctp dump\n");
6566 } else {
6567 ql_log(ql_log_info, vha, 0x5070,
6568 "Mctp dump capture for host (%ld/%p).\n",
6569 vha->host_no, ha->mctp_dump);
6570 ha->mctp_dumped = 1;
6571 }
6572
409ee0fe 6573 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 6574 ha->flags.nic_core_reset_hdlr_active = 1;
6575 rval = qla83xx_restart_nic_firmware(vha);
6576 if (rval)
6577 /* NIC Core reset failed. */
6578 ql_log(ql_log_warn, vha, 0x5071,
6579 "Failed to restart nic firmware\n");
6580 else
6581 ql_dbg(ql_dbg_p3p, vha, 0xb084,
6582 "Restarted NIC firmware successfully.\n");
6583 ha->flags.nic_core_reset_hdlr_active = 0;
6584 }
6585
6586 return rval;
6587
6588}
6589
579d12b5 6590/*
8fcd6b8b 6591* qla2x00_quiesce_io
579d12b5
SK		 6592* Description: This function will block the new I/Os
6593* Its not aborting any I/Os as context
6594* is not destroyed during quiescence
6595* Arguments: scsi_qla_host_t
6596* return : void
6597*/
6598void
8fcd6b8b 6599qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 6600{
6601 struct qla_hw_data *ha = vha->hw;
6602 struct scsi_qla_host *vp;
6603
8fcd6b8b
CD		 6604 ql_dbg(ql_dbg_dpc, vha, 0x401d,
6605 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 6606
6607 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
6608 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6609 atomic_set(&vha->loop_state, LOOP_DOWN);
6610 qla2x00_mark_all_devices_lost(vha, 0);
6611 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 6612 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 6613 } else {
6614 if (!atomic_read(&vha->loop_down_timer))
6615 atomic_set(&vha->loop_down_timer,
6616 LOOP_DOWN_TIME);
6617 }
6618 /* Wait for pending cmds to complete */
fcef0893
BVA		 6619 WARN_ON_ONCE(qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST)
6620 != QLA_SUCCESS);
579d12b5
SK		 6621}
6622
a9083016
GM		 6623void
6624qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
6625{
6626 struct qla_hw_data *ha = vha->hw;
579d12b5 6627 struct scsi_qla_host *vp;
feafb7b1 6628 unsigned long flags;
6aef87be 6629 fc_port_t *fcport;
7c3f8fd1 6630 u16 i;
a9083016 6631
e46ef004
SK		 6632 /* For ISP82XX, driver waits for completion of the commands.
6633 * online flag should be set.
6634 */
7ec0effd 6635 if (!(IS_P3P_TYPE(ha)))
e46ef004 6636 vha->flags.online = 0;
a9083016
GM		 6637 ha->flags.chip_reset_done = 0;
6638 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 6639 vha->qla_stats.total_isp_aborts++;
a9083016 6640
7c3df132
SK		 6641 ql_log(ql_log_info, vha, 0x00af,
6642 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 6643
b2000805 6644 ha->flags.purge_mbox = 1;
e46ef004
SK		 6645 /* For ISP82XX, reset_chip is just disabling interrupts.
6646 * Driver waits for the completion of the commands.
6647 * the interrupts need to be enabled.
6648 */
7ec0effd 6649 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 6650 ha->isp_ops->reset_chip(vha);
6651
5d74c87a 6652 ha->link_data_rate = PORT_SPEED_UNKNOWN;
9cd883f0
QT		 6653 SAVE_TOPO(ha);
6654 ha->flags.rida_fmt2 = 0;
ec7193e2
QT		 6655 ha->flags.n2n_ae = 0;
6656 ha->flags.lip_ae = 0;
6657 ha->current_topology = 0;
6658 ha->flags.fw_started = 0;
6659 ha->flags.fw_init_done = 0;
b2000805
QT		 6660 ha->chip_reset++;
6661 ha->base_qpair->chip_reset = ha->chip_reset;
7c3f8fd1
QT		 6662 for (i = 0; i < ha->max_qpairs; i++) {
6663 if (ha->queue_pair_map[i])
6664 ha->queue_pair_map[i]->chip_reset =
6665 ha->base_qpair->chip_reset;
6666 }
726b8548 6667
b2000805
QT		 6668 /* purge MBox commands */
6669 if (atomic_read(&ha->num_pend_mbx_stage3)) {
6670 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
6671 complete(&ha->mbx_intr_comp);
6672 }
6673
6674 i = 0;
6675 while (atomic_read(&ha->num_pend_mbx_stage3) ||
6676 atomic_read(&ha->num_pend_mbx_stage2) ||
6677 atomic_read(&ha->num_pend_mbx_stage1)) {
6678 msleep(20);
6679 i++;
6680 if (i > 50)
6681 break;
6682 }
6683 ha->flags.purge_mbox = 0;
6684
a9083016
GM		 6685 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
6686 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6687 atomic_set(&vha->loop_state, LOOP_DOWN);
6688 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 6689
6690 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 6691 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 6692 atomic_inc(&vp->vref_count);
6693 spin_unlock_irqrestore(&ha->vport_slock, flags);
6694
a9083016 6695 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 6696
6697 spin_lock_irqsave(&ha->vport_slock, flags);
6698 atomic_dec(&vp->vref_count);
6699 }
6700 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 6701 } else {
6702 if (!atomic_read(&vha->loop_down_timer))
6703 atomic_set(&vha->loop_down_timer,
6704 LOOP_DOWN_TIME);
6705 }
6706
6aef87be 6707 /* Clear all async request states across all VPs. */
8b5292bc 6708 list_for_each_entry(fcport, &vha->vp_fcports, list) {
6aef87be 6709 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
8b5292bc
QT		 6710 fcport->scan_state = 0;
6711 }
6aef87be
AV		 6712 spin_lock_irqsave(&ha->vport_slock, flags);
6713 list_for_each_entry(vp, &ha->vp_list, list) {
6714 atomic_inc(&vp->vref_count);
6715 spin_unlock_irqrestore(&ha->vport_slock, flags);
6716
6717 list_for_each_entry(fcport, &vp->vp_fcports, list)
6718 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6719
6720 spin_lock_irqsave(&ha->vport_slock, flags);
6721 atomic_dec(&vp->vref_count);
6722 }
6723 spin_unlock_irqrestore(&ha->vport_slock, flags);
6724
bddd2d65
LC		 6725 if (!ha->flags.eeh_busy) {
6726 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 6727 if (IS_P3P_TYPE(ha)) {
7190575f 6728 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 6729 ql_log(ql_log_info, vha, 0x00b4,
6730 "Done chip reset cleanup.\n");
a9083016 6731
e46ef004
SK		 6732 /* Done waiting for pending commands.
6733 * Reset the online flag.
6734 */
6735 vha->flags.online = 0;
4d78c973 6736 }
a9083016 6737
bddd2d65
LC		 6738 /* Requeue all commands in outstanding command list. */
6739 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
6740 }
b6a029e1
AE		 6741 /* memory barrier */
6742 wmb();
a9083016
GM		 6743}
6744
1da177e4
LT		 6745/*
6746* qla2x00_abort_isp
6747* Resets ISP and aborts all outstanding commands.
6748*
6749* Input:
6750* ha = adapter block pointer.
6751*
6752* Returns:
6753* 0 = success
6754*/
6755int
e315cd28 6756qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 6757{
476e8978 6758 int rval;
1da177e4 6759 uint8_t status = 0;
e315cd28
AC		 6760 struct qla_hw_data *ha = vha->hw;
6761 struct scsi_qla_host *vp;
73208dfd 6762 struct req_que *req = ha->req_q_map[0];
feafb7b1 6763 unsigned long flags;
1da177e4 6764
e315cd28 6765 if (vha->flags.online) {
a9083016 6766 qla2x00_abort_isp_cleanup(vha);
1da177e4 6767
3f006ac3
MH		 6768 if (test_and_clear_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags)) {
6769 ha->flags.chip_reset_done = 1;
6770 vha->flags.online = 1;
6771 status = 0;
6772 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6773 return status;
6774 }
6775
a6171297
SV		 6776 if (IS_QLA8031(ha)) {
6777 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
6778 "Clearing fcoe driver presence.\n");
6779 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
6780 ql_dbg(ql_dbg_p3p, vha, 0xb073,
6781 "Error while clearing DRV-Presence.\n");
6782 }
6783
85880801
AV		 6784 if (unlikely(pci_channel_offline(ha->pdev) &&
6785 ha->flags.pci_channel_io_perm_failure)) {
6786 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6787 status = 0;
6788 return status;
6789 }
6790
0645cb83
QT		 6791 switch (vha->qlini_mode) {
6792 case QLA2XXX_INI_MODE_DISABLED:
6793 if (!qla_tgt_mode_enabled(vha))
6794 return 0;
6795 break;
6796 case QLA2XXX_INI_MODE_DUAL:
6797 if (!qla_dual_mode_enabled(vha))
6798 return 0;
6799 break;
6800 case QLA2XXX_INI_MODE_ENABLED:
6801 default:
6802 break;
6803 }
6804
73208dfd 6805 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 6806
e315cd28 6807 ha->isp_ops->nvram_config(vha);
1da177e4 6808
e315cd28
AC		 6809 if (!qla2x00_restart_isp(vha)) {
6810 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 6811
e315cd28 6812 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 6813 /*
6814 * Issue marker command only when we are going
6815 * to start the I/O .
6816 */
e315cd28 6817 vha->marker_needed = 1;
1da177e4
LT		 6818 }
6819
e315cd28 6820 vha->flags.online = 1;
1da177e4 6821
fd34f556 6822 ha->isp_ops->enable_intrs(ha);
1da177e4 6823
fa2a1ce5 6824 ha->isp_abort_cnt = 0;
e315cd28 6825 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 6826
6246b8a1
GM		 6827 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
6828 qla2x00_get_fw_version(vha);
df613b96
AV		 6829 if (ha->fce) {
6830 ha->flags.fce_enabled = 1;
6831 memset(ha->fce, 0,
6832 fce_calc_size(ha->fce_bufs));
e315cd28 6833 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 6834 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6835 &ha->fce_bufs);
6836 if (rval) {
7c3df132 6837 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 6838 "Unable to reinitialize FCE "
6839 "(%d).\n", rval);
6840 ha->flags.fce_enabled = 0;
6841 }
6842 }
436a7b11
AV		 6843
6844 if (ha->eft) {
6845 memset(ha->eft, 0, EFT_SIZE);
e315cd28 6846 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 6847 ha->eft_dma, EFT_NUM_BUFFERS);
6848 if (rval) {
7c3df132 6849 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 6850 "Unable to reinitialize EFT "
6851 "(%d).\n", rval);
6852 }
6853 }
1da177e4 6854 } else { /* failed the ISP abort */
e315cd28
AC		 6855 vha->flags.online = 1;
6856 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 6857 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 6858 ql_log(ql_log_fatal, vha, 0x8035,
6859 "ISP error recover failed - "
6860 "board disabled.\n");
fa2a1ce5 6861 /*
1da177e4
LT		 6862 * The next call disables the board
6863 * completely.
6864 */
1e4ac5d6 6865 qla2x00_abort_isp_cleanup(vha);
e315cd28 6866 vha->flags.online = 0;
1da177e4 6867 clear_bit(ISP_ABORT_RETRY,
e315cd28 6868 &vha->dpc_flags);
1da177e4
LT		 6869 status = 0;
6870 } else { /* schedule another ISP abort */
6871 ha->isp_abort_cnt--;
7c3df132
SK		 6872 ql_dbg(ql_dbg_taskm, vha, 0x8020,
6873 "ISP abort - retry remaining %d.\n",
6874 ha->isp_abort_cnt);
1da177e4
LT		 6875 status = 1;
6876 }
6877 } else {
6878 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 6879 ql_dbg(ql_dbg_taskm, vha, 0x8021,
6880 "ISP error recovery - retrying (%d) "
6881 "more times.\n", ha->isp_abort_cnt);
e315cd28 6882 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 6883 status = 1;
6884 }
6885 }
fa2a1ce5 6886
1da177e4
LT		 6887 }
6888
e315cd28 6889 if (!status) {
7c3df132 6890 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
1608cc4a 6891 qla2x00_configure_hba(vha);
feafb7b1
AE		 6892 spin_lock_irqsave(&ha->vport_slock, flags);
6893 list_for_each_entry(vp, &ha->vp_list, list) {
6894 if (vp->vp_idx) {
6895 atomic_inc(&vp->vref_count);
6896 spin_unlock_irqrestore(&ha->vport_slock, flags);
6897
e315cd28 6898 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6899
6900 spin_lock_irqsave(&ha->vport_slock, flags);
6901 atomic_dec(&vp->vref_count);
6902 }
e315cd28 6903 }
feafb7b1
AE		 6904 spin_unlock_irqrestore(&ha->vport_slock, flags);
6905
7d613ac6
SV		 6906 if (IS_QLA8031(ha)) {
6907 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
6908 "Setting back fcoe driver presence.\n");
6909 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
6910 ql_dbg(ql_dbg_p3p, vha, 0xb074,
6911 "Error while setting DRV-Presence.\n");
6912 }
e315cd28 6913 } else {
d8424f68
JP		 6914 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
6915 __func__);
1da177e4
LT		 6916 }
6917
6918 return(status);
6919}
6920
6921/*
6922* qla2x00_restart_isp
6923* restarts the ISP after a reset
6924*
6925* Input:
6926* ha = adapter block pointer.
6927*
6928* Returns:
6929* 0 = success
6930*/
6931static int
e315cd28 6932qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 6933{
c6b2fca8 6934 int status = 0;
e315cd28 6935 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 6936
6937 /* If firmware needs to be loaded */
e315cd28
AC		 6938 if (qla2x00_isp_firmware(vha)) {
6939 vha->flags.online = 0;
6940 status = ha->isp_ops->chip_diag(vha);
6941 if (!status)
6942 status = qla2x00_setup_chip(vha);
1da177e4
LT		 6943 }
6944
e315cd28
AC		 6945 if (!status && !(status = qla2x00_init_rings(vha))) {
6946 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 6947 ha->flags.chip_reset_done = 1;
7108b76e 6948
73208dfd
AC		 6949 /* Initialize the queues in use */
6950 qla25xx_init_queues(ha);
6951
e315cd28
AC		 6952 status = qla2x00_fw_ready(vha);
6953 if (!status) {
0107109e 6954 /* Issue a marker after FW becomes ready. */
9eb9c6dc 6955 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
7108b76e 6956 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6957 }
6958
6959 /* if no cable then assume it's good */
e315cd28 6960 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 6961 status = 0;
1da177e4
LT		 6962 }
6963 return (status);
6964}
6965
73208dfd
AC		 6966static int
6967qla25xx_init_queues(struct qla_hw_data *ha)
6968{
6969 struct rsp_que *rsp = NULL;
6970 struct req_que *req = NULL;
6971 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6972 int ret = -1;
6973 int i;
6974
2afa19a9 6975 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 6976 rsp = ha->rsp_q_map[i];
cb43285f 6977 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 6978 rsp->options &= ~BIT_0;
618a7523 6979 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 6980 if (ret != QLA_SUCCESS)
7c3df132
SK		 6981 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
6982 "%s Rsp que: %d init failed.\n",
6983 __func__, rsp->id);
73208dfd 6984 else
7c3df132
SK		 6985 ql_dbg(ql_dbg_init, base_vha, 0x0100,
6986 "%s Rsp que: %d inited.\n",
6987 __func__, rsp->id);
73208dfd 6988 }
2afa19a9
AC		 6989 }
6990 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 6991 req = ha->req_q_map[i];
cb43285f
QT		 6992 if (req && test_bit(i, ha->req_qid_map)) {
6993 /* Clear outstanding commands array. */
73208dfd 6994 req->options &= ~BIT_0;
618a7523 6995 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 6996 if (ret != QLA_SUCCESS)
7c3df132
SK		 6997 ql_dbg(ql_dbg_init, base_vha, 0x0101,
6998 "%s Req que: %d init failed.\n",
6999 __func__, req->id);
73208dfd 7000 else
7c3df132
SK		 7001 ql_dbg(ql_dbg_init, base_vha, 0x0102,
7002 "%s Req que: %d inited.\n",
7003 __func__, req->id);
73208dfd
AC		 7004 }
7005 }
7006 return ret;
7007}
7008
1da177e4
LT		 7009/*
7010* qla2x00_reset_adapter
7011* Reset adapter.
7012*
7013* Input:
7014* ha = adapter block pointer.
7015*/
3f006ac3 7016int
e315cd28 7017qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 7018{
7019 unsigned long flags = 0;
e315cd28 7020 struct qla_hw_data *ha = vha->hw;
3d71644c 7021 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 7022
e315cd28 7023 vha->flags.online = 0;
fd34f556 7024 ha->isp_ops->disable_intrs(ha);
1da177e4 7025
1da177e4
LT		 7026 spin_lock_irqsave(&ha->hardware_lock, flags);
7027 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
7028 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
7029 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
7030 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
7031 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3f006ac3
MH		 7032
7033 return QLA_SUCCESS;
1da177e4 7034}
0107109e 7035
3f006ac3 7036int
e315cd28 7037qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 7038{
7039 unsigned long flags = 0;
e315cd28 7040 struct qla_hw_data *ha = vha->hw;
0107109e 7041 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
3f006ac3 7042 int rval = QLA_SUCCESS;
0107109e 7043
7ec0effd 7044 if (IS_P3P_TYPE(ha))
3f006ac3 7045 return rval;
a9083016 7046
e315cd28 7047 vha->flags.online = 0;
fd34f556 7048 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 7049
7050 spin_lock_irqsave(&ha->hardware_lock, flags);
7051 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
7052 RD_REG_DWORD(&reg->hccr);
7053 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
7054 RD_REG_DWORD(&reg->hccr);
7055 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 7056
7057 if (IS_NOPOLLING_TYPE(ha))
7058 ha->isp_ops->enable_intrs(ha);
3f006ac3
MH		 7059
7060 return rval;
0107109e
AV		 7061}
7062
4e08df3f
DM		 7063/* On sparc systems, obtain port and node WWN from firmware
7064 * properties.
7065 */
e315cd28
AC		 7066static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
7067 struct nvram_24xx *nv)
4e08df3f
DM		 7068{
7069#ifdef CONFIG_SPARC
e315cd28 7070 struct qla_hw_data *ha = vha->hw;
4e08df3f 7071 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 7072 struct device_node *dp = pci_device_to_OF_node(pdev);
7073 const u8 *val;
4e08df3f
DM		 7074 int len;
7075
7076 val = of_get_property(dp, "port-wwn", &len);
7077 if (val && len >= WWN_SIZE)
7078 memcpy(nv->port_name, val, WWN_SIZE);
7079
7080 val = of_get_property(dp, "node-wwn", &len);
7081 if (val && len >= WWN_SIZE)
7082 memcpy(nv->node_name, val, WWN_SIZE);
7083#endif
7084}
7085
0107109e 7086int
e315cd28 7087qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 7088{
4e08df3f 7089 int rval;
0107109e
AV		 7090 struct init_cb_24xx *icb;
7091 struct nvram_24xx *nv;
7092 uint32_t *dptr;
7093 uint8_t *dptr1, *dptr2;
7094 uint32_t chksum;
7095 uint16_t cnt;
e315cd28 7096 struct qla_hw_data *ha = vha->hw;
0107109e 7097
4e08df3f 7098 rval = QLA_SUCCESS;
0107109e 7099 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 7100 nv = ha->nvram;
0107109e
AV		 7101
7102 /* Determine NVRAM starting address. */
f73cb695 7103 if (ha->port_no == 0) {
e5b68a61
AC		 7104 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
7105 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
7106 } else {
0107109e 7107 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 7108 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
7109 }
f73cb695 7110
f8f97b0c 7111 ha->nvram_size = sizeof(*nv);
e5b68a61 7112 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 7113
281afe19
SJ		 7114 /* Get VPD data into cache */
7115 ha->vpd = ha->nvram + VPD_OFFSET;
3695310e 7116 ha->isp_ops->read_nvram(vha, ha->vpd,
281afe19
SJ		 7117 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
7118
7119 /* Get NVRAM data into cache and calculate checksum. */
0107109e 7120 dptr = (uint32_t *)nv;
3695310e 7121 ha->isp_ops->read_nvram(vha, dptr, ha->nvram_base, ha->nvram_size);
da08ef5c
JC		 7122 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
7123 chksum += le32_to_cpu(*dptr);
0107109e 7124
7c3df132
SK		 7125 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
7126 "Contents of NVRAM\n");
7127 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
f8f97b0c 7128 nv, ha->nvram_size);
0107109e
AV		 7129
7130 /* Bad NVRAM data, set defaults parameters. */
a28d9e4e
JC		 7131 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
7132 le16_to_cpu(nv->nvram_version) < ICB_VERSION) {
0107109e 7133 /* Reset NVRAM data. */
7c3df132 7134 ql_log(ql_log_warn, vha, 0x006b,
3695310e
JC		 7135 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n",
7136 chksum, nv->id, nv->nvram_version);
7137 ql_dump_buffer(ql_dbg_init, vha, 0x006b, nv, sizeof(*nv));
7c3df132
SK		 7138 ql_log(ql_log_warn, vha, 0x006c,
7139 "Falling back to functioning (yet invalid -- WWPN) "
7140 "defaults.\n");
4e08df3f
DM		 7141
7142 /*
7143 * Set default initialization control block.
7144 */
7145 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 7146 nv->nvram_version = cpu_to_le16(ICB_VERSION);
7147 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 7148 nv->frame_payload_size = 2048;
ad950360
BVA		 7149 nv->execution_throttle = cpu_to_le16(0xFFFF);
7150 nv->exchange_count = cpu_to_le16(0);
7151 nv->hard_address = cpu_to_le16(124);
4e08df3f 7152 nv->port_name[0] = 0x21;
f73cb695 7153 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 7154 nv->port_name[2] = 0x00;
7155 nv->port_name[3] = 0xe0;
7156 nv->port_name[4] = 0x8b;
7157 nv->port_name[5] = 0x1c;
7158 nv->port_name[6] = 0x55;
7159 nv->port_name[7] = 0x86;
7160 nv->node_name[0] = 0x20;
7161 nv->node_name[1] = 0x00;
7162 nv->node_name[2] = 0x00;
7163 nv->node_name[3] = 0xe0;
7164 nv->node_name[4] = 0x8b;
7165 nv->node_name[5] = 0x1c;
7166 nv->node_name[6] = 0x55;
7167 nv->node_name[7] = 0x86;
e315cd28 7168 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 7169 nv->login_retry_count = cpu_to_le16(8);
7170 nv->interrupt_delay_timer = cpu_to_le16(0);
7171 nv->login_timeout = cpu_to_le16(0);
4e08df3f 7172 nv->firmware_options_1 =
ad950360
BVA		 7173 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7174 nv->firmware_options_2 = cpu_to_le32(2 << 4);
7175 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7176 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7177 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7178 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 7179 nv->reset_delay = 5;
ad950360
BVA		 7180 nv->max_luns_per_target = cpu_to_le16(128);
7181 nv->port_down_retry_count = cpu_to_le16(30);
7182 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 7183
7184 rval = 1;
0107109e
AV		 7185 }
7186
726b8548 7187 if (qla_tgt_mode_enabled(vha)) {
2d70c103 7188 /* Don't enable full login after initial LIP */
ad950360 7189 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 7190 /* Don't enable LIP full login for initiator */
ad950360 7191 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 7192 }
7193
7194 qlt_24xx_config_nvram_stage1(vha, nv);
7195
0107109e 7196 /* Reset Initialization control block */
e315cd28 7197 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 7198
7199 /* Copy 1st segment. */
7200 dptr1 = (uint8_t *)icb;
7201 dptr2 = (uint8_t *)&nv->version;
7202 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7203 while (cnt--)
7204 *dptr1++ = *dptr2++;
7205
7206 icb->login_retry_count = nv->login_retry_count;
3ea66e28 7207 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 7208
7209 /* Copy 2nd segment. */
7210 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7211 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7212 cnt = (uint8_t *)&icb->reserved_3 -
7213 (uint8_t *)&icb->interrupt_delay_timer;
7214 while (cnt--)
7215 *dptr1++ = *dptr2++;
0eaaca4c 7216 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
0107109e
AV		 7217 /*
7218 * Setup driver NVRAM options.
7219 */
e315cd28 7220 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 7221 "QLA2462");
0107109e 7222
2d70c103
NB		 7223 qlt_24xx_config_nvram_stage2(vha, icb);
7224
ad950360 7225 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 7226 /* Use alternate WWN? */
5341e868
AV		 7227 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7228 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7229 }
7230
0107109e 7231 /* Prepare nodename */
ad950360 7232 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 7233 /*
7234 * Firmware will apply the following mask if the nodename was
7235 * not provided.
7236 */
7237 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7238 icb->node_name[0] &= 0xF0;
7239 }
7240
7241 /* Set host adapter parameters. */
7242 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 7243 ha->flags.enable_lip_reset = 0;
7244 ha->flags.enable_lip_full_login =
58e2753c 7245 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0;
0c8c39af 7246 ha->flags.enable_target_reset =
58e2753c 7247 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0;
0107109e 7248 ha->flags.enable_led_scheme = 0;
58e2753c 7249 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0;
0107109e 7250
fd0e7e4d
AV		 7251 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7252 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 7253
7254 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
7255 sizeof(ha->fw_seriallink_options24));
7256
7257 /* save HBA serial number */
7258 ha->serial0 = icb->port_name[5];
7259 ha->serial1 = icb->port_name[6];
7260 ha->serial2 = icb->port_name[7];
e315cd28
AC		 7261 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7262 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 7263
ad950360 7264 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 7265
0107109e
AV		 7266 ha->retry_count = le16_to_cpu(nv->login_retry_count);
7267
7268 /* Set minimum login_timeout to 4 seconds. */
7269 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7270 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7271 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 7272 nv->login_timeout = cpu_to_le16(4);
0107109e 7273 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 7274
00a537b8
AV		 7275 /* Set minimum RATOV to 100 tenths of a second. */
7276 ha->r_a_tov = 100;
0107109e
AV		 7277
7278 ha->loop_reset_delay = nv->reset_delay;
7279
7280 /* Link Down Timeout = 0:
7281 *
7282 * When Port Down timer expires we will start returning
7283 * I/O's to OS with "DID_NO_CONNECT".
7284 *
7285 * Link Down Timeout != 0:
7286 *
7287 * The driver waits for the link to come up after link down
7288 * before returning I/Os to OS with "DID_NO_CONNECT".
7289 */
7290 if (le16_to_cpu(nv->link_down_timeout) == 0) {
7291 ha->loop_down_abort_time =
7292 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7293 } else {
7294 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7295 ha->loop_down_abort_time =
7296 (LOOP_DOWN_TIME - ha->link_down_timeout);
7297 }
7298
7299 /* Need enough time to try and get the port back. */
7300 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7301 if (qlport_down_retry)
7302 ha->port_down_retry_count = qlport_down_retry;
7303
7304 /* Set login_retry_count */
7305 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7306 if (ha->port_down_retry_count ==
7307 le16_to_cpu(nv->port_down_retry_count) &&
7308 ha->port_down_retry_count > 3)
7309 ha->login_retry_count = ha->port_down_retry_count;
7310 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7311 ha->login_retry_count = ha->port_down_retry_count;
7312 if (ql2xloginretrycount)
7313 ha->login_retry_count = ql2xloginretrycount;
7314
8777e431
QT		 7315 /* N2N: driver will initiate Login instead of FW */
7316 icb->firmware_options_3 |= BIT_8;
7317
4fdfefe5 7318 /* Enable ZIO. */
e315cd28 7319 if (!vha->flags.init_done) {
4fdfefe5
AV		 7320 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
7321 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
7322 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
58e2753c 7323 le16_to_cpu(icb->interrupt_delay_timer) : 2;
4fdfefe5 7324 }
ad950360 7325 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 7326 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
4fdfefe5 7327 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 7328 ha->zio_mode = QLA_ZIO_MODE_6;
7329
7c3df132 7330 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 7331 "ZIO mode %d enabled; timer delay (%d us).\n",
7332 ha->zio_mode, ha->zio_timer * 100);
7333
7334 icb->firmware_options_2 |= cpu_to_le32(
7335 (uint32_t)ha->zio_mode);
7336 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
4fdfefe5
AV		 7337 }
7338
4e08df3f 7339 if (rval) {
7c3df132
SK		 7340 ql_log(ql_log_warn, vha, 0x0070,
7341 "NVRAM configuration failed.\n");
4e08df3f
DM		 7342 }
7343 return (rval);
0107109e
AV		 7344}
7345
5fa8774c
JC		 7346static void
7347qla27xx_print_image(struct scsi_qla_host *vha, char *name,
7348 struct qla27xx_image_status *image_status)
7349{
7350 ql_dbg(ql_dbg_init, vha, 0x018b,
7351 "%s %s: mask=%#02x gen=%#04x ver=%u.%u map=%#01x sum=%#08x sig=%#08x\n",
7352 name, "status",
7353 image_status->image_status_mask,
7354 le16_to_cpu(image_status->generation),
7355 image_status->ver_major,
7356 image_status->ver_minor,
7357 image_status->bitmap,
7358 le32_to_cpu(image_status->checksum),
7359 le32_to_cpu(image_status->signature));
7360}
7361
7362static bool
7363qla28xx_check_aux_image_status_signature(
7364 struct qla27xx_image_status *image_status)
7365{
7366 ulong signature = le32_to_cpu(image_status->signature);
7367
7368 return signature != QLA28XX_AUX_IMG_STATUS_SIGN;
7369}
7370
7371static bool
7372qla27xx_check_image_status_signature(struct qla27xx_image_status *image_status)
7373{
7374 ulong signature = le32_to_cpu(image_status->signature);
7375
7376 return
7377 signature != QLA27XX_IMG_STATUS_SIGN &&
7378 signature != QLA28XX_IMG_STATUS_SIGN;
7379}
7380
7381static ulong
7382qla27xx_image_status_checksum(struct qla27xx_image_status *image_status)
7383{
7384 uint32_t *p = (void *)image_status;
7385 uint n = sizeof(*image_status) / sizeof(*p);
7386 uint32_t sum = 0;
7387
7388 for ( ; n--; p++)
7389 sum += le32_to_cpup(p);
7390
7391 return sum;
7392}
7393
7394static inline uint
7395qla28xx_component_bitmask(struct qla27xx_image_status *aux, uint bitmask)
7396{
7397 return aux->bitmap & bitmask ?
7398 QLA27XX_SECONDARY_IMAGE : QLA27XX_PRIMARY_IMAGE;
7399}
7400
7401static void
7402qla28xx_component_status(
7403 struct active_regions *active_regions, struct qla27xx_image_status *aux)
7404{
7405 active_regions->aux.board_config =
7406 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_BOARD_CONFIG);
7407
7408 active_regions->aux.vpd_nvram =
7409 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_VPD_NVRAM);
7410
7411 active_regions->aux.npiv_config_0_1 =
7412 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_0_1);
7413
7414 active_regions->aux.npiv_config_2_3 =
7415 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_2_3);
7416}
7417
7418static int
7419qla27xx_compare_image_generation(
7420 struct qla27xx_image_status *pri_image_status,
7421 struct qla27xx_image_status *sec_image_status)
7422{
7423 /* calculate generation delta as uint16 (this accounts for wrap) */
7424 int16_t delta =
7425 le16_to_cpu(pri_image_status->generation) -
7426 le16_to_cpu(sec_image_status->generation);
7427
7428 ql_dbg(ql_dbg_init, NULL, 0x0180, "generation delta = %d\n", delta);
7429
7430 return delta;
7431}
7432
7433void
7434qla28xx_get_aux_images(
7435 struct scsi_qla_host *vha, struct active_regions *active_regions)
4243c115 7436{
4243c115 7437 struct qla_hw_data *ha = vha->hw;
5fa8774c
JC		 7438 struct qla27xx_image_status pri_aux_image_status, sec_aux_image_status;
7439 bool valid_pri_image = false, valid_sec_image = false;
7440 bool active_pri_image = false, active_sec_image = false;
7441
7442 if (!ha->flt_region_aux_img_status_pri) {
7443 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary aux image not addressed\n");
7444 goto check_sec_image;
7445 }
7446
7447 qla24xx_read_flash_data(vha, (void *)&pri_aux_image_status,
7448 ha->flt_region_aux_img_status_pri,
7449 sizeof(pri_aux_image_status) >> 2);
7450 qla27xx_print_image(vha, "Primary aux image", &pri_aux_image_status);
7451
7452 if (qla28xx_check_aux_image_status_signature(&pri_aux_image_status)) {
7453 ql_dbg(ql_dbg_init, vha, 0x018b,
7454 "Primary aux image signature (%#x) not valid\n",
7455 le32_to_cpu(pri_aux_image_status.signature));
7456 goto check_sec_image;
7457 }
7458
7459 if (qla27xx_image_status_checksum(&pri_aux_image_status)) {
7460 ql_dbg(ql_dbg_init, vha, 0x018c,
7461 "Primary aux image checksum failed\n");
7462 goto check_sec_image;
7463 }
7464
7465 valid_pri_image = true;
7466
7467 if (pri_aux_image_status.image_status_mask & 1) {
7468 ql_dbg(ql_dbg_init, vha, 0x018d,
7469 "Primary aux image is active\n");
7470 active_pri_image = true;
7471 }
7472
7473check_sec_image:
7474 if (!ha->flt_region_aux_img_status_sec) {
7475 ql_dbg(ql_dbg_init, vha, 0x018a,
7476 "Secondary aux image not addressed\n");
7477 goto check_valid_image;
7478 }
7479
7480 qla24xx_read_flash_data(vha, (void *)&sec_aux_image_status,
7481 ha->flt_region_aux_img_status_sec,
7482 sizeof(sec_aux_image_status) >> 2);
7483 qla27xx_print_image(vha, "Secondary aux image", &sec_aux_image_status);
7484
7485 if (qla28xx_check_aux_image_status_signature(&sec_aux_image_status)) {
7486 ql_dbg(ql_dbg_init, vha, 0x018b,
7487 "Secondary aux image signature (%#x) not valid\n",
7488 le32_to_cpu(sec_aux_image_status.signature));
7489 goto check_valid_image;
7490 }
7491
7492 if (qla27xx_image_status_checksum(&sec_aux_image_status)) {
7493 ql_dbg(ql_dbg_init, vha, 0x018c,
7494 "Secondary aux image checksum failed\n");
7495 goto check_valid_image;
7496 }
4243c115 7497
5fa8774c
JC		 7498 valid_sec_image = true;
7499
7500 if (sec_aux_image_status.image_status_mask & 1) {
7501 ql_dbg(ql_dbg_init, vha, 0x018d,
7502 "Secondary aux image is active\n");
7503 active_sec_image = true;
7504 }
7505
7506check_valid_image:
7507 if (valid_pri_image && active_pri_image &&
7508 valid_sec_image && active_sec_image) {
7509 if (qla27xx_compare_image_generation(&pri_aux_image_status,
7510 &sec_aux_image_status) >= 0) {
7511 qla28xx_component_status(active_regions,
7512 &pri_aux_image_status);
7513 } else {
7514 qla28xx_component_status(active_regions,
7515 &sec_aux_image_status);
7516 }
7517 } else if (valid_pri_image && active_pri_image) {
7518 qla28xx_component_status(active_regions, &pri_aux_image_status);
7519 } else if (valid_sec_image && active_sec_image) {
7520 qla28xx_component_status(active_regions, &sec_aux_image_status);
7521 }
7522
7523 ql_dbg(ql_dbg_init, vha, 0x018f,
7524 "aux images active: BCFG=%u VPD/NVR=%u NPIV0/1=%u NPIV2/3=%u\n",
7525 active_regions->aux.board_config,
7526 active_regions->aux.vpd_nvram,
7527 active_regions->aux.npiv_config_0_1,
7528 active_regions->aux.npiv_config_2_3);
7529}
7530
7531void
7532qla27xx_get_active_image(struct scsi_qla_host *vha,
7533 struct active_regions *active_regions)
7534{
7535 struct qla_hw_data *ha = vha->hw;
7536 struct qla27xx_image_status pri_image_status, sec_image_status;
7537 bool valid_pri_image = false, valid_sec_image = false;
7538 bool active_pri_image = false, active_sec_image = false;
4243c115
SC		 7539
7540 if (!ha->flt_region_img_status_pri) {
5fa8774c 7541 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary image not addressed\n");
4243c115
SC		 7542 goto check_sec_image;
7543 }
7544
0597fe60
BVA		 7545 if (qla24xx_read_flash_data(vha, (void *)(&pri_image_status),
7546 ha->flt_region_img_status_pri, sizeof(pri_image_status) >> 2) !=
7547 QLA_SUCCESS) {
7548 WARN_ON_ONCE(true);
7549 goto check_sec_image;
7550 }
5fa8774c 7551 qla27xx_print_image(vha, "Primary image", &pri_image_status);
4243c115 7552
5fa8774c 7553 if (qla27xx_check_image_status_signature(&pri_image_status)) {
4243c115 7554 ql_dbg(ql_dbg_init, vha, 0x018b,
f8f97b0c
JC		 7555 "Primary image signature (%#x) not valid\n",
7556 le32_to_cpu(pri_image_status.signature));
4243c115
SC		 7557 goto check_sec_image;
7558 }
7559
5fa8774c
JC		 7560 if (qla27xx_image_status_checksum(&pri_image_status)) {
7561 ql_dbg(ql_dbg_init, vha, 0x018c,
7562 "Primary image checksum failed\n");
7563 goto check_sec_image;
7564 }
4243c115 7565
5fa8774c 7566 valid_pri_image = true;
41dc529a 7567
5fa8774c
JC		 7568 if (pri_image_status.image_status_mask & 1) {
7569 ql_dbg(ql_dbg_init, vha, 0x018d,
7570 "Primary image is active\n");
7571 active_pri_image = true;
4243c115
SC		 7572 }
7573
7574check_sec_image:
7575 if (!ha->flt_region_img_status_sec) {
5fa8774c 7576 ql_dbg(ql_dbg_init, vha, 0x018a, "Secondary image not addressed\n");
4243c115
SC		 7577 goto check_valid_image;
7578 }
7579
7580 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
5fa8774c
JC		 7581 ha->flt_region_img_status_sec, sizeof(sec_image_status) >> 2);
7582 qla27xx_print_image(vha, "Secondary image", &sec_image_status);
4243c115 7583
5fa8774c
JC		 7584 if (qla27xx_check_image_status_signature(&sec_image_status)) {
7585 ql_dbg(ql_dbg_init, vha, 0x018b,
f8f97b0c
JC		 7586 "Secondary image signature (%#x) not valid\n",
7587 le32_to_cpu(sec_image_status.signature));
4243c115
SC		 7588 goto check_valid_image;
7589 }
7590
5fa8774c
JC		 7591 if (qla27xx_image_status_checksum(&sec_image_status)) {
7592 ql_dbg(ql_dbg_init, vha, 0x018c,
7593 "Secondary image checksum failed\n");
7594 goto check_valid_image;
7595 }
7596
7597 valid_sec_image = true;
7598
7599 if (sec_image_status.image_status_mask & 1) {
7600 ql_dbg(ql_dbg_init, vha, 0x018d,
7601 "Secondary image is active\n");
7602 active_sec_image = true;
4243c115
SC		 7603 }
7604
7605check_valid_image:
5fa8774c
JC		 7606 if (valid_pri_image && active_pri_image)
7607 active_regions->global = QLA27XX_PRIMARY_IMAGE;
7608
7609 if (valid_sec_image && active_sec_image) {
7610 if (!active_regions->global ||
7611 qla27xx_compare_image_generation(
7612 &pri_image_status, &sec_image_status) < 0) {
7613 active_regions->global = QLA27XX_SECONDARY_IMAGE;
f8f97b0c 7614 }
4243c115
SC		 7615 }
7616
5fa8774c
JC		 7617 ql_dbg(ql_dbg_init, vha, 0x018f, "active image %s (%u)\n",
7618 active_regions->global == QLA27XX_DEFAULT_IMAGE ?
7619 "default (boot/fw)" :
7620 active_regions->global == QLA27XX_PRIMARY_IMAGE ?
7621 "primary" :
7622 active_regions->global == QLA27XX_SECONDARY_IMAGE ?
7623 "secondary" : "invalid",
7624 active_regions->global);
4243c115
SC		 7625}
7626
f8f97b0c
JC		 7627bool qla24xx_risc_firmware_invalid(uint32_t *dword)
7628{
7629 return
7630 !(dword[4] | dword[5] | dword[6] | dword[7]) ||
7631 !(~dword[4] | ~dword[5] | ~dword[6] | ~dword[7]);
7632}
7633
413975a0 7634static int
cbc8eb67
AV		 7635qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
7636 uint32_t faddr)
d1c61909 7637{
a28d9e4e
JC		 7638 int rval;
7639 uint templates, segments, fragment;
7640 ulong i;
7641 uint j;
7642 ulong dlen;
7643 uint32_t *dcode;
7644 uint32_t risc_addr, risc_size, risc_attr = 0;
e315cd28 7645 struct qla_hw_data *ha = vha->hw;
73208dfd 7646 struct req_que *req = ha->req_q_map[0];
a28d9e4e 7647 struct fwdt *fwdt = ha->fwdt;
eaac30be 7648
7c3df132 7649 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 7650 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 7651
f8f97b0c
JC		 7652 dcode = (void *)req->ring;
7653 qla24xx_read_flash_data(vha, dcode, faddr, 8);
7654 if (qla24xx_risc_firmware_invalid(dcode)) {
7c3df132
SK		 7655 ql_log(ql_log_fatal, vha, 0x008c,
7656 "Unable to verify the integrity of flash firmware "
7657 "image.\n");
7658 ql_log(ql_log_fatal, vha, 0x008d,
7659 "Firmware data: %08x %08x %08x %08x.\n",
7660 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 7661
7662 return QLA_FUNCTION_FAILED;
7663 }
7664
a28d9e4e
JC		 7665 dcode = (void *)req->ring;
7666 *srisc_addr = 0;
7667 segments = FA_RISC_CODE_SEGMENTS;
7668 for (j = 0; j < segments; j++) {
7669 ql_dbg(ql_dbg_init, vha, 0x008d,
7670 "-> Loading segment %u...\n", j);
7671 qla24xx_read_flash_data(vha, dcode, faddr, 10);
d1c61909 7672 risc_addr = be32_to_cpu(dcode[2]);
d1c61909 7673 risc_size = be32_to_cpu(dcode[3]);
a28d9e4e
JC		 7674 if (!*srisc_addr) {
7675 *srisc_addr = risc_addr;
7676 risc_attr = be32_to_cpu(dcode[9]);
7677 }
d1c61909 7678
a28d9e4e
JC		 7679 dlen = ha->fw_transfer_size >> 2;
7680 for (fragment = 0; risc_size; fragment++) {
d1c61909
AV		 7681 if (dlen > risc_size)
7682 dlen = risc_size;
7683
7c3df132 7684 ql_dbg(ql_dbg_init, vha, 0x008e,
a28d9e4e
JC		 7685 "-> Loading fragment %u: %#x <- %#x (%#lx dwords)...\n",
7686 fragment, risc_addr, faddr, dlen);
e315cd28 7687 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 7688 for (i = 0; i < dlen; i++)
7689 dcode[i] = swab32(dcode[i]);
7690
a28d9e4e 7691 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen);
d1c61909 7692 if (rval) {
7c3df132 7693 ql_log(ql_log_fatal, vha, 0x008f,
a28d9e4e 7694 "-> Failed load firmware fragment %u.\n",
7c3df132 7695 fragment);
f261f7af 7696 return QLA_FUNCTION_FAILED;
d1c61909
AV		 7697 }
7698
7699 faddr += dlen;
7700 risc_addr += dlen;
7701 risc_size -= dlen;
d1c61909 7702 }
d1c61909
AV		 7703 }
7704
ecc89f25 7705 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
a28d9e4e 7706 return QLA_SUCCESS;
f73cb695 7707
a28d9e4e
JC		 7708 templates = (risc_attr & BIT_9) ? 2 : 1;
7709 ql_dbg(ql_dbg_init, vha, 0x0160, "-> templates = %u\n", templates);
7710 for (j = 0; j < templates; j++, fwdt++) {
7711 if (fwdt->template)
7712 vfree(fwdt->template);
7713 fwdt->template = NULL;
7714 fwdt->length = 0;
7715
3695310e 7716 dcode = (void *)req->ring;
a28d9e4e
JC		 7717 qla24xx_read_flash_data(vha, dcode, faddr, 7);
7718 risc_size = be32_to_cpu(dcode[2]);
7719 ql_dbg(ql_dbg_init, vha, 0x0161,
7720 "-> fwdt%u template array at %#x (%#x dwords)\n",
7721 j, faddr, risc_size);
7722 if (!risc_size || !~risc_size) {
7723 ql_dbg(ql_dbg_init, vha, 0x0162,
7724 "-> fwdt%u failed to read array\n", j);
7725 goto failed;
7726 }
f73cb695 7727
a28d9e4e
JC		 7728 /* skip header and ignore checksum */
7729 faddr += 7;
7730 risc_size -= 8;
7731
7732 ql_dbg(ql_dbg_init, vha, 0x0163,
7733 "-> fwdt%u template allocate template %#x words...\n",
7734 j, risc_size);
7735 fwdt->template = vmalloc(risc_size * sizeof(*dcode));
7736 if (!fwdt->template) {
7737 ql_log(ql_log_warn, vha, 0x0164,
7738 "-> fwdt%u failed allocate template.\n", j);
7739 goto failed;
7740 }
f73cb695 7741
a28d9e4e
JC		 7742 dcode = fwdt->template;
7743 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
f73cb695 7744
a28d9e4e
JC		 7745 if (!qla27xx_fwdt_template_valid(dcode)) {
7746 ql_log(ql_log_warn, vha, 0x0165,
7747 "-> fwdt%u failed template validate\n", j);
7748 goto failed;
7749 }
f73cb695 7750
a28d9e4e
JC		 7751 dlen = qla27xx_fwdt_template_size(dcode);
7752 ql_dbg(ql_dbg_init, vha, 0x0166,
7753 "-> fwdt%u template size %#lx bytes (%#lx words)\n",
7754 j, dlen, dlen / sizeof(*dcode));
7755 if (dlen > risc_size * sizeof(*dcode)) {
7756 ql_log(ql_log_warn, vha, 0x0167,
7757 "-> fwdt%u template exceeds array (%-lu bytes)\n",
7758 j, dlen - risc_size * sizeof(*dcode));
7759 goto failed;
7760 }
7761
7762 fwdt->length = dlen;
7763 ql_dbg(ql_dbg_init, vha, 0x0168,
7764 "-> fwdt%u loaded template ok\n", j);
7765
7766 faddr += risc_size + 1;
f73cb695 7767 }
a28d9e4e
JC		 7768
7769 return QLA_SUCCESS;
f73cb695 7770
2ff6ae85 7771failed:
a28d9e4e
JC		 7772 if (fwdt->template)
7773 vfree(fwdt->template);
7774 fwdt->template = NULL;
7775 fwdt->length = 0;
7776
7777 return QLA_SUCCESS;
d1c61909
AV		 7778}
7779
e9454a88 7780#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 7781
0107109e 7782int
e315cd28 7783qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 7784{
7785 int rval;
7786 int i, fragment;
7787 uint16_t *wcode, *fwcode;
7788 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
7789 struct fw_blob *blob;
e315cd28 7790 struct qla_hw_data *ha = vha->hw;
73208dfd 7791 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 7792
7793 /* Load firmware blob. */
e315cd28 7794 blob = qla2x00_request_firmware(vha);
5433383e 7795 if (!blob) {
7c3df132 7796 ql_log(ql_log_info, vha, 0x0083,
94bcf830 7797 "Firmware image unavailable.\n");
7c3df132
SK		 7798 ql_log(ql_log_info, vha, 0x0084,
7799 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 7800 return QLA_FUNCTION_FAILED;
7801 }
7802
7803 rval = QLA_SUCCESS;
7804
73208dfd 7805 wcode = (uint16_t *)req->ring;
5433383e
AV		 7806 *srisc_addr = 0;
7807 fwcode = (uint16_t *)blob->fw->data;
7808 fwclen = 0;
7809
7810 /* Validate firmware image by checking version. */
7811 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132 7812 ql_log(ql_log_fatal, vha, 0x0085,
5b5e0928 7813 "Unable to verify integrity of firmware image (%zd).\n",
5433383e
AV		 7814 blob->fw->size);
7815 goto fail_fw_integrity;
7816 }
7817 for (i = 0; i < 4; i++)
7818 wcode[i] = be16_to_cpu(fwcode[i + 4]);
7819 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
7820 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
7821 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 7822 ql_log(ql_log_fatal, vha, 0x0086,
7823 "Unable to verify integrity of firmware image.\n");
7824 ql_log(ql_log_fatal, vha, 0x0087,
7825 "Firmware data: %04x %04x %04x %04x.\n",
7826 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 7827 goto fail_fw_integrity;
7828 }
7829
7830 seg = blob->segs;
7831 while (*seg && rval == QLA_SUCCESS) {
7832 risc_addr = *seg;
7833 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
7834 risc_size = be16_to_cpu(fwcode[3]);
7835
7836 /* Validate firmware image size. */
7837 fwclen += risc_size * sizeof(uint16_t);
7838 if (blob->fw->size < fwclen) {
7c3df132 7839 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 7840 "Unable to verify integrity of firmware image "
5b5e0928 7841 "(%zd).\n", blob->fw->size);
5433383e
AV		 7842 goto fail_fw_integrity;
7843 }
7844
7845 fragment = 0;
7846 while (risc_size > 0 && rval == QLA_SUCCESS) {
7847 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
7848 if (wlen > risc_size)
7849 wlen = risc_size;
7c3df132
SK		 7850 ql_dbg(ql_dbg_init, vha, 0x0089,
7851 "Loading risc segment@ risc addr %x number of "
7852 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 7853
7854 for (i = 0; i < wlen; i++)
7855 wcode[i] = swab16(fwcode[i]);
7856
73208dfd 7857 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 7858 wlen);
7859 if (rval) {
7c3df132
SK		 7860 ql_log(ql_log_fatal, vha, 0x008a,
7861 "Failed to load segment %d of firmware.\n",
7862 fragment);
5433383e
AV		 7863 break;
7864 }
7865
7866 fwcode += wlen;
7867 risc_addr += wlen;
7868 risc_size -= wlen;
7869 fragment++;
7870 }
7871
7872 /* Next segment. */
7873 seg++;
7874 }
7875 return rval;
7876
7877fail_fw_integrity:
7878 return QLA_FUNCTION_FAILED;
7879}
7880
eaac30be
AV		 7881static int
7882qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 7883{
7884 int rval;
a28d9e4e
JC		 7885 uint templates, segments, fragment;
7886 uint32_t *dcode;
7887 ulong dlen;
7888 uint32_t risc_addr, risc_size, risc_attr = 0;
7889 ulong i;
7890 uint j;
5433383e 7891 struct fw_blob *blob;
f8f97b0c 7892 uint32_t *fwcode;
e315cd28 7893 struct qla_hw_data *ha = vha->hw;
73208dfd 7894 struct req_que *req = ha->req_q_map[0];
a28d9e4e
JC		 7895 struct fwdt *fwdt = ha->fwdt;
7896
7897 ql_dbg(ql_dbg_init, vha, 0x0090,
7898 "-> FW: Loading via request-firmware.\n");
0107109e 7899
e315cd28 7900 blob = qla2x00_request_firmware(vha);
5433383e 7901 if (!blob) {
a28d9e4e
JC		 7902 ql_log(ql_log_warn, vha, 0x0092,
7903 "-> Firmware file not found.\n");
d1c61909 7904
eaac30be 7905 return QLA_FUNCTION_FAILED;
0107109e
AV		 7906 }
7907
f8f97b0c 7908 fwcode = (void *)blob->fw->data;
1710ac17 7909 dcode = fwcode;
f8f97b0c 7910 if (qla24xx_risc_firmware_invalid(dcode)) {
7c3df132 7911 ql_log(ql_log_fatal, vha, 0x0093,
5b5e0928 7912 "Unable to verify integrity of firmware image (%zd).\n",
5433383e 7913 blob->fw->size);
7c3df132
SK		 7914 ql_log(ql_log_fatal, vha, 0x0095,
7915 "Firmware data: %08x %08x %08x %08x.\n",
7916 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 7917 return QLA_FUNCTION_FAILED;
0107109e
AV		 7918 }
7919
a28d9e4e
JC		 7920 dcode = (void *)req->ring;
7921 *srisc_addr = 0;
7922 segments = FA_RISC_CODE_SEGMENTS;
7923 for (j = 0; j < segments; j++) {
7924 ql_dbg(ql_dbg_init, vha, 0x0096,
7925 "-> Loading segment %u...\n", j);
0107109e 7926 risc_addr = be32_to_cpu(fwcode[2]);
0107109e
AV		 7927 risc_size = be32_to_cpu(fwcode[3]);
7928
a28d9e4e
JC		 7929 if (!*srisc_addr) {
7930 *srisc_addr = risc_addr;
7931 risc_attr = be32_to_cpu(fwcode[9]);
0107109e
AV		 7932 }
7933
a28d9e4e
JC		 7934 dlen = ha->fw_transfer_size >> 2;
7935 for (fragment = 0; risc_size; fragment++) {
0107109e
AV		 7936 if (dlen > risc_size)
7937 dlen = risc_size;
7938
7c3df132 7939 ql_dbg(ql_dbg_init, vha, 0x0097,
a28d9e4e
JC		 7940 "-> Loading fragment %u: %#x <- %#x (%#lx words)...\n",
7941 fragment, risc_addr,
7942 (uint32_t)(fwcode - (typeof(fwcode))blob->fw->data),
7943 dlen);
0107109e
AV		 7944
7945 for (i = 0; i < dlen; i++)
7946 dcode[i] = swab32(fwcode[i]);
7947
a28d9e4e 7948 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen);
0107109e 7949 if (rval) {
7c3df132 7950 ql_log(ql_log_fatal, vha, 0x0098,
a28d9e4e 7951 "-> Failed load firmware fragment %u.\n",
7c3df132 7952 fragment);
f261f7af 7953 return QLA_FUNCTION_FAILED;
0107109e
AV		 7954 }
7955
7956 fwcode += dlen;
7957 risc_addr += dlen;
7958 risc_size -= dlen;
0107109e 7959 }
0107109e 7960 }
f73cb695 7961
ecc89f25 7962 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
a28d9e4e 7963 return QLA_SUCCESS;
f73cb695 7964
a28d9e4e
JC		 7965 templates = (risc_attr & BIT_9) ? 2 : 1;
7966 ql_dbg(ql_dbg_init, vha, 0x0170, "-> templates = %u\n", templates);
7967 for (j = 0; j < templates; j++, fwdt++) {
7968 if (fwdt->template)
7969 vfree(fwdt->template);
7970 fwdt->template = NULL;
7971 fwdt->length = 0;
7972
7973 risc_size = be32_to_cpu(fwcode[2]);
7974 ql_dbg(ql_dbg_init, vha, 0x0171,
7975 "-> fwdt%u template array at %#x (%#x dwords)\n",
7976 j, (uint32_t)((void *)fwcode - (void *)blob->fw->data),
7977 risc_size);
7978 if (!risc_size || !~risc_size) {
7979 ql_dbg(ql_dbg_init, vha, 0x0172,
7980 "-> fwdt%u failed to read array\n", j);
7981 goto failed;
7982 }
f73cb695 7983
a28d9e4e
JC		 7984 /* skip header and ignore checksum */
7985 fwcode += 7;
7986 risc_size -= 8;
7987
7988 ql_dbg(ql_dbg_init, vha, 0x0173,
7989 "-> fwdt%u template allocate template %#x words...\n",
7990 j, risc_size);
7991 fwdt->template = vmalloc(risc_size * sizeof(*dcode));
7992 if (!fwdt->template) {
7993 ql_log(ql_log_warn, vha, 0x0174,
7994 "-> fwdt%u failed allocate template.\n", j);
7995 goto failed;
7996 }
f73cb695 7997
a28d9e4e
JC		 7998 dcode = fwdt->template;
7999 for (i = 0; i < risc_size; i++)
5fa8774c 8000 dcode[i] = fwcode[i];
f73cb695 8001
a28d9e4e
JC		 8002 if (!qla27xx_fwdt_template_valid(dcode)) {
8003 ql_log(ql_log_warn, vha, 0x0175,
8004 "-> fwdt%u failed template validate\n", j);
8005 goto failed;
8006 }
f73cb695 8007
a28d9e4e
JC		 8008 dlen = qla27xx_fwdt_template_size(dcode);
8009 ql_dbg(ql_dbg_init, vha, 0x0176,
8010 "-> fwdt%u template size %#lx bytes (%#lx words)\n",
8011 j, dlen, dlen / sizeof(*dcode));
8012 if (dlen > risc_size * sizeof(*dcode)) {
8013 ql_log(ql_log_warn, vha, 0x0177,
8014 "-> fwdt%u template exceeds array (%-lu bytes)\n",
8015 j, dlen - risc_size * sizeof(*dcode));
8016 goto failed;
8017 }
8018
8019 fwdt->length = dlen;
8020 ql_dbg(ql_dbg_init, vha, 0x0178,
8021 "-> fwdt%u loaded template ok\n", j);
8022
8023 fwcode += risc_size + 1;
f73cb695 8024 }
a28d9e4e
JC		 8025
8026 return QLA_SUCCESS;
f73cb695 8027
2ff6ae85 8028failed:
a28d9e4e
JC		 8029 if (fwdt->template)
8030 vfree(fwdt->template);
8031 fwdt->template = NULL;
8032 fwdt->length = 0;
8033
8034 return QLA_SUCCESS;
0107109e 8035}
18c6c127 8036
eaac30be
AV		 8037int
8038qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
8039{
8040 int rval;
8041
e337d907
AV		 8042 if (ql2xfwloadbin == 1)
8043 return qla81xx_load_risc(vha, srisc_addr);
8044
eaac30be
AV		 8045 /*
8046 * FW Load priority:
8047 * 1) Firmware via request-firmware interface (.bin file).
8048 * 2) Firmware residing in flash.
8049 */
8050 rval = qla24xx_load_risc_blob(vha, srisc_addr);
8051 if (rval == QLA_SUCCESS)
8052 return rval;
8053
cbc8eb67
AV		 8054 return qla24xx_load_risc_flash(vha, srisc_addr,
8055 vha->hw->flt_region_fw);
eaac30be
AV		 8056}
8057
8058int
8059qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
8060{
8061 int rval;
cbc8eb67 8062 struct qla_hw_data *ha = vha->hw;
5fa8774c 8063 struct active_regions active_regions = { };
eaac30be 8064
e337d907 8065 if (ql2xfwloadbin == 2)
cbc8eb67 8066 goto try_blob_fw;
e337d907 8067
f8f97b0c 8068 /* FW Load priority:
eaac30be
AV		 8069 * 1) Firmware residing in flash.
8070 * 2) Firmware via request-firmware interface (.bin file).
f8f97b0c 8071 * 3) Golden-Firmware residing in flash -- (limited operation).
eaac30be 8072 */
f8f97b0c 8073
5fa8774c 8074 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
f8f97b0c
JC		 8075 goto try_primary_fw;
8076
5fa8774c
JC		 8077 qla27xx_get_active_image(vha, &active_regions);
8078
8079 if (active_regions.global != QLA27XX_SECONDARY_IMAGE)
f8f97b0c
JC		 8080 goto try_primary_fw;
8081
8082 ql_dbg(ql_dbg_init, vha, 0x008b,
8083 "Loading secondary firmware image.\n");
8084 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw_sec);
8085 if (!rval)
8086 return rval;
8087
8088try_primary_fw:
8089 ql_dbg(ql_dbg_init, vha, 0x008b,
8090 "Loading primary firmware image.\n");
cbc8eb67 8091 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
f8f97b0c 8092 if (!rval)
eaac30be
AV		 8093 return rval;
8094
cbc8eb67
AV		 8095try_blob_fw:
8096 rval = qla24xx_load_risc_blob(vha, srisc_addr);
f8f97b0c 8097 if (!rval || !ha->flt_region_gold_fw)
cbc8eb67
AV		 8098 return rval;
8099
7c3df132
SK		 8100 ql_log(ql_log_info, vha, 0x0099,
8101 "Attempting to fallback to golden firmware.\n");
cbc8eb67 8102 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
f8f97b0c 8103 if (rval)
cbc8eb67
AV		 8104 return rval;
8105
f8f97b0c 8106 ql_log(ql_log_info, vha, 0x009a, "Need firmware flash update.\n");
cbc8eb67 8107 ha->flags.running_gold_fw = 1;
cbc8eb67 8108 return rval;
eaac30be
AV		 8109}
8110
18c6c127 8111void
e315cd28 8112qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 8113{
8114 int ret, retries;
e315cd28 8115 struct qla_hw_data *ha = vha->hw;
18c6c127 8116
85880801
AV		 8117 if (ha->flags.pci_channel_io_perm_failure)
8118 return;
e428924c 8119 if (!IS_FWI2_CAPABLE(ha))
18c6c127 8120 return;
75edf81d
AV		 8121 if (!ha->fw_major_version)
8122 return;
ec7193e2
QT		 8123 if (!ha->flags.fw_started)
8124 return;
18c6c127 8125
e315cd28 8126 ret = qla2x00_stop_firmware(vha);
7c7f1f29 8127 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 8128 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 8129 ha->isp_ops->reset_chip(vha);
8130 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 8131 continue;
e315cd28 8132 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 8133 continue;
7c3df132
SK		 8134 ql_log(ql_log_info, vha, 0x8015,
8135 "Attempting retry of stop-firmware command.\n");
e315cd28 8136 ret = qla2x00_stop_firmware(vha);
18c6c127 8137 }
ec7193e2 8138
4b60c827 8139 QLA_FW_STOPPED(ha);
ec7193e2 8140 ha->flags.fw_init_done = 0;
18c6c127 8141}
2c3dfe3f
SJ		 8142
8143int
e315cd28 8144qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 8145{
8146 int rval = QLA_SUCCESS;
0b91d116 8147 int rval2;
2c3dfe3f 8148 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 8149 struct qla_hw_data *ha = vha->hw;
8150 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 8151
e315cd28 8152 if (!vha->vp_idx)
2c3dfe3f
SJ		 8153 return -EINVAL;
8154
e315cd28 8155 rval = qla2x00_fw_ready(base_vha);
67c2e93a 8156
2c3dfe3f 8157 if (rval == QLA_SUCCESS) {
e315cd28 8158 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
9eb9c6dc 8159 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 8160 }
8161
e315cd28 8162 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 8163
8164 /* Login to SNS first */
0b91d116
CD		 8165 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
8166 BIT_1);
8167 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
8168 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
8169 ql_dbg(ql_dbg_init, vha, 0x0120,
8170 "Failed SNS login: loop_id=%x, rval2=%d\n",
8171 NPH_SNS, rval2);
8172 else
8173 ql_dbg(ql_dbg_init, vha, 0x0103,
8174 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
8175 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
8176 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 8177 return (QLA_FUNCTION_FAILED);
8178 }
8179
e315cd28
AC		 8180 atomic_set(&vha->loop_down_timer, 0);
8181 atomic_set(&vha->loop_state, LOOP_UP);
8182 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
8183 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
8184 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 8185
8186 return rval;
8187}
4d4df193
HK		 8188
8189/* 84XX Support **************************************************************/
8190
8191static LIST_HEAD(qla_cs84xx_list);
8192static DEFINE_MUTEX(qla_cs84xx_mutex);
8193
8194static struct qla_chip_state_84xx *
e315cd28 8195qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 8196{
8197 struct qla_chip_state_84xx *cs84xx;
e315cd28 8198 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 8199
8200 mutex_lock(&qla_cs84xx_mutex);
8201
8202 /* Find any shared 84xx chip. */
8203 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
8204 if (cs84xx->bus == ha->pdev->bus) {
8205 kref_get(&cs84xx->kref);
8206 goto done;
8207 }
8208 }
8209
8210 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
8211 if (!cs84xx)
8212 goto done;
8213
8214 kref_init(&cs84xx->kref);
8215 spin_lock_init(&cs84xx->access_lock);
8216 mutex_init(&cs84xx->fw_update_mutex);
8217 cs84xx->bus = ha->pdev->bus;
8218
8219 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
8220done:
8221 mutex_unlock(&qla_cs84xx_mutex);
8222 return cs84xx;
8223}
8224
8225static void
8226__qla84xx_chip_release(struct kref *kref)
8227{
8228 struct qla_chip_state_84xx *cs84xx =
8229 container_of(kref, struct qla_chip_state_84xx, kref);
8230
8231 mutex_lock(&qla_cs84xx_mutex);
8232 list_del(&cs84xx->list);
8233 mutex_unlock(&qla_cs84xx_mutex);
8234 kfree(cs84xx);
8235}
8236
8237void
e315cd28 8238qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 8239{
e315cd28 8240 struct qla_hw_data *ha = vha->hw;
bd432bb5 8241
4d4df193
HK		 8242 if (ha->cs84xx)
8243 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
8244}
8245
8246static int
e315cd28 8247qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 8248{
8249 int rval;
8250 uint16_t status[2];
e315cd28 8251 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 8252
8253 mutex_lock(&ha->cs84xx->fw_update_mutex);
8254
e315cd28 8255 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 8256
8257 mutex_unlock(&ha->cs84xx->fw_update_mutex);
8258
58e2753c 8259 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED :
4d4df193
HK		 8260 QLA_SUCCESS;
8261}
3a03eb79
AV		 8262
8263/* 81XX Support **************************************************************/
8264
8265int
8266qla81xx_nvram_config(scsi_qla_host_t *vha)
8267{
8268 int rval;
8269 struct init_cb_81xx *icb;
8270 struct nvram_81xx *nv;
8271 uint32_t *dptr;
8272 uint8_t *dptr1, *dptr2;
8273 uint32_t chksum;
8274 uint16_t cnt;
8275 struct qla_hw_data *ha = vha->hw;
5fa8774c
JC		 8276 uint32_t faddr;
8277 struct active_regions active_regions = { };
3a03eb79
AV		 8278
8279 rval = QLA_SUCCESS;
8280 icb = (struct init_cb_81xx *)ha->init_cb;
8281 nv = ha->nvram;
8282
8283 /* Determine NVRAM starting address. */
f8f97b0c 8284 ha->nvram_size = sizeof(*nv);
3a03eb79 8285 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 8286 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
8287 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79 8288
3f006ac3 8289 if (IS_QLA28XX(ha) || IS_QLA27XX(ha))
5fa8774c
JC		 8290 qla28xx_get_aux_images(vha, &active_regions);
8291
3a03eb79
AV		 8292 /* Get VPD data into cache */
8293 ha->vpd = ha->nvram + VPD_OFFSET;
5fa8774c
JC		 8294
8295 faddr = ha->flt_region_vpd;
8296 if (IS_QLA28XX(ha)) {
8297 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE)
8298 faddr = ha->flt_region_vpd_sec;
8299 ql_dbg(ql_dbg_init, vha, 0x0110,
8300 "Loading %s nvram image.\n",
8301 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ?
8302 "primary" : "secondary");
8303 }
8304 qla24xx_read_flash_data(vha, ha->vpd, faddr, ha->vpd_size >> 2);
3a03eb79
AV		 8305
8306 /* Get NVRAM data into cache and calculate checksum. */
5fa8774c
JC		 8307 faddr = ha->flt_region_nvram;
8308 if (IS_QLA28XX(ha)) {
8309 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE)
8310 faddr = ha->flt_region_nvram_sec;
8311 }
8312 ql_dbg(ql_dbg_init, vha, 0x0110,
8313 "Loading %s nvram image.\n",
8314 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ?
8315 "primary" : "secondary");
8316 qla24xx_read_flash_data(vha, ha->nvram, faddr, ha->nvram_size >> 2);
8317
3d79038f 8318 dptr = (uint32_t *)nv;
da08ef5c
JC		 8319 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
8320 chksum += le32_to_cpu(*dptr);
3a03eb79 8321
7c3df132
SK		 8322 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
8323 "Contents of NVRAM:\n");
8324 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
f8f97b0c 8325 nv, ha->nvram_size);
3a03eb79
AV		 8326
8327 /* Bad NVRAM data, set defaults parameters. */
a28d9e4e
JC		 8328 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
8329 le16_to_cpu(nv->nvram_version) < ICB_VERSION) {
3a03eb79 8330 /* Reset NVRAM data. */
7c3df132 8331 ql_log(ql_log_info, vha, 0x0073,
3695310e
JC		 8332 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n",
8333 chksum, nv->id, le16_to_cpu(nv->nvram_version));
8334 ql_dump_buffer(ql_dbg_init, vha, 0x0073, nv, sizeof(*nv));
7c3df132
SK		 8335 ql_log(ql_log_info, vha, 0x0074,
8336 "Falling back to functioning (yet invalid -- WWPN) "
8337 "defaults.\n");
3a03eb79
AV		 8338
8339 /*
8340 * Set default initialization control block.
8341 */
8342 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 8343 nv->nvram_version = cpu_to_le16(ICB_VERSION);
8344 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 8345 nv->frame_payload_size = 2048;
ad950360
BVA		 8346 nv->execution_throttle = cpu_to_le16(0xFFFF);
8347 nv->exchange_count = cpu_to_le16(0);
3a03eb79 8348 nv->port_name[0] = 0x21;
f73cb695 8349 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 8350 nv->port_name[2] = 0x00;
8351 nv->port_name[3] = 0xe0;
8352 nv->port_name[4] = 0x8b;
8353 nv->port_name[5] = 0x1c;
8354 nv->port_name[6] = 0x55;
8355 nv->port_name[7] = 0x86;
8356 nv->node_name[0] = 0x20;
8357 nv->node_name[1] = 0x00;
8358 nv->node_name[2] = 0x00;
8359 nv->node_name[3] = 0xe0;
8360 nv->node_name[4] = 0x8b;
8361 nv->node_name[5] = 0x1c;
8362 nv->node_name[6] = 0x55;
8363 nv->node_name[7] = 0x86;
ad950360
BVA		 8364 nv->login_retry_count = cpu_to_le16(8);
8365 nv->interrupt_delay_timer = cpu_to_le16(0);
8366 nv->login_timeout = cpu_to_le16(0);
3a03eb79 8367 nv->firmware_options_1 =
ad950360
BVA		 8368 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
8369 nv->firmware_options_2 = cpu_to_le32(2 << 4);
8370 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
8371 nv->firmware_options_3 = cpu_to_le32(2 << 13);
8372 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
8373 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 8374 nv->reset_delay = 5;
ad950360
BVA		 8375 nv->max_luns_per_target = cpu_to_le16(128);
8376 nv->port_down_retry_count = cpu_to_le16(30);
8377 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 8378 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 8379 nv->enode_mac[1] = 0xC0;
8380 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 8381 nv->enode_mac[3] = 0x04;
8382 nv->enode_mac[4] = 0x05;
f73cb695 8383 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 8384
8385 rval = 1;
8386 }
8387
9e522cd8
AE		 8388 if (IS_T10_PI_CAPABLE(ha))
8389 nv->frame_payload_size &= ~7;
8390
aa230bc5
AE		 8391 qlt_81xx_config_nvram_stage1(vha, nv);
8392
3a03eb79 8393 /* Reset Initialization control block */
773120e4 8394 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 8395
8396 /* Copy 1st segment. */
8397 dptr1 = (uint8_t *)icb;
8398 dptr2 = (uint8_t *)&nv->version;
8399 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
8400 while (cnt--)
8401 *dptr1++ = *dptr2++;
8402
8403 icb->login_retry_count = nv->login_retry_count;
8404
8405 /* Copy 2nd segment. */
8406 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
8407 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
8408 cnt = (uint8_t *)&icb->reserved_5 -
8409 (uint8_t *)&icb->interrupt_delay_timer;
8410 while (cnt--)
8411 *dptr1++ = *dptr2++;
8412
8413 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
8414 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
8415 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 8416 icb->enode_mac[0] = 0x00;
8417 icb->enode_mac[1] = 0xC0;
8418 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 8419 icb->enode_mac[3] = 0x04;
8420 icb->enode_mac[4] = 0x05;
f73cb695 8421 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 8422 }
8423
b64b0e8f
AV		 8424 /* Use extended-initialization control block. */
8425 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
0eaaca4c 8426 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
3a03eb79
AV		 8427 /*
8428 * Setup driver NVRAM options.
8429 */
8430 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 8431 "QLE8XXX");
3a03eb79 8432
aa230bc5
AE		 8433 qlt_81xx_config_nvram_stage2(vha, icb);
8434
3a03eb79 8435 /* Use alternate WWN? */
ad950360 8436 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 8437 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
8438 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
8439 }
8440
8441 /* Prepare nodename */
ad950360 8442 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 8443 /*
8444 * Firmware will apply the following mask if the nodename was
8445 * not provided.
8446 */
8447 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
8448 icb->node_name[0] &= 0xF0;
8449 }
8450
8451 /* Set host adapter parameters. */
8452 ha->flags.disable_risc_code_load = 0;
8453 ha->flags.enable_lip_reset = 0;
8454 ha->flags.enable_lip_full_login =
58e2753c 8455 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0;
3a03eb79 8456 ha->flags.enable_target_reset =
58e2753c 8457 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0;
3a03eb79 8458 ha->flags.enable_led_scheme = 0;
58e2753c 8459 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0;
3a03eb79
AV		 8460
8461 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
8462 (BIT_6 | BIT_5 | BIT_4)) >> 4;
8463
8464 /* save HBA serial number */
8465 ha->serial0 = icb->port_name[5];
8466 ha->serial1 = icb->port_name[6];
8467 ha->serial2 = icb->port_name[7];
8468 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
8469 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
8470
ad950360 8471 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 8472
8473 ha->retry_count = le16_to_cpu(nv->login_retry_count);
8474
8475 /* Set minimum login_timeout to 4 seconds. */
8476 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
8477 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
8478 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 8479 nv->login_timeout = cpu_to_le16(4);
3a03eb79 8480 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 8481
8482 /* Set minimum RATOV to 100 tenths of a second. */
8483 ha->r_a_tov = 100;
8484
8485 ha->loop_reset_delay = nv->reset_delay;
8486
8487 /* Link Down Timeout = 0:
8488 *
7ec0effd 8489 * When Port Down timer expires we will start returning
3a03eb79
AV		 8490 * I/O's to OS with "DID_NO_CONNECT".
8491 *
8492 * Link Down Timeout != 0:
8493 *
8494 * The driver waits for the link to come up after link down
8495 * before returning I/Os to OS with "DID_NO_CONNECT".
8496 */
8497 if (le16_to_cpu(nv->link_down_timeout) == 0) {
8498 ha->loop_down_abort_time =
8499 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
8500 } else {
8501 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
8502 ha->loop_down_abort_time =
8503 (LOOP_DOWN_TIME - ha->link_down_timeout);
8504 }
8505
8506 /* Need enough time to try and get the port back. */
8507 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
8508 if (qlport_down_retry)
8509 ha->port_down_retry_count = qlport_down_retry;
8510
8511 /* Set login_retry_count */
8512 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
8513 if (ha->port_down_retry_count ==
8514 le16_to_cpu(nv->port_down_retry_count) &&
8515 ha->port_down_retry_count > 3)
8516 ha->login_retry_count = ha->port_down_retry_count;
8517 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
8518 ha->login_retry_count = ha->port_down_retry_count;
8519 if (ql2xloginretrycount)
8520 ha->login_retry_count = ql2xloginretrycount;
8521
6246b8a1 8522 /* if not running MSI-X we need handshaking on interrupts */
ecc89f25
JC		 8523 if (!vha->hw->flags.msix_enabled &&
8524 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)))
ad950360 8525 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 8526
3a03eb79
AV		 8527 /* Enable ZIO. */
8528 if (!vha->flags.init_done) {
8529 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
8530 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
8531 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
58e2753c 8532 le16_to_cpu(icb->interrupt_delay_timer) : 2;
3a03eb79 8533 }
ad950360 8534 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 8535 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
8536 vha->flags.process_response_queue = 0;
8537 if (ha->zio_mode != QLA_ZIO_DISABLED) {
8538 ha->zio_mode = QLA_ZIO_MODE_6;
8539
7c3df132 8540 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 8541 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 8542 ha->zio_mode,
8543 ha->zio_timer * 100);
3a03eb79
AV		 8544
8545 icb->firmware_options_2 |= cpu_to_le32(
8546 (uint32_t)ha->zio_mode);
8547 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
8548 vha->flags.process_response_queue = 1;
8549 }
8550
41dc529a 8551 /* enable RIDA Format2 */
48acad09 8552 icb->firmware_options_3 |= BIT_0;
41dc529a 8553
8777e431
QT		 8554 /* N2N: driver will initiate Login instead of FW */
8555 icb->firmware_options_3 |= BIT_8;
41dc529a 8556
3a03eb79 8557 if (rval) {
7c3df132
SK		 8558 ql_log(ql_log_warn, vha, 0x0076,
8559 "NVRAM configuration failed.\n");
3a03eb79
AV		 8560 }
8561 return (rval);
8562}
8563
a9083016
GM		 8564int
8565qla82xx_restart_isp(scsi_qla_host_t *vha)
8566{
8567 int status, rval;
a9083016 8568 struct qla_hw_data *ha = vha->hw;
a9083016 8569 struct scsi_qla_host *vp;
feafb7b1 8570 unsigned long flags;
a9083016
GM		 8571
8572 status = qla2x00_init_rings(vha);
8573 if (!status) {
8574 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8575 ha->flags.chip_reset_done = 1;
8576
8577 status = qla2x00_fw_ready(vha);
8578 if (!status) {
a9083016 8579 /* Issue a marker after FW becomes ready. */
9eb9c6dc 8580 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
a9083016 8581 vha->flags.online = 1;
7108b76e 8582 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 8583 }
8584
8585 /* if no cable then assume it's good */
8586 if ((vha->device_flags & DFLG_NO_CABLE))
8587 status = 0;
a9083016
GM		 8588 }
8589
8590 if (!status) {
8591 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8592
8593 if (!atomic_read(&vha->loop_down_timer)) {
8594 /*
8595 * Issue marker command only when we are going
8596 * to start the I/O .
8597 */
8598 vha->marker_needed = 1;
8599 }
8600
a9083016
GM		 8601 ha->isp_ops->enable_intrs(ha);
8602
8603 ha->isp_abort_cnt = 0;
8604 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
8605
53296788 8606 /* Update the firmware version */
3173167f 8607 status = qla82xx_check_md_needed(vha);
53296788 8608
a9083016
GM		 8609 if (ha->fce) {
8610 ha->flags.fce_enabled = 1;
8611 memset(ha->fce, 0,
8612 fce_calc_size(ha->fce_bufs));
8613 rval = qla2x00_enable_fce_trace(vha,
8614 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
8615 &ha->fce_bufs);
8616 if (rval) {
cfb0919c 8617 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 8618 "Unable to reinitialize FCE (%d).\n",
8619 rval);
a9083016
GM		 8620 ha->flags.fce_enabled = 0;
8621 }
8622 }
8623
8624 if (ha->eft) {
8625 memset(ha->eft, 0, EFT_SIZE);
8626 rval = qla2x00_enable_eft_trace(vha,
8627 ha->eft_dma, EFT_NUM_BUFFERS);
8628 if (rval) {
cfb0919c 8629 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 8630 "Unable to reinitialize EFT (%d).\n",
8631 rval);
a9083016
GM		 8632 }
8633 }
a9083016
GM		 8634 }
8635
8636 if (!status) {
cfb0919c 8637 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 8638 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 8639
8640 spin_lock_irqsave(&ha->vport_slock, flags);
8641 list_for_each_entry(vp, &ha->vp_list, list) {
8642 if (vp->vp_idx) {
8643 atomic_inc(&vp->vref_count);
8644 spin_unlock_irqrestore(&ha->vport_slock, flags);
8645
a9083016 8646 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 8647
8648 spin_lock_irqsave(&ha->vport_slock, flags);
8649 atomic_dec(&vp->vref_count);
8650 }
a9083016 8651 }
feafb7b1
AE		 8652 spin_unlock_irqrestore(&ha->vport_slock, flags);
8653
a9083016 8654 } else {
cfb0919c 8655 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 8656 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 8657 }
8658
8659 return status;
8660}
8661
3a03eb79 8662void
ae97c91e 8663qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 8664{
ae97c91e
AV		 8665 struct qla_hw_data *ha = vha->hw;
8666
f198cafa
HM		 8667 /* Hold status IOCBs until ABTS response received. */
8668 if (ql2xfwholdabts)
8669 ha->fw_options[3] |= BIT_12;
8670
088d09d4
GM		 8671 /* Set Retry FLOGI in case of P2P connection */
8672 if (ha->operating_mode == P2P) {
8673 ha->fw_options[2] |= BIT_3;
8674 ql_dbg(ql_dbg_disc, vha, 0x2103,
8675 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
8676 __func__, ha->fw_options[2]);
8677 }
8678
41dc529a
QT		 8679 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
8680 if (ql2xmvasynctoatio) {
8681 if (qla_tgt_mode_enabled(vha) ||
8682 qla_dual_mode_enabled(vha))
8683 ha->fw_options[2] |= BIT_11;
8684 else
8685 ha->fw_options[2] &= ~BIT_11;
8686 }
8687
f7e761f5 8688 if (qla_tgt_mode_enabled(vha) ||
2da52737
QT		 8689 qla_dual_mode_enabled(vha)) {
8690 /* FW auto send SCSI status during */
8691 ha->fw_options[1] |= BIT_8;
8692 ha->fw_options[10] |= (u16)SAM_STAT_BUSY << 8;
8693
8694 /* FW perform Exchange validation */
f7e761f5 8695 ha->fw_options[2] |= BIT_4;
2da52737
QT		 8696 } else {
8697 ha->fw_options[1] &= ~BIT_8;
8698 ha->fw_options[10] &= 0x00ff;
8699
f7e761f5 8700 ha->fw_options[2] &= ~BIT_4;
2da52737 8701 }
f7e761f5 8702
41dc529a
QT		 8703 if (ql2xetsenable) {
8704 /* Enable ETS Burst. */
8705 memset(ha->fw_options, 0, sizeof(ha->fw_options));
8706 ha->fw_options[2] |= BIT_9;
8707 }
8708
83548fe2
QT		 8709 ql_dbg(ql_dbg_init, vha, 0x00e9,
8710 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
8711 __func__, ha->fw_options[1], ha->fw_options[2],
8712 ha->fw_options[3], vha->host->active_mode);
ae97c91e 8713
ae97c91e 8714 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 8715}
09ff701a
SR		 8716
8717/*
8718 * qla24xx_get_fcp_prio
8719 * Gets the fcp cmd priority value for the logged in port.
8720 * Looks for a match of the port descriptors within
8721 * each of the fcp prio config entries. If a match is found,
8722 * the tag (priority) value is returned.
8723 *
8724 * Input:
21090cbe 8725 * vha = scsi host structure pointer.
09ff701a
SR		 8726 * fcport = port structure pointer.
8727 *
8728 * Return:
6c452a45 8729 * non-zero (if found)
f28a0a96 8730 * -1 (if not found)
09ff701a
SR		 8731 *
8732 * Context:
8733 * Kernel context
8734 */
f28a0a96 8735static int
09ff701a
SR		 8736qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
8737{
8738 int i, entries;
8739 uint8_t pid_match, wwn_match;
f28a0a96 8740 int priority;
09ff701a
SR		 8741 uint32_t pid1, pid2;
8742 uint64_t wwn1, wwn2;
8743 struct qla_fcp_prio_entry *pri_entry;
8744 struct qla_hw_data *ha = vha->hw;
8745
8746 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 8747 return -1;
09ff701a 8748
f28a0a96 8749 priority = -1;
09ff701a
SR		 8750 entries = ha->fcp_prio_cfg->num_entries;
8751 pri_entry = &ha->fcp_prio_cfg->entry[0];
8752
8753 for (i = 0; i < entries; i++) {
8754 pid_match = wwn_match = 0;
8755
8756 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
8757 pri_entry++;
8758 continue;
8759 }
8760
8761 /* check source pid for a match */
8762 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
8763 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
8764 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
8765 if (pid1 == INVALID_PORT_ID)
8766 pid_match++;
8767 else if (pid1 == pid2)
8768 pid_match++;
8769 }
8770
8771 /* check destination pid for a match */
8772 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
8773 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
8774 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
8775 if (pid1 == INVALID_PORT_ID)
8776 pid_match++;
8777 else if (pid1 == pid2)
8778 pid_match++;
8779 }
8780
8781 /* check source WWN for a match */
8782 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
8783 wwn1 = wwn_to_u64(vha->port_name);
8784 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
8785 if (wwn2 == (uint64_t)-1)
8786 wwn_match++;
8787 else if (wwn1 == wwn2)
8788 wwn_match++;
8789 }
8790
8791 /* check destination WWN for a match */
8792 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
8793 wwn1 = wwn_to_u64(fcport->port_name);
8794 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
8795 if (wwn2 == (uint64_t)-1)
8796 wwn_match++;
8797 else if (wwn1 == wwn2)
8798 wwn_match++;
8799 }
8800
8801 if (pid_match == 2 || wwn_match == 2) {
8802 /* Found a matching entry */
8803 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
8804 priority = pri_entry->tag;
8805 break;
8806 }
8807
8808 pri_entry++;
8809 }
8810
8811 return priority;
8812}
8813
8814/*
8815 * qla24xx_update_fcport_fcp_prio
8816 * Activates fcp priority for the logged in fc port
8817 *
8818 * Input:
21090cbe 8819 * vha = scsi host structure pointer.
09ff701a
SR		 8820 * fcp = port structure pointer.
8821 *
8822 * Return:
8823 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8824 *
8825 * Context:
8826 * Kernel context.
8827 */
8828int
21090cbe 8829qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 8830{
8831 int ret;
f28a0a96 8832 int priority;
09ff701a
SR		 8833 uint16_t mb[5];
8834
21090cbe
MI		 8835 if (fcport->port_type != FCT_TARGET ||
8836 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 8837 return QLA_FUNCTION_FAILED;
8838
21090cbe 8839 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 8840 if (priority < 0)
8841 return QLA_FUNCTION_FAILED;
8842
7ec0effd 8843 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 8844 fcport->fcp_prio = priority & 0xf;
8845 return QLA_SUCCESS;
8846 }
8847
21090cbe 8848 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 8849 if (ret == QLA_SUCCESS) {
8850 if (fcport->fcp_prio != priority)
8851 ql_dbg(ql_dbg_user, vha, 0x709e,
8852 "Updated FCP_CMND priority - value=%d loop_id=%d "
8853 "port_id=%02x%02x%02x.\n", priority,
8854 fcport->loop_id, fcport->d_id.b.domain,
8855 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 8856 fcport->fcp_prio = priority & 0xf;
cfb0919c 8857 } else
7c3df132 8858 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 8859 "Unable to update FCP_CMND priority - ret=0x%x for "
8860 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
8861 fcport->d_id.b.domain, fcport->d_id.b.area,
8862 fcport->d_id.b.al_pa);
09ff701a
SR		 8863 return ret;
8864}
8865
8866/*
8867 * qla24xx_update_all_fcp_prio
8868 * Activates fcp priority for all the logged in ports
8869 *
8870 * Input:
8871 * ha = adapter block pointer.
8872 *
8873 * Return:
8874 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8875 *
8876 * Context:
8877 * Kernel context.
8878 */
8879int
8880qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
8881{
8882 int ret;
8883 fc_port_t *fcport;
8884
8885 ret = QLA_FUNCTION_FAILED;
8886 /* We need to set priority for all logged in ports */
8887 list_for_each_entry(fcport, &vha->vp_fcports, list)
8888 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
8889
8890 return ret;
8891}
d7459527 8892
82de802a
QT		 8893struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos,
8894 int vp_idx, bool startqp)
d7459527
MH		 8895{
8896 int rsp_id = 0;
8897 int req_id = 0;
8898 int i;
8899 struct qla_hw_data *ha = vha->hw;
8900 uint16_t qpair_id = 0;
8901 struct qla_qpair *qpair = NULL;
8902 struct qla_msix_entry *msix;
8903
8904 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
8905 ql_log(ql_log_warn, vha, 0x00181,
8906 "FW/Driver is not multi-queue capable.\n");
8907 return NULL;
8908 }
8909
c38d1baf 8910 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 8911 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
8912 if (qpair == NULL) {
8913 ql_log(ql_log_warn, vha, 0x0182,
8914 "Failed to allocate memory for queue pair.\n");
8915 return NULL;
8916 }
d7459527
MH		 8917
8918 qpair->hw = vha->hw;
25ff6af1 8919 qpair->vha = vha;
82de802a
QT		 8920 qpair->qp_lock_ptr = &qpair->qp_lock;
8921 spin_lock_init(&qpair->qp_lock);
af7bb382 8922 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
d7459527
MH		 8923
8924 /* Assign available que pair id */
8925 mutex_lock(&ha->mq_lock);
8926 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
b95b9452 8927 if (ha->num_qpairs >= ha->max_qpairs) {
d7459527
MH		 8928 mutex_unlock(&ha->mq_lock);
8929 ql_log(ql_log_warn, vha, 0x0183,
8930 "No resources to create additional q pair.\n");
8931 goto fail_qid_map;
8932 }
b95b9452 8933 ha->num_qpairs++;
d7459527
MH		 8934 set_bit(qpair_id, ha->qpair_qid_map);
8935 ha->queue_pair_map[qpair_id] = qpair;
8936 qpair->id = qpair_id;
8937 qpair->vp_idx = vp_idx;
e6373f33 8938 qpair->fw_started = ha->flags.fw_started;
e326d22a 8939 INIT_LIST_HEAD(&qpair->hints_list);
7c3f8fd1
QT		 8940 qpair->chip_reset = ha->base_qpair->chip_reset;
8941 qpair->enable_class_2 = ha->base_qpair->enable_class_2;
8942 qpair->enable_explicit_conf =
8943 ha->base_qpair->enable_explicit_conf;
d7459527
MH		 8944
8945 for (i = 0; i < ha->msix_count; i++) {
093df737 8946 msix = &ha->msix_entries[i];
d7459527
MH		 8947 if (msix->in_use)
8948 continue;
8949 qpair->msix = msix;
83548fe2 8950 ql_dbg(ql_dbg_multiq, vha, 0xc00f,
d7459527
MH		 8951 "Vector %x selected for qpair\n", msix->vector);
8952 break;
8953 }
8954 if (!qpair->msix) {
8955 ql_log(ql_log_warn, vha, 0x0184,
8956 "Out of MSI-X vectors!.\n");
8957 goto fail_msix;
8958 }
8959
8960 qpair->msix->in_use = 1;
8961 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
8abfa9e2 8962 qpair->pdev = ha->pdev;
ecc89f25 8963 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
8abfa9e2 8964 qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
d7459527
MH		 8965
8966 mutex_unlock(&ha->mq_lock);
8967
8968 /* Create response queue first */
82de802a 8969 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp);
d7459527
MH		 8970 if (!rsp_id) {
8971 ql_log(ql_log_warn, vha, 0x0185,
8972 "Failed to create response queue.\n");
8973 goto fail_rsp;
8974 }
8975
8976 qpair->rsp = ha->rsp_q_map[rsp_id];
8977
8978 /* Create request queue */
82de802a
QT		 8979 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos,
8980 startqp);
d7459527
MH		 8981 if (!req_id) {
8982 ql_log(ql_log_warn, vha, 0x0186,
8983 "Failed to create request queue.\n");
8984 goto fail_req;
8985 }
8986
8987 qpair->req = ha->req_q_map[req_id];
8988 qpair->rsp->req = qpair->req;
82de802a 8989 qpair->rsp->qpair = qpair;
e326d22a
QT		 8990 /* init qpair to this cpu. Will adjust at run time. */
8991 qla_cpu_update(qpair, smp_processor_id());
d7459527
MH		 8992
8993 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
8994 if (ha->fw_attributes & BIT_4)
8995 qpair->difdix_supported = 1;
8996 }
8997
8998 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
8999 if (!qpair->srb_mempool) {
83548fe2 9000 ql_log(ql_log_warn, vha, 0xd036,
d7459527
MH		 9001 "Failed to create srb mempool for qpair %d\n",
9002 qpair->id);
9003 goto fail_mempool;
9004 }
9005
9006 /* Mark as online */
9007 qpair->online = 1;
9008
9009 if (!vha->flags.qpairs_available)
9010 vha->flags.qpairs_available = 1;
9011
9012 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
9013 "Request/Response queue pair created, id %d\n",
9014 qpair->id);
9015 ql_dbg(ql_dbg_init, vha, 0x0187,
9016 "Request/Response queue pair created, id %d\n",
9017 qpair->id);
9018 }
9019 return qpair;
9020
9021fail_mempool:
9022fail_req:
9023 qla25xx_delete_rsp_que(vha, qpair->rsp);
9024fail_rsp:
9025 mutex_lock(&ha->mq_lock);
9026 qpair->msix->in_use = 0;
9027 list_del(&qpair->qp_list_elem);
9028 if (list_empty(&vha->qp_list))
9029 vha->flags.qpairs_available = 0;
9030fail_msix:
9031 ha->queue_pair_map[qpair_id] = NULL;
9032 clear_bit(qpair_id, ha->qpair_qid_map);
b95b9452 9033 ha->num_qpairs--;
d7459527
MH		 9034 mutex_unlock(&ha->mq_lock);
9035fail_qid_map:
9036 kfree(qpair);
9037 return NULL;
9038}
9039
9040int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
9041{
d65237c7 9042 int ret = QLA_FUNCTION_FAILED;
d7459527
MH		 9043 struct qla_hw_data *ha = qpair->hw;
9044
9045 qpair->delete_in_progress = 1;
9046 while (atomic_read(&qpair->ref_count))
9047 msleep(500);
9048
9049 ret = qla25xx_delete_req_que(vha, qpair->req);
9050 if (ret != QLA_SUCCESS)
9051 goto fail;
7867b98d 9052
d7459527
MH		 9053 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
9054 if (ret != QLA_SUCCESS)
9055 goto fail;
9056
9057 mutex_lock(&ha->mq_lock);
9058 ha->queue_pair_map[qpair->id] = NULL;
9059 clear_bit(qpair->id, ha->qpair_qid_map);
b95b9452 9060 ha->num_qpairs--;
d7459527 9061 list_del(&qpair->qp_list_elem);
d65237c7 9062 if (list_empty(&vha->qp_list)) {
d7459527 9063 vha->flags.qpairs_available = 0;
d65237c7
SC		 9064 vha->flags.qpairs_req_created = 0;
9065 vha->flags.qpairs_rsp_created = 0;
9066 }
d7459527
MH		 9067 mempool_destroy(qpair->srb_mempool);
9068 kfree(qpair);
9069 mutex_unlock(&ha->mq_lock);
9070
9071 return QLA_SUCCESS;
9072fail:
9073 return ret;
9074}
Linux 6.x block layer and io_uring tree(s)