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scsi: qla2xxx: Declare fourth qla2x00_set_model_info() argument const
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
726b8548 33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
1da177e4 34static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 35
4d4df193
HK		 36static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
37static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 38static int qla25xx_init_queues(struct qla_hw_data *);
a5d42f4c 39static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *);
726b8548
QT		 40static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *,
41 struct event_arg *);
a5d42f4c
DG		 42static void qla24xx_handle_prli_done_event(struct scsi_qla_host *,
43 struct event_arg *);
a4239945 44static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *);
4d4df193 45
ac280b67
AV		 46/* SRB Extensions ---------------------------------------------------------- */
47
9ba56b95 48void
8e5f4ba0 49qla2x00_sp_timeout(struct timer_list *t)
ac280b67 50{
8e5f4ba0 51 srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer);
4916392b 52 struct srb_iocb *iocb;
ac280b67
AV		 53 struct req_que *req;
54 unsigned long flags;
bcc71cc3 55 struct qla_hw_data *ha = sp->vha->hw;
ac280b67 56
ef801f07 57 WARN_ON_ONCE(irqs_disabled());
bcc71cc3 58 spin_lock_irqsave(&ha->hardware_lock, flags);
f6145e86 59 req = sp->qpair->req;
ac280b67 60 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 61 iocb = &sp->u.iocb_cmd;
bcc71cc3 62 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4916392b 63 iocb->timeout(sp);
ac280b67
AV		 64}
65
9ba56b95 66void
25ff6af1 67qla2x00_sp_free(void *ptr)
ac280b67 68{
25ff6af1 69 srb_t *sp = ptr;
9ba56b95 70 struct srb_iocb *iocb = &sp->u.iocb_cmd;
ac280b67 71
4d97cc53 72 del_timer(&iocb->timer);
25ff6af1 73 qla2x00_rel_sp(sp);
ac280b67
AV		 74}
75
ac280b67
AV		 76/* Asynchronous Login/Logout Routines -------------------------------------- */
77
a9b6f722 78unsigned long
5b91490e
AV		 79qla2x00_get_async_timeout(struct scsi_qla_host *vha)
80{
81 unsigned long tmo;
82 struct qla_hw_data *ha = vha->hw;
83
84 /* Firmware should use switch negotiated r_a_tov for timeout. */
85 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 86 if (IS_QLAFX00(ha)) {
87 tmo = FX00_DEF_RATOV * 2;
88 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 89 /*
90 * Except for earlier ISPs where the timeout is seeded from the
91 * initialization control block.
92 */
93 tmo = ha->login_timeout;
94 }
95 return tmo;
96}
ac280b67 97
1956eee5
BVA		 98static void qla24xx_abort_iocb_timeout(void *data)
99{
100 srb_t *sp = data;
101 struct srb_iocb *abt = &sp->u.iocb_cmd;
0c6df590
QT		 102 struct qla_qpair *qpair = sp->qpair;
103 u32 handle;
104 unsigned long flags;
105
106 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
107 for (handle = 1; handle < qpair->req->num_outstanding_cmds; handle++) {
108 /* removing the abort */
109 if (qpair->req->outstanding_cmds[handle] == sp) {
110 qpair->req->outstanding_cmds[handle] = NULL;
111 break;
112 }
113 }
114 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1956eee5
BVA		 115
116 abt->u.abt.comp_status = CS_TIMEOUT;
0c6df590 117 sp->done(sp, QLA_OS_TIMER_EXPIRED);
1956eee5
BVA		 118}
119
120static void qla24xx_abort_sp_done(void *ptr, int res)
121{
122 srb_t *sp = ptr;
123 struct srb_iocb *abt = &sp->u.iocb_cmd;
124
f1333c48
BVA		 125 del_timer(&sp->u.iocb_cmd.timer);
126 if (sp->flags & SRB_WAKEUP_ON_COMP)
127 complete(&abt->u.abt.comp);
128 else
129 sp->free(sp);
1956eee5
BVA		 130}
131
132static int qla24xx_async_abort_cmd(srb_t *cmd_sp, bool wait)
133{
134 scsi_qla_host_t *vha = cmd_sp->vha;
135 struct srb_iocb *abt_iocb;
136 srb_t *sp;
137 int rval = QLA_FUNCTION_FAILED;
138
139 sp = qla2xxx_get_qpair_sp(cmd_sp->vha, cmd_sp->qpair, cmd_sp->fcport,
140 GFP_ATOMIC);
141 if (!sp)
142 goto done;
143
144 abt_iocb = &sp->u.iocb_cmd;
145 sp->type = SRB_ABT_CMD;
146 sp->name = "abort";
147 sp->qpair = cmd_sp->qpair;
148 if (wait)
149 sp->flags = SRB_WAKEUP_ON_COMP;
150
151 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
152 init_completion(&abt_iocb->u.abt.comp);
153 /* FW can send 2 x ABTS's timeout/20s */
154 qla2x00_init_timer(sp, 42);
155
156 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
157 abt_iocb->u.abt.req_que_no = cpu_to_le16(cmd_sp->qpair->req->id);
158
159 sp->done = qla24xx_abort_sp_done;
160
161 ql_dbg(ql_dbg_async, vha, 0x507c,
162 "Abort command issued - hdl=%x, type=%x\n", cmd_sp->handle,
163 cmd_sp->type);
164
165 rval = qla2x00_start_sp(sp);
166 if (rval != QLA_SUCCESS)
167 goto done_free_sp;
168
169 if (wait) {
170 wait_for_completion(&abt_iocb->u.abt.comp);
171 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
172 QLA_SUCCESS : QLA_FUNCTION_FAILED;
173 } else {
174 goto done;
175 }
176
177done_free_sp:
178 sp->free(sp);
179done:
180 return rval;
181}
182
726b8548 183void
9ba56b95 184qla2x00_async_iocb_timeout(void *data)
ac280b67 185{
25ff6af1 186 srb_t *sp = data;
ac280b67 187 fc_port_t *fcport = sp->fcport;
726b8548 188 struct srb_iocb *lio = &sp->u.iocb_cmd;
f6145e86
QT		 189 int rc, h;
190 unsigned long flags;
ac280b67 191
5c25d451
QT		 192 if (fcport) {
193 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
194 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
195 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
196
6d674927 197 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
5c25d451
QT		 198 } else {
199 pr_info("Async-%s timeout - hdl=%x.\n",
200 sp->name, sp->handle);
201 }
726b8548
QT		 202
203 switch (sp->type) {
204 case SRB_LOGIN_CMD:
f6145e86
QT		 205 rc = qla24xx_async_abort_cmd(sp, false);
206 if (rc) {
207 /* Retry as needed. */
208 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
209 lio->u.logio.data[1] =
210 lio->u.logio.flags & SRB_LOGIN_RETRIED ?
211 QLA_LOGIO_LOGIN_RETRIED : 0;
212 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
213 for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
214 h++) {
215 if (sp->qpair->req->outstanding_cmds[h] ==
216 sp) {
217 sp->qpair->req->outstanding_cmds[h] =
218 NULL;
219 break;
220 }
221 }
222 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
223 sp->done(sp, QLA_FUNCTION_TIMEOUT);
224 }
726b8548
QT		 225 break;
226 case SRB_LOGOUT_CMD:
726b8548
QT		 227 case SRB_CT_PTHRU_CMD:
228 case SRB_MB_IOCB:
229 case SRB_NACK_PLOGI:
230 case SRB_NACK_PRLI:
231 case SRB_NACK_LOGO:
2853192e 232 case SRB_CTRL_VP:
f6145e86
QT		 233 rc = qla24xx_async_abort_cmd(sp, false);
234 if (rc) {
235 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
236 for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
237 h++) {
238 if (sp->qpair->req->outstanding_cmds[h] ==
239 sp) {
240 sp->qpair->req->outstanding_cmds[h] =
241 NULL;
242 break;
243 }
244 }
245 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
246 sp->done(sp, QLA_FUNCTION_TIMEOUT);
247 }
726b8548 248 break;
6ac52608 249 }
ac280b67
AV		 250}
251
99b0bec7 252static void
25ff6af1 253qla2x00_async_login_sp_done(void *ptr, int res)
99b0bec7 254{
25ff6af1
JC		 255 srb_t *sp = ptr;
256 struct scsi_qla_host *vha = sp->vha;
9ba56b95 257 struct srb_iocb *lio = &sp->u.iocb_cmd;
726b8548 258 struct event_arg ea;
9ba56b95 259
83548fe2 260 ql_dbg(ql_dbg_disc, vha, 0x20dd,
25ff6af1 261 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
726b8548 262
6d674927
QT		 263 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
264
726b8548
QT		 265 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
266 memset(&ea, 0, sizeof(ea));
267 ea.event = FCME_PLOGI_DONE;
268 ea.fcport = sp->fcport;
269 ea.data[0] = lio->u.logio.data[0];
270 ea.data[1] = lio->u.logio.data[1];
271 ea.iop[0] = lio->u.logio.iop[0];
272 ea.iop[1] = lio->u.logio.iop[1];
273 ea.sp = sp;
274 qla2x00_fcport_event_handler(vha, &ea);
275 }
9ba56b95 276
25ff6af1 277 sp->free(sp);
99b0bec7
AV		 278}
279
48acad09
QT		 280static inline bool
281fcport_is_smaller(fc_port_t *fcport)
282{
283 if (wwn_to_u64(fcport->port_name) <
284 wwn_to_u64(fcport->vha->port_name))
285 return true;
286 else
287 return false;
288}
289
290static inline bool
291fcport_is_bigger(fc_port_t *fcport)
292{
293 return !fcport_is_smaller(fcport);
294}
295
ac280b67
AV		 296int
297qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
298 uint16_t *data)
299{
ac280b67 300 srb_t *sp;
4916392b 301 struct srb_iocb *lio;
726b8548
QT		 302 int rval = QLA_FUNCTION_FAILED;
303
8b5292bc
QT		 304 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) ||
305 fcport->loop_id == FC_NO_LOOP_ID) {
306 ql_log(ql_log_warn, vha, 0xffff,
307 "%s: %8phC - not sending command.\n",
308 __func__, fcport->port_name);
309 return rval;
310 }
726b8548 311
9ba56b95 312 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 313 if (!sp)
314 goto done;
315
726b8548
QT		 316 fcport->flags |= FCF_ASYNC_SENT;
317 fcport->logout_completed = 0;
318
a4239945 319 fcport->disc_state = DSC_LOGIN_PEND;
9ba56b95
GM		 320 sp->type = SRB_LOGIN_CMD;
321 sp->name = "login";
a4239945
QT		 322 sp->gen1 = fcport->rscn_gen;
323 sp->gen2 = fcport->login_gen;
9ba56b95
GM		 324
325 lio = &sp->u.iocb_cmd;
3822263e 326 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 327 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
328
9ba56b95 329 sp->done = qla2x00_async_login_sp_done;
835aa4f2 330 if (N2N_TOPO(fcport->vha->hw) && fcport_is_bigger(fcport))
48acad09 331 lio->u.logio.flags |= SRB_LOGIN_PRLI_ONLY;
835aa4f2 332 else
48acad09 333 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
a5d42f4c 334
835aa4f2
GM		 335 if (fcport->fc4f_nvme)
336 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI;
a5d42f4c 337
9fe278f4
GM		 338 ql_dbg(ql_dbg_disc, vha, 0x2072,
339 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
340 "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
341 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
342 fcport->login_retry);
343
ac280b67 344 rval = qla2x00_start_sp(sp);
080c9517 345 if (rval != QLA_SUCCESS) {
080c9517
CD		 346 fcport->flags |= FCF_LOGIN_NEEDED;
347 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 348 goto done_free_sp;
080c9517 349 }
ac280b67 350
ac280b67
AV		 351 return rval;
352
353done_free_sp:
25ff6af1 354 sp->free(sp);
726b8548 355 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 356done:
fa83e658 357 fcport->flags &= ~FCF_ASYNC_ACTIVE;
ac280b67
AV		 358 return rval;
359}
360
99b0bec7 361static void
25ff6af1 362qla2x00_async_logout_sp_done(void *ptr, int res)
99b0bec7 363{
25ff6af1 364 srb_t *sp = ptr;
9ba56b95 365
6d674927 366 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
eaf75d18
QT		 367 sp->fcport->login_gen++;
368 qlt_logo_completion_handler(sp->fcport, res);
25ff6af1 369 sp->free(sp);
99b0bec7
AV		 370}
371
ac280b67
AV		 372int
373qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
374{
ac280b67 375 srb_t *sp;
4916392b 376 struct srb_iocb *lio;
3dbec59b
QT		 377 int rval = QLA_FUNCTION_FAILED;
378
726b8548 379 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 380 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 381 if (!sp)
382 goto done;
383
9ba56b95
GM		 384 sp->type = SRB_LOGOUT_CMD;
385 sp->name = "logout";
9ba56b95
GM		 386
387 lio = &sp->u.iocb_cmd;
3822263e 388 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 389 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
390
9ba56b95 391 sp->done = qla2x00_async_logout_sp_done;
ac280b67 392
7c3df132 393 ql_dbg(ql_dbg_disc, vha, 0x2070,
726b8548 394 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
cfb0919c 395 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
726b8548
QT		 396 fcport->d_id.b.area, fcport->d_id.b.al_pa,
397 fcport->port_name);
9fe278f4
GM		 398
399 rval = qla2x00_start_sp(sp);
400 if (rval != QLA_SUCCESS)
401 goto done_free_sp;
ac280b67
AV		 402 return rval;
403
404done_free_sp:
25ff6af1 405 sp->free(sp);
ac280b67 406done:
fa83e658 407 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
ac280b67
AV		 408 return rval;
409}
11aea16a
QT		 410
411void
412qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport,
413 uint16_t *data)
414{
fa83e658 415 fcport->flags &= ~FCF_ASYNC_ACTIVE;
11aea16a
QT		 416 /* Don't re-login in target mode */
417 if (!fcport->tgt_session)
418 qla2x00_mark_device_lost(vha, fcport, 1, 0);
419 qlt_logo_completion_handler(fcport, data[0]);
420}
421
422static void
423qla2x00_async_prlo_sp_done(void *s, int res)
424{
425 srb_t *sp = (srb_t *)s;
426 struct srb_iocb *lio = &sp->u.iocb_cmd;
427 struct scsi_qla_host *vha = sp->vha;
428
fa83e658 429 sp->fcport->flags &= ~FCF_ASYNC_ACTIVE;
11aea16a
QT		 430 if (!test_bit(UNLOADING, &vha->dpc_flags))
431 qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport,
432 lio->u.logio.data);
433 sp->free(sp);
434}
435
436int
437qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport)
438{
439 srb_t *sp;
440 struct srb_iocb *lio;
441 int rval;
442
443 rval = QLA_FUNCTION_FAILED;
444 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
445 if (!sp)
446 goto done;
447
448 sp->type = SRB_PRLO_CMD;
449 sp->name = "prlo";
11aea16a
QT		 450
451 lio = &sp->u.iocb_cmd;
452 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 453 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
454
11aea16a 455 sp->done = qla2x00_async_prlo_sp_done;
11aea16a
QT		 456
457 ql_dbg(ql_dbg_disc, vha, 0x2070,
458 "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
459 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
460 fcport->d_id.b.area, fcport->d_id.b.al_pa);
f233e8c0
BK		 461
462 rval = qla2x00_start_sp(sp);
463 if (rval != QLA_SUCCESS)
464 goto done_free_sp;
465
11aea16a
QT		 466 return rval;
467
468done_free_sp:
469 sp->free(sp);
470done:
fa83e658 471 fcport->flags &= ~FCF_ASYNC_ACTIVE;
11aea16a
QT		 472 return rval;
473}
474
f13515ac
QT		 475static
476void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea)
477{
0616e965
QT		 478 struct fc_port *fcport = ea->fcport;
479
480 ql_dbg(ql_dbg_disc, vha, 0x20d2,
481 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n",
482 __func__, fcport->port_name, fcport->disc_state,
483 fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2,
484 fcport->rscn_gen, ea->sp->gen1, fcport->loop_id);
485
486 if (ea->data[0] != MBS_COMMAND_COMPLETE) {
a4239945
QT		 487 ql_dbg(ql_dbg_disc, vha, 0x2066,
488 "%s %8phC: adisc fail: post delete\n",
489 __func__, ea->fcport->port_name);
2d3fdbeb
QT		 490 /* deleted = 0 & logout_on_delete = force fw cleanup */
491 fcport->deleted = 0;
492 fcport->logout_on_delete = 1;
94cff6e1 493 qlt_schedule_sess_for_deletion(ea->fcport);
a4239945
QT		 494 return;
495 }
a4239945
QT		 496
497 if (ea->fcport->disc_state == DSC_DELETE_PEND)
498 return;
499
500 if (ea->sp->gen2 != ea->fcport->login_gen) {
501 /* target side must have changed it. */
502 ql_dbg(ql_dbg_disc, vha, 0x20d3,
0616e965
QT		 503 "%s %8phC generation changed\n",
504 __func__, ea->fcport->port_name);
a4239945
QT		 505 return;
506 } else if (ea->sp->gen1 != ea->fcport->rscn_gen) {
d4f7a16a 507 qla_rscn_replay(fcport);
861d483d 508 qlt_schedule_sess_for_deletion(fcport);
a4239945
QT		 509 return;
510 }
511
512 __qla24xx_handle_gpdb_event(vha, ea);
f13515ac 513}
ac280b67 514
8f9a2148 515static int qla_post_els_plogi_work(struct scsi_qla_host *vha, fc_port_t *fcport)
8777e431
QT		 516{
517 struct qla_work_evt *e;
518
519 e = qla2x00_alloc_work(vha, QLA_EVT_ELS_PLOGI);
520 if (!e)
521 return QLA_FUNCTION_FAILED;
522
523 e->u.fcport.fcport = fcport;
524 fcport->flags |= FCF_ASYNC_ACTIVE;
525 return qla2x00_post_work(vha, e);
526}
527
5ff1d584 528static void
25ff6af1 529qla2x00_async_adisc_sp_done(void *ptr, int res)
5ff1d584 530{
25ff6af1
JC		 531 srb_t *sp = ptr;
532 struct scsi_qla_host *vha = sp->vha;
f13515ac 533 struct event_arg ea;
0616e965 534 struct srb_iocb *lio = &sp->u.iocb_cmd;
f13515ac
QT		 535
536 ql_dbg(ql_dbg_disc, vha, 0x2066,
537 "Async done-%s res %x %8phC\n",
538 sp->name, res, sp->fcport->port_name);
539
15b6c3c9 540 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
fa83e658 541
f13515ac
QT		 542 memset(&ea, 0, sizeof(ea));
543 ea.event = FCME_ADISC_DONE;
544 ea.rc = res;
0616e965
QT		 545 ea.data[0] = lio->u.logio.data[0];
546 ea.data[1] = lio->u.logio.data[1];
547 ea.iop[0] = lio->u.logio.iop[0];
548 ea.iop[1] = lio->u.logio.iop[1];
f13515ac
QT		 549 ea.fcport = sp->fcport;
550 ea.sp = sp;
551
552 qla2x00_fcport_event_handler(vha, &ea);
9ba56b95 553
25ff6af1 554 sp->free(sp);
5ff1d584
AV		 555}
556
557int
558qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
559 uint16_t *data)
560{
5ff1d584 561 srb_t *sp;
4916392b 562 struct srb_iocb *lio;
192c4e9b
QT		 563 int rval = QLA_FUNCTION_FAILED;
564
565 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
566 return rval;
5ff1d584 567
726b8548 568 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 569 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 570 if (!sp)
571 goto done;
572
9ba56b95
GM		 573 sp->type = SRB_ADISC_CMD;
574 sp->name = "adisc";
9ba56b95
GM		 575
576 lio = &sp->u.iocb_cmd;
3822263e 577 lio->timeout = qla2x00_async_iocb_timeout;
8777e431
QT		 578 sp->gen1 = fcport->rscn_gen;
579 sp->gen2 = fcport->login_gen;
e74e7d95
BH		 580 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
581
9ba56b95 582 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 583 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 584 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584 585
7c3df132 586 ql_dbg(ql_dbg_disc, vha, 0x206f,
f13515ac
QT		 587 "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n",
588 sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name);
9fe278f4
GM		 589
590 rval = qla2x00_start_sp(sp);
591 if (rval != QLA_SUCCESS)
592 goto done_free_sp;
593
5ff1d584
AV		 594 return rval;
595
596done_free_sp:
25ff6af1 597 sp->free(sp);
5ff1d584 598done:
fa83e658 599 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
f13515ac 600 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548
QT		 601 return rval;
602}
603
0c6660b2
BVA		 604static bool qla2x00_is_reserved_id(scsi_qla_host_t *vha, uint16_t loop_id)
605{
606 struct qla_hw_data *ha = vha->hw;
607
608 if (IS_FWI2_CAPABLE(ha))
609 return loop_id > NPH_LAST_HANDLE;
610
611 return (loop_id > ha->max_loop_id && loop_id < SNS_FIRST_LOOP_ID) ||
612 loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST;
613}
614
94f5b916
BVA		 615/**
616 * qla2x00_find_new_loop_id - scan through our port list and find a new usable loop ID
617 * @vha: adapter state pointer.
618 * @dev: port structure pointer.
619 *
620 * Returns:
621 * qla2x00 local function return status code.
622 *
623 * Context:
624 * Kernel context.
625 */
626static int qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
627{
628 int rval;
629 struct qla_hw_data *ha = vha->hw;
630 unsigned long flags = 0;
631
632 rval = QLA_SUCCESS;
633
634 spin_lock_irqsave(&ha->vport_slock, flags);
635
636 dev->loop_id = find_first_zero_bit(ha->loop_id_map, LOOPID_MAP_SIZE);
637 if (dev->loop_id >= LOOPID_MAP_SIZE ||
638 qla2x00_is_reserved_id(vha, dev->loop_id)) {
639 dev->loop_id = FC_NO_LOOP_ID;
640 rval = QLA_FUNCTION_FAILED;
641 } else {
642 set_bit(dev->loop_id, ha->loop_id_map);
643 }
644 spin_unlock_irqrestore(&ha->vport_slock, flags);
645
646 if (rval == QLA_SUCCESS)
647 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
648 "Assigning new loopid=%x, portid=%x.\n",
649 dev->loop_id, dev->d_id.b24);
650 else
651 ql_log(ql_log_warn, dev->vha, 0x2087,
652 "No loop_id's available, portid=%x.\n",
653 dev->d_id.b24);
654
655 return rval;
656}
657
ef1eb688
BVA		 658void qla2x00_clear_loop_id(fc_port_t *fcport)
659{
660 struct qla_hw_data *ha = fcport->vha->hw;
661
662 if (fcport->loop_id == FC_NO_LOOP_ID ||
663 qla2x00_is_reserved_id(fcport->vha, fcport->loop_id))
664 return;
665
666 clear_bit(fcport->loop_id, ha->loop_id_map);
667 fcport->loop_id = FC_NO_LOOP_ID;
668}
669
726b8548
QT		 670static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
671 struct event_arg *ea)
672{
673 fc_port_t *fcport, *conflict_fcport;
674 struct get_name_list_extended *e;
675 u16 i, n, found = 0, loop_id;
676 port_id_t id;
677 u64 wwn;
a4239945
QT		 678 u16 data[2];
679 u8 current_login_state;
726b8548
QT		 680
681 fcport = ea->fcport;
f352eeb7
QT		 682 ql_dbg(ql_dbg_disc, vha, 0xffff,
683 "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d\n",
684 __func__, fcport->port_name, fcport->disc_state,
685 fcport->fw_login_state, ea->rc,
686 fcport->login_gen, fcport->last_login_gen,
687 fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id);
726b8548 688
a4239945
QT		 689 if (fcport->disc_state == DSC_DELETE_PEND)
690 return;
691
726b8548
QT		 692 if (ea->rc) { /* rval */
693 if (fcport->login_retry == 0) {
83548fe2
QT		 694 ql_dbg(ql_dbg_disc, vha, 0x20de,
695 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
696 fcport->port_name, fcport->login_retry);
726b8548
QT		 697 }
698 return;
699 }
700
701 if (fcport->last_rscn_gen != fcport->rscn_gen) {
d4f7a16a 702 qla_rscn_replay(fcport);
861d483d 703 qlt_schedule_sess_for_deletion(fcport);
726b8548
QT		 704 return;
705 } else if (fcport->last_login_gen != fcport->login_gen) {
83548fe2 706 ql_dbg(ql_dbg_disc, vha, 0x20e0,
f352eeb7
QT		 707 "%s %8phC login gen changed\n",
708 __func__, fcport->port_name);
726b8548
QT		 709 return;
710 }
711
712 n = ea->data[0] / sizeof(struct get_name_list_extended);
713
83548fe2 714 ql_dbg(ql_dbg_disc, vha, 0x20e1,
726b8548
QT		 715 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
716 __func__, __LINE__, fcport->port_name, n,
717 fcport->d_id.b.domain, fcport->d_id.b.area,
718 fcport->d_id.b.al_pa, fcport->loop_id);
719
720 for (i = 0; i < n; i++) {
721 e = &vha->gnl.l[i];
722 wwn = wwn_to_u64(e->port_name);
48acad09
QT		 723 id.b.domain = e->port_id[2];
724 id.b.area = e->port_id[1];
725 id.b.al_pa = e->port_id[0];
726 id.b.rsvd_1 = 0;
726b8548
QT		 727
728 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
729 continue;
730
48acad09
QT		 731 if (IS_SW_RESV_ADDR(id))
732 continue;
733
726b8548 734 found = 1;
726b8548
QT		 735
736 loop_id = le16_to_cpu(e->nport_handle);
737 loop_id = (loop_id & 0x7fff);
8777e431
QT		 738 if (fcport->fc4f_nvme)
739 current_login_state = e->current_login_state >> 4;
740 else
741 current_login_state = e->current_login_state & 0xf;
742
726b8548 743
83548fe2 744 ql_dbg(ql_dbg_disc, vha, 0x20e2,
8777e431 745 "%s found %8phC CLS [%x|%x] nvme %d ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n",
83548fe2
QT		 746 __func__, fcport->port_name,
747 e->current_login_state, fcport->fw_login_state,
8777e431 748 fcport->fc4f_nvme, id.b.domain, id.b.area, id.b.al_pa,
83548fe2
QT		 749 fcport->d_id.b.domain, fcport->d_id.b.area,
750 fcport->d_id.b.al_pa, loop_id, fcport->loop_id);
726b8548 751
48acad09
QT		 752 switch (fcport->disc_state) {
753 case DSC_DELETE_PEND:
754 case DSC_DELETED:
755 break;
756 default:
8777e431
QT		 757 if ((id.b24 != fcport->d_id.b24 &&
758 fcport->d_id.b24) ||
759 (fcport->loop_id != FC_NO_LOOP_ID &&
760 fcport->loop_id != loop_id)) {
761 ql_dbg(ql_dbg_disc, vha, 0x20e3,
762 "%s %d %8phC post del sess\n",
763 __func__, __LINE__, fcport->port_name);
48acad09
QT		 764 qlt_schedule_sess_for_deletion(fcport);
765 return;
766 }
767 break;
726b8548
QT		 768 }
769
770 fcport->loop_id = loop_id;
771
772 wwn = wwn_to_u64(fcport->port_name);
773 qlt_find_sess_invalidate_other(vha, wwn,
774 id, loop_id, &conflict_fcport);
775
776 if (conflict_fcport) {
777 /*
778 * Another share fcport share the same loop_id &
779 * nport id. Conflict fcport needs to finish
780 * cleanup before this fcport can proceed to login.
781 */
782 conflict_fcport->conflict = fcport;
783 fcport->login_pause = 1;
784 }
785
48acad09
QT		 786 switch (vha->hw->current_topology) {
787 default:
788 switch (current_login_state) {
789 case DSC_LS_PRLI_COMP:
790 ql_dbg(ql_dbg_disc + ql_dbg_verbose,
791 vha, 0x20e4, "%s %d %8phC post gpdb\n",
792 __func__, __LINE__, fcport->port_name);
a4239945 793
48acad09
QT		 794 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
795 fcport->port_type = FCT_INITIATOR;
796 else
797 fcport->port_type = FCT_TARGET;
798 data[0] = data[1] = 0;
799 qla2x00_post_async_adisc_work(vha, fcport,
800 data);
801 break;
802 case DSC_LS_PORT_UNAVAIL:
803 default:
ec322937
HM		 804 if (fcport->loop_id == FC_NO_LOOP_ID) {
805 qla2x00_find_new_loop_id(vha, fcport);
806 fcport->fw_login_state =
807 DSC_LS_PORT_UNAVAIL;
808 }
809 ql_dbg(ql_dbg_disc, vha, 0x20e5,
810 "%s %d %8phC\n", __func__, __LINE__,
811 fcport->port_name);
48acad09
QT		 812 qla24xx_fcport_handle_login(vha, fcport);
813 break;
726b8548 814 }
726b8548 815 break;
48acad09 816 case ISP_CFG_N:
8777e431
QT		 817 fcport->fw_login_state = current_login_state;
818 fcport->d_id = id;
48acad09
QT		 819 switch (current_login_state) {
820 case DSC_LS_PRLI_COMP:
821 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
822 fcport->port_type = FCT_INITIATOR;
823 else
824 fcport->port_type = FCT_TARGET;
825
826 data[0] = data[1] = 0;
827 qla2x00_post_async_adisc_work(vha, fcport,
828 data);
829 break;
830 case DSC_LS_PLOGI_COMP:
831 if (fcport_is_bigger(fcport)) {
832 /* local adapter is smaller */
833 if (fcport->loop_id != FC_NO_LOOP_ID)
834 qla2x00_clear_loop_id(fcport);
835
836 fcport->loop_id = loop_id;
837 qla24xx_fcport_handle_login(vha,
838 fcport);
839 break;
840 }
50435d42 841 /* fall through */
48acad09
QT		 842 default:
843 if (fcport_is_smaller(fcport)) {
844 /* local adapter is bigger */
845 if (fcport->loop_id != FC_NO_LOOP_ID)
846 qla2x00_clear_loop_id(fcport);
847
848 fcport->loop_id = loop_id;
849 qla24xx_fcport_handle_login(vha,
850 fcport);
851 }
852 break;
853 }
854 break;
855 } /* switch (ha->current_topology) */
726b8548
QT		 856 }
857
858 if (!found) {
48acad09
QT		 859 switch (vha->hw->current_topology) {
860 case ISP_CFG_F:
861 case ISP_CFG_FL:
862 for (i = 0; i < n; i++) {
863 e = &vha->gnl.l[i];
864 id.b.domain = e->port_id[0];
865 id.b.area = e->port_id[1];
866 id.b.al_pa = e->port_id[2];
867 id.b.rsvd_1 = 0;
868 loop_id = le16_to_cpu(e->nport_handle);
869
870 if (fcport->d_id.b24 == id.b24) {
871 conflict_fcport =
872 qla2x00_find_fcport_by_wwpn(vha,
873 e->port_name, 0);
72f02ba6
LT		 874 if (conflict_fcport) {
875 ql_dbg(ql_dbg_disc + ql_dbg_verbose,
876 vha, 0x20e5,
877 "%s %d %8phC post del sess\n",
878 __func__, __LINE__,
879 conflict_fcport->port_name);
880 qlt_schedule_sess_for_deletion
881 (conflict_fcport);
882 }
36eb8ff6 883 }
48acad09
QT		 884 /*
885 * FW already picked this loop id for
886 * another fcport
887 */
888 if (fcport->loop_id == loop_id)
889 fcport->loop_id = FC_NO_LOOP_ID;
726b8548 890 }
48acad09
QT		 891 qla24xx_fcport_handle_login(vha, fcport);
892 break;
893 case ISP_CFG_N:
8777e431
QT		 894 fcport->disc_state = DSC_DELETED;
895 if (time_after_eq(jiffies, fcport->dm_login_expire)) {
896 if (fcport->n2n_link_reset_cnt < 2) {
897 fcport->n2n_link_reset_cnt++;
898 /*
899 * remote port is not sending PLOGI.
900 * Reset link to kick start his state
901 * machine
902 */
903 set_bit(N2N_LINK_RESET,
904 &vha->dpc_flags);
905 } else {
906 if (fcport->n2n_chip_reset < 1) {
907 ql_log(ql_log_info, vha, 0x705d,
908 "Chip reset to bring laser down");
909 set_bit(ISP_ABORT_NEEDED,
910 &vha->dpc_flags);
911 fcport->n2n_chip_reset++;
912 } else {
913 ql_log(ql_log_info, vha, 0x705d,
914 "Remote port %8ph is not coming back\n",
915 fcport->port_name);
916 fcport->scan_state = 0;
917 }
918 }
919 qla2xxx_wake_dpc(vha);
920 } else {
921 /*
922 * report port suppose to do PLOGI. Give him
923 * more time. FW will catch it.
924 */
925 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
926 }
48acad09
QT		 927 break;
928 default:
929 break;
726b8548 930 }
726b8548
QT		 931 }
932} /* gnl_event */
933
934static void
25ff6af1 935qla24xx_async_gnl_sp_done(void *s, int res)
726b8548 936{
25ff6af1
JC		 937 struct srb *sp = s;
938 struct scsi_qla_host *vha = sp->vha;
726b8548
QT		 939 unsigned long flags;
940 struct fc_port *fcport = NULL, *tf;
941 u16 i, n = 0, loop_id;
942 struct event_arg ea;
943 struct get_name_list_extended *e;
944 u64 wwn;
945 struct list_head h;
a4239945 946 bool found = false;
726b8548 947
83548fe2 948 ql_dbg(ql_dbg_disc, vha, 0x20e7,
726b8548
QT		 949 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
950 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
951 sp->u.iocb_cmd.u.mbx.in_mb[2]);
952
ef801f07
HM		 953 if (res == QLA_FUNCTION_TIMEOUT)
954 return;
955
0aca7784 956 sp->fcport->flags &= ~(FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE);
726b8548
QT		 957 memset(&ea, 0, sizeof(ea));
958 ea.sp = sp;
959 ea.rc = res;
960 ea.event = FCME_GNL_DONE;
961
962 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
963 sizeof(struct get_name_list_extended)) {
964 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
965 sizeof(struct get_name_list_extended);
966 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
967 }
968
969 for (i = 0; i < n; i++) {
970 e = &vha->gnl.l[i];
971 loop_id = le16_to_cpu(e->nport_handle);
972 /* mask out reserve bit */
973 loop_id = (loop_id & 0x7fff);
974 set_bit(loop_id, vha->hw->loop_id_map);
975 wwn = wwn_to_u64(e->port_name);
976
83548fe2 977 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20e8,
726b8548
QT		 978 "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n",
979 __func__, (void *)&wwn, e->port_id[2], e->port_id[1],
980 e->port_id[0], e->current_login_state, e->last_login_state,
981 (loop_id & 0x7fff));
982 }
983
0aca7784 984 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 985
986 INIT_LIST_HEAD(&h);
987 fcport = tf = NULL;
988 if (!list_empty(&vha->gnl.fcports))
989 list_splice_init(&vha->gnl.fcports, &h);
0aca7784 990 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 991
992 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
993 list_del_init(&fcport->gnl_entry);
0aca7784 994 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
6d674927 995 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
0aca7784 996 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 997 ea.fcport = fcport;
998
999 qla2x00_fcport_event_handler(vha, &ea);
1000 }
1001
a4239945
QT		 1002 /* create new fcport if fw has knowledge of new sessions */
1003 for (i = 0; i < n; i++) {
1004 port_id_t id;
1005 u64 wwnn;
1006
1007 e = &vha->gnl.l[i];
1008 wwn = wwn_to_u64(e->port_name);
1009
1010 found = false;
1011 list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) {
1012 if (!memcmp((u8 *)&wwn, fcport->port_name,
1013 WWN_SIZE)) {
1014 found = true;
1015 break;
1016 }
1017 }
1018
cf055fb0 1019 id.b.domain = e->port_id[2];
a4239945 1020 id.b.area = e->port_id[1];
cf055fb0 1021 id.b.al_pa = e->port_id[0];
a4239945
QT		 1022 id.b.rsvd_1 = 0;
1023
1024 if (!found && wwn && !IS_SW_RESV_ADDR(id)) {
1025 ql_dbg(ql_dbg_disc, vha, 0x2065,
cf055fb0
QT		 1026 "%s %d %8phC %06x post new sess\n",
1027 __func__, __LINE__, (u8 *)&wwn, id.b24);
a4239945
QT		 1028 wwnn = wwn_to_u64(e->node_name);
1029 qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn,
1030 (u8 *)&wwnn, NULL, FC4_TYPE_UNKNOWN);
1031 }
1032 }
1033
0aca7784
QT		 1034 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1035 vha->gnl.sent = 0;
726b8548
QT		 1036 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1037
25ff6af1 1038 sp->free(sp);
726b8548
QT		 1039}
1040
1041int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
1042{
1043 srb_t *sp;
1044 struct srb_iocb *mbx;
1045 int rval = QLA_FUNCTION_FAILED;
1046 unsigned long flags;
1047 u16 *mb;
1048
3dbec59b
QT		 1049 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
1050 return rval;
726b8548 1051
83548fe2 1052 ql_dbg(ql_dbg_disc, vha, 0x20d9,
726b8548
QT		 1053 "Async-gnlist WWPN %8phC \n", fcport->port_name);
1054
0aca7784
QT		 1055 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1056 fcport->flags |= FCF_ASYNC_SENT;
726b8548
QT		 1057 fcport->disc_state = DSC_GNL;
1058 fcport->last_rscn_gen = fcport->rscn_gen;
1059 fcport->last_login_gen = fcport->login_gen;
1060
1061 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
0aca7784
QT		 1062 if (vha->gnl.sent) {
1063 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1064 return QLA_SUCCESS;
1065 }
1066 vha->gnl.sent = 1;
1067 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 1068
1069 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1070 if (!sp)
1071 goto done;
3dbec59b 1072
726b8548
QT		 1073 sp->type = SRB_MB_IOCB;
1074 sp->name = "gnlist";
1075 sp->gen1 = fcport->rscn_gen;
1076 sp->gen2 = fcport->login_gen;
1077
e74e7d95
BH		 1078 mbx = &sp->u.iocb_cmd;
1079 mbx->timeout = qla2x00_async_iocb_timeout;
726b8548
QT		 1080 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
1081
1082 mb = sp->u.iocb_cmd.u.mbx.out_mb;
1083 mb[0] = MBC_PORT_NODE_NAME_LIST;
1084 mb[1] = BIT_2 | BIT_3;
1085 mb[2] = MSW(vha->gnl.ldma);
1086 mb[3] = LSW(vha->gnl.ldma);
1087 mb[6] = MSW(MSD(vha->gnl.ldma));
1088 mb[7] = LSW(MSD(vha->gnl.ldma));
1089 mb[8] = vha->gnl.size;
1090 mb[9] = vha->vp_idx;
1091
726b8548
QT		 1092 sp->done = qla24xx_async_gnl_sp_done;
1093
83548fe2
QT		 1094 ql_dbg(ql_dbg_disc, vha, 0x20da,
1095 "Async-%s - OUT WWPN %8phC hndl %x\n",
1096 sp->name, fcport->port_name, sp->handle);
726b8548 1097
f233e8c0
BK		 1098 rval = qla2x00_start_sp(sp);
1099 if (rval != QLA_SUCCESS)
1100 goto done_free_sp;
1101
726b8548
QT		 1102 return rval;
1103
1104done_free_sp:
25ff6af1 1105 sp->free(sp);
726b8548 1106 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 1107done:
726b8548
QT		 1108 return rval;
1109}
1110
1111int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
1112{
1113 struct qla_work_evt *e;
1114
1115 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
1116 if (!e)
1117 return QLA_FUNCTION_FAILED;
1118
1119 e->u.fcport.fcport = fcport;
6d674927 1120 fcport->flags |= FCF_ASYNC_ACTIVE;
726b8548
QT		 1121 return qla2x00_post_work(vha, e);
1122}
1123
1124static
25ff6af1 1125void qla24xx_async_gpdb_sp_done(void *s, int res)
726b8548 1126{
25ff6af1
JC		 1127 struct srb *sp = s;
1128 struct scsi_qla_host *vha = sp->vha;
726b8548 1129 struct qla_hw_data *ha = vha->hw;
726b8548
QT		 1130 fc_port_t *fcport = sp->fcport;
1131 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
726b8548
QT		 1132 struct event_arg ea;
1133
83548fe2 1134 ql_dbg(ql_dbg_disc, vha, 0x20db,
726b8548
QT		 1135 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
1136 sp->name, res, fcport->port_name, mb[1], mb[2]);
1137
bcc71cc3
GM		 1138 if (res == QLA_FUNCTION_TIMEOUT) {
1139 dma_pool_free(sp->vha->hw->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
1140 sp->u.iocb_cmd.u.mbx.in_dma);
1141 return;
1142 }
1143
ef801f07 1144 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
726b8548
QT		 1145 memset(&ea, 0, sizeof(ea));
1146 ea.event = FCME_GPDB_DONE;
726b8548
QT		 1147 ea.fcport = fcport;
1148 ea.sp = sp;
1149
1150 qla2x00_fcport_event_handler(vha, &ea);
1151
1152 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
1153 sp->u.iocb_cmd.u.mbx.in_dma);
1154
25ff6af1 1155 sp->free(sp);
726b8548
QT		 1156}
1157
a5d42f4c
DG		 1158static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport)
1159{
1160 struct qla_work_evt *e;
1161
1162 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI);
1163 if (!e)
1164 return QLA_FUNCTION_FAILED;
1165
1166 e->u.fcport.fcport = fcport;
1167
1168 return qla2x00_post_work(vha, e);
1169}
1170
1171static void
1172qla2x00_async_prli_sp_done(void *ptr, int res)
1173{
1174 srb_t *sp = ptr;
1175 struct scsi_qla_host *vha = sp->vha;
1176 struct srb_iocb *lio = &sp->u.iocb_cmd;
1177 struct event_arg ea;
1178
1179 ql_dbg(ql_dbg_disc, vha, 0x2129,
1180 "%s %8phC res %d \n", __func__,
1181 sp->fcport->port_name, res);
1182
1183 sp->fcport->flags &= ~FCF_ASYNC_SENT;
1184
1185 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
1186 memset(&ea, 0, sizeof(ea));
1187 ea.event = FCME_PRLI_DONE;
1188 ea.fcport = sp->fcport;
1189 ea.data[0] = lio->u.logio.data[0];
1190 ea.data[1] = lio->u.logio.data[1];
1191 ea.iop[0] = lio->u.logio.iop[0];
1192 ea.iop[1] = lio->u.logio.iop[1];
1193 ea.sp = sp;
1194
1195 qla2x00_fcport_event_handler(vha, &ea);
1196 }
1197
1198 sp->free(sp);
1199}
1200
1201int
1202qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport)
1203{
1204 srb_t *sp;
1205 struct srb_iocb *lio;
1206 int rval = QLA_FUNCTION_FAILED;
1207
1208 if (!vha->flags.online)
1209 return rval;
1210
1211 if (fcport->fw_login_state == DSC_LS_PLOGI_PEND ||
a5d42f4c
DG		 1212 fcport->fw_login_state == DSC_LS_PRLI_PEND)
1213 return rval;
1214
1215 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1216 if (!sp)
1217 return rval;
1218
1219 fcport->flags |= FCF_ASYNC_SENT;
1220 fcport->logout_completed = 0;
1221
1222 sp->type = SRB_PRLI_CMD;
1223 sp->name = "prli";
a5d42f4c
DG		 1224
1225 lio = &sp->u.iocb_cmd;
1226 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 1227 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
1228
a5d42f4c
DG		 1229 sp->done = qla2x00_async_prli_sp_done;
1230 lio->u.logio.flags = 0;
1231
1232 if (fcport->fc4f_nvme)
1233 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI;
1234
f233e8c0
BK		 1235 ql_dbg(ql_dbg_disc, vha, 0x211b,
1236 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d %s.\n",
1237 fcport->port_name, sp->handle, fcport->loop_id, fcport->d_id.b24,
1238 fcport->login_retry, fcport->fc4f_nvme ? "nvme" : "fc");
1239
a5d42f4c
DG		 1240 rval = qla2x00_start_sp(sp);
1241 if (rval != QLA_SUCCESS) {
a5d42f4c
DG		 1242 fcport->flags |= FCF_LOGIN_NEEDED;
1243 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1244 goto done_free_sp;
1245 }
1246
a5d42f4c
DG		 1247 return rval;
1248
1249done_free_sp:
1250 sp->free(sp);
1251 fcport->flags &= ~FCF_ASYNC_SENT;
1252 return rval;
1253}
1254
a07fc0a4 1255int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
726b8548
QT		 1256{
1257 struct qla_work_evt *e;
1258
1259 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
1260 if (!e)
1261 return QLA_FUNCTION_FAILED;
1262
1263 e->u.fcport.fcport = fcport;
1264 e->u.fcport.opt = opt;
6d674927 1265 fcport->flags |= FCF_ASYNC_ACTIVE;
726b8548
QT		 1266 return qla2x00_post_work(vha, e);
1267}
1268
1269int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
1270{
1271 srb_t *sp;
1272 struct srb_iocb *mbx;
1273 int rval = QLA_FUNCTION_FAILED;
1274 u16 *mb;
1275 dma_addr_t pd_dma;
1276 struct port_database_24xx *pd;
1277 struct qla_hw_data *ha = vha->hw;
1278
8b5292bc
QT		 1279 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) ||
1280 fcport->loop_id == FC_NO_LOOP_ID) {
1281 ql_log(ql_log_warn, vha, 0xffff,
1282 "%s: %8phC - not sending command.\n",
1283 __func__, fcport->port_name);
3dbec59b 1284 return rval;
8b5292bc 1285 }
726b8548 1286
726b8548
QT		 1287 fcport->disc_state = DSC_GPDB;
1288
1289 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1290 if (!sp)
1291 goto done;
1292
3dbec59b 1293 fcport->flags |= FCF_ASYNC_SENT;
e0824e69
JC		 1294 sp->type = SRB_MB_IOCB;
1295 sp->name = "gpdb";
1296 sp->gen1 = fcport->rscn_gen;
1297 sp->gen2 = fcport->login_gen;
e74e7d95
BH		 1298
1299 mbx = &sp->u.iocb_cmd;
1300 mbx->timeout = qla2x00_async_iocb_timeout;
e0824e69
JC		 1301 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
1302
08eb7f45 1303 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
726b8548 1304 if (pd == NULL) {
83548fe2
QT		 1305 ql_log(ql_log_warn, vha, 0xd043,
1306 "Failed to allocate port database structure.\n");
726b8548
QT		 1307 goto done_free_sp;
1308 }
726b8548 1309
726b8548
QT		 1310 mb = sp->u.iocb_cmd.u.mbx.out_mb;
1311 mb[0] = MBC_GET_PORT_DATABASE;
1312 mb[1] = fcport->loop_id;
1313 mb[2] = MSW(pd_dma);
1314 mb[3] = LSW(pd_dma);
1315 mb[6] = MSW(MSD(pd_dma));
1316 mb[7] = LSW(MSD(pd_dma));
1317 mb[9] = vha->vp_idx;
1318 mb[10] = opt;
1319
726b8548
QT		 1320 mbx->u.mbx.in = (void *)pd;
1321 mbx->u.mbx.in_dma = pd_dma;
1322
1323 sp->done = qla24xx_async_gpdb_sp_done;
1324
83548fe2
QT		 1325 ql_dbg(ql_dbg_disc, vha, 0x20dc,
1326 "Async-%s %8phC hndl %x opt %x\n",
1327 sp->name, fcport->port_name, sp->handle, opt);
726b8548 1328
9fe278f4
GM		 1329 rval = qla2x00_start_sp(sp);
1330 if (rval != QLA_SUCCESS)
1331 goto done_free_sp;
726b8548
QT		 1332 return rval;
1333
1334done_free_sp:
1335 if (pd)
1336 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1337
25ff6af1 1338 sp->free(sp);
726b8548 1339 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 1340done:
726b8548 1341 qla24xx_post_gpdb_work(vha, fcport, opt);
5ff1d584
AV		 1342 return rval;
1343}
1344
726b8548 1345static
a4239945 1346void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1347{
726b8548
QT		 1348 unsigned long flags;
1349
726b8548 1350 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
f13515ac 1351 ea->fcport->login_gen++;
726b8548
QT		 1352 ea->fcport->deleted = 0;
1353 ea->fcport->logout_on_delete = 1;
1354
1355 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
1356 vha->fcport_count++;
1357 ea->fcport->login_succ = 1;
1358
0aca7784 1359 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
cd4ed6b4 1360 qla24xx_sched_upd_fcport(ea->fcport);
0aca7784 1361 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
414d9ff3
QT		 1362 } else if (ea->fcport->login_succ) {
1363 /*
1364 * We have an existing session. A late RSCN delivery
1365 * must have triggered the session to be re-validate.
a4239945 1366 * Session is still valid.
414d9ff3 1367 */
5ef696aa
QT		 1368 ql_dbg(ql_dbg_disc, vha, 0x20d6,
1369 "%s %d %8phC session revalidate success\n",
a4239945 1370 __func__, __LINE__, ea->fcport->port_name);
8a7eac2f 1371 ea->fcport->disc_state = DSC_LOGIN_COMPLETE;
726b8548
QT		 1372 }
1373 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
a4239945
QT		 1374}
1375
1376static
1377void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
1378{
a4239945
QT		 1379 fc_port_t *fcport = ea->fcport;
1380 struct port_database_24xx *pd;
1381 struct srb *sp = ea->sp;
2b5b9647 1382 uint8_t ls;
a4239945
QT		 1383
1384 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
1385
1386 fcport->flags &= ~FCF_ASYNC_SENT;
1387
1388 ql_dbg(ql_dbg_disc, vha, 0x20d2,
8777e431
QT		 1389 "%s %8phC DS %d LS %d nvme %x rc %d\n", __func__, fcport->port_name,
1390 fcport->disc_state, pd->current_login_state, fcport->fc4f_nvme,
1391 ea->rc);
a4239945
QT		 1392
1393 if (fcport->disc_state == DSC_DELETE_PEND)
1394 return;
726b8548 1395
2b5b9647
DT		 1396 if (fcport->fc4f_nvme)
1397 ls = pd->current_login_state >> 4;
1398 else
1399 ls = pd->current_login_state & 0xf;
1400
d4f7a16a
HM		 1401 if (ea->sp->gen2 != fcport->login_gen) {
1402 /* target side must have changed it. */
1403
1404 ql_dbg(ql_dbg_disc, vha, 0x20d3,
1405 "%s %8phC generation changed\n",
1406 __func__, fcport->port_name);
1407 return;
1408 } else if (ea->sp->gen1 != fcport->rscn_gen) {
1409 qla_rscn_replay(fcport);
861d483d 1410 qlt_schedule_sess_for_deletion(fcport);
d4f7a16a
HM		 1411 return;
1412 }
1413
2b5b9647 1414 switch (ls) {
a4239945
QT		 1415 case PDS_PRLI_COMPLETE:
1416 __qla24xx_parse_gpdb(vha, fcport, pd);
1417 break;
1418 case PDS_PLOGI_PENDING:
1419 case PDS_PLOGI_COMPLETE:
1420 case PDS_PRLI_PENDING:
1421 case PDS_PRLI2_PENDING:
8fde6977
QT		 1422 /* Set discovery state back to GNL to Relogin attempt */
1423 if (qla_dual_mode_enabled(vha) ||
1424 qla_ini_mode_enabled(vha)) {
1425 fcport->disc_state = DSC_GNL;
1426 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1427 }
a4239945
QT		 1428 return;
1429 case PDS_LOGO_PENDING:
1430 case PDS_PORT_UNAVAILABLE:
1431 default:
1432 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n",
1433 __func__, __LINE__, fcport->port_name);
d8630bb9 1434 qlt_schedule_sess_for_deletion(fcport);
a4239945
QT		 1435 return;
1436 }
1437 __qla24xx_handle_gpdb_event(vha, ea);
1438} /* gpdb event */
9cd883f0
QT		 1439
1440static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1441{
1442 u8 login = 0;
040036bb 1443 int rc;
9cd883f0
QT		 1444
1445 if (qla_tgt_mode_enabled(vha))
1446 return;
1447
1448 if (qla_dual_mode_enabled(vha)) {
1449 if (N2N_TOPO(vha->hw)) {
1450 u64 mywwn, wwn;
1451
1452 mywwn = wwn_to_u64(vha->port_name);
1453 wwn = wwn_to_u64(fcport->port_name);
1454 if (mywwn > wwn)
1455 login = 1;
1456 else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1457 && time_after_eq(jiffies,
1458 fcport->plogi_nack_done_deadline))
1459 login = 1;
1460 } else {
1461 login = 1;
1462 }
1463 } else {
1464 /* initiator mode */
1465 login = 1;
1466 }
1467
0754d5e0
QT		 1468 if (login && fcport->login_retry) {
1469 fcport->login_retry--;
040036bb
QT		 1470 if (fcport->loop_id == FC_NO_LOOP_ID) {
1471 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
1472 rc = qla2x00_find_new_loop_id(vha, fcport);
1473 if (rc) {
1474 ql_dbg(ql_dbg_disc, vha, 0x20e6,
1475 "%s %d %8phC post del sess - out of loopid\n",
1476 __func__, __LINE__, fcport->port_name);
1477 fcport->scan_state = 0;
94cff6e1 1478 qlt_schedule_sess_for_deletion(fcport);
040036bb
QT		 1479 return;
1480 }
1481 }
9cd883f0
QT		 1482 ql_dbg(ql_dbg_disc, vha, 0x20bf,
1483 "%s %d %8phC post login\n",
1484 __func__, __LINE__, fcport->port_name);
9cd883f0
QT		 1485 qla2x00_post_async_login_work(vha, fcport, NULL);
1486 }
1487}
1488
726b8548
QT		 1489int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1490{
f13515ac 1491 u16 data[2];
a4239945 1492 u64 wwn;
cd4ed6b4 1493 u16 sec;
726b8548 1494
0754d5e0
QT		 1495 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20d8,
1496 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d lid %d scan %d\n",
726b8548
QT		 1497 __func__, fcport->port_name, fcport->disc_state,
1498 fcport->fw_login_state, fcport->login_pause, fcport->flags,
1499 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
0754d5e0 1500 fcport->login_gen, fcport->loop_id, fcport->scan_state);
726b8548 1501
a4239945
QT		 1502 if (fcport->scan_state != QLA_FCPORT_FOUND)
1503 return 0;
726b8548 1504
07ea4b60
HR		 1505 if ((fcport->loop_id != FC_NO_LOOP_ID) &&
1506 ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
1507 (fcport->fw_login_state == DSC_LS_PRLI_PEND)))
726b8548
QT		 1508 return 0;
1509
5b33469a 1510 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
9cd883f0
QT		 1511 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1512 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5b33469a 1513 return 0;
9cd883f0 1514 }
5b33469a
QT		 1515 }
1516
726b8548
QT		 1517 /* for pure Target Mode. Login will not be initiated */
1518 if (vha->host->active_mode == MODE_TARGET)
1519 return 0;
1520
1521 if (fcport->flags & FCF_ASYNC_SENT) {
1522 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1523 return 0;
1524 }
1525
1526 switch (fcport->disc_state) {
1527 case DSC_DELETED:
a4239945 1528 wwn = wwn_to_u64(fcport->node_name);
8777e431
QT		 1529 switch (vha->hw->current_topology) {
1530 case ISP_CFG_N:
1531 if (fcport_is_smaller(fcport)) {
1532 /* this adapter is bigger */
1533 if (fcport->login_retry) {
1534 if (fcport->loop_id == FC_NO_LOOP_ID) {
1535 qla2x00_find_new_loop_id(vha,
1536 fcport);
1537 fcport->fw_login_state =
1538 DSC_LS_PORT_UNAVAIL;
1539 }
1540 fcport->login_retry--;
1541 qla_post_els_plogi_work(vha, fcport);
1542 } else {
1543 ql_log(ql_log_info, vha, 0x705d,
1544 "Unable to reach remote port %8phC",
1545 fcport->port_name);
1546 }
1547 } else {
1548 qla24xx_post_gnl_work(vha, fcport);
1549 }
1550 break;
1551 default:
1552 if (wwn == 0) {
1553 ql_dbg(ql_dbg_disc, vha, 0xffff,
1554 "%s %d %8phC post GNNID\n",
1555 __func__, __LINE__, fcport->port_name);
1556 qla24xx_post_gnnid_work(vha, fcport);
1557 } else if (fcport->loop_id == FC_NO_LOOP_ID) {
1558 ql_dbg(ql_dbg_disc, vha, 0x20bd,
1559 "%s %d %8phC post gnl\n",
1560 __func__, __LINE__, fcport->port_name);
1561 qla24xx_post_gnl_work(vha, fcport);
1562 } else {
1563 qla_chk_n2n_b4_login(vha, fcport);
1564 }
1565 break;
726b8548
QT		 1566 }
1567 break;
1568
1569 case DSC_GNL:
8777e431
QT		 1570 switch (vha->hw->current_topology) {
1571 case ISP_CFG_N:
1572 if ((fcport->current_login_state & 0xf) == 0x6) {
1573 ql_dbg(ql_dbg_disc, vha, 0x2118,
1574 "%s %d %8phC post GPDB work\n",
1575 __func__, __LINE__, fcport->port_name);
1576 fcport->chip_reset =
1577 vha->hw->base_qpair->chip_reset;
1578 qla24xx_post_gpdb_work(vha, fcport, 0);
1579 } else {
1580 ql_dbg(ql_dbg_disc, vha, 0x2118,
1581 "%s %d %8phC post NVMe PRLI\n",
1582 __func__, __LINE__, fcport->port_name);
1583 qla24xx_post_prli_work(vha, fcport);
1584 }
1585 break;
1586 default:
1587 if (fcport->login_pause) {
1588 fcport->last_rscn_gen = fcport->rscn_gen;
1589 fcport->last_login_gen = fcport->login_gen;
1590 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1591 break;
1592 }
1593 qla_chk_n2n_b4_login(vha, fcport);
726b8548
QT		 1594 break;
1595 }
726b8548
QT		 1596 break;
1597
1598 case DSC_LOGIN_FAILED:
9cd883f0
QT		 1599 if (N2N_TOPO(vha->hw))
1600 qla_chk_n2n_b4_login(vha, fcport);
1601 else
d4f7a16a 1602 qlt_schedule_sess_for_deletion(fcport);
726b8548
QT		 1603 break;
1604
1605 case DSC_LOGIN_COMPLETE:
1606 /* recheck login state */
f13515ac
QT		 1607 data[0] = data[1] = 0;
1608 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548
QT		 1609 break;
1610
1cbc0efc
DT		 1611 case DSC_LOGIN_PEND:
1612 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1613 qla24xx_post_prli_work(vha, fcport);
1614 break;
1615
cd4ed6b4
QT		 1616 case DSC_UPD_FCPORT:
1617 sec = jiffies_to_msecs(jiffies -
1618 fcport->jiffies_at_registration)/1000;
1619 if (fcport->sec_since_registration < sec && sec &&
1620 !(sec % 60)) {
1621 fcport->sec_since_registration = sec;
1622 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
1623 "%s %8phC - Slow Rport registration(%d Sec)\n",
1624 __func__, fcport->port_name, sec);
1625 }
1626
1627 if (fcport->next_disc_state != DSC_DELETE_PEND)
1628 fcport->next_disc_state = DSC_ADISC;
1629 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1630 break;
1631
726b8548
QT		 1632 default:
1633 break;
1634 }
1635
1636 return 0;
1637}
1638
726b8548 1639int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
a4239945 1640 u8 *port_name, u8 *node_name, void *pla, u8 fc4_type)
726b8548
QT		 1641{
1642 struct qla_work_evt *e;
bd432bb5 1643
726b8548
QT		 1644 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
1645 if (!e)
1646 return QLA_FUNCTION_FAILED;
1647
1648 e->u.new_sess.id = *id;
1649 e->u.new_sess.pla = pla;
a4239945 1650 e->u.new_sess.fc4_type = fc4_type;
726b8548 1651 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
a4239945
QT		 1652 if (node_name)
1653 memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE);
726b8548
QT		 1654
1655 return qla2x00_post_work(vha, e);
1656}
1657
726b8548
QT		 1658static
1659void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
1660 struct event_arg *ea)
1661{
1662 fc_port_t *fcport = ea->fcport;
1663
83548fe2
QT		 1664 ql_dbg(ql_dbg_disc, vha, 0x2102,
1665 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
1666 __func__, fcport->port_name, fcport->disc_state,
1667 fcport->fw_login_state, fcport->login_pause,
1668 fcport->deleted, fcport->conflict,
1669 fcport->last_rscn_gen, fcport->rscn_gen,
1670 fcport->last_login_gen, fcport->login_gen,
1671 fcport->flags);
726b8548
QT		 1672
1673 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1674 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1675 return;
1676
5b33469a 1677 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
9cd883f0
QT		 1678 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1679 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5b33469a 1680 return;
9cd883f0 1681 }
5b33469a
QT		 1682 }
1683
726b8548 1684 if (fcport->last_rscn_gen != fcport->rscn_gen) {
9e744591 1685 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gnl\n",
726b8548 1686 __func__, __LINE__, fcport->port_name);
9e744591 1687 qla24xx_post_gnl_work(vha, fcport);
726b8548
QT		 1688 return;
1689 }
1690
1691 qla24xx_fcport_handle_login(vha, fcport);
1692}
1693
8777e431 1694
8f9a2148
BVA		 1695static void qla_handle_els_plogi_done(scsi_qla_host_t *vha,
1696 struct event_arg *ea)
8777e431
QT		 1697{
1698 ql_dbg(ql_dbg_disc, vha, 0x2118,
1699 "%s %d %8phC post PRLI\n",
1700 __func__, __LINE__, ea->fcport->port_name);
1701 qla24xx_post_prli_work(vha, ea->fcport);
1702}
1703
41dc529a 1704void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1705{
bee8b846 1706 fc_port_t *fcport;
726b8548
QT		 1707
1708 switch (ea->event) {
1709 case FCME_RELOGIN:
1710 if (test_bit(UNLOADING, &vha->dpc_flags))
1711 return;
5ff1d584 1712
726b8548
QT		 1713 qla24xx_handle_relogin_event(vha, ea);
1714 break;
1715 case FCME_RSCN:
1716 if (test_bit(UNLOADING, &vha->dpc_flags))
1717 return;
d4f7a16a
HM		 1718 {
1719 unsigned long flags;
bd432bb5 1720
bee8b846
QT		 1721 fcport = qla2x00_find_fcport_by_nportid
1722 (vha, &ea->id, 1);
cd4ed6b4 1723 if (fcport) {
cb873ba4 1724 fcport->scan_needed = 1;
cd4ed6b4
QT		 1725 fcport->rscn_gen++;
1726 }
bee8b846 1727
f352eeb7
QT		 1728 spin_lock_irqsave(&vha->work_lock, flags);
1729 if (vha->scan.scan_flags == 0) {
1730 ql_dbg(ql_dbg_disc, vha, 0xffff,
1731 "%s: schedule\n", __func__);
1732 vha->scan.scan_flags |= SF_QUEUED;
1733 schedule_delayed_work(&vha->scan.scan_work, 5);
41dc529a 1734 }
f352eeb7 1735 spin_unlock_irqrestore(&vha->work_lock, flags);
d4f7a16a 1736 }
726b8548 1737 break;
726b8548
QT		 1738 case FCME_GNL_DONE:
1739 qla24xx_handle_gnl_done_event(vha, ea);
1740 break;
1741 case FCME_GPSC_DONE:
a4239945 1742 qla24xx_handle_gpsc_event(vha, ea);
726b8548
QT		 1743 break;
1744 case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */
1745 qla24xx_handle_plogi_done_event(vha, ea);
1746 break;
a5d42f4c
DG		 1747 case FCME_PRLI_DONE:
1748 qla24xx_handle_prli_done_event(vha, ea);
1749 break;
726b8548
QT		 1750 case FCME_GPDB_DONE:
1751 qla24xx_handle_gpdb_event(vha, ea);
1752 break;
1753 case FCME_GPNID_DONE:
1754 qla24xx_handle_gpnid_event(vha, ea);
1755 break;
d3bae931
DG		 1756 case FCME_GFFID_DONE:
1757 qla24xx_handle_gffid_event(vha, ea);
1758 break;
f13515ac
QT		 1759 case FCME_ADISC_DONE:
1760 qla24xx_handle_adisc_event(vha, ea);
1761 break;
a4239945
QT		 1762 case FCME_GNNID_DONE:
1763 qla24xx_handle_gnnid_event(vha, ea);
1764 break;
1765 case FCME_GFPNID_DONE:
1766 qla24xx_handle_gfpnid_event(vha, ea);
1767 break;
8777e431
QT		 1768 case FCME_ELS_PLOGI_DONE:
1769 qla_handle_els_plogi_done(vha, ea);
1770 break;
726b8548
QT		 1771 default:
1772 BUG_ON(1);
1773 break;
1774 }
5ff1d584
AV		 1775}
1776
d4f7a16a
HM		 1777/*
1778 * RSCN(s) came in for this fcport, but the RSCN(s) was not able
1779 * to be consumed by the fcport
1780 */
1781void qla_rscn_replay(fc_port_t *fcport)
1782{
2703eaaf
BVA		 1783 struct event_arg ea;
1784
1785 switch (fcport->disc_state) {
1786 case DSC_DELETE_PEND:
1787 return;
1788 default:
1789 break;
1790 }
1791
1792 if (fcport->scan_needed) {
1793 memset(&ea, 0, sizeof(ea));
1794 ea.event = FCME_RSCN;
1795 ea.id = fcport->d_id;
1796 ea.id.b.rsvd_1 = RSCN_PORT_ADDR;
1797 qla2x00_fcport_event_handler(fcport->vha, &ea);
861d483d 1798 }
d4f7a16a
HM		 1799}
1800
3822263e 1801static void
faef62d1 1802qla2x00_tmf_iocb_timeout(void *data)
3822263e 1803{
25ff6af1 1804 srb_t *sp = data;
faef62d1 1805 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 1806
faef62d1
AB		 1807 tmf->u.tmf.comp_status = CS_TIMEOUT;
1808 complete(&tmf->u.tmf.comp);
1809}
9ba56b95 1810
faef62d1 1811static void
25ff6af1 1812qla2x00_tmf_sp_done(void *ptr, int res)
faef62d1 1813{
25ff6af1 1814 srb_t *sp = ptr;
faef62d1 1815 struct srb_iocb *tmf = &sp->u.iocb_cmd;
25ff6af1 1816
faef62d1 1817 complete(&tmf->u.tmf.comp);
3822263e
MI		 1818}
1819
1820int
faef62d1 1821qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 1822 uint32_t tag)
1823{
1824 struct scsi_qla_host *vha = fcport->vha;
faef62d1 1825 struct srb_iocb *tm_iocb;
3822263e 1826 srb_t *sp;
faef62d1 1827 int rval = QLA_FUNCTION_FAILED;
3822263e 1828
9ba56b95 1829 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 1830 if (!sp)
1831 goto done;
1832
faef62d1 1833 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 1834 sp->type = SRB_TM_CMD;
1835 sp->name = "tmf";
e74e7d95
BH		 1836
1837 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1838 init_completion(&tm_iocb->u.tmf.comp);
faef62d1 1839 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
e74e7d95 1840
faef62d1
AB		 1841 tm_iocb->u.tmf.flags = flags;
1842 tm_iocb->u.tmf.lun = lun;
1843 tm_iocb->u.tmf.data = tag;
1844 sp->done = qla2x00_tmf_sp_done;
3822263e 1845
7c3df132 1846 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 1847 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1848 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1849 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1 1850
9fe278f4
GM		 1851 rval = qla2x00_start_sp(sp);
1852 if (rval != QLA_SUCCESS)
1853 goto done_free_sp;
faef62d1
AB		 1854 wait_for_completion(&tm_iocb->u.tmf.comp);
1855
b4146c49 1856 rval = tm_iocb->u.tmf.data;
faef62d1 1857
b4146c49
AG		 1858 if (rval != QLA_SUCCESS) {
1859 ql_log(ql_log_warn, vha, 0x8030,
faef62d1
AB		 1860 "TM IOCB failed (%x).\n", rval);
1861 }
1862
1863 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1864 flags = tm_iocb->u.tmf.flags;
1865 lun = (uint16_t)tm_iocb->u.tmf.lun;
1866
1867 /* Issue Marker IOCB */
9eb9c6dc 1868 qla2x00_marker(vha, vha->hw->base_qpair,
92fff53b 1869 fcport->loop_id, lun,
faef62d1
AB		 1870 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1871 }
3822263e
MI		 1872
1873done_free_sp:
25ff6af1 1874 sp->free(sp);
388a4995 1875 fcport->flags &= ~FCF_ASYNC_SENT;
3822263e
MI		 1876done:
1877 return rval;
1878}
1879
4440e46d
AB		 1880int
1881qla24xx_async_abort_command(srb_t *sp)
1882{
1883 unsigned long flags = 0;
1884
1885 uint32_t handle;
1886 fc_port_t *fcport = sp->fcport;
585def9b 1887 struct qla_qpair *qpair = sp->qpair;
4440e46d 1888 struct scsi_qla_host *vha = fcport->vha;
585def9b 1889 struct req_que *req = qpair->req;
b027a5ac 1890
585def9b 1891 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
4440e46d
AB		 1892 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1893 if (req->outstanding_cmds[handle] == sp)
1894 break;
1895 }
585def9b
QT		 1896 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1897
4440e46d
AB		 1898 if (handle == req->num_outstanding_cmds) {
1899 /* Command not found. */
1900 return QLA_FUNCTION_FAILED;
1901 }
1902 if (sp->type == SRB_FXIOCB_DCMD)
1903 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1904 FXDISC_ABORT_IOCTL);
1905
f6145e86 1906 return qla24xx_async_abort_cmd(sp, true);
4440e46d
AB		 1907}
1908
a5d42f4c
DG		 1909static void
1910qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
1911{
1912 switch (ea->data[0]) {
1913 case MBS_COMMAND_COMPLETE:
1914 ql_dbg(ql_dbg_disc, vha, 0x2118,
1915 "%s %d %8phC post gpdb\n",
1916 __func__, __LINE__, ea->fcport->port_name);
1917
1918 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1919 ea->fcport->logout_on_delete = 1;
03aaa89f
DT		 1920 ea->fcport->nvme_prli_service_param = ea->iop[0];
1921 if (ea->iop[0] & NVME_PRLI_SP_FIRST_BURST)
1922 ea->fcport->nvme_first_burst_size =
1923 (ea->iop[1] & 0xffff) * 512;
1924 else
1925 ea->fcport->nvme_first_burst_size = 0;
a5d42f4c
DG		 1926 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1927 break;
1928 default:
1cbc0efc
DT		 1929 if ((ea->iop[0] == LSC_SCODE_ELS_REJECT) &&
1930 (ea->iop[1] == 0x50000)) { /* reson 5=busy expl:0x0 */
1931 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1932 ea->fcport->fw_login_state = DSC_LS_PLOGI_COMP;
1933 break;
1934 }
1935
edd05de1
DG		 1936 if (ea->fcport->n2n_flag) {
1937 ql_dbg(ql_dbg_disc, vha, 0x2118,
1938 "%s %d %8phC post fc4 prli\n",
1939 __func__, __LINE__, ea->fcport->port_name);
1940 ea->fcport->fc4f_nvme = 0;
1941 ea->fcport->n2n_flag = 0;
1942 qla24xx_post_prli_work(vha, ea->fcport);
1943 }
a5d42f4c
DG		 1944 ql_dbg(ql_dbg_disc, vha, 0x2119,
1945 "%s %d %8phC unhandle event of %x\n",
1946 __func__, __LINE__, ea->fcport->port_name, ea->data[0]);
1947 break;
1948 }
1949}
1950
726b8548
QT		 1951static void
1952qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
ac280b67 1953{
726b8548 1954 port_id_t cid; /* conflict Nport id */
a084fd68
QT		 1955 u16 lid;
1956 struct fc_port *conflict_fcport;
82abdcaf 1957 unsigned long flags;
a4239945
QT		 1958 struct fc_port *fcport = ea->fcport;
1959
f352eeb7
QT		 1960 ql_dbg(ql_dbg_disc, vha, 0xffff,
1961 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n",
1962 __func__, fcport->port_name, fcport->disc_state,
1963 fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen,
861d483d 1964 ea->sp->gen1, fcport->rscn_gen,
f352eeb7
QT		 1965 ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]);
1966
a4239945
QT		 1967 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
1968 (fcport->fw_login_state == DSC_LS_PRLI_PEND)) {
1969 ql_dbg(ql_dbg_disc, vha, 0x20ea,
1970 "%s %d %8phC Remote is trying to login\n",
1971 __func__, __LINE__, fcport->port_name);
1972 return;
1973 }
1974
8b5292bc
QT		 1975 if ((fcport->disc_state == DSC_DELETE_PEND) ||
1976 (fcport->disc_state == DSC_DELETED)) {
1977 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
a4239945 1978 return;
8b5292bc 1979 }
a4239945
QT		 1980
1981 if (ea->sp->gen2 != fcport->login_gen) {
1982 /* target side must have changed it. */
1983 ql_dbg(ql_dbg_disc, vha, 0x20d3,
f352eeb7
QT		 1984 "%s %8phC generation changed\n",
1985 __func__, fcport->port_name);
1986 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
a4239945
QT		 1987 return;
1988 } else if (ea->sp->gen1 != fcport->rscn_gen) {
861d483d
QT		 1989 ql_dbg(ql_dbg_disc, vha, 0x20d3,
1990 "%s %8phC RSCN generation changed\n",
1991 __func__, fcport->port_name);
d4f7a16a 1992 qla_rscn_replay(fcport);
861d483d 1993 qlt_schedule_sess_for_deletion(fcport);
a4239945
QT		 1994 return;
1995 }
ac280b67 1996
726b8548 1997 switch (ea->data[0]) {
ac280b67 1998 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 1999 /*
2000 * Driver must validate login state - If PRLI not complete,
2001 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
2002 * requests.
2003 */
a5d42f4c
DG		 2004 if (ea->fcport->fc4f_nvme) {
2005 ql_dbg(ql_dbg_disc, vha, 0x2117,
2006 "%s %d %8phC post prli\n",
2007 __func__, __LINE__, ea->fcport->port_name);
2008 qla24xx_post_prli_work(vha, ea->fcport);
2009 } else {
2010 ql_dbg(ql_dbg_disc, vha, 0x20ea,
a084fd68
QT		 2011 "%s %d %8phC LoopID 0x%x in use with %06x. post gnl\n",
2012 __func__, __LINE__, ea->fcport->port_name,
2013 ea->fcport->loop_id, ea->fcport->d_id.b24);
2014
2015 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
82abdcaf 2016 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a5d42f4c
DG		 2017 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
2018 ea->fcport->logout_on_delete = 1;
3515832c 2019 ea->fcport->send_els_logo = 0;
82abdcaf
QT		 2020 ea->fcport->fw_login_state = DSC_LS_PRLI_COMP;
2021 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
2022
a5d42f4c
DG		 2023 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
2024 }
ac280b67
AV		 2025 break;
2026 case MBS_COMMAND_ERROR:
83548fe2 2027 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n",
726b8548
QT		 2028 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
2029
2030 ea->fcport->flags &= ~FCF_ASYNC_SENT;
2031 ea->fcport->disc_state = DSC_LOGIN_FAILED;
2032 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
ac280b67
AV		 2033 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
2034 else
726b8548 2035 qla2x00_mark_device_lost(vha, ea->fcport, 1, 0);
ac280b67
AV		 2036 break;
2037 case MBS_LOOP_ID_USED:
726b8548
QT		 2038 /* data[1] = IO PARAM 1 = nport ID */
2039 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
2040 cid.b.area = (ea->iop[1] >> 8) & 0xff;
2041 cid.b.al_pa = ea->iop[1] & 0xff;
2042 cid.b.rsvd_1 = 0;
2043
83548fe2 2044 ql_dbg(ql_dbg_disc, vha, 0x20ec,
5c640053 2045 "%s %d %8phC lid %#x in use with pid %06x post gnl\n",
83548fe2 2046 __func__, __LINE__, ea->fcport->port_name,
5c640053 2047 ea->fcport->loop_id, cid.b24);
726b8548 2048
5c640053
QT		 2049 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
2050 ea->fcport->loop_id = FC_NO_LOOP_ID;
726b8548
QT		 2051 qla24xx_post_gnl_work(vha, ea->fcport);
2052 break;
2053 case MBS_PORT_ID_USED:
a084fd68
QT		 2054 lid = ea->iop[1] & 0xffff;
2055 qlt_find_sess_invalidate_other(vha,
2056 wwn_to_u64(ea->fcport->port_name),
2057 ea->fcport->d_id, lid, &conflict_fcport);
2058
2059 if (conflict_fcport) {
2060 /*
2061 * Another fcport share the same loop_id/nport id.
2062 * Conflict fcport needs to finish cleanup before this
2063 * fcport can proceed to login.
2064 */
2065 conflict_fcport->conflict = ea->fcport;
2066 ea->fcport->login_pause = 1;
2067
2068 ql_dbg(ql_dbg_disc, vha, 0x20ed,
2069 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. post gidpn\n",
2070 __func__, __LINE__, ea->fcport->port_name,
2071 ea->fcport->d_id.b24, lid);
a084fd68
QT		 2072 } else {
2073 ql_dbg(ql_dbg_disc, vha, 0x20ed,
2074 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n",
2075 __func__, __LINE__, ea->fcport->port_name,
2076 ea->fcport->d_id.b24, lid);
2077
2078 qla2x00_clear_loop_id(ea->fcport);
2079 set_bit(lid, vha->hw->loop_id_map);
2080 ea->fcport->loop_id = lid;
2081 ea->fcport->keep_nport_handle = 0;
94cff6e1 2082 qlt_schedule_sess_for_deletion(ea->fcport);
a084fd68 2083 }
ac280b67
AV		 2084 break;
2085 }
4916392b 2086 return;
ac280b67
AV		 2087}
2088
4916392b 2089void
ac280b67
AV		 2090qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
2091 uint16_t *data)
2092{
a6ca8878 2093 qlt_logo_completion_handler(fcport, data[0]);
726b8548 2094 fcport->login_gen++;
fa83e658 2095 fcport->flags &= ~FCF_ASYNC_ACTIVE;
4916392b 2096 return;
ac280b67
AV		 2097}
2098
1da177e4
LT		 2099/****************************************************************************/
2100/* QLogic ISP2x00 Hardware Support Functions. */
2101/****************************************************************************/
2102
fa492630 2103static int
7d613ac6
SV		 2104qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
2105{
2106 int rval = QLA_SUCCESS;
2107 struct qla_hw_data *ha = vha->hw;
2108 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 2109 uint16_t config[4];
7d613ac6
SV		 2110
2111 qla83xx_idc_lock(vha, 0);
2112
2113 /* SV: TODO: Assign initialization timeout from
2114 * flash-info / other param
2115 */
2116 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
2117 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
2118
2119 /* Set our fcoe function presence */
2120 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
2121 ql_dbg(ql_dbg_p3p, vha, 0xb077,
2122 "Error while setting DRV-Presence.\n");
2123 rval = QLA_FUNCTION_FAILED;
2124 goto exit;
2125 }
2126
2127 /* Decide the reset ownership */
2128 qla83xx_reset_ownership(vha);
2129
2130 /*
2131 * On first protocol driver load:
2132 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
2133 * register.
2134 * Others: Check compatibility with current IDC Major version.
2135 */
2136 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
2137 if (ha->flags.nic_core_reset_owner) {
2138 /* Set IDC Major version */
2139 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
2140 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
2141
2142 /* Clearing IDC-Lock-Recovery register */
2143 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
2144 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
2145 /*
2146 * Clear further IDC participation if we are not compatible with
2147 * the current IDC Major Version.
2148 */
2149 ql_log(ql_log_warn, vha, 0xb07d,
2150 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
2151 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
2152 __qla83xx_clear_drv_presence(vha);
2153 rval = QLA_FUNCTION_FAILED;
2154 goto exit;
2155 }
2156 /* Each function sets its supported Minor version. */
2157 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
2158 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
2159 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
2160
711aa7f7
SK		 2161 if (ha->flags.nic_core_reset_owner) {
2162 memset(config, 0, sizeof(config));
2163 if (!qla81xx_get_port_config(vha, config))
2164 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
2165 QLA8XXX_DEV_READY);
2166 }
2167
7d613ac6
SV		 2168 rval = qla83xx_idc_state_handler(vha);
2169
2170exit:
2171 qla83xx_idc_unlock(vha, 0);
2172
2173 return rval;
2174}
2175
1da177e4
LT		 2176/*
2177* qla2x00_initialize_adapter
2178* Initialize board.
2179*
2180* Input:
2181* ha = adapter block pointer.
2182*
2183* Returns:
2184* 0 = success
2185*/
2186int
e315cd28 2187qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 2188{
2189 int rval;
e315cd28 2190 struct qla_hw_data *ha = vha->hw;
73208dfd 2191 struct req_que *req = ha->req_q_map[0];
3f006ac3 2192 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2533cf67 2193
fc90adaf
JC		 2194 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
2195 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
2196
1da177e4 2197 /* Clear adapter flags. */
e315cd28 2198 vha->flags.online = 0;
2533cf67 2199 ha->flags.chip_reset_done = 0;
e315cd28 2200 vha->flags.reset_active = 0;
85880801
AV		 2201 ha->flags.pci_channel_io_perm_failure = 0;
2202 ha->flags.eeh_busy = 0;
fabbb8df 2203 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 2204 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
2205 atomic_set(&vha->loop_state, LOOP_DOWN);
2206 vha->device_flags = DFLG_NO_CABLE;
2207 vha->dpc_flags = 0;
2208 vha->flags.management_server_logged_in = 0;
2209 vha->marker_needed = 0;
1da177e4
LT		 2210 ha->isp_abort_cnt = 0;
2211 ha->beacon_blink_led = 0;
2212
73208dfd
AC		 2213 set_bit(0, ha->req_qid_map);
2214 set_bit(0, ha->rsp_qid_map);
2215
cfb0919c 2216 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 2217 "Configuring PCI space...\n");
e315cd28 2218 rval = ha->isp_ops->pci_config(vha);
1da177e4 2219 if (rval) {
7c3df132
SK		 2220 ql_log(ql_log_warn, vha, 0x0044,
2221 "Unable to configure PCI space.\n");
1da177e4
LT		 2222 return (rval);
2223 }
2224
e315cd28 2225 ha->isp_ops->reset_chip(vha);
1da177e4 2226
3f006ac3
MH		 2227 /* Check for secure flash support */
2228 if (IS_QLA28XX(ha)) {
2229 if (RD_REG_DWORD(&reg->mailbox12) & BIT_0) {
2230 ql_log(ql_log_info, vha, 0xffff, "Adapter is Secure\n");
2231 ha->flags.secure_adapter = 1;
2232 }
2233 }
2234
2235
e315cd28 2236 rval = qla2xxx_get_flash_info(vha);
c00d8994 2237 if (rval) {
7c3df132
SK		 2238 ql_log(ql_log_fatal, vha, 0x004f,
2239 "Unable to validate FLASH data.\n");
7ec0effd
AD		 2240 return rval;
2241 }
2242
2243 if (IS_QLA8044(ha)) {
2244 qla8044_read_reset_template(vha);
2245
2246 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
2247 * If DONRESET_BIT0 is set, drivers should not set dev_state
2248 * to NEED_RESET. But if NEED_RESET is set, drivers should
2249 * should honor the reset. */
2250 if (ql2xdontresethba == 1)
2251 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 2252 }
2253
73208dfd 2254 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 2255 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 2256 "Configure NVRAM parameters...\n");
0107109e 2257
e315cd28 2258 ha->isp_ops->nvram_config(vha);
1da177e4 2259
d4c760c2
AV		 2260 if (ha->flags.disable_serdes) {
2261 /* Mask HBA via NVRAM settings? */
7c3df132 2262 ql_log(ql_log_info, vha, 0x0077,
7b833558 2263 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 2264 return QLA_FUNCTION_FAILED;
2265 }
2266
cfb0919c 2267 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 2268 "Verifying loaded RISC code...\n");
1da177e4 2269
e315cd28
AC		 2270 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
2271 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 2272 if (rval)
2273 return (rval);
e315cd28 2274 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 2275 if (rval)
2276 return (rval);
1da177e4 2277 }
a9083016 2278
4d4df193 2279 if (IS_QLA84XX(ha)) {
e315cd28 2280 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 2281 if (!ha->cs84xx) {
7c3df132 2282 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 2283 "Unable to configure ISP84XX.\n");
2284 return QLA_FUNCTION_FAILED;
2285 }
2286 }
2d70c103 2287
ead03855 2288 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2d70c103
NB		 2289 rval = qla2x00_init_rings(vha);
2290
26a77799
AV		 2291 /* No point in continuing if firmware initialization failed. */
2292 if (rval != QLA_SUCCESS)
2293 return rval;
2294
2533cf67 2295 ha->flags.chip_reset_done = 1;
1da177e4 2296
9a069e19 2297 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 2298 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 2299 rval = qla84xx_init_chip(vha);
2300 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2301 ql_log(ql_log_warn, vha, 0x00d4,
2302 "Unable to initialize ISP84XX.\n");
8d2b21db 2303 qla84xx_put_chip(vha);
9a069e19
GM		 2304 }
2305 }
2306
7d613ac6
SV		 2307 /* Load the NIC Core f/w if we are the first protocol driver. */
2308 if (IS_QLA8031(ha)) {
2309 rval = qla83xx_nic_core_fw_load(vha);
2310 if (rval)
2311 ql_log(ql_log_warn, vha, 0x0124,
2312 "Error in initializing NIC Core f/w.\n");
2313 }
2314
2f0f3f4f
MI		 2315 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
2316 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 2317
c46e65c7
JC		 2318 if (IS_P3P_TYPE(ha))
2319 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
2320 else
2321 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
2322
1da177e4
LT		 2323 return (rval);
2324}
2325
2326/**
abbd8870 2327 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
2db6228d 2328 * @vha: HA context
1da177e4
LT		 2329 *
2330 * Returns 0 on success.
2331 */
abbd8870 2332int
e315cd28 2333qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 2334{
a157b101 2335 uint16_t w;
abbd8870 2336 unsigned long flags;
e315cd28 2337 struct qla_hw_data *ha = vha->hw;
3d71644c 2338 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2339
1da177e4 2340 pci_set_master(ha->pdev);
af6177d8 2341 pci_try_set_mwi(ha->pdev);
1da177e4 2342
1da177e4 2343 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2344 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 2345 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2346
737faece 2347 pci_disable_rom(ha->pdev);
1da177e4
LT		 2348
2349 /* Get PCI bus information. */
2350 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 2351 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 2352 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2353
abbd8870
AV		 2354 return QLA_SUCCESS;
2355}
1da177e4 2356
abbd8870
AV		 2357/**
2358 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
2db6228d 2359 * @vha: HA context
abbd8870
AV		 2360 *
2361 * Returns 0 on success.
2362 */
2363int
e315cd28 2364qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 2365{
a157b101 2366 uint16_t w;
abbd8870
AV		 2367 unsigned long flags = 0;
2368 uint32_t cnt;
e315cd28 2369 struct qla_hw_data *ha = vha->hw;
3d71644c 2370 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2371
abbd8870 2372 pci_set_master(ha->pdev);
af6177d8 2373 pci_try_set_mwi(ha->pdev);
1da177e4 2374
abbd8870 2375 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2376 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 2377
abbd8870
AV		 2378 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2379 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 2380 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 2381
abbd8870
AV		 2382 /*
2383 * If this is a 2300 card and not 2312, reset the
2384 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
2385 * the 2310 also reports itself as a 2300 so we need to get the
2386 * fb revision level -- a 6 indicates it really is a 2300 and
2387 * not a 2310.
2388 */
2389 if (IS_QLA2300(ha)) {
2390 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 2391
abbd8870 2392 /* Pause RISC. */
3d71644c 2393 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 2394 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 2395 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 2396 break;
1da177e4 2397
abbd8870
AV		 2398 udelay(10);
2399 }
1da177e4 2400
abbd8870 2401 /* Select FPM registers. */
3d71644c
AV		 2402 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2403 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2404
2405 /* Get the fb rev level */
3d71644c 2406 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 2407
2408 if (ha->fb_rev == FPM_2300)
a157b101 2409 pci_clear_mwi(ha->pdev);
abbd8870
AV		 2410
2411 /* Deselect FPM registers. */
3d71644c
AV		 2412 WRT_REG_WORD(&reg->ctrl_status, 0x0);
2413 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2414
2415 /* Release RISC module. */
3d71644c 2416 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 2417 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 2418 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 2419 break;
2420
2421 udelay(10);
1da177e4 2422 }
1da177e4 2423
abbd8870
AV		 2424 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2425 }
1da177e4 2426
abbd8870
AV		 2427 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2428
737faece 2429 pci_disable_rom(ha->pdev);
1da177e4 2430
abbd8870
AV		 2431 /* Get PCI bus information. */
2432 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 2433 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2434 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2435
2436 return QLA_SUCCESS;
1da177e4
LT		 2437}
2438
0107109e
AV		 2439/**
2440 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
2db6228d 2441 * @vha: HA context
0107109e
AV		 2442 *
2443 * Returns 0 on success.
2444 */
2445int
e315cd28 2446qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 2447{
a157b101 2448 uint16_t w;
0107109e 2449 unsigned long flags = 0;
e315cd28 2450 struct qla_hw_data *ha = vha->hw;
0107109e 2451 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 2452
2453 pci_set_master(ha->pdev);
af6177d8 2454 pci_try_set_mwi(ha->pdev);
0107109e
AV		 2455
2456 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2457 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 2458 w &= ~PCI_COMMAND_INTX_DISABLE;
2459 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2460
2461 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2462
2463 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 2464 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
2465 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 2466
2467 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 2468 if (pci_is_pcie(ha->pdev))
5ffd3a52 2469 pcie_set_readrq(ha->pdev, 4096);
0107109e 2470
737faece 2471 pci_disable_rom(ha->pdev);
0107109e 2472
44c10138 2473 ha->chip_revision = ha->pdev->revision;
a8488abe 2474
0107109e
AV		 2475 /* Get PCI bus information. */
2476 spin_lock_irqsave(&ha->hardware_lock, flags);
2477 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
2478 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2479
2480 return QLA_SUCCESS;
2481}
2482
c3a2f0df
AV		 2483/**
2484 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
2db6228d 2485 * @vha: HA context
c3a2f0df
AV		 2486 *
2487 * Returns 0 on success.
2488 */
2489int
e315cd28 2490qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 2491{
2492 uint16_t w;
e315cd28 2493 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 2494
2495 pci_set_master(ha->pdev);
2496 pci_try_set_mwi(ha->pdev);
2497
2498 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2499 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2500 w &= ~PCI_COMMAND_INTX_DISABLE;
2501 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2502
2503 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 2504 if (pci_is_pcie(ha->pdev))
5ffd3a52 2505 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 2506
737faece 2507 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 2508
2509 ha->chip_revision = ha->pdev->revision;
2510
2511 return QLA_SUCCESS;
2512}
2513
1da177e4
LT		 2514/**
2515 * qla2x00_isp_firmware() - Choose firmware image.
2db6228d 2516 * @vha: HA context
1da177e4
LT		 2517 *
2518 * Returns 0 on success.
2519 */
2520static int
e315cd28 2521qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 2522{
2523 int rval;
42e421b1
AV		 2524 uint16_t loop_id, topo, sw_cap;
2525 uint8_t domain, area, al_pa;
e315cd28 2526 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2527
2528 /* Assume loading risc code */
fa2a1ce5 2529 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 2530
2531 if (ha->flags.disable_risc_code_load) {
7c3df132 2532 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 2533
2534 /* Verify checksum of loaded RISC code. */
e315cd28 2535 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 2536 if (rval == QLA_SUCCESS) {
2537 /* And, verify we are not in ROM code. */
e315cd28 2538 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 2539 &area, &domain, &topo, &sw_cap);
2540 }
1da177e4
LT		 2541 }
2542
7c3df132
SK		 2543 if (rval)
2544 ql_dbg(ql_dbg_init, vha, 0x007a,
2545 "**** Load RISC code ****.\n");
1da177e4
LT		 2546
2547 return (rval);
2548}
2549
2550/**
2551 * qla2x00_reset_chip() - Reset ISP chip.
2db6228d 2552 * @vha: HA context
1da177e4
LT		 2553 *
2554 * Returns 0 on success.
2555 */
3f006ac3 2556int
e315cd28 2557qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 2558{
2559 unsigned long flags = 0;
e315cd28 2560 struct qla_hw_data *ha = vha->hw;
3d71644c 2561 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2562 uint32_t cnt;
1da177e4 2563 uint16_t cmd;
3f006ac3 2564 int rval = QLA_FUNCTION_FAILED;
1da177e4 2565
85880801 2566 if (unlikely(pci_channel_offline(ha->pdev)))
3f006ac3 2567 return rval;
85880801 2568
fd34f556 2569 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 2570
2571 spin_lock_irqsave(&ha->hardware_lock, flags);
2572
2573 /* Turn off master enable */
2574 cmd = 0;
2575 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
2576 cmd &= ~PCI_COMMAND_MASTER;
2577 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2578
2579 if (!IS_QLA2100(ha)) {
2580 /* Pause RISC. */
2581 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2582 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
2583 for (cnt = 0; cnt < 30000; cnt++) {
2584 if ((RD_REG_WORD(&reg->hccr) &
2585 HCCR_RISC_PAUSE) != 0)
2586 break;
2587 udelay(100);
2588 }
2589 } else {
2590 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2591 udelay(10);
2592 }
2593
2594 /* Select FPM registers. */
2595 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2596 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2597
2598 /* FPM Soft Reset. */
2599 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
2600 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2601
2602 /* Toggle Fpm Reset. */
2603 if (!IS_QLA2200(ha)) {
2604 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
2605 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2606 }
2607
2608 /* Select frame buffer registers. */
2609 WRT_REG_WORD(&reg->ctrl_status, 0x10);
2610 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2611
2612 /* Reset frame buffer FIFOs. */
2613 if (IS_QLA2200(ha)) {
2614 WRT_FB_CMD_REG(ha, reg, 0xa000);
2615 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
2616 } else {
2617 WRT_FB_CMD_REG(ha, reg, 0x00fc);
2618
2619 /* Read back fb_cmd until zero or 3 seconds max */
2620 for (cnt = 0; cnt < 3000; cnt++) {
2621 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
2622 break;
2623 udelay(100);
2624 }
2625 }
2626
2627 /* Select RISC module registers. */
2628 WRT_REG_WORD(&reg->ctrl_status, 0);
2629 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2630
2631 /* Reset RISC processor. */
2632 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2633 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2634
2635 /* Release RISC processor. */
2636 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2637 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2638 }
2639
2640 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
2641 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
2642
2643 /* Reset ISP chip. */
2644 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2645
2646 /* Wait for RISC to recover from reset. */
2647 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2648 /*
2649 * It is necessary to for a delay here since the card doesn't
2650 * respond to PCI reads during a reset. On some architectures
2651 * this will result in an MCA.
2652 */
2653 udelay(20);
2654 for (cnt = 30000; cnt; cnt--) {
2655 if ((RD_REG_WORD(&reg->ctrl_status) &
2656 CSR_ISP_SOFT_RESET) == 0)
2657 break;
2658 udelay(100);
2659 }
2660 } else
2661 udelay(10);
2662
2663 /* Reset RISC processor. */
2664 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2665
2666 WRT_REG_WORD(&reg->semaphore, 0);
2667
2668 /* Release RISC processor. */
2669 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2670 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2671
2672 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2673 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 2674 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 2675 break;
1da177e4
LT		 2676
2677 udelay(100);
2678 }
2679 } else
2680 udelay(100);
2681
2682 /* Turn on master enable */
2683 cmd |= PCI_COMMAND_MASTER;
2684 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2685
2686 /* Disable RISC pause on FPM parity error. */
2687 if (!IS_QLA2100(ha)) {
2688 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
2689 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2690 }
2691
2692 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3f006ac3
MH		 2693
2694 return QLA_SUCCESS;
1da177e4
LT		 2695}
2696
b1d46989
MI		 2697/**
2698 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
2db6228d 2699 * @vha: HA context
b1d46989
MI		 2700 *
2701 * Returns 0 on success.
2702 */
fa492630 2703static int
b1d46989
MI		 2704qla81xx_reset_mpi(scsi_qla_host_t *vha)
2705{
2706 uint16_t mb[4] = {0x1010, 0, 1, 0};
2707
6246b8a1
GM		 2708 if (!IS_QLA81XX(vha->hw))
2709 return QLA_SUCCESS;
2710
b1d46989
MI		 2711 return qla81xx_write_mpi_register(vha, mb);
2712}
2713
0107109e 2714/**
88c26663 2715 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
2db6228d 2716 * @vha: HA context
0107109e
AV		 2717 *
2718 * Returns 0 on success.
2719 */
d14e72fb 2720static inline int
e315cd28 2721qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 2722{
2723 unsigned long flags = 0;
e315cd28 2724 struct qla_hw_data *ha = vha->hw;
0107109e 2725 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 2726 uint32_t cnt;
335a1cc9 2727 uint16_t wd;
b1d46989 2728 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 2729 int rval = QLA_SUCCESS;
0107109e 2730
0107109e
AV		 2731 spin_lock_irqsave(&ha->hardware_lock, flags);
2732
2733 /* Reset RISC. */
2734 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2735 for (cnt = 0; cnt < 30000; cnt++) {
2736 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2737 break;
2738
2739 udelay(10);
2740 }
2741
d14e72fb
HM		 2742 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
2743 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2744
2745 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2746 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2747 RD_REG_DWORD(&reg->hccr),
2748 RD_REG_DWORD(&reg->ctrl_status),
2749 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
2750
0107109e
AV		 2751 WRT_REG_DWORD(&reg->ctrl_status,
2752 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 2753 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 2754
335a1cc9 2755 udelay(100);
d14e72fb 2756
88c26663 2757 /* Wait for firmware to complete NVRAM accesses. */
52c82823 2758 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 2759 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2760 rval == QLA_SUCCESS; cnt--) {
88c26663 2761 barrier();
d14e72fb
HM		 2762 if (cnt)
2763 udelay(5);
2764 else
2765 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 2766 }
2767
d14e72fb
HM		 2768 if (rval == QLA_SUCCESS)
2769 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2770
2771 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2772 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2773 RD_REG_DWORD(&reg->hccr),
2774 RD_REG_DWORD(&reg->mailbox0));
2775
335a1cc9 2776 /* Wait for soft-reset to complete. */
52c82823 2777 RD_REG_DWORD(&reg->ctrl_status);
200ffb15 2778 for (cnt = 0; cnt < 60; cnt++) {
0107109e 2779 barrier();
d14e72fb
HM		 2780 if ((RD_REG_DWORD(&reg->ctrl_status) &
2781 CSRX_ISP_SOFT_RESET) == 0)
2782 break;
2783
2784 udelay(5);
0107109e 2785 }
d14e72fb
HM		 2786 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
2787 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2788
2789 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2790 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2791 RD_REG_DWORD(&reg->hccr),
2792 RD_REG_DWORD(&reg->ctrl_status));
0107109e 2793
b1d46989
MI		 2794 /* If required, do an MPI FW reset now */
2795 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2796 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2797 if (++abts_cnt < 5) {
2798 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2799 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2800 } else {
2801 /*
2802 * We exhausted the ISP abort retries. We have to
2803 * set the board offline.
2804 */
2805 abts_cnt = 0;
2806 vha->flags.online = 0;
2807 }
2808 }
2809 }
2810
0107109e
AV		 2811 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2812 RD_REG_DWORD(&reg->hccr);
2813
2814 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2815 RD_REG_DWORD(&reg->hccr);
2816
2817 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2818 RD_REG_DWORD(&reg->hccr);
2819
52c82823 2820 RD_REG_WORD(&reg->mailbox0);
200ffb15 2821 for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
d14e72fb 2822 rval == QLA_SUCCESS; cnt--) {
0107109e 2823 barrier();
d14e72fb
HM		 2824 if (cnt)
2825 udelay(5);
2826 else
2827 rval = QLA_FUNCTION_TIMEOUT;
0107109e 2828 }
d14e72fb
HM		 2829 if (rval == QLA_SUCCESS)
2830 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2831
2832 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2833 "Host Risc 0x%x, mailbox0 0x%x\n",
2834 RD_REG_DWORD(&reg->hccr),
2835 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 2836
2837 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 2838
d14e72fb
HM		 2839 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2840 "Driver in %s mode\n",
2841 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2842
124f85e6
AV		 2843 if (IS_NOPOLLING_TYPE(ha))
2844 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 2845
2846 return rval;
0107109e
AV		 2847}
2848
4ea2c9c7
JC		 2849static void
2850qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2851{
2852 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2853
2854 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2855 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
2856
2857}
2858
2859static void
2860qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2861{
2862 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2863
2864 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2865 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
2866}
2867
2868static void
2869qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2870{
4ea2c9c7
JC		 2871 uint32_t wd32 = 0;
2872 uint delta_msec = 100;
2873 uint elapsed_msec = 0;
2874 uint timeout_msec;
2875 ulong n;
2876
cc790764
JC		 2877 if (vha->hw->pdev->subsystem_device != 0x0175 &&
2878 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 2879 return;
2880
8dd7e3a5
JC		 2881 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2882 udelay(100);
2883
4ea2c9c7
JC		 2884attempt:
2885 timeout_msec = TIMEOUT_SEMAPHORE;
2886 n = timeout_msec / delta_msec;
2887 while (n--) {
2888 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
2889 qla25xx_read_risc_sema_reg(vha, &wd32);
2890 if (wd32 & RISC_SEMAPHORE)
2891 break;
2892 msleep(delta_msec);
2893 elapsed_msec += delta_msec;
2894 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2895 goto force;
2896 }
2897
2898 if (!(wd32 & RISC_SEMAPHORE))
2899 goto force;
2900
2901 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2902 goto acquired;
2903
2904 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
2905 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
2906 n = timeout_msec / delta_msec;
2907 while (n--) {
2908 qla25xx_read_risc_sema_reg(vha, &wd32);
2909 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2910 break;
2911 msleep(delta_msec);
2912 elapsed_msec += delta_msec;
2913 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2914 goto force;
2915 }
2916
2917 if (wd32 & RISC_SEMAPHORE_FORCE)
2918 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
2919
2920 goto attempt;
2921
2922force:
2923 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
2924
2925acquired:
2926 return;
2927}
2928
88c26663
AV		 2929/**
2930 * qla24xx_reset_chip() - Reset ISP24xx chip.
2db6228d 2931 * @vha: HA context
88c26663
AV		 2932 *
2933 * Returns 0 on success.
2934 */
3f006ac3 2935int
e315cd28 2936qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 2937{
e315cd28 2938 struct qla_hw_data *ha = vha->hw;
3f006ac3 2939 int rval = QLA_FUNCTION_FAILED;
85880801
AV		 2940
2941 if (pci_channel_offline(ha->pdev) &&
2942 ha->flags.pci_channel_io_perm_failure) {
3f006ac3 2943 return rval;
85880801
AV		 2944 }
2945
fd34f556 2946 ha->isp_ops->disable_intrs(ha);
88c26663 2947
4ea2c9c7
JC		 2948 qla25xx_manipulate_risc_semaphore(vha);
2949
88c26663 2950 /* Perform RISC reset. */
3f006ac3
MH		 2951 rval = qla24xx_reset_risc(vha);
2952
2953 return rval;
88c26663
AV		 2954}
2955
1da177e4
LT		 2956/**
2957 * qla2x00_chip_diag() - Test chip for proper operation.
2db6228d 2958 * @vha: HA context
1da177e4
LT		 2959 *
2960 * Returns 0 on success.
2961 */
abbd8870 2962int
e315cd28 2963qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 2964{
2965 int rval;
e315cd28 2966 struct qla_hw_data *ha = vha->hw;
3d71644c 2967 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 2968 unsigned long flags = 0;
2969 uint16_t data;
2970 uint32_t cnt;
2971 uint16_t mb[5];
73208dfd 2972 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 2973
2974 /* Assume a failed state */
2975 rval = QLA_FUNCTION_FAILED;
2976
da4704d9
BVA		 2977 ql_dbg(ql_dbg_init, vha, 0x007b, "Testing device at %p.\n",
2978 &reg->flash_address);
1da177e4
LT		 2979
2980 spin_lock_irqsave(&ha->hardware_lock, flags);
2981
2982 /* Reset ISP chip. */
2983 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2984
2985 /*
2986 * We need to have a delay here since the card will not respond while
2987 * in reset causing an MCA on some architectures.
2988 */
2989 udelay(20);
2990 data = qla2x00_debounce_register(&reg->ctrl_status);
2991 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
2992 udelay(5);
2993 data = RD_REG_WORD(&reg->ctrl_status);
2994 barrier();
2995 }
2996
2997 if (!cnt)
2998 goto chip_diag_failed;
2999
7c3df132
SK		 3000 ql_dbg(ql_dbg_init, vha, 0x007c,
3001 "Reset register cleared by chip reset.\n");
1da177e4
LT		 3002
3003 /* Reset RISC processor. */
3004 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
3005 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
3006
3007 /* Workaround for QLA2312 PCI parity error */
3008 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
3009 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
3010 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
3011 udelay(5);
3012 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 3013 barrier();
1da177e4
LT		 3014 }
3015 } else
3016 udelay(10);
3017
3018 if (!cnt)
3019 goto chip_diag_failed;
3020
3021 /* Check product ID of chip */
5a68a1c2 3022 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
1da177e4
LT		 3023
3024 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
3025 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
3026 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
3027 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
3028 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
3029 mb[3] != PROD_ID_3) {
7c3df132
SK		 3030 ql_log(ql_log_warn, vha, 0x0062,
3031 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
3032 mb[1], mb[2], mb[3]);
1da177e4
LT		 3033
3034 goto chip_diag_failed;
3035 }
3036 ha->product_id[0] = mb[1];
3037 ha->product_id[1] = mb[2];
3038 ha->product_id[2] = mb[3];
3039 ha->product_id[3] = mb[4];
3040
3041 /* Adjust fw RISC transfer size */
73208dfd 3042 if (req->length > 1024)
1da177e4
LT		 3043 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
3044 else
3045 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 3046 req->length;
1da177e4
LT		 3047
3048 if (IS_QLA2200(ha) &&
3049 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
3050 /* Limit firmware transfer size with a 2200A */
7c3df132 3051 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 3052
ea5b6382 3053 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 3054 ha->fw_transfer_size = 128;
3055 }
3056
3057 /* Wrap Incoming Mailboxes Test. */
3058 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3059
7c3df132 3060 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 3061 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 3062 if (rval)
3063 ql_log(ql_log_warn, vha, 0x0080,
3064 "Failed mailbox send register test.\n");
3065 else
1da177e4
LT		 3066 /* Flag a successful rval */
3067 rval = QLA_SUCCESS;
1da177e4
LT		 3068 spin_lock_irqsave(&ha->hardware_lock, flags);
3069
3070chip_diag_failed:
3071 if (rval)
7c3df132
SK		 3072 ql_log(ql_log_info, vha, 0x0081,
3073 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 3074
3075 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3076
3077 return (rval);
3078}
3079
0107109e
AV		 3080/**
3081 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
2db6228d 3082 * @vha: HA context
0107109e
AV		 3083 *
3084 * Returns 0 on success.
3085 */
3086int
e315cd28 3087qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 3088{
3089 int rval;
e315cd28 3090 struct qla_hw_data *ha = vha->hw;
73208dfd 3091 struct req_que *req = ha->req_q_map[0];
0107109e 3092
7ec0effd 3093 if (IS_P3P_TYPE(ha))
a9083016
GM		 3094 return QLA_SUCCESS;
3095
73208dfd 3096 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 3097
e315cd28 3098 rval = qla2x00_mbx_reg_test(vha);
0107109e 3099 if (rval) {
7c3df132
SK		 3100 ql_log(ql_log_warn, vha, 0x0082,
3101 "Failed mailbox send register test.\n");
0107109e
AV		 3102 } else {
3103 /* Flag a successful rval */
3104 rval = QLA_SUCCESS;
3105 }
3106
3107 return rval;
3108}
3109
ad0a0b01
QT		 3110static void
3111qla2x00_alloc_offload_mem(scsi_qla_host_t *vha)
0107109e 3112{
a7a167bf 3113 int rval;
df613b96
AV		 3114 dma_addr_t tc_dma;
3115 void *tc;
e315cd28 3116 struct qla_hw_data *ha = vha->hw;
a7a167bf 3117
ad0a0b01 3118 if (ha->eft) {
7c3df132 3119 ql_dbg(ql_dbg_init, vha, 0x00bd,
ad0a0b01
QT		 3120 "%s: Offload Mem is already allocated.\n",
3121 __func__);
a7a167bf
AV		 3122 return;
3123 }
d4e3e04d 3124
ad0a0b01 3125 if (IS_FWI2_CAPABLE(ha)) {
df613b96 3126 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695 3127 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
ecc89f25 3128 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
436a7b11 3129 goto try_eft;
df613b96 3130
f73cb695
CD		 3131 if (ha->fce)
3132 dma_free_coherent(&ha->pdev->dev,
3133 FCE_SIZE, ha->fce, ha->fce_dma);
3134
3135 /* Allocate memory for Fibre Channel Event Buffer. */
750afb08
LC		 3136 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
3137 GFP_KERNEL);
df613b96 3138 if (!tc) {
7c3df132
SK		 3139 ql_log(ql_log_warn, vha, 0x00be,
3140 "Unable to allocate (%d KB) for FCE.\n",
3141 FCE_SIZE / 1024);
17d98630 3142 goto try_eft;
df613b96
AV		 3143 }
3144
e315cd28 3145 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 3146 ha->fce_mb, &ha->fce_bufs);
3147 if (rval) {
7c3df132
SK		 3148 ql_log(ql_log_warn, vha, 0x00bf,
3149 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 3150 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
3151 tc_dma);
3152 ha->flags.fce_enabled = 0;
17d98630 3153 goto try_eft;
df613b96 3154 }
cfb0919c 3155 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 3156 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 3157
df613b96
AV		 3158 ha->flags.fce_enabled = 1;
3159 ha->fce_dma = tc_dma;
3160 ha->fce = tc;
f73cb695 3161
436a7b11 3162try_eft:
f73cb695
CD		 3163 if (ha->eft)
3164 dma_free_coherent(&ha->pdev->dev,
3165 EFT_SIZE, ha->eft, ha->eft_dma);
3166
436a7b11 3167 /* Allocate memory for Extended Trace Buffer. */
750afb08
LC		 3168 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
3169 GFP_KERNEL);
436a7b11 3170 if (!tc) {
7c3df132
SK		 3171 ql_log(ql_log_warn, vha, 0x00c1,
3172 "Unable to allocate (%d KB) for EFT.\n",
3173 EFT_SIZE / 1024);
ad0a0b01 3174 goto eft_err;
436a7b11
AV		 3175 }
3176
e315cd28 3177 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 3178 if (rval) {
7c3df132
SK		 3179 ql_log(ql_log_warn, vha, 0x00c2,
3180 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 3181 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
3182 tc_dma);
ad0a0b01 3183 goto eft_err;
436a7b11 3184 }
cfb0919c 3185 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 3186 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11 3187
436a7b11
AV		 3188 ha->eft_dma = tc_dma;
3189 ha->eft = tc;
d4e3e04d 3190 }
f73cb695 3191
ad0a0b01
QT		 3192eft_err:
3193 return;
3194}
3195
3196void
3197qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
3198{
a28d9e4e 3199 int rval;
ad0a0b01
QT		 3200 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
3201 eft_size, fce_size, mq_size;
3202 struct qla_hw_data *ha = vha->hw;
3203 struct req_que *req = ha->req_q_map[0];
3204 struct rsp_que *rsp = ha->rsp_q_map[0];
3205 struct qla2xxx_fw_dump *fw_dump;
a28d9e4e
JC		 3206 dma_addr_t tc_dma;
3207 void *tc;
ad0a0b01
QT		 3208
3209 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
3210 req_q_size = rsp_q_size = 0;
3211
3212 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3213 fixed_size = sizeof(struct qla2100_fw_dump);
3214 } else if (IS_QLA23XX(ha)) {
3215 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
3216 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
3217 sizeof(uint16_t);
3218 } else if (IS_FWI2_CAPABLE(ha)) {
ecc89f25 3219 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
ad0a0b01
QT		 3220 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
3221 else if (IS_QLA81XX(ha))
3222 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
3223 else if (IS_QLA25XX(ha))
3224 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
3225 else
3226 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
3227
3228 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
3229 sizeof(uint32_t);
3230 if (ha->mqenable) {
ecc89f25
JC		 3231 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) &&
3232 !IS_QLA28XX(ha))
ad0a0b01
QT		 3233 mq_size = sizeof(struct qla2xxx_mq_chain);
3234 /*
a4226ec3 3235 * Allocate maximum buffer size for all queues - Q0.
ad0a0b01
QT		 3236 * Resizing must be done at end-of-dump processing.
3237 */
a4226ec3 3238 mq_size += (ha->max_req_queues - 1) *
ad0a0b01 3239 (req->length * sizeof(request_t));
a4226ec3 3240 mq_size += (ha->max_rsp_queues - 1) *
ad0a0b01
QT		 3241 (rsp->length * sizeof(response_t));
3242 }
3243 if (ha->tgt.atio_ring)
3244 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
3245 /* Allocate memory for Fibre Channel Event Buffer. */
3246 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
ecc89f25 3247 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
ad0a0b01
QT		 3248 goto try_eft;
3249
3250 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
3251try_eft:
a28d9e4e
JC		 3252 if (ha->eft)
3253 dma_free_coherent(&ha->pdev->dev,
3254 EFT_SIZE, ha->eft, ha->eft_dma);
3255
3256 /* Allocate memory for Extended Trace Buffer. */
3257 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
3258 GFP_KERNEL);
3259 if (!tc) {
3260 ql_log(ql_log_warn, vha, 0x00c1,
3261 "Unable to allocate (%d KB) for EFT.\n",
3262 EFT_SIZE / 1024);
3263 goto allocate;
3264 }
3265
3266 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
3267 if (rval) {
3268 ql_log(ql_log_warn, vha, 0x00c2,
3269 "Unable to initialize EFT (%d).\n", rval);
3270 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
3271 tc_dma);
3272 }
ad0a0b01
QT		 3273 ql_dbg(ql_dbg_init, vha, 0x00c3,
3274 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
3275 eft_size = EFT_SIZE;
3276 }
3277
ecc89f25 3278 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
a28d9e4e
JC		 3279 struct fwdt *fwdt = ha->fwdt;
3280 uint j;
3281
3282 for (j = 0; j < 2; j++, fwdt++) {
3283 if (!fwdt->template) {
3284 ql_log(ql_log_warn, vha, 0x00ba,
3285 "-> fwdt%u no template\n", j);
3286 continue;
3287 }
3288 ql_dbg(ql_dbg_init, vha, 0x00fa,
3289 "-> fwdt%u calculating fwdump size...\n", j);
3290 fwdt->dump_size = qla27xx_fwdt_calculate_dump_size(
3291 vha, fwdt->template);
3292 ql_dbg(ql_dbg_init, vha, 0x00fa,
3293 "-> fwdt%u calculated fwdump size = %#lx bytes\n",
3294 j, fwdt->dump_size);
3295 dump_size += fwdt->dump_size;
f73cb695 3296 }
f73cb695
CD		 3297 goto allocate;
3298 }
3299
73208dfd
AC		 3300 req_q_size = req->length * sizeof(request_t);
3301 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 3302 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 3303 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 3304 ha->chain_offset = dump_size;
3305 dump_size += mq_size + fce_size;
d4e3e04d 3306
b945e777
QT		 3307 if (ha->exchoffld_buf)
3308 dump_size += sizeof(struct qla2xxx_offld_chain) +
3309 ha->exchoffld_size;
3310 if (ha->exlogin_buf)
3311 dump_size += sizeof(struct qla2xxx_offld_chain) +
3312 ha->exlogin_size;
3313
f73cb695 3314allocate:
a4226ec3
QT		 3315 if (!ha->fw_dump_len || dump_size > ha->fw_dump_alloc_len) {
3316
3317 ql_dbg(ql_dbg_init, vha, 0x00c5,
3318 "%s dump_size %d fw_dump_len %d fw_dump_alloc_len %d\n",
3319 __func__, dump_size, ha->fw_dump_len,
3320 ha->fw_dump_alloc_len);
3321
ad0a0b01
QT		 3322 fw_dump = vmalloc(dump_size);
3323 if (!fw_dump) {
3324 ql_log(ql_log_warn, vha, 0x00c4,
3325 "Unable to allocate (%d KB) for firmware dump.\n",
3326 dump_size / 1024);
3327 } else {
a6b95d1c 3328 mutex_lock(&ha->optrom_mutex);
a4226ec3
QT		 3329 if (ha->fw_dumped) {
3330 memcpy(fw_dump, ha->fw_dump, ha->fw_dump_len);
ad0a0b01 3331 vfree(ha->fw_dump);
a4226ec3
QT		 3332 ha->fw_dump = fw_dump;
3333 ha->fw_dump_alloc_len = dump_size;
3334 ql_dbg(ql_dbg_init, vha, 0x00c5,
3335 "Re-Allocated (%d KB) and save firmware dump.\n",
3336 dump_size / 1024);
3337 } else {
3338 if (ha->fw_dump)
3339 vfree(ha->fw_dump);
3340 ha->fw_dump = fw_dump;
3341
3342 ha->fw_dump_len = ha->fw_dump_alloc_len =
3343 dump_size;
3344 ql_dbg(ql_dbg_init, vha, 0x00c5,
3345 "Allocated (%d KB) for firmware dump.\n",
3346 dump_size / 1024);
3347
a6b95d1c
QT		 3348 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
3349 mutex_unlock(&ha->optrom_mutex);
a4226ec3 3350 return;
a6b95d1c 3351 }
a4226ec3
QT		 3352
3353 ha->fw_dump->signature[0] = 'Q';
3354 ha->fw_dump->signature[1] = 'L';
3355 ha->fw_dump->signature[2] = 'G';
3356 ha->fw_dump->signature[3] = 'C';
3357 ha->fw_dump->version = htonl(1);
3358
3359 ha->fw_dump->fixed_size = htonl(fixed_size);
3360 ha->fw_dump->mem_size = htonl(mem_size);
3361 ha->fw_dump->req_q_size = htonl(req_q_size);
3362 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
3363
3364 ha->fw_dump->eft_size = htonl(eft_size);
3365 ha->fw_dump->eft_addr_l =
3366 htonl(LSD(ha->eft_dma));
3367 ha->fw_dump->eft_addr_h =
3368 htonl(MSD(ha->eft_dma));
3369
3370 ha->fw_dump->header_size =
3371 htonl(offsetof
3372 (struct qla2xxx_fw_dump, isp));
3373 }
a6b95d1c 3374 mutex_unlock(&ha->optrom_mutex);
a7a167bf 3375 }
a7a167bf 3376 }
0107109e
AV		 3377}
3378
18e7555a
AV		 3379static int
3380qla81xx_mpi_sync(scsi_qla_host_t *vha)
3381{
3382#define MPS_MASK 0xe0
3383 int rval;
3384 uint16_t dc;
3385 uint32_t dw;
18e7555a
AV		 3386
3387 if (!IS_QLA81XX(vha->hw))
3388 return QLA_SUCCESS;
3389
3390 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
3391 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3392 ql_log(ql_log_warn, vha, 0x0105,
3393 "Unable to acquire semaphore.\n");
18e7555a
AV		 3394 goto done;
3395 }
3396
3397 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
3398 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
3399 if (rval != QLA_SUCCESS) {
7c3df132 3400 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 3401 goto done_release;
3402 }
3403
3404 dc &= MPS_MASK;
3405 if (dc == (dw & MPS_MASK))
3406 goto done_release;
3407
3408 dw &= ~MPS_MASK;
3409 dw |= dc;
3410 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
3411 if (rval != QLA_SUCCESS) {
7c3df132 3412 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 3413 }
3414
3415done_release:
3416 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
3417 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3418 ql_log(ql_log_warn, vha, 0x006d,
3419 "Unable to release semaphore.\n");
18e7555a
AV		 3420 }
3421
3422done:
3423 return rval;
3424}
3425
8d93f550
CD		 3426int
3427qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
3428{
3429 /* Don't try to reallocate the array */
3430 if (req->outstanding_cmds)
3431 return QLA_SUCCESS;
3432
d7459527 3433 if (!IS_FWI2_CAPABLE(ha))
8d93f550
CD		 3434 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
3435 else {
03e8c680
QT		 3436 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
3437 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 3438 else
03e8c680 3439 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 3440 }
3441
6396bb22
KC		 3442 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds,
3443 sizeof(srb_t *),
3444 GFP_KERNEL);
8d93f550
CD		 3445
3446 if (!req->outstanding_cmds) {
3447 /*
3448 * Try to allocate a minimal size just so we can get through
3449 * initialization.
3450 */
3451 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
6396bb22
KC		 3452 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds,
3453 sizeof(srb_t *),
3454 GFP_KERNEL);
8d93f550
CD		 3455
3456 if (!req->outstanding_cmds) {
3457 ql_log(ql_log_fatal, NULL, 0x0126,
3458 "Failed to allocate memory for "
3459 "outstanding_cmds for req_que %p.\n", req);
3460 req->num_outstanding_cmds = 0;
3461 return QLA_FUNCTION_FAILED;
3462 }
3463 }
3464
3465 return QLA_SUCCESS;
3466}
3467
e4e3a2ce
QT		 3468#define PRINT_FIELD(_field, _flag, _str) { \
3469 if (a0->_field & _flag) {\
3470 if (p) {\
3471 strcat(ptr, "|");\
3472 ptr++;\
3473 leftover--;\
3474 } \
3475 len = snprintf(ptr, leftover, "%s", _str); \
3476 p = 1;\
3477 leftover -= len;\
3478 ptr += len; \
3479 } \
3480}
3481
3482static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha)
3483{
3484#define STR_LEN 64
3485 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data;
3486 u8 str[STR_LEN], *ptr, p;
3487 int leftover, len;
3488
3489 memset(str, 0, STR_LEN);
3490 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name);
3491 ql_dbg(ql_dbg_init, vha, 0x015a,
3492 "SFP MFG Name: %s\n", str);
3493
3494 memset(str, 0, STR_LEN);
3495 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn);
3496 ql_dbg(ql_dbg_init, vha, 0x015c,
3497 "SFP Part Name: %s\n", str);
3498
3499 /* media */
3500 memset(str, 0, STR_LEN);
3501 ptr = str;
3502 leftover = STR_LEN;
3503 p = len = 0;
3504 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX");
3505 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair");
3506 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax");
3507 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax");
3508 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um");
3509 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um");
3510 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode");
3511 ql_dbg(ql_dbg_init, vha, 0x0160,
3512 "SFP Media: %s\n", str);
3513
3514 /* link length */
3515 memset(str, 0, STR_LEN);
3516 ptr = str;
3517 leftover = STR_LEN;
3518 p = len = 0;
3519 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long");
3520 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short");
3521 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate");
3522 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long");
3523 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium");
3524 ql_dbg(ql_dbg_init, vha, 0x0196,
3525 "SFP Link Length: %s\n", str);
3526
3527 memset(str, 0, STR_LEN);
3528 ptr = str;
3529 leftover = STR_LEN;
3530 p = len = 0;
3531 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)");
3532 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)");
3533 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)");
3534 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)");
3535 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)");
3536 ql_dbg(ql_dbg_init, vha, 0x016e,
3537 "SFP FC Link Tech: %s\n", str);
3538
3539 if (a0->length_km)
3540 ql_dbg(ql_dbg_init, vha, 0x016f,
3541 "SFP Distant: %d km\n", a0->length_km);
3542 if (a0->length_100m)
3543 ql_dbg(ql_dbg_init, vha, 0x0170,
3544 "SFP Distant: %d m\n", a0->length_100m*100);
3545 if (a0->length_50um_10m)
3546 ql_dbg(ql_dbg_init, vha, 0x0189,
3547 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10);
3548 if (a0->length_62um_10m)
3549 ql_dbg(ql_dbg_init, vha, 0x018a,
3550 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10);
3551 if (a0->length_om4_10m)
3552 ql_dbg(ql_dbg_init, vha, 0x0194,
3553 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10);
3554 if (a0->length_om3_10m)
3555 ql_dbg(ql_dbg_init, vha, 0x0195,
3556 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10);
3557}
3558
3559
3560/*
3561 * Return Code:
3562 * QLA_SUCCESS: no action
3563 * QLA_INTERFACE_ERROR: SFP is not there.
3564 * QLA_FUNCTION_FAILED: detected New SFP
3565 */
3566int
3567qla24xx_detect_sfp(scsi_qla_host_t *vha)
3568{
3569 int rc = QLA_SUCCESS;
3570 struct sff_8247_a0 *a;
3571 struct qla_hw_data *ha = vha->hw;
3572
3573 if (!AUTO_DETECT_SFP_SUPPORT(vha))
3574 goto out;
3575
3576 rc = qla2x00_read_sfp_dev(vha, NULL, 0);
3577 if (rc)
3578 goto out;
3579
3580 a = (struct sff_8247_a0 *)vha->hw->sfp_data;
3581 qla2xxx_print_sfp_info(vha);
3582
3583 if (a->fc_ll_cc7 & FC_LL_VL || a->fc_ll_cc7 & FC_LL_L) {
3584 /* long range */
3585 ha->flags.detected_lr_sfp = 1;
3586
3587 if (a->length_km > 5 || a->length_100m > 50)
3588 ha->long_range_distance = LR_DISTANCE_10K;
3589 else
3590 ha->long_range_distance = LR_DISTANCE_5K;
3591
3592 if (ha->flags.detected_lr_sfp != ha->flags.using_lr_setting)
3593 ql_dbg(ql_dbg_async, vha, 0x507b,
3594 "Detected Long Range SFP.\n");
3595 } else {
3596 /* short range */
3597 ha->flags.detected_lr_sfp = 0;
3598 if (ha->flags.using_lr_setting)
3599 ql_dbg(ql_dbg_async, vha, 0x5084,
3600 "Detected Short Range SFP.\n");
3601 }
3602
3603 if (!vha->flags.init_done)
3604 rc = QLA_SUCCESS;
3605out:
3606 return rc;
3607}
3608
1da177e4
LT		 3609/**
3610 * qla2x00_setup_chip() - Load and start RISC firmware.
2db6228d 3611 * @vha: HA context
1da177e4
LT		 3612 *
3613 * Returns 0 on success.
3614 */
3615static int
e315cd28 3616qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 3617{
0107109e
AV		 3618 int rval;
3619 uint32_t srisc_address = 0;
e315cd28 3620 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 3621 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
3622 unsigned long flags;
dda772e8 3623 uint16_t fw_major_version;
3db0652e 3624
7ec0effd 3625 if (IS_P3P_TYPE(ha)) {
a9083016 3626 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 3627 if (rval == QLA_SUCCESS) {
3628 qla2x00_stop_firmware(vha);
a9083016 3629 goto enable_82xx_npiv;
14e303d9 3630 } else
b963752f 3631 goto failed;
a9083016
GM		 3632 }
3633
3db0652e
AV		 3634 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3635 /* Disable SRAM, Instruction RAM and GP RAM parity. */
3636 spin_lock_irqsave(&ha->hardware_lock, flags);
3637 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
3638 RD_REG_WORD(&reg->hccr);
3639 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3640 }
1da177e4 3641
18e7555a
AV		 3642 qla81xx_mpi_sync(vha);
3643
1da177e4 3644 /* Load firmware sequences */
e315cd28 3645 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 3646 if (rval == QLA_SUCCESS) {
7c3df132
SK		 3647 ql_dbg(ql_dbg_init, vha, 0x00c9,
3648 "Verifying Checksum of loaded RISC code.\n");
1da177e4 3649
e315cd28 3650 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 3651 if (rval == QLA_SUCCESS) {
3652 /* Start firmware execution. */
7c3df132
SK		 3653 ql_dbg(ql_dbg_init, vha, 0x00ca,
3654 "Starting firmware.\n");
1da177e4 3655
b0d6cabd
HM		 3656 if (ql2xexlogins)
3657 ha->flags.exlogins_enabled = 1;
3658
99e1b683 3659 if (qla_is_exch_offld_enabled(vha))
2f56a7f1
HM		 3660 ha->flags.exchoffld_enabled = 1;
3661
e315cd28 3662 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 3663 /* Retrieve firmware information. */
dda772e8 3664 if (rval == QLA_SUCCESS) {
e4e3a2ce
QT		 3665 qla24xx_detect_sfp(vha);
3666
ecc89f25
JC		 3667 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3668 IS_QLA28XX(ha)) &&
8b4673ba
QT		 3669 (ha->zio_mode == QLA_ZIO_MODE_6))
3670 qla27xx_set_zio_threshold(vha,
3671 ha->last_zio_threshold);
3672
b0d6cabd
HM		 3673 rval = qla2x00_set_exlogins_buffer(vha);
3674 if (rval != QLA_SUCCESS)
3675 goto failed;
3676
2f56a7f1
HM		 3677 rval = qla2x00_set_exchoffld_buffer(vha);
3678 if (rval != QLA_SUCCESS)
3679 goto failed;
3680
a9083016 3681enable_82xx_npiv:
dda772e8 3682 fw_major_version = ha->fw_major_version;
7ec0effd 3683 if (IS_P3P_TYPE(ha))
3173167f 3684 qla82xx_check_md_needed(vha);
6246b8a1
GM		 3685 else
3686 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 3687 if (rval != QLA_SUCCESS)
3688 goto failed;
2c3dfe3f 3689 ha->flags.npiv_supported = 0;
e315cd28 3690 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 3691 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 3692 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 3693 if ((!ha->max_npiv_vports) ||
3694 ((ha->max_npiv_vports + 1) %
eb66dc60 3695 MIN_MULTI_ID_FABRIC))
4d0ea247 3696 ha->max_npiv_vports =
eb66dc60 3697 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 3698 }
03e8c680 3699 qla2x00_get_resource_cnts(vha);
d743de66 3700
8d93f550
CD		 3701 /*
3702 * Allocate the array of outstanding commands
3703 * now that we know the firmware resources.
3704 */
3705 rval = qla2x00_alloc_outstanding_cmds(ha,
3706 vha->req);
3707 if (rval != QLA_SUCCESS)
3708 goto failed;
3709
ad0a0b01
QT		 3710 if (!fw_major_version && !(IS_P3P_TYPE(ha)))
3711 qla2x00_alloc_offload_mem(vha);
3712
3713 if (ql2xallocfwdump && !(IS_P3P_TYPE(ha)))
08de2844 3714 qla2x00_alloc_fw_dump(vha);
ad0a0b01 3715
3b6e5b9d
CD		 3716 } else {
3717 goto failed;
1da177e4
LT		 3718 }
3719 } else {
7c3df132
SK		 3720 ql_log(ql_log_fatal, vha, 0x00cd,
3721 "ISP Firmware failed checksum.\n");
3722 goto failed;
1da177e4 3723 }
c74d88a4
AV		 3724 } else
3725 goto failed;
1da177e4 3726
3db0652e
AV		 3727 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3728 /* Enable proper parity. */
3729 spin_lock_irqsave(&ha->hardware_lock, flags);
3730 if (IS_QLA2300(ha))
3731 /* SRAM parity */
3732 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
3733 else
3734 /* SRAM, Instruction RAM and GP RAM parity */
3735 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
3736 RD_REG_WORD(&reg->hccr);
3737 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3738 }
3739
ecc89f25 3740 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
f3982d89
CD		 3741 ha->flags.fac_supported = 1;
3742 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 3743 uint32_t size;
3744
3745 rval = qla81xx_fac_get_sector_size(vha, &size);
3746 if (rval == QLA_SUCCESS) {
3747 ha->flags.fac_supported = 1;
3748 ha->fdt_block_size = size << 2;
3749 } else {
7c3df132 3750 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 3751 "Unsupported FAC firmware (%d.%02d.%02d).\n",
3752 ha->fw_major_version, ha->fw_minor_version,
3753 ha->fw_subminor_version);
1ca60e3b 3754
ecc89f25
JC		 3755 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3756 IS_QLA28XX(ha)) {
6246b8a1
GM		 3757 ha->flags.fac_supported = 0;
3758 rval = QLA_SUCCESS;
3759 }
1d2874de
JC		 3760 }
3761 }
ca9e9c3e 3762failed:
1da177e4 3763 if (rval) {
7c3df132
SK		 3764 ql_log(ql_log_fatal, vha, 0x00cf,
3765 "Setup chip ****FAILED****.\n");
1da177e4
LT		 3766 }
3767
3768 return (rval);
3769}
3770
3771/**
3772 * qla2x00_init_response_q_entries() - Initializes response queue entries.
2db6228d 3773 * @rsp: response queue
1da177e4
LT		 3774 *
3775 * Beginning of request ring has initialization control block already built
3776 * by nvram config routine.
3777 *
3778 * Returns 0 on success.
3779 */
73208dfd
AC		 3780void
3781qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 3782{
3783 uint16_t cnt;
3784 response_t *pkt;
3785
2afa19a9
AC		 3786 rsp->ring_ptr = rsp->ring;
3787 rsp->ring_index = 0;
3788 rsp->status_srb = NULL;
e315cd28
AC		 3789 pkt = rsp->ring_ptr;
3790 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 3791 pkt->signature = RESPONSE_PROCESSED;
3792 pkt++;
3793 }
1da177e4
LT		 3794}
3795
3796/**
3797 * qla2x00_update_fw_options() - Read and process firmware options.
2db6228d 3798 * @vha: HA context
1da177e4
LT		 3799 *
3800 * Returns 0 on success.
3801 */
abbd8870 3802void
e315cd28 3803qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 3804{
3805 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 3806 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3807
3808 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 3809 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 3810
3811 if (IS_QLA2100(ha) || IS_QLA2200(ha))
3812 return;
3813
3814 /* Serial Link options. */
7c3df132
SK		 3815 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
3816 "Serial link options.\n");
3817 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
f8f97b0c 3818 ha->fw_seriallink_options, sizeof(ha->fw_seriallink_options));
1da177e4
LT		 3819
3820 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
3821 if (ha->fw_seriallink_options[3] & BIT_2) {
3822 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
3823
3824 /* 1G settings */
3825 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
3826 emphasis = (ha->fw_seriallink_options[2] &
3827 (BIT_4 | BIT_3)) >> 3;
3828 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 3829 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3830 rx_sens = (ha->fw_seriallink_options[0] &
3831 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3832 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
3833 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3834 if (rx_sens == 0x0)
3835 rx_sens = 0x3;
3836 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
3837 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3838 ha->fw_options[10] |= BIT_5 |
3839 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3840 (tx_sens & (BIT_1 | BIT_0));
3841
3842 /* 2G settings */
3843 swing = (ha->fw_seriallink_options[2] &
3844 (BIT_7 | BIT_6 | BIT_5)) >> 5;
3845 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
3846 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 3847 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3848 rx_sens = (ha->fw_seriallink_options[1] &
3849 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3850 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
3851 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3852 if (rx_sens == 0x0)
3853 rx_sens = 0x3;
3854 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
3855 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3856 ha->fw_options[11] |= BIT_5 |
3857 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3858 (tx_sens & (BIT_1 | BIT_0));
3859 }
3860
3861 /* FCP2 options. */
3862 /* Return command IOCBs without waiting for an ABTS to complete. */
3863 ha->fw_options[3] |= BIT_13;
3864
3865 /* LED scheme. */
3866 if (ha->flags.enable_led_scheme)
3867 ha->fw_options[2] |= BIT_12;
3868
48c02fde 3869 /* Detect ISP6312. */
3870 if (IS_QLA6312(ha))
3871 ha->fw_options[2] |= BIT_13;
3872
088d09d4
GM		 3873 /* Set Retry FLOGI in case of P2P connection */
3874 if (ha->operating_mode == P2P) {
3875 ha->fw_options[2] |= BIT_3;
3876 ql_dbg(ql_dbg_disc, vha, 0x2100,
3877 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3878 __func__, ha->fw_options[2]);
3879 }
3880
1da177e4 3881 /* Update firmware options. */
e315cd28 3882 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 3883}
3884
0107109e 3885void
e315cd28 3886qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 3887{
3888 int rval;
e315cd28 3889 struct qla_hw_data *ha = vha->hw;
0107109e 3890
7ec0effd 3891 if (IS_P3P_TYPE(ha))
a9083016
GM		 3892 return;
3893
f198cafa
HM		 3894 /* Hold status IOCBs until ABTS response received. */
3895 if (ql2xfwholdabts)
3896 ha->fw_options[3] |= BIT_12;
3897
088d09d4
GM		 3898 /* Set Retry FLOGI in case of P2P connection */
3899 if (ha->operating_mode == P2P) {
3900 ha->fw_options[2] |= BIT_3;
3901 ql_dbg(ql_dbg_disc, vha, 0x2101,
3902 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3903 __func__, ha->fw_options[2]);
3904 }
3905
41dc529a 3906 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
3c4810ff 3907 if (ql2xmvasynctoatio &&
ecc89f25 3908 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
41dc529a
QT		 3909 if (qla_tgt_mode_enabled(vha) ||
3910 qla_dual_mode_enabled(vha))
3911 ha->fw_options[2] |= BIT_11;
3912 else
3913 ha->fw_options[2] &= ~BIT_11;
3914 }
3915
ecc89f25
JC		 3916 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3917 IS_QLA28XX(ha)) {
f7e761f5
QT		 3918 /*
3919 * Tell FW to track each exchange to prevent
3920 * driver from using stale exchange.
3921 */
3922 if (qla_tgt_mode_enabled(vha) ||
3923 qla_dual_mode_enabled(vha))
3924 ha->fw_options[2] |= BIT_4;
3925 else
3926 ha->fw_options[2] &= ~BIT_4;
9ecf0b0d
QT		 3927
3928 /* Reserve 1/2 of emergency exchanges for ELS.*/
3929 if (qla2xuseresexchforels)
3930 ha->fw_options[2] |= BIT_8;
3931 else
3932 ha->fw_options[2] &= ~BIT_8;
f7e761f5
QT		 3933 }
3934
83548fe2
QT		 3935 ql_dbg(ql_dbg_init, vha, 0x00e8,
3936 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
3937 __func__, ha->fw_options[1], ha->fw_options[2],
3938 ha->fw_options[3], vha->host->active_mode);
3c4810ff
QT		 3939
3940 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
3941 qla2x00_set_fw_options(vha, ha->fw_options);
41dc529a 3942
0107109e 3943 /* Update Serial Link options. */
f94097ed 3944 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 3945 return;
3946
e315cd28 3947 rval = qla2x00_set_serdes_params(vha,
f94097ed 3948 le16_to_cpu(ha->fw_seriallink_options24[1]),
3949 le16_to_cpu(ha->fw_seriallink_options24[2]),
3950 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 3951 if (rval != QLA_SUCCESS) {
7c3df132 3952 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 3953 "Unable to update Serial Link options (%x).\n", rval);
3954 }
3955}
3956
abbd8870 3957void
e315cd28 3958qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 3959{
e315cd28 3960 struct qla_hw_data *ha = vha->hw;
3d71644c 3961 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 3962 struct req_que *req = ha->req_q_map[0];
3963 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 3964
3965 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 3966 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
3967 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3968 ha->init_cb->request_q_length = cpu_to_le16(req->length);
3969 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
d4556a49
BVA		 3970 put_unaligned_le64(req->dma, &ha->init_cb->request_q_address);
3971 put_unaligned_le64(rsp->dma, &ha->init_cb->response_q_address);
abbd8870
AV		 3972
3973 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
3974 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
3975 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
3976 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
3977 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
3978}
3979
0107109e 3980void
e315cd28 3981qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 3982{
e315cd28 3983 struct qla_hw_data *ha = vha->hw;
118e2ef9 3984 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 3985 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
3986 struct qla_msix_entry *msix;
0107109e 3987 struct init_cb_24xx *icb;
73208dfd
AC		 3988 uint16_t rid = 0;
3989 struct req_que *req = ha->req_q_map[0];
3990 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 3991
6246b8a1 3992 /* Setup ring parameters in initialization control block. */
0107109e 3993 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 3994 icb->request_q_outpointer = cpu_to_le16(0);
3995 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3996 icb->request_q_length = cpu_to_le16(req->length);
3997 icb->response_q_length = cpu_to_le16(rsp->length);
d4556a49
BVA		 3998 put_unaligned_le64(req->dma, &icb->request_q_address);
3999 put_unaligned_le64(rsp->dma, &icb->response_q_address);
0107109e 4000
2d70c103 4001 /* Setup ATIO queue dma pointers for target mode */
ad950360 4002 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103 4003 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
d4556a49 4004 put_unaligned_le64(ha->tgt.atio_dma, &icb->atio_q_address);
2d70c103 4005
7c6300e3 4006 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 4007 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 4008
ecc89f25
JC		 4009 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
4010 IS_QLA28XX(ha)) {
ad950360
BVA		 4011 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
4012 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 4013 if (ha->flags.msix_enabled) {
4014 msix = &ha->msix_entries[1];
83548fe2 4015 ql_dbg(ql_dbg_init, vha, 0x0019,
7c3df132
SK		 4016 "Registering vector 0x%x for base que.\n",
4017 msix->entry);
73208dfd
AC		 4018 icb->msix = cpu_to_le16(msix->entry);
4019 }
4020 /* Use alternate PCI bus number */
4021 if (MSB(rid))
ad950360 4022 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 4023 /* Use alternate PCI devfn */
4024 if (LSB(rid))
ad950360 4025 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 4026
3155754a 4027 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 4028 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
4029 (ha->flags.msix_enabled)) {
ad950360 4030 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 4031 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 4032 ql_dbg(ql_dbg_init, vha, 0x00fe,
4033 "MSIX Handshake Disable Mode turned on.\n");
3155754a 4034 } else {
ad950360 4035 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 4036 }
ad950360 4037 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 4038
4039 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
4040 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
4041 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
4042 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
4043 } else {
4044 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
4045 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
4046 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
4047 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
4048 }
4910b524 4049
aa230bc5 4050 qlt_24xx_config_rings(vha);
2d70c103 4051
4910b524
AG		 4052 /* If the user has configured the speed, set it here */
4053 if (ha->set_data_rate) {
4054 ql_dbg(ql_dbg_init, vha, 0x00fd,
4055 "Speed set by user : %s Gbps \n",
4056 qla2x00_get_link_speed_str(ha, ha->set_data_rate));
4057 icb->firmware_options_3 = (ha->set_data_rate << 13);
4058 }
4059
73208dfd
AC		 4060 /* PCI posting */
4061 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 4062}
4063
1da177e4
LT		 4064/**
4065 * qla2x00_init_rings() - Initializes firmware.
2db6228d 4066 * @vha: HA context
1da177e4
LT		 4067 *
4068 * Beginning of request ring has initialization control block already built
4069 * by nvram config routine.
4070 *
4071 * Returns 0 on success.
4072 */
8ae6d9c7 4073int
e315cd28 4074qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 4075{
4076 int rval;
4077 unsigned long flags = 0;
29bdccbe 4078 int cnt, que;
e315cd28 4079 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 4080 struct req_que *req;
4081 struct rsp_que *rsp;
2c3dfe3f
SJ		 4082 struct mid_init_cb_24xx *mid_init_cb =
4083 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 4084
4085 spin_lock_irqsave(&ha->hardware_lock, flags);
4086
4087 /* Clear outstanding commands array. */
2afa19a9 4088 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 4089 req = ha->req_q_map[que];
cb43285f 4090 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 4091 continue;
7c6300e3
JC		 4092 req->out_ptr = (void *)(req->ring + req->length);
4093 *req->out_ptr = 0;
8d93f550 4094 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 4095 req->outstanding_cmds[cnt] = NULL;
1da177e4 4096
2afa19a9 4097 req->current_outstanding_cmd = 1;
1da177e4 4098
29bdccbe
AC		 4099 /* Initialize firmware. */
4100 req->ring_ptr = req->ring;
4101 req->ring_index = 0;
4102 req->cnt = req->length;
4103 }
1da177e4 4104
2afa19a9 4105 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 4106 rsp = ha->rsp_q_map[que];
cb43285f 4107 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 4108 continue;
7c6300e3
JC		 4109 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
4110 *rsp->in_ptr = 0;
29bdccbe 4111 /* Initialize response queue entries */
8ae6d9c7
GM		 4112 if (IS_QLAFX00(ha))
4113 qlafx00_init_response_q_entries(rsp);
4114 else
4115 qla2x00_init_response_q_entries(rsp);
29bdccbe 4116 }
1da177e4 4117
2d70c103
NB		 4118 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
4119 ha->tgt.atio_ring_index = 0;
4120 /* Initialize ATIO queue entries */
4121 qlt_init_atio_q_entries(vha);
4122
e315cd28 4123 ha->isp_ops->config_rings(vha);
1da177e4
LT		 4124
4125 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4126
8ae6d9c7
GM		 4127 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
4128
4129 if (IS_QLAFX00(ha)) {
4130 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
4131 goto next_check;
4132 }
4133
1da177e4 4134 /* Update any ISP specific firmware options before initialization. */
e315cd28 4135 ha->isp_ops->update_fw_options(vha);
1da177e4 4136
605aa2bc 4137 if (ha->flags.npiv_supported) {
45980cc2 4138 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 4139 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 4140 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 4141 }
4142
24a08138 4143 if (IS_FWI2_CAPABLE(ha)) {
ad950360 4144 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 4145 mid_init_cb->init_cb.execution_throttle =
03e8c680 4146 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 4147 ha->flags.dport_enabled =
4148 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
4149 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
4150 (ha->flags.dport_enabled) ? "enabled" : "disabled");
4151 /* FA-WWPN Status */
2486c627 4152 ha->flags.fawwpn_enabled =
40f3862b 4153 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
83548fe2 4154 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n",
2486c627 4155 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 4156 }
2c3dfe3f 4157
e315cd28 4158 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 4159next_check:
1da177e4 4160 if (rval) {
7c3df132
SK		 4161 ql_log(ql_log_fatal, vha, 0x00d2,
4162 "Init Firmware **** FAILED ****.\n");
1da177e4 4163 } else {
7c3df132
SK		 4164 ql_dbg(ql_dbg_init, vha, 0x00d3,
4165 "Init Firmware -- success.\n");
4b60c827 4166 QLA_FW_STARTED(ha);
0645cb83 4167 vha->u_ql2xexchoffld = vha->u_ql2xiniexchg = 0;
1da177e4
LT		 4168 }
4169
4170 return (rval);
4171}
4172
4173/**
4174 * qla2x00_fw_ready() - Waits for firmware ready.
2db6228d 4175 * @vha: HA context
1da177e4
LT		 4176 *
4177 * Returns 0 on success.
4178 */
4179static int
e315cd28 4180qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 4181{
4182 int rval;
4d4df193 4183 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 4184 uint16_t min_wait; /* Minimum wait time if loop is down */
4185 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 4186 uint16_t state[6];
e315cd28 4187 struct qla_hw_data *ha = vha->hw;
1da177e4 4188
8ae6d9c7
GM		 4189 if (IS_QLAFX00(vha->hw))
4190 return qlafx00_fw_ready(vha);
4191
1da177e4
LT		 4192 rval = QLA_SUCCESS;
4193
33461491
CD		 4194 /* Time to wait for loop down */
4195 if (IS_P3P_TYPE(ha))
4196 min_wait = 30;
4197 else
4198 min_wait = 20;
1da177e4
LT		 4199
4200 /*
4201 * Firmware should take at most one RATOV to login, plus 5 seconds for
4202 * our own processing.
4203 */
4204 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
4205 wait_time = min_wait;
4206 }
4207
4208 /* Min wait time if loop down */
4209 mtime = jiffies + (min_wait * HZ);
4210
4211 /* wait time before firmware ready */
4212 wtime = jiffies + (wait_time * HZ);
4213
4214 /* Wait for ISP to finish LIP */
e315cd28 4215 if (!vha->flags.init_done)
7c3df132
SK		 4216 ql_log(ql_log_info, vha, 0x801e,
4217 "Waiting for LIP to complete.\n");
1da177e4
LT		 4218
4219 do {
5b939038 4220 memset(state, -1, sizeof(state));
e315cd28 4221 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 4222 if (rval == QLA_SUCCESS) {
4d4df193 4223 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 4224 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 4225 }
4d4df193 4226 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 4227 ql_dbg(ql_dbg_taskm, vha, 0x801f,
4228 "fw_state=%x 84xx=%x.\n", state[0],
4229 state[2]);
4d4df193
HK		 4230 if ((state[2] & FSTATE_LOGGED_IN) &&
4231 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 4232 ql_dbg(ql_dbg_taskm, vha, 0x8028,
4233 "Sending verify iocb.\n");
4d4df193
HK		 4234
4235 cs84xx_time = jiffies;
e315cd28 4236 rval = qla84xx_init_chip(vha);
7c3df132
SK		 4237 if (rval != QLA_SUCCESS) {
4238 ql_log(ql_log_warn,
cfb0919c 4239 vha, 0x8007,
7c3df132 4240 "Init chip failed.\n");
4d4df193 4241 break;
7c3df132 4242 }
4d4df193
HK		 4243
4244 /* Add time taken to initialize. */
4245 cs84xx_time = jiffies - cs84xx_time;
4246 wtime += cs84xx_time;
4247 mtime += cs84xx_time;
cfb0919c 4248 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 4249 "Increasing wait time by %ld. "
4250 "New time %ld.\n", cs84xx_time,
4251 wtime);
4d4df193
HK		 4252 }
4253 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 4254 ql_dbg(ql_dbg_taskm, vha, 0x8037,
4255 "F/W Ready - OK.\n");
1da177e4 4256
e315cd28 4257 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 4258 &ha->login_timeout, &ha->r_a_tov);
4259
4260 rval = QLA_SUCCESS;
4261 break;
4262 }
4263
4264 rval = QLA_FUNCTION_FAILED;
4265
e315cd28 4266 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 4267 state[0] != FSTATE_READY) {
1da177e4 4268 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 4269 * other than Wait for Login.
4270 */
1da177e4 4271 if (time_after_eq(jiffies, mtime)) {
7c3df132 4272 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 4273 "Cable is unplugged...\n");
4274
e315cd28 4275 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 4276 break;
4277 }
4278 }
4279 } else {
4280 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 4281 if (time_after_eq(jiffies, mtime) ||
7190575f 4282 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 4283 break;
4284 }
4285
4286 if (time_after_eq(jiffies, wtime))
4287 break;
4288
4289 /* Delay for a while */
4290 msleep(500);
1da177e4
LT		 4291 } while (1);
4292
7c3df132 4293 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 4294 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
4295 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 4296
cfb0919c 4297 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 4298 ql_log(ql_log_warn, vha, 0x803b,
4299 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 4300 }
4301
4302 return (rval);
4303}
4304
4305/*
4306* qla2x00_configure_hba
4307* Setup adapter context.
4308*
4309* Input:
4310* ha = adapter state pointer.
4311*
4312* Returns:
4313* 0 = success
4314*
4315* Context:
4316* Kernel context.
4317*/
4318static int
e315cd28 4319qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 4320{
4321 int rval;
4322 uint16_t loop_id;
4323 uint16_t topo;
2c3dfe3f 4324 uint16_t sw_cap;
1da177e4
LT		 4325 uint8_t al_pa;
4326 uint8_t area;
4327 uint8_t domain;
4328 char connect_type[22];
e315cd28 4329 struct qla_hw_data *ha = vha->hw;
61e1b269 4330 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
482c9dc7 4331 port_id_t id;
9d1aa4e1 4332 unsigned long flags;
1da177e4
LT		 4333
4334 /* Get host addresses. */
e315cd28 4335 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 4336 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 4337 if (rval != QLA_SUCCESS) {
e315cd28 4338 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 4339 IS_CNA_CAPABLE(ha) ||
33135aa2 4340 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 4341 ql_dbg(ql_dbg_disc, vha, 0x2008,
4342 "Loop is in a transition state.\n");
33135aa2 4343 } else {
7c3df132
SK		 4344 ql_log(ql_log_warn, vha, 0x2009,
4345 "Unable to get host loop ID.\n");
61e1b269
JC		 4346 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
4347 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
4348 ql_log(ql_log_warn, vha, 0x1151,
4349 "Doing link init.\n");
4350 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
4351 return rval;
4352 }
e315cd28 4353 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 4354 }
1da177e4
LT		 4355 return (rval);
4356 }
4357
4358 if (topo == 4) {
7c3df132
SK		 4359 ql_log(ql_log_info, vha, 0x200a,
4360 "Cannot get topology - retrying.\n");
1da177e4
LT		 4361 return (QLA_FUNCTION_FAILED);
4362 }
4363
e315cd28 4364 vha->loop_id = loop_id;
1da177e4
LT		 4365
4366 /* initialize */
4367 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
4368 ha->operating_mode = LOOP;
2c3dfe3f 4369 ha->switch_cap = 0;
1da177e4
LT		 4370
4371 switch (topo) {
4372 case 0:
7c3df132 4373 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 4374 ha->current_topology = ISP_CFG_NL;
4375 strcpy(connect_type, "(Loop)");
4376 break;
4377
4378 case 1:
7c3df132 4379 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 4380 ha->switch_cap = sw_cap;
1da177e4
LT		 4381 ha->current_topology = ISP_CFG_FL;
4382 strcpy(connect_type, "(FL_Port)");
4383 break;
4384
4385 case 2:
7c3df132 4386 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 4387 ha->operating_mode = P2P;
4388 ha->current_topology = ISP_CFG_N;
4389 strcpy(connect_type, "(N_Port-to-N_Port)");
4390 break;
4391
4392 case 3:
7c3df132 4393 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 4394 ha->switch_cap = sw_cap;
1da177e4
LT		 4395 ha->operating_mode = P2P;
4396 ha->current_topology = ISP_CFG_F;
4397 strcpy(connect_type, "(F_Port)");
4398 break;
4399
4400 default:
7c3df132
SK		 4401 ql_dbg(ql_dbg_disc, vha, 0x200f,
4402 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 4403 ha->current_topology = ISP_CFG_NL;
4404 strcpy(connect_type, "(Loop)");
4405 break;
4406 }
4407
4408 /* Save Host port and loop ID. */
4409 /* byte order - Big Endian */
482c9dc7
QT		 4410 id.b.domain = domain;
4411 id.b.area = area;
4412 id.b.al_pa = al_pa;
4413 id.b.rsvd_1 = 0;
9d1aa4e1 4414 spin_lock_irqsave(&ha->hardware_lock, flags);
8777e431
QT		 4415 if (!(topo == 2 && ha->flags.n2n_bigger))
4416 qlt_update_host_map(vha, id);
9d1aa4e1 4417 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2d70c103 4418
e315cd28 4419 if (!vha->flags.init_done)
7c3df132
SK		 4420 ql_log(ql_log_info, vha, 0x2010,
4421 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 4422 connect_type, vha->loop_id);
1da177e4 4423
1da177e4
LT		 4424 return(rval);
4425}
4426
a9083016 4427inline void
e315cd28 4428qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
bc97c948 4429 const char *def)
9bb9fcf2
AV		 4430{
4431 char *st, *en;
4432 uint16_t index;
a28d9e4e 4433 uint64_t zero[2] = { 0 };
e315cd28 4434 struct qla_hw_data *ha = vha->hw;
ab671149 4435 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 4436 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2 4437
a28d9e4e
JC		 4438 if (len > sizeof(zero))
4439 len = sizeof(zero);
4440 if (memcmp(model, &zero, len) != 0) {
9bb9fcf2
AV		 4441 strncpy(ha->model_number, model, len);
4442 st = en = ha->model_number;
4443 en += len - 1;
4444 while (en > st) {
4445 if (*en != 0x20 && *en != 0x00)
4446 break;
4447 *en-- = '\0';
4448 }
4449
4450 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 4451 if (use_tbl &&
4452 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 4453 index < QLA_MODEL_NAMES)
1ee27146
JC		 4454 strncpy(ha->model_desc,
4455 qla2x00_model_name[index * 2 + 1],
4456 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 4457 } else {
4458 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 4459 if (use_tbl &&
4460 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 4461 index < QLA_MODEL_NAMES) {
4462 strcpy(ha->model_number,
4463 qla2x00_model_name[index * 2]);
1ee27146
JC		 4464 strncpy(ha->model_desc,
4465 qla2x00_model_name[index * 2 + 1],
4466 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 4467 } else {
4468 strcpy(ha->model_number, def);
4469 }
4470 }
1ee27146 4471 if (IS_FWI2_CAPABLE(ha))
e315cd28 4472 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 4473 sizeof(ha->model_desc));
9bb9fcf2
AV		 4474}
4475
4e08df3f
DM		 4476/* On sparc systems, obtain port and node WWN from firmware
4477 * properties.
4478 */
e315cd28 4479static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 4480{
4481#ifdef CONFIG_SPARC
e315cd28 4482 struct qla_hw_data *ha = vha->hw;
4e08df3f 4483 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4484 struct device_node *dp = pci_device_to_OF_node(pdev);
4485 const u8 *val;
4e08df3f
DM		 4486 int len;
4487
4488 val = of_get_property(dp, "port-wwn", &len);
4489 if (val && len >= WWN_SIZE)
4490 memcpy(nv->port_name, val, WWN_SIZE);
4491
4492 val = of_get_property(dp, "node-wwn", &len);
4493 if (val && len >= WWN_SIZE)
4494 memcpy(nv->node_name, val, WWN_SIZE);
4495#endif
4496}
4497
1da177e4
LT		 4498/*
4499* NVRAM configuration for ISP 2xxx
4500*
4501* Input:
4502* ha = adapter block pointer.
4503*
4504* Output:
4505* initialization control block in response_ring
4506* host adapters parameters in host adapter block
4507*
4508* Returns:
4509* 0 = success.
4510*/
abbd8870 4511int
e315cd28 4512qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 4513{
4e08df3f 4514 int rval;
0107109e
AV		 4515 uint8_t chksum = 0;
4516 uint16_t cnt;
4517 uint8_t *dptr1, *dptr2;
e315cd28 4518 struct qla_hw_data *ha = vha->hw;
0107109e 4519 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 4520 nvram_t *nv = ha->nvram;
4521 uint8_t *ptr = ha->nvram;
3d71644c 4522 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4523
4e08df3f
DM		 4524 rval = QLA_SUCCESS;
4525
1da177e4 4526 /* Determine NVRAM starting address. */
f8f97b0c 4527 ha->nvram_size = sizeof(*nv);
1da177e4
LT		 4528 ha->nvram_base = 0;
4529 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
4530 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
4531 ha->nvram_base = 0x80;
4532
4533 /* Get NVRAM data and calculate checksum. */
e315cd28 4534 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 4535 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
4536 chksum += *ptr++;
1da177e4 4537
7c3df132
SK		 4538 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
4539 "Contents of NVRAM.\n");
4540 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
f8f97b0c 4541 nv, ha->nvram_size);
1da177e4
LT		 4542
4543 /* Bad NVRAM data, set defaults parameters. */
a28d9e4e
JC		 4544 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
4545 nv->nvram_version < 1) {
1da177e4 4546 /* Reset NVRAM data. */
7c3df132 4547 ql_log(ql_log_warn, vha, 0x0064,
3695310e
JC		 4548 "Inconsistent NVRAM detected: checksum=%#x id=%.4s version=%#x.\n",
4549 chksum, nv->id, nv->nvram_version);
7c3df132
SK		 4550 ql_log(ql_log_warn, vha, 0x0065,
4551 "Falling back to "
4552 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 4553
4554 /*
4555 * Set default initialization control block.
4556 */
4557 memset(nv, 0, ha->nvram_size);
4558 nv->parameter_block_version = ICB_VERSION;
4559
4560 if (IS_QLA23XX(ha)) {
4561 nv->firmware_options[0] = BIT_2 | BIT_1;
4562 nv->firmware_options[1] = BIT_7 | BIT_5;
4563 nv->add_firmware_options[0] = BIT_5;
4564 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 4565 nv->frame_payload_size = 2048;
4e08df3f
DM		 4566 nv->special_options[1] = BIT_7;
4567 } else if (IS_QLA2200(ha)) {
4568 nv->firmware_options[0] = BIT_2 | BIT_1;
4569 nv->firmware_options[1] = BIT_7 | BIT_5;
4570 nv->add_firmware_options[0] = BIT_5;
4571 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 4572 nv->frame_payload_size = 1024;
4e08df3f
DM		 4573 } else if (IS_QLA2100(ha)) {
4574 nv->firmware_options[0] = BIT_3 | BIT_1;
4575 nv->firmware_options[1] = BIT_5;
98aee70d 4576 nv->frame_payload_size = 1024;
4e08df3f
DM		 4577 }
4578
ad950360
BVA		 4579 nv->max_iocb_allocation = cpu_to_le16(256);
4580 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 4581 nv->retry_count = 8;
4582 nv->retry_delay = 1;
4583
4584 nv->port_name[0] = 33;
4585 nv->port_name[3] = 224;
4586 nv->port_name[4] = 139;
4587
e315cd28 4588 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4589
4590 nv->login_timeout = 4;
4591
4592 /*
4593 * Set default host adapter parameters
4594 */
4595 nv->host_p[1] = BIT_2;
4596 nv->reset_delay = 5;
4597 nv->port_down_retry_count = 8;
ad950360 4598 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 4599 nv->link_down_timeout = 60;
4600
4601 rval = 1;
1da177e4
LT		 4602 }
4603
4604#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
4605 /*
4606 * The SN2 does not provide BIOS emulation which means you can't change
4607 * potentially bogus BIOS settings. Force the use of default settings
4608 * for link rate and frame size. Hope that the rest of the settings
4609 * are valid.
4610 */
4611 if (ia64_platform_is("sn2")) {
98aee70d 4612 nv->frame_payload_size = 2048;
1da177e4
LT		 4613 if (IS_QLA23XX(ha))
4614 nv->special_options[1] = BIT_7;
4615 }
4616#endif
4617
4618 /* Reset Initialization control block */
0107109e 4619 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 4620
4621 /*
4622 * Setup driver NVRAM options.
4623 */
4624 nv->firmware_options[0] |= (BIT_6 | BIT_1);
4625 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
4626 nv->firmware_options[1] |= (BIT_5 | BIT_0);
4627 nv->firmware_options[1] &= ~BIT_4;
4628
4629 if (IS_QLA23XX(ha)) {
4630 nv->firmware_options[0] |= BIT_2;
4631 nv->firmware_options[0] &= ~BIT_3;
2d70c103 4632 nv->special_options[0] &= ~BIT_6;
0107109e 4633 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 4634
4635 if (IS_QLA2300(ha)) {
4636 if (ha->fb_rev == FPM_2310) {
4637 strcpy(ha->model_number, "QLA2310");
4638 } else {
4639 strcpy(ha->model_number, "QLA2300");
4640 }
4641 } else {
e315cd28 4642 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 4643 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 4644 }
4645 } else if (IS_QLA2200(ha)) {
4646 nv->firmware_options[0] |= BIT_2;
4647 /*
4648 * 'Point-to-point preferred, else loop' is not a safe
4649 * connection mode setting.
4650 */
4651 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
4652 (BIT_5 | BIT_4)) {
4653 /* Force 'loop preferred, else point-to-point'. */
4654 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
4655 nv->add_firmware_options[0] |= BIT_5;
4656 }
4657 strcpy(ha->model_number, "QLA22xx");
4658 } else /*if (IS_QLA2100(ha))*/ {
4659 strcpy(ha->model_number, "QLA2100");
4660 }
4661
4662 /*
4663 * Copy over NVRAM RISC parameter block to initialization control block.
4664 */
4665 dptr1 = (uint8_t *)icb;
4666 dptr2 = (uint8_t *)&nv->parameter_block_version;
4667 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
4668 while (cnt--)
4669 *dptr1++ = *dptr2++;
4670
4671 /* Copy 2nd half. */
4672 dptr1 = (uint8_t *)icb->add_firmware_options;
4673 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
4674 while (cnt--)
4675 *dptr1++ = *dptr2++;
0eaaca4c 4676 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
5341e868
AV		 4677 /* Use alternate WWN? */
4678 if (nv->host_p[1] & BIT_7) {
4679 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4680 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4681 }
4682
1da177e4
LT		 4683 /* Prepare nodename */
4684 if ((icb->firmware_options[1] & BIT_6) == 0) {
4685 /*
4686 * Firmware will apply the following mask if the nodename was
4687 * not provided.
4688 */
4689 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4690 icb->node_name[0] &= 0xF0;
4691 }
4692
4693 /*
4694 * Set host adapter parameters.
4695 */
3ce8866c
SK		 4696
4697 /*
4698 * BIT_7 in the host-parameters section allows for modification to
4699 * internal driver logging.
4700 */
0181944f 4701 if (nv->host_p[0] & BIT_7)
cfb0919c 4702 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 4703 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
4704 /* Always load RISC code on non ISP2[12]00 chips. */
4705 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
4706 ha->flags.disable_risc_code_load = 0;
4707 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
4708 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
4709 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 4710 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 4711 ha->flags.disable_serdes = 0;
1da177e4
LT		 4712
4713 ha->operating_mode =
4714 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
4715
4716 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
4717 sizeof(ha->fw_seriallink_options));
4718
4719 /* save HBA serial number */
4720 ha->serial0 = icb->port_name[5];
4721 ha->serial1 = icb->port_name[6];
4722 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4723 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4724 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 4725
ad950360 4726 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 4727
4728 ha->retry_count = nv->retry_count;
4729
4730 /* Set minimum login_timeout to 4 seconds. */
5b91490e 4731 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 4732 nv->login_timeout = ql2xlogintimeout;
4733 if (nv->login_timeout < 4)
4734 nv->login_timeout = 4;
4735 ha->login_timeout = nv->login_timeout;
1da177e4 4736
00a537b8
AV		 4737 /* Set minimum RATOV to 100 tenths of a second. */
4738 ha->r_a_tov = 100;
1da177e4 4739
1da177e4
LT		 4740 ha->loop_reset_delay = nv->reset_delay;
4741
1da177e4
LT		 4742 /* Link Down Timeout = 0:
4743 *
4744 * When Port Down timer expires we will start returning
4745 * I/O's to OS with "DID_NO_CONNECT".
4746 *
4747 * Link Down Timeout != 0:
4748 *
4749 * The driver waits for the link to come up after link down
4750 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 4751 */
1da177e4
LT		 4752 if (nv->link_down_timeout == 0) {
4753 ha->loop_down_abort_time =
354d6b21 4754 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 4755 } else {
4756 ha->link_down_timeout = nv->link_down_timeout;
4757 ha->loop_down_abort_time =
4758 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 4759 }
1da177e4 4760
1da177e4
LT		 4761 /*
4762 * Need enough time to try and get the port back.
4763 */
4764 ha->port_down_retry_count = nv->port_down_retry_count;
4765 if (qlport_down_retry)
4766 ha->port_down_retry_count = qlport_down_retry;
4767 /* Set login_retry_count */
4768 ha->login_retry_count = nv->retry_count;
4769 if (ha->port_down_retry_count == nv->port_down_retry_count &&
4770 ha->port_down_retry_count > 3)
4771 ha->login_retry_count = ha->port_down_retry_count;
4772 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4773 ha->login_retry_count = ha->port_down_retry_count;
4774 if (ql2xloginretrycount)
4775 ha->login_retry_count = ql2xloginretrycount;
4776
ad950360 4777 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 4778 icb->command_resource_count = 0;
4779 icb->immediate_notify_resource_count = 0;
ad950360 4780 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 4781
4782 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4783 /* Enable RIO */
4784 icb->firmware_options[0] &= ~BIT_3;
4785 icb->add_firmware_options[0] &=
4786 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
4787 icb->add_firmware_options[0] |= BIT_2;
4788 icb->response_accumulation_timer = 3;
4789 icb->interrupt_delay_timer = 5;
4790
e315cd28 4791 vha->flags.process_response_queue = 1;
1da177e4 4792 } else {
4fdfefe5 4793 /* Enable ZIO. */
e315cd28 4794 if (!vha->flags.init_done) {
4fdfefe5
AV		 4795 ha->zio_mode = icb->add_firmware_options[0] &
4796 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4797 ha->zio_timer = icb->interrupt_delay_timer ?
58e2753c 4798 icb->interrupt_delay_timer : 2;
4fdfefe5 4799 }
1da177e4
LT		 4800 icb->add_firmware_options[0] &=
4801 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 4802 vha->flags.process_response_queue = 0;
4fdfefe5 4803 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 4804 ha->zio_mode = QLA_ZIO_MODE_6;
4805
7c3df132 4806 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 4807 "ZIO mode %d enabled; timer delay (%d us).\n",
4808 ha->zio_mode, ha->zio_timer * 100);
1da177e4 4809
4fdfefe5
AV		 4810 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
4811 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 4812 vha->flags.process_response_queue = 1;
1da177e4
LT		 4813 }
4814 }
4815
4e08df3f 4816 if (rval) {
7c3df132
SK		 4817 ql_log(ql_log_warn, vha, 0x0069,
4818 "NVRAM configuration failed.\n");
4e08df3f
DM		 4819 }
4820 return (rval);
1da177e4
LT		 4821}
4822
19a7b4ae
JSEC		 4823static void
4824qla2x00_rport_del(void *data)
4825{
4826 fc_port_t *fcport = data;
d97994dc 4827 struct fc_rport *rport;
044d78e1 4828 unsigned long flags;
d97994dc 4829
044d78e1 4830 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
58e2753c 4831 rport = fcport->drport ? fcport->drport : fcport->rport;
d97994dc 4832 fcport->drport = NULL;
044d78e1 4833 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
726b8548 4834 if (rport) {
83548fe2
QT		 4835 ql_dbg(ql_dbg_disc, fcport->vha, 0x210b,
4836 "%s %8phN. rport %p roles %x\n",
4837 __func__, fcport->port_name, rport,
4838 rport->roles);
726b8548 4839
d97994dc 4840 fc_remote_port_delete(rport);
726b8548 4841 }
19a7b4ae
JSEC		 4842}
4843
a630bdc5
BVA		 4844void qla2x00_set_fcport_state(fc_port_t *fcport, int state)
4845{
4846 int old_state;
4847
4848 old_state = atomic_read(&fcport->state);
4849 atomic_set(&fcport->state, state);
4850
4851 /* Don't print state transitions during initial allocation of fcport */
4852 if (old_state && old_state != state) {
4853 ql_dbg(ql_dbg_disc, fcport->vha, 0x207d,
4854 "FCPort %8phC state transitioned from %s to %s - portid=%02x%02x%02x.\n",
4855 fcport->port_name, port_state_str[old_state],
4856 port_state_str[state], fcport->d_id.b.domain,
4857 fcport->d_id.b.area, fcport->d_id.b.al_pa);
4858 }
4859}
4860
1da177e4
LT		 4861/**
4862 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2db6228d 4863 * @vha: HA context
1da177e4
LT		 4864 * @flags: allocation flags
4865 *
4866 * Returns a pointer to the allocated fcport, or NULL, if none available.
4867 */
9a069e19 4868fc_port_t *
e315cd28 4869qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 4870{
4871 fc_port_t *fcport;
4872
bbfbbbc1
MK		 4873 fcport = kzalloc(sizeof(fc_port_t), flags);
4874 if (!fcport)
4875 return NULL;
1da177e4 4876
9ecd6564
QT		 4877 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
4878 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
4879 flags);
4880 if (!fcport->ct_desc.ct_sns) {
4881 ql_log(ql_log_warn, vha, 0xd049,
4882 "Failed to allocate ct_sns request.\n");
4883 kfree(fcport);
4884 return NULL;
4885 }
4886
1da177e4 4887 /* Setup fcport template structure. */
e315cd28 4888 fcport->vha = vha;
1da177e4
LT		 4889 fcport->port_type = FCT_UNKNOWN;
4890 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 4891 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 4892 fcport->supported_classes = FC_COS_UNSPECIFIED;
f635e48e 4893 fcport->fp_speed = PORT_SPEED_UNKNOWN;
1da177e4 4894
726b8548
QT		 4895 fcport->disc_state = DSC_DELETED;
4896 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
4897 fcport->deleted = QLA_SESS_DELETED;
4898 fcport->login_retry = vha->hw->login_retry_count;
9ecd6564 4899 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
726b8548
QT		 4900 fcport->logout_on_delete = 1;
4901
4902 if (!fcport->ct_desc.ct_sns) {
83548fe2 4903 ql_log(ql_log_warn, vha, 0xd049,
726b8548
QT		 4904 "Failed to allocate ct_sns request.\n");
4905 kfree(fcport);
4906 fcport = NULL;
4907 }
9ecd6564 4908
726b8548 4909 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
cd4ed6b4 4910 INIT_WORK(&fcport->reg_work, qla_register_fcport_fn);
726b8548
QT		 4911 INIT_LIST_HEAD(&fcport->gnl_entry);
4912 INIT_LIST_HEAD(&fcport->list);
4913
bbfbbbc1 4914 return fcport;
1da177e4
LT		 4915}
4916
726b8548
QT		 4917void
4918qla2x00_free_fcport(fc_port_t *fcport)
4919{
4920 if (fcport->ct_desc.ct_sns) {
4921 dma_free_coherent(&fcport->vha->hw->pdev->dev,
4922 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
4923 fcport->ct_desc.ct_sns_dma);
4924
4925 fcport->ct_desc.ct_sns = NULL;
4926 }
ffbc6476
QT		 4927 list_del(&fcport->list);
4928 qla2x00_clear_loop_id(fcport);
726b8548
QT		 4929 kfree(fcport);
4930}
4931
1da177e4
LT		 4932/*
4933 * qla2x00_configure_loop
4934 * Updates Fibre Channel Device Database with what is actually on loop.
4935 *
4936 * Input:
4937 * ha = adapter block pointer.
4938 *
4939 * Returns:
4940 * 0 = success.
4941 * 1 = error.
4942 * 2 = database was full and device was not configured.
4943 */
4944static int
e315cd28 4945qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4946{
4947 int rval;
4948 unsigned long flags, save_flags;
e315cd28 4949 struct qla_hw_data *ha = vha->hw;
bd432bb5 4950
1da177e4
LT		 4951 rval = QLA_SUCCESS;
4952
4953 /* Get Initiator ID */
e315cd28
AC		 4954 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
4955 rval = qla2x00_configure_hba(vha);
1da177e4 4956 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4957 ql_dbg(ql_dbg_disc, vha, 0x2013,
4958 "Unable to configure HBA.\n");
1da177e4
LT		 4959 return (rval);
4960 }
4961 }
4962
e315cd28 4963 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 4964 ql_dbg(ql_dbg_disc, vha, 0x2014,
4965 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 4966
4967 /*
4968 * If we have both an RSCN and PORT UPDATE pending then handle them
4969 * both at the same time.
4970 */
e315cd28
AC		 4971 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
4972 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 4973
3064ff39
MH		 4974 qla2x00_get_data_rate(vha);
4975
1da177e4
LT		 4976 /* Determine what we need to do */
4977 if (ha->current_topology == ISP_CFG_FL &&
4978 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4979
1da177e4
LT		 4980 set_bit(RSCN_UPDATE, &flags);
4981
4982 } else if (ha->current_topology == ISP_CFG_F &&
4983 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4984
1da177e4
LT		 4985 set_bit(RSCN_UPDATE, &flags);
4986 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 4987
4988 } else if (ha->current_topology == ISP_CFG_N) {
4989 clear_bit(RSCN_UPDATE, &flags);
48acad09
QT		 4990 if (qla_tgt_mode_enabled(vha)) {
4991 /* allow the other side to start the login */
9cd883f0
QT		 4992 clear_bit(LOCAL_LOOP_UPDATE, &flags);
4993 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
9cd883f0 4994 }
41dc529a
QT		 4995 } else if (ha->current_topology == ISP_CFG_NL) {
4996 clear_bit(RSCN_UPDATE, &flags);
4997 set_bit(LOCAL_LOOP_UPDATE, &flags);
e315cd28 4998 } else if (!vha->flags.online ||
1da177e4 4999 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
1da177e4
LT		 5000 set_bit(RSCN_UPDATE, &flags);
5001 set_bit(LOCAL_LOOP_UPDATE, &flags);
5002 }
5003
5004 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 5005 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
5006 ql_dbg(ql_dbg_disc, vha, 0x2015,
5007 "Loop resync needed, failing.\n");
1da177e4 5008 rval = QLA_FUNCTION_FAILED;
642ef983 5009 } else
e315cd28 5010 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 5011 }
5012
5013 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132 5014 if (LOOP_TRANSITION(vha)) {
83548fe2 5015 ql_dbg(ql_dbg_disc, vha, 0x2099,
7c3df132 5016 "Needs RSCN update and loop transition.\n");
1da177e4 5017 rval = QLA_FUNCTION_FAILED;
7c3df132 5018 }
e315cd28
AC		 5019 else
5020 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 5021 }
5022
5023 if (rval == QLA_SUCCESS) {
e315cd28
AC		 5024 if (atomic_read(&vha->loop_down_timer) ||
5025 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 5026 rval = QLA_FUNCTION_FAILED;
5027 } else {
e315cd28 5028 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 5029 ql_dbg(ql_dbg_disc, vha, 0x2069,
5030 "LOOP READY.\n");
ec7193e2 5031 ha->flags.fw_init_done = 1;
3bb67df5
DKU		 5032
5033 /*
5034 * Process any ATIO queue entries that came in
5035 * while we weren't online.
5036 */
ead03855
QT		 5037 if (qla_tgt_mode_enabled(vha) ||
5038 qla_dual_mode_enabled(vha)) {
1073daa4
QT		 5039 spin_lock_irqsave(&ha->tgt.atio_lock, flags);
5040 qlt_24xx_process_atio_queue(vha, 0);
5041 spin_unlock_irqrestore(&ha->tgt.atio_lock,
5042 flags);
3bb67df5 5043 }
1da177e4
LT		 5044 }
5045 }
5046
5047 if (rval) {
7c3df132
SK		 5048 ql_dbg(ql_dbg_disc, vha, 0x206a,
5049 "%s *** FAILED ***.\n", __func__);
1da177e4 5050 } else {
7c3df132
SK		 5051 ql_dbg(ql_dbg_disc, vha, 0x206b,
5052 "%s: exiting normally.\n", __func__);
1da177e4
LT		 5053 }
5054
cc3ef7bc 5055 /* Restore state if a resync event occurred during processing */
e315cd28 5056 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 5057 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 5058 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 5059 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 5060 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 5061 }
1da177e4
LT		 5062 }
5063
5064 return (rval);
5065}
5066
1da177e4
LT		 5067/*
5068 * qla2x00_configure_local_loop
5069 * Updates Fibre Channel Device Database with local loop devices.
5070 *
5071 * Input:
5072 * ha = adapter block pointer.
5073 *
5074 * Returns:
5075 * 0 = success.
5076 */
5077static int
e315cd28 5078qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 5079{
5080 int rval, rval2;
5081 int found_devs;
5082 int found;
5083 fc_port_t *fcport, *new_fcport;
5084
5085 uint16_t index;
5086 uint16_t entries;
9c17c3b1 5087 struct gid_list_info *gid;
1da177e4
LT		 5088 uint16_t loop_id;
5089 uint8_t domain, area, al_pa;
e315cd28 5090 struct qla_hw_data *ha = vha->hw;
41dc529a 5091 unsigned long flags;
1da177e4 5092
8777e431
QT		 5093 /* Inititae N2N login. */
5094 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags)) {
5095 /* borrowing */
5096 u32 *bp, i, sz;
5097
5098 memset(ha->init_cb, 0, ha->init_cb_size);
5099 sz = min_t(int, sizeof(struct els_plogi_payload),
5100 ha->init_cb_size);
5101 rval = qla24xx_get_port_login_templ(vha, ha->init_cb_dma,
5102 (void *)ha->init_cb, sz);
5103 if (rval == QLA_SUCCESS) {
5104 bp = (uint32_t *)ha->init_cb;
5105 for (i = 0; i < sz/4 ; i++, bp++)
5106 *bp = cpu_to_be32(*bp);
5107
5108 memcpy(&ha->plogi_els_payld.data, (void *)ha->init_cb,
5109 sizeof(ha->plogi_els_payld.data));
5110 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5111 } else {
5112 ql_dbg(ql_dbg_init, vha, 0x00d1,
5113 "PLOGI ELS param read fail.\n");
5114 }
5115 return QLA_SUCCESS;
5116 }
5117
1da177e4
LT		 5118 found_devs = 0;
5119 new_fcport = NULL;
642ef983 5120 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 5121
1da177e4 5122 /* Get list of logged in devices. */
642ef983 5123 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 5124 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 5125 &entries);
5126 if (rval != QLA_SUCCESS)
5127 goto cleanup_allocation;
5128
83548fe2 5129 ql_dbg(ql_dbg_disc, vha, 0x2011,
7c3df132
SK		 5130 "Entries in ID list (%d).\n", entries);
5131 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
f8f97b0c 5132 ha->gid_list, entries * sizeof(*ha->gid_list));
1da177e4 5133
0e324e94
QT		 5134 if (entries == 0) {
5135 spin_lock_irqsave(&vha->work_lock, flags);
5136 vha->scan.scan_retry++;
5137 spin_unlock_irqrestore(&vha->work_lock, flags);
5138
5139 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) {
5140 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5141 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5142 }
5143 } else {
5144 vha->scan.scan_retry = 0;
5145 }
5146
9cd883f0
QT		 5147 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5148 fcport->scan_state = QLA_FCPORT_SCAN;
5149 }
5150
1da177e4 5151 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 5152 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5153 if (new_fcport == NULL) {
83548fe2 5154 ql_log(ql_log_warn, vha, 0x2012,
7c3df132 5155 "Memory allocation failed for fcport.\n");
1da177e4
LT		 5156 rval = QLA_MEMORY_ALLOC_FAILED;
5157 goto cleanup_allocation;
5158 }
5159 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
5160
1da177e4 5161 /* Add devices to port list. */
9c17c3b1 5162 gid = ha->gid_list;
1da177e4 5163 for (index = 0; index < entries; index++) {
9c17c3b1
BVA		 5164 domain = gid->domain;
5165 area = gid->area;
5166 al_pa = gid->al_pa;
abbd8870 5167 if (IS_QLA2100(ha) || IS_QLA2200(ha))
9c17c3b1 5168 loop_id = gid->loop_id_2100;
abbd8870 5169 else
9c17c3b1
BVA		 5170 loop_id = le16_to_cpu(gid->loop_id);
5171 gid = (void *)gid + ha->gid_list_info_size;
1da177e4
LT		 5172
5173 /* Bypass reserved domain fields. */
5174 if ((domain & 0xf0) == 0xf0)
5175 continue;
5176
4705f10e
QT		 5177 /* Bypass if not same domain and area of adapter. */
5178 if (area && domain && ((area != vha->d_id.b.area) ||
5179 (domain != vha->d_id.b.domain)) &&
5180 (ha->current_topology == ISP_CFG_NL))
5181 continue;
5182
5183
1da177e4
LT		 5184 /* Bypass invalid local loop ID. */
5185 if (loop_id > LAST_LOCAL_LOOP_ID)
5186 continue;
5187
41dc529a 5188 memset(new_fcport->port_name, 0, WWN_SIZE);
370d550e 5189
1da177e4
LT		 5190 /* Fill in member data. */
5191 new_fcport->d_id.b.domain = domain;
5192 new_fcport->d_id.b.area = area;
5193 new_fcport->d_id.b.al_pa = al_pa;
5194 new_fcport->loop_id = loop_id;
9cd883f0 5195 new_fcport->scan_state = QLA_FCPORT_FOUND;
41dc529a 5196
e315cd28 5197 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 5198 if (rval2 != QLA_SUCCESS) {
83548fe2 5199 ql_dbg(ql_dbg_disc, vha, 0x2097,
7c3df132
SK		 5200 "Failed to retrieve fcport information "
5201 "-- get_port_database=%x, loop_id=0x%04x.\n",
5202 rval2, new_fcport->loop_id);
edd05de1
DG		 5203 /* Skip retry if N2N */
5204 if (ha->current_topology != ISP_CFG_N) {
5205 ql_dbg(ql_dbg_disc, vha, 0x2105,
5206 "Scheduling resync.\n");
5207 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5208 continue;
5209 }
1da177e4
LT		 5210 }
5211
41dc529a 5212 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 5213 /* Check for matching device in port list. */
5214 found = 0;
5215 fcport = NULL;
e315cd28 5216 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 5217 if (memcmp(new_fcport->port_name, fcport->port_name,
5218 WWN_SIZE))
5219 continue;
5220
ddb9b126 5221 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 5222 fcport->loop_id = new_fcport->loop_id;
5223 fcport->port_type = new_fcport->port_type;
5224 fcport->d_id.b24 = new_fcport->d_id.b24;
5225 memcpy(fcport->node_name, new_fcport->node_name,
5226 WWN_SIZE);
9cd883f0 5227 fcport->scan_state = QLA_FCPORT_FOUND;
1da177e4
LT		 5228 found++;
5229 break;
5230 }
5231
5232 if (!found) {
5233 /* New device, add to fcports list. */
e315cd28 5234 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 5235
5236 /* Allocate a new replacement fcport. */
5237 fcport = new_fcport;
41dc529a
QT		 5238
5239 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5240
e315cd28 5241 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
41dc529a 5242
1da177e4 5243 if (new_fcport == NULL) {
83548fe2 5244 ql_log(ql_log_warn, vha, 0xd031,
7c3df132 5245 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 5246 rval = QLA_MEMORY_ALLOC_FAILED;
5247 goto cleanup_allocation;
5248 }
41dc529a 5249 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 5250 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
5251 }
5252
41dc529a
QT		 5253 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5254
d8b45213 5255 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 5256 fcport->fp_speed = ha->link_data_rate;
d8b45213 5257
1da177e4
LT		 5258 found_devs++;
5259 }
5260
9cd883f0
QT		 5261 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5262 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5263 break;
5264
5265 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5266 if ((qla_dual_mode_enabled(vha) ||
5267 qla_ini_mode_enabled(vha)) &&
5268 atomic_read(&fcport->state) == FCS_ONLINE) {
5269 qla2x00_mark_device_lost(vha, fcport,
5270 ql2xplogiabsentdevice, 0);
5271 if (fcport->loop_id != FC_NO_LOOP_ID &&
5272 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5273 fcport->port_type != FCT_INITIATOR &&
5274 fcport->port_type != FCT_BROADCAST) {
5275 ql_dbg(ql_dbg_disc, vha, 0x20f0,
5276 "%s %d %8phC post del sess\n",
5277 __func__, __LINE__,
5278 fcport->port_name);
5279
d8630bb9 5280 qlt_schedule_sess_for_deletion(fcport);
9cd883f0
QT		 5281 continue;
5282 }
5283 }
5284 }
5285
5286 if (fcport->scan_state == QLA_FCPORT_FOUND)
5287 qla24xx_fcport_handle_login(vha, fcport);
5288 }
5289
1da177e4 5290cleanup_allocation:
c9475cb0 5291 kfree(new_fcport);
1da177e4
LT		 5292
5293 if (rval != QLA_SUCCESS) {
83548fe2 5294 ql_dbg(ql_dbg_disc, vha, 0x2098,
7c3df132 5295 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 5296 }
5297
1da177e4
LT		 5298 return (rval);
5299}
5300
d8b45213 5301static void
e315cd28 5302qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 5303{
d8b45213 5304 int rval;
93f2bd67 5305 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 5306 struct qla_hw_data *ha = vha->hw;
d8b45213 5307
c76f2c01 5308 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 5309 return;
5310
c9afb9a2
GM		 5311 if (atomic_read(&fcport->state) != FCS_ONLINE)
5312 return;
5313
39bd9622 5314 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
413c2f33
HM		 5315 fcport->fp_speed > ha->link_data_rate ||
5316 !ha->flags.gpsc_supported)
d8b45213
AV		 5317 return;
5318
e315cd28 5319 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 5320 mb);
d8b45213 5321 if (rval != QLA_SUCCESS) {
7c3df132 5322 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 5323 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
5324 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 5325 } else {
7c3df132 5326 ql_dbg(ql_dbg_disc, vha, 0x2005,
33b28357 5327 "iIDMA adjusted to %s GB/s (%X) on %8phN.\n",
d0297c9a 5328 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
33b28357 5329 fcport->fp_speed, fcport->port_name);
d8b45213
AV		 5330 }
5331}
5332
cc28e0ac
QT		 5333void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
5334{
5335 qla2x00_iidma_fcport(vha, fcport);
5336 qla24xx_update_fcport_fcp_prio(vha, fcport);
5337}
5338
5339int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
5340{
5341 struct qla_work_evt *e;
5342
5343 e = qla2x00_alloc_work(vha, QLA_EVT_IIDMA);
5344 if (!e)
5345 return QLA_FUNCTION_FAILED;
5346
5347 e->u.fcport.fcport = fcport;
5348 return qla2x00_post_work(vha, e);
5349}
5350
726b8548 5351/* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
23be331d 5352static void
e315cd28 5353qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 5354{
5355 struct fc_rport_identifiers rport_ids;
bdf79621 5356 struct fc_rport *rport;
044d78e1 5357 unsigned long flags;
8482e118 5358
b63d8b89
QT		 5359 if (atomic_read(&fcport->state) == FCS_ONLINE)
5360 return;
5361
f8b02a85
AV		 5362 rport_ids.node_name = wwn_to_u64(fcport->node_name);
5363 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 5364 rport_ids.port_id = fcport->d_id.b.domain << 16 |
5365 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 5366 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 5367 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 5368 if (!rport) {
7c3df132
SK		 5369 ql_log(ql_log_warn, vha, 0x2006,
5370 "Unable to allocate fc remote port.\n");
77d74143
AV		 5371 return;
5372 }
2d70c103 5373
044d78e1 5374 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 5375 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 5376 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 5377
ad3e0eda 5378 rport->supported_classes = fcport->supported_classes;
77d74143 5379
a6a6d058 5380 rport_ids.roles = FC_PORT_ROLE_UNKNOWN;
8482e118 5381 if (fcport->port_type == FCT_INITIATOR)
a6a6d058 5382 rport_ids.roles |= FC_PORT_ROLE_FCP_INITIATOR;
8482e118 5383 if (fcport->port_type == FCT_TARGET)
a6a6d058
HR		 5384 rport_ids.roles |= FC_PORT_ROLE_FCP_TARGET;
5385 if (fcport->port_type & FCT_NVME_INITIATOR)
5386 rport_ids.roles |= FC_PORT_ROLE_NVME_INITIATOR;
5387 if (fcport->port_type & FCT_NVME_TARGET)
5388 rport_ids.roles |= FC_PORT_ROLE_NVME_TARGET;
5389 if (fcport->port_type & FCT_NVME_DISCOVERY)
5390 rport_ids.roles |= FC_PORT_ROLE_NVME_DISCOVERY;
726b8548 5391
83548fe2
QT		 5392 ql_dbg(ql_dbg_disc, vha, 0x20ee,
5393 "%s %8phN. rport %p is %s mode\n",
5394 __func__, fcport->port_name, rport,
a6a6d058 5395 (fcport->port_type == FCT_TARGET) ? "tgt" :
c1c7178c 5396 ((fcport->port_type & FCT_NVME) ? "nvme" : "ini"));
726b8548 5397
77d74143 5398 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 5399}
5400
23be331d
AB		 5401/*
5402 * qla2x00_update_fcport
5403 * Updates device on list.
5404 *
5405 * Input:
5406 * ha = adapter block pointer.
5407 * fcport = port structure pointer.
5408 *
5409 * Return:
5410 * 0 - Success
5411 * BIT_0 - error
5412 *
5413 * Context:
5414 * Kernel context.
5415 */
5416void
e315cd28 5417qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 5418{
726b8548
QT		 5419 if (IS_SW_RESV_ADDR(fcport->d_id))
5420 return;
5421
cd4ed6b4
QT		 5422 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n",
5423 __func__, fcport->port_name);
5424
5425 fcport->disc_state = DSC_UPD_FCPORT;
5426 fcport->login_retry = vha->hw->login_retry_count;
b63d8b89 5427 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
b63d8b89
QT		 5428 fcport->deleted = 0;
5429 fcport->logout_on_delete = 1;
8777e431 5430 fcport->n2n_chip_reset = fcport->n2n_link_reset_cnt = 0;
23be331d 5431
8777e431
QT		 5432 switch (vha->hw->current_topology) {
5433 case ISP_CFG_N:
5434 case ISP_CFG_NL:
5435 fcport->keep_nport_handle = 1;
5436 break;
5437 default:
5438 break;
5439 }
5440
aecf0434
QT		 5441 qla2x00_iidma_fcport(vha, fcport);
5442
e84067d7
DG		 5443 if (fcport->fc4f_nvme) {
5444 qla_nvme_register_remote(vha, fcport);
b63d8b89
QT		 5445 fcport->disc_state = DSC_LOGIN_COMPLETE;
5446 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e84067d7
DG		 5447 return;
5448 }
5449
21090cbe 5450 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b 5451
726b8548
QT		 5452 switch (vha->host->active_mode) {
5453 case MODE_INITIATOR:
d20ed91b 5454 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 5455 break;
5456 case MODE_TARGET:
5457 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5458 !vha->vha_tgt.qla_tgt->tgt_stopped)
5459 qlt_fc_port_added(vha, fcport);
5460 break;
5461 case MODE_DUAL:
d20ed91b 5462 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 5463 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5464 !vha->vha_tgt.qla_tgt->tgt_stopped)
5465 qlt_fc_port_added(vha, fcport);
5466 break;
5467 default:
5468 break;
d20ed91b 5469 }
cc28e0ac 5470
aecf0434
QT		 5471 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
5472
cc28e0ac
QT		 5473 if (IS_IIDMA_CAPABLE(vha->hw) && vha->hw->flags.gpsc_supported) {
5474 if (fcport->id_changed) {
5475 fcport->id_changed = 0;
5476 ql_dbg(ql_dbg_disc, vha, 0x20d7,
5477 "%s %d %8phC post gfpnid fcp_cnt %d\n",
5478 __func__, __LINE__, fcport->port_name,
5479 vha->fcport_count);
5480 qla24xx_post_gfpnid_work(vha, fcport);
5481 } else {
5482 ql_dbg(ql_dbg_disc, vha, 0x20d7,
5483 "%s %d %8phC post gpsc fcp_cnt %d\n",
5484 __func__, __LINE__, fcport->port_name,
5485 vha->fcport_count);
5486 qla24xx_post_gpsc_work(vha, fcport);
5487 }
5488 }
cd4ed6b4
QT		 5489
5490 fcport->disc_state = DSC_LOGIN_COMPLETE;
5491}
5492
5493void qla_register_fcport_fn(struct work_struct *work)
5494{
5495 fc_port_t *fcport = container_of(work, struct fc_port, reg_work);
5496 u32 rscn_gen = fcport->rscn_gen;
5497 u16 data[2];
5498
5499 if (IS_SW_RESV_ADDR(fcport->d_id))
5500 return;
5501
5502 qla2x00_update_fcport(fcport->vha, fcport);
5503
5504 if (rscn_gen != fcport->rscn_gen) {
5505 /* RSCN(s) came in while registration */
5506 switch (fcport->next_disc_state) {
5507 case DSC_DELETE_PEND:
5508 qlt_schedule_sess_for_deletion(fcport);
5509 break;
5510 case DSC_ADISC:
5511 data[0] = data[1] = 0;
5512 qla2x00_post_async_adisc_work(fcport->vha, fcport,
5513 data);
5514 break;
5515 default:
5516 break;
5517 }
5518 }
23be331d
AB		 5519}
5520
1da177e4
LT		 5521/*
5522 * qla2x00_configure_fabric
5523 * Setup SNS devices with loop ID's.
5524 *
5525 * Input:
5526 * ha = adapter block pointer.
5527 *
5528 * Returns:
5529 * 0 = success.
5530 * BIT_0 = error
5531 */
5532static int
e315cd28 5533qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 5534{
b3b02e6e 5535 int rval;
726b8548 5536 fc_port_t *fcport;
1da177e4 5537 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 5538 uint16_t loop_id;
1da177e4 5539 LIST_HEAD(new_fcports);
e315cd28 5540 struct qla_hw_data *ha = vha->hw;
df673274 5541 int discovery_gen;
1da177e4
LT		 5542
5543 /* If FL port exists, then SNS is present */
e428924c 5544 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 5545 loop_id = NPH_F_PORT;
5546 else
5547 loop_id = SNS_FL_PORT;
e315cd28 5548 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 5549 if (rval != QLA_SUCCESS) {
83548fe2 5550 ql_dbg(ql_dbg_disc, vha, 0x20a0,
7c3df132 5551 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 5552
e315cd28 5553 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 5554 return (QLA_SUCCESS);
5555 }
e315cd28 5556 vha->device_flags |= SWITCH_FOUND;
1da177e4 5557
41dc529a
QT		 5558
5559 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
5560 rval = qla2x00_send_change_request(vha, 0x3, 0);
5561 if (rval != QLA_SUCCESS)
5562 ql_log(ql_log_warn, vha, 0x121,
5563 "Failed to enable receiving of RSCN requests: 0x%x.\n",
5564 rval);
5565 }
5566
5567
1da177e4 5568 do {
726b8548
QT		 5569 qla2x00_mgmt_svr_login(vha);
5570
cca5335c
AV		 5571 /* FDMI support. */
5572 if (ql2xfdmienable &&
e315cd28
AC		 5573 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
5574 qla2x00_fdmi_register(vha);
cca5335c 5575
1da177e4 5576 /* Ensure we are logged into the SNS. */
a14c7711 5577 loop_id = NPH_SNS_LID(ha);
0b91d116
CD		 5578 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
5579 0xfc, mb, BIT_1|BIT_0);
a14c7711
JC		 5580 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5581 ql_dbg(ql_dbg_disc, vha, 0x20a1,
5582 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n",
5583 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval);
0b91d116 5584 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 5585 return rval;
0b91d116 5586 }
e315cd28
AC		 5587 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
5588 if (qla2x00_rft_id(vha)) {
1da177e4 5589 /* EMPTY */
83548fe2 5590 ql_dbg(ql_dbg_disc, vha, 0x20a2,
7c3df132 5591 "Register FC-4 TYPE failed.\n");
b98ae0d7
QT		 5592 if (test_bit(LOOP_RESYNC_NEEDED,
5593 &vha->dpc_flags))
5594 break;
1da177e4 5595 }
d3bae931 5596 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) {
1da177e4 5597 /* EMPTY */
83548fe2 5598 ql_dbg(ql_dbg_disc, vha, 0x209a,
7c3df132 5599 "Register FC-4 Features failed.\n");
b98ae0d7
QT		 5600 if (test_bit(LOOP_RESYNC_NEEDED,
5601 &vha->dpc_flags))
5602 break;
1da177e4 5603 }
d3bae931
DG		 5604 if (vha->flags.nvme_enabled) {
5605 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) {
5606 ql_dbg(ql_dbg_disc, vha, 0x2049,
5607 "Register NVME FC Type Features failed.\n");
5608 }
5609 }
e315cd28 5610 if (qla2x00_rnn_id(vha)) {
1da177e4 5611 /* EMPTY */
83548fe2 5612 ql_dbg(ql_dbg_disc, vha, 0x2104,
7c3df132 5613 "Register Node Name failed.\n");
b98ae0d7
QT		 5614 if (test_bit(LOOP_RESYNC_NEEDED,
5615 &vha->dpc_flags))
5616 break;
e315cd28 5617 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 5618 /* EMPTY */
83548fe2 5619 ql_dbg(ql_dbg_disc, vha, 0x209b,
0bf0efa1 5620 "Register Symbolic Node Name failed.\n");
b98ae0d7
QT		 5621 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5622 break;
1da177e4
LT		 5623 }
5624 }
5625
827210ba 5626
df673274
AP		 5627 /* Mark the time right before querying FW for connected ports.
5628 * This process is long, asynchronous and by the time it's done,
5629 * collected information might not be accurate anymore. E.g.
5630 * disconnected port might have re-connected and a brand new
5631 * session has been created. In this case session's generation
5632 * will be newer than discovery_gen. */
5633 qlt_do_generation_tick(vha, &discovery_gen);
5634
a4239945 5635 if (USE_ASYNC_SCAN(ha)) {
33b28357
QT		 5636 rval = qla24xx_async_gpnft(vha, FC4_TYPE_FCP_SCSI,
5637 NULL);
a4239945
QT		 5638 if (rval)
5639 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5640 } else {
f352eeb7
QT		 5641 list_for_each_entry(fcport, &vha->vp_fcports, list)
5642 fcport->scan_state = QLA_FCPORT_SCAN;
5643
a4239945
QT		 5644 rval = qla2x00_find_all_fabric_devs(vha);
5645 }
1da177e4
LT		 5646 if (rval != QLA_SUCCESS)
5647 break;
1da177e4
LT		 5648 } while (0);
5649
e84067d7
DG		 5650 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
5651 qla_nvme_register_hba(vha);
5652
726b8548 5653 if (rval)
7c3df132
SK		 5654 ql_dbg(ql_dbg_disc, vha, 0x2068,
5655 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 5656
5657 return (rval);
5658}
5659
1da177e4
LT		 5660/*
5661 * qla2x00_find_all_fabric_devs
5662 *
5663 * Input:
5664 * ha = adapter block pointer.
5665 * dev = database device entry pointer.
5666 *
5667 * Returns:
5668 * 0 = success.
5669 *
5670 * Context:
5671 * Kernel context.
5672 */
5673static int
726b8548 5674qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
1da177e4
LT		 5675{
5676 int rval;
5677 uint16_t loop_id;
726b8548 5678 fc_port_t *fcport, *new_fcport;
1da177e4
LT		 5679 int found;
5680
5681 sw_info_t *swl;
5682 int swl_idx;
5683 int first_dev, last_dev;
1516ef44 5684 port_id_t wrap = {}, nxt_d_id;
e315cd28 5685 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 5686 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
726b8548 5687 unsigned long flags;
1da177e4
LT		 5688
5689 rval = QLA_SUCCESS;
5690
5691 /* Try GID_PT to get device list, else GAN. */
7a67735b 5692 if (!ha->swl)
642ef983 5693 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 5694 GFP_KERNEL);
5695 swl = ha->swl;
bbfbbbc1 5696 if (!swl) {
1da177e4 5697 /*EMPTY*/
83548fe2 5698 ql_dbg(ql_dbg_disc, vha, 0x209c,
7c3df132 5699 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 5700 } else {
642ef983 5701 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 5702 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 5703 swl = NULL;
b98ae0d7
QT		 5704 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5705 return rval;
e315cd28 5706 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5707 swl = NULL;
b98ae0d7
QT		 5708 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5709 return rval;
e315cd28 5710 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5711 swl = NULL;
b98ae0d7
QT		 5712 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5713 return rval;
726b8548
QT		 5714 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
5715 swl = NULL;
b98ae0d7
QT		 5716 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5717 return rval;
1da177e4 5718 }
e8c72ba5
CD		 5719
5720 /* If other queries succeeded probe for FC-4 type */
b98ae0d7 5721 if (swl) {
e8c72ba5 5722 qla2x00_gff_id(vha, swl);
b98ae0d7
QT		 5723 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5724 return rval;
5725 }
1da177e4
LT		 5726 }
5727 swl_idx = 0;
5728
5729 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 5730 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5731 if (new_fcport == NULL) {
83548fe2 5732 ql_log(ql_log_warn, vha, 0x209d,
7c3df132 5733 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 5734 return (QLA_MEMORY_ALLOC_FAILED);
5735 }
5736 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 5737 /* Set start port ID scan at adapter ID. */
5738 first_dev = 1;
5739 last_dev = 0;
5740
5741 /* Starting free loop ID. */
e315cd28
AC		 5742 loop_id = ha->min_external_loopid;
5743 for (; loop_id <= ha->max_loop_id; loop_id++) {
5744 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 5745 continue;
5746
3a6478df
GM		 5747 if (ha->current_topology == ISP_CFG_FL &&
5748 (atomic_read(&vha->loop_down_timer) ||
5749 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 5750 atomic_set(&vha->loop_down_timer, 0);
5751 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5752 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 5753 break;
bb2d52b2 5754 }
1da177e4
LT		 5755
5756 if (swl != NULL) {
5757 if (last_dev) {
5758 wrap.b24 = new_fcport->d_id.b24;
5759 } else {
5760 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
5761 memcpy(new_fcport->node_name,
5762 swl[swl_idx].node_name, WWN_SIZE);
5763 memcpy(new_fcport->port_name,
5764 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 5765 memcpy(new_fcport->fabric_port_name,
5766 swl[swl_idx].fabric_port_name, WWN_SIZE);
5767 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 5768 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4 5769
a5d42f4c 5770 new_fcport->nvme_flag = 0;
1a28faa0 5771 new_fcport->fc4f_nvme = 0;
a5d42f4c
DG		 5772 if (vha->flags.nvme_enabled &&
5773 swl[swl_idx].fc4f_nvme) {
5774 new_fcport->fc4f_nvme =
5775 swl[swl_idx].fc4f_nvme;
5776 ql_log(ql_log_info, vha, 0x2131,
5777 "FOUND: NVME port %8phC as FC Type 28h\n",
5778 new_fcport->port_name);
5779 }
5780
1da177e4
LT		 5781 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
5782 last_dev = 1;
5783 }
5784 swl_idx++;
5785 }
5786 } else {
5787 /* Send GA_NXT to the switch */
e315cd28 5788 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 5789 if (rval != QLA_SUCCESS) {
83548fe2 5790 ql_log(ql_log_warn, vha, 0x209e,
7c3df132
SK		 5791 "SNS scan failed -- assuming "
5792 "zero-entry result.\n");
1da177e4
LT		 5793 rval = QLA_SUCCESS;
5794 break;
5795 }
5796 }
5797
5798 /* If wrap on switch device list, exit. */
5799 if (first_dev) {
5800 wrap.b24 = new_fcport->d_id.b24;
5801 first_dev = 0;
5802 } else if (new_fcport->d_id.b24 == wrap.b24) {
83548fe2 5803 ql_dbg(ql_dbg_disc, vha, 0x209f,
7c3df132
SK		 5804 "Device wrap (%02x%02x%02x).\n",
5805 new_fcport->d_id.b.domain,
5806 new_fcport->d_id.b.area,
5807 new_fcport->d_id.b.al_pa);
1da177e4
LT		 5808 break;
5809 }
5810
2c3dfe3f 5811 /* Bypass if same physical adapter. */
e315cd28 5812 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 5813 continue;
5814
2c3dfe3f 5815 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 5816 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
5817 continue;
2c3dfe3f 5818
f7d289f6
AV		 5819 /* Bypass if same domain and area of adapter. */
5820 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 5821 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 5822 ISP_CFG_FL)
5823 continue;
5824
1da177e4
LT		 5825 /* Bypass reserved domain fields. */
5826 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
5827 continue;
5828
e8c72ba5 5829 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 5830 if (ql2xgffidenable &&
5831 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
5832 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 5833 continue;
5834
726b8548
QT		 5835 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5836
1da177e4
LT		 5837 /* Locate matching device in database. */
5838 found = 0;
e315cd28 5839 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 5840 if (memcmp(new_fcport->port_name, fcport->port_name,
5841 WWN_SIZE))
5842 continue;
5843
827210ba 5844 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 5845
1da177e4
LT		 5846 found++;
5847
d8b45213
AV		 5848 /* Update port state. */
5849 memcpy(fcport->fabric_port_name,
5850 new_fcport->fabric_port_name, WWN_SIZE);
5851 fcport->fp_speed = new_fcport->fp_speed;
5852
1da177e4 5853 /*
b2032fd5
RD		 5854 * If address the same and state FCS_ONLINE
5855 * (or in target mode), nothing changed.
1da177e4
LT		 5856 */
5857 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5 5858 (atomic_read(&fcport->state) == FCS_ONLINE ||
726b8548 5859 (vha->host->active_mode == MODE_TARGET))) {
1da177e4
LT		 5860 break;
5861 }
5862
5863 /*
5864 * If device was not a fabric device before.
5865 */
5866 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
5867 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 5868 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 5869 fcport->flags |= (FCF_FABRIC_DEVICE |
5870 FCF_LOGIN_NEEDED);
1da177e4
LT		 5871 break;
5872 }
5873
5874 /*
5875 * Port ID changed or device was marked to be updated;
5876 * Log it out if still logged in and mark it for
5877 * relogin later.
5878 */
726b8548 5879 if (qla_tgt_mode_enabled(base_vha)) {
b2032fd5
RD		 5880 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
5881 "port changed FC ID, %8phC"
5882 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
5883 fcport->port_name,
5884 fcport->d_id.b.domain,
5885 fcport->d_id.b.area,
5886 fcport->d_id.b.al_pa,
5887 fcport->loop_id,
5888 new_fcport->d_id.b.domain,
5889 new_fcport->d_id.b.area,
5890 new_fcport->d_id.b.al_pa);
5891 fcport->d_id.b24 = new_fcport->d_id.b24;
5892 break;
5893 }
5894
1da177e4
LT		 5895 fcport->d_id.b24 = new_fcport->d_id.b24;
5896 fcport->flags |= FCF_LOGIN_NEEDED;
1da177e4
LT		 5897 break;
5898 }
5899
9dd9686b
DT		 5900 if (fcport->fc4f_nvme) {
5901 if (fcport->disc_state == DSC_DELETE_PEND) {
5902 fcport->disc_state = DSC_GNL;
5903 vha->fcport_count--;
5904 fcport->login_succ = 0;
5905 }
5906 }
5907
726b8548
QT		 5908 if (found) {
5909 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1da177e4 5910 continue;
726b8548 5911 }
1da177e4 5912 /* If device was not in our fcports list, then add it. */
b2032fd5 5913 new_fcport->scan_state = QLA_FCPORT_FOUND;
726b8548
QT		 5914 list_add_tail(&new_fcport->list, &vha->vp_fcports);
5915
5916 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5917
1da177e4
LT		 5918
5919 /* Allocate a new replacement fcport. */
5920 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 5921 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5922 if (new_fcport == NULL) {
83548fe2 5923 ql_log(ql_log_warn, vha, 0xd032,
7c3df132 5924 "Memory allocation failed for fcport.\n");
1da177e4
LT		 5925 return (QLA_MEMORY_ALLOC_FAILED);
5926 }
5927 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
5928 new_fcport->d_id.b24 = nxt_d_id.b24;
5929 }
5930
726b8548
QT		 5931 qla2x00_free_fcport(new_fcport);
5932
5933 /*
5934 * Logout all previous fabric dev marked lost, except FCP2 devices.
5935 */
5936 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5937 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5938 break;
5939
5940 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
5941 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
5942 continue;
5943
5944 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5945 if ((qla_dual_mode_enabled(vha) ||
5946 qla_ini_mode_enabled(vha)) &&
5947 atomic_read(&fcport->state) == FCS_ONLINE) {
5948 qla2x00_mark_device_lost(vha, fcport,
5949 ql2xplogiabsentdevice, 0);
5950 if (fcport->loop_id != FC_NO_LOOP_ID &&
5951 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5952 fcport->port_type != FCT_INITIATOR &&
5953 fcport->port_type != FCT_BROADCAST) {
83548fe2 5954 ql_dbg(ql_dbg_disc, vha, 0x20f0,
726b8548
QT		 5955 "%s %d %8phC post del sess\n",
5956 __func__, __LINE__,
5957 fcport->port_name);
d8630bb9 5958 qlt_schedule_sess_for_deletion(fcport);
726b8548
QT		 5959 continue;
5960 }
5961 }
5962 }
1da177e4 5963
726b8548
QT		 5964 if (fcport->scan_state == QLA_FCPORT_FOUND)
5965 qla24xx_fcport_handle_login(vha, fcport);
5966 }
1da177e4
LT		 5967 return (rval);
5968}
5969
f6602f3b
QT		 5970/* FW does not set aside Loop id for MGMT Server/FFFFFAh */
5971int
5972qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *vha)
5973{
5974 int loop_id = FC_NO_LOOP_ID;
5975 int lid = NPH_MGMT_SERVER - vha->vp_idx;
5976 unsigned long flags;
5977 struct qla_hw_data *ha = vha->hw;
5978
5979 if (vha->vp_idx == 0) {
5980 set_bit(NPH_MGMT_SERVER, ha->loop_id_map);
5981 return NPH_MGMT_SERVER;
5982 }
5983
5984 /* pick id from high and work down to low */
5985 spin_lock_irqsave(&ha->vport_slock, flags);
5986 for (; lid > 0; lid--) {
5987 if (!test_bit(lid, vha->hw->loop_id_map)) {
5988 set_bit(lid, vha->hw->loop_id_map);
5989 loop_id = lid;
5990 break;
5991 }
5992 }
5993 spin_unlock_irqrestore(&ha->vport_slock, flags);
5994
5995 return loop_id;
5996}
5997
1da177e4
LT		 5998/*
5999 * qla2x00_fabric_login
6000 * Issue fabric login command.
6001 *
6002 * Input:
6003 * ha = adapter block pointer.
6004 * device = pointer to FC device type structure.
6005 *
6006 * Returns:
6007 * 0 - Login successfully
6008 * 1 - Login failed
6009 * 2 - Initiator device
6010 * 3 - Fatal error
6011 */
6012int
e315cd28 6013qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 6014 uint16_t *next_loopid)
6015{
6016 int rval;
6017 int retry;
6018 uint16_t tmp_loopid;
6019 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 6020 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 6021
6022 retry = 0;
6023 tmp_loopid = 0;
6024
6025 for (;;) {
7c3df132
SK		 6026 ql_dbg(ql_dbg_disc, vha, 0x2000,
6027 "Trying Fabric Login w/loop id 0x%04x for port "
6028 "%02x%02x%02x.\n",
6029 fcport->loop_id, fcport->d_id.b.domain,
6030 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 6031
6032 /* Login fcport on switch. */
0b91d116 6033 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 6034 fcport->d_id.b.domain, fcport->d_id.b.area,
6035 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 6036 if (rval != QLA_SUCCESS) {
6037 return rval;
6038 }
1da177e4
LT		 6039 if (mb[0] == MBS_PORT_ID_USED) {
6040 /*
6041 * Device has another loop ID. The firmware team
0107109e
AV		 6042 * recommends the driver perform an implicit login with
6043 * the specified ID again. The ID we just used is save
6044 * here so we return with an ID that can be tried by
6045 * the next login.
1da177e4
LT		 6046 */
6047 retry++;
6048 tmp_loopid = fcport->loop_id;
6049 fcport->loop_id = mb[1];
6050
7c3df132
SK		 6051 ql_dbg(ql_dbg_disc, vha, 0x2001,
6052 "Fabric Login: port in use - next loop "
6053 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 6054 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 6055 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 6056
6057 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
6058 /*
6059 * Login succeeded.
6060 */
6061 if (retry) {
6062 /* A retry occurred before. */
6063 *next_loopid = tmp_loopid;
6064 } else {
6065 /*
6066 * No retry occurred before. Just increment the
6067 * ID value for next login.
6068 */
6069 *next_loopid = (fcport->loop_id + 1);
6070 }
6071
6072 if (mb[1] & BIT_0) {
6073 fcport->port_type = FCT_INITIATOR;
6074 } else {
6075 fcport->port_type = FCT_TARGET;
6076 if (mb[1] & BIT_1) {
8474f3a0 6077 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 6078 }
6079 }
6080
ad3e0eda
AV		 6081 if (mb[10] & BIT_0)
6082 fcport->supported_classes |= FC_COS_CLASS2;
6083 if (mb[10] & BIT_1)
6084 fcport->supported_classes |= FC_COS_CLASS3;
6085
2d70c103
NB		 6086 if (IS_FWI2_CAPABLE(ha)) {
6087 if (mb[10] & BIT_7)
6088 fcport->flags |=
6089 FCF_CONF_COMP_SUPPORTED;
6090 }
6091
1da177e4
LT		 6092 rval = QLA_SUCCESS;
6093 break;
6094 } else if (mb[0] == MBS_LOOP_ID_USED) {
6095 /*
6096 * Loop ID already used, try next loop ID.
6097 */
6098 fcport->loop_id++;
e315cd28 6099 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 6100 if (rval != QLA_SUCCESS) {
6101 /* Ran out of loop IDs to use */
6102 break;
6103 }
6104 } else if (mb[0] == MBS_COMMAND_ERROR) {
6105 /*
6106 * Firmware possibly timed out during login. If NO
6107 * retries are left to do then the device is declared
6108 * dead.
6109 */
6110 *next_loopid = fcport->loop_id;
e315cd28 6111 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 6112 fcport->d_id.b.domain, fcport->d_id.b.area,
6113 fcport->d_id.b.al_pa);
e315cd28 6114 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 6115
6116 rval = 1;
6117 break;
6118 } else {
6119 /*
6120 * unrecoverable / not handled error
6121 */
7c3df132
SK		 6122 ql_dbg(ql_dbg_disc, vha, 0x2002,
6123 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
6124 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
6125 fcport->d_id.b.area, fcport->d_id.b.al_pa,
6126 fcport->loop_id, jiffies);
1da177e4
LT		 6127
6128 *next_loopid = fcport->loop_id;
e315cd28 6129 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 6130 fcport->d_id.b.domain, fcport->d_id.b.area,
6131 fcport->d_id.b.al_pa);
5f16b331 6132 qla2x00_clear_loop_id(fcport);
0eedfcf0 6133 fcport->login_retry = 0;
1da177e4
LT		 6134
6135 rval = 3;
6136 break;
6137 }
6138 }
6139
6140 return (rval);
6141}
6142
6143/*
6144 * qla2x00_local_device_login
6145 * Issue local device login command.
6146 *
6147 * Input:
6148 * ha = adapter block pointer.
6149 * loop_id = loop id of device to login to.
6150 *
6151 * Returns (Where's the #define!!!!):
6152 * 0 - Login successfully
6153 * 1 - Login failed
6154 * 3 - Fatal error
6155 */
6156int
e315cd28 6157qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 6158{
6159 int rval;
6160 uint16_t mb[MAILBOX_REGISTER_COUNT];
6161
6162 memset(mb, 0, sizeof(mb));
e315cd28 6163 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 6164 if (rval == QLA_SUCCESS) {
6165 /* Interrogate mailbox registers for any errors */
6166 if (mb[0] == MBS_COMMAND_ERROR)
6167 rval = 1;
6168 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
6169 /* device not in PCB table */
6170 rval = 3;
6171 }
6172
6173 return (rval);
6174}
6175
6176/*
6177 * qla2x00_loop_resync
6178 * Resync with fibre channel devices.
6179 *
6180 * Input:
6181 * ha = adapter block pointer.
6182 *
6183 * Returns:
6184 * 0 = success
6185 */
6186int
e315cd28 6187qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 6188{
73208dfd 6189 int rval = QLA_SUCCESS;
1da177e4 6190 uint32_t wait_time;
1da177e4 6191
e315cd28
AC		 6192 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6193 if (vha->flags.online) {
6194 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 6195 /* Wait at most MAX_TARGET RSCNs for a stable link. */
6196 wait_time = 256;
6197 do {
8ae6d9c7
GM		 6198 if (!IS_QLAFX00(vha->hw)) {
6199 /*
6200 * Issue a marker after FW becomes
6201 * ready.
6202 */
9eb9c6dc
QT		 6203 qla2x00_marker(vha, vha->hw->base_qpair,
6204 0, 0, MK_SYNC_ALL);
8ae6d9c7
GM		 6205 vha->marker_needed = 0;
6206 }
1da177e4
LT		 6207
6208 /* Remap devices on Loop. */
e315cd28 6209 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 6210
8ae6d9c7
GM		 6211 if (IS_QLAFX00(vha->hw))
6212 qlafx00_configure_devices(vha);
6213 else
6214 qla2x00_configure_loop(vha);
6215
1da177e4 6216 wait_time--;
e315cd28
AC		 6217 } while (!atomic_read(&vha->loop_down_timer) &&
6218 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
6219 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
6220 &vha->dpc_flags)));
1da177e4 6221 }
1da177e4
LT		 6222 }
6223
e315cd28 6224 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 6225 return (QLA_FUNCTION_FAILED);
1da177e4 6226
e315cd28 6227 if (rval)
7c3df132
SK		 6228 ql_dbg(ql_dbg_disc, vha, 0x206c,
6229 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 6230
6231 return (rval);
6232}
6233
579d12b5
SK		 6234/*
6235* qla2x00_perform_loop_resync
6236* Description: This function will set the appropriate flags and call
6237* qla2x00_loop_resync. If successful loop will be resynced
6238* Arguments : scsi_qla_host_t pointer
6239* returm : Success or Failure
6240*/
6241
6242int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
6243{
6244 int32_t rval = 0;
6245
6246 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
6247 /*Configure the flags so that resync happens properly*/
6248 atomic_set(&ha->loop_down_timer, 0);
6249 if (!(ha->device_flags & DFLG_NO_CABLE)) {
6250 atomic_set(&ha->loop_state, LOOP_UP);
6251 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
6252 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
6253 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
6254
6255 rval = qla2x00_loop_resync(ha);
6256 } else
6257 atomic_set(&ha->loop_state, LOOP_DEAD);
6258
6259 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
6260 }
6261
6262 return rval;
6263}
6264
d97994dc 6265void
67becc00 6266qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 6267{
6268 fc_port_t *fcport;
feafb7b1
AE		 6269 struct scsi_qla_host *vha;
6270 struct qla_hw_data *ha = base_vha->hw;
6271 unsigned long flags;
d97994dc 6272
feafb7b1 6273 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 6274 /* Go with deferred removal of rport references. */
feafb7b1
AE		 6275 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
6276 atomic_inc(&vha->vref_count);
6277 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 6278 if (fcport->drport &&
feafb7b1
AE		 6279 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
6280 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 6281 qla2x00_rport_del(fcport);
df673274 6282
feafb7b1
AE		 6283 spin_lock_irqsave(&ha->vport_slock, flags);
6284 }
6285 }
6286 atomic_dec(&vha->vref_count);
c4a9b538 6287 wake_up(&vha->vref_waitq);
feafb7b1
AE		 6288 }
6289 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 6290}
6291
7d613ac6
SV		 6292/* Assumes idc_lock always held on entry */
6293void
6294qla83xx_reset_ownership(scsi_qla_host_t *vha)
6295{
6296 struct qla_hw_data *ha = vha->hw;
6297 uint32_t drv_presence, drv_presence_mask;
6298 uint32_t dev_part_info1, dev_part_info2, class_type;
6299 uint32_t class_type_mask = 0x3;
6300 uint16_t fcoe_other_function = 0xffff, i;
6301
7ec0effd
AD		 6302 if (IS_QLA8044(ha)) {
6303 drv_presence = qla8044_rd_direct(vha,
6304 QLA8044_CRB_DRV_ACTIVE_INDEX);
6305 dev_part_info1 = qla8044_rd_direct(vha,
6306 QLA8044_CRB_DEV_PART_INFO_INDEX);
6307 dev_part_info2 = qla8044_rd_direct(vha,
6308 QLA8044_CRB_DEV_PART_INFO2);
6309 } else {
6310 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6311 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
6312 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
6313 }
7d613ac6
SV		 6314 for (i = 0; i < 8; i++) {
6315 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
6316 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
6317 (i != ha->portnum)) {
6318 fcoe_other_function = i;
6319 break;
6320 }
6321 }
6322 if (fcoe_other_function == 0xffff) {
6323 for (i = 0; i < 8; i++) {
6324 class_type = ((dev_part_info2 >> (i * 4)) &
6325 class_type_mask);
6326 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
6327 ((i + 8) != ha->portnum)) {
6328 fcoe_other_function = i + 8;
6329 break;
6330 }
6331 }
6332 }
6333 /*
6334 * Prepare drv-presence mask based on fcoe functions present.
6335 * However consider only valid physical fcoe function numbers (0-15).
6336 */
6337 drv_presence_mask = ~((1 << (ha->portnum)) |
6338 ((fcoe_other_function == 0xffff) ?
6339 0 : (1 << (fcoe_other_function))));
6340
6341 /* We are the reset owner iff:
6342 * - No other protocol drivers present.
6343 * - This is the lowest among fcoe functions. */
6344 if (!(drv_presence & drv_presence_mask) &&
6345 (ha->portnum < fcoe_other_function)) {
6346 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
6347 "This host is Reset owner.\n");
6348 ha->flags.nic_core_reset_owner = 1;
6349 }
6350}
6351
fa492630 6352static int
7d613ac6
SV		 6353__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
6354{
6355 int rval = QLA_SUCCESS;
6356 struct qla_hw_data *ha = vha->hw;
6357 uint32_t drv_ack;
6358
6359 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6360 if (rval == QLA_SUCCESS) {
6361 drv_ack |= (1 << ha->portnum);
6362 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6363 }
6364
6365 return rval;
6366}
6367
fa492630 6368static int
7d613ac6
SV		 6369__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
6370{
6371 int rval = QLA_SUCCESS;
6372 struct qla_hw_data *ha = vha->hw;
6373 uint32_t drv_ack;
6374
6375 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6376 if (rval == QLA_SUCCESS) {
6377 drv_ack &= ~(1 << ha->portnum);
6378 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6379 }
6380
6381 return rval;
6382}
6383
fa492630 6384static const char *
7d613ac6
SV		 6385qla83xx_dev_state_to_string(uint32_t dev_state)
6386{
6387 switch (dev_state) {
6388 case QLA8XXX_DEV_COLD:
6389 return "COLD/RE-INIT";
6390 case QLA8XXX_DEV_INITIALIZING:
6391 return "INITIALIZING";
6392 case QLA8XXX_DEV_READY:
6393 return "READY";
6394 case QLA8XXX_DEV_NEED_RESET:
6395 return "NEED RESET";
6396 case QLA8XXX_DEV_NEED_QUIESCENT:
6397 return "NEED QUIESCENT";
6398 case QLA8XXX_DEV_FAILED:
6399 return "FAILED";
6400 case QLA8XXX_DEV_QUIESCENT:
6401 return "QUIESCENT";
6402 default:
6403 return "Unknown";
6404 }
6405}
6406
6407/* Assumes idc-lock always held on entry */
6408void
6409qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
6410{
6411 struct qla_hw_data *ha = vha->hw;
6412 uint32_t idc_audit_reg = 0, duration_secs = 0;
6413
6414 switch (audit_type) {
6415 case IDC_AUDIT_TIMESTAMP:
6416 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
6417 idc_audit_reg = (ha->portnum) |
6418 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
6419 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6420 break;
6421
6422 case IDC_AUDIT_COMPLETION:
6423 duration_secs = ((jiffies_to_msecs(jiffies) -
6424 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
6425 idc_audit_reg = (ha->portnum) |
6426 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
6427 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6428 break;
6429
6430 default:
6431 ql_log(ql_log_warn, vha, 0xb078,
6432 "Invalid audit type specified.\n");
6433 break;
6434 }
6435}
6436
6437/* Assumes idc_lock always held on entry */
fa492630 6438static int
7d613ac6
SV		 6439qla83xx_initiating_reset(scsi_qla_host_t *vha)
6440{
6441 struct qla_hw_data *ha = vha->hw;
6442 uint32_t idc_control, dev_state;
6443
6444 __qla83xx_get_idc_control(vha, &idc_control);
6445 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
6446 ql_log(ql_log_info, vha, 0xb080,
6447 "NIC Core reset has been disabled. idc-control=0x%x\n",
6448 idc_control);
6449 return QLA_FUNCTION_FAILED;
6450 }
6451
6452 /* Set NEED-RESET iff in READY state and we are the reset-owner */
6453 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6454 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
6455 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
6456 QLA8XXX_DEV_NEED_RESET);
6457 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
6458 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
6459 } else {
6460 const char *state = qla83xx_dev_state_to_string(dev_state);
bd432bb5 6461
7d613ac6
SV		 6462 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
6463
6464 /* SV: XXX: Is timeout required here? */
6465 /* Wait for IDC state change READY -> NEED_RESET */
6466 while (dev_state == QLA8XXX_DEV_READY) {
6467 qla83xx_idc_unlock(vha, 0);
6468 msleep(200);
6469 qla83xx_idc_lock(vha, 0);
6470 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6471 }
6472 }
6473
6474 /* Send IDC ack by writing to drv-ack register */
6475 __qla83xx_set_drv_ack(vha);
6476
6477 return QLA_SUCCESS;
6478}
6479
6480int
6481__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
6482{
6483 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6484}
6485
7d613ac6
SV		 6486int
6487__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
6488{
6489 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6490}
6491
fa492630 6492static int
7d613ac6
SV		 6493qla83xx_check_driver_presence(scsi_qla_host_t *vha)
6494{
6495 uint32_t drv_presence = 0;
6496 struct qla_hw_data *ha = vha->hw;
6497
6498 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6499 if (drv_presence & (1 << ha->portnum))
6500 return QLA_SUCCESS;
6501 else
6502 return QLA_TEST_FAILED;
6503}
6504
6505int
6506qla83xx_nic_core_reset(scsi_qla_host_t *vha)
6507{
6508 int rval = QLA_SUCCESS;
6509 struct qla_hw_data *ha = vha->hw;
6510
6511 ql_dbg(ql_dbg_p3p, vha, 0xb058,
6512 "Entered %s().\n", __func__);
6513
6514 if (vha->device_flags & DFLG_DEV_FAILED) {
6515 ql_log(ql_log_warn, vha, 0xb059,
6516 "Device in unrecoverable FAILED state.\n");
6517 return QLA_FUNCTION_FAILED;
6518 }
6519
6520 qla83xx_idc_lock(vha, 0);
6521
6522 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
6523 ql_log(ql_log_warn, vha, 0xb05a,
6524 "Function=0x%x has been removed from IDC participation.\n",
6525 ha->portnum);
6526 rval = QLA_FUNCTION_FAILED;
6527 goto exit;
6528 }
6529
6530 qla83xx_reset_ownership(vha);
6531
6532 rval = qla83xx_initiating_reset(vha);
6533
6534 /*
6535 * Perform reset if we are the reset-owner,
6536 * else wait till IDC state changes to READY/FAILED.
6537 */
6538 if (rval == QLA_SUCCESS) {
6539 rval = qla83xx_idc_state_handler(vha);
6540
6541 if (rval == QLA_SUCCESS)
6542 ha->flags.nic_core_hung = 0;
6543 __qla83xx_clear_drv_ack(vha);
6544 }
6545
6546exit:
6547 qla83xx_idc_unlock(vha, 0);
6548
6549 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
6550
6551 return rval;
6552}
6553
81178772
SK		 6554int
6555qla2xxx_mctp_dump(scsi_qla_host_t *vha)
6556{
6557 struct qla_hw_data *ha = vha->hw;
6558 int rval = QLA_FUNCTION_FAILED;
6559
6560 if (!IS_MCTP_CAPABLE(ha)) {
6561 /* This message can be removed from the final version */
6562 ql_log(ql_log_info, vha, 0x506d,
6563 "This board is not MCTP capable\n");
6564 return rval;
6565 }
6566
6567 if (!ha->mctp_dump) {
6568 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
6569 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
6570
6571 if (!ha->mctp_dump) {
6572 ql_log(ql_log_warn, vha, 0x506e,
6573 "Failed to allocate memory for mctp dump\n");
6574 return rval;
6575 }
6576 }
6577
6578#define MCTP_DUMP_STR_ADDR 0x00000000
6579 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
6580 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
6581 if (rval != QLA_SUCCESS) {
6582 ql_log(ql_log_warn, vha, 0x506f,
6583 "Failed to capture mctp dump\n");
6584 } else {
6585 ql_log(ql_log_info, vha, 0x5070,
6586 "Mctp dump capture for host (%ld/%p).\n",
6587 vha->host_no, ha->mctp_dump);
6588 ha->mctp_dumped = 1;
6589 }
6590
409ee0fe 6591 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 6592 ha->flags.nic_core_reset_hdlr_active = 1;
6593 rval = qla83xx_restart_nic_firmware(vha);
6594 if (rval)
6595 /* NIC Core reset failed. */
6596 ql_log(ql_log_warn, vha, 0x5071,
6597 "Failed to restart nic firmware\n");
6598 else
6599 ql_dbg(ql_dbg_p3p, vha, 0xb084,
6600 "Restarted NIC firmware successfully.\n");
6601 ha->flags.nic_core_reset_hdlr_active = 0;
6602 }
6603
6604 return rval;
6605
6606}
6607
579d12b5 6608/*
8fcd6b8b 6609* qla2x00_quiesce_io
579d12b5
SK		 6610* Description: This function will block the new I/Os
6611* Its not aborting any I/Os as context
6612* is not destroyed during quiescence
6613* Arguments: scsi_qla_host_t
6614* return : void
6615*/
6616void
8fcd6b8b 6617qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 6618{
6619 struct qla_hw_data *ha = vha->hw;
6620 struct scsi_qla_host *vp;
6621
8fcd6b8b
CD		 6622 ql_dbg(ql_dbg_dpc, vha, 0x401d,
6623 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 6624
6625 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
6626 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6627 atomic_set(&vha->loop_state, LOOP_DOWN);
6628 qla2x00_mark_all_devices_lost(vha, 0);
6629 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 6630 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 6631 } else {
6632 if (!atomic_read(&vha->loop_down_timer))
6633 atomic_set(&vha->loop_down_timer,
6634 LOOP_DOWN_TIME);
6635 }
6636 /* Wait for pending cmds to complete */
6637 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
6638}
6639
a9083016
GM		 6640void
6641qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
6642{
6643 struct qla_hw_data *ha = vha->hw;
579d12b5 6644 struct scsi_qla_host *vp;
feafb7b1 6645 unsigned long flags;
6aef87be 6646 fc_port_t *fcport;
7c3f8fd1 6647 u16 i;
a9083016 6648
e46ef004
SK		 6649 /* For ISP82XX, driver waits for completion of the commands.
6650 * online flag should be set.
6651 */
7ec0effd 6652 if (!(IS_P3P_TYPE(ha)))
e46ef004 6653 vha->flags.online = 0;
a9083016
GM		 6654 ha->flags.chip_reset_done = 0;
6655 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 6656 vha->qla_stats.total_isp_aborts++;
a9083016 6657
7c3df132
SK		 6658 ql_log(ql_log_info, vha, 0x00af,
6659 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 6660
b2000805 6661 ha->flags.purge_mbox = 1;
e46ef004
SK		 6662 /* For ISP82XX, reset_chip is just disabling interrupts.
6663 * Driver waits for the completion of the commands.
6664 * the interrupts need to be enabled.
6665 */
7ec0effd 6666 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 6667 ha->isp_ops->reset_chip(vha);
6668
5d74c87a 6669 ha->link_data_rate = PORT_SPEED_UNKNOWN;
9cd883f0
QT		 6670 SAVE_TOPO(ha);
6671 ha->flags.rida_fmt2 = 0;
ec7193e2
QT		 6672 ha->flags.n2n_ae = 0;
6673 ha->flags.lip_ae = 0;
6674 ha->current_topology = 0;
6675 ha->flags.fw_started = 0;
6676 ha->flags.fw_init_done = 0;
b2000805
QT		 6677 ha->chip_reset++;
6678 ha->base_qpair->chip_reset = ha->chip_reset;
7c3f8fd1
QT		 6679 for (i = 0; i < ha->max_qpairs; i++) {
6680 if (ha->queue_pair_map[i])
6681 ha->queue_pair_map[i]->chip_reset =
6682 ha->base_qpair->chip_reset;
6683 }
726b8548 6684
b2000805
QT		 6685 /* purge MBox commands */
6686 if (atomic_read(&ha->num_pend_mbx_stage3)) {
6687 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
6688 complete(&ha->mbx_intr_comp);
6689 }
6690
6691 i = 0;
6692 while (atomic_read(&ha->num_pend_mbx_stage3) ||
6693 atomic_read(&ha->num_pend_mbx_stage2) ||
6694 atomic_read(&ha->num_pend_mbx_stage1)) {
6695 msleep(20);
6696 i++;
6697 if (i > 50)
6698 break;
6699 }
6700 ha->flags.purge_mbox = 0;
6701
a9083016
GM		 6702 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
6703 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6704 atomic_set(&vha->loop_state, LOOP_DOWN);
6705 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 6706
6707 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 6708 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 6709 atomic_inc(&vp->vref_count);
6710 spin_unlock_irqrestore(&ha->vport_slock, flags);
6711
a9083016 6712 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 6713
6714 spin_lock_irqsave(&ha->vport_slock, flags);
6715 atomic_dec(&vp->vref_count);
6716 }
6717 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 6718 } else {
6719 if (!atomic_read(&vha->loop_down_timer))
6720 atomic_set(&vha->loop_down_timer,
6721 LOOP_DOWN_TIME);
6722 }
6723
6aef87be 6724 /* Clear all async request states across all VPs. */
8b5292bc 6725 list_for_each_entry(fcport, &vha->vp_fcports, list) {
6aef87be 6726 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
8b5292bc
QT		 6727 fcport->scan_state = 0;
6728 }
6aef87be
AV		 6729 spin_lock_irqsave(&ha->vport_slock, flags);
6730 list_for_each_entry(vp, &ha->vp_list, list) {
6731 atomic_inc(&vp->vref_count);
6732 spin_unlock_irqrestore(&ha->vport_slock, flags);
6733
6734 list_for_each_entry(fcport, &vp->vp_fcports, list)
6735 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6736
6737 spin_lock_irqsave(&ha->vport_slock, flags);
6738 atomic_dec(&vp->vref_count);
6739 }
6740 spin_unlock_irqrestore(&ha->vport_slock, flags);
6741
bddd2d65
LC		 6742 if (!ha->flags.eeh_busy) {
6743 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 6744 if (IS_P3P_TYPE(ha)) {
7190575f 6745 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 6746 ql_log(ql_log_info, vha, 0x00b4,
6747 "Done chip reset cleanup.\n");
a9083016 6748
e46ef004
SK		 6749 /* Done waiting for pending commands.
6750 * Reset the online flag.
6751 */
6752 vha->flags.online = 0;
4d78c973 6753 }
a9083016 6754
bddd2d65
LC		 6755 /* Requeue all commands in outstanding command list. */
6756 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
6757 }
b6a029e1
AE		 6758 /* memory barrier */
6759 wmb();
a9083016
GM		 6760}
6761
1da177e4
LT		 6762/*
6763* qla2x00_abort_isp
6764* Resets ISP and aborts all outstanding commands.
6765*
6766* Input:
6767* ha = adapter block pointer.
6768*
6769* Returns:
6770* 0 = success
6771*/
6772int
e315cd28 6773qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 6774{
476e8978 6775 int rval;
1da177e4 6776 uint8_t status = 0;
e315cd28
AC		 6777 struct qla_hw_data *ha = vha->hw;
6778 struct scsi_qla_host *vp;
73208dfd 6779 struct req_que *req = ha->req_q_map[0];
feafb7b1 6780 unsigned long flags;
1da177e4 6781
e315cd28 6782 if (vha->flags.online) {
a9083016 6783 qla2x00_abort_isp_cleanup(vha);
1da177e4 6784
3f006ac3
MH		 6785 if (test_and_clear_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags)) {
6786 ha->flags.chip_reset_done = 1;
6787 vha->flags.online = 1;
6788 status = 0;
6789 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6790 return status;
6791 }
6792
a6171297
SV		 6793 if (IS_QLA8031(ha)) {
6794 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
6795 "Clearing fcoe driver presence.\n");
6796 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
6797 ql_dbg(ql_dbg_p3p, vha, 0xb073,
6798 "Error while clearing DRV-Presence.\n");
6799 }
6800
85880801
AV		 6801 if (unlikely(pci_channel_offline(ha->pdev) &&
6802 ha->flags.pci_channel_io_perm_failure)) {
6803 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6804 status = 0;
6805 return status;
6806 }
6807
0645cb83
QT		 6808 switch (vha->qlini_mode) {
6809 case QLA2XXX_INI_MODE_DISABLED:
6810 if (!qla_tgt_mode_enabled(vha))
6811 return 0;
6812 break;
6813 case QLA2XXX_INI_MODE_DUAL:
6814 if (!qla_dual_mode_enabled(vha))
6815 return 0;
6816 break;
6817 case QLA2XXX_INI_MODE_ENABLED:
6818 default:
6819 break;
6820 }
6821
73208dfd 6822 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 6823
e315cd28 6824 ha->isp_ops->nvram_config(vha);
1da177e4 6825
e315cd28
AC		 6826 if (!qla2x00_restart_isp(vha)) {
6827 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 6828
e315cd28 6829 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 6830 /*
6831 * Issue marker command only when we are going
6832 * to start the I/O .
6833 */
e315cd28 6834 vha->marker_needed = 1;
1da177e4
LT		 6835 }
6836
e315cd28 6837 vha->flags.online = 1;
1da177e4 6838
fd34f556 6839 ha->isp_ops->enable_intrs(ha);
1da177e4 6840
fa2a1ce5 6841 ha->isp_abort_cnt = 0;
e315cd28 6842 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 6843
6246b8a1
GM		 6844 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
6845 qla2x00_get_fw_version(vha);
df613b96
AV		 6846 if (ha->fce) {
6847 ha->flags.fce_enabled = 1;
6848 memset(ha->fce, 0,
6849 fce_calc_size(ha->fce_bufs));
e315cd28 6850 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 6851 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6852 &ha->fce_bufs);
6853 if (rval) {
7c3df132 6854 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 6855 "Unable to reinitialize FCE "
6856 "(%d).\n", rval);
6857 ha->flags.fce_enabled = 0;
6858 }
6859 }
436a7b11
AV		 6860
6861 if (ha->eft) {
6862 memset(ha->eft, 0, EFT_SIZE);
e315cd28 6863 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 6864 ha->eft_dma, EFT_NUM_BUFFERS);
6865 if (rval) {
7c3df132 6866 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 6867 "Unable to reinitialize EFT "
6868 "(%d).\n", rval);
6869 }
6870 }
1da177e4 6871 } else { /* failed the ISP abort */
e315cd28
AC		 6872 vha->flags.online = 1;
6873 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 6874 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 6875 ql_log(ql_log_fatal, vha, 0x8035,
6876 "ISP error recover failed - "
6877 "board disabled.\n");
fa2a1ce5 6878 /*
1da177e4
LT		 6879 * The next call disables the board
6880 * completely.
6881 */
1e4ac5d6 6882 qla2x00_abort_isp_cleanup(vha);
e315cd28 6883 vha->flags.online = 0;
1da177e4 6884 clear_bit(ISP_ABORT_RETRY,
e315cd28 6885 &vha->dpc_flags);
1da177e4
LT		 6886 status = 0;
6887 } else { /* schedule another ISP abort */
6888 ha->isp_abort_cnt--;
7c3df132
SK		 6889 ql_dbg(ql_dbg_taskm, vha, 0x8020,
6890 "ISP abort - retry remaining %d.\n",
6891 ha->isp_abort_cnt);
1da177e4
LT		 6892 status = 1;
6893 }
6894 } else {
6895 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 6896 ql_dbg(ql_dbg_taskm, vha, 0x8021,
6897 "ISP error recovery - retrying (%d) "
6898 "more times.\n", ha->isp_abort_cnt);
e315cd28 6899 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 6900 status = 1;
6901 }
6902 }
fa2a1ce5 6903
1da177e4
LT		 6904 }
6905
e315cd28 6906 if (!status) {
7c3df132 6907 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
1608cc4a 6908 qla2x00_configure_hba(vha);
feafb7b1
AE		 6909 spin_lock_irqsave(&ha->vport_slock, flags);
6910 list_for_each_entry(vp, &ha->vp_list, list) {
6911 if (vp->vp_idx) {
6912 atomic_inc(&vp->vref_count);
6913 spin_unlock_irqrestore(&ha->vport_slock, flags);
6914
e315cd28 6915 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6916
6917 spin_lock_irqsave(&ha->vport_slock, flags);
6918 atomic_dec(&vp->vref_count);
6919 }
e315cd28 6920 }
feafb7b1
AE		 6921 spin_unlock_irqrestore(&ha->vport_slock, flags);
6922
7d613ac6
SV		 6923 if (IS_QLA8031(ha)) {
6924 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
6925 "Setting back fcoe driver presence.\n");
6926 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
6927 ql_dbg(ql_dbg_p3p, vha, 0xb074,
6928 "Error while setting DRV-Presence.\n");
6929 }
e315cd28 6930 } else {
d8424f68
JP		 6931 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
6932 __func__);
1da177e4
LT		 6933 }
6934
6935 return(status);
6936}
6937
6938/*
6939* qla2x00_restart_isp
6940* restarts the ISP after a reset
6941*
6942* Input:
6943* ha = adapter block pointer.
6944*
6945* Returns:
6946* 0 = success
6947*/
6948static int
e315cd28 6949qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 6950{
c6b2fca8 6951 int status = 0;
e315cd28 6952 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 6953
6954 /* If firmware needs to be loaded */
e315cd28
AC		 6955 if (qla2x00_isp_firmware(vha)) {
6956 vha->flags.online = 0;
6957 status = ha->isp_ops->chip_diag(vha);
6958 if (!status)
6959 status = qla2x00_setup_chip(vha);
1da177e4
LT		 6960 }
6961
e315cd28
AC		 6962 if (!status && !(status = qla2x00_init_rings(vha))) {
6963 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 6964 ha->flags.chip_reset_done = 1;
7108b76e 6965
73208dfd
AC		 6966 /* Initialize the queues in use */
6967 qla25xx_init_queues(ha);
6968
e315cd28
AC		 6969 status = qla2x00_fw_ready(vha);
6970 if (!status) {
0107109e 6971 /* Issue a marker after FW becomes ready. */
9eb9c6dc 6972 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
7108b76e 6973 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6974 }
6975
6976 /* if no cable then assume it's good */
e315cd28 6977 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 6978 status = 0;
1da177e4
LT		 6979 }
6980 return (status);
6981}
6982
73208dfd
AC		 6983static int
6984qla25xx_init_queues(struct qla_hw_data *ha)
6985{
6986 struct rsp_que *rsp = NULL;
6987 struct req_que *req = NULL;
6988 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6989 int ret = -1;
6990 int i;
6991
2afa19a9 6992 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 6993 rsp = ha->rsp_q_map[i];
cb43285f 6994 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 6995 rsp->options &= ~BIT_0;
618a7523 6996 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 6997 if (ret != QLA_SUCCESS)
7c3df132
SK		 6998 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
6999 "%s Rsp que: %d init failed.\n",
7000 __func__, rsp->id);
73208dfd 7001 else
7c3df132
SK		 7002 ql_dbg(ql_dbg_init, base_vha, 0x0100,
7003 "%s Rsp que: %d inited.\n",
7004 __func__, rsp->id);
73208dfd 7005 }
2afa19a9
AC		 7006 }
7007 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 7008 req = ha->req_q_map[i];
cb43285f
QT		 7009 if (req && test_bit(i, ha->req_qid_map)) {
7010 /* Clear outstanding commands array. */
73208dfd 7011 req->options &= ~BIT_0;
618a7523 7012 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 7013 if (ret != QLA_SUCCESS)
7c3df132
SK		 7014 ql_dbg(ql_dbg_init, base_vha, 0x0101,
7015 "%s Req que: %d init failed.\n",
7016 __func__, req->id);
73208dfd 7017 else
7c3df132
SK		 7018 ql_dbg(ql_dbg_init, base_vha, 0x0102,
7019 "%s Req que: %d inited.\n",
7020 __func__, req->id);
73208dfd
AC		 7021 }
7022 }
7023 return ret;
7024}
7025
1da177e4
LT		 7026/*
7027* qla2x00_reset_adapter
7028* Reset adapter.
7029*
7030* Input:
7031* ha = adapter block pointer.
7032*/
3f006ac3 7033int
e315cd28 7034qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 7035{
7036 unsigned long flags = 0;
e315cd28 7037 struct qla_hw_data *ha = vha->hw;
3d71644c 7038 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 7039
e315cd28 7040 vha->flags.online = 0;
fd34f556 7041 ha->isp_ops->disable_intrs(ha);
1da177e4 7042
1da177e4
LT		 7043 spin_lock_irqsave(&ha->hardware_lock, flags);
7044 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
7045 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
7046 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
7047 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
7048 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3f006ac3
MH		 7049
7050 return QLA_SUCCESS;
1da177e4 7051}
0107109e 7052
3f006ac3 7053int
e315cd28 7054qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 7055{
7056 unsigned long flags = 0;
e315cd28 7057 struct qla_hw_data *ha = vha->hw;
0107109e 7058 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
3f006ac3 7059 int rval = QLA_SUCCESS;
0107109e 7060
7ec0effd 7061 if (IS_P3P_TYPE(ha))
3f006ac3 7062 return rval;
a9083016 7063
e315cd28 7064 vha->flags.online = 0;
fd34f556 7065 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 7066
7067 spin_lock_irqsave(&ha->hardware_lock, flags);
7068 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
7069 RD_REG_DWORD(&reg->hccr);
7070 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
7071 RD_REG_DWORD(&reg->hccr);
7072 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 7073
7074 if (IS_NOPOLLING_TYPE(ha))
7075 ha->isp_ops->enable_intrs(ha);
3f006ac3
MH		 7076
7077 return rval;
0107109e
AV		 7078}
7079
4e08df3f
DM		 7080/* On sparc systems, obtain port and node WWN from firmware
7081 * properties.
7082 */
e315cd28
AC		 7083static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
7084 struct nvram_24xx *nv)
4e08df3f
DM		 7085{
7086#ifdef CONFIG_SPARC
e315cd28 7087 struct qla_hw_data *ha = vha->hw;
4e08df3f 7088 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 7089 struct device_node *dp = pci_device_to_OF_node(pdev);
7090 const u8 *val;
4e08df3f
DM		 7091 int len;
7092
7093 val = of_get_property(dp, "port-wwn", &len);
7094 if (val && len >= WWN_SIZE)
7095 memcpy(nv->port_name, val, WWN_SIZE);
7096
7097 val = of_get_property(dp, "node-wwn", &len);
7098 if (val && len >= WWN_SIZE)
7099 memcpy(nv->node_name, val, WWN_SIZE);
7100#endif
7101}
7102
0107109e 7103int
e315cd28 7104qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 7105{
4e08df3f 7106 int rval;
0107109e
AV		 7107 struct init_cb_24xx *icb;
7108 struct nvram_24xx *nv;
7109 uint32_t *dptr;
7110 uint8_t *dptr1, *dptr2;
7111 uint32_t chksum;
7112 uint16_t cnt;
e315cd28 7113 struct qla_hw_data *ha = vha->hw;
0107109e 7114
4e08df3f 7115 rval = QLA_SUCCESS;
0107109e 7116 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 7117 nv = ha->nvram;
0107109e
AV		 7118
7119 /* Determine NVRAM starting address. */
f73cb695 7120 if (ha->port_no == 0) {
e5b68a61
AC		 7121 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
7122 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
7123 } else {
0107109e 7124 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 7125 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
7126 }
f73cb695 7127
f8f97b0c 7128 ha->nvram_size = sizeof(*nv);
e5b68a61 7129 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 7130
281afe19
SJ		 7131 /* Get VPD data into cache */
7132 ha->vpd = ha->nvram + VPD_OFFSET;
3695310e 7133 ha->isp_ops->read_nvram(vha, ha->vpd,
281afe19
SJ		 7134 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
7135
7136 /* Get NVRAM data into cache and calculate checksum. */
0107109e 7137 dptr = (uint32_t *)nv;
3695310e 7138 ha->isp_ops->read_nvram(vha, dptr, ha->nvram_base, ha->nvram_size);
da08ef5c
JC		 7139 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
7140 chksum += le32_to_cpu(*dptr);
0107109e 7141
7c3df132
SK		 7142 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
7143 "Contents of NVRAM\n");
7144 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
f8f97b0c 7145 nv, ha->nvram_size);
0107109e
AV		 7146
7147 /* Bad NVRAM data, set defaults parameters. */
a28d9e4e
JC		 7148 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
7149 le16_to_cpu(nv->nvram_version) < ICB_VERSION) {
0107109e 7150 /* Reset NVRAM data. */
7c3df132 7151 ql_log(ql_log_warn, vha, 0x006b,
3695310e
JC		 7152 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n",
7153 chksum, nv->id, nv->nvram_version);
7154 ql_dump_buffer(ql_dbg_init, vha, 0x006b, nv, sizeof(*nv));
7c3df132
SK		 7155 ql_log(ql_log_warn, vha, 0x006c,
7156 "Falling back to functioning (yet invalid -- WWPN) "
7157 "defaults.\n");
4e08df3f
DM		 7158
7159 /*
7160 * Set default initialization control block.
7161 */
7162 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 7163 nv->nvram_version = cpu_to_le16(ICB_VERSION);
7164 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 7165 nv->frame_payload_size = 2048;
ad950360
BVA		 7166 nv->execution_throttle = cpu_to_le16(0xFFFF);
7167 nv->exchange_count = cpu_to_le16(0);
7168 nv->hard_address = cpu_to_le16(124);
4e08df3f 7169 nv->port_name[0] = 0x21;
f73cb695 7170 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 7171 nv->port_name[2] = 0x00;
7172 nv->port_name[3] = 0xe0;
7173 nv->port_name[4] = 0x8b;
7174 nv->port_name[5] = 0x1c;
7175 nv->port_name[6] = 0x55;
7176 nv->port_name[7] = 0x86;
7177 nv->node_name[0] = 0x20;
7178 nv->node_name[1] = 0x00;
7179 nv->node_name[2] = 0x00;
7180 nv->node_name[3] = 0xe0;
7181 nv->node_name[4] = 0x8b;
7182 nv->node_name[5] = 0x1c;
7183 nv->node_name[6] = 0x55;
7184 nv->node_name[7] = 0x86;
e315cd28 7185 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 7186 nv->login_retry_count = cpu_to_le16(8);
7187 nv->interrupt_delay_timer = cpu_to_le16(0);
7188 nv->login_timeout = cpu_to_le16(0);
4e08df3f 7189 nv->firmware_options_1 =
ad950360
BVA		 7190 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7191 nv->firmware_options_2 = cpu_to_le32(2 << 4);
7192 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7193 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7194 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7195 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 7196 nv->reset_delay = 5;
ad950360
BVA		 7197 nv->max_luns_per_target = cpu_to_le16(128);
7198 nv->port_down_retry_count = cpu_to_le16(30);
7199 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 7200
7201 rval = 1;
0107109e
AV		 7202 }
7203
726b8548 7204 if (qla_tgt_mode_enabled(vha)) {
2d70c103 7205 /* Don't enable full login after initial LIP */
ad950360 7206 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 7207 /* Don't enable LIP full login for initiator */
ad950360 7208 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 7209 }
7210
7211 qlt_24xx_config_nvram_stage1(vha, nv);
7212
0107109e 7213 /* Reset Initialization control block */
e315cd28 7214 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 7215
7216 /* Copy 1st segment. */
7217 dptr1 = (uint8_t *)icb;
7218 dptr2 = (uint8_t *)&nv->version;
7219 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7220 while (cnt--)
7221 *dptr1++ = *dptr2++;
7222
7223 icb->login_retry_count = nv->login_retry_count;
3ea66e28 7224 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 7225
7226 /* Copy 2nd segment. */
7227 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7228 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7229 cnt = (uint8_t *)&icb->reserved_3 -
7230 (uint8_t *)&icb->interrupt_delay_timer;
7231 while (cnt--)
7232 *dptr1++ = *dptr2++;
0eaaca4c 7233 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
0107109e
AV		 7234 /*
7235 * Setup driver NVRAM options.
7236 */
e315cd28 7237 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 7238 "QLA2462");
0107109e 7239
2d70c103
NB		 7240 qlt_24xx_config_nvram_stage2(vha, icb);
7241
ad950360 7242 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 7243 /* Use alternate WWN? */
5341e868
AV		 7244 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7245 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7246 }
7247
0107109e 7248 /* Prepare nodename */
ad950360 7249 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 7250 /*
7251 * Firmware will apply the following mask if the nodename was
7252 * not provided.
7253 */
7254 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7255 icb->node_name[0] &= 0xF0;
7256 }
7257
7258 /* Set host adapter parameters. */
7259 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 7260 ha->flags.enable_lip_reset = 0;
7261 ha->flags.enable_lip_full_login =
58e2753c 7262 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0;
0c8c39af 7263 ha->flags.enable_target_reset =
58e2753c 7264 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0;
0107109e 7265 ha->flags.enable_led_scheme = 0;
58e2753c 7266 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0;
0107109e 7267
fd0e7e4d
AV		 7268 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7269 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 7270
7271 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
7272 sizeof(ha->fw_seriallink_options24));
7273
7274 /* save HBA serial number */
7275 ha->serial0 = icb->port_name[5];
7276 ha->serial1 = icb->port_name[6];
7277 ha->serial2 = icb->port_name[7];
e315cd28
AC		 7278 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7279 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 7280
ad950360 7281 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 7282
0107109e
AV		 7283 ha->retry_count = le16_to_cpu(nv->login_retry_count);
7284
7285 /* Set minimum login_timeout to 4 seconds. */
7286 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7287 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7288 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 7289 nv->login_timeout = cpu_to_le16(4);
0107109e 7290 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 7291
00a537b8
AV		 7292 /* Set minimum RATOV to 100 tenths of a second. */
7293 ha->r_a_tov = 100;
0107109e
AV		 7294
7295 ha->loop_reset_delay = nv->reset_delay;
7296
7297 /* Link Down Timeout = 0:
7298 *
7299 * When Port Down timer expires we will start returning
7300 * I/O's to OS with "DID_NO_CONNECT".
7301 *
7302 * Link Down Timeout != 0:
7303 *
7304 * The driver waits for the link to come up after link down
7305 * before returning I/Os to OS with "DID_NO_CONNECT".
7306 */
7307 if (le16_to_cpu(nv->link_down_timeout) == 0) {
7308 ha->loop_down_abort_time =
7309 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7310 } else {
7311 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7312 ha->loop_down_abort_time =
7313 (LOOP_DOWN_TIME - ha->link_down_timeout);
7314 }
7315
7316 /* Need enough time to try and get the port back. */
7317 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7318 if (qlport_down_retry)
7319 ha->port_down_retry_count = qlport_down_retry;
7320
7321 /* Set login_retry_count */
7322 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7323 if (ha->port_down_retry_count ==
7324 le16_to_cpu(nv->port_down_retry_count) &&
7325 ha->port_down_retry_count > 3)
7326 ha->login_retry_count = ha->port_down_retry_count;
7327 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7328 ha->login_retry_count = ha->port_down_retry_count;
7329 if (ql2xloginretrycount)
7330 ha->login_retry_count = ql2xloginretrycount;
7331
8777e431
QT		 7332 /* N2N: driver will initiate Login instead of FW */
7333 icb->firmware_options_3 |= BIT_8;
7334
4fdfefe5 7335 /* Enable ZIO. */
e315cd28 7336 if (!vha->flags.init_done) {
4fdfefe5
AV		 7337 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
7338 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
7339 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
58e2753c 7340 le16_to_cpu(icb->interrupt_delay_timer) : 2;
4fdfefe5 7341 }
ad950360 7342 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 7343 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
4fdfefe5 7344 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 7345 ha->zio_mode = QLA_ZIO_MODE_6;
7346
7c3df132 7347 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 7348 "ZIO mode %d enabled; timer delay (%d us).\n",
7349 ha->zio_mode, ha->zio_timer * 100);
7350
7351 icb->firmware_options_2 |= cpu_to_le32(
7352 (uint32_t)ha->zio_mode);
7353 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
4fdfefe5
AV		 7354 }
7355
4e08df3f 7356 if (rval) {
7c3df132
SK		 7357 ql_log(ql_log_warn, vha, 0x0070,
7358 "NVRAM configuration failed.\n");
4e08df3f
DM		 7359 }
7360 return (rval);
0107109e
AV		 7361}
7362
5fa8774c
JC		 7363static void
7364qla27xx_print_image(struct scsi_qla_host *vha, char *name,
7365 struct qla27xx_image_status *image_status)
7366{
7367 ql_dbg(ql_dbg_init, vha, 0x018b,
7368 "%s %s: mask=%#02x gen=%#04x ver=%u.%u map=%#01x sum=%#08x sig=%#08x\n",
7369 name, "status",
7370 image_status->image_status_mask,
7371 le16_to_cpu(image_status->generation),
7372 image_status->ver_major,
7373 image_status->ver_minor,
7374 image_status->bitmap,
7375 le32_to_cpu(image_status->checksum),
7376 le32_to_cpu(image_status->signature));
7377}
7378
7379static bool
7380qla28xx_check_aux_image_status_signature(
7381 struct qla27xx_image_status *image_status)
7382{
7383 ulong signature = le32_to_cpu(image_status->signature);
7384
7385 return signature != QLA28XX_AUX_IMG_STATUS_SIGN;
7386}
7387
7388static bool
7389qla27xx_check_image_status_signature(struct qla27xx_image_status *image_status)
7390{
7391 ulong signature = le32_to_cpu(image_status->signature);
7392
7393 return
7394 signature != QLA27XX_IMG_STATUS_SIGN &&
7395 signature != QLA28XX_IMG_STATUS_SIGN;
7396}
7397
7398static ulong
7399qla27xx_image_status_checksum(struct qla27xx_image_status *image_status)
7400{
7401 uint32_t *p = (void *)image_status;
7402 uint n = sizeof(*image_status) / sizeof(*p);
7403 uint32_t sum = 0;
7404
7405 for ( ; n--; p++)
7406 sum += le32_to_cpup(p);
7407
7408 return sum;
7409}
7410
7411static inline uint
7412qla28xx_component_bitmask(struct qla27xx_image_status *aux, uint bitmask)
7413{
7414 return aux->bitmap & bitmask ?
7415 QLA27XX_SECONDARY_IMAGE : QLA27XX_PRIMARY_IMAGE;
7416}
7417
7418static void
7419qla28xx_component_status(
7420 struct active_regions *active_regions, struct qla27xx_image_status *aux)
7421{
7422 active_regions->aux.board_config =
7423 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_BOARD_CONFIG);
7424
7425 active_regions->aux.vpd_nvram =
7426 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_VPD_NVRAM);
7427
7428 active_regions->aux.npiv_config_0_1 =
7429 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_0_1);
7430
7431 active_regions->aux.npiv_config_2_3 =
7432 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_2_3);
7433}
7434
7435static int
7436qla27xx_compare_image_generation(
7437 struct qla27xx_image_status *pri_image_status,
7438 struct qla27xx_image_status *sec_image_status)
7439{
7440 /* calculate generation delta as uint16 (this accounts for wrap) */
7441 int16_t delta =
7442 le16_to_cpu(pri_image_status->generation) -
7443 le16_to_cpu(sec_image_status->generation);
7444
7445 ql_dbg(ql_dbg_init, NULL, 0x0180, "generation delta = %d\n", delta);
7446
7447 return delta;
7448}
7449
7450void
7451qla28xx_get_aux_images(
7452 struct scsi_qla_host *vha, struct active_regions *active_regions)
4243c115 7453{
4243c115 7454 struct qla_hw_data *ha = vha->hw;
5fa8774c
JC		 7455 struct qla27xx_image_status pri_aux_image_status, sec_aux_image_status;
7456 bool valid_pri_image = false, valid_sec_image = false;
7457 bool active_pri_image = false, active_sec_image = false;
7458
7459 if (!ha->flt_region_aux_img_status_pri) {
7460 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary aux image not addressed\n");
7461 goto check_sec_image;
7462 }
7463
7464 qla24xx_read_flash_data(vha, (void *)&pri_aux_image_status,
7465 ha->flt_region_aux_img_status_pri,
7466 sizeof(pri_aux_image_status) >> 2);
7467 qla27xx_print_image(vha, "Primary aux image", &pri_aux_image_status);
7468
7469 if (qla28xx_check_aux_image_status_signature(&pri_aux_image_status)) {
7470 ql_dbg(ql_dbg_init, vha, 0x018b,
7471 "Primary aux image signature (%#x) not valid\n",
7472 le32_to_cpu(pri_aux_image_status.signature));
7473 goto check_sec_image;
7474 }
7475
7476 if (qla27xx_image_status_checksum(&pri_aux_image_status)) {
7477 ql_dbg(ql_dbg_init, vha, 0x018c,
7478 "Primary aux image checksum failed\n");
7479 goto check_sec_image;
7480 }
7481
7482 valid_pri_image = true;
7483
7484 if (pri_aux_image_status.image_status_mask & 1) {
7485 ql_dbg(ql_dbg_init, vha, 0x018d,
7486 "Primary aux image is active\n");
7487 active_pri_image = true;
7488 }
7489
7490check_sec_image:
7491 if (!ha->flt_region_aux_img_status_sec) {
7492 ql_dbg(ql_dbg_init, vha, 0x018a,
7493 "Secondary aux image not addressed\n");
7494 goto check_valid_image;
7495 }
7496
7497 qla24xx_read_flash_data(vha, (void *)&sec_aux_image_status,
7498 ha->flt_region_aux_img_status_sec,
7499 sizeof(sec_aux_image_status) >> 2);
7500 qla27xx_print_image(vha, "Secondary aux image", &sec_aux_image_status);
7501
7502 if (qla28xx_check_aux_image_status_signature(&sec_aux_image_status)) {
7503 ql_dbg(ql_dbg_init, vha, 0x018b,
7504 "Secondary aux image signature (%#x) not valid\n",
7505 le32_to_cpu(sec_aux_image_status.signature));
7506 goto check_valid_image;
7507 }
7508
7509 if (qla27xx_image_status_checksum(&sec_aux_image_status)) {
7510 ql_dbg(ql_dbg_init, vha, 0x018c,
7511 "Secondary aux image checksum failed\n");
7512 goto check_valid_image;
7513 }
4243c115 7514
5fa8774c
JC		 7515 valid_sec_image = true;
7516
7517 if (sec_aux_image_status.image_status_mask & 1) {
7518 ql_dbg(ql_dbg_init, vha, 0x018d,
7519 "Secondary aux image is active\n");
7520 active_sec_image = true;
7521 }
7522
7523check_valid_image:
7524 if (valid_pri_image && active_pri_image &&
7525 valid_sec_image && active_sec_image) {
7526 if (qla27xx_compare_image_generation(&pri_aux_image_status,
7527 &sec_aux_image_status) >= 0) {
7528 qla28xx_component_status(active_regions,
7529 &pri_aux_image_status);
7530 } else {
7531 qla28xx_component_status(active_regions,
7532 &sec_aux_image_status);
7533 }
7534 } else if (valid_pri_image && active_pri_image) {
7535 qla28xx_component_status(active_regions, &pri_aux_image_status);
7536 } else if (valid_sec_image && active_sec_image) {
7537 qla28xx_component_status(active_regions, &sec_aux_image_status);
7538 }
7539
7540 ql_dbg(ql_dbg_init, vha, 0x018f,
7541 "aux images active: BCFG=%u VPD/NVR=%u NPIV0/1=%u NPIV2/3=%u\n",
7542 active_regions->aux.board_config,
7543 active_regions->aux.vpd_nvram,
7544 active_regions->aux.npiv_config_0_1,
7545 active_regions->aux.npiv_config_2_3);
7546}
7547
7548void
7549qla27xx_get_active_image(struct scsi_qla_host *vha,
7550 struct active_regions *active_regions)
7551{
7552 struct qla_hw_data *ha = vha->hw;
7553 struct qla27xx_image_status pri_image_status, sec_image_status;
7554 bool valid_pri_image = false, valid_sec_image = false;
7555 bool active_pri_image = false, active_sec_image = false;
4243c115
SC		 7556
7557 if (!ha->flt_region_img_status_pri) {
5fa8774c 7558 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary image not addressed\n");
4243c115
SC		 7559 goto check_sec_image;
7560 }
7561
5fa8774c
JC		 7562 qla24xx_read_flash_data(vha, (void *)(&pri_image_status),
7563 ha->flt_region_img_status_pri, sizeof(pri_image_status) >> 2);
7564 qla27xx_print_image(vha, "Primary image", &pri_image_status);
4243c115 7565
5fa8774c 7566 if (qla27xx_check_image_status_signature(&pri_image_status)) {
4243c115 7567 ql_dbg(ql_dbg_init, vha, 0x018b,
f8f97b0c
JC		 7568 "Primary image signature (%#x) not valid\n",
7569 le32_to_cpu(pri_image_status.signature));
4243c115
SC		 7570 goto check_sec_image;
7571 }
7572
5fa8774c
JC		 7573 if (qla27xx_image_status_checksum(&pri_image_status)) {
7574 ql_dbg(ql_dbg_init, vha, 0x018c,
7575 "Primary image checksum failed\n");
7576 goto check_sec_image;
7577 }
4243c115 7578
5fa8774c 7579 valid_pri_image = true;
41dc529a 7580
5fa8774c
JC		 7581 if (pri_image_status.image_status_mask & 1) {
7582 ql_dbg(ql_dbg_init, vha, 0x018d,
7583 "Primary image is active\n");
7584 active_pri_image = true;
4243c115
SC		 7585 }
7586
7587check_sec_image:
7588 if (!ha->flt_region_img_status_sec) {
5fa8774c 7589 ql_dbg(ql_dbg_init, vha, 0x018a, "Secondary image not addressed\n");
4243c115
SC		 7590 goto check_valid_image;
7591 }
7592
7593 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
5fa8774c
JC		 7594 ha->flt_region_img_status_sec, sizeof(sec_image_status) >> 2);
7595 qla27xx_print_image(vha, "Secondary image", &sec_image_status);
4243c115 7596
5fa8774c
JC		 7597 if (qla27xx_check_image_status_signature(&sec_image_status)) {
7598 ql_dbg(ql_dbg_init, vha, 0x018b,
f8f97b0c
JC		 7599 "Secondary image signature (%#x) not valid\n",
7600 le32_to_cpu(sec_image_status.signature));
4243c115
SC		 7601 goto check_valid_image;
7602 }
7603
5fa8774c
JC		 7604 if (qla27xx_image_status_checksum(&sec_image_status)) {
7605 ql_dbg(ql_dbg_init, vha, 0x018c,
7606 "Secondary image checksum failed\n");
7607 goto check_valid_image;
7608 }
7609
7610 valid_sec_image = true;
7611
7612 if (sec_image_status.image_status_mask & 1) {
7613 ql_dbg(ql_dbg_init, vha, 0x018d,
7614 "Secondary image is active\n");
7615 active_sec_image = true;
4243c115
SC		 7616 }
7617
7618check_valid_image:
5fa8774c
JC		 7619 if (valid_pri_image && active_pri_image)
7620 active_regions->global = QLA27XX_PRIMARY_IMAGE;
7621
7622 if (valid_sec_image && active_sec_image) {
7623 if (!active_regions->global ||
7624 qla27xx_compare_image_generation(
7625 &pri_image_status, &sec_image_status) < 0) {
7626 active_regions->global = QLA27XX_SECONDARY_IMAGE;
f8f97b0c 7627 }
4243c115
SC		 7628 }
7629
5fa8774c
JC		 7630 ql_dbg(ql_dbg_init, vha, 0x018f, "active image %s (%u)\n",
7631 active_regions->global == QLA27XX_DEFAULT_IMAGE ?
7632 "default (boot/fw)" :
7633 active_regions->global == QLA27XX_PRIMARY_IMAGE ?
7634 "primary" :
7635 active_regions->global == QLA27XX_SECONDARY_IMAGE ?
7636 "secondary" : "invalid",
7637 active_regions->global);
4243c115
SC		 7638}
7639
f8f97b0c
JC		 7640bool qla24xx_risc_firmware_invalid(uint32_t *dword)
7641{
7642 return
7643 !(dword[4] | dword[5] | dword[6] | dword[7]) ||
7644 !(~dword[4] | ~dword[5] | ~dword[6] | ~dword[7]);
7645}
7646
413975a0 7647static int
cbc8eb67
AV		 7648qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
7649 uint32_t faddr)
d1c61909 7650{
a28d9e4e
JC		 7651 int rval;
7652 uint templates, segments, fragment;
7653 ulong i;
7654 uint j;
7655 ulong dlen;
7656 uint32_t *dcode;
7657 uint32_t risc_addr, risc_size, risc_attr = 0;
e315cd28 7658 struct qla_hw_data *ha = vha->hw;
73208dfd 7659 struct req_que *req = ha->req_q_map[0];
a28d9e4e 7660 struct fwdt *fwdt = ha->fwdt;
eaac30be 7661
7c3df132 7662 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 7663 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 7664
f8f97b0c
JC		 7665 dcode = (void *)req->ring;
7666 qla24xx_read_flash_data(vha, dcode, faddr, 8);
7667 if (qla24xx_risc_firmware_invalid(dcode)) {
7c3df132
SK		 7668 ql_log(ql_log_fatal, vha, 0x008c,
7669 "Unable to verify the integrity of flash firmware "
7670 "image.\n");
7671 ql_log(ql_log_fatal, vha, 0x008d,
7672 "Firmware data: %08x %08x %08x %08x.\n",
7673 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 7674
7675 return QLA_FUNCTION_FAILED;
7676 }
7677
a28d9e4e
JC		 7678 dcode = (void *)req->ring;
7679 *srisc_addr = 0;
7680 segments = FA_RISC_CODE_SEGMENTS;
7681 for (j = 0; j < segments; j++) {
7682 ql_dbg(ql_dbg_init, vha, 0x008d,
7683 "-> Loading segment %u...\n", j);
7684 qla24xx_read_flash_data(vha, dcode, faddr, 10);
d1c61909 7685 risc_addr = be32_to_cpu(dcode[2]);
d1c61909 7686 risc_size = be32_to_cpu(dcode[3]);
a28d9e4e
JC		 7687 if (!*srisc_addr) {
7688 *srisc_addr = risc_addr;
7689 risc_attr = be32_to_cpu(dcode[9]);
7690 }
d1c61909 7691
a28d9e4e
JC		 7692 dlen = ha->fw_transfer_size >> 2;
7693 for (fragment = 0; risc_size; fragment++) {
d1c61909
AV		 7694 if (dlen > risc_size)
7695 dlen = risc_size;
7696
7c3df132 7697 ql_dbg(ql_dbg_init, vha, 0x008e,
a28d9e4e
JC		 7698 "-> Loading fragment %u: %#x <- %#x (%#lx dwords)...\n",
7699 fragment, risc_addr, faddr, dlen);
e315cd28 7700 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 7701 for (i = 0; i < dlen; i++)
7702 dcode[i] = swab32(dcode[i]);
7703
a28d9e4e 7704 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen);
d1c61909 7705 if (rval) {
7c3df132 7706 ql_log(ql_log_fatal, vha, 0x008f,
a28d9e4e 7707 "-> Failed load firmware fragment %u.\n",
7c3df132 7708 fragment);
f261f7af 7709 return QLA_FUNCTION_FAILED;
d1c61909
AV		 7710 }
7711
7712 faddr += dlen;
7713 risc_addr += dlen;
7714 risc_size -= dlen;
d1c61909 7715 }
d1c61909
AV		 7716 }
7717
ecc89f25 7718 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
a28d9e4e 7719 return QLA_SUCCESS;
f73cb695 7720
a28d9e4e
JC		 7721 templates = (risc_attr & BIT_9) ? 2 : 1;
7722 ql_dbg(ql_dbg_init, vha, 0x0160, "-> templates = %u\n", templates);
7723 for (j = 0; j < templates; j++, fwdt++) {
7724 if (fwdt->template)
7725 vfree(fwdt->template);
7726 fwdt->template = NULL;
7727 fwdt->length = 0;
7728
3695310e 7729 dcode = (void *)req->ring;
a28d9e4e
JC		 7730 qla24xx_read_flash_data(vha, dcode, faddr, 7);
7731 risc_size = be32_to_cpu(dcode[2]);
7732 ql_dbg(ql_dbg_init, vha, 0x0161,
7733 "-> fwdt%u template array at %#x (%#x dwords)\n",
7734 j, faddr, risc_size);
7735 if (!risc_size || !~risc_size) {
7736 ql_dbg(ql_dbg_init, vha, 0x0162,
7737 "-> fwdt%u failed to read array\n", j);
7738 goto failed;
7739 }
f73cb695 7740
a28d9e4e
JC		 7741 /* skip header and ignore checksum */
7742 faddr += 7;
7743 risc_size -= 8;
7744
7745 ql_dbg(ql_dbg_init, vha, 0x0163,
7746 "-> fwdt%u template allocate template %#x words...\n",
7747 j, risc_size);
7748 fwdt->template = vmalloc(risc_size * sizeof(*dcode));
7749 if (!fwdt->template) {
7750 ql_log(ql_log_warn, vha, 0x0164,
7751 "-> fwdt%u failed allocate template.\n", j);
7752 goto failed;
7753 }
f73cb695 7754
a28d9e4e
JC		 7755 dcode = fwdt->template;
7756 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
f73cb695 7757
a28d9e4e
JC		 7758 if (!qla27xx_fwdt_template_valid(dcode)) {
7759 ql_log(ql_log_warn, vha, 0x0165,
7760 "-> fwdt%u failed template validate\n", j);
7761 goto failed;
7762 }
f73cb695 7763
a28d9e4e
JC		 7764 dlen = qla27xx_fwdt_template_size(dcode);
7765 ql_dbg(ql_dbg_init, vha, 0x0166,
7766 "-> fwdt%u template size %#lx bytes (%#lx words)\n",
7767 j, dlen, dlen / sizeof(*dcode));
7768 if (dlen > risc_size * sizeof(*dcode)) {
7769 ql_log(ql_log_warn, vha, 0x0167,
7770 "-> fwdt%u template exceeds array (%-lu bytes)\n",
7771 j, dlen - risc_size * sizeof(*dcode));
7772 goto failed;
7773 }
7774
7775 fwdt->length = dlen;
7776 ql_dbg(ql_dbg_init, vha, 0x0168,
7777 "-> fwdt%u loaded template ok\n", j);
7778
7779 faddr += risc_size + 1;
f73cb695 7780 }
a28d9e4e
JC		 7781
7782 return QLA_SUCCESS;
f73cb695 7783
2ff6ae85 7784failed:
a28d9e4e
JC		 7785 if (fwdt->template)
7786 vfree(fwdt->template);
7787 fwdt->template = NULL;
7788 fwdt->length = 0;
7789
7790 return QLA_SUCCESS;
d1c61909
AV		 7791}
7792
e9454a88 7793#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 7794
0107109e 7795int
e315cd28 7796qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 7797{
7798 int rval;
7799 int i, fragment;
7800 uint16_t *wcode, *fwcode;
7801 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
7802 struct fw_blob *blob;
e315cd28 7803 struct qla_hw_data *ha = vha->hw;
73208dfd 7804 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 7805
7806 /* Load firmware blob. */
e315cd28 7807 blob = qla2x00_request_firmware(vha);
5433383e 7808 if (!blob) {
7c3df132 7809 ql_log(ql_log_info, vha, 0x0083,
94bcf830 7810 "Firmware image unavailable.\n");
7c3df132
SK		 7811 ql_log(ql_log_info, vha, 0x0084,
7812 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 7813 return QLA_FUNCTION_FAILED;
7814 }
7815
7816 rval = QLA_SUCCESS;
7817
73208dfd 7818 wcode = (uint16_t *)req->ring;
5433383e
AV		 7819 *srisc_addr = 0;
7820 fwcode = (uint16_t *)blob->fw->data;
7821 fwclen = 0;
7822
7823 /* Validate firmware image by checking version. */
7824 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132 7825 ql_log(ql_log_fatal, vha, 0x0085,
5b5e0928 7826 "Unable to verify integrity of firmware image (%zd).\n",
5433383e
AV		 7827 blob->fw->size);
7828 goto fail_fw_integrity;
7829 }
7830 for (i = 0; i < 4; i++)
7831 wcode[i] = be16_to_cpu(fwcode[i + 4]);
7832 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
7833 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
7834 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 7835 ql_log(ql_log_fatal, vha, 0x0086,
7836 "Unable to verify integrity of firmware image.\n");
7837 ql_log(ql_log_fatal, vha, 0x0087,
7838 "Firmware data: %04x %04x %04x %04x.\n",
7839 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 7840 goto fail_fw_integrity;
7841 }
7842
7843 seg = blob->segs;
7844 while (*seg && rval == QLA_SUCCESS) {
7845 risc_addr = *seg;
7846 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
7847 risc_size = be16_to_cpu(fwcode[3]);
7848
7849 /* Validate firmware image size. */
7850 fwclen += risc_size * sizeof(uint16_t);
7851 if (blob->fw->size < fwclen) {
7c3df132 7852 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 7853 "Unable to verify integrity of firmware image "
5b5e0928 7854 "(%zd).\n", blob->fw->size);
5433383e
AV		 7855 goto fail_fw_integrity;
7856 }
7857
7858 fragment = 0;
7859 while (risc_size > 0 && rval == QLA_SUCCESS) {
7860 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
7861 if (wlen > risc_size)
7862 wlen = risc_size;
7c3df132
SK		 7863 ql_dbg(ql_dbg_init, vha, 0x0089,
7864 "Loading risc segment@ risc addr %x number of "
7865 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 7866
7867 for (i = 0; i < wlen; i++)
7868 wcode[i] = swab16(fwcode[i]);
7869
73208dfd 7870 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 7871 wlen);
7872 if (rval) {
7c3df132
SK		 7873 ql_log(ql_log_fatal, vha, 0x008a,
7874 "Failed to load segment %d of firmware.\n",
7875 fragment);
5433383e
AV		 7876 break;
7877 }
7878
7879 fwcode += wlen;
7880 risc_addr += wlen;
7881 risc_size -= wlen;
7882 fragment++;
7883 }
7884
7885 /* Next segment. */
7886 seg++;
7887 }
7888 return rval;
7889
7890fail_fw_integrity:
7891 return QLA_FUNCTION_FAILED;
7892}
7893
eaac30be
AV		 7894static int
7895qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 7896{
7897 int rval;
a28d9e4e
JC		 7898 uint templates, segments, fragment;
7899 uint32_t *dcode;
7900 ulong dlen;
7901 uint32_t risc_addr, risc_size, risc_attr = 0;
7902 ulong i;
7903 uint j;
5433383e 7904 struct fw_blob *blob;
f8f97b0c 7905 uint32_t *fwcode;
e315cd28 7906 struct qla_hw_data *ha = vha->hw;
73208dfd 7907 struct req_que *req = ha->req_q_map[0];
a28d9e4e
JC		 7908 struct fwdt *fwdt = ha->fwdt;
7909
7910 ql_dbg(ql_dbg_init, vha, 0x0090,
7911 "-> FW: Loading via request-firmware.\n");
0107109e 7912
e315cd28 7913 blob = qla2x00_request_firmware(vha);
5433383e 7914 if (!blob) {
a28d9e4e
JC		 7915 ql_log(ql_log_warn, vha, 0x0092,
7916 "-> Firmware file not found.\n");
d1c61909 7917
eaac30be 7918 return QLA_FUNCTION_FAILED;
0107109e
AV		 7919 }
7920
f8f97b0c 7921 fwcode = (void *)blob->fw->data;
1710ac17 7922 dcode = fwcode;
f8f97b0c 7923 if (qla24xx_risc_firmware_invalid(dcode)) {
7c3df132 7924 ql_log(ql_log_fatal, vha, 0x0093,
5b5e0928 7925 "Unable to verify integrity of firmware image (%zd).\n",
5433383e 7926 blob->fw->size);
7c3df132
SK		 7927 ql_log(ql_log_fatal, vha, 0x0095,
7928 "Firmware data: %08x %08x %08x %08x.\n",
7929 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 7930 return QLA_FUNCTION_FAILED;
0107109e
AV		 7931 }
7932
a28d9e4e
JC		 7933 dcode = (void *)req->ring;
7934 *srisc_addr = 0;
7935 segments = FA_RISC_CODE_SEGMENTS;
7936 for (j = 0; j < segments; j++) {
7937 ql_dbg(ql_dbg_init, vha, 0x0096,
7938 "-> Loading segment %u...\n", j);
0107109e 7939 risc_addr = be32_to_cpu(fwcode[2]);
0107109e
AV		 7940 risc_size = be32_to_cpu(fwcode[3]);
7941
a28d9e4e
JC		 7942 if (!*srisc_addr) {
7943 *srisc_addr = risc_addr;
7944 risc_attr = be32_to_cpu(fwcode[9]);
0107109e
AV		 7945 }
7946
a28d9e4e
JC		 7947 dlen = ha->fw_transfer_size >> 2;
7948 for (fragment = 0; risc_size; fragment++) {
0107109e
AV		 7949 if (dlen > risc_size)
7950 dlen = risc_size;
7951
7c3df132 7952 ql_dbg(ql_dbg_init, vha, 0x0097,
a28d9e4e
JC		 7953 "-> Loading fragment %u: %#x <- %#x (%#lx words)...\n",
7954 fragment, risc_addr,
7955 (uint32_t)(fwcode - (typeof(fwcode))blob->fw->data),
7956 dlen);
0107109e
AV		 7957
7958 for (i = 0; i < dlen; i++)
7959 dcode[i] = swab32(fwcode[i]);
7960
a28d9e4e 7961 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen);
0107109e 7962 if (rval) {
7c3df132 7963 ql_log(ql_log_fatal, vha, 0x0098,
a28d9e4e 7964 "-> Failed load firmware fragment %u.\n",
7c3df132 7965 fragment);
f261f7af 7966 return QLA_FUNCTION_FAILED;
0107109e
AV		 7967 }
7968
7969 fwcode += dlen;
7970 risc_addr += dlen;
7971 risc_size -= dlen;
0107109e 7972 }
0107109e 7973 }
f73cb695 7974
ecc89f25 7975 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
a28d9e4e 7976 return QLA_SUCCESS;
f73cb695 7977
a28d9e4e
JC		 7978 templates = (risc_attr & BIT_9) ? 2 : 1;
7979 ql_dbg(ql_dbg_init, vha, 0x0170, "-> templates = %u\n", templates);
7980 for (j = 0; j < templates; j++, fwdt++) {
7981 if (fwdt->template)
7982 vfree(fwdt->template);
7983 fwdt->template = NULL;
7984 fwdt->length = 0;
7985
7986 risc_size = be32_to_cpu(fwcode[2]);
7987 ql_dbg(ql_dbg_init, vha, 0x0171,
7988 "-> fwdt%u template array at %#x (%#x dwords)\n",
7989 j, (uint32_t)((void *)fwcode - (void *)blob->fw->data),
7990 risc_size);
7991 if (!risc_size || !~risc_size) {
7992 ql_dbg(ql_dbg_init, vha, 0x0172,
7993 "-> fwdt%u failed to read array\n", j);
7994 goto failed;
7995 }
f73cb695 7996
a28d9e4e
JC		 7997 /* skip header and ignore checksum */
7998 fwcode += 7;
7999 risc_size -= 8;
8000
8001 ql_dbg(ql_dbg_init, vha, 0x0173,
8002 "-> fwdt%u template allocate template %#x words...\n",
8003 j, risc_size);
8004 fwdt->template = vmalloc(risc_size * sizeof(*dcode));
8005 if (!fwdt->template) {
8006 ql_log(ql_log_warn, vha, 0x0174,
8007 "-> fwdt%u failed allocate template.\n", j);
8008 goto failed;
8009 }
f73cb695 8010
a28d9e4e
JC		 8011 dcode = fwdt->template;
8012 for (i = 0; i < risc_size; i++)
5fa8774c 8013 dcode[i] = fwcode[i];
f73cb695 8014
a28d9e4e
JC		 8015 if (!qla27xx_fwdt_template_valid(dcode)) {
8016 ql_log(ql_log_warn, vha, 0x0175,
8017 "-> fwdt%u failed template validate\n", j);
8018 goto failed;
8019 }
f73cb695 8020
a28d9e4e
JC		 8021 dlen = qla27xx_fwdt_template_size(dcode);
8022 ql_dbg(ql_dbg_init, vha, 0x0176,
8023 "-> fwdt%u template size %#lx bytes (%#lx words)\n",
8024 j, dlen, dlen / sizeof(*dcode));
8025 if (dlen > risc_size * sizeof(*dcode)) {
8026 ql_log(ql_log_warn, vha, 0x0177,
8027 "-> fwdt%u template exceeds array (%-lu bytes)\n",
8028 j, dlen - risc_size * sizeof(*dcode));
8029 goto failed;
8030 }
8031
8032 fwdt->length = dlen;
8033 ql_dbg(ql_dbg_init, vha, 0x0178,
8034 "-> fwdt%u loaded template ok\n", j);
8035
8036 fwcode += risc_size + 1;
f73cb695 8037 }
a28d9e4e
JC		 8038
8039 return QLA_SUCCESS;
f73cb695 8040
2ff6ae85 8041failed:
a28d9e4e
JC		 8042 if (fwdt->template)
8043 vfree(fwdt->template);
8044 fwdt->template = NULL;
8045 fwdt->length = 0;
8046
8047 return QLA_SUCCESS;
0107109e 8048}
18c6c127 8049
eaac30be
AV		 8050int
8051qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
8052{
8053 int rval;
8054
e337d907
AV		 8055 if (ql2xfwloadbin == 1)
8056 return qla81xx_load_risc(vha, srisc_addr);
8057
eaac30be
AV		 8058 /*
8059 * FW Load priority:
8060 * 1) Firmware via request-firmware interface (.bin file).
8061 * 2) Firmware residing in flash.
8062 */
8063 rval = qla24xx_load_risc_blob(vha, srisc_addr);
8064 if (rval == QLA_SUCCESS)
8065 return rval;
8066
cbc8eb67
AV		 8067 return qla24xx_load_risc_flash(vha, srisc_addr,
8068 vha->hw->flt_region_fw);
eaac30be
AV		 8069}
8070
8071int
8072qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
8073{
8074 int rval;
cbc8eb67 8075 struct qla_hw_data *ha = vha->hw;
5fa8774c 8076 struct active_regions active_regions = { };
eaac30be 8077
e337d907 8078 if (ql2xfwloadbin == 2)
cbc8eb67 8079 goto try_blob_fw;
e337d907 8080
f8f97b0c 8081 /* FW Load priority:
eaac30be
AV		 8082 * 1) Firmware residing in flash.
8083 * 2) Firmware via request-firmware interface (.bin file).
f8f97b0c 8084 * 3) Golden-Firmware residing in flash -- (limited operation).
eaac30be 8085 */
f8f97b0c 8086
5fa8774c 8087 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
f8f97b0c
JC		 8088 goto try_primary_fw;
8089
5fa8774c
JC		 8090 qla27xx_get_active_image(vha, &active_regions);
8091
8092 if (active_regions.global != QLA27XX_SECONDARY_IMAGE)
f8f97b0c
JC		 8093 goto try_primary_fw;
8094
8095 ql_dbg(ql_dbg_init, vha, 0x008b,
8096 "Loading secondary firmware image.\n");
8097 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw_sec);
8098 if (!rval)
8099 return rval;
8100
8101try_primary_fw:
8102 ql_dbg(ql_dbg_init, vha, 0x008b,
8103 "Loading primary firmware image.\n");
cbc8eb67 8104 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
f8f97b0c 8105 if (!rval)
eaac30be
AV		 8106 return rval;
8107
cbc8eb67
AV		 8108try_blob_fw:
8109 rval = qla24xx_load_risc_blob(vha, srisc_addr);
f8f97b0c 8110 if (!rval || !ha->flt_region_gold_fw)
cbc8eb67
AV		 8111 return rval;
8112
7c3df132
SK		 8113 ql_log(ql_log_info, vha, 0x0099,
8114 "Attempting to fallback to golden firmware.\n");
cbc8eb67 8115 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
f8f97b0c 8116 if (rval)
cbc8eb67
AV		 8117 return rval;
8118
f8f97b0c 8119 ql_log(ql_log_info, vha, 0x009a, "Need firmware flash update.\n");
cbc8eb67 8120 ha->flags.running_gold_fw = 1;
cbc8eb67 8121 return rval;
eaac30be
AV		 8122}
8123
18c6c127 8124void
e315cd28 8125qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 8126{
8127 int ret, retries;
e315cd28 8128 struct qla_hw_data *ha = vha->hw;
18c6c127 8129
85880801
AV		 8130 if (ha->flags.pci_channel_io_perm_failure)
8131 return;
e428924c 8132 if (!IS_FWI2_CAPABLE(ha))
18c6c127 8133 return;
75edf81d
AV		 8134 if (!ha->fw_major_version)
8135 return;
ec7193e2
QT		 8136 if (!ha->flags.fw_started)
8137 return;
18c6c127 8138
e315cd28 8139 ret = qla2x00_stop_firmware(vha);
7c7f1f29 8140 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 8141 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 8142 ha->isp_ops->reset_chip(vha);
8143 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 8144 continue;
e315cd28 8145 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 8146 continue;
7c3df132
SK		 8147 ql_log(ql_log_info, vha, 0x8015,
8148 "Attempting retry of stop-firmware command.\n");
e315cd28 8149 ret = qla2x00_stop_firmware(vha);
18c6c127 8150 }
ec7193e2 8151
4b60c827 8152 QLA_FW_STOPPED(ha);
ec7193e2 8153 ha->flags.fw_init_done = 0;
18c6c127 8154}
2c3dfe3f
SJ		 8155
8156int
e315cd28 8157qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 8158{
8159 int rval = QLA_SUCCESS;
0b91d116 8160 int rval2;
2c3dfe3f 8161 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 8162 struct qla_hw_data *ha = vha->hw;
8163 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 8164
e315cd28 8165 if (!vha->vp_idx)
2c3dfe3f
SJ		 8166 return -EINVAL;
8167
e315cd28 8168 rval = qla2x00_fw_ready(base_vha);
67c2e93a 8169
2c3dfe3f 8170 if (rval == QLA_SUCCESS) {
e315cd28 8171 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
9eb9c6dc 8172 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 8173 }
8174
e315cd28 8175 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 8176
8177 /* Login to SNS first */
0b91d116
CD		 8178 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
8179 BIT_1);
8180 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
8181 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
8182 ql_dbg(ql_dbg_init, vha, 0x0120,
8183 "Failed SNS login: loop_id=%x, rval2=%d\n",
8184 NPH_SNS, rval2);
8185 else
8186 ql_dbg(ql_dbg_init, vha, 0x0103,
8187 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
8188 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
8189 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 8190 return (QLA_FUNCTION_FAILED);
8191 }
8192
e315cd28
AC		 8193 atomic_set(&vha->loop_down_timer, 0);
8194 atomic_set(&vha->loop_state, LOOP_UP);
8195 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
8196 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
8197 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 8198
8199 return rval;
8200}
4d4df193
HK		 8201
8202/* 84XX Support **************************************************************/
8203
8204static LIST_HEAD(qla_cs84xx_list);
8205static DEFINE_MUTEX(qla_cs84xx_mutex);
8206
8207static struct qla_chip_state_84xx *
e315cd28 8208qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 8209{
8210 struct qla_chip_state_84xx *cs84xx;
e315cd28 8211 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 8212
8213 mutex_lock(&qla_cs84xx_mutex);
8214
8215 /* Find any shared 84xx chip. */
8216 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
8217 if (cs84xx->bus == ha->pdev->bus) {
8218 kref_get(&cs84xx->kref);
8219 goto done;
8220 }
8221 }
8222
8223 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
8224 if (!cs84xx)
8225 goto done;
8226
8227 kref_init(&cs84xx->kref);
8228 spin_lock_init(&cs84xx->access_lock);
8229 mutex_init(&cs84xx->fw_update_mutex);
8230 cs84xx->bus = ha->pdev->bus;
8231
8232 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
8233done:
8234 mutex_unlock(&qla_cs84xx_mutex);
8235 return cs84xx;
8236}
8237
8238static void
8239__qla84xx_chip_release(struct kref *kref)
8240{
8241 struct qla_chip_state_84xx *cs84xx =
8242 container_of(kref, struct qla_chip_state_84xx, kref);
8243
8244 mutex_lock(&qla_cs84xx_mutex);
8245 list_del(&cs84xx->list);
8246 mutex_unlock(&qla_cs84xx_mutex);
8247 kfree(cs84xx);
8248}
8249
8250void
e315cd28 8251qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 8252{
e315cd28 8253 struct qla_hw_data *ha = vha->hw;
bd432bb5 8254
4d4df193
HK		 8255 if (ha->cs84xx)
8256 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
8257}
8258
8259static int
e315cd28 8260qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 8261{
8262 int rval;
8263 uint16_t status[2];
e315cd28 8264 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 8265
8266 mutex_lock(&ha->cs84xx->fw_update_mutex);
8267
e315cd28 8268 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 8269
8270 mutex_unlock(&ha->cs84xx->fw_update_mutex);
8271
58e2753c 8272 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED :
4d4df193
HK		 8273 QLA_SUCCESS;
8274}
3a03eb79
AV		 8275
8276/* 81XX Support **************************************************************/
8277
8278int
8279qla81xx_nvram_config(scsi_qla_host_t *vha)
8280{
8281 int rval;
8282 struct init_cb_81xx *icb;
8283 struct nvram_81xx *nv;
8284 uint32_t *dptr;
8285 uint8_t *dptr1, *dptr2;
8286 uint32_t chksum;
8287 uint16_t cnt;
8288 struct qla_hw_data *ha = vha->hw;
5fa8774c
JC		 8289 uint32_t faddr;
8290 struct active_regions active_regions = { };
3a03eb79
AV		 8291
8292 rval = QLA_SUCCESS;
8293 icb = (struct init_cb_81xx *)ha->init_cb;
8294 nv = ha->nvram;
8295
8296 /* Determine NVRAM starting address. */
f8f97b0c 8297 ha->nvram_size = sizeof(*nv);
3a03eb79 8298 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 8299 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
8300 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79 8301
3f006ac3 8302 if (IS_QLA28XX(ha) || IS_QLA27XX(ha))
5fa8774c
JC		 8303 qla28xx_get_aux_images(vha, &active_regions);
8304
3a03eb79
AV		 8305 /* Get VPD data into cache */
8306 ha->vpd = ha->nvram + VPD_OFFSET;
5fa8774c
JC		 8307
8308 faddr = ha->flt_region_vpd;
8309 if (IS_QLA28XX(ha)) {
8310 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE)
8311 faddr = ha->flt_region_vpd_sec;
8312 ql_dbg(ql_dbg_init, vha, 0x0110,
8313 "Loading %s nvram image.\n",
8314 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ?
8315 "primary" : "secondary");
8316 }
8317 qla24xx_read_flash_data(vha, ha->vpd, faddr, ha->vpd_size >> 2);
3a03eb79
AV		 8318
8319 /* Get NVRAM data into cache and calculate checksum. */
5fa8774c
JC		 8320 faddr = ha->flt_region_nvram;
8321 if (IS_QLA28XX(ha)) {
8322 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE)
8323 faddr = ha->flt_region_nvram_sec;
8324 }
8325 ql_dbg(ql_dbg_init, vha, 0x0110,
8326 "Loading %s nvram image.\n",
8327 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ?
8328 "primary" : "secondary");
8329 qla24xx_read_flash_data(vha, ha->nvram, faddr, ha->nvram_size >> 2);
8330
3d79038f 8331 dptr = (uint32_t *)nv;
da08ef5c
JC		 8332 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
8333 chksum += le32_to_cpu(*dptr);
3a03eb79 8334
7c3df132
SK		 8335 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
8336 "Contents of NVRAM:\n");
8337 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
f8f97b0c 8338 nv, ha->nvram_size);
3a03eb79
AV		 8339
8340 /* Bad NVRAM data, set defaults parameters. */
a28d9e4e
JC		 8341 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
8342 le16_to_cpu(nv->nvram_version) < ICB_VERSION) {
3a03eb79 8343 /* Reset NVRAM data. */
7c3df132 8344 ql_log(ql_log_info, vha, 0x0073,
3695310e
JC		 8345 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n",
8346 chksum, nv->id, le16_to_cpu(nv->nvram_version));
8347 ql_dump_buffer(ql_dbg_init, vha, 0x0073, nv, sizeof(*nv));
7c3df132
SK		 8348 ql_log(ql_log_info, vha, 0x0074,
8349 "Falling back to functioning (yet invalid -- WWPN) "
8350 "defaults.\n");
3a03eb79
AV		 8351
8352 /*
8353 * Set default initialization control block.
8354 */
8355 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 8356 nv->nvram_version = cpu_to_le16(ICB_VERSION);
8357 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 8358 nv->frame_payload_size = 2048;
ad950360
BVA		 8359 nv->execution_throttle = cpu_to_le16(0xFFFF);
8360 nv->exchange_count = cpu_to_le16(0);
3a03eb79 8361 nv->port_name[0] = 0x21;
f73cb695 8362 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 8363 nv->port_name[2] = 0x00;
8364 nv->port_name[3] = 0xe0;
8365 nv->port_name[4] = 0x8b;
8366 nv->port_name[5] = 0x1c;
8367 nv->port_name[6] = 0x55;
8368 nv->port_name[7] = 0x86;
8369 nv->node_name[0] = 0x20;
8370 nv->node_name[1] = 0x00;
8371 nv->node_name[2] = 0x00;
8372 nv->node_name[3] = 0xe0;
8373 nv->node_name[4] = 0x8b;
8374 nv->node_name[5] = 0x1c;
8375 nv->node_name[6] = 0x55;
8376 nv->node_name[7] = 0x86;
ad950360
BVA		 8377 nv->login_retry_count = cpu_to_le16(8);
8378 nv->interrupt_delay_timer = cpu_to_le16(0);
8379 nv->login_timeout = cpu_to_le16(0);
3a03eb79 8380 nv->firmware_options_1 =
ad950360
BVA		 8381 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
8382 nv->firmware_options_2 = cpu_to_le32(2 << 4);
8383 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
8384 nv->firmware_options_3 = cpu_to_le32(2 << 13);
8385 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
8386 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 8387 nv->reset_delay = 5;
ad950360
BVA		 8388 nv->max_luns_per_target = cpu_to_le16(128);
8389 nv->port_down_retry_count = cpu_to_le16(30);
8390 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 8391 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 8392 nv->enode_mac[1] = 0xC0;
8393 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 8394 nv->enode_mac[3] = 0x04;
8395 nv->enode_mac[4] = 0x05;
f73cb695 8396 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 8397
8398 rval = 1;
8399 }
8400
9e522cd8
AE		 8401 if (IS_T10_PI_CAPABLE(ha))
8402 nv->frame_payload_size &= ~7;
8403
aa230bc5
AE		 8404 qlt_81xx_config_nvram_stage1(vha, nv);
8405
3a03eb79 8406 /* Reset Initialization control block */
773120e4 8407 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 8408
8409 /* Copy 1st segment. */
8410 dptr1 = (uint8_t *)icb;
8411 dptr2 = (uint8_t *)&nv->version;
8412 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
8413 while (cnt--)
8414 *dptr1++ = *dptr2++;
8415
8416 icb->login_retry_count = nv->login_retry_count;
8417
8418 /* Copy 2nd segment. */
8419 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
8420 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
8421 cnt = (uint8_t *)&icb->reserved_5 -
8422 (uint8_t *)&icb->interrupt_delay_timer;
8423 while (cnt--)
8424 *dptr1++ = *dptr2++;
8425
8426 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
8427 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
8428 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 8429 icb->enode_mac[0] = 0x00;
8430 icb->enode_mac[1] = 0xC0;
8431 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 8432 icb->enode_mac[3] = 0x04;
8433 icb->enode_mac[4] = 0x05;
f73cb695 8434 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 8435 }
8436
b64b0e8f
AV		 8437 /* Use extended-initialization control block. */
8438 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
0eaaca4c 8439 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
3a03eb79
AV		 8440 /*
8441 * Setup driver NVRAM options.
8442 */
8443 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 8444 "QLE8XXX");
3a03eb79 8445
aa230bc5
AE		 8446 qlt_81xx_config_nvram_stage2(vha, icb);
8447
3a03eb79 8448 /* Use alternate WWN? */
ad950360 8449 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 8450 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
8451 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
8452 }
8453
8454 /* Prepare nodename */
ad950360 8455 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 8456 /*
8457 * Firmware will apply the following mask if the nodename was
8458 * not provided.
8459 */
8460 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
8461 icb->node_name[0] &= 0xF0;
8462 }
8463
8464 /* Set host adapter parameters. */
8465 ha->flags.disable_risc_code_load = 0;
8466 ha->flags.enable_lip_reset = 0;
8467 ha->flags.enable_lip_full_login =
58e2753c 8468 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0;
3a03eb79 8469 ha->flags.enable_target_reset =
58e2753c 8470 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0;
3a03eb79 8471 ha->flags.enable_led_scheme = 0;
58e2753c 8472 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0;
3a03eb79
AV		 8473
8474 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
8475 (BIT_6 | BIT_5 | BIT_4)) >> 4;
8476
8477 /* save HBA serial number */
8478 ha->serial0 = icb->port_name[5];
8479 ha->serial1 = icb->port_name[6];
8480 ha->serial2 = icb->port_name[7];
8481 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
8482 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
8483
ad950360 8484 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 8485
8486 ha->retry_count = le16_to_cpu(nv->login_retry_count);
8487
8488 /* Set minimum login_timeout to 4 seconds. */
8489 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
8490 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
8491 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 8492 nv->login_timeout = cpu_to_le16(4);
3a03eb79 8493 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 8494
8495 /* Set minimum RATOV to 100 tenths of a second. */
8496 ha->r_a_tov = 100;
8497
8498 ha->loop_reset_delay = nv->reset_delay;
8499
8500 /* Link Down Timeout = 0:
8501 *
7ec0effd 8502 * When Port Down timer expires we will start returning
3a03eb79
AV		 8503 * I/O's to OS with "DID_NO_CONNECT".
8504 *
8505 * Link Down Timeout != 0:
8506 *
8507 * The driver waits for the link to come up after link down
8508 * before returning I/Os to OS with "DID_NO_CONNECT".
8509 */
8510 if (le16_to_cpu(nv->link_down_timeout) == 0) {
8511 ha->loop_down_abort_time =
8512 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
8513 } else {
8514 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
8515 ha->loop_down_abort_time =
8516 (LOOP_DOWN_TIME - ha->link_down_timeout);
8517 }
8518
8519 /* Need enough time to try and get the port back. */
8520 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
8521 if (qlport_down_retry)
8522 ha->port_down_retry_count = qlport_down_retry;
8523
8524 /* Set login_retry_count */
8525 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
8526 if (ha->port_down_retry_count ==
8527 le16_to_cpu(nv->port_down_retry_count) &&
8528 ha->port_down_retry_count > 3)
8529 ha->login_retry_count = ha->port_down_retry_count;
8530 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
8531 ha->login_retry_count = ha->port_down_retry_count;
8532 if (ql2xloginretrycount)
8533 ha->login_retry_count = ql2xloginretrycount;
8534
6246b8a1 8535 /* if not running MSI-X we need handshaking on interrupts */
ecc89f25
JC		 8536 if (!vha->hw->flags.msix_enabled &&
8537 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)))
ad950360 8538 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 8539
3a03eb79
AV		 8540 /* Enable ZIO. */
8541 if (!vha->flags.init_done) {
8542 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
8543 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
8544 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
58e2753c 8545 le16_to_cpu(icb->interrupt_delay_timer) : 2;
3a03eb79 8546 }
ad950360 8547 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 8548 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
8549 vha->flags.process_response_queue = 0;
8550 if (ha->zio_mode != QLA_ZIO_DISABLED) {
8551 ha->zio_mode = QLA_ZIO_MODE_6;
8552
7c3df132 8553 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 8554 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 8555 ha->zio_mode,
8556 ha->zio_timer * 100);
3a03eb79
AV		 8557
8558 icb->firmware_options_2 |= cpu_to_le32(
8559 (uint32_t)ha->zio_mode);
8560 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
8561 vha->flags.process_response_queue = 1;
8562 }
8563
41dc529a 8564 /* enable RIDA Format2 */
48acad09 8565 icb->firmware_options_3 |= BIT_0;
41dc529a 8566
8777e431
QT		 8567 /* N2N: driver will initiate Login instead of FW */
8568 icb->firmware_options_3 |= BIT_8;
41dc529a 8569
3a03eb79 8570 if (rval) {
7c3df132
SK		 8571 ql_log(ql_log_warn, vha, 0x0076,
8572 "NVRAM configuration failed.\n");
3a03eb79
AV		 8573 }
8574 return (rval);
8575}
8576
a9083016
GM		 8577int
8578qla82xx_restart_isp(scsi_qla_host_t *vha)
8579{
8580 int status, rval;
a9083016 8581 struct qla_hw_data *ha = vha->hw;
a9083016 8582 struct scsi_qla_host *vp;
feafb7b1 8583 unsigned long flags;
a9083016
GM		 8584
8585 status = qla2x00_init_rings(vha);
8586 if (!status) {
8587 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8588 ha->flags.chip_reset_done = 1;
8589
8590 status = qla2x00_fw_ready(vha);
8591 if (!status) {
a9083016 8592 /* Issue a marker after FW becomes ready. */
9eb9c6dc 8593 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
a9083016 8594 vha->flags.online = 1;
7108b76e 8595 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 8596 }
8597
8598 /* if no cable then assume it's good */
8599 if ((vha->device_flags & DFLG_NO_CABLE))
8600 status = 0;
a9083016
GM		 8601 }
8602
8603 if (!status) {
8604 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8605
8606 if (!atomic_read(&vha->loop_down_timer)) {
8607 /*
8608 * Issue marker command only when we are going
8609 * to start the I/O .
8610 */
8611 vha->marker_needed = 1;
8612 }
8613
a9083016
GM		 8614 ha->isp_ops->enable_intrs(ha);
8615
8616 ha->isp_abort_cnt = 0;
8617 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
8618
53296788 8619 /* Update the firmware version */
3173167f 8620 status = qla82xx_check_md_needed(vha);
53296788 8621
a9083016
GM		 8622 if (ha->fce) {
8623 ha->flags.fce_enabled = 1;
8624 memset(ha->fce, 0,
8625 fce_calc_size(ha->fce_bufs));
8626 rval = qla2x00_enable_fce_trace(vha,
8627 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
8628 &ha->fce_bufs);
8629 if (rval) {
cfb0919c 8630 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 8631 "Unable to reinitialize FCE (%d).\n",
8632 rval);
a9083016
GM		 8633 ha->flags.fce_enabled = 0;
8634 }
8635 }
8636
8637 if (ha->eft) {
8638 memset(ha->eft, 0, EFT_SIZE);
8639 rval = qla2x00_enable_eft_trace(vha,
8640 ha->eft_dma, EFT_NUM_BUFFERS);
8641 if (rval) {
cfb0919c 8642 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 8643 "Unable to reinitialize EFT (%d).\n",
8644 rval);
a9083016
GM		 8645 }
8646 }
a9083016
GM		 8647 }
8648
8649 if (!status) {
cfb0919c 8650 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 8651 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 8652
8653 spin_lock_irqsave(&ha->vport_slock, flags);
8654 list_for_each_entry(vp, &ha->vp_list, list) {
8655 if (vp->vp_idx) {
8656 atomic_inc(&vp->vref_count);
8657 spin_unlock_irqrestore(&ha->vport_slock, flags);
8658
a9083016 8659 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 8660
8661 spin_lock_irqsave(&ha->vport_slock, flags);
8662 atomic_dec(&vp->vref_count);
8663 }
a9083016 8664 }
feafb7b1
AE		 8665 spin_unlock_irqrestore(&ha->vport_slock, flags);
8666
a9083016 8667 } else {
cfb0919c 8668 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 8669 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 8670 }
8671
8672 return status;
8673}
8674
3a03eb79 8675void
ae97c91e 8676qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 8677{
ae97c91e
AV		 8678 struct qla_hw_data *ha = vha->hw;
8679
f198cafa
HM		 8680 /* Hold status IOCBs until ABTS response received. */
8681 if (ql2xfwholdabts)
8682 ha->fw_options[3] |= BIT_12;
8683
088d09d4
GM		 8684 /* Set Retry FLOGI in case of P2P connection */
8685 if (ha->operating_mode == P2P) {
8686 ha->fw_options[2] |= BIT_3;
8687 ql_dbg(ql_dbg_disc, vha, 0x2103,
8688 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
8689 __func__, ha->fw_options[2]);
8690 }
8691
41dc529a
QT		 8692 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
8693 if (ql2xmvasynctoatio) {
8694 if (qla_tgt_mode_enabled(vha) ||
8695 qla_dual_mode_enabled(vha))
8696 ha->fw_options[2] |= BIT_11;
8697 else
8698 ha->fw_options[2] &= ~BIT_11;
8699 }
8700
f7e761f5 8701 if (qla_tgt_mode_enabled(vha) ||
2da52737
QT		 8702 qla_dual_mode_enabled(vha)) {
8703 /* FW auto send SCSI status during */
8704 ha->fw_options[1] |= BIT_8;
8705 ha->fw_options[10] |= (u16)SAM_STAT_BUSY << 8;
8706
8707 /* FW perform Exchange validation */
f7e761f5 8708 ha->fw_options[2] |= BIT_4;
2da52737
QT		 8709 } else {
8710 ha->fw_options[1] &= ~BIT_8;
8711 ha->fw_options[10] &= 0x00ff;
8712
f7e761f5 8713 ha->fw_options[2] &= ~BIT_4;
2da52737 8714 }
f7e761f5 8715
41dc529a
QT		 8716 if (ql2xetsenable) {
8717 /* Enable ETS Burst. */
8718 memset(ha->fw_options, 0, sizeof(ha->fw_options));
8719 ha->fw_options[2] |= BIT_9;
8720 }
8721
83548fe2
QT		 8722 ql_dbg(ql_dbg_init, vha, 0x00e9,
8723 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
8724 __func__, ha->fw_options[1], ha->fw_options[2],
8725 ha->fw_options[3], vha->host->active_mode);
ae97c91e 8726
ae97c91e 8727 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 8728}
09ff701a
SR		 8729
8730/*
8731 * qla24xx_get_fcp_prio
8732 * Gets the fcp cmd priority value for the logged in port.
8733 * Looks for a match of the port descriptors within
8734 * each of the fcp prio config entries. If a match is found,
8735 * the tag (priority) value is returned.
8736 *
8737 * Input:
21090cbe 8738 * vha = scsi host structure pointer.
09ff701a
SR		 8739 * fcport = port structure pointer.
8740 *
8741 * Return:
6c452a45 8742 * non-zero (if found)
f28a0a96 8743 * -1 (if not found)
09ff701a
SR		 8744 *
8745 * Context:
8746 * Kernel context
8747 */
f28a0a96 8748static int
09ff701a
SR		 8749qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
8750{
8751 int i, entries;
8752 uint8_t pid_match, wwn_match;
f28a0a96 8753 int priority;
09ff701a
SR		 8754 uint32_t pid1, pid2;
8755 uint64_t wwn1, wwn2;
8756 struct qla_fcp_prio_entry *pri_entry;
8757 struct qla_hw_data *ha = vha->hw;
8758
8759 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 8760 return -1;
09ff701a 8761
f28a0a96 8762 priority = -1;
09ff701a
SR		 8763 entries = ha->fcp_prio_cfg->num_entries;
8764 pri_entry = &ha->fcp_prio_cfg->entry[0];
8765
8766 for (i = 0; i < entries; i++) {
8767 pid_match = wwn_match = 0;
8768
8769 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
8770 pri_entry++;
8771 continue;
8772 }
8773
8774 /* check source pid for a match */
8775 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
8776 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
8777 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
8778 if (pid1 == INVALID_PORT_ID)
8779 pid_match++;
8780 else if (pid1 == pid2)
8781 pid_match++;
8782 }
8783
8784 /* check destination pid for a match */
8785 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
8786 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
8787 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
8788 if (pid1 == INVALID_PORT_ID)
8789 pid_match++;
8790 else if (pid1 == pid2)
8791 pid_match++;
8792 }
8793
8794 /* check source WWN for a match */
8795 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
8796 wwn1 = wwn_to_u64(vha->port_name);
8797 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
8798 if (wwn2 == (uint64_t)-1)
8799 wwn_match++;
8800 else if (wwn1 == wwn2)
8801 wwn_match++;
8802 }
8803
8804 /* check destination WWN for a match */
8805 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
8806 wwn1 = wwn_to_u64(fcport->port_name);
8807 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
8808 if (wwn2 == (uint64_t)-1)
8809 wwn_match++;
8810 else if (wwn1 == wwn2)
8811 wwn_match++;
8812 }
8813
8814 if (pid_match == 2 || wwn_match == 2) {
8815 /* Found a matching entry */
8816 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
8817 priority = pri_entry->tag;
8818 break;
8819 }
8820
8821 pri_entry++;
8822 }
8823
8824 return priority;
8825}
8826
8827/*
8828 * qla24xx_update_fcport_fcp_prio
8829 * Activates fcp priority for the logged in fc port
8830 *
8831 * Input:
21090cbe 8832 * vha = scsi host structure pointer.
09ff701a
SR		 8833 * fcp = port structure pointer.
8834 *
8835 * Return:
8836 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8837 *
8838 * Context:
8839 * Kernel context.
8840 */
8841int
21090cbe 8842qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 8843{
8844 int ret;
f28a0a96 8845 int priority;
09ff701a
SR		 8846 uint16_t mb[5];
8847
21090cbe
MI		 8848 if (fcport->port_type != FCT_TARGET ||
8849 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 8850 return QLA_FUNCTION_FAILED;
8851
21090cbe 8852 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 8853 if (priority < 0)
8854 return QLA_FUNCTION_FAILED;
8855
7ec0effd 8856 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 8857 fcport->fcp_prio = priority & 0xf;
8858 return QLA_SUCCESS;
8859 }
8860
21090cbe 8861 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 8862 if (ret == QLA_SUCCESS) {
8863 if (fcport->fcp_prio != priority)
8864 ql_dbg(ql_dbg_user, vha, 0x709e,
8865 "Updated FCP_CMND priority - value=%d loop_id=%d "
8866 "port_id=%02x%02x%02x.\n", priority,
8867 fcport->loop_id, fcport->d_id.b.domain,
8868 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 8869 fcport->fcp_prio = priority & 0xf;
cfb0919c 8870 } else
7c3df132 8871 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 8872 "Unable to update FCP_CMND priority - ret=0x%x for "
8873 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
8874 fcport->d_id.b.domain, fcport->d_id.b.area,
8875 fcport->d_id.b.al_pa);
09ff701a
SR		 8876 return ret;
8877}
8878
8879/*
8880 * qla24xx_update_all_fcp_prio
8881 * Activates fcp priority for all the logged in ports
8882 *
8883 * Input:
8884 * ha = adapter block pointer.
8885 *
8886 * Return:
8887 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8888 *
8889 * Context:
8890 * Kernel context.
8891 */
8892int
8893qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
8894{
8895 int ret;
8896 fc_port_t *fcport;
8897
8898 ret = QLA_FUNCTION_FAILED;
8899 /* We need to set priority for all logged in ports */
8900 list_for_each_entry(fcport, &vha->vp_fcports, list)
8901 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
8902
8903 return ret;
8904}
d7459527 8905
82de802a
QT		 8906struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos,
8907 int vp_idx, bool startqp)
d7459527
MH		 8908{
8909 int rsp_id = 0;
8910 int req_id = 0;
8911 int i;
8912 struct qla_hw_data *ha = vha->hw;
8913 uint16_t qpair_id = 0;
8914 struct qla_qpair *qpair = NULL;
8915 struct qla_msix_entry *msix;
8916
8917 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
8918 ql_log(ql_log_warn, vha, 0x00181,
8919 "FW/Driver is not multi-queue capable.\n");
8920 return NULL;
8921 }
8922
c38d1baf 8923 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 8924 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
8925 if (qpair == NULL) {
8926 ql_log(ql_log_warn, vha, 0x0182,
8927 "Failed to allocate memory for queue pair.\n");
8928 return NULL;
8929 }
d7459527
MH		 8930
8931 qpair->hw = vha->hw;
25ff6af1 8932 qpair->vha = vha;
82de802a
QT		 8933 qpair->qp_lock_ptr = &qpair->qp_lock;
8934 spin_lock_init(&qpair->qp_lock);
af7bb382 8935 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
d7459527
MH		 8936
8937 /* Assign available que pair id */
8938 mutex_lock(&ha->mq_lock);
8939 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
b95b9452 8940 if (ha->num_qpairs >= ha->max_qpairs) {
d7459527
MH		 8941 mutex_unlock(&ha->mq_lock);
8942 ql_log(ql_log_warn, vha, 0x0183,
8943 "No resources to create additional q pair.\n");
8944 goto fail_qid_map;
8945 }
b95b9452 8946 ha->num_qpairs++;
d7459527
MH		 8947 set_bit(qpair_id, ha->qpair_qid_map);
8948 ha->queue_pair_map[qpair_id] = qpair;
8949 qpair->id = qpair_id;
8950 qpair->vp_idx = vp_idx;
e6373f33 8951 qpair->fw_started = ha->flags.fw_started;
e326d22a 8952 INIT_LIST_HEAD(&qpair->hints_list);
7c3f8fd1
QT		 8953 qpair->chip_reset = ha->base_qpair->chip_reset;
8954 qpair->enable_class_2 = ha->base_qpair->enable_class_2;
8955 qpair->enable_explicit_conf =
8956 ha->base_qpair->enable_explicit_conf;
d7459527
MH		 8957
8958 for (i = 0; i < ha->msix_count; i++) {
093df737 8959 msix = &ha->msix_entries[i];
d7459527
MH		 8960 if (msix->in_use)
8961 continue;
8962 qpair->msix = msix;
83548fe2 8963 ql_dbg(ql_dbg_multiq, vha, 0xc00f,
d7459527
MH		 8964 "Vector %x selected for qpair\n", msix->vector);
8965 break;
8966 }
8967 if (!qpair->msix) {
8968 ql_log(ql_log_warn, vha, 0x0184,
8969 "Out of MSI-X vectors!.\n");
8970 goto fail_msix;
8971 }
8972
8973 qpair->msix->in_use = 1;
8974 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
8abfa9e2 8975 qpair->pdev = ha->pdev;
ecc89f25 8976 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
8abfa9e2 8977 qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
d7459527
MH		 8978
8979 mutex_unlock(&ha->mq_lock);
8980
8981 /* Create response queue first */
82de802a 8982 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp);
d7459527
MH		 8983 if (!rsp_id) {
8984 ql_log(ql_log_warn, vha, 0x0185,
8985 "Failed to create response queue.\n");
8986 goto fail_rsp;
8987 }
8988
8989 qpair->rsp = ha->rsp_q_map[rsp_id];
8990
8991 /* Create request queue */
82de802a
QT		 8992 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos,
8993 startqp);
d7459527
MH		 8994 if (!req_id) {
8995 ql_log(ql_log_warn, vha, 0x0186,
8996 "Failed to create request queue.\n");
8997 goto fail_req;
8998 }
8999
9000 qpair->req = ha->req_q_map[req_id];
9001 qpair->rsp->req = qpair->req;
82de802a 9002 qpair->rsp->qpair = qpair;
e326d22a
QT		 9003 /* init qpair to this cpu. Will adjust at run time. */
9004 qla_cpu_update(qpair, smp_processor_id());
d7459527
MH		 9005
9006 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
9007 if (ha->fw_attributes & BIT_4)
9008 qpair->difdix_supported = 1;
9009 }
9010
9011 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
9012 if (!qpair->srb_mempool) {
83548fe2 9013 ql_log(ql_log_warn, vha, 0xd036,
d7459527
MH		 9014 "Failed to create srb mempool for qpair %d\n",
9015 qpair->id);
9016 goto fail_mempool;
9017 }
9018
9019 /* Mark as online */
9020 qpair->online = 1;
9021
9022 if (!vha->flags.qpairs_available)
9023 vha->flags.qpairs_available = 1;
9024
9025 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
9026 "Request/Response queue pair created, id %d\n",
9027 qpair->id);
9028 ql_dbg(ql_dbg_init, vha, 0x0187,
9029 "Request/Response queue pair created, id %d\n",
9030 qpair->id);
9031 }
9032 return qpair;
9033
9034fail_mempool:
9035fail_req:
9036 qla25xx_delete_rsp_que(vha, qpair->rsp);
9037fail_rsp:
9038 mutex_lock(&ha->mq_lock);
9039 qpair->msix->in_use = 0;
9040 list_del(&qpair->qp_list_elem);
9041 if (list_empty(&vha->qp_list))
9042 vha->flags.qpairs_available = 0;
9043fail_msix:
9044 ha->queue_pair_map[qpair_id] = NULL;
9045 clear_bit(qpair_id, ha->qpair_qid_map);
b95b9452 9046 ha->num_qpairs--;
d7459527
MH		 9047 mutex_unlock(&ha->mq_lock);
9048fail_qid_map:
9049 kfree(qpair);
9050 return NULL;
9051}
9052
9053int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
9054{
d65237c7 9055 int ret = QLA_FUNCTION_FAILED;
d7459527
MH		 9056 struct qla_hw_data *ha = qpair->hw;
9057
9058 qpair->delete_in_progress = 1;
9059 while (atomic_read(&qpair->ref_count))
9060 msleep(500);
9061
9062 ret = qla25xx_delete_req_que(vha, qpair->req);
9063 if (ret != QLA_SUCCESS)
9064 goto fail;
7867b98d 9065
d7459527
MH		 9066 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
9067 if (ret != QLA_SUCCESS)
9068 goto fail;
9069
9070 mutex_lock(&ha->mq_lock);
9071 ha->queue_pair_map[qpair->id] = NULL;
9072 clear_bit(qpair->id, ha->qpair_qid_map);
b95b9452 9073 ha->num_qpairs--;
d7459527 9074 list_del(&qpair->qp_list_elem);
d65237c7 9075 if (list_empty(&vha->qp_list)) {
d7459527 9076 vha->flags.qpairs_available = 0;
d65237c7
SC		 9077 vha->flags.qpairs_req_created = 0;
9078 vha->flags.qpairs_rsp_created = 0;
9079 }
d7459527
MH		 9080 mempool_destroy(qpair->srb_mempool);
9081 kfree(qpair);
9082 mutex_unlock(&ha->mq_lock);
9083
9084 return QLA_SUCCESS;
9085fail:
9086 return ret;
9087}
Linux 6.x block layer and io_uring tree(s)