[linux-2.6-block.git] / arch / arm64 / boot / dts / broadcom / ns2.dtsi

/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/bcm-ns2.h>

/memreserve/ 0x84b00000 0x00000008;

/ {
	compatible = "brcm,ns2";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		A57_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 0>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0x84b00000>;
			next-level-cache = <&CLUSTER0_L2>;
		};

		A57_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 1>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0x84b00000>;
			next-level-cache = <&CLUSTER0_L2>;
		};

		A57_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 2>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0x84b00000>;
			next-level-cache = <&CLUSTER0_L2>;
		};

		A57_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 3>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0x84b00000>;
			next-level-cache = <&CLUSTER0_L2>;
		};

		CLUSTER0_L2: l2-cache@000 {
			compatible = "cache";
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_EDGE_RISING)>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A57_0>,
				     <&A57_1>,
				     <&A57_2>,
				     <&A57_3>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;

		osc: oscillator {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
		};

		iprocmed: iprocmed {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
			clock-div = <2>;
			clock-mult = <1>;
		};

		iprocslow: iprocslow {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
			clock-div = <4>;
			clock-mult = <1>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;

		smmu: mmu@64000000 {
			compatible = "arm,mmu-500";
			reg = <0x64000000 0x40000>;
			#global-interrupts = <2>;
			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
			mmu-masters;
		};

		lcpll_ddr: lcpll_ddr@6501d058 {
			#clock-cells = <1>;
			compatible = "brcm,ns2-lcpll-ddr";
			reg = <0x6501d058 0x20>,
			      <0x6501c020 0x4>,
			      <0x6501d04c 0x4>;
			clocks = <&osc>;
			clock-output-names = "lcpll_ddr", "pcie_sata_usb",
					     "ddr", "ddr_ch2_unused",
					     "ddr_ch3_unused", "ddr_ch4_unused",
					     "ddr_ch5_unused";
		};

		lcpll_ports: lcpll_ports@6501d078 {
			#clock-cells = <1>;
			compatible = "brcm,ns2-lcpll-ports";
			reg = <0x6501d078 0x20>,
			      <0x6501c020 0x4>,
			      <0x6501d054 0x4>;
			clocks = <&osc>;
			clock-output-names = "lcpll_ports", "wan", "rgmii",
					     "ports_ch2_unused",
					     "ports_ch3_unused",
					     "ports_ch4_unused",
					     "ports_ch5_unused";
		};

		genpll_scr: genpll_scr@6501d098 {
			#clock-cells = <1>;
			compatible = "brcm,ns2-genpll-scr";
			reg = <0x6501d098 0x32>,
			      <0x6501c020 0x4>,
			      <0x6501d044 0x4>;
			clocks = <&osc>;
			clock-output-names = "genpll_scr", "scr", "fs",
					     "audio_ref", "scr_ch3_unused",
					     "scr_ch4_unused", "scr_ch5_unused";
		};

		genpll_sw: genpll_sw@6501d0c4 {
			#clock-cells = <1>;
			compatible = "brcm,ns2-genpll-sw";
			reg = <0x6501d0c4 0x32>,
			      <0x6501c020 0x4>,
			      <0x6501d044 0x4>;
			clocks = <&osc>;
			clock-output-names = "genpll_sw", "rpe", "250", "nic",
					     "chimp", "port", "sdio";
		};

		crmu: crmu@65024000 {
			compatible = "syscon";
			reg = <0x65024000 0x100>;
		};

		reboot@65024000 {
			compatible ="syscon-reboot";
			regmap = <&crmu>;
			offset = <0x90>;
			mask = <0xfffffffd>;
		};

		gic: interrupt-controller@65210000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x65210000 0x1000>,
			      <0x65220000 0x1000>,
			      <0x65240000 0x2000>,
			      <0x65260000 0x1000>;
		};

		i2c0: i2c@66080000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x66080000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c1: i2c@660b0000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x660b0000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		uart3: serial@66130000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x66130000 0x100>;
			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			status = "disabled";
		};

		hwrng: hwrng@66220000 {
			compatible = "brcm,iproc-rng200";
			reg = <0x66220000 0x28>;
		};

		nand: nand@66460000 {
			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
			reg = <0x66460000 0x600>,
			      <0x67015408 0x600>,
			      <0x66460f00 0x20>;
			reg-names = "nand", "iproc-idm", "iproc-ext";
			interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;
			#size-cells = <0>;

			brcm,nand-has-wp;
		};
	};
};
Commit	Line	Data
6aad8bf9 RJ	1	/*
	2	* BSD LICENSE
	3	*
	4	* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in
	14	* the documentation and/or other materials provided with the
	15	* distribution.
	16	* * Neither the name of Broadcom Corporation nor the names of its
	17	* contributors may be used to endorse or promote products derived
	18	* from this software without specific prior written permission.
	19	*
	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	21	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	22	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	23	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	24	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	25	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	26	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	27	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	28	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	30	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*/
	32
	33	#include <dt-bindings/interrupt-controller/arm-gic.h>
d8bd64c1	34	#include <dt-bindings/clock/bcm-ns2.h>
6aad8bf9 RJ	35
	36	/memreserve/ 0x84b00000 0x00000008;
	37
	38	/ {
	39	compatible = "brcm,ns2";
	40	interrupt-parent = <&gic>;
	41	#address-cells = <2>;
	42	#size-cells = <2>;
	43
	44	cpus {
	45	#address-cells = <2>;
	46	#size-cells = <0>;
	47
5b31d875	48	A57_0: cpu@0 {
6aad8bf9 RJ	49	device_type = "cpu";
	50	compatible = "arm,cortex-a57", "arm,armv8";
	51	reg = <0 0>;
	52	enable-method = "spin-table";
	53	cpu-release-addr = <0 0x84b00000>;
33a93aa4	54	next-level-cache = <&CLUSTER0_L2>;
6aad8bf9 RJ	55	};
6aad8bf9 RJ	56
5b31d875	57	A57_1: cpu@1 {
6aad8bf9 RJ	58	device_type = "cpu";
	59	compatible = "arm,cortex-a57", "arm,armv8";
	60	reg = <0 1>;
	61	enable-method = "spin-table";
	62	cpu-release-addr = <0 0x84b00000>;
33a93aa4	63	next-level-cache = <&CLUSTER0_L2>;
6aad8bf9 RJ	64	};
6aad8bf9 RJ	65
5b31d875	66	A57_2: cpu@2 {
6aad8bf9 RJ	67	device_type = "cpu";
	68	compatible = "arm,cortex-a57", "arm,armv8";
	69	reg = <0 2>;
	70	enable-method = "spin-table";
	71	cpu-release-addr = <0 0x84b00000>;
33a93aa4	72	next-level-cache = <&CLUSTER0_L2>;
6aad8bf9 RJ	73	};
6aad8bf9 RJ	74
5b31d875	75	A57_3: cpu@3 {
6aad8bf9 RJ	76	device_type = "cpu";
	77	compatible = "arm,cortex-a57", "arm,armv8";
	78	reg = <0 3>;
	79	enable-method = "spin-table";
	80	cpu-release-addr = <0 0x84b00000>;
33a93aa4 AP	81	next-level-cache = <&CLUSTER0_L2>;
	82	};
	83
	84	CLUSTER0_L2: l2-cache@000 {
	85	compatible = "cache";
6aad8bf9 RJ	86	};
	87	};
	88
	89	timer {
	90	compatible = "arm,armv8-timer";
	91	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) \|
	92	IRQ_TYPE_EDGE_RISING)>,
	93	<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) \|
	94	IRQ_TYPE_EDGE_RISING)>,
	95	<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) \|
	96	IRQ_TYPE_EDGE_RISING)>,
	97	<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) \|
	98	IRQ_TYPE_EDGE_RISING)>;
	99	};
	100
5b31d875 AP	101	pmu {
	102	compatible = "arm,armv8-pmuv3";
	103	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	104	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
	105	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	106	<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
	107	interrupt-affinity = <&A57_0>,
	108	<&A57_1>,
	109	<&A57_2>,
	110	<&A57_3>;
	111	};
	112
d8bd64c1 JM	113	clocks {
	114	#address-cells = <1>;
	115	#size-cells = <1>;
	116
	117	osc: oscillator {
	118	#clock-cells = <0>;
	119	compatible = "fixed-clock";
	120	clock-frequency = <25000000>;
	121	};
	122
	123	iprocmed: iprocmed {
	124	#clock-cells = <0>;
	125	compatible = "fixed-factor-clock";
	126	clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
	127	clock-div = <2>;
	128	clock-mult = <1>;
	129	};
	130
	131	iprocslow: iprocslow {
	132	#clock-cells = <0>;
	133	compatible = "fixed-factor-clock";
	134	clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
	135	clock-div = <4>;
	136	clock-mult = <1>;
	137	};
	138	};
	139
6aad8bf9 RJ	140	soc: soc {
	141	compatible = "simple-bus";
	142	#address-cells = <1>;
	143	#size-cells = <1>;
	144	ranges = <0 0 0 0xffffffff>;
	145
6ec5f3c5 AP	146	smmu: mmu@64000000 {
	147	compatible = "arm,mmu-500";
	148	reg = <0x64000000 0x40000>;
	149	#global-interrupts = <2>;
	150	interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
	151	<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
	152	<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
	153	<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
	154	<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
	155	<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
	156	<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
	157	<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
	158	<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
	159	<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
	160	<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
	161	<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
	162	<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
	163	<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
	164	<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
	165	<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
	166	<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
	167	<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
	168	<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
	169	<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
	170	<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
	171	<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
	172	<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
	173	<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
	174	<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
	175	<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
	176	<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
	177	<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	178	<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
	179	<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
	180	<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
	181	<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
	182	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
	183	<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
	184	mmu-masters;
	185	};
	186
d8bd64c1 JM	187	lcpll_ddr: lcpll_ddr@6501d058 {
	188	#clock-cells = <1>;
	189	compatible = "brcm,ns2-lcpll-ddr";
	190	reg = <0x6501d058 0x20>,
	191	<0x6501c020 0x4>,
	192	<0x6501d04c 0x4>;
	193	clocks = <&osc>;
	194	clock-output-names = "lcpll_ddr", "pcie_sata_usb",
	195	"ddr", "ddr_ch2_unused",
	196	"ddr_ch3_unused", "ddr_ch4_unused",
	197	"ddr_ch5_unused";
	198	};
	199
	200	lcpll_ports: lcpll_ports@6501d078 {
	201	#clock-cells = <1>;
	202	compatible = "brcm,ns2-lcpll-ports";
	203	reg = <0x6501d078 0x20>,
	204	<0x6501c020 0x4>,
	205	<0x6501d054 0x4>;
	206	clocks = <&osc>;
	207	clock-output-names = "lcpll_ports", "wan", "rgmii",
	208	"ports_ch2_unused",
	209	"ports_ch3_unused",
	210	"ports_ch4_unused",
	211	"ports_ch5_unused";
	212	};
	213
	214	genpll_scr: genpll_scr@6501d098 {
	215	#clock-cells = <1>;
	216	compatible = "brcm,ns2-genpll-scr";
	217	reg = <0x6501d098 0x32>,
	218	<0x6501c020 0x4>,
	219	<0x6501d044 0x4>;
	220	clocks = <&osc>;
	221	clock-output-names = "genpll_scr", "scr", "fs",
	222	"audio_ref", "scr_ch3_unused",
	223	"scr_ch4_unused", "scr_ch5_unused";
	224	};
	225
	226	genpll_sw: genpll_sw@6501d0c4 {
	227	#clock-cells = <1>;
	228	compatible = "brcm,ns2-genpll-sw";
	229	reg = <0x6501d0c4 0x32>,
	230	<0x6501c020 0x4>,
	231	<0x6501d044 0x4>;
	232	clocks = <&osc>;
	233	clock-output-names = "genpll_sw", "rpe", "250", "nic",
	234	"chimp", "port", "sdio";
	235	};
	236
5b467c3b AP	237	crmu: crmu@65024000 {
	238	compatible = "syscon";
	239	reg = <0x65024000 0x100>;
	240	};
	241
	242	reboot@65024000 {
	243	compatible ="syscon-reboot";
	244	regmap = <&crmu>;
	245	offset = <0x90>;
	246	mask = <0xfffffffd>;
	247	};
	248
6aad8bf9 RJ	249	gic: interrupt-controller@65210000 {
	250	compatible = "arm,gic-400";
	251	#interrupt-cells = <3>;
	252	interrupt-controller;
	253	reg = <0x65210000 0x1000>,
	254	<0x65220000 0x1000>,
	255	<0x65240000 0x2000>,
	256	<0x65260000 0x1000>;
	257	};
	258
7ac674e8 RJ	259	i2c0: i2c@66080000 {
	260	compatible = "brcm,iproc-i2c";
	261	reg = <0x66080000 0x100>;
	262	#address-cells = <1>;
	263	#size-cells = <0>;
	264	interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
	265	clock-frequency = <100000>;
	266	status = "disabled";
	267	};
	268
	269	i2c1: i2c@660b0000 {
	270	compatible = "brcm,iproc-i2c";
	271	reg = <0x660b0000 0x100>;
	272	#address-cells = <1>;
	273	#size-cells = <0>;
	274	interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
	275	clock-frequency = <100000>;
	276	status = "disabled";
	277	};
	278
6aad8bf9 RJ	279	uart3: serial@66130000 {
	280	compatible = "snps,dw-apb-uart";
	281	reg = <0x66130000 0x100>;
	282	interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
	283	reg-shift = <2>;
	284	reg-io-width = <4>;
d8bd64c1	285	clocks = <&osc>;
6aad8bf9 RJ	286	status = "disabled";
6aad8bf9 RJ	287	};
e8a6e265 AP	288
	289	hwrng: hwrng@66220000 {
	290	compatible = "brcm,iproc-rng200";
	291	reg = <0x66220000 0x28>;
	292	};
c6fe9a2e AP	293
	294	nand: nand@66460000 {
	295	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
	296	reg = <0x66460000 0x600>,
	297	<0x67015408 0x600>,
	298	<0x66460f00 0x20>;
	299	reg-names = "nand", "iproc-idm", "iproc-ext";
	300	interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
	301
	302	#address-cells = <1>;
	303	#size-cells = <0>;
	304
	305	brcm,nand-has-wp;
	306	};
6aad8bf9 RJ	307	};
6aad8bf9 RJ	308	};