[linux-2.6-block.git] / arch / arm64 / boot / dts / broadcom / ns2.dtsi

/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/memreserve/ 0x84b00000 0x00000008;

/ {
	compatible = "brcm,ns2";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		A57_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 0>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0x84b00000>;
			next-level-cache = <&CLUSTER0_L2>;
		};

		A57_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 1>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0x84b00000>;
			next-level-cache = <&CLUSTER0_L2>;
		};

		A57_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 2>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0x84b00000>;
			next-level-cache = <&CLUSTER0_L2>;
		};

		A57_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 3>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0x84b00000>;
			next-level-cache = <&CLUSTER0_L2>;
		};

		CLUSTER0_L2: l2-cache@000 {
			compatible = "cache";
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_EDGE_RISING)>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A57_0>,
				     <&A57_1>,
				     <&A57_2>,
				     <&A57_3>;
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;

		smmu: mmu@64000000 {
			compatible = "arm,mmu-500";
			reg = <0x64000000 0x40000>;
			#global-interrupts = <2>;
			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
			mmu-masters;
		};

		crmu: crmu@65024000 {
			compatible = "syscon";
			reg = <0x65024000 0x100>;
		};

		reboot@65024000 {
			compatible ="syscon-reboot";
			regmap = <&crmu>;
			offset = <0x90>;
			mask = <0xfffffffd>;
		};

		gic: interrupt-controller@65210000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x65210000 0x1000>,
			      <0x65220000 0x1000>,
			      <0x65240000 0x2000>,
			      <0x65260000 0x1000>;
		};

		uart3: serial@66130000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x66130000 0x100>;
			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clock-frequency = <23961600>;
			status = "disabled";
		};

		hwrng: hwrng@66220000 {
			compatible = "brcm,iproc-rng200";
			reg = <0x66220000 0x28>;
		};
	};
};
Commit	Line	Data
6aad8bf9 RJ	1	/*
	2	* BSD LICENSE
	3	*
	4	* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in
	14	* the documentation and/or other materials provided with the
	15	* distribution.
	16	* * Neither the name of Broadcom Corporation nor the names of its
	17	* contributors may be used to endorse or promote products derived
	18	* from this software without specific prior written permission.
	19	*
	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	21	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	22	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	23	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	24	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	25	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	26	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	27	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	28	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	30	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*/
	32
	33	#include <dt-bindings/interrupt-controller/arm-gic.h>
	34
	35	/memreserve/ 0x84b00000 0x00000008;
	36
	37	/ {
	38	compatible = "brcm,ns2";
	39	interrupt-parent = <&gic>;
	40	#address-cells = <2>;
	41	#size-cells = <2>;
	42
	43	cpus {
	44	#address-cells = <2>;
	45	#size-cells = <0>;
	46
5b31d875	47	A57_0: cpu@0 {
6aad8bf9 RJ	48	device_type = "cpu";
	49	compatible = "arm,cortex-a57", "arm,armv8";
	50	reg = <0 0>;
	51	enable-method = "spin-table";
	52	cpu-release-addr = <0 0x84b00000>;
33a93aa4	53	next-level-cache = <&CLUSTER0_L2>;
6aad8bf9 RJ	54	};
6aad8bf9 RJ	55
5b31d875	56	A57_1: cpu@1 {
6aad8bf9 RJ	57	device_type = "cpu";
	58	compatible = "arm,cortex-a57", "arm,armv8";
	59	reg = <0 1>;
	60	enable-method = "spin-table";
	61	cpu-release-addr = <0 0x84b00000>;
33a93aa4	62	next-level-cache = <&CLUSTER0_L2>;
6aad8bf9 RJ	63	};
6aad8bf9 RJ	64
5b31d875	65	A57_2: cpu@2 {
6aad8bf9 RJ	66	device_type = "cpu";
	67	compatible = "arm,cortex-a57", "arm,armv8";
	68	reg = <0 2>;
	69	enable-method = "spin-table";
	70	cpu-release-addr = <0 0x84b00000>;
33a93aa4	71	next-level-cache = <&CLUSTER0_L2>;
6aad8bf9 RJ	72	};
6aad8bf9 RJ	73
5b31d875	74	A57_3: cpu@3 {
6aad8bf9 RJ	75	device_type = "cpu";
	76	compatible = "arm,cortex-a57", "arm,armv8";
	77	reg = <0 3>;
	78	enable-method = "spin-table";
	79	cpu-release-addr = <0 0x84b00000>;
33a93aa4 AP	80	next-level-cache = <&CLUSTER0_L2>;
	81	};
	82
	83	CLUSTER0_L2: l2-cache@000 {
	84	compatible = "cache";
6aad8bf9 RJ	85	};
	86	};
	87
	88	timer {
	89	compatible = "arm,armv8-timer";
	90	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) \|
	91	IRQ_TYPE_EDGE_RISING)>,
	92	<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) \|
	93	IRQ_TYPE_EDGE_RISING)>,
	94	<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) \|
	95	IRQ_TYPE_EDGE_RISING)>,
	96	<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) \|
	97	IRQ_TYPE_EDGE_RISING)>;
	98	};
	99
5b31d875 AP	100	pmu {
	101	compatible = "arm,armv8-pmuv3";
	102	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	103	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
	104	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	105	<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
	106	interrupt-affinity = <&A57_0>,
	107	<&A57_1>,
	108	<&A57_2>,
	109	<&A57_3>;
	110	};
	111
6aad8bf9 RJ	112	soc: soc {
	113	compatible = "simple-bus";
	114	#address-cells = <1>;
	115	#size-cells = <1>;
	116	ranges = <0 0 0 0xffffffff>;
	117
6ec5f3c5 AP	118	smmu: mmu@64000000 {
	119	compatible = "arm,mmu-500";
	120	reg = <0x64000000 0x40000>;
	121	#global-interrupts = <2>;
	122	interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
	123	<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
	124	<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
	125	<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
	126	<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
	127	<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
	128	<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
	129	<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
	130	<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
	131	<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
	132	<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
	133	<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
	134	<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
	135	<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
	136	<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
	137	<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
	138	<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
	139	<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
	140	<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
	141	<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
	142	<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
	143	<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
	144	<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
	145	<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
	146	<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
	147	<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
	148	<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
	149	<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	150	<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
	151	<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
	152	<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
	153	<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
	154	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
	155	<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
	156	mmu-masters;
	157	};
	158
5b467c3b AP	159	crmu: crmu@65024000 {
	160	compatible = "syscon";
	161	reg = <0x65024000 0x100>;
	162	};
	163
	164	reboot@65024000 {
	165	compatible ="syscon-reboot";
	166	regmap = <&crmu>;
	167	offset = <0x90>;
	168	mask = <0xfffffffd>;
	169	};
	170
6aad8bf9 RJ	171	gic: interrupt-controller@65210000 {
	172	compatible = "arm,gic-400";
	173	#interrupt-cells = <3>;
	174	interrupt-controller;
	175	reg = <0x65210000 0x1000>,
	176	<0x65220000 0x1000>,
	177	<0x65240000 0x2000>,
	178	<0x65260000 0x1000>;
	179	};
	180
	181	uart3: serial@66130000 {
	182	compatible = "snps,dw-apb-uart";
	183	reg = <0x66130000 0x100>;
	184	interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
	185	reg-shift = <2>;
	186	reg-io-width = <4>;
	187	clock-frequency = <23961600>;
	188	status = "disabled";
	189	};
e8a6e265 AP	190
	191	hwrng: hwrng@66220000 {
	192	compatible = "brcm,iproc-rng200";
	193	reg = <0x66220000 0x28>;
	194	};
6aad8bf9 RJ	195	};
6aad8bf9 RJ	196	};