ARM: dts: armada388-clearfog: enable spi flash

[linux-2.6-block.git] / arch / arm / boot / dts / armada-38x-solidrun-microsom.dtsi

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for SolidRun Armada 38x Microsom
 *
 *  Copyright (C) 2015 Russell King
 *
 * This board is in development; the contents of this file work with
 * the A1 rev 2.0 of the board, which does not represent final
 * production board.  Things will change, don't expect this file to
 * remain compatible info the future.
 */
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>; /* 256 MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;

		internal-regs {
			rtc@a3800 {
				/*
				 * If the rtc doesn't work, run "date reset"
				 * twice in u-boot.
				 */
				status = "okay";
			};
		};
	};
};

&bm {
	status = "okay";
};

&bm_bppi {
	status = "okay";
};

&eth0 {
	/* ethernet@70000 */
	pinctrl-0 = <&ge0_rgmii_pins>;
	pinctrl-names = "default";
	phy = <&phy_dedicated>;
	phy-mode = "rgmii-id";
	buffer-manager = <&bm>;
	bm,pool-long = <0>;
	bm,pool-short = <1>;
	status = "okay";
};

&mdio {
	/*
	 * Add the phy clock here, so the phy can be accessed to read its
	 * IDs prior to binding with the driver.
	 */
	pinctrl-0 = <&mdio_pins &microsom_phy_clk_pins>;
	pinctrl-names = "default";

	phy_dedicated: ethernet-phy@0 {
		/*
		 * Annoyingly, the marvell phy driver configures the LED
		 * register, rather than preserving reset-loaded setting.
		 * We undo that rubbish here.
		 */
		marvell,reg-init = <3 16 0 0x101e>;
		reg = <0>;
	};
};

&pinctrl {
	microsom_phy_clk_pins: microsom-phy-clk-pins {
		marvell,pins = "mpp45";
		marvell,function = "ref";
	};
	/* Optional eMMC */
	microsom_sdhci_pins: microsom-sdhci-pins {
		marvell,pins = "mpp21", "mpp28", "mpp37",
			       "mpp38", "mpp39", "mpp40";
		marvell,function = "sd0";
	};
};

&spi1 {
	/* The microsom has an optional W25Q32 on board, connected to CS0 */
	pinctrl-0 = <&spi1_pins>;

	w25q32: spi-flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "w25q32", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <3000000>;
	};
};

&uart0 {
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
	status = "okay";
};