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1 | /* |
2 | * Device Tree file for SolidRun Armada 38x Microsom | |
3 | * | |
4 | * Copyright (C) 2015 Russell King | |
5 | * | |
6 | * This board is in development; the contents of this file work with | |
7 | * the A1 rev 2.0 of the board, which does not represent final | |
8 | * production board. Things will change, don't expect this file to | |
9 | * remain compatible info the future. | |
10 | * | |
11 | * This file is dual-licensed: you can use it either under the terms | |
12 | * of the GPL or the X11 license, at your option. Note that this dual | |
13 | * licensing only applies to this file, and not this project as a | |
14 | * whole. | |
15 | * | |
16 | * a) This file is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License | |
18 | * version 2 as published by the Free Software Foundation. | |
19 | * | |
24f0b6fe | 20 | * This file is distributed in the hope that it will be useful, |
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21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
24f0b6fe | 25 | * Or, alternatively, |
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26 | * |
27 | * b) Permission is hereby granted, free of charge, to any person | |
28 | * obtaining a copy of this software and associated documentation | |
29 | * files (the "Software"), to deal in the Software without | |
24f0b6fe | 30 | * restriction, including without limitation the rights to use, |
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31 | * copy, modify, merge, publish, distribute, sublicense, and/or |
32 | * sell copies of the Software, and to permit persons to whom the | |
33 | * Software is furnished to do so, subject to the following | |
34 | * conditions: | |
35 | * | |
36 | * The above copyright notice and this permission notice shall be | |
37 | * included in all copies or substantial portions of the Software. | |
38 | * | |
24f0b6fe | 39 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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40 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
41 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
42 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
24f0b6fe | 43 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
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44 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
45 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
46 | * OTHER DEALINGS IN THE SOFTWARE. | |
47 | */ | |
48 | #include <dt-bindings/input/input.h> | |
49 | #include <dt-bindings/gpio/gpio.h> | |
50 | ||
51 | / { | |
52 | memory { | |
53 | device_type = "memory"; | |
54 | reg = <0x00000000 0x10000000>; /* 256 MB */ | |
55 | }; | |
56 | ||
57 | soc { | |
58 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 | |
59 | MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 | |
60 | MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 | |
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61 | MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000 |
62 | MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; | |
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63 | |
64 | internal-regs { | |
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65 | rtc@a3800 { |
66 | /* | |
67 | * If the rtc doesn't work, run "date reset" | |
68 | * twice in u-boot. | |
69 | */ | |
70 | status = "okay"; | |
71 | }; | |
4c945e85 | 72 | }; |
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73 | }; |
74 | }; | |
c49e99c2 | 75 | |
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76 | &bm { |
77 | status = "okay"; | |
78 | }; | |
79 | ||
80 | &bm_bppi { | |
81 | status = "okay"; | |
82 | }; | |
83 | ||
84 | ð0 { | |
85 | /* ethernet@70000 */ | |
86 | pinctrl-0 = <&ge0_rgmii_pins>; | |
87 | pinctrl-names = "default"; | |
88 | phy = <&phy_dedicated>; | |
89 | phy-mode = "rgmii-id"; | |
90 | buffer-manager = <&bm>; | |
91 | bm,pool-long = <0>; | |
92 | bm,pool-short = <1>; | |
93 | status = "okay"; | |
94 | }; | |
95 | ||
96 | &mdio { | |
97 | /* | |
98 | * Add the phy clock here, so the phy can be accessed to read its | |
99 | * IDs prior to binding with the driver. | |
100 | */ | |
101 | pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>; | |
102 | pinctrl-names = "default"; | |
c49e99c2 | 103 | |
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104 | phy_dedicated: ethernet-phy@0 { |
105 | /* | |
106 | * Annoyingly, the marvell phy driver configures the LED | |
107 | * register, rather than preserving reset-loaded setting. | |
108 | * We undo that rubbish here. | |
109 | */ | |
110 | marvell,reg-init = <3 16 0 0x101e>; | |
111 | reg = <0>; | |
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112 | }; |
113 | }; | |
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115 | &pinctrl { |
116 | microsom_phy_clk_pins: microsom-phy-clk-pins { | |
117 | marvell,pins = "mpp45"; | |
118 | marvell,function = "ref"; | |
119 | }; | |
120 | /* Optional eMMC */ | |
121 | microsom_sdhci_pins: microsom-sdhci-pins { | |
122 | marvell,pins = "mpp21", "mpp28", "mpp37", | |
123 | "mpp38", "mpp39", "mpp40"; | |
124 | marvell,function = "sd0"; | |
125 | }; | |
126 | }; | |
127 | ||
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128 | &spi1 { |
129 | /* The microsom has an optional W25Q32 on board, connected to CS0 */ | |
130 | pinctrl-0 = <&spi1_pins>; | |
131 | ||
132 | w25q32: spi-flash@0 { | |
133 | #address-cells = <1>; | |
134 | #size-cells = <1>; | |
135 | compatible = "w25q32", "jedec,spi-nor"; | |
136 | reg = <0>; /* Chip select 0 */ | |
137 | spi-max-frequency = <3000000>; | |
138 | status = "disabled"; | |
139 | }; | |
140 | }; | |
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141 | |
142 | &uart0 { | |
143 | pinctrl-0 = <&uart0_pins>; | |
144 | pinctrl-names = "default"; | |
145 | status = "okay"; | |
146 | }; |