[PATCH] Add store barrier defines for a bunch of archs

This makes blktrace work/compile on: alpha, hppa, sparc, m68k, mips and arm.

Signed-off-by: Jens Axboe <jens.axboe@oracle.com>

diff --git a/barrier.h b/barrier.h
index 280dc2221ce6b21bdf6649c6a3523fbc3bfa43ca..19169d7cd703b03b55dd522e7cc7b478d2d905da 100644 (file)
--- a/barrier.h
+++ b/barrier.h
@@ -2,17 +2,32 @@
 #define BARRIER_H
 
 #if defined(__ia64__)
-#define store_barrier()         asm volatile ("mf" ::: "memory")
+  #define store_barrier()         asm volatile ("mf" ::: "memory")
 #elif defined(__x86_64__)
-#define store_barrier()         asm volatile("sfence" ::: "memory")
+  #define store_barrier()         asm volatile("sfence" ::: "memory")
 #elif defined(__i386__)
-#define store_barrier()         asm volatile ("": : :"memory")
+  #define store_barrier()         asm volatile ("": : :"memory")
 #elif defined(__ppc__) || defined(__powerpc__)
-#define store_barrier()         asm volatile ("eieio" : : : "memory")
+  #define store_barrier()         asm volatile ("eieio" : : : "memory")
 #elif defined(__s390__) || defined(__s390x__)
-#define store_barrier()         asm volatile ("bcr 15,0" : : : "memory")
+  #define store_barrier()         asm volatile ("bcr 15,0" : : : "memory")
+#elif defined(__alpha__)
+  #define store_barrier()         asm volatile("wmb": : :"memory")
+#elif defined(__hppa__)
+  #define store_barrier()         asm volatile("":::"memory")
+#elif defined(__sparc__)
+  #define store_barrier()         asm volatile("":::"memory")
+#elif defined(__m68000__)
+  #define store_barrier()         asm volatile("":::"memory")
+#elif defined(__mips__)  /* also mipsel */
+  #define store_barrier()         do { } while(0)
+#elif defined(__arm__)
+  /* taken from linux/arch/arm/kernel/entry-armv.S, thanks to pbrook! */
+  typedef void (__kernel_dmb_t)(void);
+  #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
+  #define store_barrier()        __kernel_dmb()
 #else
-#error Define store_barrier() for your CPU
+  #error Define store_barrier() for your CPU
 #endif
 
 #endif