drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kernel.h>
  30 #include <linux/mm.h>
  31 #include <linux/module.h>
  32 #include <linux/moduleparam.h>
  33 #include <linux/pci.h>
  34 #include <linux/poison.h>
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/types.h>
  38 #include <linux/version.h>
  39
  40 #define NVME_Q_DEPTH 1024
  41 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  42 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  43 #define NVME_MINORS 64
  44 #define IO_TIMEOUT      (5 * HZ)
  45 #define ADMIN_TIMEOUT   (60 * HZ)
  46
  47 static int nvme_major;
  48 module_param(nvme_major, int, 0);
  49
  50 static int use_threaded_interrupts;
  51 module_param(use_threaded_interrupts, int, 0);
  52
  53 /*
  54  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  55  */
  56 struct nvme_dev {
  57         struct nvme_queue **queues;
  58         u32 __iomem *dbs;
  59         struct pci_dev *pci_dev;
  60         struct dma_pool *prp_page_pool;
  61         struct dma_pool *prp_small_pool;
  62         int instance;
  63         int queue_count;
  64         u32 ctrl_config;
  65         struct msix_entry *entry;
  66         struct nvme_bar __iomem *bar;
  67         struct list_head namespaces;
  68         char serial[20];
  69         char model[40];
  70         char firmware_rev[8];
  71 };
  72
  73 /*
  74  * An NVM Express namespace is equivalent to a SCSI LUN
  75  */
  76 struct nvme_ns {
  77         struct list_head list;
  78
  79         struct nvme_dev *dev;
  80         struct request_queue *queue;
  81         struct gendisk *disk;
  82
  83         int ns_id;
  84         int lba_shift;
  85 };
  86
  87 /*
  88  * An NVM Express queue.  Each device has at least two (one for admin
  89  * commands and one for I/O commands).
  90  */
  91 struct nvme_queue {
  92         struct device *q_dmadev;
  93         struct nvme_dev *dev;
  94         spinlock_t q_lock;
  95         struct nvme_command *sq_cmds;
  96         volatile struct nvme_completion *cqes;
  97         dma_addr_t sq_dma_addr;
  98         dma_addr_t cq_dma_addr;
  99         wait_queue_head_t sq_full;
 100         struct bio_list sq_cong;
 101         u32 __iomem *q_db;
 102         u16 q_depth;
 103         u16 cq_vector;
 104         u16 sq_head;
 105         u16 sq_tail;
 106         u16 cq_head;
 107         u16 cq_phase;
 108         unsigned long cmdid_data[];
 109 };
 110
 111 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio);
 112
 113 /*
 114  * Check we didin't inadvertently grow the command struct
 115  */
 116 static inline void _nvme_check_size(void)
 117 {
 118         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 119         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 120         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 121         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 122         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 123         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 124         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 125         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 126         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 127 }
 128
 129 struct nvme_cmd_info {
 130         unsigned long ctx;
 131         unsigned long timeout;
 132 };
 133
 134 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 135 {
 136         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 137 }
 138
 139 /**
 140  * alloc_cmdid - Allocate a Command ID
 141  * @param nvmeq The queue that will be used for this command
 142  * @param ctx A pointer that will be passed to the handler
 143  * @param handler The ID of the handler to call
 144  *
 145  * Allocate a Command ID for a queue.  The data passed in will
 146  * be passed to the completion handler.  This is implemented by using
 147  * the bottom two bits of the ctx pointer to store the handler ID.
 148  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 149  * We can change this if it becomes a problem.
 150  */
 151 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 152                                                         unsigned timeout)
 153 {
 154         int depth = nvmeq->q_depth;
 155         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 156         int cmdid;
 157
 158         BUG_ON((unsigned long)ctx & 3);
 159
 160         do {
 161                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 162                 if (cmdid >= depth)
 163                         return -EBUSY;
 164         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 165
 166         info[cmdid].ctx = (unsigned long)ctx | handler;
 167         info[cmdid].timeout = jiffies + timeout;
 168         return cmdid;
 169 }
 170
 171 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 172                                                 int handler, unsigned timeout)
 173 {
 174         int cmdid;
 175         wait_event_killable(nvmeq->sq_full,
 176                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 177         return (cmdid < 0) ? -EINTR : cmdid;
 178 }
 179
 180 /* If you need more than four handlers, you'll need to change how
 181  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 182  * CMD_CTX value instead, if that works for your situation.
 183  */
 184 enum {
 185         sync_completion_id = 0,
 186         bio_completion_id,
 187 };
 188
 189 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 190 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 191 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 192 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 193
 194 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 195 {
 196         unsigned long data;
 197         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 198
 199         if (cmdid >= nvmeq->q_depth)
 200                 return CMD_CTX_INVALID;
 201         data = info[cmdid].ctx;
 202         info[cmdid].ctx = CMD_CTX_COMPLETED;
 203         clear_bit(cmdid, nvmeq->cmdid_data);
 204         wake_up(&nvmeq->sq_full);
 205         return data;
 206 }
 207
 208 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 209 {
 210         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 211         info[cmdid].ctx = CMD_CTX_CANCELLED;
 212 }
 213
 214 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 215 {
 216         int qid, cpu = get_cpu();
 217         if (cpu < ns->dev->queue_count)
 218                 qid = cpu + 1;
 219         else
 220                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 221         return ns->dev->queues[qid];
 222 }
 223
 224 static void put_nvmeq(struct nvme_queue *nvmeq)
 225 {
 226         put_cpu();
 227 }
 228
 229 /**
 230  * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
 231  * @nvmeq: The queue to use
 232  * @cmd: The command to send
 233  *
 234  * Safe to use from interrupt context
 235  */
 236 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 237 {
 238         unsigned long flags;
 239         u16 tail;
 240         /* XXX: Need to check tail isn't going to overrun head */
 241         spin_lock_irqsave(&nvmeq->q_lock, flags);
 242         tail = nvmeq->sq_tail;
 243         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 244         writel(tail, nvmeq->q_db);
 245         if (++tail == nvmeq->q_depth)
 246                 tail = 0;
 247         nvmeq->sq_tail = tail;
 248         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 249
 250         return 0;
 251 }
 252
 253 struct nvme_prps {
 254         int npages;
 255         dma_addr_t first_dma;
 256         __le64 *list[0];
 257 };
 258
 259 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
 260 {
 261         const int last_prp = PAGE_SIZE / 8 - 1;
 262         int i;
 263         dma_addr_t prp_dma;
 264
 265         if (!prps)
 266                 return;
 267
 268         prp_dma = prps->first_dma;
 269
 270         if (prps->npages == 0)
 271                 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
 272         for (i = 0; i < prps->npages; i++) {
 273                 __le64 *prp_list = prps->list[i];
 274                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 275                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 276                 prp_dma = next_prp_dma;
 277         }
 278         kfree(prps);
 279 }
 280
 281 struct nvme_bio {
 282         struct bio *bio;
 283         int nents;
 284         struct nvme_prps *prps;
 285         struct scatterlist sg[0];
 286 };
 287
 288 /* XXX: use a mempool */
 289 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
 290 {
 291         return kzalloc(sizeof(struct nvme_bio) +
 292                         sizeof(struct scatterlist) * nseg, gfp);
 293 }
 294
 295 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
 296 {
 297         nvme_free_prps(nvmeq->dev, nbio->prps);
 298         kfree(nbio);
 299 }
 300
 301 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 302                                                 struct nvme_completion *cqe)
 303 {
 304         struct nvme_bio *nbio = ctx;
 305         struct bio *bio = nbio->bio;
 306         u16 status = le16_to_cpup(&cqe->status) >> 1;
 307
 308         dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
 309                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 310         free_nbio(nvmeq, nbio);
 311         bio_endio(bio, status ? -EIO : 0);
 312         bio = bio_list_pop(&nvmeq->sq_cong);
 313         if (bio)
 314                 nvme_resubmit_bio(nvmeq, bio);
 315 }
 316
 317 /* length is in bytes */
 318 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
 319                                         struct nvme_common_command *cmd,
 320                                         struct scatterlist *sg, int length)
 321 {
 322         struct dma_pool *pool;
 323         int dma_len = sg_dma_len(sg);
 324         u64 dma_addr = sg_dma_address(sg);
 325         int offset = offset_in_page(dma_addr);
 326         __le64 *prp_list;
 327         dma_addr_t prp_dma;
 328         int nprps, npages, i, prp_page;
 329         struct nvme_prps *prps = NULL;
 330
 331         cmd->prp1 = cpu_to_le64(dma_addr);
 332         length -= (PAGE_SIZE - offset);
 333         if (length <= 0)
 334                 return prps;
 335
 336         dma_len -= (PAGE_SIZE - offset);
 337         if (dma_len) {
 338                 dma_addr += (PAGE_SIZE - offset);
 339         } else {
 340                 sg = sg_next(sg);
 341                 dma_addr = sg_dma_address(sg);
 342                 dma_len = sg_dma_len(sg);
 343         }
 344
 345         if (length <= PAGE_SIZE) {
 346                 cmd->prp2 = cpu_to_le64(dma_addr);
 347                 return prps;
 348         }
 349
 350         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 351         npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
 352         prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
 353         prp_page = 0;
 354         if (nprps <= (256 / 8)) {
 355                 pool = dev->prp_small_pool;
 356                 prps->npages = 0;
 357         } else {
 358                 pool = dev->prp_page_pool;
 359                 prps->npages = npages;
 360         }
 361
 362         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 363         prps->list[prp_page++] = prp_list;
 364         prps->first_dma = prp_dma;
 365         cmd->prp2 = cpu_to_le64(prp_dma);
 366         i = 0;
 367         for (;;) {
 368                 if (i == PAGE_SIZE / 8 - 1) {
 369                         __le64 *old_prp_list = prp_list;
 370                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 371                         prps->list[prp_page++] = prp_list;
 372                         old_prp_list[i] = cpu_to_le64(prp_dma);
 373                         i = 0;
 374                 }
 375                 prp_list[i++] = cpu_to_le64(dma_addr);
 376                 dma_len -= PAGE_SIZE;
 377                 dma_addr += PAGE_SIZE;
 378                 length -= PAGE_SIZE;
 379                 if (length <= 0)
 380                         break;
 381                 if (dma_len > 0)
 382                         continue;
 383                 BUG_ON(dma_len < 0);
 384                 sg = sg_next(sg);
 385                 dma_addr = sg_dma_address(sg);
 386                 dma_len = sg_dma_len(sg);
 387         }
 388
 389         return prps;
 390 }
 391
 392 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
 393                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 394 {
 395         struct bio_vec *bvec, *bvprv = NULL;
 396         struct scatterlist *sg = NULL;
 397         int i, nsegs = 0;
 398
 399         sg_init_table(nbio->sg, psegs);
 400         bio_for_each_segment(bvec, bio, i) {
 401                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
 402                         sg->length += bvec->bv_len;
 403                 } else {
 404                         /* Check bvprv && offset == 0 */
 405                         sg = sg ? sg + 1 : nbio->sg;
 406                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
 407                                                         bvec->bv_offset);
 408                         nsegs++;
 409                 }
 410                 bvprv = bvec;
 411         }
 412         nbio->nents = nsegs;
 413         sg_mark_end(sg);
 414         return dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir);
 415 }
 416
 417 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 418                                                                 struct bio *bio)
 419 {
 420         struct nvme_command *cmnd;
 421         struct nvme_bio *nbio;
 422         enum dma_data_direction dma_dir;
 423         int cmdid, result = -ENOMEM;
 424         u16 control;
 425         u32 dsmgmt;
 426         int psegs = bio_phys_segments(ns->queue, bio);
 427
 428         nbio = alloc_nbio(psegs, GFP_ATOMIC);
 429         if (!nbio)
 430                 goto nomem;
 431         nbio->bio = bio;
 432
 433         result = -EBUSY;
 434         cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
 435         if (unlikely(cmdid < 0))
 436                 goto free_nbio;
 437
 438         control = 0;
 439         if (bio->bi_rw & REQ_FUA)
 440                 control |= NVME_RW_FUA;
 441         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 442                 control |= NVME_RW_LR;
 443
 444         dsmgmt = 0;
 445         if (bio->bi_rw & REQ_RAHEAD)
 446                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 447
 448         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 449
 450         memset(cmnd, 0, sizeof(*cmnd));
 451         if (bio_data_dir(bio)) {
 452                 cmnd->rw.opcode = nvme_cmd_write;
 453                 dma_dir = DMA_TO_DEVICE;
 454         } else {
 455                 cmnd->rw.opcode = nvme_cmd_read;
 456                 dma_dir = DMA_FROM_DEVICE;
 457         }
 458
 459         result = -ENOMEM;
 460         if (nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs) == 0)
 461                 goto free_nbio;
 462
 463         cmnd->rw.flags = 1;
 464         cmnd->rw.command_id = cmdid;
 465         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 466         nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
 467                                                                 bio->bi_size);
 468         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 469         cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
 470         cmnd->rw.control = cpu_to_le16(control);
 471         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 472
 473         writel(nvmeq->sq_tail, nvmeq->q_db);
 474         if (++nvmeq->sq_tail == nvmeq->q_depth)
 475                 nvmeq->sq_tail = 0;
 476
 477         return 0;
 478
 479  free_nbio:
 480         free_nbio(nvmeq, nbio);
 481  nomem:
 482         return result;
 483 }
 484
 485 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio)
 486 {
 487         struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
 488         if (nvme_submit_bio_queue(nvmeq, ns, bio))
 489                 bio_list_add_head(&nvmeq->sq_cong, bio);
 490         else if (bio_list_empty(&nvmeq->sq_cong))
 491                 blk_clear_queue_congested(ns->queue, rw_is_sync(bio->bi_rw));
 492         /* XXX: Need to duplicate the logic from __freed_request here */
 493 }
 494
 495 /*
 496  * NB: return value of non-zero would mean that we were a stacking driver.
 497  * make_request must always succeed.
 498  */
 499 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 500 {
 501         struct nvme_ns *ns = q->queuedata;
 502         struct nvme_queue *nvmeq = get_nvmeq(ns);
 503         int result = -EBUSY;
 504
 505         spin_lock_irq(&nvmeq->q_lock);
 506         if (bio_list_empty(&nvmeq->sq_cong))
 507                 result = nvme_submit_bio_queue(nvmeq, ns, bio);
 508         if (unlikely(result)) {
 509                 if (bio_list_empty(&nvmeq->sq_cong))
 510                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 511                 bio_list_add(&nvmeq->sq_cong, bio);
 512         }
 513
 514         spin_unlock_irq(&nvmeq->q_lock);
 515         put_nvmeq(nvmeq);
 516
 517         return 0;
 518 }
 519
 520 struct sync_cmd_info {
 521         struct task_struct *task;
 522         u32 result;
 523         int status;
 524 };
 525
 526 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 527                                                 struct nvme_completion *cqe)
 528 {
 529         struct sync_cmd_info *cmdinfo = ctx;
 530         if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
 531                 return;
 532         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 533                 dev_warn(nvmeq->q_dmadev,
 534                                 "completed id %d twice on queue %d\n",
 535                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 536                 return;
 537         }
 538         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 539                 dev_warn(nvmeq->q_dmadev,
 540                                 "invalid id %d completed on queue %d\n",
 541                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 542                 return;
 543         }
 544         cmdinfo->result = le32_to_cpup(&cqe->result);
 545         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 546         wake_up_process(cmdinfo->task);
 547 }
 548
 549 typedef void (*completion_fn)(struct nvme_queue *, void *,
 550                                                 struct nvme_completion *);
 551
 552 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 553 {
 554         u16 head, phase;
 555
 556         static const completion_fn completions[4] = {
 557                 [sync_completion_id] = sync_completion,
 558                 [bio_completion_id]  = bio_completion,
 559         };
 560
 561         head = nvmeq->cq_head;
 562         phase = nvmeq->cq_phase;
 563
 564         for (;;) {
 565                 unsigned long data;
 566                 void *ptr;
 567                 unsigned char handler;
 568                 struct nvme_completion cqe = nvmeq->cqes[head];
 569                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 570                         break;
 571                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 572                 if (++head == nvmeq->q_depth) {
 573                         head = 0;
 574                         phase = !phase;
 575                 }
 576
 577                 data = free_cmdid(nvmeq, cqe.command_id);
 578                 handler = data & 3;
 579                 ptr = (void *)(data & ~3UL);
 580                 completions[handler](nvmeq, ptr, &cqe);
 581         }
 582
 583         /* If the controller ignores the cq head doorbell and continuously
 584          * writes to the queue, it is theoretically possible to wrap around
 585          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 586          * requires that 0.1% of your interrupts are handled, so this isn't
 587          * a big problem.
 588          */
 589         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 590                 return IRQ_NONE;
 591
 592         writel(head, nvmeq->q_db + 1);
 593         nvmeq->cq_head = head;
 594         nvmeq->cq_phase = phase;
 595
 596         return IRQ_HANDLED;
 597 }
 598
 599 static irqreturn_t nvme_irq(int irq, void *data)
 600 {
 601         irqreturn_t result;
 602         struct nvme_queue *nvmeq = data;
 603         spin_lock(&nvmeq->q_lock);
 604         result = nvme_process_cq(nvmeq);
 605         spin_unlock(&nvmeq->q_lock);
 606         return result;
 607 }
 608
 609 static irqreturn_t nvme_irq_check(int irq, void *data)
 610 {
 611         struct nvme_queue *nvmeq = data;
 612         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 613         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 614                 return IRQ_NONE;
 615         return IRQ_WAKE_THREAD;
 616 }
 617
 618 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 619 {
 620         spin_lock_irq(&nvmeq->q_lock);
 621         cancel_cmdid_data(nvmeq, cmdid);
 622         spin_unlock_irq(&nvmeq->q_lock);
 623 }
 624
 625 /*
 626  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 627  * if the result is positive, it's an NVM Express status code
 628  */
 629 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 630                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 631 {
 632         int cmdid;
 633         struct sync_cmd_info cmdinfo;
 634
 635         cmdinfo.task = current;
 636         cmdinfo.status = -EINTR;
 637
 638         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 639                                                                 timeout);
 640         if (cmdid < 0)
 641                 return cmdid;
 642         cmd->common.command_id = cmdid;
 643
 644         set_current_state(TASK_KILLABLE);
 645         nvme_submit_cmd(nvmeq, cmd);
 646         schedule();
 647
 648         if (cmdinfo.status == -EINTR) {
 649                 nvme_abort_command(nvmeq, cmdid);
 650                 return -EINTR;
 651         }
 652
 653         if (result)
 654                 *result = cmdinfo.result;
 655
 656         return cmdinfo.status;
 657 }
 658
 659 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 660                                                                 u32 *result)
 661 {
 662         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 663 }
 664
 665 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 666 {
 667         int status;
 668         struct nvme_command c;
 669
 670         memset(&c, 0, sizeof(c));
 671         c.delete_queue.opcode = opcode;
 672         c.delete_queue.qid = cpu_to_le16(id);
 673
 674         status = nvme_submit_admin_cmd(dev, &c, NULL);
 675         if (status)
 676                 return -EIO;
 677         return 0;
 678 }
 679
 680 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 681                                                 struct nvme_queue *nvmeq)
 682 {
 683         int status;
 684         struct nvme_command c;
 685         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 686
 687         memset(&c, 0, sizeof(c));
 688         c.create_cq.opcode = nvme_admin_create_cq;
 689         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 690         c.create_cq.cqid = cpu_to_le16(qid);
 691         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 692         c.create_cq.cq_flags = cpu_to_le16(flags);
 693         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 694
 695         status = nvme_submit_admin_cmd(dev, &c, NULL);
 696         if (status)
 697                 return -EIO;
 698         return 0;
 699 }
 700
 701 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 702                                                 struct nvme_queue *nvmeq)
 703 {
 704         int status;
 705         struct nvme_command c;
 706         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 707
 708         memset(&c, 0, sizeof(c));
 709         c.create_sq.opcode = nvme_admin_create_sq;
 710         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 711         c.create_sq.sqid = cpu_to_le16(qid);
 712         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 713         c.create_sq.sq_flags = cpu_to_le16(flags);
 714         c.create_sq.cqid = cpu_to_le16(qid);
 715
 716         status = nvme_submit_admin_cmd(dev, &c, NULL);
 717         if (status)
 718                 return -EIO;
 719         return 0;
 720 }
 721
 722 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 723 {
 724         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 725 }
 726
 727 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 728 {
 729         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 730 }
 731
 732 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 733 {
 734         struct nvme_queue *nvmeq = dev->queues[qid];
 735
 736         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 737
 738         /* Don't tell the adapter to delete the admin queue */
 739         if (qid) {
 740                 adapter_delete_sq(dev, qid);
 741                 adapter_delete_cq(dev, qid);
 742         }
 743
 744         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 745                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 746         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 747                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 748         kfree(nvmeq);
 749 }
 750
 751 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 752                                                         int depth, int vector)
 753 {
 754         struct device *dmadev = &dev->pci_dev->dev;
 755         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 756         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 757         if (!nvmeq)
 758                 return NULL;
 759
 760         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 761                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 762         if (!nvmeq->cqes)
 763                 goto free_nvmeq;
 764         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 765
 766         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 767                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 768         if (!nvmeq->sq_cmds)
 769                 goto free_cqdma;
 770
 771         nvmeq->q_dmadev = dmadev;
 772         nvmeq->dev = dev;
 773         spin_lock_init(&nvmeq->q_lock);
 774         nvmeq->cq_head = 0;
 775         nvmeq->cq_phase = 1;
 776         init_waitqueue_head(&nvmeq->sq_full);
 777         bio_list_init(&nvmeq->sq_cong);
 778         nvmeq->q_db = &dev->dbs[qid * 2];
 779         nvmeq->q_depth = depth;
 780         nvmeq->cq_vector = vector;
 781
 782         return nvmeq;
 783
 784  free_cqdma:
 785         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 786                                                         nvmeq->cq_dma_addr);
 787  free_nvmeq:
 788         kfree(nvmeq);
 789         return NULL;
 790 }
 791
 792 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 793                                                         const char *name)
 794 {
 795         if (use_threaded_interrupts)
 796                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 797                                         nvme_irq_check, nvme_irq,
 798                                         IRQF_DISABLED | IRQF_SHARED,
 799                                         name, nvmeq);
 800         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 801                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 802 }
 803
 804 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 805                                         int qid, int cq_size, int vector)
 806 {
 807         int result;
 808         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 809
 810         if (!nvmeq)
 811                 return NULL;
 812
 813         result = adapter_alloc_cq(dev, qid, nvmeq);
 814         if (result < 0)
 815                 goto free_nvmeq;
 816
 817         result = adapter_alloc_sq(dev, qid, nvmeq);
 818         if (result < 0)
 819                 goto release_cq;
 820
 821         result = queue_request_irq(dev, nvmeq, "nvme");
 822         if (result < 0)
 823                 goto release_sq;
 824
 825         return nvmeq;
 826
 827  release_sq:
 828         adapter_delete_sq(dev, qid);
 829  release_cq:
 830         adapter_delete_cq(dev, qid);
 831  free_nvmeq:
 832         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 833                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 834         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 835                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 836         kfree(nvmeq);
 837         return NULL;
 838 }
 839
 840 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 841 {
 842         int result;
 843         u32 aqa;
 844         struct nvme_queue *nvmeq;
 845
 846         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 847
 848         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 849         if (!nvmeq)
 850                 return -ENOMEM;
 851
 852         aqa = nvmeq->q_depth - 1;
 853         aqa |= aqa << 16;
 854
 855         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 856         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 857         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 858
 859         writel(0, &dev->bar->cc);
 860         writel(aqa, &dev->bar->aqa);
 861         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 862         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 863         writel(dev->ctrl_config, &dev->bar->cc);
 864
 865         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 866                 msleep(100);
 867                 if (fatal_signal_pending(current))
 868                         return -EINTR;
 869         }
 870
 871         result = queue_request_irq(dev, nvmeq, "nvme admin");
 872         dev->queues[0] = nvmeq;
 873         return result;
 874 }
 875
 876 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 877                                 unsigned long addr, unsigned length,
 878                                 struct scatterlist **sgp)
 879 {
 880         int i, err, count, nents, offset;
 881         struct scatterlist *sg;
 882         struct page **pages;
 883
 884         if (addr & 3)
 885                 return -EINVAL;
 886         if (!length)
 887                 return -EINVAL;
 888
 889         offset = offset_in_page(addr);
 890         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 891         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 892
 893         err = get_user_pages_fast(addr, count, 1, pages);
 894         if (err < count) {
 895                 count = err;
 896                 err = -EFAULT;
 897                 goto put_pages;
 898         }
 899
 900         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 901         sg_init_table(sg, count);
 902         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 903         length -= (PAGE_SIZE - offset);
 904         for (i = 1; i < count; i++) {
 905                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 906                 length -= PAGE_SIZE;
 907         }
 908
 909         err = -ENOMEM;
 910         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 911                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 912         if (!nents)
 913                 goto put_pages;
 914
 915         kfree(pages);
 916         *sgp = sg;
 917         return nents;
 918
 919  put_pages:
 920         for (i = 0; i < count; i++)
 921                 put_page(pages[i]);
 922         kfree(pages);
 923         return err;
 924 }
 925
 926 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 927                                 unsigned long addr, int length,
 928                                 struct scatterlist *sg, int nents)
 929 {
 930         int i, count;
 931
 932         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 933         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 934
 935         for (i = 0; i < count; i++)
 936                 put_page(sg_page(&sg[i]));
 937 }
 938
 939 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 940                                         unsigned long addr, unsigned length,
 941                                         struct nvme_command *cmd)
 942 {
 943         int err, nents;
 944         struct scatterlist *sg;
 945         struct nvme_prps *prps;
 946
 947         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
 948         if (nents < 0)
 949                 return nents;
 950         prps = nvme_setup_prps(dev, &cmd->common, sg, length);
 951         err = nvme_submit_admin_cmd(dev, cmd, NULL);
 952         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
 953         nvme_free_prps(dev, prps);
 954         return err ? -EIO : 0;
 955 }
 956
 957 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
 958 {
 959         struct nvme_command c;
 960
 961         memset(&c, 0, sizeof(c));
 962         c.identify.opcode = nvme_admin_identify;
 963         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
 964         c.identify.cns = cpu_to_le32(cns);
 965
 966         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 967 }
 968
 969 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
 970 {
 971         struct nvme_command c;
 972
 973         memset(&c, 0, sizeof(c));
 974         c.features.opcode = nvme_admin_get_features;
 975         c.features.nsid = cpu_to_le32(ns->ns_id);
 976         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
 977
 978         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 979 }
 980
 981 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
 982 {
 983         struct nvme_dev *dev = ns->dev;
 984         struct nvme_queue *nvmeq;
 985         struct nvme_user_io io;
 986         struct nvme_command c;
 987         unsigned length;
 988         u32 result;
 989         int nents, status;
 990         struct scatterlist *sg;
 991         struct nvme_prps *prps;
 992
 993         if (copy_from_user(&io, uio, sizeof(io)))
 994                 return -EFAULT;
 995         length = io.nblocks << io.block_shift;
 996         nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
 997         if (nents < 0)
 998                 return nents;
 999
1000         memset(&c, 0, sizeof(c));
1001         c.rw.opcode = io.opcode;
1002         c.rw.flags = io.flags;
1003         c.rw.nsid = cpu_to_le32(io.nsid);
1004         c.rw.slba = cpu_to_le64(io.slba);
1005         c.rw.length = cpu_to_le16(io.nblocks - 1);
1006         c.rw.control = cpu_to_le16(io.control);
1007         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1008         c.rw.reftag = cpu_to_le32(io.reftag);   /* XXX: endian? */
1009         c.rw.apptag = cpu_to_le16(io.apptag);
1010         c.rw.appmask = cpu_to_le16(io.appmask);
1011         /* XXX: metadata */
1012         prps = nvme_setup_prps(dev, &c.common, sg, length);
1013
1014         nvmeq = get_nvmeq(ns);
1015         /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1016          * disabled.  We may be preempted at any point, and be rescheduled
1017          * to a different CPU.  That will cause cacheline bouncing, but no
1018          * additional races since q_lock already protects against other CPUs.
1019          */
1020         put_nvmeq(nvmeq);
1021         status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
1022
1023         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1024         nvme_free_prps(dev, prps);
1025         put_user(result, &uio->result);
1026         return status;
1027 }
1028
1029 static int nvme_download_firmware(struct nvme_ns *ns,
1030                                                 struct nvme_dlfw __user *udlfw)
1031 {
1032         struct nvme_dev *dev = ns->dev;
1033         struct nvme_dlfw dlfw;
1034         struct nvme_command c;
1035         int nents, status;
1036         struct scatterlist *sg;
1037         struct nvme_prps *prps;
1038
1039         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1040                 return -EFAULT;
1041         if (dlfw.length >= (1 << 30))
1042                 return -EINVAL;
1043
1044         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1045         if (nents < 0)
1046                 return nents;
1047
1048         memset(&c, 0, sizeof(c));
1049         c.dlfw.opcode = nvme_admin_download_fw;
1050         c.dlfw.numd = cpu_to_le32(dlfw.length);
1051         c.dlfw.offset = cpu_to_le32(dlfw.offset);
1052         prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
1053
1054         status = nvme_submit_admin_cmd(dev, &c, NULL);
1055         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1056         nvme_free_prps(dev, prps);
1057         return status;
1058 }
1059
1060 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1061 {
1062         struct nvme_dev *dev = ns->dev;
1063         struct nvme_command c;
1064
1065         memset(&c, 0, sizeof(c));
1066         c.common.opcode = nvme_admin_activate_fw;
1067         c.common.rsvd10[0] = cpu_to_le32(arg);
1068
1069         return nvme_submit_admin_cmd(dev, &c, NULL);
1070 }
1071
1072 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1073                                                         unsigned long arg)
1074 {
1075         struct nvme_ns *ns = bdev->bd_disk->private_data;
1076
1077         switch (cmd) {
1078         case NVME_IOCTL_IDENTIFY_NS:
1079                 return nvme_identify(ns, arg, 0);
1080         case NVME_IOCTL_IDENTIFY_CTRL:
1081                 return nvme_identify(ns, arg, 1);
1082         case NVME_IOCTL_GET_RANGE_TYPE:
1083                 return nvme_get_range_type(ns, arg);
1084         case NVME_IOCTL_SUBMIT_IO:
1085                 return nvme_submit_io(ns, (void __user *)arg);
1086         case NVME_IOCTL_DOWNLOAD_FW:
1087                 return nvme_download_firmware(ns, (void __user *)arg);
1088         case NVME_IOCTL_ACTIVATE_FW:
1089                 return nvme_activate_firmware(ns, arg);
1090         default:
1091                 return -ENOTTY;
1092         }
1093 }
1094
1095 static const struct block_device_operations nvme_fops = {
1096         .owner          = THIS_MODULE,
1097         .ioctl          = nvme_ioctl,
1098 };
1099
1100 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1101                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1102 {
1103         struct nvme_ns *ns;
1104         struct gendisk *disk;
1105         int lbaf;
1106
1107         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1108                 return NULL;
1109
1110         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1111         if (!ns)
1112                 return NULL;
1113         ns->queue = blk_alloc_queue(GFP_KERNEL);
1114         if (!ns->queue)
1115                 goto out_free_ns;
1116         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1117                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1118         blk_queue_make_request(ns->queue, nvme_make_request);
1119         ns->dev = dev;
1120         ns->queue->queuedata = ns;
1121
1122         disk = alloc_disk(NVME_MINORS);
1123         if (!disk)
1124                 goto out_free_queue;
1125         ns->ns_id = index;
1126         ns->disk = disk;
1127         lbaf = id->flbas & 0xf;
1128         ns->lba_shift = id->lbaf[lbaf].ds;
1129
1130         disk->major = nvme_major;
1131         disk->minors = NVME_MINORS;
1132         disk->first_minor = NVME_MINORS * index;
1133         disk->fops = &nvme_fops;
1134         disk->private_data = ns;
1135         disk->queue = ns->queue;
1136         disk->driverfs_dev = &dev->pci_dev->dev;
1137         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1138         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1139
1140         return ns;
1141
1142  out_free_queue:
1143         blk_cleanup_queue(ns->queue);
1144  out_free_ns:
1145         kfree(ns);
1146         return NULL;
1147 }
1148
1149 static void nvme_ns_free(struct nvme_ns *ns)
1150 {
1151         put_disk(ns->disk);
1152         blk_cleanup_queue(ns->queue);
1153         kfree(ns);
1154 }
1155
1156 static int set_queue_count(struct nvme_dev *dev, int count)
1157 {
1158         int status;
1159         u32 result;
1160         struct nvme_command c;
1161         u32 q_count = (count - 1) | ((count - 1) << 16);
1162
1163         memset(&c, 0, sizeof(c));
1164         c.features.opcode = nvme_admin_get_features;
1165         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1166         c.features.dword11 = cpu_to_le32(q_count);
1167
1168         status = nvme_submit_admin_cmd(dev, &c, &result);
1169         if (status)
1170                 return -EIO;
1171         return min(result & 0xffff, result >> 16) + 1;
1172 }
1173
1174 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1175 {
1176         int result, cpu, i, nr_queues;
1177
1178         nr_queues = num_online_cpus();
1179         result = set_queue_count(dev, nr_queues);
1180         if (result < 0)
1181                 return result;
1182         if (result < nr_queues)
1183                 nr_queues = result;
1184
1185         /* Deregister the admin queue's interrupt */
1186         free_irq(dev->entry[0].vector, dev->queues[0]);
1187
1188         for (i = 0; i < nr_queues; i++)
1189                 dev->entry[i].entry = i;
1190         for (;;) {
1191                 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1192                 if (result == 0) {
1193                         break;
1194                 } else if (result > 0) {
1195                         nr_queues = result;
1196                         continue;
1197                 } else {
1198                         nr_queues = 1;
1199                         break;
1200                 }
1201         }
1202
1203         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1204         /* XXX: handle failure here */
1205
1206         cpu = cpumask_first(cpu_online_mask);
1207         for (i = 0; i < nr_queues; i++) {
1208                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1209                 cpu = cpumask_next(cpu, cpu_online_mask);
1210         }
1211
1212         for (i = 0; i < nr_queues; i++) {
1213                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1214                                                         NVME_Q_DEPTH, i);
1215                 if (!dev->queues[i + 1])
1216                         return -ENOMEM;
1217                 dev->queue_count++;
1218         }
1219
1220         return 0;
1221 }
1222
1223 static void nvme_free_queues(struct nvme_dev *dev)
1224 {
1225         int i;
1226
1227         for (i = dev->queue_count - 1; i >= 0; i--)
1228                 nvme_free_queue(dev, i);
1229 }
1230
1231 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1232 {
1233         int res, nn, i;
1234         struct nvme_ns *ns, *next;
1235         struct nvme_id_ctrl *ctrl;
1236         void *id;
1237         dma_addr_t dma_addr;
1238         struct nvme_command cid, crt;
1239
1240         res = nvme_setup_io_queues(dev);
1241         if (res)
1242                 return res;
1243
1244         /* XXX: Switch to a SG list once prp2 works */
1245         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1246                                                                 GFP_KERNEL);
1247
1248         memset(&cid, 0, sizeof(cid));
1249         cid.identify.opcode = nvme_admin_identify;
1250         cid.identify.nsid = 0;
1251         cid.identify.prp1 = cpu_to_le64(dma_addr);
1252         cid.identify.cns = cpu_to_le32(1);
1253
1254         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1255         if (res) {
1256                 res = -EIO;
1257                 goto out_free;
1258         }
1259
1260         ctrl = id;
1261         nn = le32_to_cpup(&ctrl->nn);
1262         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1263         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1264         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1265
1266         cid.identify.cns = 0;
1267         memset(&crt, 0, sizeof(crt));
1268         crt.features.opcode = nvme_admin_get_features;
1269         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1270         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1271
1272         for (i = 0; i < nn; i++) {
1273                 cid.identify.nsid = cpu_to_le32(i);
1274                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1275                 if (res)
1276                         continue;
1277
1278                 if (((struct nvme_id_ns *)id)->ncap == 0)
1279                         continue;
1280
1281                 crt.features.nsid = cpu_to_le32(i);
1282                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1283                 if (res)
1284                         continue;
1285
1286                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1287                 if (ns)
1288                         list_add_tail(&ns->list, &dev->namespaces);
1289         }
1290         list_for_each_entry(ns, &dev->namespaces, list)
1291                 add_disk(ns->disk);
1292
1293         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1294         return 0;
1295
1296  out_free:
1297         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1298                 list_del(&ns->list);
1299                 nvme_ns_free(ns);
1300         }
1301
1302         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1303         return res;
1304 }
1305
1306 static int nvme_dev_remove(struct nvme_dev *dev)
1307 {
1308         struct nvme_ns *ns, *next;
1309
1310         /* TODO: wait all I/O finished or cancel them */
1311
1312         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1313                 list_del(&ns->list);
1314                 del_gendisk(ns->disk);
1315                 nvme_ns_free(ns);
1316         }
1317
1318         nvme_free_queues(dev);
1319
1320         return 0;
1321 }
1322
1323 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1324 {
1325         struct device *dmadev = &dev->pci_dev->dev;
1326         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1327                                                 PAGE_SIZE, PAGE_SIZE, 0);
1328         if (!dev->prp_page_pool)
1329                 return -ENOMEM;
1330
1331         /* Optimisation for I/Os between 4k and 128k */
1332         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1333                                                 256, 256, 0);
1334         if (!dev->prp_small_pool) {
1335                 dma_pool_destroy(dev->prp_page_pool);
1336                 return -ENOMEM;
1337         }
1338         return 0;
1339 }
1340
1341 static void nvme_release_prp_pools(struct nvme_dev *dev)
1342 {
1343         dma_pool_destroy(dev->prp_page_pool);
1344         dma_pool_destroy(dev->prp_small_pool);
1345 }
1346
1347 /* XXX: Use an ida or something to let remove / add work correctly */
1348 static void nvme_set_instance(struct nvme_dev *dev)
1349 {
1350         static int instance;
1351         dev->instance = instance++;
1352 }
1353
1354 static void nvme_release_instance(struct nvme_dev *dev)
1355 {
1356 }
1357
1358 static int __devinit nvme_probe(struct pci_dev *pdev,
1359                                                 const struct pci_device_id *id)
1360 {
1361         int bars, result = -ENOMEM;
1362         struct nvme_dev *dev;
1363
1364         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1365         if (!dev)
1366                 return -ENOMEM;
1367         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1368                                                                 GFP_KERNEL);
1369         if (!dev->entry)
1370                 goto free;
1371         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1372                                                                 GFP_KERNEL);
1373         if (!dev->queues)
1374                 goto free;
1375
1376         if (pci_enable_device_mem(pdev))
1377                 goto free;
1378         pci_set_master(pdev);
1379         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1380         if (pci_request_selected_regions(pdev, bars, "nvme"))
1381                 goto disable;
1382
1383         INIT_LIST_HEAD(&dev->namespaces);
1384         dev->pci_dev = pdev;
1385         pci_set_drvdata(pdev, dev);
1386         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1387         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1388         nvme_set_instance(dev);
1389         dev->entry[0].vector = pdev->irq;
1390
1391         result = nvme_setup_prp_pools(dev);
1392         if (result)
1393                 goto disable_msix;
1394
1395         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1396         if (!dev->bar) {
1397                 result = -ENOMEM;
1398                 goto disable_msix;
1399         }
1400
1401         result = nvme_configure_admin_queue(dev);
1402         if (result)
1403                 goto unmap;
1404         dev->queue_count++;
1405
1406         result = nvme_dev_add(dev);
1407         if (result)
1408                 goto delete;
1409         return 0;
1410
1411  delete:
1412         nvme_free_queues(dev);
1413  unmap:
1414         iounmap(dev->bar);
1415  disable_msix:
1416         pci_disable_msix(pdev);
1417         nvme_release_instance(dev);
1418         nvme_release_prp_pools(dev);
1419  disable:
1420         pci_disable_device(pdev);
1421         pci_release_regions(pdev);
1422  free:
1423         kfree(dev->queues);
1424         kfree(dev->entry);
1425         kfree(dev);
1426         return result;
1427 }
1428
1429 static void __devexit nvme_remove(struct pci_dev *pdev)
1430 {
1431         struct nvme_dev *dev = pci_get_drvdata(pdev);
1432         nvme_dev_remove(dev);
1433         pci_disable_msix(pdev);
1434         iounmap(dev->bar);
1435         nvme_release_instance(dev);
1436         nvme_release_prp_pools(dev);
1437         pci_disable_device(pdev);
1438         pci_release_regions(pdev);
1439         kfree(dev->queues);
1440         kfree(dev->entry);
1441         kfree(dev);
1442 }
1443
1444 /* These functions are yet to be implemented */
1445 #define nvme_error_detected NULL
1446 #define nvme_dump_registers NULL
1447 #define nvme_link_reset NULL
1448 #define nvme_slot_reset NULL
1449 #define nvme_error_resume NULL
1450 #define nvme_suspend NULL
1451 #define nvme_resume NULL
1452
1453 static struct pci_error_handlers nvme_err_handler = {
1454         .error_detected = nvme_error_detected,
1455         .mmio_enabled   = nvme_dump_registers,
1456         .link_reset     = nvme_link_reset,
1457         .slot_reset     = nvme_slot_reset,
1458         .resume         = nvme_error_resume,
1459 };
1460
1461 /* Move to pci_ids.h later */
1462 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1463
1464 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1465         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1466         { 0, }
1467 };
1468 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1469
1470 static struct pci_driver nvme_driver = {
1471         .name           = "nvme",
1472         .id_table       = nvme_id_table,
1473         .probe          = nvme_probe,
1474         .remove         = __devexit_p(nvme_remove),
1475         .suspend        = nvme_suspend,
1476         .resume         = nvme_resume,
1477         .err_handler    = &nvme_err_handler,
1478 };
1479
1480 static int __init nvme_init(void)
1481 {
1482         int result;
1483
1484         nvme_major = register_blkdev(nvme_major, "nvme");
1485         if (nvme_major <= 0)
1486                 return -EBUSY;
1487
1488         result = pci_register_driver(&nvme_driver);
1489         if (!result)
1490                 return 0;
1491
1492         unregister_blkdev(nvme_major, "nvme");
1493         return result;
1494 }
1495
1496 static void __exit nvme_exit(void)
1497 {
1498         pci_unregister_driver(&nvme_driver);
1499         unregister_blkdev(nvme_major, "nvme");
1500 }
1501
1502 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1503 MODULE_LICENSE("GPL");
1504 MODULE_VERSION("0.2");
1505 module_init(nvme_init);
1506 module_exit(nvme_exit);