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81629cba AD |
1 | /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- |
2 | * | |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. | |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. | |
6 | * Copyright 2014 Advanced Micro Devices, Inc. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
24 | * OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | * Authors: | |
27 | * Kevin E. Martin <martin@valinux.com> | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | */ | |
31 | ||
32 | #ifndef __AMDGPU_DRM_H__ | |
33 | #define __AMDGPU_DRM_H__ | |
34 | ||
b3fcf36a | 35 | #include "drm.h" |
81629cba | 36 | |
cfa7152f EV |
37 | #if defined(__cplusplus) |
38 | extern "C" { | |
39 | #endif | |
40 | ||
81629cba AD |
41 | #define DRM_AMDGPU_GEM_CREATE 0x00 |
42 | #define DRM_AMDGPU_GEM_MMAP 0x01 | |
43 | #define DRM_AMDGPU_CTX 0x02 | |
44 | #define DRM_AMDGPU_BO_LIST 0x03 | |
45 | #define DRM_AMDGPU_CS 0x04 | |
46 | #define DRM_AMDGPU_INFO 0x05 | |
47 | #define DRM_AMDGPU_GEM_METADATA 0x06 | |
48 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 | |
49 | #define DRM_AMDGPU_GEM_VA 0x08 | |
50 | #define DRM_AMDGPU_WAIT_CS 0x09 | |
51 | #define DRM_AMDGPU_GEM_OP 0x10 | |
52 | #define DRM_AMDGPU_GEM_USERPTR 0x11 | |
eef18a82 | 53 | #define DRM_AMDGPU_WAIT_FENCES 0x12 |
cfbcacf4 | 54 | #define DRM_AMDGPU_VM 0x13 |
7ca24cf2 | 55 | #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 |
81629cba AD |
56 | |
57 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) | |
58 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) | |
59 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) | |
60 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) | |
61 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) | |
62 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) | |
63 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) | |
64 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) | |
34b5f6a6 | 65 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
81629cba AD |
66 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
67 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) | |
68 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) | |
eef18a82 | 69 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) |
cfbcacf4 | 70 | #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) |
7ca24cf2 | 71 | #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) |
81629cba AD |
72 | |
73 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 | |
74 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 | |
75 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 | |
76 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 | |
77 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 | |
78 | #define AMDGPU_GEM_DOMAIN_OA 0x20 | |
79 | ||
81629cba AD |
80 | /* Flag that CPU access will be required for the case of VRAM domain */ |
81 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) | |
82 | /* Flag that CPU access will not work, this VRAM domain is invisible */ | |
83 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) | |
81629cba | 84 | /* Flag that USWC attributes should be used for GTT */ |
88671288 | 85 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
4fea83ff FC |
86 | /* Flag that the memory should be in VRAM and cleared */ |
87 | #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) | |
e7893c4b CZ |
88 | /* Flag that create shadow bo(GTT) while allocating vram bo */ |
89 | #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) | |
03f48dd5 CK |
90 | /* Flag that allocating the BO should use linear VRAM */ |
91 | #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) | |
e1eb899b CK |
92 | /* Flag that BO is always valid in this VM */ |
93 | #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) | |
81629cba | 94 | |
81629cba AD |
95 | struct drm_amdgpu_gem_create_in { |
96 | /** the requested memory size */ | |
2ce9dde0 | 97 | __u64 bo_size; |
81629cba | 98 | /** physical start_addr alignment in bytes for some HW requirements */ |
2ce9dde0 | 99 | __u64 alignment; |
81629cba | 100 | /** the requested memory domains */ |
2ce9dde0 | 101 | __u64 domains; |
81629cba | 102 | /** allocation flags */ |
2ce9dde0 | 103 | __u64 domain_flags; |
81629cba AD |
104 | }; |
105 | ||
106 | struct drm_amdgpu_gem_create_out { | |
107 | /** returned GEM object handle */ | |
2ce9dde0 MR |
108 | __u32 handle; |
109 | __u32 _pad; | |
81629cba AD |
110 | }; |
111 | ||
112 | union drm_amdgpu_gem_create { | |
113 | struct drm_amdgpu_gem_create_in in; | |
114 | struct drm_amdgpu_gem_create_out out; | |
115 | }; | |
116 | ||
117 | /** Opcode to create new residency list. */ | |
118 | #define AMDGPU_BO_LIST_OP_CREATE 0 | |
119 | /** Opcode to destroy previously created residency list */ | |
120 | #define AMDGPU_BO_LIST_OP_DESTROY 1 | |
121 | /** Opcode to update resource information in the list */ | |
122 | #define AMDGPU_BO_LIST_OP_UPDATE 2 | |
123 | ||
124 | struct drm_amdgpu_bo_list_in { | |
125 | /** Type of operation */ | |
2ce9dde0 | 126 | __u32 operation; |
81629cba | 127 | /** Handle of list or 0 if we want to create one */ |
2ce9dde0 | 128 | __u32 list_handle; |
81629cba | 129 | /** Number of BOs in list */ |
2ce9dde0 | 130 | __u32 bo_number; |
81629cba | 131 | /** Size of each element describing BO */ |
2ce9dde0 | 132 | __u32 bo_info_size; |
81629cba | 133 | /** Pointer to array describing BOs */ |
2ce9dde0 | 134 | __u64 bo_info_ptr; |
81629cba AD |
135 | }; |
136 | ||
137 | struct drm_amdgpu_bo_list_entry { | |
138 | /** Handle of BO */ | |
2ce9dde0 | 139 | __u32 bo_handle; |
81629cba | 140 | /** New (if specified) BO priority to be used during migration */ |
2ce9dde0 | 141 | __u32 bo_priority; |
81629cba AD |
142 | }; |
143 | ||
144 | struct drm_amdgpu_bo_list_out { | |
145 | /** Handle of resource list */ | |
2ce9dde0 MR |
146 | __u32 list_handle; |
147 | __u32 _pad; | |
81629cba AD |
148 | }; |
149 | ||
150 | union drm_amdgpu_bo_list { | |
151 | struct drm_amdgpu_bo_list_in in; | |
152 | struct drm_amdgpu_bo_list_out out; | |
153 | }; | |
154 | ||
155 | /* context related */ | |
156 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 | |
157 | #define AMDGPU_CTX_OP_FREE_CTX 2 | |
158 | #define AMDGPU_CTX_OP_QUERY_STATE 3 | |
159 | ||
d94aed5a MO |
160 | /* GPU reset status */ |
161 | #define AMDGPU_CTX_NO_RESET 0 | |
675da0dd CK |
162 | /* this the context caused it */ |
163 | #define AMDGPU_CTX_GUILTY_RESET 1 | |
164 | /* some other context caused it */ | |
165 | #define AMDGPU_CTX_INNOCENT_RESET 2 | |
166 | /* unknown cause */ | |
167 | #define AMDGPU_CTX_UNKNOWN_RESET 3 | |
d94aed5a | 168 | |
81629cba | 169 | struct drm_amdgpu_ctx_in { |
675da0dd | 170 | /** AMDGPU_CTX_OP_* */ |
2ce9dde0 | 171 | __u32 op; |
675da0dd | 172 | /** For future use, no flags defined so far */ |
2ce9dde0 MR |
173 | __u32 flags; |
174 | __u32 ctx_id; | |
175 | __u32 _pad; | |
81629cba AD |
176 | }; |
177 | ||
178 | union drm_amdgpu_ctx_out { | |
179 | struct { | |
2ce9dde0 MR |
180 | __u32 ctx_id; |
181 | __u32 _pad; | |
81629cba AD |
182 | } alloc; |
183 | ||
184 | struct { | |
675da0dd | 185 | /** For future use, no flags defined so far */ |
2ce9dde0 | 186 | __u64 flags; |
d94aed5a | 187 | /** Number of resets caused by this context so far. */ |
2ce9dde0 | 188 | __u32 hangs; |
d94aed5a | 189 | /** Reset status since the last call of the ioctl. */ |
2ce9dde0 | 190 | __u32 reset_status; |
81629cba AD |
191 | } state; |
192 | }; | |
193 | ||
194 | union drm_amdgpu_ctx { | |
195 | struct drm_amdgpu_ctx_in in; | |
196 | union drm_amdgpu_ctx_out out; | |
197 | }; | |
198 | ||
cfbcacf4 CZ |
199 | /* vm ioctl */ |
200 | #define AMDGPU_VM_OP_RESERVE_VMID 1 | |
201 | #define AMDGPU_VM_OP_UNRESERVE_VMID 2 | |
202 | ||
203 | struct drm_amdgpu_vm_in { | |
204 | /** AMDGPU_VM_OP_* */ | |
205 | __u32 op; | |
206 | __u32 flags; | |
207 | }; | |
208 | ||
209 | struct drm_amdgpu_vm_out { | |
210 | /** For future use, no flags defined so far */ | |
211 | __u64 flags; | |
212 | }; | |
213 | ||
214 | union drm_amdgpu_vm { | |
215 | struct drm_amdgpu_vm_in in; | |
216 | struct drm_amdgpu_vm_out out; | |
217 | }; | |
218 | ||
81629cba AD |
219 | /* |
220 | * This is not a reliable API and you should expect it to fail for any | |
221 | * number of reasons and have fallback path that do not use userptr to | |
222 | * perform any operation. | |
223 | */ | |
224 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) | |
225 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) | |
226 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) | |
227 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) | |
228 | ||
229 | struct drm_amdgpu_gem_userptr { | |
2ce9dde0 MR |
230 | __u64 addr; |
231 | __u64 size; | |
675da0dd | 232 | /* AMDGPU_GEM_USERPTR_* */ |
2ce9dde0 | 233 | __u32 flags; |
675da0dd | 234 | /* Resulting GEM handle */ |
2ce9dde0 | 235 | __u32 handle; |
81629cba AD |
236 | }; |
237 | ||
00ac6f6b | 238 | /* SI-CI-VI: */ |
fbd76d59 MO |
239 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ |
240 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 | |
241 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf | |
242 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 | |
243 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f | |
244 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 | |
245 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 | |
246 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 | |
247 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 | |
248 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 | |
249 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 | |
250 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 | |
251 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 | |
252 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 | |
253 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 | |
254 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 | |
255 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 | |
256 | ||
00ac6f6b AD |
257 | /* GFX9 and later: */ |
258 | #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 | |
259 | #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f | |
260 | ||
261 | /* Set/Get helpers for tiling flags. */ | |
fbd76d59 | 262 | #define AMDGPU_TILING_SET(field, value) \ |
00ac6f6b | 263 | (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) |
fbd76d59 | 264 | #define AMDGPU_TILING_GET(value, field) \ |
00ac6f6b | 265 | (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) |
81629cba AD |
266 | |
267 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 | |
268 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 | |
269 | ||
270 | /** The same structure is shared for input/output */ | |
271 | struct drm_amdgpu_gem_metadata { | |
675da0dd | 272 | /** GEM Object handle */ |
2ce9dde0 | 273 | __u32 handle; |
675da0dd | 274 | /** Do we want get or set metadata */ |
2ce9dde0 | 275 | __u32 op; |
81629cba | 276 | struct { |
675da0dd | 277 | /** For future use, no flags defined so far */ |
2ce9dde0 | 278 | __u64 flags; |
675da0dd | 279 | /** family specific tiling info */ |
2ce9dde0 MR |
280 | __u64 tiling_info; |
281 | __u32 data_size_bytes; | |
282 | __u32 data[64]; | |
81629cba AD |
283 | } data; |
284 | }; | |
285 | ||
286 | struct drm_amdgpu_gem_mmap_in { | |
675da0dd | 287 | /** the GEM object handle */ |
2ce9dde0 MR |
288 | __u32 handle; |
289 | __u32 _pad; | |
81629cba AD |
290 | }; |
291 | ||
292 | struct drm_amdgpu_gem_mmap_out { | |
675da0dd | 293 | /** mmap offset from the vma offset manager */ |
2ce9dde0 | 294 | __u64 addr_ptr; |
81629cba AD |
295 | }; |
296 | ||
297 | union drm_amdgpu_gem_mmap { | |
298 | struct drm_amdgpu_gem_mmap_in in; | |
299 | struct drm_amdgpu_gem_mmap_out out; | |
300 | }; | |
301 | ||
302 | struct drm_amdgpu_gem_wait_idle_in { | |
675da0dd | 303 | /** GEM object handle */ |
2ce9dde0 | 304 | __u32 handle; |
675da0dd | 305 | /** For future use, no flags defined so far */ |
2ce9dde0 | 306 | __u32 flags; |
675da0dd | 307 | /** Absolute timeout to wait */ |
2ce9dde0 | 308 | __u64 timeout; |
81629cba AD |
309 | }; |
310 | ||
311 | struct drm_amdgpu_gem_wait_idle_out { | |
675da0dd | 312 | /** BO status: 0 - BO is idle, 1 - BO is busy */ |
2ce9dde0 | 313 | __u32 status; |
675da0dd | 314 | /** Returned current memory domain */ |
2ce9dde0 | 315 | __u32 domain; |
81629cba AD |
316 | }; |
317 | ||
318 | union drm_amdgpu_gem_wait_idle { | |
319 | struct drm_amdgpu_gem_wait_idle_in in; | |
320 | struct drm_amdgpu_gem_wait_idle_out out; | |
321 | }; | |
322 | ||
323 | struct drm_amdgpu_wait_cs_in { | |
d7b1eeb2 ML |
324 | /* Command submission handle |
325 | * handle equals 0 means none to wait for | |
080b24eb | 326 | * handle equals ~0ull means wait for the latest sequence number |
d7b1eeb2 | 327 | */ |
2ce9dde0 | 328 | __u64 handle; |
675da0dd | 329 | /** Absolute timeout to wait */ |
2ce9dde0 MR |
330 | __u64 timeout; |
331 | __u32 ip_type; | |
332 | __u32 ip_instance; | |
333 | __u32 ring; | |
334 | __u32 ctx_id; | |
81629cba AD |
335 | }; |
336 | ||
337 | struct drm_amdgpu_wait_cs_out { | |
675da0dd | 338 | /** CS status: 0 - CS completed, 1 - CS still busy */ |
2ce9dde0 | 339 | __u64 status; |
81629cba AD |
340 | }; |
341 | ||
342 | union drm_amdgpu_wait_cs { | |
343 | struct drm_amdgpu_wait_cs_in in; | |
344 | struct drm_amdgpu_wait_cs_out out; | |
345 | }; | |
346 | ||
eef18a82 JZ |
347 | struct drm_amdgpu_fence { |
348 | __u32 ctx_id; | |
349 | __u32 ip_type; | |
350 | __u32 ip_instance; | |
351 | __u32 ring; | |
352 | __u64 seq_no; | |
353 | }; | |
354 | ||
355 | struct drm_amdgpu_wait_fences_in { | |
356 | /** This points to uint64_t * which points to fences */ | |
357 | __u64 fences; | |
358 | __u32 fence_count; | |
359 | __u32 wait_all; | |
360 | __u64 timeout_ns; | |
361 | }; | |
362 | ||
363 | struct drm_amdgpu_wait_fences_out { | |
364 | __u32 status; | |
365 | __u32 first_signaled; | |
366 | }; | |
367 | ||
368 | union drm_amdgpu_wait_fences { | |
369 | struct drm_amdgpu_wait_fences_in in; | |
370 | struct drm_amdgpu_wait_fences_out out; | |
371 | }; | |
372 | ||
675da0dd CK |
373 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
374 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 | |
375 | ||
81629cba AD |
376 | /* Sets or returns a value associated with a buffer. */ |
377 | struct drm_amdgpu_gem_op { | |
675da0dd | 378 | /** GEM object handle */ |
2ce9dde0 | 379 | __u32 handle; |
675da0dd | 380 | /** AMDGPU_GEM_OP_* */ |
2ce9dde0 | 381 | __u32 op; |
675da0dd | 382 | /** Input or return value */ |
2ce9dde0 | 383 | __u64 value; |
81629cba AD |
384 | }; |
385 | ||
81629cba AD |
386 | #define AMDGPU_VA_OP_MAP 1 |
387 | #define AMDGPU_VA_OP_UNMAP 2 | |
dc54d3d1 | 388 | #define AMDGPU_VA_OP_CLEAR 3 |
80f95c57 | 389 | #define AMDGPU_VA_OP_REPLACE 4 |
81629cba | 390 | |
fc220f65 CK |
391 | /* Delay the page table update till the next CS */ |
392 | #define AMDGPU_VM_DELAY_UPDATE (1 << 0) | |
393 | ||
81629cba AD |
394 | /* Mapping flags */ |
395 | /* readable mapping */ | |
396 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) | |
397 | /* writable mapping */ | |
398 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) | |
399 | /* executable mapping, new for VI */ | |
400 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) | |
b85891bd JZ |
401 | /* partially resident texture */ |
402 | #define AMDGPU_VM_PAGE_PRT (1 << 4) | |
66e02bc3 AX |
403 | /* MTYPE flags use bit 5 to 8 */ |
404 | #define AMDGPU_VM_MTYPE_MASK (0xf << 5) | |
405 | /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ | |
406 | #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) | |
407 | /* Use NC MTYPE instead of default MTYPE */ | |
408 | #define AMDGPU_VM_MTYPE_NC (1 << 5) | |
409 | /* Use WC MTYPE instead of default MTYPE */ | |
410 | #define AMDGPU_VM_MTYPE_WC (2 << 5) | |
411 | /* Use CC MTYPE instead of default MTYPE */ | |
412 | #define AMDGPU_VM_MTYPE_CC (3 << 5) | |
413 | /* Use UC MTYPE instead of default MTYPE */ | |
414 | #define AMDGPU_VM_MTYPE_UC (4 << 5) | |
81629cba | 415 | |
34b5f6a6 | 416 | struct drm_amdgpu_gem_va { |
675da0dd | 417 | /** GEM object handle */ |
2ce9dde0 MR |
418 | __u32 handle; |
419 | __u32 _pad; | |
675da0dd | 420 | /** AMDGPU_VA_OP_* */ |
2ce9dde0 | 421 | __u32 operation; |
675da0dd | 422 | /** AMDGPU_VM_PAGE_* */ |
2ce9dde0 | 423 | __u32 flags; |
675da0dd | 424 | /** va address to assign . Must be correctly aligned.*/ |
2ce9dde0 | 425 | __u64 va_address; |
675da0dd | 426 | /** Specify offset inside of BO to assign. Must be correctly aligned.*/ |
2ce9dde0 | 427 | __u64 offset_in_bo; |
675da0dd | 428 | /** Specify mapping size. Must be correctly aligned. */ |
2ce9dde0 | 429 | __u64 map_size; |
81629cba AD |
430 | }; |
431 | ||
81629cba AD |
432 | #define AMDGPU_HW_IP_GFX 0 |
433 | #define AMDGPU_HW_IP_COMPUTE 1 | |
434 | #define AMDGPU_HW_IP_DMA 2 | |
435 | #define AMDGPU_HW_IP_UVD 3 | |
436 | #define AMDGPU_HW_IP_VCE 4 | |
a50798b6 | 437 | #define AMDGPU_HW_IP_UVD_ENC 5 |
66e236f1 | 438 | #define AMDGPU_HW_IP_VCN_DEC 6 |
fcfc5a90 LL |
439 | #define AMDGPU_HW_IP_VCN_ENC 7 |
440 | #define AMDGPU_HW_IP_NUM 8 | |
81629cba AD |
441 | |
442 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 | |
443 | ||
444 | #define AMDGPU_CHUNK_ID_IB 0x01 | |
445 | #define AMDGPU_CHUNK_ID_FENCE 0x02 | |
2b48d323 | 446 | #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 |
660e8558 DA |
447 | #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 |
448 | #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 | |
675da0dd | 449 | |
81629cba | 450 | struct drm_amdgpu_cs_chunk { |
2ce9dde0 MR |
451 | __u32 chunk_id; |
452 | __u32 length_dw; | |
453 | __u64 chunk_data; | |
81629cba AD |
454 | }; |
455 | ||
456 | struct drm_amdgpu_cs_in { | |
457 | /** Rendering context id */ | |
2ce9dde0 | 458 | __u32 ctx_id; |
81629cba | 459 | /** Handle of resource list associated with CS */ |
2ce9dde0 MR |
460 | __u32 bo_list_handle; |
461 | __u32 num_chunks; | |
462 | __u32 _pad; | |
463 | /** this points to __u64 * which point to cs chunks */ | |
464 | __u64 chunks; | |
81629cba AD |
465 | }; |
466 | ||
467 | struct drm_amdgpu_cs_out { | |
2ce9dde0 | 468 | __u64 handle; |
81629cba AD |
469 | }; |
470 | ||
471 | union drm_amdgpu_cs { | |
675da0dd CK |
472 | struct drm_amdgpu_cs_in in; |
473 | struct drm_amdgpu_cs_out out; | |
81629cba AD |
474 | }; |
475 | ||
476 | /* Specify flags to be used for IB */ | |
477 | ||
478 | /* This IB should be submitted to CE */ | |
479 | #define AMDGPU_IB_FLAG_CE (1<<0) | |
480 | ||
ed834af2 | 481 | /* Preamble flag, which means the IB could be dropped if no context switch */ |
cab6d57c | 482 | #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) |
aa2bdb24 | 483 | |
71aec257 ML |
484 | /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ |
485 | #define AMDGPU_IB_FLAG_PREEMPT (1<<2) | |
486 | ||
81629cba | 487 | struct drm_amdgpu_cs_chunk_ib { |
2ce9dde0 | 488 | __u32 _pad; |
675da0dd | 489 | /** AMDGPU_IB_FLAG_* */ |
2ce9dde0 | 490 | __u32 flags; |
675da0dd | 491 | /** Virtual address to begin IB execution */ |
2ce9dde0 | 492 | __u64 va_start; |
675da0dd | 493 | /** Size of submission */ |
2ce9dde0 | 494 | __u32 ib_bytes; |
675da0dd | 495 | /** HW IP to submit to */ |
2ce9dde0 | 496 | __u32 ip_type; |
675da0dd | 497 | /** HW IP index of the same type to submit to */ |
2ce9dde0 | 498 | __u32 ip_instance; |
675da0dd | 499 | /** Ring index to submit to */ |
2ce9dde0 | 500 | __u32 ring; |
81629cba AD |
501 | }; |
502 | ||
2b48d323 | 503 | struct drm_amdgpu_cs_chunk_dep { |
2ce9dde0 MR |
504 | __u32 ip_type; |
505 | __u32 ip_instance; | |
506 | __u32 ring; | |
507 | __u32 ctx_id; | |
508 | __u64 handle; | |
2b48d323 CK |
509 | }; |
510 | ||
81629cba | 511 | struct drm_amdgpu_cs_chunk_fence { |
2ce9dde0 MR |
512 | __u32 handle; |
513 | __u32 offset; | |
81629cba AD |
514 | }; |
515 | ||
660e8558 DA |
516 | struct drm_amdgpu_cs_chunk_sem { |
517 | __u32 handle; | |
518 | }; | |
519 | ||
7ca24cf2 MO |
520 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 |
521 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 | |
522 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 | |
523 | ||
524 | union drm_amdgpu_fence_to_handle { | |
525 | struct { | |
526 | struct drm_amdgpu_fence fence; | |
527 | __u32 what; | |
528 | } in; | |
529 | struct { | |
530 | __u32 handle; | |
531 | } out; | |
532 | }; | |
533 | ||
81629cba AD |
534 | struct drm_amdgpu_cs_chunk_data { |
535 | union { | |
536 | struct drm_amdgpu_cs_chunk_ib ib_data; | |
537 | struct drm_amdgpu_cs_chunk_fence fence_data; | |
538 | }; | |
539 | }; | |
540 | ||
541 | /** | |
542 | * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU | |
543 | * | |
544 | */ | |
545 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 | |
aafcafa0 | 546 | #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 |
81629cba AD |
547 | |
548 | /* indicate if acceleration can be working */ | |
549 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 | |
550 | /* get the crtc_id from the mode object id? */ | |
551 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 | |
552 | /* query hw IP info */ | |
553 | #define AMDGPU_INFO_HW_IP_INFO 0x02 | |
554 | /* query hw IP instance count for the specified type */ | |
555 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 | |
556 | /* timestamp for GL_ARB_timer_query */ | |
557 | #define AMDGPU_INFO_TIMESTAMP 0x05 | |
558 | /* Query the firmware version */ | |
559 | #define AMDGPU_INFO_FW_VERSION 0x0e | |
560 | /* Subquery id: Query VCE firmware version */ | |
561 | #define AMDGPU_INFO_FW_VCE 0x1 | |
562 | /* Subquery id: Query UVD firmware version */ | |
563 | #define AMDGPU_INFO_FW_UVD 0x2 | |
564 | /* Subquery id: Query GMC firmware version */ | |
565 | #define AMDGPU_INFO_FW_GMC 0x03 | |
566 | /* Subquery id: Query GFX ME firmware version */ | |
567 | #define AMDGPU_INFO_FW_GFX_ME 0x04 | |
568 | /* Subquery id: Query GFX PFP firmware version */ | |
569 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 | |
570 | /* Subquery id: Query GFX CE firmware version */ | |
571 | #define AMDGPU_INFO_FW_GFX_CE 0x06 | |
572 | /* Subquery id: Query GFX RLC firmware version */ | |
573 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 | |
574 | /* Subquery id: Query GFX MEC firmware version */ | |
575 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 | |
576 | /* Subquery id: Query SMC firmware version */ | |
577 | #define AMDGPU_INFO_FW_SMC 0x0a | |
578 | /* Subquery id: Query SDMA firmware version */ | |
579 | #define AMDGPU_INFO_FW_SDMA 0x0b | |
6a7ed07e HR |
580 | /* Subquery id: Query PSP SOS firmware version */ |
581 | #define AMDGPU_INFO_FW_SOS 0x0c | |
582 | /* Subquery id: Query PSP ASD firmware version */ | |
583 | #define AMDGPU_INFO_FW_ASD 0x0d | |
81629cba AD |
584 | /* number of bytes moved for TTM migration */ |
585 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f | |
586 | /* the used VRAM size */ | |
587 | #define AMDGPU_INFO_VRAM_USAGE 0x10 | |
588 | /* the used GTT size */ | |
589 | #define AMDGPU_INFO_GTT_USAGE 0x11 | |
590 | /* Information about GDS, etc. resource configuration */ | |
591 | #define AMDGPU_INFO_GDS_CONFIG 0x13 | |
592 | /* Query information about VRAM and GTT domains */ | |
593 | #define AMDGPU_INFO_VRAM_GTT 0x14 | |
594 | /* Query information about register in MMR address space*/ | |
595 | #define AMDGPU_INFO_READ_MMR_REG 0x15 | |
596 | /* Query information about device: rev id, family, etc. */ | |
597 | #define AMDGPU_INFO_DEV_INFO 0x16 | |
598 | /* visible vram usage */ | |
599 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 | |
83a59b63 MO |
600 | /* number of TTM buffer evictions */ |
601 | #define AMDGPU_INFO_NUM_EVICTIONS 0x18 | |
e0adf6c8 JZ |
602 | /* Query memory about VRAM and GTT domains */ |
603 | #define AMDGPU_INFO_MEMORY 0x19 | |
bbe87974 AD |
604 | /* Query vce clock table */ |
605 | #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A | |
40ee5888 EQ |
606 | /* Query vbios related information */ |
607 | #define AMDGPU_INFO_VBIOS 0x1B | |
608 | /* Subquery id: Query vbios size */ | |
609 | #define AMDGPU_INFO_VBIOS_SIZE 0x1 | |
610 | /* Subquery id: Query vbios image */ | |
611 | #define AMDGPU_INFO_VBIOS_IMAGE 0x2 | |
44879b62 AN |
612 | /* Query UVD handles */ |
613 | #define AMDGPU_INFO_NUM_HANDLES 0x1C | |
5ebbac4b AD |
614 | /* Query sensor related information */ |
615 | #define AMDGPU_INFO_SENSOR 0x1D | |
616 | /* Subquery id: Query GPU shader clock */ | |
617 | #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 | |
618 | /* Subquery id: Query GPU memory clock */ | |
619 | #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 | |
620 | /* Subquery id: Query GPU temperature */ | |
621 | #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 | |
622 | /* Subquery id: Query GPU load */ | |
623 | #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 | |
624 | /* Subquery id: Query average GPU power */ | |
625 | #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 | |
626 | /* Subquery id: Query northbridge voltage */ | |
627 | #define AMDGPU_INFO_SENSOR_VDDNB 0x6 | |
628 | /* Subquery id: Query graphics voltage */ | |
629 | #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 | |
68e2c5ff MO |
630 | /* Number of VRAM page faults on CPU access. */ |
631 | #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E | |
81629cba AD |
632 | |
633 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 | |
634 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff | |
635 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 | |
636 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff | |
637 | ||
000cab9a HR |
638 | struct drm_amdgpu_query_fw { |
639 | /** AMDGPU_INFO_FW_* */ | |
640 | __u32 fw_type; | |
641 | /** | |
642 | * Index of the IP if there are more IPs of | |
643 | * the same type. | |
644 | */ | |
645 | __u32 ip_instance; | |
646 | /** | |
647 | * Index of the engine. Whether this is used depends | |
648 | * on the firmware type. (e.g. MEC, SDMA) | |
649 | */ | |
650 | __u32 index; | |
651 | __u32 _pad; | |
652 | }; | |
653 | ||
81629cba AD |
654 | /* Input structure for the INFO ioctl */ |
655 | struct drm_amdgpu_info { | |
656 | /* Where the return value will be stored */ | |
2ce9dde0 | 657 | __u64 return_pointer; |
81629cba AD |
658 | /* The size of the return value. Just like "size" in "snprintf", |
659 | * it limits how many bytes the kernel can write. */ | |
2ce9dde0 | 660 | __u32 return_size; |
81629cba | 661 | /* The query request id. */ |
2ce9dde0 | 662 | __u32 query; |
81629cba AD |
663 | |
664 | union { | |
665 | struct { | |
2ce9dde0 MR |
666 | __u32 id; |
667 | __u32 _pad; | |
81629cba AD |
668 | } mode_crtc; |
669 | ||
670 | struct { | |
671 | /** AMDGPU_HW_IP_* */ | |
2ce9dde0 | 672 | __u32 type; |
81629cba | 673 | /** |
675da0dd CK |
674 | * Index of the IP if there are more IPs of the same |
675 | * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. | |
81629cba | 676 | */ |
2ce9dde0 | 677 | __u32 ip_instance; |
81629cba AD |
678 | } query_hw_ip; |
679 | ||
680 | struct { | |
2ce9dde0 | 681 | __u32 dword_offset; |
675da0dd | 682 | /** number of registers to read */ |
2ce9dde0 MR |
683 | __u32 count; |
684 | __u32 instance; | |
675da0dd | 685 | /** For future use, no flags defined so far */ |
2ce9dde0 | 686 | __u32 flags; |
81629cba AD |
687 | } read_mmr_reg; |
688 | ||
000cab9a | 689 | struct drm_amdgpu_query_fw query_fw; |
40ee5888 EQ |
690 | |
691 | struct { | |
692 | __u32 type; | |
693 | __u32 offset; | |
694 | } vbios_info; | |
5ebbac4b AD |
695 | |
696 | struct { | |
697 | __u32 type; | |
698 | } sensor_info; | |
81629cba AD |
699 | }; |
700 | }; | |
701 | ||
702 | struct drm_amdgpu_info_gds { | |
703 | /** GDS GFX partition size */ | |
2ce9dde0 | 704 | __u32 gds_gfx_partition_size; |
81629cba | 705 | /** GDS compute partition size */ |
2ce9dde0 | 706 | __u32 compute_partition_size; |
81629cba | 707 | /** total GDS memory size */ |
2ce9dde0 | 708 | __u32 gds_total_size; |
81629cba | 709 | /** GWS size per GFX partition */ |
2ce9dde0 | 710 | __u32 gws_per_gfx_partition; |
81629cba | 711 | /** GSW size per compute partition */ |
2ce9dde0 | 712 | __u32 gws_per_compute_partition; |
81629cba | 713 | /** OA size per GFX partition */ |
2ce9dde0 | 714 | __u32 oa_per_gfx_partition; |
81629cba | 715 | /** OA size per compute partition */ |
2ce9dde0 MR |
716 | __u32 oa_per_compute_partition; |
717 | __u32 _pad; | |
81629cba AD |
718 | }; |
719 | ||
720 | struct drm_amdgpu_info_vram_gtt { | |
2ce9dde0 MR |
721 | __u64 vram_size; |
722 | __u64 vram_cpu_accessible_size; | |
723 | __u64 gtt_size; | |
81629cba AD |
724 | }; |
725 | ||
e0adf6c8 JZ |
726 | struct drm_amdgpu_heap_info { |
727 | /** max. physical memory */ | |
728 | __u64 total_heap_size; | |
729 | ||
730 | /** Theoretical max. available memory in the given heap */ | |
731 | __u64 usable_heap_size; | |
732 | ||
733 | /** | |
734 | * Number of bytes allocated in the heap. This includes all processes | |
735 | * and private allocations in the kernel. It changes when new buffers | |
736 | * are allocated, freed, and moved. It cannot be larger than | |
737 | * heap_size. | |
738 | */ | |
739 | __u64 heap_usage; | |
740 | ||
741 | /** | |
742 | * Theoretical possible max. size of buffer which | |
743 | * could be allocated in the given heap | |
744 | */ | |
745 | __u64 max_allocation; | |
9f6163e7 JZ |
746 | }; |
747 | ||
e0adf6c8 JZ |
748 | struct drm_amdgpu_memory_info { |
749 | struct drm_amdgpu_heap_info vram; | |
750 | struct drm_amdgpu_heap_info cpu_accessible_vram; | |
751 | struct drm_amdgpu_heap_info gtt; | |
cfa32556 JZ |
752 | }; |
753 | ||
81629cba | 754 | struct drm_amdgpu_info_firmware { |
2ce9dde0 MR |
755 | __u32 ver; |
756 | __u32 feature; | |
81629cba AD |
757 | }; |
758 | ||
81c59f54 KW |
759 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
760 | #define AMDGPU_VRAM_TYPE_GDDR1 1 | |
761 | #define AMDGPU_VRAM_TYPE_DDR2 2 | |
762 | #define AMDGPU_VRAM_TYPE_GDDR3 3 | |
763 | #define AMDGPU_VRAM_TYPE_GDDR4 4 | |
764 | #define AMDGPU_VRAM_TYPE_GDDR5 5 | |
765 | #define AMDGPU_VRAM_TYPE_HBM 6 | |
766 | #define AMDGPU_VRAM_TYPE_DDR3 7 | |
767 | ||
81629cba AD |
768 | struct drm_amdgpu_info_device { |
769 | /** PCI Device ID */ | |
2ce9dde0 | 770 | __u32 device_id; |
81629cba | 771 | /** Internal chip revision: A0, A1, etc.) */ |
2ce9dde0 MR |
772 | __u32 chip_rev; |
773 | __u32 external_rev; | |
81629cba | 774 | /** Revision id in PCI Config space */ |
2ce9dde0 MR |
775 | __u32 pci_rev; |
776 | __u32 family; | |
777 | __u32 num_shader_engines; | |
778 | __u32 num_shader_arrays_per_engine; | |
675da0dd | 779 | /* in KHz */ |
2ce9dde0 MR |
780 | __u32 gpu_counter_freq; |
781 | __u64 max_engine_clock; | |
782 | __u64 max_memory_clock; | |
81629cba | 783 | /* cu information */ |
2ce9dde0 | 784 | __u32 cu_active_number; |
dbfe85ea | 785 | /* NOTE: cu_ao_mask is INVALID, DON'T use it */ |
2ce9dde0 MR |
786 | __u32 cu_ao_mask; |
787 | __u32 cu_bitmap[4][4]; | |
81629cba | 788 | /** Render backend pipe mask. One render backend is CB+DB. */ |
2ce9dde0 MR |
789 | __u32 enabled_rb_pipes_mask; |
790 | __u32 num_rb_pipes; | |
791 | __u32 num_hw_gfx_contexts; | |
792 | __u32 _pad; | |
793 | __u64 ids_flags; | |
81629cba | 794 | /** Starting virtual address for UMDs. */ |
2ce9dde0 | 795 | __u64 virtual_address_offset; |
02b70c8c | 796 | /** The maximum virtual address */ |
2ce9dde0 | 797 | __u64 virtual_address_max; |
81629cba | 798 | /** Required alignment of virtual addresses. */ |
2ce9dde0 | 799 | __u32 virtual_address_alignment; |
81629cba | 800 | /** Page table entry - fragment size */ |
2ce9dde0 MR |
801 | __u32 pte_fragment_size; |
802 | __u32 gart_page_size; | |
a101a899 | 803 | /** constant engine ram size*/ |
2ce9dde0 | 804 | __u32 ce_ram_size; |
cab6d57c | 805 | /** video memory type info*/ |
2ce9dde0 | 806 | __u32 vram_type; |
81c59f54 | 807 | /** video memory bit width*/ |
2ce9dde0 | 808 | __u32 vram_bit_width; |
fa92754e | 809 | /* vce harvesting instance */ |
2ce9dde0 | 810 | __u32 vce_harvest_config; |
df6e2c4a JZ |
811 | /* gfx double offchip LDS buffers */ |
812 | __u32 gc_double_offchip_lds_buf; | |
bce23e00 AD |
813 | /* NGG Primitive Buffer */ |
814 | __u64 prim_buf_gpu_addr; | |
815 | /* NGG Position Buffer */ | |
816 | __u64 pos_buf_gpu_addr; | |
817 | /* NGG Control Sideband */ | |
818 | __u64 cntl_sb_buf_gpu_addr; | |
819 | /* NGG Parameter Cache */ | |
820 | __u64 param_buf_gpu_addr; | |
408bfe7c JZ |
821 | __u32 prim_buf_size; |
822 | __u32 pos_buf_size; | |
823 | __u32 cntl_sb_buf_size; | |
824 | __u32 param_buf_size; | |
825 | /* wavefront size*/ | |
826 | __u32 wave_front_size; | |
827 | /* shader visible vgprs*/ | |
828 | __u32 num_shader_visible_vgprs; | |
829 | /* CU per shader array*/ | |
830 | __u32 num_cu_per_sh; | |
831 | /* number of tcc blocks*/ | |
832 | __u32 num_tcc_blocks; | |
833 | /* gs vgt table depth*/ | |
834 | __u32 gs_vgt_table_depth; | |
835 | /* gs primitive buffer depth*/ | |
836 | __u32 gs_prim_buffer_depth; | |
837 | /* max gs wavefront per vgt*/ | |
838 | __u32 max_gs_waves_per_vgt; | |
839 | __u32 _pad1; | |
dbfe85ea FC |
840 | /* always on cu bitmap */ |
841 | __u32 cu_ao_bitmap[4][4]; | |
81629cba AD |
842 | }; |
843 | ||
844 | struct drm_amdgpu_info_hw_ip { | |
845 | /** Version of h/w IP */ | |
2ce9dde0 MR |
846 | __u32 hw_ip_version_major; |
847 | __u32 hw_ip_version_minor; | |
81629cba | 848 | /** Capabilities */ |
2ce9dde0 | 849 | __u64 capabilities_flags; |
71062f43 | 850 | /** command buffer address start alignment*/ |
2ce9dde0 | 851 | __u32 ib_start_alignment; |
71062f43 | 852 | /** command buffer size alignment*/ |
2ce9dde0 | 853 | __u32 ib_size_alignment; |
81629cba | 854 | /** Bitmask of available rings. Bit 0 means ring 0, etc. */ |
2ce9dde0 MR |
855 | __u32 available_rings; |
856 | __u32 _pad; | |
81629cba AD |
857 | }; |
858 | ||
44879b62 AN |
859 | struct drm_amdgpu_info_num_handles { |
860 | /** Max handles as supported by firmware for UVD */ | |
861 | __u32 uvd_max_handles; | |
862 | /** Handles currently in use for UVD */ | |
863 | __u32 uvd_used_handles; | |
864 | }; | |
865 | ||
bbe87974 AD |
866 | #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 |
867 | ||
868 | struct drm_amdgpu_info_vce_clock_table_entry { | |
869 | /** System clock */ | |
870 | __u32 sclk; | |
871 | /** Memory clock */ | |
872 | __u32 mclk; | |
873 | /** VCE clock */ | |
874 | __u32 eclk; | |
875 | __u32 pad; | |
876 | }; | |
877 | ||
878 | struct drm_amdgpu_info_vce_clock_table { | |
879 | struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; | |
880 | __u32 num_valid_entries; | |
881 | __u32 pad; | |
882 | }; | |
883 | ||
81629cba AD |
884 | /* |
885 | * Supported GPU families | |
886 | */ | |
887 | #define AMDGPU_FAMILY_UNKNOWN 0 | |
295d0daf | 888 | #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ |
81629cba AD |
889 | #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ |
890 | #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ | |
891 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ | |
39bb0c92 | 892 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ |
a8f1f1ce | 893 | #define AMDGPU_FAMILY_AI 141 /* Vega10 */ |
2ca8a5d2 | 894 | #define AMDGPU_FAMILY_RV 142 /* Raven */ |
81629cba | 895 | |
cfa7152f EV |
896 | #if defined(__cplusplus) |
897 | } | |
898 | #endif | |
899 | ||
81629cba | 900 | #endif |