[linux-2.6-block.git] / include / uapi / drm / amdgpu_drm.h

/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
 *
 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Kevin E. Martin <martin@valinux.com>
 *    Gareth Hughes <gareth@valinux.com>
 *    Keith Whitwell <keith@tungstengraphics.com>
 */

#ifndef __AMDGPU_DRM_H__
#define __AMDGPU_DRM_H__

#include <drm/drm.h>

#define DRM_AMDGPU_GEM_CREATE		0x00
#define DRM_AMDGPU_GEM_MMAP		0x01
#define DRM_AMDGPU_CTX			0x02
#define DRM_AMDGPU_BO_LIST		0x03
#define DRM_AMDGPU_CS			0x04
#define DRM_AMDGPU_INFO			0x05
#define DRM_AMDGPU_GEM_METADATA		0x06
#define DRM_AMDGPU_GEM_WAIT_IDLE	0x07
#define DRM_AMDGPU_GEM_VA		0x08
#define DRM_AMDGPU_WAIT_CS		0x09
#define DRM_AMDGPU_GEM_OP		0x10
#define DRM_AMDGPU_GEM_USERPTR		0x11

#define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
#define DRM_IOCTL_AMDGPU_CTX		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
#define DRM_IOCTL_AMDGPU_BO_LIST	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
#define DRM_IOCTL_AMDGPU_CS		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
#define DRM_IOCTL_AMDGPU_INFO		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
#define DRM_IOCTL_AMDGPU_GEM_METADATA	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
#define DRM_IOCTL_AMDGPU_GEM_VA		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, union drm_amdgpu_gem_va)
#define DRM_IOCTL_AMDGPU_WAIT_CS	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
#define DRM_IOCTL_AMDGPU_GEM_OP		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
#define DRM_IOCTL_AMDGPU_GEM_USERPTR	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)

#define AMDGPU_GEM_DOMAIN_CPU		0x1
#define AMDGPU_GEM_DOMAIN_GTT		0x2
#define AMDGPU_GEM_DOMAIN_VRAM		0x4
#define AMDGPU_GEM_DOMAIN_GDS		0x8
#define AMDGPU_GEM_DOMAIN_GWS		0x10
#define AMDGPU_GEM_DOMAIN_OA		0x20

/* Flag that CPU access will be required for the case of VRAM domain */
#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED	(1 << 0)
/* Flag that CPU access will not work, this VRAM domain is invisible */
#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS		(1 << 1)
/* Flag that USWC attributes should be used for GTT */
#define AMDGPU_GEM_CREATE_CPU_GTT_USWC		(1 << 2)

struct drm_amdgpu_gem_create_in  {
	/** the requested memory size */
	uint64_t bo_size;
	/** physical start_addr alignment in bytes for some HW requirements */
	uint64_t alignment;
	/** the requested memory domains */
	uint64_t domains;
	/** allocation flags */
	uint64_t domain_flags;
};

struct drm_amdgpu_gem_create_out  {
	/** returned GEM object handle */
	uint32_t handle;
	uint32_t _pad;
};

union drm_amdgpu_gem_create {
	struct drm_amdgpu_gem_create_in		in;
	struct drm_amdgpu_gem_create_out	out;
};

/** Opcode to create new residency list.  */
#define AMDGPU_BO_LIST_OP_CREATE	0
/** Opcode to destroy previously created residency list */
#define AMDGPU_BO_LIST_OP_DESTROY	1
/** Opcode to update resource information in the list */
#define AMDGPU_BO_LIST_OP_UPDATE	2

struct drm_amdgpu_bo_list_in {
	/** Type of operation */
	uint32_t operation;
	/** Handle of list or 0 if we want to create one */
	uint32_t list_handle;
	/** Number of BOs in list  */
	uint32_t bo_number;
	/** Size of each element describing BO */
	uint32_t bo_info_size;
	/** Pointer to array describing BOs */
	uint64_t bo_info_ptr;
};

struct drm_amdgpu_bo_list_entry {
	/** Handle of BO */
	uint32_t bo_handle;
	/** New (if specified) BO priority to be used during migration */
	uint32_t bo_priority;
};

struct drm_amdgpu_bo_list_out {
	/** Handle of resource list  */
	uint32_t list_handle;
	uint32_t _pad;
};

union drm_amdgpu_bo_list {
	struct drm_amdgpu_bo_list_in in;
	struct drm_amdgpu_bo_list_out out;
};

/* context related */
#define AMDGPU_CTX_OP_ALLOC_CTX	1
#define AMDGPU_CTX_OP_FREE_CTX	2
#define AMDGPU_CTX_OP_QUERY_STATE	3

#define AMDGPU_CTX_OP_STATE_RUNNING	1

/* GPU reset status */
#define AMDGPU_CTX_NO_RESET		0
#define AMDGPU_CTX_GUILTY_RESET		1 /* this the context caused it */
#define AMDGPU_CTX_INNOCENT_RESET	2 /* some other context caused it */
#define AMDGPU_CTX_UNKNOWN_RESET	3 /* unknown cause */

struct drm_amdgpu_ctx_in {
	uint32_t	op;
	uint32_t	flags;
	uint32_t	ctx_id;
	uint32_t	_pad;
};

union drm_amdgpu_ctx_out {
		struct {
			uint32_t	ctx_id;
			uint32_t	_pad;
		} alloc;

		struct {
			uint64_t	flags;
			/** Number of resets caused by this context so far. */
			uint32_t	hangs;
			/** Reset status since the last call of the ioctl. */
			uint32_t	reset_status;
		} state;
};

union drm_amdgpu_ctx {
	struct drm_amdgpu_ctx_in in;
	union drm_amdgpu_ctx_out out;
};

/*
 * This is not a reliable API and you should expect it to fail for any
 * number of reasons and have fallback path that do not use userptr to
 * perform any operation.
 */
#define AMDGPU_GEM_USERPTR_READONLY	(1 << 0)
#define AMDGPU_GEM_USERPTR_ANONONLY	(1 << 1)
#define AMDGPU_GEM_USERPTR_VALIDATE	(1 << 2)
#define AMDGPU_GEM_USERPTR_REGISTER	(1 << 3)

struct drm_amdgpu_gem_userptr {
	uint64_t		addr;
	uint64_t		size;
	uint32_t		flags;
	uint32_t		handle;
};

/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
#define AMDGPU_TILING_ARRAY_MODE_SHIFT			0
#define AMDGPU_TILING_ARRAY_MODE_MASK			0xf
#define AMDGPU_TILING_PIPE_CONFIG_SHIFT			4
#define AMDGPU_TILING_PIPE_CONFIG_MASK			0x1f
#define AMDGPU_TILING_TILE_SPLIT_SHIFT			9
#define AMDGPU_TILING_TILE_SPLIT_MASK			0x7
#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT		12
#define AMDGPU_TILING_MICRO_TILE_MODE_MASK		0x7
#define AMDGPU_TILING_BANK_WIDTH_SHIFT			15
#define AMDGPU_TILING_BANK_WIDTH_MASK			0x3
#define AMDGPU_TILING_BANK_HEIGHT_SHIFT			17
#define AMDGPU_TILING_BANK_HEIGHT_MASK			0x3
#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT		19
#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK		0x3
#define AMDGPU_TILING_NUM_BANKS_SHIFT			21
#define AMDGPU_TILING_NUM_BANKS_MASK			0x3

#define AMDGPU_TILING_SET(field, value) \
	(((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
#define AMDGPU_TILING_GET(value, field) \
	(((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)

#define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
#define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2

/** The same structure is shared for input/output */
struct drm_amdgpu_gem_metadata {
	uint32_t	handle;		/* GEM Object handle */
	uint32_t	op;		/** Do we want get or set metadata */
	struct {
		uint64_t	flags;
		uint64_t	tiling_info; /* family specific tiling info */
		uint32_t	data_size_bytes;
		uint32_t	data[64];
	} data;
};

struct drm_amdgpu_gem_mmap_in {
	uint32_t handle;		/** the GEM object handle */
	uint32_t _pad;
};

struct drm_amdgpu_gem_mmap_out {
	uint64_t addr_ptr;	/** mmap offset from the vma offset manager */
};

union drm_amdgpu_gem_mmap {
	struct drm_amdgpu_gem_mmap_in   in;
	struct drm_amdgpu_gem_mmap_out out;
};

struct drm_amdgpu_gem_wait_idle_in {
	uint32_t handle;   	/* GEM object handle */
	uint32_t flags;
	uint64_t timeout; 	/* Timeout to wait. If 0 then returned immediately with the status */
};

struct drm_amdgpu_gem_wait_idle_out {
	uint32_t status;	/*   BO status:  0 - BO is idle, 1 - BO is busy */
	uint32_t domain; /*  Returned current memory domain */
};

union drm_amdgpu_gem_wait_idle {
	struct drm_amdgpu_gem_wait_idle_in  in;
	struct drm_amdgpu_gem_wait_idle_out out;
};

struct drm_amdgpu_wait_cs_in {
	uint64_t handle;
	uint64_t timeout;
	uint32_t ip_type;
	uint32_t ip_instance;
	uint32_t ring;
	uint32_t ctx_id;
};

struct drm_amdgpu_wait_cs_out {
	uint64_t status;
};

union drm_amdgpu_wait_cs {
	struct drm_amdgpu_wait_cs_in in;
	struct drm_amdgpu_wait_cs_out out;
};

/* Sets or returns a value associated with a buffer. */
struct drm_amdgpu_gem_op {
	uint32_t	handle; /* buffer */
	uint32_t	op;     /* AMDGPU_GEM_OP_* */
	uint64_t	value;  /* input or return value */
};

#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO	0
#define AMDGPU_GEM_OP_SET_PLACEMENT		1

#define AMDGPU_VA_OP_MAP			1
#define AMDGPU_VA_OP_UNMAP			2

#define AMDGPU_VA_RESULT_OK			0
#define AMDGPU_VA_RESULT_ERROR			1
#define AMDGPU_VA_RESULT_VA_INVALID_ALIGNMENT	2

/* Mapping flags */
/* readable mapping */
#define AMDGPU_VM_PAGE_READABLE		(1 << 1)
/* writable mapping */
#define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
/* executable mapping, new for VI */
#define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)

struct drm_amdgpu_gem_va_in {
	/* GEM object handle */
	uint32_t handle;
	uint32_t _pad;
	/* map or unmap*/
	uint32_t operation;
	/* specify mapping flags */
	uint32_t flags;
	/* va address to assign . Must be correctly aligned.*/
	uint64_t va_address;
	/* Specify offset inside of BO to assign. Must be correctly aligned.*/
	uint64_t offset_in_bo;
	/* Specify mapping size. If 0 and offset is 0 then map the whole BO.*/
	/* Must be correctly aligned. */
	uint64_t map_size;
};

struct drm_amdgpu_gem_va_out {
	uint32_t result;
	uint32_t _pad;
};

union drm_amdgpu_gem_va {
	struct drm_amdgpu_gem_va_in  in;
	struct drm_amdgpu_gem_va_out out;
};

#define AMDGPU_HW_IP_GFX          0
#define AMDGPU_HW_IP_COMPUTE      1
#define AMDGPU_HW_IP_DMA          2
#define AMDGPU_HW_IP_UVD          3
#define AMDGPU_HW_IP_VCE          4
#define AMDGPU_HW_IP_NUM          5

#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1

#define AMDGPU_CHUNK_ID_IB		0x01
#define AMDGPU_CHUNK_ID_FENCE		0x02
struct drm_amdgpu_cs_chunk {
	uint32_t		chunk_id;
	uint32_t		length_dw;
	uint64_t		chunk_data;
};

struct drm_amdgpu_cs_in {
	/** Rendering context id */
	uint32_t		ctx_id;
	/**  Handle of resource list associated with CS */
	uint32_t		bo_list_handle;
	uint32_t		num_chunks;
	uint32_t		_pad;
	/* this points to uint64_t * which point to cs chunks */
	uint64_t		chunks;
};

struct drm_amdgpu_cs_out {
	uint64_t handle;
};

union drm_amdgpu_cs {
       struct drm_amdgpu_cs_in in;
       struct drm_amdgpu_cs_out out;
};

/* Specify flags to be used for IB */

/* This IB should be submitted to CE */
#define AMDGPU_IB_FLAG_CE	(1<<0)

/* GDS is used by this IB */
#define AMDGPU_IB_FLAG_GDS	(1<<1)

/* CE Preamble */
#define AMDGPU_IB_FLAG_PREAMBLE (1<<2)

struct drm_amdgpu_cs_chunk_ib {
	uint32_t _pad;
	uint32_t flags;		/* IB Flags */
	uint64_t va_start;	/* Virtual address to begin IB execution */
	uint32_t ib_bytes;	/* Size of submission */
	uint32_t ip_type;	/* HW IP to submit to */
	uint32_t ip_instance;	/* HW IP index of the same type to submit to  */
	uint32_t ring;		/* Ring index to submit to */
};

struct drm_amdgpu_cs_chunk_fence {
	uint32_t handle;
	uint32_t offset;
};

struct drm_amdgpu_cs_chunk_data {
	union {
		struct drm_amdgpu_cs_chunk_ib		ib_data;
		struct drm_amdgpu_cs_chunk_fence	fence_data;
	};
};

/**
 *  Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
 *
 */
#define AMDGPU_IDS_FLAGS_FUSION         0x1

/* indicate if acceleration can be working */
#define AMDGPU_INFO_ACCEL_WORKING		0x00
/* get the crtc_id from the mode object id? */
#define AMDGPU_INFO_CRTC_FROM_ID		0x01
/* query hw IP info */
#define AMDGPU_INFO_HW_IP_INFO			0x02
/* query hw IP instance count for the specified type */
#define AMDGPU_INFO_HW_IP_COUNT			0x03
/* timestamp for GL_ARB_timer_query */
#define AMDGPU_INFO_TIMESTAMP			0x05
/* Query the firmware version */
#define AMDGPU_INFO_FW_VERSION			0x0e
	/* Subquery id: Query VCE firmware version */
	#define AMDGPU_INFO_FW_VCE		0x1
	/* Subquery id: Query UVD firmware version */
	#define AMDGPU_INFO_FW_UVD		0x2
	/* Subquery id: Query GMC firmware version */
	#define AMDGPU_INFO_FW_GMC		0x03
	/* Subquery id: Query GFX ME firmware version */
	#define AMDGPU_INFO_FW_GFX_ME		0x04
	/* Subquery id: Query GFX PFP firmware version */
	#define AMDGPU_INFO_FW_GFX_PFP		0x05
	/* Subquery id: Query GFX CE firmware version */
	#define AMDGPU_INFO_FW_GFX_CE		0x06
	/* Subquery id: Query GFX RLC firmware version */
	#define AMDGPU_INFO_FW_GFX_RLC		0x07
	/* Subquery id: Query GFX MEC firmware version */
	#define AMDGPU_INFO_FW_GFX_MEC		0x08
	/* Subquery id: Query SMC firmware version */
	#define AMDGPU_INFO_FW_SMC		0x0a
	/* Subquery id: Query SDMA firmware version */
	#define AMDGPU_INFO_FW_SDMA		0x0b
/* number of bytes moved for TTM migration */
#define AMDGPU_INFO_NUM_BYTES_MOVED		0x0f
/* the used VRAM size */
#define AMDGPU_INFO_VRAM_USAGE			0x10
/* the used GTT size */
#define AMDGPU_INFO_GTT_USAGE			0x11
/* Information about GDS, etc. resource configuration */
#define AMDGPU_INFO_GDS_CONFIG			0x13
/* Query information about VRAM and GTT domains */
#define AMDGPU_INFO_VRAM_GTT			0x14
/* Query information about register in MMR address space*/
#define AMDGPU_INFO_READ_MMR_REG		0x15
/* Query information about device: rev id, family, etc. */
#define AMDGPU_INFO_DEV_INFO			0x16
/* visible vram usage */
#define AMDGPU_INFO_VIS_VRAM_USAGE		0x17

#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff
#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT	8
#define AMDGPU_INFO_MMR_SH_INDEX_MASK	0xff

/* Input structure for the INFO ioctl */
struct drm_amdgpu_info {
	/* Where the return value will be stored */
	uint64_t return_pointer;
	/* The size of the return value. Just like "size" in "snprintf",
	 * it limits how many bytes the kernel can write. */
	uint32_t return_size;
	/* The query request id. */
	uint32_t query;

	union {
		struct {
			uint32_t id;
			uint32_t _pad;
		} mode_crtc;

		struct {
			/** AMDGPU_HW_IP_* */
			uint32_t type;
			/**
			 * Index of the IP if there are more IPs of the same type.
			 * Ignored by AMDGPU_INFO_HW_IP_COUNT.
			 */
			uint32_t ip_instance;
		} query_hw_ip;

		struct {
			uint32_t dword_offset;
			uint32_t count; /* number of registers to read */
			uint32_t instance;
			uint32_t flags;
		} read_mmr_reg;

		struct {
			/** AMDGPU_INFO_FW_* */
			uint32_t fw_type;
			/** Index of the IP if there are more IPs of the same type. */
			uint32_t ip_instance;
			/**
			 * Index of the engine. Whether this is used depends
			 * on the firmware type. (e.g. MEC, SDMA)
			 */
			uint32_t index;
			uint32_t _pad;
		} query_fw;
	};
};

struct drm_amdgpu_info_gds {
	/** GDS GFX partition size */
	uint32_t gds_gfx_partition_size;
	/** GDS compute partition size */
	uint32_t compute_partition_size;
	/** total GDS memory size */
	uint32_t gds_total_size;
	/** GWS size per GFX partition */
	uint32_t gws_per_gfx_partition;
	/** GSW size per compute partition */
	uint32_t gws_per_compute_partition;
	/** OA size per GFX partition */
	uint32_t oa_per_gfx_partition;
	/** OA size per compute partition */
	uint32_t oa_per_compute_partition;
	uint32_t _pad;
};

struct drm_amdgpu_info_vram_gtt {
	uint64_t vram_size;
	uint64_t vram_cpu_accessible_size;
	uint64_t gtt_size;
};

struct drm_amdgpu_info_firmware {
	uint32_t ver;
	uint32_t feature;
};

#define AMDGPU_VRAM_TYPE_UNKNOWN 0
#define AMDGPU_VRAM_TYPE_GDDR1 1
#define AMDGPU_VRAM_TYPE_DDR2  2
#define AMDGPU_VRAM_TYPE_GDDR3 3
#define AMDGPU_VRAM_TYPE_GDDR4 4
#define AMDGPU_VRAM_TYPE_GDDR5 5
#define AMDGPU_VRAM_TYPE_HBM   6
#define AMDGPU_VRAM_TYPE_DDR3  7

struct drm_amdgpu_info_device {
	/** PCI Device ID */
	uint32_t device_id;
	/** Internal chip revision: A0, A1, etc.) */
	uint32_t chip_rev;
	uint32_t external_rev;
	/** Revision id in PCI Config space */
	uint32_t pci_rev;
	uint32_t family;
	uint32_t num_shader_engines;
	uint32_t num_shader_arrays_per_engine;
	uint32_t gpu_counter_freq; /* in KHz */
	uint64_t max_engine_clock; /* in KHz */
	uint64_t max_memory_clock; /* in KHz */
	/* cu information */
	uint32_t cu_active_number;
	uint32_t cu_ao_mask;
	uint32_t cu_bitmap[4][4];
	/** Render backend pipe mask. One render backend is CB+DB. */
	uint32_t enabled_rb_pipes_mask;
	uint32_t num_rb_pipes;
	uint32_t num_hw_gfx_contexts;
	uint32_t _pad;
	uint64_t ids_flags;
	/** Starting virtual address for UMDs. */
	uint64_t virtual_address_offset;
	/** The maximum virtual address */
	uint64_t virtual_address_max;
	/** Required alignment of virtual addresses. */
	uint32_t virtual_address_alignment;
	/** Page table entry - fragment size */
	uint32_t pte_fragment_size;
	uint32_t gart_page_size;
	/** constant engine ram size*/
	uint32_t ce_ram_size;
	/** video memory type infro*/
	uint32_t vram_type;
	/** video memory bit width*/
	uint32_t vram_bit_width;
};

struct drm_amdgpu_info_hw_ip {
	/** Version of h/w IP */
	uint32_t  hw_ip_version_major;
	uint32_t  hw_ip_version_minor;
	/** Capabilities */
	uint64_t  capabilities_flags;
	/** command buffer address start alignment*/
	uint32_t  ib_start_alignment;
	/** command buffer size alignment*/
	uint32_t  ib_size_alignment;
	/** Bitmask of available rings. Bit 0 means ring 0, etc. */
	uint32_t  available_rings;
	uint32_t  _pad;
};

/*
 * Supported GPU families
 */
#define AMDGPU_FAMILY_UNKNOWN			0
#define AMDGPU_FAMILY_CI			120 /* Bonaire, Hawaii */
#define AMDGPU_FAMILY_KV			125 /* Kaveri, Kabini, Mullins */
#define AMDGPU_FAMILY_VI			130 /* Iceland, Tonga */
#define AMDGPU_FAMILY_CZ			135 /* Carrizo */

#endif
Commit	Line	Data
81629cba AD	1	/* amdgpu_drm.h -- Public header for the amdgpu driver -- linux-c --
	2	*
	3	* Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
	4	* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
	5	* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
	6	* Copyright 2014 Advanced Micro Devices, Inc.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the "Software"),
	10	* to deal in the Software without restriction, including without limitation
	11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	12	* and/or sell copies of the Software, and to permit persons to whom the
	13	* Software is furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	22	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	23	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	24	* OTHER DEALINGS IN THE SOFTWARE.
	25	*
	26	* Authors:
	27	* Kevin E. Martin <martin@valinux.com>
	28	* Gareth Hughes <gareth@valinux.com>
	29	* Keith Whitwell <keith@tungstengraphics.com>
	30	*/
	31
	32	#ifndef __AMDGPU_DRM_H__
	33	#define __AMDGPU_DRM_H__
	34
	35	#include <drm/drm.h>
	36
	37	#define DRM_AMDGPU_GEM_CREATE 0x00
	38	#define DRM_AMDGPU_GEM_MMAP 0x01
	39	#define DRM_AMDGPU_CTX 0x02
	40	#define DRM_AMDGPU_BO_LIST 0x03
	41	#define DRM_AMDGPU_CS 0x04
	42	#define DRM_AMDGPU_INFO 0x05
	43	#define DRM_AMDGPU_GEM_METADATA 0x06
	44	#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
	45	#define DRM_AMDGPU_GEM_VA 0x08
	46	#define DRM_AMDGPU_WAIT_CS 0x09
	47	#define DRM_AMDGPU_GEM_OP 0x10
	48	#define DRM_AMDGPU_GEM_USERPTR 0x11
	49
	50	#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
	51	#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
	52	#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
	53	#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
	54	#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
	55	#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
	56	#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
	57	#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
	58	#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, union drm_amdgpu_gem_va)
	59	#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
	60	#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
	61	#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
	62
	63	#define AMDGPU_GEM_DOMAIN_CPU 0x1
	64	#define AMDGPU_GEM_DOMAIN_GTT 0x2
65	#define AMDGPU_GEM_DOMAIN_VRAM 0x4
66	#define AMDGPU_GEM_DOMAIN_GDS 0x8
67	#define AMDGPU_GEM_DOMAIN_GWS 0x10
68	#define AMDGPU_GEM_DOMAIN_OA 0x20
69
81629cba AD	70	/* Flag that CPU access will be required for the case of VRAM domain */
	71	#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
	72	/* Flag that CPU access will not work, this VRAM domain is invisible */
	73	#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
81629cba	74	/* Flag that USWC attributes should be used for GTT */
88671288	75	#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
81629cba	76
81629cba AD	77	struct drm_amdgpu_gem_create_in {
	78	/** the requested memory size */
	79	uint64_t bo_size;
	80	/** physical start_addr alignment in bytes for some HW requirements */
	81	uint64_t alignment;
	82	/** the requested memory domains */
	83	uint64_t domains;
	84	/** allocation flags */
	85	uint64_t domain_flags;
	86	};
	87
	88	struct drm_amdgpu_gem_create_out {
	89	/** returned GEM object handle */
	90	uint32_t handle;
	91	uint32_t _pad;
	92	};
	93
	94	union drm_amdgpu_gem_create {
	95	struct drm_amdgpu_gem_create_in in;
	96	struct drm_amdgpu_gem_create_out out;
	97	};
	98
	99	/** Opcode to create new residency list. */
	100	#define AMDGPU_BO_LIST_OP_CREATE 0
	101	/** Opcode to destroy previously created residency list */
	102	#define AMDGPU_BO_LIST_OP_DESTROY 1
	103	/** Opcode to update resource information in the list */
	104	#define AMDGPU_BO_LIST_OP_UPDATE 2
	105
	106	struct drm_amdgpu_bo_list_in {
	107	/** Type of operation */
	108	uint32_t operation;
	109	/** Handle of list or 0 if we want to create one */
	110	uint32_t list_handle;
	111	/** Number of BOs in list */
	112	uint32_t bo_number;
	113	/** Size of each element describing BO */
	114	uint32_t bo_info_size;
	115	/** Pointer to array describing BOs */
	116	uint64_t bo_info_ptr;
	117	};
	118
	119	struct drm_amdgpu_bo_list_entry {
	120	/** Handle of BO */
	121	uint32_t bo_handle;
	122	/** New (if specified) BO priority to be used during migration */
	123	uint32_t bo_priority;
	124	};
	125
	126	struct drm_amdgpu_bo_list_out {
	127	/** Handle of resource list */
	128	uint32_t list_handle;
	129	uint32_t _pad;
	130	};
	131
	132	union drm_amdgpu_bo_list {
	133	struct drm_amdgpu_bo_list_in in;
	134	struct drm_amdgpu_bo_list_out out;
	135	};
	136
	137	/* context related */
	138	#define AMDGPU_CTX_OP_ALLOC_CTX 1
	139	#define AMDGPU_CTX_OP_FREE_CTX 2
	140	#define AMDGPU_CTX_OP_QUERY_STATE 3
141
142	#define AMDGPU_CTX_OP_STATE_RUNNING 1
143
d94aed5a MO	144	/* GPU reset status */
	145	#define AMDGPU_CTX_NO_RESET 0
	146	#define AMDGPU_CTX_GUILTY_RESET 1 /* this the context caused it */
	147	#define AMDGPU_CTX_INNOCENT_RESET 2 /* some other context caused it */
	148	#define AMDGPU_CTX_UNKNOWN_RESET 3 /* unknown cause */
	149
81629cba AD	150	struct drm_amdgpu_ctx_in {
	151	uint32_t op;
	152	uint32_t flags;
	153	uint32_t ctx_id;
	154	uint32_t _pad;
	155	};
	156
	157	union drm_amdgpu_ctx_out {
	158	struct {
	159	uint32_t ctx_id;
	160	uint32_t _pad;
	161	} alloc;
	162
	163	struct {
	164	uint64_t flags;
d94aed5a MO	165	/** Number of resets caused by this context so far. */
	166	uint32_t hangs;
	167	/** Reset status since the last call of the ioctl. */
	168	uint32_t reset_status;
81629cba AD	169	} state;
	170	};
	171
	172	union drm_amdgpu_ctx {
	173	struct drm_amdgpu_ctx_in in;
	174	union drm_amdgpu_ctx_out out;
	175	};
	176
	177	/*
	178	* This is not a reliable API and you should expect it to fail for any
	179	* number of reasons and have fallback path that do not use userptr to
	180	* perform any operation.
	181	*/
	182	#define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
	183	#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
	184	#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
	185	#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
	186
	187	struct drm_amdgpu_gem_userptr {
	188	uint64_t addr;
	189	uint64_t size;
	190	uint32_t flags;
	191	uint32_t handle;
	192	};
	193
fbd76d59 MO	194	/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
	195	#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
	196	#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
	197	#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
	198	#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
	199	#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
	200	#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
	201	#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
	202	#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
	203	#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
	204	#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
	205	#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
	206	#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
	207	#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
	208	#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
	209	#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
	210	#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
	211
	212	#define AMDGPU_TILING_SET(field, value) \
	213	(((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
	214	#define AMDGPU_TILING_GET(value, field) \
	215	(((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
81629cba AD	216
	217	#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
	218	#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
	219
	220	/** The same structure is shared for input/output */
	221	struct drm_amdgpu_gem_metadata {
	222	uint32_t handle; /* GEM Object handle */
	223	uint32_t op; /** Do we want get or set metadata */
	224	struct {
	225	uint64_t flags;
	226	uint64_t tiling_info; /* family specific tiling info */
	227	uint32_t data_size_bytes;
	228	uint32_t data[64];
	229	} data;
	230	};
	231
	232	struct drm_amdgpu_gem_mmap_in {
	233	uint32_t handle; /** the GEM object handle */
	234	uint32_t _pad;
	235	};
	236
	237	struct drm_amdgpu_gem_mmap_out {
	238	uint64_t addr_ptr; /** mmap offset from the vma offset manager */
	239	};
	240
	241	union drm_amdgpu_gem_mmap {
	242	struct drm_amdgpu_gem_mmap_in in;
	243	struct drm_amdgpu_gem_mmap_out out;
	244	};
	245
	246	struct drm_amdgpu_gem_wait_idle_in {
	247	uint32_t handle; /* GEM object handle */
	248	uint32_t flags;
	249	uint64_t timeout; /* Timeout to wait. If 0 then returned immediately with the status */
	250	};
	251
	252	struct drm_amdgpu_gem_wait_idle_out {
	253	uint32_t status; /* BO status: 0 - BO is idle, 1 - BO is busy */
	254	uint32_t domain; /* Returned current memory domain */
	255	};
	256
	257	union drm_amdgpu_gem_wait_idle {
	258	struct drm_amdgpu_gem_wait_idle_in in;
	259	struct drm_amdgpu_gem_wait_idle_out out;
	260	};
	261
	262	struct drm_amdgpu_wait_cs_in {
	263	uint64_t handle;
	264	uint64_t timeout;
	265	uint32_t ip_type;
	266	uint32_t ip_instance;
	267	uint32_t ring;
66b3cf2a	268	uint32_t ctx_id;
81629cba AD	269	};
	270
	271	struct drm_amdgpu_wait_cs_out {
	272	uint64_t status;
	273	};
	274
	275	union drm_amdgpu_wait_cs {
	276	struct drm_amdgpu_wait_cs_in in;
	277	struct drm_amdgpu_wait_cs_out out;
	278	};
	279
	280	/* Sets or returns a value associated with a buffer. */
	281	struct drm_amdgpu_gem_op {
	282	uint32_t handle; /* buffer */
	283	uint32_t op; /* AMDGPU_GEM_OP_* */
	284	uint64_t value; /* input or return value */
	285	};
	286
d8f65a23 MO	287	#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
d8f65a23 MO	288	#define AMDGPU_GEM_OP_SET_PLACEMENT 1
81629cba AD	289
	290	#define AMDGPU_VA_OP_MAP 1
	291	#define AMDGPU_VA_OP_UNMAP 2
	292
	293	#define AMDGPU_VA_RESULT_OK 0
	294	#define AMDGPU_VA_RESULT_ERROR 1
	295	#define AMDGPU_VA_RESULT_VA_INVALID_ALIGNMENT 2
	296
	297	/* Mapping flags */
	298	/* readable mapping */
	299	#define AMDGPU_VM_PAGE_READABLE (1 << 1)
	300	/* writable mapping */
	301	#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
	302	/* executable mapping, new for VI */
	303	#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
	304
	305	struct drm_amdgpu_gem_va_in {
	306	/* GEM object handle */
	307	uint32_t handle;
	308	uint32_t _pad;
	309	/* map or unmap*/
	310	uint32_t operation;
	311	/* specify mapping flags */
	312	uint32_t flags;
	313	/* va address to assign . Must be correctly aligned.*/
	314	uint64_t va_address;
	315	/* Specify offset inside of BO to assign. Must be correctly aligned.*/
	316	uint64_t offset_in_bo;
	317	/* Specify mapping size. If 0 and offset is 0 then map the whole BO.*/
	318	/* Must be correctly aligned. */
	319	uint64_t map_size;
	320	};
	321
	322	struct drm_amdgpu_gem_va_out {
	323	uint32_t result;
	324	uint32_t _pad;
	325	};
	326
	327	union drm_amdgpu_gem_va {
	328	struct drm_amdgpu_gem_va_in in;
	329	struct drm_amdgpu_gem_va_out out;
	330	};
	331
	332	#define AMDGPU_HW_IP_GFX 0
	333	#define AMDGPU_HW_IP_COMPUTE 1
	334	#define AMDGPU_HW_IP_DMA 2
	335	#define AMDGPU_HW_IP_UVD 3
	336	#define AMDGPU_HW_IP_VCE 4
	337	#define AMDGPU_HW_IP_NUM 5
	338
	339	#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
	340
	341	#define AMDGPU_CHUNK_ID_IB 0x01
	342	#define AMDGPU_CHUNK_ID_FENCE 0x02
	343	struct drm_amdgpu_cs_chunk {
	344	uint32_t chunk_id;
	345	uint32_t length_dw;
	346	uint64_t chunk_data;
	347	};
	348
	349	struct drm_amdgpu_cs_in {
	350	/** Rendering context id */
	351	uint32_t ctx_id;
	352	/** Handle of resource list associated with CS */
353	uint32_t bo_list_handle;
354	uint32_t num_chunks;
355	uint32_t _pad;
356	/* this points to uint64_t * which point to cs chunks */
357	uint64_t chunks;
358	};
359
360	struct drm_amdgpu_cs_out {
361	uint64_t handle;
362	};
363
364	union drm_amdgpu_cs {
365	struct drm_amdgpu_cs_in in;
366	struct drm_amdgpu_cs_out out;
367	};
368
369	/* Specify flags to be used for IB */
370
371	/* This IB should be submitted to CE */
372	#define AMDGPU_IB_FLAG_CE (1<<0)
373
374	/* GDS is used by this IB */
375	#define AMDGPU_IB_FLAG_GDS (1<<1)
376
aa2bdb24 JZ	377	/* CE Preamble */
	378	#define AMDGPU_IB_FLAG_PREAMBLE (1<<2)
	379
81629cba	380	struct drm_amdgpu_cs_chunk_ib {
3ccec53c	381	uint32_t _pad;
81629cba AD	382	uint32_t flags; /* IB Flags */
	383	uint64_t va_start; /* Virtual address to begin IB execution */
	384	uint32_t ib_bytes; /* Size of submission */
	385	uint32_t ip_type; /* HW IP to submit to */
	386	uint32_t ip_instance; /* HW IP index of the same type to submit to */
	387	uint32_t ring; /* Ring index to submit to */
	388	};
	389
	390	struct drm_amdgpu_cs_chunk_fence {
	391	uint32_t handle;
	392	uint32_t offset;
	393	};
	394
	395	struct drm_amdgpu_cs_chunk_data {
	396	union {
	397	struct drm_amdgpu_cs_chunk_ib ib_data;
	398	struct drm_amdgpu_cs_chunk_fence fence_data;
	399	};
	400	};
	401
	402	/**
	403	* Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
	404	*
	405	*/
	406	#define AMDGPU_IDS_FLAGS_FUSION 0x1
	407
	408	/* indicate if acceleration can be working */
	409	#define AMDGPU_INFO_ACCEL_WORKING 0x00
	410	/* get the crtc_id from the mode object id? */
	411	#define AMDGPU_INFO_CRTC_FROM_ID 0x01
	412	/* query hw IP info */
	413	#define AMDGPU_INFO_HW_IP_INFO 0x02
	414	/* query hw IP instance count for the specified type */
	415	#define AMDGPU_INFO_HW_IP_COUNT 0x03
	416	/* timestamp for GL_ARB_timer_query */
	417	#define AMDGPU_INFO_TIMESTAMP 0x05
	418	/* Query the firmware version */
	419	#define AMDGPU_INFO_FW_VERSION 0x0e
	420	/* Subquery id: Query VCE firmware version */
	421	#define AMDGPU_INFO_FW_VCE 0x1
	422	/* Subquery id: Query UVD firmware version */
	423	#define AMDGPU_INFO_FW_UVD 0x2
	424	/* Subquery id: Query GMC firmware version */
	425	#define AMDGPU_INFO_FW_GMC 0x03
	426	/* Subquery id: Query GFX ME firmware version */
	427	#define AMDGPU_INFO_FW_GFX_ME 0x04
	428	/* Subquery id: Query GFX PFP firmware version */
	429	#define AMDGPU_INFO_FW_GFX_PFP 0x05
	430	/* Subquery id: Query GFX CE firmware version */
	431	#define AMDGPU_INFO_FW_GFX_CE 0x06
	432	/* Subquery id: Query GFX RLC firmware version */
	433	#define AMDGPU_INFO_FW_GFX_RLC 0x07
	434	/* Subquery id: Query GFX MEC firmware version */
	435	#define AMDGPU_INFO_FW_GFX_MEC 0x08
	436	/* Subquery id: Query SMC firmware version */
	437	#define AMDGPU_INFO_FW_SMC 0x0a
	438	/* Subquery id: Query SDMA firmware version */
	439	#define AMDGPU_INFO_FW_SDMA 0x0b
	440	/* number of bytes moved for TTM migration */
	441	#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
	442	/* the used VRAM size */
	443	#define AMDGPU_INFO_VRAM_USAGE 0x10
	444	/* the used GTT size */
	445	#define AMDGPU_INFO_GTT_USAGE 0x11
446	/* Information about GDS, etc. resource configuration */
447	#define AMDGPU_INFO_GDS_CONFIG 0x13
448	/* Query information about VRAM and GTT domains */
449	#define AMDGPU_INFO_VRAM_GTT 0x14
450	/* Query information about register in MMR address space*/
451	#define AMDGPU_INFO_READ_MMR_REG 0x15
452	/* Query information about device: rev id, family, etc. */
453	#define AMDGPU_INFO_DEV_INFO 0x16
454	/* visible vram usage */
455	#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
456
457	#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
458	#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
459	#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
460	#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
461
462	/* Input structure for the INFO ioctl */
463	struct drm_amdgpu_info {
464	/* Where the return value will be stored */
465	uint64_t return_pointer;
466	/* The size of the return value. Just like "size" in "snprintf",
467	* it limits how many bytes the kernel can write. */
468	uint32_t return_size;
469	/* The query request id. */
470	uint32_t query;
471
472	union {
473	struct {
474	uint32_t id;
475	uint32_t _pad;
476	} mode_crtc;
477
478	struct {
479	/** AMDGPU_HW_IP_* */
480	uint32_t type;
481	/**
482	* Index of the IP if there are more IPs of the same type.
483	* Ignored by AMDGPU_INFO_HW_IP_COUNT.
484	*/
485	uint32_t ip_instance;
486	} query_hw_ip;
487
488	struct {
489	uint32_t dword_offset;
490	uint32_t count; /* number of registers to read */
491	uint32_t instance;
492	uint32_t flags;
493	} read_mmr_reg;
494
495	struct {
496	/** AMDGPU_INFO_FW_* */
497	uint32_t fw_type;
498	/** Index of the IP if there are more IPs of the same type. */
499	uint32_t ip_instance;
500	/**
501	* Index of the engine. Whether this is used depends
502	* on the firmware type. (e.g. MEC, SDMA)
503	*/
504	uint32_t index;
505	uint32_t _pad;
506	} query_fw;
507	};
508	};
509
510	struct drm_amdgpu_info_gds {
511	/** GDS GFX partition size */
512	uint32_t gds_gfx_partition_size;
513	/** GDS compute partition size */
514	uint32_t compute_partition_size;
515	/** total GDS memory size */
516	uint32_t gds_total_size;
517	/** GWS size per GFX partition */
518	uint32_t gws_per_gfx_partition;
519	/** GSW size per compute partition */
520	uint32_t gws_per_compute_partition;
521	/** OA size per GFX partition */
522	uint32_t oa_per_gfx_partition;
523	/** OA size per compute partition */
524	uint32_t oa_per_compute_partition;
525	uint32_t _pad;
526	};
527
528	struct drm_amdgpu_info_vram_gtt {
529	uint64_t vram_size;
530	uint64_t vram_cpu_accessible_size;
531	uint64_t gtt_size;
532	};
533
534	struct drm_amdgpu_info_firmware {
535	uint32_t ver;
536	uint32_t feature;
537	};
538
81c59f54 KW	539	#define AMDGPU_VRAM_TYPE_UNKNOWN 0
	540	#define AMDGPU_VRAM_TYPE_GDDR1 1
	541	#define AMDGPU_VRAM_TYPE_DDR2 2
	542	#define AMDGPU_VRAM_TYPE_GDDR3 3
	543	#define AMDGPU_VRAM_TYPE_GDDR4 4
	544	#define AMDGPU_VRAM_TYPE_GDDR5 5
	545	#define AMDGPU_VRAM_TYPE_HBM 6
	546	#define AMDGPU_VRAM_TYPE_DDR3 7
	547
81629cba AD	548	struct drm_amdgpu_info_device {
	549	/** PCI Device ID */
	550	uint32_t device_id;
	551	/** Internal chip revision: A0, A1, etc.) */
	552	uint32_t chip_rev;
	553	uint32_t external_rev;
	554	/** Revision id in PCI Config space */
	555	uint32_t pci_rev;
	556	uint32_t family;
	557	uint32_t num_shader_engines;
	558	uint32_t num_shader_arrays_per_engine;
	559	uint32_t gpu_counter_freq; /* in KHz */
	560	uint64_t max_engine_clock; /* in KHz */
32bf7106	561	uint64_t max_memory_clock; /* in KHz */
81629cba AD	562	/* cu information */
	563	uint32_t cu_active_number;
	564	uint32_t cu_ao_mask;
	565	uint32_t cu_bitmap[4][4];
	566	/** Render backend pipe mask. One render backend is CB+DB. */
	567	uint32_t enabled_rb_pipes_mask;
	568	uint32_t num_rb_pipes;
	569	uint32_t num_hw_gfx_contexts;
	570	uint32_t _pad;
	571	uint64_t ids_flags;
	572	/** Starting virtual address for UMDs. */
	573	uint64_t virtual_address_offset;
02b70c8c JZ	574	/** The maximum virtual address */
02b70c8c JZ	575	uint64_t virtual_address_max;
81629cba AD	576	/** Required alignment of virtual addresses. */
	577	uint32_t virtual_address_alignment;
	578	/** Page table entry - fragment size */
	579	uint32_t pte_fragment_size;
	580	uint32_t gart_page_size;
a101a899 KW	581	/** constant engine ram size*/
a101a899 KW	582	uint32_t ce_ram_size;
81c59f54 KW	583	/** video memory type infro*/
	584	uint32_t vram_type;
	585	/** video memory bit width*/
	586	uint32_t vram_bit_width;
81629cba AD	587	};
	588
	589	struct drm_amdgpu_info_hw_ip {
	590	/** Version of h/w IP */
	591	uint32_t hw_ip_version_major;
	592	uint32_t hw_ip_version_minor;
	593	/** Capabilities */
	594	uint64_t capabilities_flags;
71062f43 KW	595	/** command buffer address start alignment*/
	596	uint32_t ib_start_alignment;
	597	/** command buffer size alignment*/
	598	uint32_t ib_size_alignment;
81629cba AD	599	/** Bitmask of available rings. Bit 0 means ring 0, etc. */
	600	uint32_t available_rings;
	601	uint32_t _pad;
	602	};
	603
	604	/*
	605	* Supported GPU families
	606	*/
	607	#define AMDGPU_FAMILY_UNKNOWN 0
	608	#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
	609	#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
	610	#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
	611	#define AMDGPU_FAMILY_CZ 135 /* Carrizo */
	612
	613	#endif