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81629cba AD |
1 | /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- |
2 | * | |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. | |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. | |
6 | * Copyright 2014 Advanced Micro Devices, Inc. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
24 | * OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | * Authors: | |
27 | * Kevin E. Martin <martin@valinux.com> | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | */ | |
31 | ||
32 | #ifndef __AMDGPU_DRM_H__ | |
33 | #define __AMDGPU_DRM_H__ | |
34 | ||
b3fcf36a | 35 | #include "drm.h" |
81629cba | 36 | |
cfa7152f EV |
37 | #if defined(__cplusplus) |
38 | extern "C" { | |
39 | #endif | |
40 | ||
81629cba AD |
41 | #define DRM_AMDGPU_GEM_CREATE 0x00 |
42 | #define DRM_AMDGPU_GEM_MMAP 0x01 | |
43 | #define DRM_AMDGPU_CTX 0x02 | |
44 | #define DRM_AMDGPU_BO_LIST 0x03 | |
45 | #define DRM_AMDGPU_CS 0x04 | |
46 | #define DRM_AMDGPU_INFO 0x05 | |
47 | #define DRM_AMDGPU_GEM_METADATA 0x06 | |
48 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 | |
49 | #define DRM_AMDGPU_GEM_VA 0x08 | |
50 | #define DRM_AMDGPU_WAIT_CS 0x09 | |
51 | #define DRM_AMDGPU_GEM_OP 0x10 | |
52 | #define DRM_AMDGPU_GEM_USERPTR 0x11 | |
eef18a82 | 53 | #define DRM_AMDGPU_WAIT_FENCES 0x12 |
cfbcacf4 | 54 | #define DRM_AMDGPU_VM 0x13 |
7ca24cf2 | 55 | #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 |
52c6a62c | 56 | #define DRM_AMDGPU_SCHED 0x15 |
81629cba AD |
57 | |
58 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) | |
59 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) | |
60 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) | |
61 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) | |
62 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) | |
63 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) | |
64 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) | |
65 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) | |
34b5f6a6 | 66 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
81629cba AD |
67 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
68 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) | |
69 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) | |
eef18a82 | 70 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) |
cfbcacf4 | 71 | #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) |
7ca24cf2 | 72 | #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) |
52c6a62c | 73 | #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) |
81629cba | 74 | |
b646c1dc SL |
75 | /** |
76 | * DOC: memory domains | |
77 | * | |
78 | * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. | |
79 | * Memory in this pool could be swapped out to disk if there is pressure. | |
80 | * | |
81 | * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the | |
82 | * GPU's virtual address space via gart. Gart memory linearizes non-contiguous | |
83 | * pages of system memory, allows GPU access system memory in a linezrized | |
84 | * fashion. | |
85 | * | |
86 | * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory | |
87 | * carved out by the BIOS. | |
88 | * | |
89 | * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data | |
90 | * across shader threads. | |
91 | * | |
92 | * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the | |
93 | * execution of all the waves on a device. | |
94 | * | |
95 | * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines | |
96 | * for appending data. | |
97 | */ | |
81629cba AD |
98 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 |
99 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 | |
100 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 | |
101 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 | |
102 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 | |
103 | #define AMDGPU_GEM_DOMAIN_OA 0x20 | |
3f188453 CZ |
104 | #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ |
105 | AMDGPU_GEM_DOMAIN_GTT | \ | |
106 | AMDGPU_GEM_DOMAIN_VRAM | \ | |
107 | AMDGPU_GEM_DOMAIN_GDS | \ | |
108 | AMDGPU_GEM_DOMAIN_GWS | \ | |
109 | AMDGPU_GEM_DOMAIN_OA) | |
81629cba | 110 | |
81629cba AD |
111 | /* Flag that CPU access will be required for the case of VRAM domain */ |
112 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) | |
113 | /* Flag that CPU access will not work, this VRAM domain is invisible */ | |
114 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) | |
81629cba | 115 | /* Flag that USWC attributes should be used for GTT */ |
88671288 | 116 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
4fea83ff FC |
117 | /* Flag that the memory should be in VRAM and cleared */ |
118 | #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) | |
e7893c4b CZ |
119 | /* Flag that create shadow bo(GTT) while allocating vram bo */ |
120 | #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) | |
03f48dd5 CK |
121 | /* Flag that allocating the BO should use linear VRAM */ |
122 | #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) | |
e1eb899b CK |
123 | /* Flag that BO is always valid in this VM */ |
124 | #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) | |
177ae09b AR |
125 | /* Flag that BO sharing will be explicitly synchronized */ |
126 | #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) | |
959a2091 YZ |
127 | /* Flag that indicates allocating MQD gart on GFX9, where the mtype |
128 | * for the second page onward should be set to NC. | |
129 | */ | |
130 | #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8) | |
d8f4981e FK |
131 | /* Flag that BO may contain sensitive data that must be wiped before |
132 | * releasing the memory | |
133 | */ | |
134 | #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) | |
81629cba | 135 | |
81629cba AD |
136 | struct drm_amdgpu_gem_create_in { |
137 | /** the requested memory size */ | |
2ce9dde0 | 138 | __u64 bo_size; |
81629cba | 139 | /** physical start_addr alignment in bytes for some HW requirements */ |
2ce9dde0 | 140 | __u64 alignment; |
81629cba | 141 | /** the requested memory domains */ |
2ce9dde0 | 142 | __u64 domains; |
81629cba | 143 | /** allocation flags */ |
2ce9dde0 | 144 | __u64 domain_flags; |
81629cba AD |
145 | }; |
146 | ||
147 | struct drm_amdgpu_gem_create_out { | |
148 | /** returned GEM object handle */ | |
2ce9dde0 MR |
149 | __u32 handle; |
150 | __u32 _pad; | |
81629cba AD |
151 | }; |
152 | ||
153 | union drm_amdgpu_gem_create { | |
154 | struct drm_amdgpu_gem_create_in in; | |
155 | struct drm_amdgpu_gem_create_out out; | |
156 | }; | |
157 | ||
158 | /** Opcode to create new residency list. */ | |
159 | #define AMDGPU_BO_LIST_OP_CREATE 0 | |
160 | /** Opcode to destroy previously created residency list */ | |
161 | #define AMDGPU_BO_LIST_OP_DESTROY 1 | |
162 | /** Opcode to update resource information in the list */ | |
163 | #define AMDGPU_BO_LIST_OP_UPDATE 2 | |
164 | ||
165 | struct drm_amdgpu_bo_list_in { | |
166 | /** Type of operation */ | |
2ce9dde0 | 167 | __u32 operation; |
81629cba | 168 | /** Handle of list or 0 if we want to create one */ |
2ce9dde0 | 169 | __u32 list_handle; |
81629cba | 170 | /** Number of BOs in list */ |
2ce9dde0 | 171 | __u32 bo_number; |
81629cba | 172 | /** Size of each element describing BO */ |
2ce9dde0 | 173 | __u32 bo_info_size; |
81629cba | 174 | /** Pointer to array describing BOs */ |
2ce9dde0 | 175 | __u64 bo_info_ptr; |
81629cba AD |
176 | }; |
177 | ||
178 | struct drm_amdgpu_bo_list_entry { | |
179 | /** Handle of BO */ | |
2ce9dde0 | 180 | __u32 bo_handle; |
81629cba | 181 | /** New (if specified) BO priority to be used during migration */ |
2ce9dde0 | 182 | __u32 bo_priority; |
81629cba AD |
183 | }; |
184 | ||
185 | struct drm_amdgpu_bo_list_out { | |
186 | /** Handle of resource list */ | |
2ce9dde0 MR |
187 | __u32 list_handle; |
188 | __u32 _pad; | |
81629cba AD |
189 | }; |
190 | ||
191 | union drm_amdgpu_bo_list { | |
192 | struct drm_amdgpu_bo_list_in in; | |
193 | struct drm_amdgpu_bo_list_out out; | |
194 | }; | |
195 | ||
196 | /* context related */ | |
197 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 | |
198 | #define AMDGPU_CTX_OP_FREE_CTX 2 | |
199 | #define AMDGPU_CTX_OP_QUERY_STATE 3 | |
bc1b1bf6 | 200 | #define AMDGPU_CTX_OP_QUERY_STATE2 4 |
81629cba | 201 | |
d94aed5a MO |
202 | /* GPU reset status */ |
203 | #define AMDGPU_CTX_NO_RESET 0 | |
675da0dd CK |
204 | /* this the context caused it */ |
205 | #define AMDGPU_CTX_GUILTY_RESET 1 | |
206 | /* some other context caused it */ | |
207 | #define AMDGPU_CTX_INNOCENT_RESET 2 | |
208 | /* unknown cause */ | |
209 | #define AMDGPU_CTX_UNKNOWN_RESET 3 | |
d94aed5a | 210 | |
bc1b1bf6 ML |
211 | /* indicate gpu reset occured after ctx created */ |
212 | #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) | |
213 | /* indicate vram lost occured after ctx created */ | |
214 | #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) | |
215 | /* indicate some job from this context once cause gpu hang */ | |
216 | #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) | |
ae363a21 | 217 | /* indicate some errors are detected by RAS */ |
218 | #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) | |
219 | #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) | |
bc1b1bf6 | 220 | |
c2636dc5 | 221 | /* Context priority level */ |
f3d19bf8 | 222 | #define AMDGPU_CTX_PRIORITY_UNSET -2048 |
8bc4c256 AR |
223 | #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 |
224 | #define AMDGPU_CTX_PRIORITY_LOW -512 | |
c2636dc5 | 225 | #define AMDGPU_CTX_PRIORITY_NORMAL 0 |
cf034477 EV |
226 | /* |
227 | * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires | |
228 | * CAP_SYS_NICE or DRM_MASTER | |
229 | */ | |
8bc4c256 AR |
230 | #define AMDGPU_CTX_PRIORITY_HIGH 512 |
231 | #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 | |
c2636dc5 | 232 | |
81629cba | 233 | struct drm_amdgpu_ctx_in { |
675da0dd | 234 | /** AMDGPU_CTX_OP_* */ |
2ce9dde0 | 235 | __u32 op; |
675da0dd | 236 | /** For future use, no flags defined so far */ |
2ce9dde0 MR |
237 | __u32 flags; |
238 | __u32 ctx_id; | |
cf034477 | 239 | /** AMDGPU_CTX_PRIORITY_* */ |
c2636dc5 | 240 | __s32 priority; |
81629cba AD |
241 | }; |
242 | ||
243 | union drm_amdgpu_ctx_out { | |
244 | struct { | |
2ce9dde0 MR |
245 | __u32 ctx_id; |
246 | __u32 _pad; | |
81629cba AD |
247 | } alloc; |
248 | ||
249 | struct { | |
675da0dd | 250 | /** For future use, no flags defined so far */ |
2ce9dde0 | 251 | __u64 flags; |
d94aed5a | 252 | /** Number of resets caused by this context so far. */ |
2ce9dde0 | 253 | __u32 hangs; |
d94aed5a | 254 | /** Reset status since the last call of the ioctl. */ |
2ce9dde0 | 255 | __u32 reset_status; |
81629cba AD |
256 | } state; |
257 | }; | |
258 | ||
259 | union drm_amdgpu_ctx { | |
260 | struct drm_amdgpu_ctx_in in; | |
261 | union drm_amdgpu_ctx_out out; | |
262 | }; | |
263 | ||
cfbcacf4 CZ |
264 | /* vm ioctl */ |
265 | #define AMDGPU_VM_OP_RESERVE_VMID 1 | |
266 | #define AMDGPU_VM_OP_UNRESERVE_VMID 2 | |
267 | ||
268 | struct drm_amdgpu_vm_in { | |
269 | /** AMDGPU_VM_OP_* */ | |
270 | __u32 op; | |
271 | __u32 flags; | |
272 | }; | |
273 | ||
274 | struct drm_amdgpu_vm_out { | |
275 | /** For future use, no flags defined so far */ | |
276 | __u64 flags; | |
277 | }; | |
278 | ||
279 | union drm_amdgpu_vm { | |
280 | struct drm_amdgpu_vm_in in; | |
281 | struct drm_amdgpu_vm_out out; | |
282 | }; | |
283 | ||
52c6a62c AR |
284 | /* sched ioctl */ |
285 | #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 | |
b5bb37ed | 286 | #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 |
52c6a62c AR |
287 | |
288 | struct drm_amdgpu_sched_in { | |
289 | /* AMDGPU_SCHED_OP_* */ | |
290 | __u32 op; | |
291 | __u32 fd; | |
cf034477 | 292 | /** AMDGPU_CTX_PRIORITY_* */ |
52c6a62c | 293 | __s32 priority; |
b5bb37ed | 294 | __u32 ctx_id; |
52c6a62c AR |
295 | }; |
296 | ||
297 | union drm_amdgpu_sched { | |
298 | struct drm_amdgpu_sched_in in; | |
299 | }; | |
300 | ||
81629cba AD |
301 | /* |
302 | * This is not a reliable API and you should expect it to fail for any | |
303 | * number of reasons and have fallback path that do not use userptr to | |
304 | * perform any operation. | |
305 | */ | |
306 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) | |
307 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) | |
308 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) | |
309 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) | |
310 | ||
311 | struct drm_amdgpu_gem_userptr { | |
2ce9dde0 MR |
312 | __u64 addr; |
313 | __u64 size; | |
675da0dd | 314 | /* AMDGPU_GEM_USERPTR_* */ |
2ce9dde0 | 315 | __u32 flags; |
675da0dd | 316 | /* Resulting GEM handle */ |
2ce9dde0 | 317 | __u32 handle; |
81629cba AD |
318 | }; |
319 | ||
00ac6f6b | 320 | /* SI-CI-VI: */ |
fbd76d59 MO |
321 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ |
322 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 | |
323 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf | |
324 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 | |
325 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f | |
326 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 | |
327 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 | |
328 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 | |
329 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 | |
330 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 | |
331 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 | |
332 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 | |
333 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 | |
334 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 | |
335 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 | |
336 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 | |
337 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 | |
338 | ||
00ac6f6b AD |
339 | /* GFX9 and later: */ |
340 | #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 | |
341 | #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f | |
ce331f8f NK |
342 | #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 |
343 | #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF | |
344 | #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 | |
345 | #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF | |
346 | #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 | |
347 | #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 | |
00ac6f6b AD |
348 | |
349 | /* Set/Get helpers for tiling flags. */ | |
fbd76d59 | 350 | #define AMDGPU_TILING_SET(field, value) \ |
00ac6f6b | 351 | (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) |
fbd76d59 | 352 | #define AMDGPU_TILING_GET(value, field) \ |
00ac6f6b | 353 | (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) |
81629cba AD |
354 | |
355 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 | |
356 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 | |
357 | ||
358 | /** The same structure is shared for input/output */ | |
359 | struct drm_amdgpu_gem_metadata { | |
675da0dd | 360 | /** GEM Object handle */ |
2ce9dde0 | 361 | __u32 handle; |
675da0dd | 362 | /** Do we want get or set metadata */ |
2ce9dde0 | 363 | __u32 op; |
81629cba | 364 | struct { |
675da0dd | 365 | /** For future use, no flags defined so far */ |
2ce9dde0 | 366 | __u64 flags; |
675da0dd | 367 | /** family specific tiling info */ |
2ce9dde0 MR |
368 | __u64 tiling_info; |
369 | __u32 data_size_bytes; | |
370 | __u32 data[64]; | |
81629cba AD |
371 | } data; |
372 | }; | |
373 | ||
374 | struct drm_amdgpu_gem_mmap_in { | |
675da0dd | 375 | /** the GEM object handle */ |
2ce9dde0 MR |
376 | __u32 handle; |
377 | __u32 _pad; | |
81629cba AD |
378 | }; |
379 | ||
380 | struct drm_amdgpu_gem_mmap_out { | |
675da0dd | 381 | /** mmap offset from the vma offset manager */ |
2ce9dde0 | 382 | __u64 addr_ptr; |
81629cba AD |
383 | }; |
384 | ||
385 | union drm_amdgpu_gem_mmap { | |
386 | struct drm_amdgpu_gem_mmap_in in; | |
387 | struct drm_amdgpu_gem_mmap_out out; | |
388 | }; | |
389 | ||
390 | struct drm_amdgpu_gem_wait_idle_in { | |
675da0dd | 391 | /** GEM object handle */ |
2ce9dde0 | 392 | __u32 handle; |
675da0dd | 393 | /** For future use, no flags defined so far */ |
2ce9dde0 | 394 | __u32 flags; |
675da0dd | 395 | /** Absolute timeout to wait */ |
2ce9dde0 | 396 | __u64 timeout; |
81629cba AD |
397 | }; |
398 | ||
399 | struct drm_amdgpu_gem_wait_idle_out { | |
675da0dd | 400 | /** BO status: 0 - BO is idle, 1 - BO is busy */ |
2ce9dde0 | 401 | __u32 status; |
675da0dd | 402 | /** Returned current memory domain */ |
2ce9dde0 | 403 | __u32 domain; |
81629cba AD |
404 | }; |
405 | ||
406 | union drm_amdgpu_gem_wait_idle { | |
407 | struct drm_amdgpu_gem_wait_idle_in in; | |
408 | struct drm_amdgpu_gem_wait_idle_out out; | |
409 | }; | |
410 | ||
411 | struct drm_amdgpu_wait_cs_in { | |
d7b1eeb2 ML |
412 | /* Command submission handle |
413 | * handle equals 0 means none to wait for | |
080b24eb | 414 | * handle equals ~0ull means wait for the latest sequence number |
d7b1eeb2 | 415 | */ |
2ce9dde0 | 416 | __u64 handle; |
675da0dd | 417 | /** Absolute timeout to wait */ |
2ce9dde0 MR |
418 | __u64 timeout; |
419 | __u32 ip_type; | |
420 | __u32 ip_instance; | |
421 | __u32 ring; | |
422 | __u32 ctx_id; | |
81629cba AD |
423 | }; |
424 | ||
425 | struct drm_amdgpu_wait_cs_out { | |
675da0dd | 426 | /** CS status: 0 - CS completed, 1 - CS still busy */ |
2ce9dde0 | 427 | __u64 status; |
81629cba AD |
428 | }; |
429 | ||
430 | union drm_amdgpu_wait_cs { | |
431 | struct drm_amdgpu_wait_cs_in in; | |
432 | struct drm_amdgpu_wait_cs_out out; | |
433 | }; | |
434 | ||
eef18a82 JZ |
435 | struct drm_amdgpu_fence { |
436 | __u32 ctx_id; | |
437 | __u32 ip_type; | |
438 | __u32 ip_instance; | |
439 | __u32 ring; | |
440 | __u64 seq_no; | |
441 | }; | |
442 | ||
443 | struct drm_amdgpu_wait_fences_in { | |
444 | /** This points to uint64_t * which points to fences */ | |
445 | __u64 fences; | |
446 | __u32 fence_count; | |
447 | __u32 wait_all; | |
448 | __u64 timeout_ns; | |
449 | }; | |
450 | ||
451 | struct drm_amdgpu_wait_fences_out { | |
452 | __u32 status; | |
453 | __u32 first_signaled; | |
454 | }; | |
455 | ||
456 | union drm_amdgpu_wait_fences { | |
457 | struct drm_amdgpu_wait_fences_in in; | |
458 | struct drm_amdgpu_wait_fences_out out; | |
459 | }; | |
460 | ||
675da0dd CK |
461 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
462 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 | |
463 | ||
81629cba AD |
464 | /* Sets or returns a value associated with a buffer. */ |
465 | struct drm_amdgpu_gem_op { | |
675da0dd | 466 | /** GEM object handle */ |
2ce9dde0 | 467 | __u32 handle; |
675da0dd | 468 | /** AMDGPU_GEM_OP_* */ |
2ce9dde0 | 469 | __u32 op; |
675da0dd | 470 | /** Input or return value */ |
2ce9dde0 | 471 | __u64 value; |
81629cba AD |
472 | }; |
473 | ||
81629cba AD |
474 | #define AMDGPU_VA_OP_MAP 1 |
475 | #define AMDGPU_VA_OP_UNMAP 2 | |
dc54d3d1 | 476 | #define AMDGPU_VA_OP_CLEAR 3 |
80f95c57 | 477 | #define AMDGPU_VA_OP_REPLACE 4 |
81629cba | 478 | |
fc220f65 CK |
479 | /* Delay the page table update till the next CS */ |
480 | #define AMDGPU_VM_DELAY_UPDATE (1 << 0) | |
481 | ||
81629cba AD |
482 | /* Mapping flags */ |
483 | /* readable mapping */ | |
484 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) | |
485 | /* writable mapping */ | |
486 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) | |
487 | /* executable mapping, new for VI */ | |
488 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) | |
b85891bd JZ |
489 | /* partially resident texture */ |
490 | #define AMDGPU_VM_PAGE_PRT (1 << 4) | |
66e02bc3 AX |
491 | /* MTYPE flags use bit 5 to 8 */ |
492 | #define AMDGPU_VM_MTYPE_MASK (0xf << 5) | |
493 | /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ | |
494 | #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) | |
495 | /* Use NC MTYPE instead of default MTYPE */ | |
496 | #define AMDGPU_VM_MTYPE_NC (1 << 5) | |
497 | /* Use WC MTYPE instead of default MTYPE */ | |
498 | #define AMDGPU_VM_MTYPE_WC (2 << 5) | |
499 | /* Use CC MTYPE instead of default MTYPE */ | |
500 | #define AMDGPU_VM_MTYPE_CC (3 << 5) | |
501 | /* Use UC MTYPE instead of default MTYPE */ | |
502 | #define AMDGPU_VM_MTYPE_UC (4 << 5) | |
484deaed OZ |
503 | /* Use RW MTYPE instead of default MTYPE */ |
504 | #define AMDGPU_VM_MTYPE_RW (5 << 5) | |
81629cba | 505 | |
34b5f6a6 | 506 | struct drm_amdgpu_gem_va { |
675da0dd | 507 | /** GEM object handle */ |
2ce9dde0 MR |
508 | __u32 handle; |
509 | __u32 _pad; | |
675da0dd | 510 | /** AMDGPU_VA_OP_* */ |
2ce9dde0 | 511 | __u32 operation; |
675da0dd | 512 | /** AMDGPU_VM_PAGE_* */ |
2ce9dde0 | 513 | __u32 flags; |
675da0dd | 514 | /** va address to assign . Must be correctly aligned.*/ |
2ce9dde0 | 515 | __u64 va_address; |
675da0dd | 516 | /** Specify offset inside of BO to assign. Must be correctly aligned.*/ |
2ce9dde0 | 517 | __u64 offset_in_bo; |
675da0dd | 518 | /** Specify mapping size. Must be correctly aligned. */ |
2ce9dde0 | 519 | __u64 map_size; |
81629cba AD |
520 | }; |
521 | ||
81629cba AD |
522 | #define AMDGPU_HW_IP_GFX 0 |
523 | #define AMDGPU_HW_IP_COMPUTE 1 | |
524 | #define AMDGPU_HW_IP_DMA 2 | |
525 | #define AMDGPU_HW_IP_UVD 3 | |
526 | #define AMDGPU_HW_IP_VCE 4 | |
a50798b6 | 527 | #define AMDGPU_HW_IP_UVD_ENC 5 |
66e236f1 | 528 | #define AMDGPU_HW_IP_VCN_DEC 6 |
fcfc5a90 | 529 | #define AMDGPU_HW_IP_VCN_ENC 7 |
81d35014 BZ |
530 | #define AMDGPU_HW_IP_VCN_JPEG 8 |
531 | #define AMDGPU_HW_IP_NUM 9 | |
81629cba AD |
532 | |
533 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 | |
534 | ||
535 | #define AMDGPU_CHUNK_ID_IB 0x01 | |
536 | #define AMDGPU_CHUNK_ID_FENCE 0x02 | |
2b48d323 | 537 | #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 |
660e8558 DA |
538 | #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 |
539 | #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 | |
964d0fbf | 540 | #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 |
67dd1a36 | 541 | #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 |
2624dd15 CZ |
542 | #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 |
543 | #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 | |
675da0dd | 544 | |
81629cba | 545 | struct drm_amdgpu_cs_chunk { |
2ce9dde0 MR |
546 | __u32 chunk_id; |
547 | __u32 length_dw; | |
548 | __u64 chunk_data; | |
81629cba AD |
549 | }; |
550 | ||
551 | struct drm_amdgpu_cs_in { | |
552 | /** Rendering context id */ | |
2ce9dde0 | 553 | __u32 ctx_id; |
81629cba | 554 | /** Handle of resource list associated with CS */ |
2ce9dde0 MR |
555 | __u32 bo_list_handle; |
556 | __u32 num_chunks; | |
557 | __u32 _pad; | |
558 | /** this points to __u64 * which point to cs chunks */ | |
559 | __u64 chunks; | |
81629cba AD |
560 | }; |
561 | ||
562 | struct drm_amdgpu_cs_out { | |
2ce9dde0 | 563 | __u64 handle; |
81629cba AD |
564 | }; |
565 | ||
566 | union drm_amdgpu_cs { | |
675da0dd CK |
567 | struct drm_amdgpu_cs_in in; |
568 | struct drm_amdgpu_cs_out out; | |
81629cba AD |
569 | }; |
570 | ||
571 | /* Specify flags to be used for IB */ | |
572 | ||
573 | /* This IB should be submitted to CE */ | |
574 | #define AMDGPU_IB_FLAG_CE (1<<0) | |
575 | ||
ed834af2 | 576 | /* Preamble flag, which means the IB could be dropped if no context switch */ |
cab6d57c | 577 | #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) |
aa2bdb24 | 578 | |
71aec257 ML |
579 | /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ |
580 | #define AMDGPU_IB_FLAG_PREEMPT (1<<2) | |
581 | ||
d240cd9e MO |
582 | /* The IB fence should do the L2 writeback but not invalidate any shader |
583 | * caches (L2/vL1/sL1/I$). */ | |
584 | #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) | |
585 | ||
41cca166 MO |
586 | /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. |
587 | * This will reset wave ID counters for the IB. | |
588 | */ | |
589 | #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) | |
590 | ||
81629cba | 591 | struct drm_amdgpu_cs_chunk_ib { |
2ce9dde0 | 592 | __u32 _pad; |
675da0dd | 593 | /** AMDGPU_IB_FLAG_* */ |
2ce9dde0 | 594 | __u32 flags; |
675da0dd | 595 | /** Virtual address to begin IB execution */ |
2ce9dde0 | 596 | __u64 va_start; |
675da0dd | 597 | /** Size of submission */ |
2ce9dde0 | 598 | __u32 ib_bytes; |
675da0dd | 599 | /** HW IP to submit to */ |
2ce9dde0 | 600 | __u32 ip_type; |
675da0dd | 601 | /** HW IP index of the same type to submit to */ |
2ce9dde0 | 602 | __u32 ip_instance; |
675da0dd | 603 | /** Ring index to submit to */ |
2ce9dde0 | 604 | __u32 ring; |
81629cba AD |
605 | }; |
606 | ||
2b48d323 | 607 | struct drm_amdgpu_cs_chunk_dep { |
2ce9dde0 MR |
608 | __u32 ip_type; |
609 | __u32 ip_instance; | |
610 | __u32 ring; | |
611 | __u32 ctx_id; | |
612 | __u64 handle; | |
2b48d323 CK |
613 | }; |
614 | ||
81629cba | 615 | struct drm_amdgpu_cs_chunk_fence { |
2ce9dde0 MR |
616 | __u32 handle; |
617 | __u32 offset; | |
81629cba AD |
618 | }; |
619 | ||
660e8558 DA |
620 | struct drm_amdgpu_cs_chunk_sem { |
621 | __u32 handle; | |
622 | }; | |
623 | ||
2624dd15 CZ |
624 | struct drm_amdgpu_cs_chunk_syncobj { |
625 | __u32 handle; | |
626 | __u32 flags; | |
627 | __u64 point; | |
628 | }; | |
629 | ||
7ca24cf2 MO |
630 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 |
631 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 | |
632 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 | |
633 | ||
634 | union drm_amdgpu_fence_to_handle { | |
635 | struct { | |
636 | struct drm_amdgpu_fence fence; | |
637 | __u32 what; | |
56e0349f | 638 | __u32 pad; |
7ca24cf2 MO |
639 | } in; |
640 | struct { | |
641 | __u32 handle; | |
642 | } out; | |
643 | }; | |
644 | ||
81629cba AD |
645 | struct drm_amdgpu_cs_chunk_data { |
646 | union { | |
647 | struct drm_amdgpu_cs_chunk_ib ib_data; | |
648 | struct drm_amdgpu_cs_chunk_fence fence_data; | |
649 | }; | |
650 | }; | |
651 | ||
652 | /** | |
653 | * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU | |
654 | * | |
655 | */ | |
656 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 | |
aafcafa0 | 657 | #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 |
81629cba AD |
658 | |
659 | /* indicate if acceleration can be working */ | |
660 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 | |
661 | /* get the crtc_id from the mode object id? */ | |
662 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 | |
663 | /* query hw IP info */ | |
664 | #define AMDGPU_INFO_HW_IP_INFO 0x02 | |
665 | /* query hw IP instance count for the specified type */ | |
666 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 | |
667 | /* timestamp for GL_ARB_timer_query */ | |
668 | #define AMDGPU_INFO_TIMESTAMP 0x05 | |
669 | /* Query the firmware version */ | |
670 | #define AMDGPU_INFO_FW_VERSION 0x0e | |
671 | /* Subquery id: Query VCE firmware version */ | |
672 | #define AMDGPU_INFO_FW_VCE 0x1 | |
673 | /* Subquery id: Query UVD firmware version */ | |
674 | #define AMDGPU_INFO_FW_UVD 0x2 | |
675 | /* Subquery id: Query GMC firmware version */ | |
676 | #define AMDGPU_INFO_FW_GMC 0x03 | |
677 | /* Subquery id: Query GFX ME firmware version */ | |
678 | #define AMDGPU_INFO_FW_GFX_ME 0x04 | |
679 | /* Subquery id: Query GFX PFP firmware version */ | |
680 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 | |
681 | /* Subquery id: Query GFX CE firmware version */ | |
682 | #define AMDGPU_INFO_FW_GFX_CE 0x06 | |
683 | /* Subquery id: Query GFX RLC firmware version */ | |
684 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 | |
685 | /* Subquery id: Query GFX MEC firmware version */ | |
686 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 | |
687 | /* Subquery id: Query SMC firmware version */ | |
688 | #define AMDGPU_INFO_FW_SMC 0x0a | |
689 | /* Subquery id: Query SDMA firmware version */ | |
690 | #define AMDGPU_INFO_FW_SDMA 0x0b | |
6a7ed07e HR |
691 | /* Subquery id: Query PSP SOS firmware version */ |
692 | #define AMDGPU_INFO_FW_SOS 0x0c | |
693 | /* Subquery id: Query PSP ASD firmware version */ | |
694 | #define AMDGPU_INFO_FW_ASD 0x0d | |
3ac952b1 AD |
695 | /* Subquery id: Query VCN firmware version */ |
696 | #define AMDGPU_INFO_FW_VCN 0x0e | |
621a6318 HR |
697 | /* Subquery id: Query GFX RLC SRLC firmware version */ |
698 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f | |
699 | /* Subquery id: Query GFX RLC SRLG firmware version */ | |
700 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 | |
701 | /* Subquery id: Query GFX RLC SRLS firmware version */ | |
702 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 | |
4d11b4b2 DF |
703 | /* Subquery id: Query DMCU firmware version */ |
704 | #define AMDGPU_INFO_FW_DMCU 0x12 | |
9b9ca62d | 705 | #define AMDGPU_INFO_FW_TA 0x13 |
81629cba AD |
706 | /* number of bytes moved for TTM migration */ |
707 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f | |
708 | /* the used VRAM size */ | |
709 | #define AMDGPU_INFO_VRAM_USAGE 0x10 | |
710 | /* the used GTT size */ | |
711 | #define AMDGPU_INFO_GTT_USAGE 0x11 | |
712 | /* Information about GDS, etc. resource configuration */ | |
713 | #define AMDGPU_INFO_GDS_CONFIG 0x13 | |
714 | /* Query information about VRAM and GTT domains */ | |
715 | #define AMDGPU_INFO_VRAM_GTT 0x14 | |
716 | /* Query information about register in MMR address space*/ | |
717 | #define AMDGPU_INFO_READ_MMR_REG 0x15 | |
718 | /* Query information about device: rev id, family, etc. */ | |
719 | #define AMDGPU_INFO_DEV_INFO 0x16 | |
720 | /* visible vram usage */ | |
721 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 | |
83a59b63 MO |
722 | /* number of TTM buffer evictions */ |
723 | #define AMDGPU_INFO_NUM_EVICTIONS 0x18 | |
e0adf6c8 JZ |
724 | /* Query memory about VRAM and GTT domains */ |
725 | #define AMDGPU_INFO_MEMORY 0x19 | |
bbe87974 AD |
726 | /* Query vce clock table */ |
727 | #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A | |
40ee5888 EQ |
728 | /* Query vbios related information */ |
729 | #define AMDGPU_INFO_VBIOS 0x1B | |
730 | /* Subquery id: Query vbios size */ | |
731 | #define AMDGPU_INFO_VBIOS_SIZE 0x1 | |
732 | /* Subquery id: Query vbios image */ | |
733 | #define AMDGPU_INFO_VBIOS_IMAGE 0x2 | |
44879b62 AN |
734 | /* Query UVD handles */ |
735 | #define AMDGPU_INFO_NUM_HANDLES 0x1C | |
5ebbac4b AD |
736 | /* Query sensor related information */ |
737 | #define AMDGPU_INFO_SENSOR 0x1D | |
738 | /* Subquery id: Query GPU shader clock */ | |
739 | #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 | |
740 | /* Subquery id: Query GPU memory clock */ | |
741 | #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 | |
742 | /* Subquery id: Query GPU temperature */ | |
743 | #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 | |
744 | /* Subquery id: Query GPU load */ | |
745 | #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 | |
746 | /* Subquery id: Query average GPU power */ | |
747 | #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 | |
748 | /* Subquery id: Query northbridge voltage */ | |
749 | #define AMDGPU_INFO_SENSOR_VDDNB 0x6 | |
750 | /* Subquery id: Query graphics voltage */ | |
751 | #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 | |
60bbade2 RZ |
752 | /* Subquery id: Query GPU stable pstate shader clock */ |
753 | #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 | |
754 | /* Subquery id: Query GPU stable pstate memory clock */ | |
755 | #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 | |
68e2c5ff MO |
756 | /* Number of VRAM page faults on CPU access. */ |
757 | #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E | |
1f7251b7 | 758 | #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F |
5cb77114 | 759 | /* query ras mask of enabled features*/ |
760 | #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 | |
761 | ||
762 | /* RAS MASK: UMC (VRAM) */ | |
763 | #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) | |
764 | /* RAS MASK: SDMA */ | |
765 | #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) | |
766 | /* RAS MASK: GFX */ | |
767 | #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) | |
768 | /* RAS MASK: MMHUB */ | |
769 | #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) | |
770 | /* RAS MASK: ATHUB */ | |
771 | #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) | |
772 | /* RAS MASK: PCIE */ | |
773 | #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) | |
774 | /* RAS MASK: HDP */ | |
775 | #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) | |
776 | /* RAS MASK: XGMI */ | |
777 | #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) | |
778 | /* RAS MASK: DF */ | |
779 | #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) | |
780 | /* RAS MASK: SMN */ | |
781 | #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) | |
782 | /* RAS MASK: SEM */ | |
783 | #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) | |
784 | /* RAS MASK: MP0 */ | |
785 | #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) | |
786 | /* RAS MASK: MP1 */ | |
787 | #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) | |
788 | /* RAS MASK: FUSE */ | |
789 | #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) | |
81629cba AD |
790 | |
791 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 | |
792 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff | |
793 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 | |
794 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff | |
795 | ||
000cab9a HR |
796 | struct drm_amdgpu_query_fw { |
797 | /** AMDGPU_INFO_FW_* */ | |
798 | __u32 fw_type; | |
799 | /** | |
800 | * Index of the IP if there are more IPs of | |
801 | * the same type. | |
802 | */ | |
803 | __u32 ip_instance; | |
804 | /** | |
805 | * Index of the engine. Whether this is used depends | |
806 | * on the firmware type. (e.g. MEC, SDMA) | |
807 | */ | |
808 | __u32 index; | |
809 | __u32 _pad; | |
810 | }; | |
811 | ||
81629cba AD |
812 | /* Input structure for the INFO ioctl */ |
813 | struct drm_amdgpu_info { | |
814 | /* Where the return value will be stored */ | |
2ce9dde0 | 815 | __u64 return_pointer; |
81629cba AD |
816 | /* The size of the return value. Just like "size" in "snprintf", |
817 | * it limits how many bytes the kernel can write. */ | |
2ce9dde0 | 818 | __u32 return_size; |
81629cba | 819 | /* The query request id. */ |
2ce9dde0 | 820 | __u32 query; |
81629cba AD |
821 | |
822 | union { | |
823 | struct { | |
2ce9dde0 MR |
824 | __u32 id; |
825 | __u32 _pad; | |
81629cba AD |
826 | } mode_crtc; |
827 | ||
828 | struct { | |
829 | /** AMDGPU_HW_IP_* */ | |
2ce9dde0 | 830 | __u32 type; |
81629cba | 831 | /** |
675da0dd CK |
832 | * Index of the IP if there are more IPs of the same |
833 | * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. | |
81629cba | 834 | */ |
2ce9dde0 | 835 | __u32 ip_instance; |
81629cba AD |
836 | } query_hw_ip; |
837 | ||
838 | struct { | |
2ce9dde0 | 839 | __u32 dword_offset; |
675da0dd | 840 | /** number of registers to read */ |
2ce9dde0 MR |
841 | __u32 count; |
842 | __u32 instance; | |
675da0dd | 843 | /** For future use, no flags defined so far */ |
2ce9dde0 | 844 | __u32 flags; |
81629cba AD |
845 | } read_mmr_reg; |
846 | ||
000cab9a | 847 | struct drm_amdgpu_query_fw query_fw; |
40ee5888 EQ |
848 | |
849 | struct { | |
850 | __u32 type; | |
851 | __u32 offset; | |
852 | } vbios_info; | |
5ebbac4b AD |
853 | |
854 | struct { | |
855 | __u32 type; | |
856 | } sensor_info; | |
81629cba AD |
857 | }; |
858 | }; | |
859 | ||
860 | struct drm_amdgpu_info_gds { | |
861 | /** GDS GFX partition size */ | |
2ce9dde0 | 862 | __u32 gds_gfx_partition_size; |
81629cba | 863 | /** GDS compute partition size */ |
2ce9dde0 | 864 | __u32 compute_partition_size; |
81629cba | 865 | /** total GDS memory size */ |
2ce9dde0 | 866 | __u32 gds_total_size; |
81629cba | 867 | /** GWS size per GFX partition */ |
2ce9dde0 | 868 | __u32 gws_per_gfx_partition; |
81629cba | 869 | /** GSW size per compute partition */ |
2ce9dde0 | 870 | __u32 gws_per_compute_partition; |
81629cba | 871 | /** OA size per GFX partition */ |
2ce9dde0 | 872 | __u32 oa_per_gfx_partition; |
81629cba | 873 | /** OA size per compute partition */ |
2ce9dde0 MR |
874 | __u32 oa_per_compute_partition; |
875 | __u32 _pad; | |
81629cba AD |
876 | }; |
877 | ||
878 | struct drm_amdgpu_info_vram_gtt { | |
2ce9dde0 MR |
879 | __u64 vram_size; |
880 | __u64 vram_cpu_accessible_size; | |
881 | __u64 gtt_size; | |
81629cba AD |
882 | }; |
883 | ||
e0adf6c8 JZ |
884 | struct drm_amdgpu_heap_info { |
885 | /** max. physical memory */ | |
886 | __u64 total_heap_size; | |
887 | ||
888 | /** Theoretical max. available memory in the given heap */ | |
889 | __u64 usable_heap_size; | |
890 | ||
891 | /** | |
892 | * Number of bytes allocated in the heap. This includes all processes | |
893 | * and private allocations in the kernel. It changes when new buffers | |
894 | * are allocated, freed, and moved. It cannot be larger than | |
895 | * heap_size. | |
896 | */ | |
897 | __u64 heap_usage; | |
898 | ||
899 | /** | |
900 | * Theoretical possible max. size of buffer which | |
901 | * could be allocated in the given heap | |
902 | */ | |
903 | __u64 max_allocation; | |
9f6163e7 JZ |
904 | }; |
905 | ||
e0adf6c8 JZ |
906 | struct drm_amdgpu_memory_info { |
907 | struct drm_amdgpu_heap_info vram; | |
908 | struct drm_amdgpu_heap_info cpu_accessible_vram; | |
909 | struct drm_amdgpu_heap_info gtt; | |
cfa32556 JZ |
910 | }; |
911 | ||
81629cba | 912 | struct drm_amdgpu_info_firmware { |
2ce9dde0 MR |
913 | __u32 ver; |
914 | __u32 feature; | |
81629cba AD |
915 | }; |
916 | ||
81c59f54 KW |
917 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
918 | #define AMDGPU_VRAM_TYPE_GDDR1 1 | |
919 | #define AMDGPU_VRAM_TYPE_DDR2 2 | |
920 | #define AMDGPU_VRAM_TYPE_GDDR3 3 | |
921 | #define AMDGPU_VRAM_TYPE_GDDR4 4 | |
922 | #define AMDGPU_VRAM_TYPE_GDDR5 5 | |
923 | #define AMDGPU_VRAM_TYPE_HBM 6 | |
924 | #define AMDGPU_VRAM_TYPE_DDR3 7 | |
1e09b053 | 925 | #define AMDGPU_VRAM_TYPE_DDR4 8 |
d67383e6 | 926 | #define AMDGPU_VRAM_TYPE_GDDR6 9 |
81c59f54 | 927 | |
81629cba AD |
928 | struct drm_amdgpu_info_device { |
929 | /** PCI Device ID */ | |
2ce9dde0 | 930 | __u32 device_id; |
81629cba | 931 | /** Internal chip revision: A0, A1, etc.) */ |
2ce9dde0 MR |
932 | __u32 chip_rev; |
933 | __u32 external_rev; | |
81629cba | 934 | /** Revision id in PCI Config space */ |
2ce9dde0 MR |
935 | __u32 pci_rev; |
936 | __u32 family; | |
937 | __u32 num_shader_engines; | |
938 | __u32 num_shader_arrays_per_engine; | |
675da0dd | 939 | /* in KHz */ |
2ce9dde0 MR |
940 | __u32 gpu_counter_freq; |
941 | __u64 max_engine_clock; | |
942 | __u64 max_memory_clock; | |
81629cba | 943 | /* cu information */ |
2ce9dde0 | 944 | __u32 cu_active_number; |
dbfe85ea | 945 | /* NOTE: cu_ao_mask is INVALID, DON'T use it */ |
2ce9dde0 MR |
946 | __u32 cu_ao_mask; |
947 | __u32 cu_bitmap[4][4]; | |
81629cba | 948 | /** Render backend pipe mask. One render backend is CB+DB. */ |
2ce9dde0 MR |
949 | __u32 enabled_rb_pipes_mask; |
950 | __u32 num_rb_pipes; | |
951 | __u32 num_hw_gfx_contexts; | |
952 | __u32 _pad; | |
953 | __u64 ids_flags; | |
81629cba | 954 | /** Starting virtual address for UMDs. */ |
2ce9dde0 | 955 | __u64 virtual_address_offset; |
02b70c8c | 956 | /** The maximum virtual address */ |
2ce9dde0 | 957 | __u64 virtual_address_max; |
81629cba | 958 | /** Required alignment of virtual addresses. */ |
2ce9dde0 | 959 | __u32 virtual_address_alignment; |
81629cba | 960 | /** Page table entry - fragment size */ |
2ce9dde0 MR |
961 | __u32 pte_fragment_size; |
962 | __u32 gart_page_size; | |
a101a899 | 963 | /** constant engine ram size*/ |
2ce9dde0 | 964 | __u32 ce_ram_size; |
cab6d57c | 965 | /** video memory type info*/ |
2ce9dde0 | 966 | __u32 vram_type; |
81c59f54 | 967 | /** video memory bit width*/ |
2ce9dde0 | 968 | __u32 vram_bit_width; |
fa92754e | 969 | /* vce harvesting instance */ |
2ce9dde0 | 970 | __u32 vce_harvest_config; |
df6e2c4a JZ |
971 | /* gfx double offchip LDS buffers */ |
972 | __u32 gc_double_offchip_lds_buf; | |
bce23e00 AD |
973 | /* NGG Primitive Buffer */ |
974 | __u64 prim_buf_gpu_addr; | |
975 | /* NGG Position Buffer */ | |
976 | __u64 pos_buf_gpu_addr; | |
977 | /* NGG Control Sideband */ | |
978 | __u64 cntl_sb_buf_gpu_addr; | |
979 | /* NGG Parameter Cache */ | |
980 | __u64 param_buf_gpu_addr; | |
408bfe7c JZ |
981 | __u32 prim_buf_size; |
982 | __u32 pos_buf_size; | |
983 | __u32 cntl_sb_buf_size; | |
984 | __u32 param_buf_size; | |
985 | /* wavefront size*/ | |
986 | __u32 wave_front_size; | |
987 | /* shader visible vgprs*/ | |
988 | __u32 num_shader_visible_vgprs; | |
989 | /* CU per shader array*/ | |
990 | __u32 num_cu_per_sh; | |
991 | /* number of tcc blocks*/ | |
992 | __u32 num_tcc_blocks; | |
993 | /* gs vgt table depth*/ | |
994 | __u32 gs_vgt_table_depth; | |
995 | /* gs primitive buffer depth*/ | |
996 | __u32 gs_prim_buffer_depth; | |
997 | /* max gs wavefront per vgt*/ | |
998 | __u32 max_gs_waves_per_vgt; | |
999 | __u32 _pad1; | |
dbfe85ea FC |
1000 | /* always on cu bitmap */ |
1001 | __u32 cu_ao_bitmap[4][4]; | |
5b565e0e CK |
1002 | /** Starting high virtual address for UMDs. */ |
1003 | __u64 high_va_offset; | |
1004 | /** The maximum high virtual address */ | |
1005 | __u64 high_va_max; | |
22e96fa6 HZ |
1006 | /* gfx10 pa_sc_tile_steering_override */ |
1007 | __u32 pa_sc_tile_steering_override; | |
cf21e76a MO |
1008 | /* disabled TCCs */ |
1009 | __u64 tcc_disabled_mask; | |
81629cba AD |
1010 | }; |
1011 | ||
1012 | struct drm_amdgpu_info_hw_ip { | |
1013 | /** Version of h/w IP */ | |
2ce9dde0 MR |
1014 | __u32 hw_ip_version_major; |
1015 | __u32 hw_ip_version_minor; | |
81629cba | 1016 | /** Capabilities */ |
2ce9dde0 | 1017 | __u64 capabilities_flags; |
71062f43 | 1018 | /** command buffer address start alignment*/ |
2ce9dde0 | 1019 | __u32 ib_start_alignment; |
71062f43 | 1020 | /** command buffer size alignment*/ |
2ce9dde0 | 1021 | __u32 ib_size_alignment; |
81629cba | 1022 | /** Bitmask of available rings. Bit 0 means ring 0, etc. */ |
2ce9dde0 MR |
1023 | __u32 available_rings; |
1024 | __u32 _pad; | |
81629cba AD |
1025 | }; |
1026 | ||
44879b62 AN |
1027 | struct drm_amdgpu_info_num_handles { |
1028 | /** Max handles as supported by firmware for UVD */ | |
1029 | __u32 uvd_max_handles; | |
1030 | /** Handles currently in use for UVD */ | |
1031 | __u32 uvd_used_handles; | |
1032 | }; | |
1033 | ||
bbe87974 AD |
1034 | #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 |
1035 | ||
1036 | struct drm_amdgpu_info_vce_clock_table_entry { | |
1037 | /** System clock */ | |
1038 | __u32 sclk; | |
1039 | /** Memory clock */ | |
1040 | __u32 mclk; | |
1041 | /** VCE clock */ | |
1042 | __u32 eclk; | |
1043 | __u32 pad; | |
1044 | }; | |
1045 | ||
1046 | struct drm_amdgpu_info_vce_clock_table { | |
1047 | struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; | |
1048 | __u32 num_valid_entries; | |
1049 | __u32 pad; | |
1050 | }; | |
1051 | ||
81629cba AD |
1052 | /* |
1053 | * Supported GPU families | |
1054 | */ | |
1055 | #define AMDGPU_FAMILY_UNKNOWN 0 | |
295d0daf | 1056 | #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ |
81629cba AD |
1057 | #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ |
1058 | #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ | |
1059 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ | |
39bb0c92 | 1060 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ |
a8f1f1ce | 1061 | #define AMDGPU_FAMILY_AI 141 /* Vega10 */ |
2ca8a5d2 | 1062 | #define AMDGPU_FAMILY_RV 142 /* Raven */ |
107c34bc | 1063 | #define AMDGPU_FAMILY_NV 143 /* Navi10 */ |
81629cba | 1064 | |
cfa7152f EV |
1065 | #if defined(__cplusplus) |
1066 | } | |
1067 | #endif | |
1068 | ||
81629cba | 1069 | #endif |