[linux-2.6-block.git] / include / linux / nvme.h

/*
 * Definitions for the NVM Express interface
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _LINUX_NVME_H
#define _LINUX_NVME_H

#include <linux/types.h>

enum {
	NVME_REG_CAP	= 0x0000,	/* Controller Capabilities */
	NVME_REG_VS	= 0x0008,	/* Version */
	NVME_REG_INTMS	= 0x000c,	/* Interrupt Mask Set */
	NVME_REG_INTMC	= 0x0010,	/* Interrupt Mask Clear */
	NVME_REG_CC	= 0x0014,	/* Controller Configuration */
	NVME_REG_CSTS	= 0x001c,	/* Controller Status */
	NVME_REG_NSSR	= 0x0020,	/* NVM Subsystem Reset */
	NVME_REG_AQA	= 0x0024,	/* Admin Queue Attributes */
	NVME_REG_ASQ	= 0x0028,	/* Admin SQ Base Address */
	NVME_REG_ACQ	= 0x0030,	/* Admin CQ Base Address */
	NVME_REG_CMBLOC = 0x0038,	/* Controller Memory Buffer Location */
	NVME_REG_CMBSZ	= 0x003c,	/* Controller Memory Buffer Size */
};

#define NVME_CAP_MQES(cap)	((cap) & 0xffff)
#define NVME_CAP_TIMEOUT(cap)	(((cap) >> 24) & 0xff)
#define NVME_CAP_STRIDE(cap)	(((cap) >> 32) & 0xf)
#define NVME_CAP_NSSRC(cap)	(((cap) >> 36) & 0x1)
#define NVME_CAP_MPSMIN(cap)	(((cap) >> 48) & 0xf)
#define NVME_CAP_MPSMAX(cap)	(((cap) >> 52) & 0xf)

#define NVME_CMB_BIR(cmbloc)	((cmbloc) & 0x7)
#define NVME_CMB_OFST(cmbloc)	(((cmbloc) >> 12) & 0xfffff)
#define NVME_CMB_SZ(cmbsz)	(((cmbsz) >> 12) & 0xfffff)
#define NVME_CMB_SZU(cmbsz)	(((cmbsz) >> 8) & 0xf)

#define NVME_CMB_WDS(cmbsz)	((cmbsz) & 0x10)
#define NVME_CMB_RDS(cmbsz)	((cmbsz) & 0x8)
#define NVME_CMB_LISTS(cmbsz)	((cmbsz) & 0x4)
#define NVME_CMB_CQS(cmbsz)	((cmbsz) & 0x2)
#define NVME_CMB_SQS(cmbsz)	((cmbsz) & 0x1)

/*
 * Submission and Completion Queue Entry Sizes for the NVM command set.
 * (In bytes and specified as a power of two (2^n)).
 */
#define NVME_NVM_IOSQES		6
#define NVME_NVM_IOCQES		4

enum {
	NVME_CC_ENABLE		= 1 << 0,
	NVME_CC_CSS_NVM		= 0 << 4,
	NVME_CC_MPS_SHIFT	= 7,
	NVME_CC_ARB_RR		= 0 << 11,
	NVME_CC_ARB_WRRU	= 1 << 11,
	NVME_CC_ARB_VS		= 7 << 11,
	NVME_CC_SHN_NONE	= 0 << 14,
	NVME_CC_SHN_NORMAL	= 1 << 14,
	NVME_CC_SHN_ABRUPT	= 2 << 14,
	NVME_CC_SHN_MASK	= 3 << 14,
	NVME_CC_IOSQES		= NVME_NVM_IOSQES << 16,
	NVME_CC_IOCQES		= NVME_NVM_IOCQES << 20,
	NVME_CSTS_RDY		= 1 << 0,
	NVME_CSTS_CFS		= 1 << 1,
	NVME_CSTS_NSSRO		= 1 << 4,
	NVME_CSTS_SHST_NORMAL	= 0 << 2,
	NVME_CSTS_SHST_OCCUR	= 1 << 2,
	NVME_CSTS_SHST_CMPLT	= 2 << 2,
	NVME_CSTS_SHST_MASK	= 3 << 2,
};

struct nvme_id_power_state {
	__le16			max_power;	/* centiwatts */
	__u8			rsvd2;
	__u8			flags;
	__le32			entry_lat;	/* microseconds */
	__le32			exit_lat;	/* microseconds */
	__u8			read_tput;
	__u8			read_lat;
	__u8			write_tput;
	__u8			write_lat;
	__le16			idle_power;
	__u8			idle_scale;
	__u8			rsvd19;
	__le16			active_power;
	__u8			active_work_scale;
	__u8			rsvd23[9];
};

enum {
	NVME_PS_FLAGS_MAX_POWER_SCALE	= 1 << 0,
	NVME_PS_FLAGS_NON_OP_STATE	= 1 << 1,
};

struct nvme_id_ctrl {
	__le16			vid;
	__le16			ssvid;
	char			sn[20];
	char			mn[40];
	char			fr[8];
	__u8			rab;
	__u8			ieee[3];
	__u8			mic;
	__u8			mdts;
	__le16			cntlid;
	__le32			ver;
	__le32			rtd3r;
	__le32			rtd3e;
	__le32			oaes;
	__u8			rsvd96[160];
	__le16			oacs;
	__u8			acl;
	__u8			aerl;
	__u8			frmw;
	__u8			lpa;
	__u8			elpe;
	__u8			npss;
	__u8			avscc;
	__u8			apsta;
	__le16			wctemp;
	__le16			cctemp;
	__u8			rsvd270[242];
	__u8			sqes;
	__u8			cqes;
	__u8			rsvd514[2];
	__le32			nn;
	__le16			oncs;
	__le16			fuses;
	__u8			fna;
	__u8			vwc;
	__le16			awun;
	__le16			awupf;
	__u8			nvscc;
	__u8			rsvd531;
	__le16			acwu;
	__u8			rsvd534[2];
	__le32			sgls;
	__u8			rsvd540[1508];
	struct nvme_id_power_state	psd[32];
	__u8			vs[1024];
};

enum {
	NVME_CTRL_ONCS_COMPARE			= 1 << 0,
	NVME_CTRL_ONCS_WRITE_UNCORRECTABLE	= 1 << 1,
	NVME_CTRL_ONCS_DSM			= 1 << 2,
	NVME_CTRL_VWC_PRESENT			= 1 << 0,
};

struct nvme_lbaf {
	__le16			ms;
	__u8			ds;
	__u8			rp;
};

struct nvme_id_ns {
	__le64			nsze;
	__le64			ncap;
	__le64			nuse;
	__u8			nsfeat;
	__u8			nlbaf;
	__u8			flbas;
	__u8			mc;
	__u8			dpc;
	__u8			dps;
	__u8			nmic;
	__u8			rescap;
	__u8			fpi;
	__u8			rsvd33;
	__le16			nawun;
	__le16			nawupf;
	__le16			nacwu;
	__le16			nabsn;
	__le16			nabo;
	__le16			nabspf;
	__u16			rsvd46;
	__le64			nvmcap[2];
	__u8			rsvd64[40];
	__u8			nguid[16];
	__u8			eui64[8];
	struct nvme_lbaf	lbaf[16];
	__u8			rsvd192[192];
	__u8			vs[3712];
};

enum {
	NVME_NS_FEAT_THIN	= 1 << 0,
	NVME_NS_FLBAS_LBA_MASK	= 0xf,
	NVME_NS_FLBAS_META_EXT	= 0x10,
	NVME_LBAF_RP_BEST	= 0,
	NVME_LBAF_RP_BETTER	= 1,
	NVME_LBAF_RP_GOOD	= 2,
	NVME_LBAF_RP_DEGRADED	= 3,
	NVME_NS_DPC_PI_LAST	= 1 << 4,
	NVME_NS_DPC_PI_FIRST	= 1 << 3,
	NVME_NS_DPC_PI_TYPE3	= 1 << 2,
	NVME_NS_DPC_PI_TYPE2	= 1 << 1,
	NVME_NS_DPC_PI_TYPE1	= 1 << 0,
	NVME_NS_DPS_PI_FIRST	= 1 << 3,
	NVME_NS_DPS_PI_MASK	= 0x7,
	NVME_NS_DPS_PI_TYPE1	= 1,
	NVME_NS_DPS_PI_TYPE2	= 2,
	NVME_NS_DPS_PI_TYPE3	= 3,
};

struct nvme_smart_log {
	__u8			critical_warning;
	__u8			temperature[2];
	__u8			avail_spare;
	__u8			spare_thresh;
	__u8			percent_used;
	__u8			rsvd6[26];
	__u8			data_units_read[16];
	__u8			data_units_written[16];
	__u8			host_reads[16];
	__u8			host_writes[16];
	__u8			ctrl_busy_time[16];
	__u8			power_cycles[16];
	__u8			power_on_hours[16];
	__u8			unsafe_shutdowns[16];
	__u8			media_errors[16];
	__u8			num_err_log_entries[16];
	__le32			warning_temp_time;
	__le32			critical_comp_time;
	__le16			temp_sensor[8];
	__u8			rsvd216[296];
};

enum {
	NVME_SMART_CRIT_SPARE		= 1 << 0,
	NVME_SMART_CRIT_TEMPERATURE	= 1 << 1,
	NVME_SMART_CRIT_RELIABILITY	= 1 << 2,
	NVME_SMART_CRIT_MEDIA		= 1 << 3,
	NVME_SMART_CRIT_VOLATILE_MEMORY	= 1 << 4,
};

enum {
	NVME_AER_NOTICE_NS_CHANGED	= 0x0002,
};

struct nvme_lba_range_type {
	__u8			type;
	__u8			attributes;
	__u8			rsvd2[14];
	__u64			slba;
	__u64			nlb;
	__u8			guid[16];
	__u8			rsvd48[16];
};

enum {
	NVME_LBART_TYPE_FS	= 0x01,
	NVME_LBART_TYPE_RAID	= 0x02,
	NVME_LBART_TYPE_CACHE	= 0x03,
	NVME_LBART_TYPE_SWAP	= 0x04,

	NVME_LBART_ATTRIB_TEMP	= 1 << 0,
	NVME_LBART_ATTRIB_HIDE	= 1 << 1,
};

struct nvme_reservation_status {
	__le32	gen;
	__u8	rtype;
	__u8	regctl[2];
	__u8	resv5[2];
	__u8	ptpls;
	__u8	resv10[13];
	struct {
		__le16	cntlid;
		__u8	rcsts;
		__u8	resv3[5];
		__le64	hostid;
		__le64	rkey;
	} regctl_ds[];
};

enum nvme_async_event_type {
	NVME_AER_TYPE_ERROR	= 0,
	NVME_AER_TYPE_SMART	= 1,
	NVME_AER_TYPE_NOTICE	= 2,
};

/* I/O commands */

enum nvme_opcode {
	nvme_cmd_flush		= 0x00,
	nvme_cmd_write		= 0x01,
	nvme_cmd_read		= 0x02,
	nvme_cmd_write_uncor	= 0x04,
	nvme_cmd_compare	= 0x05,
	nvme_cmd_write_zeroes	= 0x08,
	nvme_cmd_dsm		= 0x09,
	nvme_cmd_resv_register	= 0x0d,
	nvme_cmd_resv_report	= 0x0e,
	nvme_cmd_resv_acquire	= 0x11,
	nvme_cmd_resv_release	= 0x15,
};

struct nvme_common_command {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__le32			cdw2[2];
	__le64			metadata;
	__le64			prp1;
	__le64			prp2;
	__le32			cdw10[6];
};

struct nvme_rw_command {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2;
	__le64			metadata;
	__le64			prp1;
	__le64			prp2;
	__le64			slba;
	__le16			length;
	__le16			control;
	__le32			dsmgmt;
	__le32			reftag;
	__le16			apptag;
	__le16			appmask;
};

enum {
	NVME_RW_LR			= 1 << 15,
	NVME_RW_FUA			= 1 << 14,
	NVME_RW_DSM_FREQ_UNSPEC		= 0,
	NVME_RW_DSM_FREQ_TYPICAL	= 1,
	NVME_RW_DSM_FREQ_RARE		= 2,
	NVME_RW_DSM_FREQ_READS		= 3,
	NVME_RW_DSM_FREQ_WRITES		= 4,
	NVME_RW_DSM_FREQ_RW		= 5,
	NVME_RW_DSM_FREQ_ONCE		= 6,
	NVME_RW_DSM_FREQ_PREFETCH	= 7,
	NVME_RW_DSM_FREQ_TEMP		= 8,
	NVME_RW_DSM_LATENCY_NONE	= 0 << 4,
	NVME_RW_DSM_LATENCY_IDLE	= 1 << 4,
	NVME_RW_DSM_LATENCY_NORM	= 2 << 4,
	NVME_RW_DSM_LATENCY_LOW		= 3 << 4,
	NVME_RW_DSM_SEQ_REQ		= 1 << 6,
	NVME_RW_DSM_COMPRESSED		= 1 << 7,
	NVME_RW_PRINFO_PRCHK_REF	= 1 << 10,
	NVME_RW_PRINFO_PRCHK_APP	= 1 << 11,
	NVME_RW_PRINFO_PRCHK_GUARD	= 1 << 12,
	NVME_RW_PRINFO_PRACT		= 1 << 13,
};

struct nvme_dsm_cmd {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[2];
	__le64			prp1;
	__le64			prp2;
	__le32			nr;
	__le32			attributes;
	__u32			rsvd12[4];
};

enum {
	NVME_DSMGMT_IDR		= 1 << 0,
	NVME_DSMGMT_IDW		= 1 << 1,
	NVME_DSMGMT_AD		= 1 << 2,
};

struct nvme_dsm_range {
	__le32			cattr;
	__le32			nlb;
	__le64			slba;
};

/* Admin commands */

enum nvme_admin_opcode {
	nvme_admin_delete_sq		= 0x00,
	nvme_admin_create_sq		= 0x01,
	nvme_admin_get_log_page		= 0x02,
	nvme_admin_delete_cq		= 0x04,
	nvme_admin_create_cq		= 0x05,
	nvme_admin_identify		= 0x06,
	nvme_admin_abort_cmd		= 0x08,
	nvme_admin_set_features		= 0x09,
	nvme_admin_get_features		= 0x0a,
	nvme_admin_async_event		= 0x0c,
	nvme_admin_activate_fw		= 0x10,
	nvme_admin_download_fw		= 0x11,
	nvme_admin_format_nvm		= 0x80,
	nvme_admin_security_send	= 0x81,
	nvme_admin_security_recv	= 0x82,
};

enum {
	NVME_QUEUE_PHYS_CONTIG	= (1 << 0),
	NVME_CQ_IRQ_ENABLED	= (1 << 1),
	NVME_SQ_PRIO_URGENT	= (0 << 1),
	NVME_SQ_PRIO_HIGH	= (1 << 1),
	NVME_SQ_PRIO_MEDIUM	= (2 << 1),
	NVME_SQ_PRIO_LOW	= (3 << 1),
	NVME_FEAT_ARBITRATION	= 0x01,
	NVME_FEAT_POWER_MGMT	= 0x02,
	NVME_FEAT_LBA_RANGE	= 0x03,
	NVME_FEAT_TEMP_THRESH	= 0x04,
	NVME_FEAT_ERR_RECOVERY	= 0x05,
	NVME_FEAT_VOLATILE_WC	= 0x06,
	NVME_FEAT_NUM_QUEUES	= 0x07,
	NVME_FEAT_IRQ_COALESCE	= 0x08,
	NVME_FEAT_IRQ_CONFIG	= 0x09,
	NVME_FEAT_WRITE_ATOMIC	= 0x0a,
	NVME_FEAT_ASYNC_EVENT	= 0x0b,
	NVME_FEAT_AUTO_PST	= 0x0c,
	NVME_FEAT_SW_PROGRESS	= 0x80,
	NVME_FEAT_HOST_ID	= 0x81,
	NVME_FEAT_RESV_MASK	= 0x82,
	NVME_FEAT_RESV_PERSIST	= 0x83,
	NVME_LOG_ERROR		= 0x01,
	NVME_LOG_SMART		= 0x02,
	NVME_LOG_FW_SLOT	= 0x03,
	NVME_LOG_RESERVATION	= 0x80,
	NVME_FWACT_REPL		= (0 << 3),
	NVME_FWACT_REPL_ACTV	= (1 << 3),
	NVME_FWACT_ACTV		= (2 << 3),
};

struct nvme_identify {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[2];
	__le64			prp1;
	__le64			prp2;
	__le32			cns;
	__u32			rsvd11[5];
};

struct nvme_features {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[2];
	__le64			prp1;
	__le64			prp2;
	__le32			fid;
	__le32			dword11;
	__u32			rsvd12[4];
};

struct nvme_create_cq {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[5];
	__le64			prp1;
	__u64			rsvd8;
	__le16			cqid;
	__le16			qsize;
	__le16			cq_flags;
	__le16			irq_vector;
	__u32			rsvd12[4];
};

struct nvme_create_sq {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[5];
	__le64			prp1;
	__u64			rsvd8;
	__le16			sqid;
	__le16			qsize;
	__le16			sq_flags;
	__le16			cqid;
	__u32			rsvd12[4];
};

struct nvme_delete_queue {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[9];
	__le16			qid;
	__u16			rsvd10;
	__u32			rsvd11[5];
};

struct nvme_abort_cmd {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[9];
	__le16			sqid;
	__u16			cid;
	__u32			rsvd11[5];
};

struct nvme_download_firmware {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[5];
	__le64			prp1;
	__le64			prp2;
	__le32			numd;
	__le32			offset;
	__u32			rsvd12[4];
};

struct nvme_format_cmd {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[4];
	__le32			cdw10;
	__u32			rsvd11[5];
};

struct nvme_get_log_page_command {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[2];
	__le64			prp1;
	__le64			prp2;
	__u8			lid;
	__u8			rsvd10;
	__le16			numdl;
	__le16			numdu;
	__u16			rsvd11;
	__le32			lpol;
	__le32			lpou;
	__u32			rsvd14[2];
};

struct nvme_command {
	union {
		struct nvme_common_command common;
		struct nvme_rw_command rw;
		struct nvme_identify identify;
		struct nvme_features features;
		struct nvme_create_cq create_cq;
		struct nvme_create_sq create_sq;
		struct nvme_delete_queue delete_queue;
		struct nvme_download_firmware dlfw;
		struct nvme_format_cmd format;
		struct nvme_dsm_cmd dsm;
		struct nvme_abort_cmd abort;
		struct nvme_get_log_page_command get_log_page;
	};
};

enum {
	NVME_SC_SUCCESS			= 0x0,
	NVME_SC_INVALID_OPCODE		= 0x1,
	NVME_SC_INVALID_FIELD		= 0x2,
	NVME_SC_CMDID_CONFLICT		= 0x3,
	NVME_SC_DATA_XFER_ERROR		= 0x4,
	NVME_SC_POWER_LOSS		= 0x5,
	NVME_SC_INTERNAL		= 0x6,
	NVME_SC_ABORT_REQ		= 0x7,
	NVME_SC_ABORT_QUEUE		= 0x8,
	NVME_SC_FUSED_FAIL		= 0x9,
	NVME_SC_FUSED_MISSING		= 0xa,
	NVME_SC_INVALID_NS		= 0xb,
	NVME_SC_CMD_SEQ_ERROR		= 0xc,
	NVME_SC_SGL_INVALID_LAST	= 0xd,
	NVME_SC_SGL_INVALID_COUNT	= 0xe,
	NVME_SC_SGL_INVALID_DATA	= 0xf,
	NVME_SC_SGL_INVALID_METADATA	= 0x10,
	NVME_SC_SGL_INVALID_TYPE	= 0x11,
	NVME_SC_LBA_RANGE		= 0x80,
	NVME_SC_CAP_EXCEEDED		= 0x81,
	NVME_SC_NS_NOT_READY		= 0x82,
	NVME_SC_RESERVATION_CONFLICT	= 0x83,
	NVME_SC_CQ_INVALID		= 0x100,
	NVME_SC_QID_INVALID		= 0x101,
	NVME_SC_QUEUE_SIZE		= 0x102,
	NVME_SC_ABORT_LIMIT		= 0x103,
	NVME_SC_ABORT_MISSING		= 0x104,
	NVME_SC_ASYNC_LIMIT		= 0x105,
	NVME_SC_FIRMWARE_SLOT		= 0x106,
	NVME_SC_FIRMWARE_IMAGE		= 0x107,
	NVME_SC_INVALID_VECTOR		= 0x108,
	NVME_SC_INVALID_LOG_PAGE	= 0x109,
	NVME_SC_INVALID_FORMAT		= 0x10a,
	NVME_SC_FIRMWARE_NEEDS_RESET	= 0x10b,
	NVME_SC_INVALID_QUEUE		= 0x10c,
	NVME_SC_FEATURE_NOT_SAVEABLE	= 0x10d,
	NVME_SC_FEATURE_NOT_CHANGEABLE	= 0x10e,
	NVME_SC_FEATURE_NOT_PER_NS	= 0x10f,
	NVME_SC_FW_NEEDS_RESET_SUBSYS	= 0x110,
	NVME_SC_BAD_ATTRIBUTES		= 0x180,
	NVME_SC_INVALID_PI		= 0x181,
	NVME_SC_READ_ONLY		= 0x182,
	NVME_SC_WRITE_FAULT		= 0x280,
	NVME_SC_READ_ERROR		= 0x281,
	NVME_SC_GUARD_CHECK		= 0x282,
	NVME_SC_APPTAG_CHECK		= 0x283,
	NVME_SC_REFTAG_CHECK		= 0x284,
	NVME_SC_COMPARE_FAILED		= 0x285,
	NVME_SC_ACCESS_DENIED		= 0x286,
	NVME_SC_DNR			= 0x4000,
};

struct nvme_completion {
	__le32	result;		/* Used by admin commands to return data */
	__u32	rsvd;
	__le16	sq_head;	/* how much of this queue may be reclaimed */
	__le16	sq_id;		/* submission queue that generated this entry */
	__u16	command_id;	/* of the command which completed */
	__le16	status;		/* did the command fail, and if so, why? */
};

#define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8))

#endif /* _LINUX_NVME_H */
Commit	Line	Data
b60503ba MW	1	/*
b60503ba MW	2	* Definitions for the NVM Express interface
8757ad65	3	* Copyright (c) 2011-2014, Intel Corporation.
b60503ba MW	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
b60503ba MW	13	*/
	14
	15	#ifndef _LINUX_NVME_H
	16	#define _LINUX_NVME_H
	17
2812dfe3 CH	18	#include <linux/types.h>
2812dfe3 CH	19
7a67cbea CH	20	enum {
	21	NVME_REG_CAP = 0x0000, /* Controller Capabilities */
	22	NVME_REG_VS = 0x0008, /* Version */
	23	NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
a5b714ad	24	NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
7a67cbea CH	25	NVME_REG_CC = 0x0014, /* Controller Configuration */
	26	NVME_REG_CSTS = 0x001c, /* Controller Status */
	27	NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
	28	NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
	29	NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
a5b714ad	30	NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
7a67cbea CH	31	NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
7a67cbea CH	32	NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
b60503ba MW	33	};
b60503ba MW	34
a0cadb85	35	#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
22605f96	36	#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e	37	#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
dfbac8c7	38	#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
8fc23e03	39	#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
1d090624	40	#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
22605f96	41
8ffaadf7 JD	42	#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
	43	#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
	44	#define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
	45	#define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
	46
	47	#define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
	48	#define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
	49	#define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
	50	#define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
	51	#define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
	52
69cd27e2 CH	53	/*
	54	* Submission and Completion Queue Entry Sizes for the NVM command set.
	55	* (In bytes and specified as a power of two (2^n)).
	56	*/
	57	#define NVME_NVM_IOSQES 6
	58	#define NVME_NVM_IOCQES 4
	59
b60503ba MW	60	enum {
	61	NVME_CC_ENABLE = 1 << 0,
	62	NVME_CC_CSS_NVM = 0 << 4,
	63	NVME_CC_MPS_SHIFT = 7,
	64	NVME_CC_ARB_RR = 0 << 11,
	65	NVME_CC_ARB_WRRU = 1 << 11,
7f53f9d2 MW	66	NVME_CC_ARB_VS = 7 << 11,
	67	NVME_CC_SHN_NONE = 0 << 14,
	68	NVME_CC_SHN_NORMAL = 1 << 14,
	69	NVME_CC_SHN_ABRUPT = 2 << 14,
1894d8f1	70	NVME_CC_SHN_MASK = 3 << 14,
69cd27e2 CH	71	NVME_CC_IOSQES = NVME_NVM_IOSQES << 16,
69cd27e2 CH	72	NVME_CC_IOCQES = NVME_NVM_IOCQES << 20,
b60503ba MW	73	NVME_CSTS_RDY = 1 << 0,
b60503ba MW	74	NVME_CSTS_CFS = 1 << 1,
dfbac8c7	75	NVME_CSTS_NSSRO = 1 << 4,
b60503ba MW	76	NVME_CSTS_SHST_NORMAL = 0 << 2,
	77	NVME_CSTS_SHST_OCCUR = 1 << 2,
	78	NVME_CSTS_SHST_CMPLT = 2 << 2,
1894d8f1	79	NVME_CSTS_SHST_MASK = 3 << 2,
b60503ba MW	80	};
b60503ba MW	81
9d99a8dd CH	82	struct nvme_id_power_state {
	83	__le16 max_power; /* centiwatts */
	84	__u8 rsvd2;
	85	__u8 flags;
	86	__le32 entry_lat; /* microseconds */
	87	__le32 exit_lat; /* microseconds */
	88	__u8 read_tput;
	89	__u8 read_lat;
	90	__u8 write_tput;
	91	__u8 write_lat;
	92	__le16 idle_power;
	93	__u8 idle_scale;
	94	__u8 rsvd19;
	95	__le16 active_power;
	96	__u8 active_work_scale;
	97	__u8 rsvd23[9];
	98	};
	99
	100	enum {
	101	NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
	102	NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
	103	};
	104
	105	struct nvme_id_ctrl {
	106	__le16 vid;
	107	__le16 ssvid;
	108	char sn[20];
	109	char mn[40];
	110	char fr[8];
	111	__u8 rab;
	112	__u8 ieee[3];
	113	__u8 mic;
	114	__u8 mdts;
08c69640 CH	115	__le16 cntlid;
08c69640 CH	116	__le32 ver;
14e974a8 CH	117	__le32 rtd3r;
	118	__le32 rtd3e;
	119	__le32 oaes;
	120	__u8 rsvd96[160];
9d99a8dd CH	121	__le16 oacs;
	122	__u8 acl;
	123	__u8 aerl;
	124	__u8 frmw;
	125	__u8 lpa;
	126	__u8 elpe;
	127	__u8 npss;
	128	__u8 avscc;
	129	__u8 apsta;
	130	__le16 wctemp;
	131	__le16 cctemp;
	132	__u8 rsvd270[242];
	133	__u8 sqes;
	134	__u8 cqes;
	135	__u8 rsvd514[2];
	136	__le32 nn;
	137	__le16 oncs;
	138	__le16 fuses;
	139	__u8 fna;
	140	__u8 vwc;
	141	__le16 awun;
	142	__le16 awupf;
	143	__u8 nvscc;
	144	__u8 rsvd531;
	145	__le16 acwu;
	146	__u8 rsvd534[2];
	147	__le32 sgls;
	148	__u8 rsvd540[1508];
	149	struct nvme_id_power_state psd[32];
	150	__u8 vs[1024];
	151	};
	152
	153	enum {
	154	NVME_CTRL_ONCS_COMPARE = 1 << 0,
	155	NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
	156	NVME_CTRL_ONCS_DSM = 1 << 2,
	157	NVME_CTRL_VWC_PRESENT = 1 << 0,
	158	};
	159
	160	struct nvme_lbaf {
	161	__le16 ms;
	162	__u8 ds;
	163	__u8 rp;
	164	};
	165
	166	struct nvme_id_ns {
	167	__le64 nsze;
	168	__le64 ncap;
	169	__le64 nuse;
	170	__u8 nsfeat;
	171	__u8 nlbaf;
	172	__u8 flbas;
	173	__u8 mc;
	174	__u8 dpc;
	175	__u8 dps;
	176	__u8 nmic;
	177	__u8 rescap;
	178	__u8 fpi;
	179	__u8 rsvd33;
	180	__le16 nawun;
	181	__le16 nawupf;
	182	__le16 nacwu;
	183	__le16 nabsn;
	184	__le16 nabo;
185	__le16 nabspf;
186	__u16 rsvd46;
187	__le64 nvmcap[2];
188	__u8 rsvd64[40];
189	__u8 nguid[16];
190	__u8 eui64[8];
191	struct nvme_lbaf lbaf[16];
192	__u8 rsvd192[192];
193	__u8 vs[3712];
194	};
195
196	enum {
197	NVME_NS_FEAT_THIN = 1 << 0,
198	NVME_NS_FLBAS_LBA_MASK = 0xf,
199	NVME_NS_FLBAS_META_EXT = 0x10,
200	NVME_LBAF_RP_BEST = 0,
201	NVME_LBAF_RP_BETTER = 1,
202	NVME_LBAF_RP_GOOD = 2,
203	NVME_LBAF_RP_DEGRADED = 3,
204	NVME_NS_DPC_PI_LAST = 1 << 4,
205	NVME_NS_DPC_PI_FIRST = 1 << 3,
206	NVME_NS_DPC_PI_TYPE3 = 1 << 2,
207	NVME_NS_DPC_PI_TYPE2 = 1 << 1,
208	NVME_NS_DPC_PI_TYPE1 = 1 << 0,
209	NVME_NS_DPS_PI_FIRST = 1 << 3,
210	NVME_NS_DPS_PI_MASK = 0x7,
211	NVME_NS_DPS_PI_TYPE1 = 1,
212	NVME_NS_DPS_PI_TYPE2 = 2,
213	NVME_NS_DPS_PI_TYPE3 = 3,
214	};
215
216	struct nvme_smart_log {
217	__u8 critical_warning;
218	__u8 temperature[2];
219	__u8 avail_spare;
220	__u8 spare_thresh;
221	__u8 percent_used;
222	__u8 rsvd6[26];
223	__u8 data_units_read[16];
224	__u8 data_units_written[16];
225	__u8 host_reads[16];
226	__u8 host_writes[16];
227	__u8 ctrl_busy_time[16];
228	__u8 power_cycles[16];
229	__u8 power_on_hours[16];
230	__u8 unsafe_shutdowns[16];
231	__u8 media_errors[16];
232	__u8 num_err_log_entries[16];
233	__le32 warning_temp_time;
234	__le32 critical_comp_time;
235	__le16 temp_sensor[8];
236	__u8 rsvd216[296];
237	};
238
239	enum {
240	NVME_SMART_CRIT_SPARE = 1 << 0,
241	NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
242	NVME_SMART_CRIT_RELIABILITY = 1 << 2,
243	NVME_SMART_CRIT_MEDIA = 1 << 3,
244	NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
245	};
246
247	enum {
248	NVME_AER_NOTICE_NS_CHANGED = 0x0002,
249	};
250
251	struct nvme_lba_range_type {
252	__u8 type;
253	__u8 attributes;
254	__u8 rsvd2[14];
255	__u64 slba;
256	__u64 nlb;
257	__u8 guid[16];
258	__u8 rsvd48[16];
259	};
260
261	enum {
262	NVME_LBART_TYPE_FS = 0x01,
263	NVME_LBART_TYPE_RAID = 0x02,
264	NVME_LBART_TYPE_CACHE = 0x03,
265	NVME_LBART_TYPE_SWAP = 0x04,
266
267	NVME_LBART_ATTRIB_TEMP = 1 << 0,
268	NVME_LBART_ATTRIB_HIDE = 1 << 1,
269	};
270
271	struct nvme_reservation_status {
272	__le32 gen;
273	__u8 rtype;
274	__u8 regctl[2];
275	__u8 resv5[2];
276	__u8 ptpls;
277	__u8 resv10[13];
278	struct {
279	__le16 cntlid;
280	__u8 rcsts;
281	__u8 resv3[5];
282	__le64 hostid;
283	__le64 rkey;
284	} regctl_ds[];
285	};
286
79f370ea CH	287	enum nvme_async_event_type {
	288	NVME_AER_TYPE_ERROR = 0,
	289	NVME_AER_TYPE_SMART = 1,
	290	NVME_AER_TYPE_NOTICE = 2,
	291	};
	292
9d99a8dd CH	293	/* I/O commands */
	294
	295	enum nvme_opcode {
	296	nvme_cmd_flush = 0x00,
	297	nvme_cmd_write = 0x01,
	298	nvme_cmd_read = 0x02,
	299	nvme_cmd_write_uncor = 0x04,
	300	nvme_cmd_compare = 0x05,
	301	nvme_cmd_write_zeroes = 0x08,
	302	nvme_cmd_dsm = 0x09,
	303	nvme_cmd_resv_register = 0x0d,
	304	nvme_cmd_resv_report = 0x0e,
	305	nvme_cmd_resv_acquire = 0x11,
	306	nvme_cmd_resv_release = 0x15,
	307	};
	308
	309	struct nvme_common_command {
	310	__u8 opcode;
	311	__u8 flags;
	312	__u16 command_id;
	313	__le32 nsid;
	314	__le32 cdw2[2];
	315	__le64 metadata;
	316	__le64 prp1;
	317	__le64 prp2;
	318	__le32 cdw10[6];
	319	};
	320
	321	struct nvme_rw_command {
	322	__u8 opcode;
	323	__u8 flags;
	324	__u16 command_id;
	325	__le32 nsid;
	326	__u64 rsvd2;
	327	__le64 metadata;
	328	__le64 prp1;
	329	__le64 prp2;
	330	__le64 slba;
	331	__le16 length;
	332	__le16 control;
	333	__le32 dsmgmt;
	334	__le32 reftag;
	335	__le16 apptag;
	336	__le16 appmask;
	337	};
	338
	339	enum {
	340	NVME_RW_LR = 1 << 15,
	341	NVME_RW_FUA = 1 << 14,
	342	NVME_RW_DSM_FREQ_UNSPEC = 0,
	343	NVME_RW_DSM_FREQ_TYPICAL = 1,
	344	NVME_RW_DSM_FREQ_RARE = 2,
	345	NVME_RW_DSM_FREQ_READS = 3,
	346	NVME_RW_DSM_FREQ_WRITES = 4,
	347	NVME_RW_DSM_FREQ_RW = 5,
	348	NVME_RW_DSM_FREQ_ONCE = 6,
	349	NVME_RW_DSM_FREQ_PREFETCH = 7,
	350	NVME_RW_DSM_FREQ_TEMP = 8,
	351	NVME_RW_DSM_LATENCY_NONE = 0 << 4,
	352	NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
	353	NVME_RW_DSM_LATENCY_NORM = 2 << 4,
	354	NVME_RW_DSM_LATENCY_LOW = 3 << 4,
	355	NVME_RW_DSM_SEQ_REQ = 1 << 6,
	356	NVME_RW_DSM_COMPRESSED = 1 << 7,
357	NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
358	NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
359	NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
360	NVME_RW_PRINFO_PRACT = 1 << 13,
361	};
362
363	struct nvme_dsm_cmd {
364	__u8 opcode;
365	__u8 flags;
366	__u16 command_id;
367	__le32 nsid;
368	__u64 rsvd2[2];
369	__le64 prp1;
370	__le64 prp2;
371	__le32 nr;
372	__le32 attributes;
373	__u32 rsvd12[4];
374	};
375
376	enum {
377	NVME_DSMGMT_IDR = 1 << 0,
378	NVME_DSMGMT_IDW = 1 << 1,
379	NVME_DSMGMT_AD = 1 << 2,
380	};
381
382	struct nvme_dsm_range {
383	__le32 cattr;
384	__le32 nlb;
385	__le64 slba;
386	};
387
388	/* Admin commands */
389
390	enum nvme_admin_opcode {
391	nvme_admin_delete_sq = 0x00,
392	nvme_admin_create_sq = 0x01,
393	nvme_admin_get_log_page = 0x02,
394	nvme_admin_delete_cq = 0x04,
395	nvme_admin_create_cq = 0x05,
396	nvme_admin_identify = 0x06,
397	nvme_admin_abort_cmd = 0x08,
398	nvme_admin_set_features = 0x09,
399	nvme_admin_get_features = 0x0a,
400	nvme_admin_async_event = 0x0c,
401	nvme_admin_activate_fw = 0x10,
402	nvme_admin_download_fw = 0x11,
403	nvme_admin_format_nvm = 0x80,
404	nvme_admin_security_send = 0x81,
405	nvme_admin_security_recv = 0x82,
406	};
407
408	enum {
409	NVME_QUEUE_PHYS_CONTIG = (1 << 0),
410	NVME_CQ_IRQ_ENABLED = (1 << 1),
411	NVME_SQ_PRIO_URGENT = (0 << 1),
412	NVME_SQ_PRIO_HIGH = (1 << 1),
413	NVME_SQ_PRIO_MEDIUM = (2 << 1),
414	NVME_SQ_PRIO_LOW = (3 << 1),
415	NVME_FEAT_ARBITRATION = 0x01,
416	NVME_FEAT_POWER_MGMT = 0x02,
417	NVME_FEAT_LBA_RANGE = 0x03,
418	NVME_FEAT_TEMP_THRESH = 0x04,
419	NVME_FEAT_ERR_RECOVERY = 0x05,
420	NVME_FEAT_VOLATILE_WC = 0x06,
421	NVME_FEAT_NUM_QUEUES = 0x07,
422	NVME_FEAT_IRQ_COALESCE = 0x08,
423	NVME_FEAT_IRQ_CONFIG = 0x09,
424	NVME_FEAT_WRITE_ATOMIC = 0x0a,
425	NVME_FEAT_ASYNC_EVENT = 0x0b,
426	NVME_FEAT_AUTO_PST = 0x0c,
427	NVME_FEAT_SW_PROGRESS = 0x80,
428	NVME_FEAT_HOST_ID = 0x81,
429	NVME_FEAT_RESV_MASK = 0x82,
430	NVME_FEAT_RESV_PERSIST = 0x83,
431	NVME_LOG_ERROR = 0x01,
432	NVME_LOG_SMART = 0x02,
433	NVME_LOG_FW_SLOT = 0x03,
434	NVME_LOG_RESERVATION = 0x80,
435	NVME_FWACT_REPL = (0 << 3),
436	NVME_FWACT_REPL_ACTV = (1 << 3),
437	NVME_FWACT_ACTV = (2 << 3),
438	};
439
440	struct nvme_identify {
441	__u8 opcode;
442	__u8 flags;
443	__u16 command_id;
444	__le32 nsid;
445	__u64 rsvd2[2];
446	__le64 prp1;
447	__le64 prp2;
448	__le32 cns;
449	__u32 rsvd11[5];
450	};
451
452	struct nvme_features {
453	__u8 opcode;
454	__u8 flags;
455	__u16 command_id;
456	__le32 nsid;
457	__u64 rsvd2[2];
458	__le64 prp1;
459	__le64 prp2;
460	__le32 fid;
461	__le32 dword11;
462	__u32 rsvd12[4];
463	};
464
465	struct nvme_create_cq {
466	__u8 opcode;
467	__u8 flags;
468	__u16 command_id;
469	__u32 rsvd1[5];
470	__le64 prp1;
471	__u64 rsvd8;
472	__le16 cqid;
473	__le16 qsize;
474	__le16 cq_flags;
475	__le16 irq_vector;
476	__u32 rsvd12[4];
477	};
478
479	struct nvme_create_sq {
480	__u8 opcode;
481	__u8 flags;
482	__u16 command_id;
483	__u32 rsvd1[5];
484	__le64 prp1;
485	__u64 rsvd8;
486	__le16 sqid;
487	__le16 qsize;
488	__le16 sq_flags;
489	__le16 cqid;
490	__u32 rsvd12[4];
491	};
492
493	struct nvme_delete_queue {
494	__u8 opcode;
495	__u8 flags;
496	__u16 command_id;
497	__u32 rsvd1[9];
498	__le16 qid;
499	__u16 rsvd10;
500	__u32 rsvd11[5];
501	};
502
503	struct nvme_abort_cmd {
504	__u8 opcode;
505	__u8 flags;
506	__u16 command_id;
507	__u32 rsvd1[9];
508	__le16 sqid;
509	__u16 cid;
510	__u32 rsvd11[5];
511	};
512
513	struct nvme_download_firmware {
514	__u8 opcode;
515	__u8 flags;
516	__u16 command_id;
517	__u32 rsvd1[5];
518	__le64 prp1;
519	__le64 prp2;
520	__le32 numd;
521	__le32 offset;
522	__u32 rsvd12[4];
523	};
524
525	struct nvme_format_cmd {
526	__u8 opcode;
527	__u8 flags;
528	__u16 command_id;
529	__le32 nsid;
530	__u64 rsvd2[4];
531	__le32 cdw10;
532	__u32 rsvd11[5];
533	};
534
725b3588 AB	535	struct nvme_get_log_page_command {
	536	__u8 opcode;
	537	__u8 flags;
	538	__u16 command_id;
	539	__le32 nsid;
	540	__u64 rsvd2[2];
	541	__le64 prp1;
	542	__le64 prp2;
	543	__u8 lid;
	544	__u8 rsvd10;
	545	__le16 numdl;
	546	__le16 numdu;
	547	__u16 rsvd11;
	548	__le32 lpol;
	549	__le32 lpou;
	550	__u32 rsvd14[2];
	551	};
	552
9d99a8dd CH	553	struct nvme_command {
	554	union {
	555	struct nvme_common_command common;
	556	struct nvme_rw_command rw;
	557	struct nvme_identify identify;
	558	struct nvme_features features;
	559	struct nvme_create_cq create_cq;
	560	struct nvme_create_sq create_sq;
	561	struct nvme_delete_queue delete_queue;
	562	struct nvme_download_firmware dlfw;
	563	struct nvme_format_cmd format;
	564	struct nvme_dsm_cmd dsm;
	565	struct nvme_abort_cmd abort;
725b3588	566	struct nvme_get_log_page_command get_log_page;
9d99a8dd CH	567	};
	568	};
	569
	570	enum {
	571	NVME_SC_SUCCESS = 0x0,
	572	NVME_SC_INVALID_OPCODE = 0x1,
	573	NVME_SC_INVALID_FIELD = 0x2,
	574	NVME_SC_CMDID_CONFLICT = 0x3,
	575	NVME_SC_DATA_XFER_ERROR = 0x4,
	576	NVME_SC_POWER_LOSS = 0x5,
	577	NVME_SC_INTERNAL = 0x6,
	578	NVME_SC_ABORT_REQ = 0x7,
	579	NVME_SC_ABORT_QUEUE = 0x8,
	580	NVME_SC_FUSED_FAIL = 0x9,
	581	NVME_SC_FUSED_MISSING = 0xa,
	582	NVME_SC_INVALID_NS = 0xb,
	583	NVME_SC_CMD_SEQ_ERROR = 0xc,
	584	NVME_SC_SGL_INVALID_LAST = 0xd,
	585	NVME_SC_SGL_INVALID_COUNT = 0xe,
	586	NVME_SC_SGL_INVALID_DATA = 0xf,
	587	NVME_SC_SGL_INVALID_METADATA = 0x10,
	588	NVME_SC_SGL_INVALID_TYPE = 0x11,
	589	NVME_SC_LBA_RANGE = 0x80,
	590	NVME_SC_CAP_EXCEEDED = 0x81,
	591	NVME_SC_NS_NOT_READY = 0x82,
	592	NVME_SC_RESERVATION_CONFLICT = 0x83,
	593	NVME_SC_CQ_INVALID = 0x100,
	594	NVME_SC_QID_INVALID = 0x101,
	595	NVME_SC_QUEUE_SIZE = 0x102,
	596	NVME_SC_ABORT_LIMIT = 0x103,
	597	NVME_SC_ABORT_MISSING = 0x104,
	598	NVME_SC_ASYNC_LIMIT = 0x105,
	599	NVME_SC_FIRMWARE_SLOT = 0x106,
	600	NVME_SC_FIRMWARE_IMAGE = 0x107,
	601	NVME_SC_INVALID_VECTOR = 0x108,
	602	NVME_SC_INVALID_LOG_PAGE = 0x109,
	603	NVME_SC_INVALID_FORMAT = 0x10a,
	604	NVME_SC_FIRMWARE_NEEDS_RESET = 0x10b,
	605	NVME_SC_INVALID_QUEUE = 0x10c,
	606	NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
	607	NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
	608	NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
	609	NVME_SC_FW_NEEDS_RESET_SUBSYS = 0x110,
	610	NVME_SC_BAD_ATTRIBUTES = 0x180,
	611	NVME_SC_INVALID_PI = 0x181,
	612	NVME_SC_READ_ONLY = 0x182,
	613	NVME_SC_WRITE_FAULT = 0x280,
	614	NVME_SC_READ_ERROR = 0x281,
	615	NVME_SC_GUARD_CHECK = 0x282,
	616	NVME_SC_APPTAG_CHECK = 0x283,
	617	NVME_SC_REFTAG_CHECK = 0x284,
	618	NVME_SC_COMPARE_FAILED = 0x285,
	619	NVME_SC_ACCESS_DENIED = 0x286,
	620	NVME_SC_DNR = 0x4000,
	621	};
	622
	623	struct nvme_completion {
	624	__le32 result; /* Used by admin commands to return data */
	625	__u32 rsvd;
	626	__le16 sq_head; /* how much of this queue may be reclaimed */
	627	__le16 sq_id; /* submission queue that generated this entry */
	628	__u16 command_id; /* of the command which completed */
	629	__le16 status; /* did the command fail, and if so, why? */
	630	};
631
632	#define NVME_VS(major, minor) (((major) << 16) \| ((minor) << 8))
633
b60503ba	634	#endif /* _LINUX_NVME_H */