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staging:iio:adc:ad7793: Use new triggered buffer setup helper function
[linux-2.6-block.git] / drivers / staging / iio / adc / ad7793.c
CommitLineData
88bc3054
MH		 1/*
2 * AD7792/AD7793 SPI ADC driver
3 *
f316983f 4 * Copyright 2011-2012 Analog Devices Inc.
88bc3054
MH		 5 *
6 * Licensed under the GPL-2.
7 */
8
9#include <linux/interrupt.h>
10#include <linux/device.h>
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/sysfs.h>
14#include <linux/spi/spi.h>
15#include <linux/regulator/consumer.h>
16#include <linux/err.h>
17#include <linux/sched.h>
18#include <linux/delay.h>
45296236 19#include <linux/module.h>
88bc3054 20
06458e27
JC		 21#include <linux/iio/iio.h>
22#include <linux/iio/sysfs.h>
23#include <linux/iio/buffer.h>
06458e27
JC		 24#include <linux/iio/trigger.h>
25#include <linux/iio/trigger_consumer.h>
82796edc 26#include <linux/iio/triggered_buffer.h>
88bc3054
MH		 27
28#include "ad7793.h"
29
30/* NOTE:
31 * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output.
32 * In order to avoid contentions on the SPI bus, it's therefore necessary
33 * to use spi bus locking.
34 *
35 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
36 */
37
38struct ad7793_chip_info {
39 struct iio_chan_spec channel[7];
40};
41
42struct ad7793_state {
43 struct spi_device *spi;
44 struct iio_trigger *trig;
45 const struct ad7793_chip_info *chip_info;
46 struct regulator *reg;
47 struct ad7793_platform_data *pdata;
48 wait_queue_head_t wq_data_avail;
49 bool done;
50 bool irq_dis;
51 u16 int_vref_mv;
52 u16 mode;
53 u16 conf;
54 u32 scale_avail[8][2];
32b5eeca
JC		 55 /* Note this uses fact that 8 the mask always fits in a long */
56 unsigned long available_scan_masks[7];
88bc3054
MH		 57 /*
58 * DMA (thus cache coherency maintenance) requires the
59 * transfer buffers to live in their own cache lines.
60 */
61 u8 data[4] ____cacheline_aligned;
62};
63
64enum ad7793_supported_device_ids {
65 ID_AD7792,
66 ID_AD7793,
67};
68
69static int __ad7793_write_reg(struct ad7793_state *st, bool locked,
70 bool cs_change, unsigned char reg,
71 unsigned size, unsigned val)
72{
73 u8 *data = st->data;
74 struct spi_transfer t = {
75 .tx_buf = data,
76 .len = size + 1,
77 .cs_change = cs_change,
78 };
79 struct spi_message m;
80
81 data[0] = AD7793_COMM_WRITE | AD7793_COMM_ADDR(reg);
82
83 switch (size) {
84 case 3:
85 data[1] = val >> 16;
86 data[2] = val >> 8;
87 data[3] = val;
88 break;
89 case 2:
90 data[1] = val >> 8;
91 data[2] = val;
92 break;
93 case 1:
94 data[1] = val;
95 break;
96 default:
97 return -EINVAL;
98 }
99
100 spi_message_init(&m);
101 spi_message_add_tail(&t, &m);
102
103 if (locked)
104 return spi_sync_locked(st->spi, &m);
105 else
106 return spi_sync(st->spi, &m);
107}
108
109static int ad7793_write_reg(struct ad7793_state *st,
110 unsigned reg, unsigned size, unsigned val)
111{
112 return __ad7793_write_reg(st, false, false, reg, size, val);
113}
114
115static int __ad7793_read_reg(struct ad7793_state *st, bool locked,
116 bool cs_change, unsigned char reg,
117 int *val, unsigned size)
118{
119 u8 *data = st->data;
120 int ret;
121 struct spi_transfer t[] = {
122 {
123 .tx_buf = data,
124 .len = 1,
125 }, {
126 .rx_buf = data,
127 .len = size,
128 .cs_change = cs_change,
129 },
130 };
131 struct spi_message m;
132
133 data[0] = AD7793_COMM_READ | AD7793_COMM_ADDR(reg);
134
135 spi_message_init(&m);
136 spi_message_add_tail(&t[0], &m);
137 spi_message_add_tail(&t[1], &m);
138
139 if (locked)
140 ret = spi_sync_locked(st->spi, &m);
141 else
142 ret = spi_sync(st->spi, &m);
143
144 if (ret < 0)
145 return ret;
146
147 switch (size) {
148 case 3:
149 *val = data[0] << 16 | data[1] << 8 | data[2];
150 break;
151 case 2:
152 *val = data[0] << 8 | data[1];
153 break;
154 case 1:
155 *val = data[0];
156 break;
157 default:
158 return -EINVAL;
159 }
160
161 return 0;
162}
163
164static int ad7793_read_reg(struct ad7793_state *st,
165 unsigned reg, int *val, unsigned size)
166{
167 return __ad7793_read_reg(st, 0, 0, reg, val, size);
168}
169
170static int ad7793_read(struct ad7793_state *st, unsigned ch,
171 unsigned len, int *val)
172{
173 int ret;
174 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | AD7793_CONF_CHAN(ch);
175 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
176 AD7793_MODE_SEL(AD7793_MODE_SINGLE);
177
178 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
179
180 spi_bus_lock(st->spi->master);
181 st->done = false;
182
183 ret = __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
184 sizeof(st->mode), st->mode);
185 if (ret < 0)
186 goto out;
187
188 st->irq_dis = false;
189 enable_irq(st->spi->irq);
190 wait_event_interruptible(st->wq_data_avail, st->done);
191
192 ret = __ad7793_read_reg(st, 1, 0, AD7793_REG_DATA, val, len);
193out:
194 spi_bus_unlock(st->spi->master);
195
196 return ret;
197}
198
199static int ad7793_calibrate(struct ad7793_state *st, unsigned mode, unsigned ch)
200{
201 int ret;
202
203 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | AD7793_CONF_CHAN(ch);
204 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) | AD7793_MODE_SEL(mode);
205
206 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
207
208 spi_bus_lock(st->spi->master);
209 st->done = false;
210
211 ret = __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
212 sizeof(st->mode), st->mode);
213 if (ret < 0)
214 goto out;
215
216 st->irq_dis = false;
217 enable_irq(st->spi->irq);
218 wait_event_interruptible(st->wq_data_avail, st->done);
219
220 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
221 AD7793_MODE_SEL(AD7793_MODE_IDLE);
222
223 ret = __ad7793_write_reg(st, 1, 0, AD7793_REG_MODE,
224 sizeof(st->mode), st->mode);
225out:
226 spi_bus_unlock(st->spi->master);
227
228 return ret;
229}
230
231static const u8 ad7793_calib_arr[6][2] = {
232 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
233 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
234 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
235 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M},
236 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M},
237 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M}
238};
239
240static int ad7793_calibrate_all(struct ad7793_state *st)
241{
242 int i, ret;
243
244 for (i = 0; i < ARRAY_SIZE(ad7793_calib_arr); i++) {
245 ret = ad7793_calibrate(st, ad7793_calib_arr[i][0],
246 ad7793_calib_arr[i][1]);
247 if (ret)
248 goto out;
249 }
250
251 return 0;
252out:
253 dev_err(&st->spi->dev, "Calibration failed\n");
254 return ret;
255}
256
257static int ad7793_setup(struct ad7793_state *st)
258{
259 int i, ret = -1;
260 unsigned long long scale_uv;
261 u32 id;
262
263 /* reset the serial interface */
264 ret = spi_write(st->spi, (u8 *)&ret, sizeof(ret));
265 if (ret < 0)
266 goto out;
267 msleep(1); /* Wait for at least 500us */
268
269 /* write/read test for device presence */
270 ret = ad7793_read_reg(st, AD7793_REG_ID, &id, 1);
271 if (ret)
272 goto out;
273
274 id &= AD7793_ID_MASK;
275
276 if (!((id == AD7792_ID) || (id == AD7793_ID))) {
277 dev_err(&st->spi->dev, "device ID query failed\n");
278 goto out;
279 }
280
281 st->mode = (st->pdata->mode & ~AD7793_MODE_SEL(-1)) |
282 AD7793_MODE_SEL(AD7793_MODE_IDLE);
283 st->conf = st->pdata->conf & ~AD7793_CONF_CHAN(-1);
284
285 ret = ad7793_write_reg(st, AD7793_REG_MODE, sizeof(st->mode), st->mode);
286 if (ret)
287 goto out;
288
289 ret = ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
290 if (ret)
291 goto out;
292
293 ret = ad7793_write_reg(st, AD7793_REG_IO,
294 sizeof(st->pdata->io), st->pdata->io);
295 if (ret)
296 goto out;
297
298 ret = ad7793_calibrate_all(st);
299 if (ret)
300 goto out;
301
302 /* Populate available ADC input ranges */
303 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
304 scale_uv = ((u64)st->int_vref_mv * 100000000)
305 >> (st->chip_info->channel[0].scan_type.realbits -
306 (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1));
307 scale_uv >>= i;
308
309 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
310 st->scale_avail[i][0] = scale_uv;
311 }
312
313 return 0;
314out:
315 dev_err(&st->spi->dev, "setup failed\n");
316 return ret;
317}
318
88bc3054
MH		 319static int ad7793_ring_preenable(struct iio_dev *indio_dev)
320{
321 struct ad7793_state *st = iio_priv(indio_dev);
88bc3054 322 unsigned channel;
81a4fc01 323 int ret;
88bc3054 324
550268ca 325 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
88bc3054 326 return -EINVAL;
81a4fc01
JC		 327 ret = iio_sw_buffer_preenable(indio_dev);
328 if (ret < 0)
329 return ret;
88bc3054 330
550268ca 331 channel = find_first_bit(indio_dev->active_scan_mask,
32b5eeca 332 indio_dev->masklength);
88bc3054 333
88bc3054
MH		 334 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
335 AD7793_MODE_SEL(AD7793_MODE_CONT);
336 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) |
337 AD7793_CONF_CHAN(indio_dev->channels[channel].address);
338
339 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
340
341 spi_bus_lock(st->spi->master);
342 __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
343 sizeof(st->mode), st->mode);
344
345 st->irq_dis = false;
346 enable_irq(st->spi->irq);
347
348 return 0;
349}
350
351static int ad7793_ring_postdisable(struct iio_dev *indio_dev)
352{
353 struct ad7793_state *st = iio_priv(indio_dev);
354
355 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
356 AD7793_MODE_SEL(AD7793_MODE_IDLE);
357
358 st->done = false;
359 wait_event_interruptible(st->wq_data_avail, st->done);
360
361 if (!st->irq_dis)
362 disable_irq_nosync(st->spi->irq);
363
364 __ad7793_write_reg(st, 1, 0, AD7793_REG_MODE,
365 sizeof(st->mode), st->mode);
366
367 return spi_bus_unlock(st->spi->master);
368}
369
370/**
371 * ad7793_trigger_handler() bh of trigger launched polling to ring buffer
372 **/
373
374static irqreturn_t ad7793_trigger_handler(int irq, void *p)
375{
376 struct iio_poll_func *pf = p;
e65bc6ac 377 struct iio_dev *indio_dev = pf->indio_dev;
14555b14 378 struct iio_buffer *ring = indio_dev->buffer;
88bc3054
MH		 379 struct ad7793_state *st = iio_priv(indio_dev);
380 s64 dat64[2];
381 s32 *dat32 = (s32 *)dat64;
382
550268ca 383 if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
88bc3054
MH		 384 __ad7793_read_reg(st, 1, 1, AD7793_REG_DATA,
385 dat32,
386 indio_dev->channels[0].scan_type.realbits/8);
387
388 /* Guaranteed to be aligned with 8 byte boundary */
fd6487f8 389 if (indio_dev->scan_timestamp)
88bc3054
MH		 390 dat64[1] = pf->timestamp;
391
392 ring->access->store_to(ring, (u8 *)dat64, pf->timestamp);
393
394 iio_trigger_notify_done(indio_dev->trig);
395 st->irq_dis = false;
396 enable_irq(st->spi->irq);
397
398 return IRQ_HANDLED;
399}
400
14555b14 401static const struct iio_buffer_setup_ops ad7793_ring_setup_ops = {
88bc3054 402 .preenable = &ad7793_ring_preenable,
3b99fb76
JC		 403 .postenable = &iio_triggered_buffer_postenable,
404 .predisable = &iio_triggered_buffer_predisable,
88bc3054
MH		 405 .postdisable = &ad7793_ring_postdisable,
406};
407
408static int ad7793_register_ring_funcs_and_init(struct iio_dev *indio_dev)
409{
82796edc
LPC		 410 return iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
411 &ad7793_trigger_handler, &ad7793_ring_setup_ops);
88bc3054
MH		 412}
413
414static void ad7793_ring_cleanup(struct iio_dev *indio_dev)
415{
82796edc 416 iio_triggered_buffer_cleanup(indio_dev);
88bc3054
MH		 417}
418
419/**
420 * ad7793_data_rdy_trig_poll() the event handler for the data rdy trig
421 **/
422static irqreturn_t ad7793_data_rdy_trig_poll(int irq, void *private)
423{
424 struct ad7793_state *st = iio_priv(private);
425
426 st->done = true;
427 wake_up_interruptible(&st->wq_data_avail);
428 disable_irq_nosync(irq);
429 st->irq_dis = true;
430 iio_trigger_poll(st->trig, iio_get_time_ns());
431
432 return IRQ_HANDLED;
433}
434
8324e860
JC		 435static struct iio_trigger_ops ad7793_trigger_ops = {
436 .owner = THIS_MODULE,
437};
438
88bc3054
MH		 439static int ad7793_probe_trigger(struct iio_dev *indio_dev)
440{
441 struct ad7793_state *st = iio_priv(indio_dev);
442 int ret;
443
7cbb7537 444 st->trig = iio_trigger_alloc("%s-dev%d",
88bc3054
MH		 445 spi_get_device_id(st->spi)->name,
446 indio_dev->id);
447 if (st->trig == NULL) {
448 ret = -ENOMEM;
449 goto error_ret;
450 }
8324e860 451 st->trig->ops = &ad7793_trigger_ops;
88bc3054
MH		 452
453 ret = request_irq(st->spi->irq,
454 ad7793_data_rdy_trig_poll,
455 IRQF_TRIGGER_LOW,
456 spi_get_device_id(st->spi)->name,
457 indio_dev);
458 if (ret)
459 goto error_free_trig;
460
461 disable_irq_nosync(st->spi->irq);
462 st->irq_dis = true;
463 st->trig->dev.parent = &st->spi->dev;
88bc3054
MH		 464 st->trig->private_data = indio_dev;
465
466 ret = iio_trigger_register(st->trig);
467
468 /* select default trigger */
469 indio_dev->trig = st->trig;
470 if (ret)
471 goto error_free_irq;
472
473 return 0;
474
475error_free_irq:
476 free_irq(st->spi->irq, indio_dev);
477error_free_trig:
7cbb7537 478 iio_trigger_free(st->trig);
88bc3054
MH		 479error_ret:
480 return ret;
481}
482
483static void ad7793_remove_trigger(struct iio_dev *indio_dev)
484{
485 struct ad7793_state *st = iio_priv(indio_dev);
486
487 iio_trigger_unregister(st->trig);
488 free_irq(st->spi->irq, indio_dev);
7cbb7537 489 iio_trigger_free(st->trig);
88bc3054
MH		 490}
491
492static const u16 sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39, 33, 19,
493 17, 16, 12, 10, 8, 6, 4};
494
495static ssize_t ad7793_read_frequency(struct device *dev,
496 struct device_attribute *attr,
497 char *buf)
498{
62c51839 499 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
88bc3054
MH		 500 struct ad7793_state *st = iio_priv(indio_dev);
501
502 return sprintf(buf, "%d\n",
503 sample_freq_avail[AD7793_MODE_RATE(st->mode)]);
504}
505
506static ssize_t ad7793_write_frequency(struct device *dev,
507 struct device_attribute *attr,
508 const char *buf,
509 size_t len)
510{
62c51839 511 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
88bc3054
MH		 512 struct ad7793_state *st = iio_priv(indio_dev);
513 long lval;
514 int i, ret;
515
516 mutex_lock(&indio_dev->mlock);
14555b14 517 if (iio_buffer_enabled(indio_dev)) {
88bc3054
MH		 518 mutex_unlock(&indio_dev->mlock);
519 return -EBUSY;
520 }
521 mutex_unlock(&indio_dev->mlock);
522
523 ret = strict_strtol(buf, 10, &lval);
524 if (ret)
525 return ret;
526
527 ret = -EINVAL;
528
529 for (i = 0; i < ARRAY_SIZE(sample_freq_avail); i++)
530 if (lval == sample_freq_avail[i]) {
531 mutex_lock(&indio_dev->mlock);
532 st->mode &= ~AD7793_MODE_RATE(-1);
533 st->mode |= AD7793_MODE_RATE(i);
534 ad7793_write_reg(st, AD7793_REG_MODE,
535 sizeof(st->mode), st->mode);
536 mutex_unlock(&indio_dev->mlock);
537 ret = 0;
538 }
539
540 return ret ? ret : len;
541}
542
543static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
544 ad7793_read_frequency,
545 ad7793_write_frequency);
546
547static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
548 "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4");
549
550static ssize_t ad7793_show_scale_available(struct device *dev,
551 struct device_attribute *attr, char *buf)
552{
62c51839 553 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
88bc3054
MH		 554 struct ad7793_state *st = iio_priv(indio_dev);
555 int i, len = 0;
556
557 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
558 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
559 st->scale_avail[i][1]);
560
561 len += sprintf(buf + len, "\n");
562
563 return len;
564}
565
566static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available, in-in_scale_available,
567 S_IRUGO, ad7793_show_scale_available, NULL, 0);
568
569static struct attribute *ad7793_attributes[] = {
570 &iio_dev_attr_sampling_frequency.dev_attr.attr,
571 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
572 &iio_dev_attr_in_m_in_scale_available.dev_attr.attr,
573 NULL
574};
575
576static const struct attribute_group ad7793_attribute_group = {
577 .attrs = ad7793_attributes,
578};
579
580static int ad7793_read_raw(struct iio_dev *indio_dev,
581 struct iio_chan_spec const *chan,
582 int *val,
583 int *val2,
584 long m)
585{
586 struct ad7793_state *st = iio_priv(indio_dev);
587 int ret, smpl = 0;
588 unsigned long long scale_uv;
589 bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);
590
591 switch (m) {
b11f98ff 592 case IIO_CHAN_INFO_RAW:
88bc3054 593 mutex_lock(&indio_dev->mlock);
14555b14 594 if (iio_buffer_enabled(indio_dev))
950935b1 595 ret = -EBUSY;
88bc3054
MH		 596 else
597 ret = ad7793_read(st, chan->address,
598 chan->scan_type.realbits / 8, &smpl);
599 mutex_unlock(&indio_dev->mlock);
600
601 if (ret < 0)
602 return ret;
603
604 *val = (smpl >> chan->scan_type.shift) &
605 ((1 << (chan->scan_type.realbits)) - 1);
606
607 if (!unipolar)
608 *val -= (1 << (chan->scan_type.realbits - 1));
609
610 return IIO_VAL_INT;
611
c8a9f805 612 case IIO_CHAN_INFO_SCALE:
88bc3054 613 switch (chan->type) {
6835cb6b 614 case IIO_VOLTAGE:
c8a9f805
JC		 615 if (chan->differential) {
616 *val = st->
617 scale_avail[(st->conf >> 8) & 0x7][0];
618 *val2 = st->
619 scale_avail[(st->conf >> 8) & 0x7][1];
620 return IIO_VAL_INT_PLUS_NANO;
621 } else {
622 /* 1170mV / 2^23 * 6 */
623 scale_uv = (1170ULL * 100000000ULL * 6ULL)
624 >> (chan->scan_type.realbits -
625 (unipolar ? 0 : 1));
626 }
88bc3054
MH		 627 break;
628 case IIO_TEMP:
629 /* Always uses unity gain and internal ref */
630 scale_uv = (2500ULL * 100000000ULL)
631 >> (chan->scan_type.realbits -
632 (unipolar ? 0 : 1));
633 break;
634 default:
635 return -EINVAL;
636 }
637
638 *val2 = do_div(scale_uv, 100000000) * 10;
639 *val = scale_uv;
640
641 return IIO_VAL_INT_PLUS_NANO;
642 }
643 return -EINVAL;
644}
645
646static int ad7793_write_raw(struct iio_dev *indio_dev,
647 struct iio_chan_spec const *chan,
648 int val,
649 int val2,
650 long mask)
651{
652 struct ad7793_state *st = iio_priv(indio_dev);
653 int ret, i;
654 unsigned int tmp;
655
656 mutex_lock(&indio_dev->mlock);
14555b14 657 if (iio_buffer_enabled(indio_dev)) {
88bc3054
MH		 658 mutex_unlock(&indio_dev->mlock);
659 return -EBUSY;
660 }
661
662 switch (mask) {
c8a9f805 663 case IIO_CHAN_INFO_SCALE:
88bc3054
MH		 664 ret = -EINVAL;
665 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
666 if (val2 == st->scale_avail[i][1]) {
667 tmp = st->conf;
668 st->conf &= ~AD7793_CONF_GAIN(-1);
669 st->conf |= AD7793_CONF_GAIN(i);
670
671 if (tmp != st->conf) {
672 ad7793_write_reg(st, AD7793_REG_CONF,
673 sizeof(st->conf),
674 st->conf);
675 ad7793_calibrate_all(st);
676 }
677 ret = 0;
678 }
679
680 default:
681 ret = -EINVAL;
682 }
683
684 mutex_unlock(&indio_dev->mlock);
685 return ret;
686}
687
688static int ad7793_validate_trigger(struct iio_dev *indio_dev,
689 struct iio_trigger *trig)
690{
691 if (indio_dev->trig != trig)
692 return -EINVAL;
693
694 return 0;
695}
696
697static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
698 struct iio_chan_spec const *chan,
699 long mask)
700{
701 return IIO_VAL_INT_PLUS_NANO;
702}
703
704static const struct iio_info ad7793_info = {
705 .read_raw = &ad7793_read_raw,
706 .write_raw = &ad7793_write_raw,
707 .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
708 .attrs = &ad7793_attribute_group,
709 .validate_trigger = ad7793_validate_trigger,
710 .driver_module = THIS_MODULE,
711};
712
713static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
714 [ID_AD7793] = {
ade7ef7b
JC		 715 .channel[0] = {
716 .type = IIO_VOLTAGE,
717 .differential = 1,
718 .indexed = 1,
719 .channel = 0,
720 .channel2 = 0,
721 .address = AD7793_CH_AIN1P_AIN1M,
b11f98ff
JC		 722 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
723 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 724 .scan_index = 0,
725 .scan_type = IIO_ST('s', 24, 32, 0)
726 },
727 .channel[1] = {
728 .type = IIO_VOLTAGE,
729 .differential = 1,
730 .indexed = 1,
731 .channel = 1,
732 .channel2 = 1,
733 .address = AD7793_CH_AIN2P_AIN2M,
b11f98ff
JC		 734 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
735 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 736 .scan_index = 1,
737 .scan_type = IIO_ST('s', 24, 32, 0)
738 },
739 .channel[2] = {
740 .type = IIO_VOLTAGE,
741 .differential = 1,
742 .indexed = 1,
743 .channel = 2,
744 .channel2 = 2,
745 .address = AD7793_CH_AIN3P_AIN3M,
b11f98ff
JC		 746 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
747 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 748 .scan_index = 2,
749 .scan_type = IIO_ST('s', 24, 32, 0)
750 },
751 .channel[3] = {
752 .type = IIO_VOLTAGE,
753 .differential = 1,
754 .extend_name = "shorted",
755 .indexed = 1,
756 .channel = 2,
757 .channel2 = 2,
758 .address = AD7793_CH_AIN1M_AIN1M,
b11f98ff
JC		 759 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
760 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 761 .scan_index = 2,
762 .scan_type = IIO_ST('s', 24, 32, 0)
763 },
764 .channel[4] = {
765 .type = IIO_TEMP,
766 .indexed = 1,
767 .channel = 0,
768 .address = AD7793_CH_TEMP,
b11f98ff
JC		 769 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
770 IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
ade7ef7b
JC		 771 .scan_index = 4,
772 .scan_type = IIO_ST('s', 24, 32, 0),
773 },
774 .channel[5] = {
775 .type = IIO_VOLTAGE,
776 .extend_name = "supply",
777 .indexed = 1,
778 .channel = 4,
779 .address = AD7793_CH_AVDD_MONITOR,
b11f98ff
JC		 780 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
781 IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
ade7ef7b
JC		 782 .scan_index = 5,
783 .scan_type = IIO_ST('s', 24, 32, 0),
784 },
88bc3054
MH		 785 .channel[6] = IIO_CHAN_SOFT_TIMESTAMP(6),
786 },
787 [ID_AD7792] = {
ade7ef7b
JC		 788 .channel[0] = {
789 .type = IIO_VOLTAGE,
790 .differential = 1,
791 .indexed = 1,
792 .channel = 0,
793 .channel2 = 0,
794 .address = AD7793_CH_AIN1P_AIN1M,
b11f98ff
JC		 795 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
796 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 797 .scan_index = 0,
798 .scan_type = IIO_ST('s', 16, 32, 0)
799 },
800 .channel[1] = {
801 .type = IIO_VOLTAGE,
802 .differential = 1,
803 .indexed = 1,
804 .channel = 1,
805 .channel2 = 1,
806 .address = AD7793_CH_AIN2P_AIN2M,
b11f98ff
JC		 807 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
808 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 809 .scan_index = 1,
810 .scan_type = IIO_ST('s', 16, 32, 0)
811 },
812 .channel[2] = {
813 .type = IIO_VOLTAGE,
814 .differential = 1,
815 .indexed = 1,
816 .channel = 2,
817 .channel2 = 2,
818 .address = AD7793_CH_AIN3P_AIN3M,
b11f98ff
JC		 819 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
820 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 821 .scan_index = 2,
822 .scan_type = IIO_ST('s', 16, 32, 0)
823 },
824 .channel[3] = {
825 .type = IIO_VOLTAGE,
826 .differential = 1,
827 .extend_name = "shorted",
828 .indexed = 1,
829 .channel = 2,
830 .channel2 = 2,
831 .address = AD7793_CH_AIN1M_AIN1M,
b11f98ff
JC		 832 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
833 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 834 .scan_index = 2,
835 .scan_type = IIO_ST('s', 16, 32, 0)
836 },
837 .channel[4] = {
838 .type = IIO_TEMP,
839 .indexed = 1,
840 .channel = 0,
841 .address = AD7793_CH_TEMP,
b11f98ff
JC		 842 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
843 IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
ade7ef7b
JC		 844 .scan_index = 4,
845 .scan_type = IIO_ST('s', 16, 32, 0),
846 },
847 .channel[5] = {
848 .type = IIO_VOLTAGE,
849 .extend_name = "supply",
850 .indexed = 1,
851 .channel = 4,
852 .address = AD7793_CH_AVDD_MONITOR,
b11f98ff
JC		 853 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
854 IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
ade7ef7b
JC		 855 .scan_index = 5,
856 .scan_type = IIO_ST('s', 16, 32, 0),
857 },
88bc3054
MH		 858 .channel[6] = IIO_CHAN_SOFT_TIMESTAMP(6),
859 },
860};
861
862static int __devinit ad7793_probe(struct spi_device *spi)
863{
864 struct ad7793_platform_data *pdata = spi->dev.platform_data;
865 struct ad7793_state *st;
866 struct iio_dev *indio_dev;
26d25ae3 867 int ret, i, voltage_uv = 0;
88bc3054
MH		 868
869 if (!pdata) {
870 dev_err(&spi->dev, "no platform data?\n");
871 return -ENODEV;
872 }
873
874 if (!spi->irq) {
875 dev_err(&spi->dev, "no IRQ?\n");
876 return -ENODEV;
877 }
878
7cbb7537 879 indio_dev = iio_device_alloc(sizeof(*st));
88bc3054
MH		 880 if (indio_dev == NULL)
881 return -ENOMEM;
882
883 st = iio_priv(indio_dev);
884
885 st->reg = regulator_get(&spi->dev, "vcc");
886 if (!IS_ERR(st->reg)) {
887 ret = regulator_enable(st->reg);
888 if (ret)
889 goto error_put_reg;
890
891 voltage_uv = regulator_get_voltage(st->reg);
892 }
893
894 st->chip_info =
895 &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data];
896
897 st->pdata = pdata;
898
899 if (pdata && pdata->vref_mv)
900 st->int_vref_mv = pdata->vref_mv;
901 else if (voltage_uv)
902 st->int_vref_mv = voltage_uv / 1000;
903 else
904 st->int_vref_mv = 2500; /* Build-in ref */
905
906 spi_set_drvdata(spi, indio_dev);
907 st->spi = spi;
908
909 indio_dev->dev.parent = &spi->dev;
910 indio_dev->name = spi_get_device_id(spi)->name;
911 indio_dev->modes = INDIO_DIRECT_MODE;
912 indio_dev->channels = st->chip_info->channel;
913 indio_dev->available_scan_masks = st->available_scan_masks;
914 indio_dev->num_channels = 7;
915 indio_dev->info = &ad7793_info;
916
32b5eeca
JC		 917 for (i = 0; i < indio_dev->num_channels; i++) {
918 set_bit(i, &st->available_scan_masks[i]);
919 set_bit(indio_dev->
920 channels[indio_dev->num_channels - 1].scan_index,
921 &st->available_scan_masks[i]);
922 }
88bc3054
MH		 923
924 init_waitqueue_head(&st->wq_data_avail);
925
926 ret = ad7793_register_ring_funcs_and_init(indio_dev);
927 if (ret)
928 goto error_disable_reg;
929
88bc3054
MH		 930 ret = ad7793_probe_trigger(indio_dev);
931 if (ret)
932 goto error_unreg_ring;
933
88bc3054
MH		 934 ret = ad7793_setup(st);
935 if (ret)
82796edc 936 goto error_remove_trigger;
88bc3054 937
26d25ae3
JC		 938 ret = iio_device_register(indio_dev);
939 if (ret)
82796edc 940 goto error_remove_trigger;
26d25ae3 941
88bc3054
MH		 942 return 0;
943
88bc3054
MH		 944error_remove_trigger:
945 ad7793_remove_trigger(indio_dev);
946error_unreg_ring:
947 ad7793_ring_cleanup(indio_dev);
948error_disable_reg:
949 if (!IS_ERR(st->reg))
950 regulator_disable(st->reg);
951error_put_reg:
952 if (!IS_ERR(st->reg))
953 regulator_put(st->reg);
954
7cbb7537 955 iio_device_free(indio_dev);
88bc3054
MH		 956
957 return ret;
958}
959
960static int ad7793_remove(struct spi_device *spi)
961{
962 struct iio_dev *indio_dev = spi_get_drvdata(spi);
963 struct ad7793_state *st = iio_priv(indio_dev);
964
d2fffd6c 965 iio_device_unregister(indio_dev);
88bc3054
MH		 966 ad7793_remove_trigger(indio_dev);
967 ad7793_ring_cleanup(indio_dev);
968
969 if (!IS_ERR(st->reg)) {
970 regulator_disable(st->reg);
971 regulator_put(st->reg);
972 }
973
7cbb7537 974 iio_device_free(indio_dev);
88bc3054
MH		 975
976 return 0;
977}
978
979static const struct spi_device_id ad7793_id[] = {
980 {"ad7792", ID_AD7792},
981 {"ad7793", ID_AD7793},
982 {}
983};
55e4390c 984MODULE_DEVICE_TABLE(spi, ad7793_id);
88bc3054
MH		 985
986static struct spi_driver ad7793_driver = {
987 .driver = {
988 .name = "ad7793",
88bc3054
MH		 989 .owner = THIS_MODULE,
990 },
991 .probe = ad7793_probe,
992 .remove = __devexit_p(ad7793_remove),
993 .id_table = ad7793_id,
994};
ae6ae6fe 995module_spi_driver(ad7793_driver);
88bc3054
MH		 996
997MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
998MODULE_DESCRIPTION("Analog Devices AD7792/3 ADC");
999MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)