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Blackfin SPI Driver: fix bug - correct usage of struct spi_transfer.cs_change
[linux-2.6-block.git] / drivers / spi / spi_bfin5xx.c
CommitLineData
a5f6abd4 1/*
26fdc1f0 2 * Blackfin On-Chip SPI Driver
a5f6abd4 3 *
131b17d4 4 * Copyright 2004-2007 Analog Devices Inc.
a5f6abd4 5 *
26fdc1f0 6 * Enter bugs at http://blackfin.uclinux.org/
a5f6abd4 7 *
26fdc1f0 8 * Licensed under the GPL-2 or later.
a5f6abd4
WB		 9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
131b17d4 13#include <linux/delay.h>
a5f6abd4 14#include <linux/device.h>
131b17d4 15#include <linux/io.h>
a5f6abd4 16#include <linux/ioport.h>
131b17d4 17#include <linux/irq.h>
a5f6abd4
WB		 18#include <linux/errno.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22#include <linux/spi/spi.h>
23#include <linux/workqueue.h>
a5f6abd4 24
a5f6abd4 25#include <asm/dma.h>
131b17d4 26#include <asm/portmux.h>
a5f6abd4 27#include <asm/bfin5xx_spi.h>
8cf5858c
VM		 28#include <asm/cacheflush.h>
29
a32c691d
BW		 30#define DRV_NAME "bfin-spi"
31#define DRV_AUTHOR "Bryan Wu, Luke Yang"
6b1a8028 32#define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
a32c691d
BW		 33#define DRV_VERSION "1.0"
34
35MODULE_AUTHOR(DRV_AUTHOR);
36MODULE_DESCRIPTION(DRV_DESC);
a5f6abd4
WB		 37MODULE_LICENSE("GPL");
38
bb90eb00 39#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
a5f6abd4 40
bb90eb00
BW		 41#define START_STATE ((void *)0)
42#define RUNNING_STATE ((void *)1)
43#define DONE_STATE ((void *)2)
44#define ERROR_STATE ((void *)-1)
45#define QUEUE_RUNNING 0
46#define QUEUE_STOPPED 1
a5f6abd4
WB		 47
48struct driver_data {
49 /* Driver model hookup */
50 struct platform_device *pdev;
51
52 /* SPI framework hookup */
53 struct spi_master *master;
54
bb90eb00 55 /* Regs base of SPI controller */
f452126c 56 void __iomem *regs_base;
bb90eb00 57
003d9226
BW		 58 /* Pin request list */
59 u16 *pin_req;
60
a5f6abd4
WB		 61 /* BFIN hookup */
62 struct bfin5xx_spi_master *master_info;
63
64 /* Driver message queue */
65 struct workqueue_struct *workqueue;
66 struct work_struct pump_messages;
67 spinlock_t lock;
68 struct list_head queue;
69 int busy;
70 int run;
71
72 /* Message Transfer pump */
73 struct tasklet_struct pump_transfers;
74
75 /* Current message transfer state info */
76 struct spi_message *cur_msg;
77 struct spi_transfer *cur_transfer;
78 struct chip_data *cur_chip;
79 size_t len_in_bytes;
80 size_t len;
81 void *tx;
82 void *tx_end;
83 void *rx;
84 void *rx_end;
bb90eb00
BW		 85
86 /* DMA stuffs */
87 int dma_channel;
a5f6abd4 88 int dma_mapped;
bb90eb00 89 int dma_requested;
a5f6abd4
WB		 90 dma_addr_t rx_dma;
91 dma_addr_t tx_dma;
bb90eb00 92
a5f6abd4
WB		 93 size_t rx_map_len;
94 size_t tx_map_len;
95 u8 n_bytes;
fad91c89 96 int cs_change;
a5f6abd4
WB		 97 void (*write) (struct driver_data *);
98 void (*read) (struct driver_data *);
99 void (*duplex) (struct driver_data *);
100};
101
102struct chip_data {
103 u16 ctl_reg;
104 u16 baud;
105 u16 flag;
106
107 u8 chip_select_num;
108 u8 n_bytes;
88b40369 109 u8 width; /* 0 or 1 */
a5f6abd4
WB		 110 u8 enable_dma;
111 u8 bits_per_word; /* 8 or 16 */
112 u8 cs_change_per_word;
62310e51 113 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
a5f6abd4
WB		 114 void (*write) (struct driver_data *);
115 void (*read) (struct driver_data *);
116 void (*duplex) (struct driver_data *);
117};
118
bb90eb00
BW		 119#define DEFINE_SPI_REG(reg, off) \
120static inline u16 read_##reg(struct driver_data *drv_data) \
121 { return bfin_read16(drv_data->regs_base + off); } \
122static inline void write_##reg(struct driver_data *drv_data, u16 v) \
123 { bfin_write16(drv_data->regs_base + off, v); }
124
125DEFINE_SPI_REG(CTRL, 0x00)
126DEFINE_SPI_REG(FLAG, 0x04)
127DEFINE_SPI_REG(STAT, 0x08)
128DEFINE_SPI_REG(TDBR, 0x0C)
129DEFINE_SPI_REG(RDBR, 0x10)
130DEFINE_SPI_REG(BAUD, 0x14)
131DEFINE_SPI_REG(SHAW, 0x18)
132
88b40369 133static void bfin_spi_enable(struct driver_data *drv_data)
a5f6abd4
WB		 134{
135 u16 cr;
136
bb90eb00
BW		 137 cr = read_CTRL(drv_data);
138 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
a5f6abd4
WB		 139}
140
88b40369 141static void bfin_spi_disable(struct driver_data *drv_data)
a5f6abd4
WB		 142{
143 u16 cr;
144
bb90eb00
BW		 145 cr = read_CTRL(drv_data);
146 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
a5f6abd4
WB		 147}
148
149/* Caculate the SPI_BAUD register value based on input HZ */
150static u16 hz_to_spi_baud(u32 speed_hz)
151{
152 u_long sclk = get_sclk();
153 u16 spi_baud = (sclk / (2 * speed_hz));
154
155 if ((sclk % (2 * speed_hz)) > 0)
156 spi_baud++;
157
7513e006
MH		 158 if (spi_baud < MIN_SPI_BAUD_VAL)
159 spi_baud = MIN_SPI_BAUD_VAL;
160
a5f6abd4
WB		 161 return spi_baud;
162}
163
164static int flush(struct driver_data *drv_data)
165{
166 unsigned long limit = loops_per_jiffy << 1;
167
168 /* wait for stop and clear stat */
bb90eb00 169 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
d8c05008 170 cpu_relax();
a5f6abd4 171
bb90eb00 172 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4
WB		 173
174 return limit;
175}
176
fad91c89 177/* Chip select operation functions for cs_change flag */
bb90eb00 178static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 179{
bb90eb00 180 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 181
182 flag |= chip->flag;
183 flag &= ~(chip->flag << 8);
184
bb90eb00 185 write_FLAG(drv_data, flag);
fad91c89
BW		 186}
187
bb90eb00 188static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 189{
bb90eb00 190 u16 flag = read_FLAG(drv_data);
fad91c89 191
2cf36834 192 flag &= ~chip->flag;
fad91c89
BW		 193 flag |= (chip->flag << 8);
194
bb90eb00 195 write_FLAG(drv_data, flag);
62310e51
BW		 196
197 /* Move delay here for consistency */
198 if (chip->cs_chg_udelay)
199 udelay(chip->cs_chg_udelay);
fad91c89
BW		 200}
201
a5f6abd4 202/* stop controller and re-config current chip*/
8d20d0a7 203static void restore_state(struct driver_data *drv_data)
a5f6abd4
WB		 204{
205 struct chip_data *chip = drv_data->cur_chip;
12e17c42 206
a5f6abd4 207 /* Clear status and disable clock */
bb90eb00 208 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4 209 bfin_spi_disable(drv_data);
88b40369 210 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
a5f6abd4 211
5fec5b5a 212 /* Load the registers */
bb90eb00 213 write_CTRL(drv_data, chip->ctl_reg);
092e1fda 214 write_BAUD(drv_data, chip->baud);
cc487e73
SZ		 215
216 bfin_spi_enable(drv_data);
07612e5f 217 cs_active(drv_data, chip);
a5f6abd4
WB		 218}
219
220/* used to kick off transfer in rx mode */
bb90eb00 221static unsigned short dummy_read(struct driver_data *drv_data)
a5f6abd4
WB		 222{
223 unsigned short tmp;
bb90eb00 224 tmp = read_RDBR(drv_data);
a5f6abd4
WB		 225 return tmp;
226}
227
228static void null_writer(struct driver_data *drv_data)
229{
230 u8 n_bytes = drv_data->n_bytes;
231
232 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 233 write_TDBR(drv_data, 0);
234 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 235 cpu_relax();
a5f6abd4
WB		 236 drv_data->tx += n_bytes;
237 }
238}
239
240static void null_reader(struct driver_data *drv_data)
241{
242 u8 n_bytes = drv_data->n_bytes;
bb90eb00 243 dummy_read(drv_data);
a5f6abd4
WB		 244
245 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 246 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 247 cpu_relax();
bb90eb00 248 dummy_read(drv_data);
a5f6abd4
WB		 249 drv_data->rx += n_bytes;
250 }
251}
252
253static void u8_writer(struct driver_data *drv_data)
254{
131b17d4 255 dev_dbg(&drv_data->pdev->dev,
bb90eb00 256 "cr8-s is 0x%x\n", read_STAT(drv_data));
cc487e73 257
a5f6abd4 258 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 259 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
260 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 261 cpu_relax();
a5f6abd4
WB		 262 ++drv_data->tx;
263 }
13f3e642
SZ		 264
265 /* poll for SPI completion before return */
266 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
267 cpu_relax();
a5f6abd4
WB		 268}
269
270static void u8_cs_chg_writer(struct driver_data *drv_data)
271{
272 struct chip_data *chip = drv_data->cur_chip;
273
274 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 275 cs_active(drv_data, chip);
a5f6abd4 276
bb90eb00
BW		 277 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
278 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 279 cpu_relax();
e26aa015
BW		 280 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
281 cpu_relax();
62310e51 282
bb90eb00 283 cs_deactive(drv_data, chip);
5fec5b5a 284
a5f6abd4
WB		 285 ++drv_data->tx;
286 }
a5f6abd4
WB		 287}
288
289static void u8_reader(struct driver_data *drv_data)
290{
131b17d4 291 dev_dbg(&drv_data->pdev->dev,
bb90eb00 292 "cr-8 is 0x%x\n", read_STAT(drv_data));
a5f6abd4 293
3f479a65 294 /* poll for SPI completion before start */
bb90eb00 295 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 296 cpu_relax();
3f479a65 297
a5f6abd4 298 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 299 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 300
bb90eb00 301 dummy_read(drv_data);
cc487e73 302
a5f6abd4 303 while (drv_data->rx < drv_data->rx_end - 1) {
bb90eb00 304 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 305 cpu_relax();
bb90eb00 306 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 307 ++drv_data->rx;
308 }
309
bb90eb00 310 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 311 cpu_relax();
bb90eb00 312 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 313 ++drv_data->rx;
314}
315
316static void u8_cs_chg_reader(struct driver_data *drv_data)
317{
318 struct chip_data *chip = drv_data->cur_chip;
319
e26aa015
BW		 320 while (drv_data->rx < drv_data->rx_end) {
321 cs_active(drv_data, chip);
322 read_RDBR(drv_data); /* kick off */
a5f6abd4 323
e26aa015
BW		 324 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
325 cpu_relax();
326 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
327 cpu_relax();
cc487e73 328
e26aa015 329 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
bb90eb00 330 cs_deactive(drv_data, chip);
5fec5b5a 331
a5f6abd4
WB		 332 ++drv_data->rx;
333 }
a5f6abd4
WB		 334}
335
336static void u8_duplex(struct driver_data *drv_data)
337{
338 /* in duplex mode, clk is triggered by writing of TDBR */
339 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 340 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
4fd432d9 341 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 342 cpu_relax();
bb90eb00 343 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 344 cpu_relax();
bb90eb00 345 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 346 ++drv_data->rx;
347 ++drv_data->tx;
348 }
349}
350
351static void u8_cs_chg_duplex(struct driver_data *drv_data)
352{
353 struct chip_data *chip = drv_data->cur_chip;
354
355 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 356 cs_active(drv_data, chip);
5fec5b5a 357
bb90eb00 358 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
e26aa015
BW		 359
360 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 361 cpu_relax();
bb90eb00 362 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 363 cpu_relax();
bb90eb00 364 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 365
bb90eb00 366 cs_deactive(drv_data, chip);
5fec5b5a 367
a5f6abd4
WB		 368 ++drv_data->rx;
369 ++drv_data->tx;
370 }
a5f6abd4
WB		 371}
372
373static void u16_writer(struct driver_data *drv_data)
374{
131b17d4 375 dev_dbg(&drv_data->pdev->dev,
bb90eb00 376 "cr16 is 0x%x\n", read_STAT(drv_data));
88b40369 377
a5f6abd4 378 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 379 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
380 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 381 cpu_relax();
a5f6abd4
WB		 382 drv_data->tx += 2;
383 }
13f3e642
SZ		 384
385 /* poll for SPI completion before return */
386 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
387 cpu_relax();
a5f6abd4
WB		 388}
389
390static void u16_cs_chg_writer(struct driver_data *drv_data)
391{
392 struct chip_data *chip = drv_data->cur_chip;
393
394 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 395 cs_active(drv_data, chip);
a5f6abd4 396
bb90eb00
BW		 397 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
398 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 399 cpu_relax();
13f3e642
SZ		 400 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
401 cpu_relax();
62310e51 402
bb90eb00 403 cs_deactive(drv_data, chip);
5fec5b5a 404
a5f6abd4
WB		 405 drv_data->tx += 2;
406 }
a5f6abd4
WB		 407}
408
409static void u16_reader(struct driver_data *drv_data)
410{
88b40369 411 dev_dbg(&drv_data->pdev->dev,
bb90eb00 412 "cr-16 is 0x%x\n", read_STAT(drv_data));
cc487e73 413
3f479a65 414 /* poll for SPI completion before start */
bb90eb00 415 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 416 cpu_relax();
3f479a65 417
cc487e73 418 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 419 write_TDBR(drv_data, 0xFFFF);
cc487e73 420
bb90eb00 421 dummy_read(drv_data);
a5f6abd4
WB		 422
423 while (drv_data->rx < (drv_data->rx_end - 2)) {
bb90eb00 424 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 425 cpu_relax();
bb90eb00 426 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 427 drv_data->rx += 2;
428 }
429
bb90eb00 430 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 431 cpu_relax();
bb90eb00 432 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 433 drv_data->rx += 2;
434}
435
436static void u16_cs_chg_reader(struct driver_data *drv_data)
437{
438 struct chip_data *chip = drv_data->cur_chip;
439
3f479a65 440 /* poll for SPI completion before start */
bb90eb00 441 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 442 cpu_relax();
3f479a65 443
cc487e73 444 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 445 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 446
bb90eb00
BW		 447 cs_active(drv_data, chip);
448 dummy_read(drv_data);
cc487e73 449
c3061abb 450 while (drv_data->rx < drv_data->rx_end - 2) {
bb90eb00 451 cs_deactive(drv_data, chip);
5fec5b5a 452
bb90eb00 453 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 454 cpu_relax();
bb90eb00
BW		 455 cs_active(drv_data, chip);
456 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 457 drv_data->rx += 2;
458 }
bb90eb00 459 cs_deactive(drv_data, chip);
cc487e73 460
bb90eb00 461 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 462 cpu_relax();
bb90eb00 463 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
cc487e73 464 drv_data->rx += 2;
a5f6abd4
WB		 465}
466
467static void u16_duplex(struct driver_data *drv_data)
468{
469 /* in duplex mode, clk is triggered by writing of TDBR */
470 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 471 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
4fd432d9 472 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 473 cpu_relax();
bb90eb00 474 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 475 cpu_relax();
bb90eb00 476 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 477 drv_data->rx += 2;
478 drv_data->tx += 2;
479 }
480}
481
482static void u16_cs_chg_duplex(struct driver_data *drv_data)
483{
484 struct chip_data *chip = drv_data->cur_chip;
485
486 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 487 cs_active(drv_data, chip);
a5f6abd4 488
bb90eb00 489 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
4fd432d9 490 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 491 cpu_relax();
bb90eb00 492 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 493 cpu_relax();
bb90eb00 494 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 495
bb90eb00 496 cs_deactive(drv_data, chip);
5fec5b5a 497
a5f6abd4
WB		 498 drv_data->rx += 2;
499 drv_data->tx += 2;
500 }
a5f6abd4
WB		 501}
502
503/* test if ther is more transfer to be done */
504static void *next_transfer(struct driver_data *drv_data)
505{
506 struct spi_message *msg = drv_data->cur_msg;
507 struct spi_transfer *trans = drv_data->cur_transfer;
508
509 /* Move to next transfer */
510 if (trans->transfer_list.next != &msg->transfers) {
511 drv_data->cur_transfer =
512 list_entry(trans->transfer_list.next,
513 struct spi_transfer, transfer_list);
514 return RUNNING_STATE;
515 } else
516 return DONE_STATE;
517}
518
519/*
520 * caller already set message->status;
521 * dma and pio irqs are blocked give finished message back
522 */
523static void giveback(struct driver_data *drv_data)
524{
fad91c89 525 struct chip_data *chip = drv_data->cur_chip;
a5f6abd4
WB		 526 struct spi_transfer *last_transfer;
527 unsigned long flags;
528 struct spi_message *msg;
529
530 spin_lock_irqsave(&drv_data->lock, flags);
531 msg = drv_data->cur_msg;
532 drv_data->cur_msg = NULL;
533 drv_data->cur_transfer = NULL;
534 drv_data->cur_chip = NULL;
535 queue_work(drv_data->workqueue, &drv_data->pump_messages);
536 spin_unlock_irqrestore(&drv_data->lock, flags);
537
538 last_transfer = list_entry(msg->transfers.prev,
539 struct spi_transfer, transfer_list);
540
541 msg->state = NULL;
542
fad91c89 543 if (!drv_data->cs_change)
bb90eb00 544 cs_deactive(drv_data, chip);
fad91c89 545
b9b2a76a
YL		 546 /* Not stop spi in autobuffer mode */
547 if (drv_data->tx_dma != 0xFFFF)
548 bfin_spi_disable(drv_data);
549
a5f6abd4
WB		 550 if (msg->complete)
551 msg->complete(msg->context);
552}
553
88b40369 554static irqreturn_t dma_irq_handler(int irq, void *dev_id)
a5f6abd4 555{
15aafa2f 556 struct driver_data *drv_data = dev_id;
fad91c89 557 struct chip_data *chip = drv_data->cur_chip;
bb90eb00 558 struct spi_message *msg = drv_data->cur_msg;
aaaf939c 559 unsigned long timeout;
d24bd1d0 560 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
04b95d2f 561 u16 spistat = read_STAT(drv_data);
a5f6abd4 562
d24bd1d0
MF		 563 dev_dbg(&drv_data->pdev->dev,
564 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
565 dmastat, spistat);
566
bb90eb00 567 clear_dma_irqstat(drv_data->dma_channel);
a5f6abd4 568
d6fe89b0 569 /* Wait for DMA to complete */
bb90eb00 570 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
d8c05008 571 cpu_relax();
d6fe89b0 572
a5f6abd4 573 /*
d6fe89b0
BW		 574 * wait for the last transaction shifted out. HRM states:
575 * at this point there may still be data in the SPI DMA FIFO waiting
576 * to be transmitted ... software needs to poll TXS in the SPI_STAT
577 * register until it goes low for 2 successive reads
a5f6abd4
WB		 578 */
579 if (drv_data->tx != NULL) {
bb90eb00
BW		 580 while ((read_STAT(drv_data) & TXS) ||
581 (read_STAT(drv_data) & TXS))
d8c05008 582 cpu_relax();
a5f6abd4
WB		 583 }
584
aaaf939c
MF		 585 dev_dbg(&drv_data->pdev->dev,
586 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
587 dmastat, read_STAT(drv_data));
588
589 timeout = jiffies + HZ;
bb90eb00 590 while (!(read_STAT(drv_data) & SPIF))
aaaf939c
MF		 591 if (!time_before(jiffies, timeout)) {
592 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
593 break;
594 } else
595 cpu_relax();
a5f6abd4 596
40a2945b 597 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
04b95d2f
MF		 598 msg->state = ERROR_STATE;
599 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
600 } else {
601 msg->actual_length += drv_data->len_in_bytes;
a5f6abd4 602
04b95d2f
MF		 603 if (drv_data->cs_change)
604 cs_deactive(drv_data, chip);
fad91c89 605
04b95d2f
MF		 606 /* Move to next transfer */
607 msg->state = next_transfer(drv_data);
608 }
a5f6abd4
WB		 609
610 /* Schedule transfer tasklet */
611 tasklet_schedule(&drv_data->pump_transfers);
612
613 /* free the irq handler before next transfer */
88b40369
BW		 614 dev_dbg(&drv_data->pdev->dev,
615 "disable dma channel irq%d\n",
bb90eb00
BW		 616 drv_data->dma_channel);
617 dma_disable_irq(drv_data->dma_channel);
a5f6abd4
WB		 618
619 return IRQ_HANDLED;
620}
621
622static void pump_transfers(unsigned long data)
623{
624 struct driver_data *drv_data = (struct driver_data *)data;
625 struct spi_message *message = NULL;
626 struct spi_transfer *transfer = NULL;
627 struct spi_transfer *previous = NULL;
628 struct chip_data *chip = NULL;
88b40369
BW		 629 u8 width;
630 u16 cr, dma_width, dma_config;
a5f6abd4 631 u32 tranf_success = 1;
8eeb12e5 632 u8 full_duplex = 0;
a5f6abd4
WB		 633
634 /* Get current state information */
635 message = drv_data->cur_msg;
636 transfer = drv_data->cur_transfer;
637 chip = drv_data->cur_chip;
092e1fda 638
a5f6abd4
WB		 639 /*
640 * if msg is error or done, report it back using complete() callback
641 */
642
643 /* Handle for abort */
644 if (message->state == ERROR_STATE) {
d24bd1d0 645 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
a5f6abd4
WB		 646 message->status = -EIO;
647 giveback(drv_data);
648 return;
649 }
650
651 /* Handle end of message */
652 if (message->state == DONE_STATE) {
d24bd1d0 653 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
a5f6abd4
WB		 654 message->status = 0;
655 giveback(drv_data);
656 return;
657 }
658
659 /* Delay if requested at end of transfer */
660 if (message->state == RUNNING_STATE) {
d24bd1d0 661 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
a5f6abd4
WB		 662 previous = list_entry(transfer->transfer_list.prev,
663 struct spi_transfer, transfer_list);
664 if (previous->delay_usecs)
665 udelay(previous->delay_usecs);
666 }
667
668 /* Setup the transfer state based on the type of transfer */
669 if (flush(drv_data) == 0) {
670 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
671 message->status = -EIO;
672 giveback(drv_data);
673 return;
674 }
675
676 if (transfer->tx_buf != NULL) {
677 drv_data->tx = (void *)transfer->tx_buf;
678 drv_data->tx_end = drv_data->tx + transfer->len;
88b40369
BW		 679 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
680 transfer->tx_buf, drv_data->tx_end);
a5f6abd4
WB		 681 } else {
682 drv_data->tx = NULL;
683 }
684
685 if (transfer->rx_buf != NULL) {
8eeb12e5 686 full_duplex = transfer->tx_buf != NULL;
a5f6abd4
WB		 687 drv_data->rx = transfer->rx_buf;
688 drv_data->rx_end = drv_data->rx + transfer->len;
88b40369
BW		 689 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
690 transfer->rx_buf, drv_data->rx_end);
a5f6abd4
WB		 691 } else {
692 drv_data->rx = NULL;
693 }
694
695 drv_data->rx_dma = transfer->rx_dma;
696 drv_data->tx_dma = transfer->tx_dma;
697 drv_data->len_in_bytes = transfer->len;
fad91c89 698 drv_data->cs_change = transfer->cs_change;
a5f6abd4 699
092e1fda
BW		 700 /* Bits per word setup */
701 switch (transfer->bits_per_word) {
702 case 8:
703 drv_data->n_bytes = 1;
704 width = CFG_SPI_WORDSIZE8;
705 drv_data->read = chip->cs_change_per_word ?
706 u8_cs_chg_reader : u8_reader;
707 drv_data->write = chip->cs_change_per_word ?
708 u8_cs_chg_writer : u8_writer;
709 drv_data->duplex = chip->cs_change_per_word ?
710 u8_cs_chg_duplex : u8_duplex;
711 break;
712
713 case 16:
714 drv_data->n_bytes = 2;
715 width = CFG_SPI_WORDSIZE16;
716 drv_data->read = chip->cs_change_per_word ?
717 u16_cs_chg_reader : u16_reader;
718 drv_data->write = chip->cs_change_per_word ?
719 u16_cs_chg_writer : u16_writer;
720 drv_data->duplex = chip->cs_change_per_word ?
721 u16_cs_chg_duplex : u16_duplex;
722 break;
723
724 default:
725 /* No change, the same as default setting */
726 drv_data->n_bytes = chip->n_bytes;
727 width = chip->width;
728 drv_data->write = drv_data->tx ? chip->write : null_writer;
729 drv_data->read = drv_data->rx ? chip->read : null_reader;
730 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
731 break;
732 }
733 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
734 cr |= (width << 8);
735 write_CTRL(drv_data, cr);
736
a5f6abd4
WB		 737 if (width == CFG_SPI_WORDSIZE16) {
738 drv_data->len = (transfer->len) >> 1;
739 } else {
740 drv_data->len = transfer->len;
741 }
4fb98efa
MF		 742 dev_dbg(&drv_data->pdev->dev,
743 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
131b17d4 744 drv_data->write, chip->write, null_writer);
a5f6abd4
WB		 745
746 /* speed and width has been set on per message */
747 message->state = RUNNING_STATE;
748 dma_config = 0;
749
092e1fda
BW		 750 /* Speed setup (surely valid because already checked) */
751 if (transfer->speed_hz)
752 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
753 else
754 write_BAUD(drv_data, chip->baud);
755
bb90eb00
BW		 756 write_STAT(drv_data, BIT_STAT_CLR);
757 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
b9b2a76a
YL		 758 if (drv_data->cs_change)
759 cs_active(drv_data, chip);
a5f6abd4 760
88b40369
BW		 761 dev_dbg(&drv_data->pdev->dev,
762 "now pumping a transfer: width is %d, len is %d\n",
763 width, transfer->len);
a5f6abd4
WB		 764
765 /*
8cf5858c
VM		 766 * Try to map dma buffer and do a dma transfer. If successful use,
767 * different way to r/w according to the enable_dma settings and if
768 * we are not doing a full duplex transfer (since the hardware does
769 * not support full duplex DMA transfers).
a5f6abd4 770 */
8eeb12e5
VM		 771 if (!full_duplex && drv_data->cur_chip->enable_dma
772 && drv_data->len > 6) {
a5f6abd4 773
11d6f599 774 unsigned long dma_start_addr, flags;
7aec3566 775
bb90eb00
BW		 776 disable_dma(drv_data->dma_channel);
777 clear_dma_irqstat(drv_data->dma_channel);
a5f6abd4
WB		 778
779 /* config dma channel */
88b40369 780 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
7aec3566 781 set_dma_x_count(drv_data->dma_channel, drv_data->len);
a5f6abd4 782 if (width == CFG_SPI_WORDSIZE16) {
bb90eb00 783 set_dma_x_modify(drv_data->dma_channel, 2);
a5f6abd4
WB		 784 dma_width = WDSIZE_16;
785 } else {
bb90eb00 786 set_dma_x_modify(drv_data->dma_channel, 1);
a5f6abd4
WB		 787 dma_width = WDSIZE_8;
788 }
789
3f479a65 790 /* poll for SPI completion before start */
bb90eb00 791 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 792 cpu_relax();
3f479a65 793
a5f6abd4
WB		 794 /* dirty hack for autobuffer DMA mode */
795 if (drv_data->tx_dma == 0xFFFF) {
88b40369
BW		 796 dev_dbg(&drv_data->pdev->dev,
797 "doing autobuffer DMA out.\n");
a5f6abd4
WB		 798
799 /* no irq in autobuffer mode */
800 dma_config =
801 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
bb90eb00
BW		 802 set_dma_config(drv_data->dma_channel, dma_config);
803 set_dma_start_addr(drv_data->dma_channel,
a32c691d 804 (unsigned long)drv_data->tx);
bb90eb00 805 enable_dma(drv_data->dma_channel);
a5f6abd4 806
07612e5f 807 /* start SPI transfer */
11d6f599 808 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
07612e5f
SZ		 809
810 /* just return here, there can only be one transfer
811 * in this mode
812 */
a5f6abd4
WB		 813 message->status = 0;
814 giveback(drv_data);
815 return;
816 }
817
818 /* In dma mode, rx or tx must be NULL in one transfer */
7aec3566 819 dma_config = (RESTART | dma_width | DI_EN);
a5f6abd4
WB		 820 if (drv_data->rx != NULL) {
821 /* set transfer mode, and enable SPI */
d24bd1d0
MF		 822 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
823 drv_data->rx, drv_data->len_in_bytes);
a5f6abd4 824
8cf5858c
VM		 825 /* invalidate caches, if needed */
826 if (bfin_addr_dcachable((unsigned long) drv_data->rx))
827 invalidate_dcache_range((unsigned long) drv_data->rx,
828 (unsigned long) (drv_data->rx +
ace32865 829 drv_data->len_in_bytes));
8cf5858c 830
a5f6abd4 831 /* clear tx reg soformer data is not shifted out */
bb90eb00 832 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 833
7aec3566
MF		 834 dma_config |= WNR;
835 dma_start_addr = (unsigned long)drv_data->rx;
b31e27a6 836 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
07612e5f 837
a5f6abd4 838 } else if (drv_data->tx != NULL) {
88b40369 839 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
a5f6abd4 840
8cf5858c
VM		 841 /* flush caches, if needed */
842 if (bfin_addr_dcachable((unsigned long) drv_data->tx))
843 flush_dcache_range((unsigned long) drv_data->tx,
844 (unsigned long) (drv_data->tx +
ace32865 845 drv_data->len_in_bytes));
8cf5858c 846
7aec3566 847 dma_start_addr = (unsigned long)drv_data->tx;
b31e27a6 848 cr |= BIT_CTL_TIMOD_DMA_TX;
7aec3566
MF		 849
850 } else
851 BUG();
852
11d6f599
MF		 853 /* oh man, here there be monsters ... and i dont mean the
854 * fluffy cute ones from pixar, i mean the kind that'll eat
855 * your data, kick your dog, and love it all. do *not* try
856 * and change these lines unless you (1) heavily test DMA
857 * with SPI flashes on a loaded system (e.g. ping floods),
858 * (2) know just how broken the DMA engine interaction with
859 * the SPI peripheral is, and (3) have someone else to blame
860 * when you screw it all up anyways.
861 */
7aec3566 862 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
11d6f599
MF		 863 set_dma_config(drv_data->dma_channel, dma_config);
864 local_irq_save(flags);
a963ea83 865 SSYNC();
11d6f599 866 write_CTRL(drv_data, cr);
a963ea83 867 enable_dma(drv_data->dma_channel);
11d6f599
MF		 868 dma_enable_irq(drv_data->dma_channel);
869 local_irq_restore(flags);
07612e5f 870
a5f6abd4
WB		 871 } else {
872 /* IO mode write then read */
88b40369 873 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
a5f6abd4 874
8eeb12e5 875 if (full_duplex) {
a5f6abd4
WB		 876 /* full duplex mode */
877 BUG_ON((drv_data->tx_end - drv_data->tx) !=
878 (drv_data->rx_end - drv_data->rx));
88b40369
BW		 879 dev_dbg(&drv_data->pdev->dev,
880 "IO duplex: cr is 0x%x\n", cr);
a5f6abd4 881
cc487e73 882 /* set SPI transfer mode */
bb90eb00 883 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 884
885 drv_data->duplex(drv_data);
886
887 if (drv_data->tx != drv_data->tx_end)
888 tranf_success = 0;
889 } else if (drv_data->tx != NULL) {
890 /* write only half duplex */
131b17d4 891 dev_dbg(&drv_data->pdev->dev,
88b40369 892 "IO write: cr is 0x%x\n", cr);
a5f6abd4 893
cc487e73 894 /* set SPI transfer mode */
bb90eb00 895 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 896
897 drv_data->write(drv_data);
898
899 if (drv_data->tx != drv_data->tx_end)
900 tranf_success = 0;
901 } else if (drv_data->rx != NULL) {
902 /* read only half duplex */
131b17d4 903 dev_dbg(&drv_data->pdev->dev,
88b40369 904 "IO read: cr is 0x%x\n", cr);
a5f6abd4 905
cc487e73 906 /* set SPI transfer mode */
bb90eb00 907 write_CTRL(drv_data, (cr | CFG_SPI_READ));
a5f6abd4
WB		 908
909 drv_data->read(drv_data);
910 if (drv_data->rx != drv_data->rx_end)
911 tranf_success = 0;
912 }
913
914 if (!tranf_success) {
131b17d4 915 dev_dbg(&drv_data->pdev->dev,
88b40369 916 "IO write error!\n");
a5f6abd4
WB		 917 message->state = ERROR_STATE;
918 } else {
919 /* Update total byte transfered */
ace32865 920 message->actual_length += drv_data->len_in_bytes;
a5f6abd4
WB		 921 /* Move to next transfer of this msg */
922 message->state = next_transfer(drv_data);
b9b2a76a
YL		 923 if (drv_data->cs_change)
924 cs_deactive(drv_data, chip);
a5f6abd4 925 }
a5f6abd4
WB		 926 /* Schedule next transfer tasklet */
927 tasklet_schedule(&drv_data->pump_transfers);
928
929 }
930}
931
932/* pop a msg from queue and kick off real transfer */
933static void pump_messages(struct work_struct *work)
934{
131b17d4 935 struct driver_data *drv_data;
a5f6abd4
WB		 936 unsigned long flags;
937
131b17d4
BW		 938 drv_data = container_of(work, struct driver_data, pump_messages);
939
a5f6abd4
WB		 940 /* Lock queue and check for queue work */
941 spin_lock_irqsave(&drv_data->lock, flags);
942 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
943 /* pumper kicked off but no work to do */
944 drv_data->busy = 0;
945 spin_unlock_irqrestore(&drv_data->lock, flags);
946 return;
947 }
948
949 /* Make sure we are not already running a message */
950 if (drv_data->cur_msg) {
951 spin_unlock_irqrestore(&drv_data->lock, flags);
952 return;
953 }
954
955 /* Extract head of queue */
956 drv_data->cur_msg = list_entry(drv_data->queue.next,
957 struct spi_message, queue);
5fec5b5a
BW		 958
959 /* Setup the SSP using the per chip configuration */
960 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
8d20d0a7 961 restore_state(drv_data);
5fec5b5a 962
a5f6abd4
WB		 963 list_del_init(&drv_data->cur_msg->queue);
964
965 /* Initial message state */
966 drv_data->cur_msg->state = START_STATE;
967 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
968 struct spi_transfer, transfer_list);
969
5fec5b5a
BW		 970 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
971 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
972 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
973 drv_data->cur_chip->ctl_reg);
131b17d4
BW		 974
975 dev_dbg(&drv_data->pdev->dev,
88b40369
BW		 976 "the first transfer len is %d\n",
977 drv_data->cur_transfer->len);
a5f6abd4
WB		 978
979 /* Mark as busy and launch transfers */
980 tasklet_schedule(&drv_data->pump_transfers);
981
982 drv_data->busy = 1;
983 spin_unlock_irqrestore(&drv_data->lock, flags);
984}
985
986/*
987 * got a msg to transfer, queue it in drv_data->queue.
988 * And kick off message pumper
989 */
990static int transfer(struct spi_device *spi, struct spi_message *msg)
991{
992 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
993 unsigned long flags;
994
995 spin_lock_irqsave(&drv_data->lock, flags);
996
997 if (drv_data->run == QUEUE_STOPPED) {
998 spin_unlock_irqrestore(&drv_data->lock, flags);
999 return -ESHUTDOWN;
1000 }
1001
1002 msg->actual_length = 0;
1003 msg->status = -EINPROGRESS;
1004 msg->state = START_STATE;
1005
88b40369 1006 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
a5f6abd4
WB		 1007 list_add_tail(&msg->queue, &drv_data->queue);
1008
1009 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1010 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1011
1012 spin_unlock_irqrestore(&drv_data->lock, flags);
1013
1014 return 0;
1015}
1016
12e17c42
SZ		 1017#define MAX_SPI_SSEL 7
1018
4160bde2 1019static u16 ssel[][MAX_SPI_SSEL] = {
12e17c42
SZ		 1020 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1021 P_SPI0_SSEL4, P_SPI0_SSEL5,
1022 P_SPI0_SSEL6, P_SPI0_SSEL7},
1023
1024 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1025 P_SPI1_SSEL4, P_SPI1_SSEL5,
1026 P_SPI1_SSEL6, P_SPI1_SSEL7},
1027
1028 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1029 P_SPI2_SSEL4, P_SPI2_SSEL5,
1030 P_SPI2_SSEL6, P_SPI2_SSEL7},
1031};
1032
a5f6abd4
WB		 1033/* first setup for new devices */
1034static int setup(struct spi_device *spi)
1035{
1036 struct bfin5xx_spi_chip *chip_info = NULL;
1037 struct chip_data *chip;
1038 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
a5f6abd4
WB		 1039
1040 /* Abort device setup if requested features are not supported */
1041 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1042 dev_err(&spi->dev, "requested mode not fully supported\n");
1043 return -EINVAL;
1044 }
1045
1046 /* Zero (the default) here means 8 bits */
1047 if (!spi->bits_per_word)
1048 spi->bits_per_word = 8;
1049
1050 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1051 return -EINVAL;
1052
1053 /* Only alloc (or use chip_info) on first setup */
1054 chip = spi_get_ctldata(spi);
1055 if (chip == NULL) {
1056 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1057 if (!chip)
1058 return -ENOMEM;
1059
1060 chip->enable_dma = 0;
1061 chip_info = spi->controller_data;
1062 }
1063
1064 /* chip_info isn't always needed */
1065 if (chip_info) {
2ed35516
MF		 1066 /* Make sure people stop trying to set fields via ctl_reg
1067 * when they should actually be using common SPI framework.
1068 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1069 * Not sure if a user actually needs/uses any of these,
1070 * but let's assume (for now) they do.
1071 */
1072 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1073 dev_err(&spi->dev, "do not set bits in ctl_reg "
1074 "that the SPI framework manages\n");
1075 return -EINVAL;
1076 }
1077
a5f6abd4
WB		 1078 chip->enable_dma = chip_info->enable_dma != 0
1079 && drv_data->master_info->enable_dma;
1080 chip->ctl_reg = chip_info->ctl_reg;
1081 chip->bits_per_word = chip_info->bits_per_word;
1082 chip->cs_change_per_word = chip_info->cs_change_per_word;
1083 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1084 }
1085
1086 /* translate common spi framework into our register */
1087 if (spi->mode & SPI_CPOL)
1088 chip->ctl_reg |= CPOL;
1089 if (spi->mode & SPI_CPHA)
1090 chip->ctl_reg |= CPHA;
1091 if (spi->mode & SPI_LSB_FIRST)
1092 chip->ctl_reg |= LSBF;
1093 /* we dont support running in slave mode (yet?) */
1094 chip->ctl_reg |= MSTR;
1095
1096 /*
1097 * if any one SPI chip is registered and wants DMA, request the
1098 * DMA channel for it
1099 */
bb90eb00 1100 if (chip->enable_dma && !drv_data->dma_requested) {
a5f6abd4 1101 /* register dma irq handler */
59bfcc66 1102 if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) {
88b40369
BW		 1103 dev_dbg(&spi->dev,
1104 "Unable to request BlackFin SPI DMA channel\n");
a5f6abd4
WB		 1105 return -ENODEV;
1106 }
bb90eb00 1107 if (set_dma_callback(drv_data->dma_channel,
59bfcc66 1108 dma_irq_handler, drv_data) < 0) {
88b40369 1109 dev_dbg(&spi->dev, "Unable to set dma callback\n");
a5f6abd4
WB		 1110 return -EPERM;
1111 }
bb90eb00
BW		 1112 dma_disable_irq(drv_data->dma_channel);
1113 drv_data->dma_requested = 1;
a5f6abd4
WB		 1114 }
1115
1116 /*
1117 * Notice: for blackfin, the speed_hz is the value of register
1118 * SPI_BAUD, not the real baudrate
1119 */
1120 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
2cf36834 1121 chip->flag = 1 << (spi->chip_select);
a5f6abd4
WB		 1122 chip->chip_select_num = spi->chip_select;
1123
1124 switch (chip->bits_per_word) {
1125 case 8:
1126 chip->n_bytes = 1;
1127 chip->width = CFG_SPI_WORDSIZE8;
1128 chip->read = chip->cs_change_per_word ?
1129 u8_cs_chg_reader : u8_reader;
1130 chip->write = chip->cs_change_per_word ?
1131 u8_cs_chg_writer : u8_writer;
1132 chip->duplex = chip->cs_change_per_word ?
1133 u8_cs_chg_duplex : u8_duplex;
1134 break;
1135
1136 case 16:
1137 chip->n_bytes = 2;
1138 chip->width = CFG_SPI_WORDSIZE16;
1139 chip->read = chip->cs_change_per_word ?
1140 u16_cs_chg_reader : u16_reader;
1141 chip->write = chip->cs_change_per_word ?
1142 u16_cs_chg_writer : u16_writer;
1143 chip->duplex = chip->cs_change_per_word ?
1144 u16_cs_chg_duplex : u16_duplex;
1145 break;
1146
1147 default:
1148 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1149 chip->bits_per_word);
1150 kfree(chip);
1151 return -ENODEV;
1152 }
1153
898eb71c 1154 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
a5f6abd4 1155 spi->modalias, chip->width, chip->enable_dma);
88b40369 1156 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
a5f6abd4
WB		 1157 chip->ctl_reg, chip->flag);
1158
1159 spi_set_ctldata(spi, chip);
1160
12e17c42
SZ		 1161 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1162 if ((chip->chip_select_num > 0)
1163 && (chip->chip_select_num <= spi->master->num_chipselect))
1164 peripheral_request(ssel[spi->master->bus_num]
aab0d83e 1165 [chip->chip_select_num-1], spi->modalias);
12e17c42 1166
07612e5f
SZ		 1167 cs_deactive(drv_data, chip);
1168
a5f6abd4
WB		 1169 return 0;
1170}
1171
1172/*
1173 * callback for spi framework.
1174 * clean driver specific data
1175 */
88b40369 1176static void cleanup(struct spi_device *spi)
a5f6abd4 1177{
27bb9e79 1178 struct chip_data *chip = spi_get_ctldata(spi);
a5f6abd4 1179
12e17c42
SZ		 1180 if ((chip->chip_select_num > 0)
1181 && (chip->chip_select_num <= spi->master->num_chipselect))
1182 peripheral_free(ssel[spi->master->bus_num]
1183 [chip->chip_select_num-1]);
1184
a5f6abd4
WB		 1185 kfree(chip);
1186}
1187
1188static inline int init_queue(struct driver_data *drv_data)
1189{
1190 INIT_LIST_HEAD(&drv_data->queue);
1191 spin_lock_init(&drv_data->lock);
1192
1193 drv_data->run = QUEUE_STOPPED;
1194 drv_data->busy = 0;
1195
1196 /* init transfer tasklet */
1197 tasklet_init(&drv_data->pump_transfers,
1198 pump_transfers, (unsigned long)drv_data);
1199
1200 /* init messages workqueue */
1201 INIT_WORK(&drv_data->pump_messages, pump_messages);
6c7377ab
KS		 1202 drv_data->workqueue = create_singlethread_workqueue(
1203 dev_name(drv_data->master->dev.parent));
a5f6abd4
WB		 1204 if (drv_data->workqueue == NULL)
1205 return -EBUSY;
1206
1207 return 0;
1208}
1209
1210static inline int start_queue(struct driver_data *drv_data)
1211{
1212 unsigned long flags;
1213
1214 spin_lock_irqsave(&drv_data->lock, flags);
1215
1216 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1217 spin_unlock_irqrestore(&drv_data->lock, flags);
1218 return -EBUSY;
1219 }
1220
1221 drv_data->run = QUEUE_RUNNING;
1222 drv_data->cur_msg = NULL;
1223 drv_data->cur_transfer = NULL;
1224 drv_data->cur_chip = NULL;
1225 spin_unlock_irqrestore(&drv_data->lock, flags);
1226
1227 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1228
1229 return 0;
1230}
1231
1232static inline int stop_queue(struct driver_data *drv_data)
1233{
1234 unsigned long flags;
1235 unsigned limit = 500;
1236 int status = 0;
1237
1238 spin_lock_irqsave(&drv_data->lock, flags);
1239
1240 /*
1241 * This is a bit lame, but is optimized for the common execution path.
1242 * A wait_queue on the drv_data->busy could be used, but then the common
1243 * execution path (pump_messages) would be required to call wake_up or
1244 * friends on every SPI message. Do this instead
1245 */
1246 drv_data->run = QUEUE_STOPPED;
1247 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1248 spin_unlock_irqrestore(&drv_data->lock, flags);
1249 msleep(10);
1250 spin_lock_irqsave(&drv_data->lock, flags);
1251 }
1252
1253 if (!list_empty(&drv_data->queue) || drv_data->busy)
1254 status = -EBUSY;
1255
1256 spin_unlock_irqrestore(&drv_data->lock, flags);
1257
1258 return status;
1259}
1260
1261static inline int destroy_queue(struct driver_data *drv_data)
1262{
1263 int status;
1264
1265 status = stop_queue(drv_data);
1266 if (status != 0)
1267 return status;
1268
1269 destroy_workqueue(drv_data->workqueue);
1270
1271 return 0;
1272}
1273
1274static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1275{
1276 struct device *dev = &pdev->dev;
1277 struct bfin5xx_spi_master *platform_info;
1278 struct spi_master *master;
1279 struct driver_data *drv_data = 0;
a32c691d 1280 struct resource *res;
a5f6abd4
WB		 1281 int status = 0;
1282
1283 platform_info = dev->platform_data;
1284
1285 /* Allocate master with space for drv_data */
1286 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1287 if (!master) {
1288 dev_err(&pdev->dev, "can not alloc spi_master\n");
1289 return -ENOMEM;
1290 }
131b17d4 1291
a5f6abd4
WB		 1292 drv_data = spi_master_get_devdata(master);
1293 drv_data->master = master;
1294 drv_data->master_info = platform_info;
1295 drv_data->pdev = pdev;
003d9226 1296 drv_data->pin_req = platform_info->pin_req;
a5f6abd4
WB		 1297
1298 master->bus_num = pdev->id;
1299 master->num_chipselect = platform_info->num_chipselect;
1300 master->cleanup = cleanup;
1301 master->setup = setup;
1302 master->transfer = transfer;
1303
a32c691d
BW		 1304 /* Find and map our resources */
1305 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1306 if (res == NULL) {
1307 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1308 status = -ENOENT;
1309 goto out_error_get_res;
1310 }
1311
f452126c
BW		 1312 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1313 if (drv_data->regs_base == NULL) {
a32c691d
BW		 1314 dev_err(dev, "Cannot map IO\n");
1315 status = -ENXIO;
1316 goto out_error_ioremap;
1317 }
1318
bb90eb00
BW		 1319 drv_data->dma_channel = platform_get_irq(pdev, 0);
1320 if (drv_data->dma_channel < 0) {
a32c691d
BW		 1321 dev_err(dev, "No DMA channel specified\n");
1322 status = -ENOENT;
1323 goto out_error_no_dma_ch;
1324 }
1325
a5f6abd4
WB		 1326 /* Initial and start queue */
1327 status = init_queue(drv_data);
1328 if (status != 0) {
a32c691d 1329 dev_err(dev, "problem initializing queue\n");
a5f6abd4
WB		 1330 goto out_error_queue_alloc;
1331 }
a32c691d 1332
a5f6abd4
WB		 1333 status = start_queue(drv_data);
1334 if (status != 0) {
a32c691d 1335 dev_err(dev, "problem starting queue\n");
a5f6abd4
WB		 1336 goto out_error_queue_alloc;
1337 }
1338
f9e522ca
VM		 1339 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1340 if (status != 0) {
1341 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1342 goto out_error_queue_alloc;
1343 }
1344
a5f6abd4
WB		 1345 /* Register with the SPI framework */
1346 platform_set_drvdata(pdev, drv_data);
1347 status = spi_register_master(master);
1348 if (status != 0) {
a32c691d 1349 dev_err(dev, "problem registering spi master\n");
a5f6abd4
WB		 1350 goto out_error_queue_alloc;
1351 }
a32c691d 1352
f452126c 1353 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
bb90eb00
BW		 1354 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1355 drv_data->dma_channel);
a5f6abd4
WB		 1356 return status;
1357
cc2f81a6 1358out_error_queue_alloc:
a5f6abd4 1359 destroy_queue(drv_data);
a32c691d 1360out_error_no_dma_ch:
bb90eb00 1361 iounmap((void *) drv_data->regs_base);
a32c691d
BW		 1362out_error_ioremap:
1363out_error_get_res:
a5f6abd4 1364 spi_master_put(master);
cc2f81a6 1365
a5f6abd4
WB		 1366 return status;
1367}
1368
1369/* stop hardware and remove the driver */
1370static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1371{
1372 struct driver_data *drv_data = platform_get_drvdata(pdev);
1373 int status = 0;
1374
1375 if (!drv_data)
1376 return 0;
1377
1378 /* Remove the queue */
1379 status = destroy_queue(drv_data);
1380 if (status != 0)
1381 return status;
1382
1383 /* Disable the SSP at the peripheral and SOC level */
1384 bfin_spi_disable(drv_data);
1385
1386 /* Release DMA */
1387 if (drv_data->master_info->enable_dma) {
bb90eb00
BW		 1388 if (dma_channel_active(drv_data->dma_channel))
1389 free_dma(drv_data->dma_channel);
a5f6abd4
WB		 1390 }
1391
1392 /* Disconnect from the SPI framework */
1393 spi_unregister_master(drv_data->master);
1394
003d9226 1395 peripheral_free_list(drv_data->pin_req);
cc2f81a6 1396
a5f6abd4
WB		 1397 /* Prevent double remove */
1398 platform_set_drvdata(pdev, NULL);
1399
1400 return 0;
1401}
1402
1403#ifdef CONFIG_PM
1404static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1405{
1406 struct driver_data *drv_data = platform_get_drvdata(pdev);
1407 int status = 0;
1408
1409 status = stop_queue(drv_data);
1410 if (status != 0)
1411 return status;
1412
1413 /* stop hardware */
1414 bfin_spi_disable(drv_data);
1415
1416 return 0;
1417}
1418
1419static int bfin5xx_spi_resume(struct platform_device *pdev)
1420{
1421 struct driver_data *drv_data = platform_get_drvdata(pdev);
1422 int status = 0;
1423
1424 /* Enable the SPI interface */
1425 bfin_spi_enable(drv_data);
1426
1427 /* Start the queue running */
1428 status = start_queue(drv_data);
1429 if (status != 0) {
1430 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1431 return status;
1432 }
1433
1434 return 0;
1435}
1436#else
1437#define bfin5xx_spi_suspend NULL
1438#define bfin5xx_spi_resume NULL
1439#endif /* CONFIG_PM */
1440
7e38c3c4 1441MODULE_ALIAS("platform:bfin-spi");
a5f6abd4 1442static struct platform_driver bfin5xx_spi_driver = {
fc3ba952 1443 .driver = {
a32c691d 1444 .name = DRV_NAME,
88b40369
BW		 1445 .owner = THIS_MODULE,
1446 },
1447 .suspend = bfin5xx_spi_suspend,
1448 .resume = bfin5xx_spi_resume,
1449 .remove = __devexit_p(bfin5xx_spi_remove),
a5f6abd4
WB		 1450};
1451
1452static int __init bfin5xx_spi_init(void)
1453{
88b40369 1454 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
a5f6abd4 1455}
a5f6abd4
WB		 1456module_init(bfin5xx_spi_init);
1457
1458static void __exit bfin5xx_spi_exit(void)
1459{
1460 platform_driver_unregister(&bfin5xx_spi_driver);
1461}
a5f6abd4 1462module_exit(bfin5xx_spi_exit);
Linux 6.x block layer and io_uring tree(s)