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edac: struct device - replace bus_id with dev_name(), dev_set_name()
[linux-2.6-block.git] / drivers / spi / spi_bfin5xx.c
CommitLineData
a5f6abd4 1/*
26fdc1f0 2 * Blackfin On-Chip SPI Driver
a5f6abd4 3 *
131b17d4 4 * Copyright 2004-2007 Analog Devices Inc.
a5f6abd4 5 *
26fdc1f0 6 * Enter bugs at http://blackfin.uclinux.org/
a5f6abd4 7 *
26fdc1f0 8 * Licensed under the GPL-2 or later.
a5f6abd4
WB		 9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
131b17d4 13#include <linux/delay.h>
a5f6abd4 14#include <linux/device.h>
131b17d4 15#include <linux/io.h>
a5f6abd4 16#include <linux/ioport.h>
131b17d4 17#include <linux/irq.h>
a5f6abd4
WB		 18#include <linux/errno.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22#include <linux/spi/spi.h>
23#include <linux/workqueue.h>
a5f6abd4 24
a5f6abd4 25#include <asm/dma.h>
131b17d4 26#include <asm/portmux.h>
a5f6abd4
WB		 27#include <asm/bfin5xx_spi.h>
28
a32c691d
BW		 29#define DRV_NAME "bfin-spi"
30#define DRV_AUTHOR "Bryan Wu, Luke Yang"
6b1a8028 31#define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
a32c691d
BW		 32#define DRV_VERSION "1.0"
33
34MODULE_AUTHOR(DRV_AUTHOR);
35MODULE_DESCRIPTION(DRV_DESC);
a5f6abd4
WB		 36MODULE_LICENSE("GPL");
37
bb90eb00 38#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
a5f6abd4 39
bb90eb00
BW		 40#define START_STATE ((void *)0)
41#define RUNNING_STATE ((void *)1)
42#define DONE_STATE ((void *)2)
43#define ERROR_STATE ((void *)-1)
44#define QUEUE_RUNNING 0
45#define QUEUE_STOPPED 1
a5f6abd4
WB		 46
47struct driver_data {
48 /* Driver model hookup */
49 struct platform_device *pdev;
50
51 /* SPI framework hookup */
52 struct spi_master *master;
53
bb90eb00 54 /* Regs base of SPI controller */
f452126c 55 void __iomem *regs_base;
bb90eb00 56
003d9226
BW		 57 /* Pin request list */
58 u16 *pin_req;
59
a5f6abd4
WB		 60 /* BFIN hookup */
61 struct bfin5xx_spi_master *master_info;
62
63 /* Driver message queue */
64 struct workqueue_struct *workqueue;
65 struct work_struct pump_messages;
66 spinlock_t lock;
67 struct list_head queue;
68 int busy;
69 int run;
70
71 /* Message Transfer pump */
72 struct tasklet_struct pump_transfers;
73
74 /* Current message transfer state info */
75 struct spi_message *cur_msg;
76 struct spi_transfer *cur_transfer;
77 struct chip_data *cur_chip;
78 size_t len_in_bytes;
79 size_t len;
80 void *tx;
81 void *tx_end;
82 void *rx;
83 void *rx_end;
bb90eb00
BW		 84
85 /* DMA stuffs */
86 int dma_channel;
a5f6abd4 87 int dma_mapped;
bb90eb00 88 int dma_requested;
a5f6abd4
WB		 89 dma_addr_t rx_dma;
90 dma_addr_t tx_dma;
bb90eb00 91
a5f6abd4
WB		 92 size_t rx_map_len;
93 size_t tx_map_len;
94 u8 n_bytes;
fad91c89 95 int cs_change;
a5f6abd4
WB		 96 void (*write) (struct driver_data *);
97 void (*read) (struct driver_data *);
98 void (*duplex) (struct driver_data *);
99};
100
101struct chip_data {
102 u16 ctl_reg;
103 u16 baud;
104 u16 flag;
105
106 u8 chip_select_num;
107 u8 n_bytes;
88b40369 108 u8 width; /* 0 or 1 */
a5f6abd4
WB		 109 u8 enable_dma;
110 u8 bits_per_word; /* 8 or 16 */
111 u8 cs_change_per_word;
62310e51 112 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
a5f6abd4
WB		 113 void (*write) (struct driver_data *);
114 void (*read) (struct driver_data *);
115 void (*duplex) (struct driver_data *);
116};
117
bb90eb00
BW		 118#define DEFINE_SPI_REG(reg, off) \
119static inline u16 read_##reg(struct driver_data *drv_data) \
120 { return bfin_read16(drv_data->regs_base + off); } \
121static inline void write_##reg(struct driver_data *drv_data, u16 v) \
122 { bfin_write16(drv_data->regs_base + off, v); }
123
124DEFINE_SPI_REG(CTRL, 0x00)
125DEFINE_SPI_REG(FLAG, 0x04)
126DEFINE_SPI_REG(STAT, 0x08)
127DEFINE_SPI_REG(TDBR, 0x0C)
128DEFINE_SPI_REG(RDBR, 0x10)
129DEFINE_SPI_REG(BAUD, 0x14)
130DEFINE_SPI_REG(SHAW, 0x18)
131
88b40369 132static void bfin_spi_enable(struct driver_data *drv_data)
a5f6abd4
WB		 133{
134 u16 cr;
135
bb90eb00
BW		 136 cr = read_CTRL(drv_data);
137 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
a5f6abd4
WB		 138}
139
88b40369 140static void bfin_spi_disable(struct driver_data *drv_data)
a5f6abd4
WB		 141{
142 u16 cr;
143
bb90eb00
BW		 144 cr = read_CTRL(drv_data);
145 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
a5f6abd4
WB		 146}
147
148/* Caculate the SPI_BAUD register value based on input HZ */
149static u16 hz_to_spi_baud(u32 speed_hz)
150{
151 u_long sclk = get_sclk();
152 u16 spi_baud = (sclk / (2 * speed_hz));
153
154 if ((sclk % (2 * speed_hz)) > 0)
155 spi_baud++;
156
a5f6abd4
WB		 157 return spi_baud;
158}
159
160static int flush(struct driver_data *drv_data)
161{
162 unsigned long limit = loops_per_jiffy << 1;
163
164 /* wait for stop and clear stat */
bb90eb00 165 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
d8c05008 166 cpu_relax();
a5f6abd4 167
bb90eb00 168 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4
WB		 169
170 return limit;
171}
172
fad91c89 173/* Chip select operation functions for cs_change flag */
bb90eb00 174static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 175{
bb90eb00 176 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 177
178 flag |= chip->flag;
179 flag &= ~(chip->flag << 8);
180
bb90eb00 181 write_FLAG(drv_data, flag);
fad91c89
BW		 182}
183
bb90eb00 184static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 185{
bb90eb00 186 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 187
188 flag |= (chip->flag << 8);
189
bb90eb00 190 write_FLAG(drv_data, flag);
62310e51
BW		 191
192 /* Move delay here for consistency */
193 if (chip->cs_chg_udelay)
194 udelay(chip->cs_chg_udelay);
fad91c89
BW		 195}
196
7c4ef094 197#define MAX_SPI_SSEL 7
5fec5b5a 198
a5f6abd4 199/* stop controller and re-config current chip*/
8d20d0a7 200static void restore_state(struct driver_data *drv_data)
a5f6abd4
WB		 201{
202 struct chip_data *chip = drv_data->cur_chip;
12e17c42 203
a5f6abd4 204 /* Clear status and disable clock */
bb90eb00 205 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4 206 bfin_spi_disable(drv_data);
88b40369 207 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
a5f6abd4 208
5fec5b5a 209 /* Load the registers */
bb90eb00 210 write_CTRL(drv_data, chip->ctl_reg);
092e1fda 211 write_BAUD(drv_data, chip->baud);
cc487e73
SZ		 212
213 bfin_spi_enable(drv_data);
07612e5f 214 cs_active(drv_data, chip);
a5f6abd4
WB		 215}
216
217/* used to kick off transfer in rx mode */
bb90eb00 218static unsigned short dummy_read(struct driver_data *drv_data)
a5f6abd4
WB		 219{
220 unsigned short tmp;
bb90eb00 221 tmp = read_RDBR(drv_data);
a5f6abd4
WB		 222 return tmp;
223}
224
225static void null_writer(struct driver_data *drv_data)
226{
227 u8 n_bytes = drv_data->n_bytes;
228
229 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 230 write_TDBR(drv_data, 0);
231 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 232 cpu_relax();
a5f6abd4
WB		 233 drv_data->tx += n_bytes;
234 }
235}
236
237static void null_reader(struct driver_data *drv_data)
238{
239 u8 n_bytes = drv_data->n_bytes;
bb90eb00 240 dummy_read(drv_data);
a5f6abd4
WB		 241
242 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 243 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 244 cpu_relax();
bb90eb00 245 dummy_read(drv_data);
a5f6abd4
WB		 246 drv_data->rx += n_bytes;
247 }
248}
249
250static void u8_writer(struct driver_data *drv_data)
251{
131b17d4 252 dev_dbg(&drv_data->pdev->dev,
bb90eb00 253 "cr8-s is 0x%x\n", read_STAT(drv_data));
cc487e73 254
a5f6abd4 255 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 256 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
257 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 258 cpu_relax();
a5f6abd4
WB		 259 ++drv_data->tx;
260 }
13f3e642
SZ		 261
262 /* poll for SPI completion before return */
263 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
264 cpu_relax();
a5f6abd4
WB		 265}
266
267static void u8_cs_chg_writer(struct driver_data *drv_data)
268{
269 struct chip_data *chip = drv_data->cur_chip;
270
271 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 272 cs_active(drv_data, chip);
a5f6abd4 273
bb90eb00
BW		 274 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
275 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 276 cpu_relax();
e26aa015
BW		 277 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
278 cpu_relax();
62310e51 279
bb90eb00 280 cs_deactive(drv_data, chip);
5fec5b5a 281
a5f6abd4
WB		 282 ++drv_data->tx;
283 }
a5f6abd4
WB		 284}
285
286static void u8_reader(struct driver_data *drv_data)
287{
131b17d4 288 dev_dbg(&drv_data->pdev->dev,
bb90eb00 289 "cr-8 is 0x%x\n", read_STAT(drv_data));
a5f6abd4 290
3f479a65 291 /* poll for SPI completion before start */
bb90eb00 292 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 293 cpu_relax();
3f479a65 294
a5f6abd4 295 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 296 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 297
bb90eb00 298 dummy_read(drv_data);
cc487e73 299
a5f6abd4 300 while (drv_data->rx < drv_data->rx_end - 1) {
bb90eb00 301 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 302 cpu_relax();
bb90eb00 303 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 304 ++drv_data->rx;
305 }
306
bb90eb00 307 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 308 cpu_relax();
bb90eb00 309 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 310 ++drv_data->rx;
311}
312
313static void u8_cs_chg_reader(struct driver_data *drv_data)
314{
315 struct chip_data *chip = drv_data->cur_chip;
316
e26aa015
BW		 317 while (drv_data->rx < drv_data->rx_end) {
318 cs_active(drv_data, chip);
319 read_RDBR(drv_data); /* kick off */
a5f6abd4 320
e26aa015
BW		 321 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
322 cpu_relax();
323 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
324 cpu_relax();
cc487e73 325
e26aa015 326 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
bb90eb00 327 cs_deactive(drv_data, chip);
5fec5b5a 328
a5f6abd4
WB		 329 ++drv_data->rx;
330 }
a5f6abd4
WB		 331}
332
333static void u8_duplex(struct driver_data *drv_data)
334{
335 /* in duplex mode, clk is triggered by writing of TDBR */
336 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 337 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
4fd432d9 338 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 339 cpu_relax();
bb90eb00 340 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 341 cpu_relax();
bb90eb00 342 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 343 ++drv_data->rx;
344 ++drv_data->tx;
345 }
346}
347
348static void u8_cs_chg_duplex(struct driver_data *drv_data)
349{
350 struct chip_data *chip = drv_data->cur_chip;
351
352 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 353 cs_active(drv_data, chip);
5fec5b5a 354
bb90eb00 355 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
e26aa015
BW		 356
357 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 358 cpu_relax();
bb90eb00 359 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 360 cpu_relax();
bb90eb00 361 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 362
bb90eb00 363 cs_deactive(drv_data, chip);
5fec5b5a 364
a5f6abd4
WB		 365 ++drv_data->rx;
366 ++drv_data->tx;
367 }
a5f6abd4
WB		 368}
369
370static void u16_writer(struct driver_data *drv_data)
371{
131b17d4 372 dev_dbg(&drv_data->pdev->dev,
bb90eb00 373 "cr16 is 0x%x\n", read_STAT(drv_data));
88b40369 374
a5f6abd4 375 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 376 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
377 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 378 cpu_relax();
a5f6abd4
WB		 379 drv_data->tx += 2;
380 }
13f3e642
SZ		 381
382 /* poll for SPI completion before return */
383 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
384 cpu_relax();
a5f6abd4
WB		 385}
386
387static void u16_cs_chg_writer(struct driver_data *drv_data)
388{
389 struct chip_data *chip = drv_data->cur_chip;
390
391 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 392 cs_active(drv_data, chip);
a5f6abd4 393
bb90eb00
BW		 394 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
395 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 396 cpu_relax();
13f3e642
SZ		 397 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
398 cpu_relax();
62310e51 399
bb90eb00 400 cs_deactive(drv_data, chip);
5fec5b5a 401
a5f6abd4
WB		 402 drv_data->tx += 2;
403 }
a5f6abd4
WB		 404}
405
406static void u16_reader(struct driver_data *drv_data)
407{
88b40369 408 dev_dbg(&drv_data->pdev->dev,
bb90eb00 409 "cr-16 is 0x%x\n", read_STAT(drv_data));
cc487e73 410
3f479a65 411 /* poll for SPI completion before start */
bb90eb00 412 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 413 cpu_relax();
3f479a65 414
cc487e73 415 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 416 write_TDBR(drv_data, 0xFFFF);
cc487e73 417
bb90eb00 418 dummy_read(drv_data);
a5f6abd4
WB		 419
420 while (drv_data->rx < (drv_data->rx_end - 2)) {
bb90eb00 421 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 422 cpu_relax();
bb90eb00 423 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 424 drv_data->rx += 2;
425 }
426
bb90eb00 427 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 428 cpu_relax();
bb90eb00 429 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 430 drv_data->rx += 2;
431}
432
433static void u16_cs_chg_reader(struct driver_data *drv_data)
434{
435 struct chip_data *chip = drv_data->cur_chip;
436
3f479a65 437 /* poll for SPI completion before start */
bb90eb00 438 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 439 cpu_relax();
3f479a65 440
cc487e73 441 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 442 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 443
bb90eb00
BW		 444 cs_active(drv_data, chip);
445 dummy_read(drv_data);
cc487e73 446
c3061abb 447 while (drv_data->rx < drv_data->rx_end - 2) {
bb90eb00 448 cs_deactive(drv_data, chip);
5fec5b5a 449
bb90eb00 450 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 451 cpu_relax();
bb90eb00
BW		 452 cs_active(drv_data, chip);
453 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 454 drv_data->rx += 2;
455 }
bb90eb00 456 cs_deactive(drv_data, chip);
cc487e73 457
bb90eb00 458 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 459 cpu_relax();
bb90eb00 460 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
cc487e73 461 drv_data->rx += 2;
a5f6abd4
WB		 462}
463
464static void u16_duplex(struct driver_data *drv_data)
465{
466 /* in duplex mode, clk is triggered by writing of TDBR */
467 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 468 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
4fd432d9 469 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 470 cpu_relax();
bb90eb00 471 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 472 cpu_relax();
bb90eb00 473 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 474 drv_data->rx += 2;
475 drv_data->tx += 2;
476 }
477}
478
479static void u16_cs_chg_duplex(struct driver_data *drv_data)
480{
481 struct chip_data *chip = drv_data->cur_chip;
482
483 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 484 cs_active(drv_data, chip);
a5f6abd4 485
bb90eb00 486 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
4fd432d9 487 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 488 cpu_relax();
bb90eb00 489 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 490 cpu_relax();
bb90eb00 491 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 492
bb90eb00 493 cs_deactive(drv_data, chip);
5fec5b5a 494
a5f6abd4
WB		 495 drv_data->rx += 2;
496 drv_data->tx += 2;
497 }
a5f6abd4
WB		 498}
499
500/* test if ther is more transfer to be done */
501static void *next_transfer(struct driver_data *drv_data)
502{
503 struct spi_message *msg = drv_data->cur_msg;
504 struct spi_transfer *trans = drv_data->cur_transfer;
505
506 /* Move to next transfer */
507 if (trans->transfer_list.next != &msg->transfers) {
508 drv_data->cur_transfer =
509 list_entry(trans->transfer_list.next,
510 struct spi_transfer, transfer_list);
511 return RUNNING_STATE;
512 } else
513 return DONE_STATE;
514}
515
516/*
517 * caller already set message->status;
518 * dma and pio irqs are blocked give finished message back
519 */
520static void giveback(struct driver_data *drv_data)
521{
fad91c89 522 struct chip_data *chip = drv_data->cur_chip;
a5f6abd4
WB		 523 struct spi_transfer *last_transfer;
524 unsigned long flags;
525 struct spi_message *msg;
526
527 spin_lock_irqsave(&drv_data->lock, flags);
528 msg = drv_data->cur_msg;
529 drv_data->cur_msg = NULL;
530 drv_data->cur_transfer = NULL;
531 drv_data->cur_chip = NULL;
532 queue_work(drv_data->workqueue, &drv_data->pump_messages);
533 spin_unlock_irqrestore(&drv_data->lock, flags);
534
535 last_transfer = list_entry(msg->transfers.prev,
536 struct spi_transfer, transfer_list);
537
538 msg->state = NULL;
539
540 /* disable chip select signal. And not stop spi in autobuffer mode */
541 if (drv_data->tx_dma != 0xFFFF) {
bb90eb00 542 cs_deactive(drv_data, chip);
a5f6abd4
WB		 543 bfin_spi_disable(drv_data);
544 }
545
fad91c89 546 if (!drv_data->cs_change)
bb90eb00 547 cs_deactive(drv_data, chip);
fad91c89 548
a5f6abd4
WB		 549 if (msg->complete)
550 msg->complete(msg->context);
551}
552
88b40369 553static irqreturn_t dma_irq_handler(int irq, void *dev_id)
a5f6abd4 554{
15aafa2f 555 struct driver_data *drv_data = dev_id;
fad91c89 556 struct chip_data *chip = drv_data->cur_chip;
bb90eb00 557 struct spi_message *msg = drv_data->cur_msg;
a5f6abd4 558
88b40369 559 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
bb90eb00 560 clear_dma_irqstat(drv_data->dma_channel);
a5f6abd4 561
d6fe89b0 562 /* Wait for DMA to complete */
bb90eb00 563 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
d8c05008 564 cpu_relax();
d6fe89b0 565
a5f6abd4 566 /*
d6fe89b0
BW		 567 * wait for the last transaction shifted out. HRM states:
568 * at this point there may still be data in the SPI DMA FIFO waiting
569 * to be transmitted ... software needs to poll TXS in the SPI_STAT
570 * register until it goes low for 2 successive reads
a5f6abd4
WB		 571 */
572 if (drv_data->tx != NULL) {
bb90eb00
BW		 573 while ((read_STAT(drv_data) & TXS) ||
574 (read_STAT(drv_data) & TXS))
d8c05008 575 cpu_relax();
a5f6abd4
WB		 576 }
577
bb90eb00 578 while (!(read_STAT(drv_data) & SPIF))
d8c05008 579 cpu_relax();
a5f6abd4 580
a5f6abd4
WB		 581 msg->actual_length += drv_data->len_in_bytes;
582
fad91c89 583 if (drv_data->cs_change)
bb90eb00 584 cs_deactive(drv_data, chip);
fad91c89 585
a5f6abd4
WB		 586 /* Move to next transfer */
587 msg->state = next_transfer(drv_data);
588
589 /* Schedule transfer tasklet */
590 tasklet_schedule(&drv_data->pump_transfers);
591
592 /* free the irq handler before next transfer */
88b40369
BW		 593 dev_dbg(&drv_data->pdev->dev,
594 "disable dma channel irq%d\n",
bb90eb00
BW		 595 drv_data->dma_channel);
596 dma_disable_irq(drv_data->dma_channel);
a5f6abd4
WB		 597
598 return IRQ_HANDLED;
599}
600
601static void pump_transfers(unsigned long data)
602{
603 struct driver_data *drv_data = (struct driver_data *)data;
604 struct spi_message *message = NULL;
605 struct spi_transfer *transfer = NULL;
606 struct spi_transfer *previous = NULL;
607 struct chip_data *chip = NULL;
88b40369
BW		 608 u8 width;
609 u16 cr, dma_width, dma_config;
a5f6abd4 610 u32 tranf_success = 1;
8eeb12e5 611 u8 full_duplex = 0;
a5f6abd4
WB		 612
613 /* Get current state information */
614 message = drv_data->cur_msg;
615 transfer = drv_data->cur_transfer;
616 chip = drv_data->cur_chip;
092e1fda 617
a5f6abd4
WB		 618 /*
619 * if msg is error or done, report it back using complete() callback
620 */
621
622 /* Handle for abort */
623 if (message->state == ERROR_STATE) {
624 message->status = -EIO;
625 giveback(drv_data);
626 return;
627 }
628
629 /* Handle end of message */
630 if (message->state == DONE_STATE) {
631 message->status = 0;
632 giveback(drv_data);
633 return;
634 }
635
636 /* Delay if requested at end of transfer */
637 if (message->state == RUNNING_STATE) {
638 previous = list_entry(transfer->transfer_list.prev,
639 struct spi_transfer, transfer_list);
640 if (previous->delay_usecs)
641 udelay(previous->delay_usecs);
642 }
643
644 /* Setup the transfer state based on the type of transfer */
645 if (flush(drv_data) == 0) {
646 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
647 message->status = -EIO;
648 giveback(drv_data);
649 return;
650 }
651
652 if (transfer->tx_buf != NULL) {
653 drv_data->tx = (void *)transfer->tx_buf;
654 drv_data->tx_end = drv_data->tx + transfer->len;
88b40369
BW		 655 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
656 transfer->tx_buf, drv_data->tx_end);
a5f6abd4
WB		 657 } else {
658 drv_data->tx = NULL;
659 }
660
661 if (transfer->rx_buf != NULL) {
8eeb12e5 662 full_duplex = transfer->tx_buf != NULL;
a5f6abd4
WB		 663 drv_data->rx = transfer->rx_buf;
664 drv_data->rx_end = drv_data->rx + transfer->len;
88b40369
BW		 665 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
666 transfer->rx_buf, drv_data->rx_end);
a5f6abd4
WB		 667 } else {
668 drv_data->rx = NULL;
669 }
670
671 drv_data->rx_dma = transfer->rx_dma;
672 drv_data->tx_dma = transfer->tx_dma;
673 drv_data->len_in_bytes = transfer->len;
fad91c89 674 drv_data->cs_change = transfer->cs_change;
a5f6abd4 675
092e1fda
BW		 676 /* Bits per word setup */
677 switch (transfer->bits_per_word) {
678 case 8:
679 drv_data->n_bytes = 1;
680 width = CFG_SPI_WORDSIZE8;
681 drv_data->read = chip->cs_change_per_word ?
682 u8_cs_chg_reader : u8_reader;
683 drv_data->write = chip->cs_change_per_word ?
684 u8_cs_chg_writer : u8_writer;
685 drv_data->duplex = chip->cs_change_per_word ?
686 u8_cs_chg_duplex : u8_duplex;
687 break;
688
689 case 16:
690 drv_data->n_bytes = 2;
691 width = CFG_SPI_WORDSIZE16;
692 drv_data->read = chip->cs_change_per_word ?
693 u16_cs_chg_reader : u16_reader;
694 drv_data->write = chip->cs_change_per_word ?
695 u16_cs_chg_writer : u16_writer;
696 drv_data->duplex = chip->cs_change_per_word ?
697 u16_cs_chg_duplex : u16_duplex;
698 break;
699
700 default:
701 /* No change, the same as default setting */
702 drv_data->n_bytes = chip->n_bytes;
703 width = chip->width;
704 drv_data->write = drv_data->tx ? chip->write : null_writer;
705 drv_data->read = drv_data->rx ? chip->read : null_reader;
706 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
707 break;
708 }
709 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
710 cr |= (width << 8);
711 write_CTRL(drv_data, cr);
712
a5f6abd4
WB		 713 if (width == CFG_SPI_WORDSIZE16) {
714 drv_data->len = (transfer->len) >> 1;
715 } else {
716 drv_data->len = transfer->len;
717 }
4fb98efa
MF		 718 dev_dbg(&drv_data->pdev->dev,
719 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
131b17d4 720 drv_data->write, chip->write, null_writer);
a5f6abd4
WB		 721
722 /* speed and width has been set on per message */
723 message->state = RUNNING_STATE;
724 dma_config = 0;
725
092e1fda
BW		 726 /* Speed setup (surely valid because already checked) */
727 if (transfer->speed_hz)
728 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
729 else
730 write_BAUD(drv_data, chip->baud);
731
bb90eb00
BW		 732 write_STAT(drv_data, BIT_STAT_CLR);
733 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
734 cs_active(drv_data, chip);
a5f6abd4 735
88b40369
BW		 736 dev_dbg(&drv_data->pdev->dev,
737 "now pumping a transfer: width is %d, len is %d\n",
738 width, transfer->len);
a5f6abd4
WB		 739
740 /*
741 * Try to map dma buffer and do a dma transfer if
742 * successful use different way to r/w according to
743 * drv_data->cur_chip->enable_dma
744 */
8eeb12e5
VM		 745 if (!full_duplex && drv_data->cur_chip->enable_dma
746 && drv_data->len > 6) {
a5f6abd4 747
bb90eb00
BW		 748 disable_dma(drv_data->dma_channel);
749 clear_dma_irqstat(drv_data->dma_channel);
07612e5f 750 bfin_spi_disable(drv_data);
a5f6abd4
WB		 751
752 /* config dma channel */
88b40369 753 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
a5f6abd4 754 if (width == CFG_SPI_WORDSIZE16) {
bb90eb00
BW		 755 set_dma_x_count(drv_data->dma_channel, drv_data->len);
756 set_dma_x_modify(drv_data->dma_channel, 2);
a5f6abd4
WB		 757 dma_width = WDSIZE_16;
758 } else {
bb90eb00
BW		 759 set_dma_x_count(drv_data->dma_channel, drv_data->len);
760 set_dma_x_modify(drv_data->dma_channel, 1);
a5f6abd4
WB		 761 dma_width = WDSIZE_8;
762 }
763
3f479a65 764 /* poll for SPI completion before start */
bb90eb00 765 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 766 cpu_relax();
3f479a65 767
a5f6abd4
WB		 768 /* dirty hack for autobuffer DMA mode */
769 if (drv_data->tx_dma == 0xFFFF) {
88b40369
BW		 770 dev_dbg(&drv_data->pdev->dev,
771 "doing autobuffer DMA out.\n");
a5f6abd4
WB		 772
773 /* no irq in autobuffer mode */
774 dma_config =
775 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
bb90eb00
BW		 776 set_dma_config(drv_data->dma_channel, dma_config);
777 set_dma_start_addr(drv_data->dma_channel,
a32c691d 778 (unsigned long)drv_data->tx);
bb90eb00 779 enable_dma(drv_data->dma_channel);
a5f6abd4 780
07612e5f
SZ		 781 /* start SPI transfer */
782 write_CTRL(drv_data,
783 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
784
785 /* just return here, there can only be one transfer
786 * in this mode
787 */
a5f6abd4
WB		 788 message->status = 0;
789 giveback(drv_data);
790 return;
791 }
792
793 /* In dma mode, rx or tx must be NULL in one transfer */
794 if (drv_data->rx != NULL) {
795 /* set transfer mode, and enable SPI */
88b40369 796 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
a5f6abd4 797
a5f6abd4 798 /* clear tx reg soformer data is not shifted out */
bb90eb00 799 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 800
bb90eb00 801 set_dma_x_count(drv_data->dma_channel, drv_data->len);
a5f6abd4
WB		 802
803 /* start dma */
bb90eb00 804 dma_enable_irq(drv_data->dma_channel);
a5f6abd4 805 dma_config = (WNR | RESTART | dma_width | DI_EN);
bb90eb00
BW		 806 set_dma_config(drv_data->dma_channel, dma_config);
807 set_dma_start_addr(drv_data->dma_channel,
a32c691d 808 (unsigned long)drv_data->rx);
bb90eb00 809 enable_dma(drv_data->dma_channel);
a5f6abd4 810
07612e5f
SZ		 811 /* start SPI transfer */
812 write_CTRL(drv_data,
813 (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
814
a5f6abd4 815 } else if (drv_data->tx != NULL) {
88b40369 816 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
a5f6abd4
WB		 817
818 /* start dma */
bb90eb00 819 dma_enable_irq(drv_data->dma_channel);
a5f6abd4 820 dma_config = (RESTART | dma_width | DI_EN);
bb90eb00
BW		 821 set_dma_config(drv_data->dma_channel, dma_config);
822 set_dma_start_addr(drv_data->dma_channel,
a32c691d 823 (unsigned long)drv_data->tx);
bb90eb00 824 enable_dma(drv_data->dma_channel);
07612e5f
SZ		 825
826 /* start SPI transfer */
827 write_CTRL(drv_data,
828 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
a5f6abd4
WB		 829 }
830 } else {
831 /* IO mode write then read */
88b40369 832 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
a5f6abd4 833
8eeb12e5 834 if (full_duplex) {
a5f6abd4
WB		 835 /* full duplex mode */
836 BUG_ON((drv_data->tx_end - drv_data->tx) !=
837 (drv_data->rx_end - drv_data->rx));
88b40369
BW		 838 dev_dbg(&drv_data->pdev->dev,
839 "IO duplex: cr is 0x%x\n", cr);
a5f6abd4 840
cc487e73 841 /* set SPI transfer mode */
bb90eb00 842 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 843
844 drv_data->duplex(drv_data);
845
846 if (drv_data->tx != drv_data->tx_end)
847 tranf_success = 0;
848 } else if (drv_data->tx != NULL) {
849 /* write only half duplex */
131b17d4 850 dev_dbg(&drv_data->pdev->dev,
88b40369 851 "IO write: cr is 0x%x\n", cr);
a5f6abd4 852
cc487e73 853 /* set SPI transfer mode */
bb90eb00 854 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 855
856 drv_data->write(drv_data);
857
858 if (drv_data->tx != drv_data->tx_end)
859 tranf_success = 0;
860 } else if (drv_data->rx != NULL) {
861 /* read only half duplex */
131b17d4 862 dev_dbg(&drv_data->pdev->dev,
88b40369 863 "IO read: cr is 0x%x\n", cr);
a5f6abd4 864
cc487e73 865 /* set SPI transfer mode */
bb90eb00 866 write_CTRL(drv_data, (cr | CFG_SPI_READ));
a5f6abd4
WB		 867
868 drv_data->read(drv_data);
869 if (drv_data->rx != drv_data->rx_end)
870 tranf_success = 0;
871 }
872
873 if (!tranf_success) {
131b17d4 874 dev_dbg(&drv_data->pdev->dev,
88b40369 875 "IO write error!\n");
a5f6abd4
WB		 876 message->state = ERROR_STATE;
877 } else {
878 /* Update total byte transfered */
879 message->actual_length += drv_data->len;
880
881 /* Move to next transfer of this msg */
882 message->state = next_transfer(drv_data);
883 }
884
885 /* Schedule next transfer tasklet */
886 tasklet_schedule(&drv_data->pump_transfers);
887
888 }
889}
890
891/* pop a msg from queue and kick off real transfer */
892static void pump_messages(struct work_struct *work)
893{
131b17d4 894 struct driver_data *drv_data;
a5f6abd4
WB		 895 unsigned long flags;
896
131b17d4
BW		 897 drv_data = container_of(work, struct driver_data, pump_messages);
898
a5f6abd4
WB		 899 /* Lock queue and check for queue work */
900 spin_lock_irqsave(&drv_data->lock, flags);
901 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
902 /* pumper kicked off but no work to do */
903 drv_data->busy = 0;
904 spin_unlock_irqrestore(&drv_data->lock, flags);
905 return;
906 }
907
908 /* Make sure we are not already running a message */
909 if (drv_data->cur_msg) {
910 spin_unlock_irqrestore(&drv_data->lock, flags);
911 return;
912 }
913
914 /* Extract head of queue */
915 drv_data->cur_msg = list_entry(drv_data->queue.next,
916 struct spi_message, queue);
5fec5b5a
BW		 917
918 /* Setup the SSP using the per chip configuration */
919 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
8d20d0a7 920 restore_state(drv_data);
5fec5b5a 921
a5f6abd4
WB		 922 list_del_init(&drv_data->cur_msg->queue);
923
924 /* Initial message state */
925 drv_data->cur_msg->state = START_STATE;
926 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
927 struct spi_transfer, transfer_list);
928
5fec5b5a
BW		 929 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
930 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
931 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
932 drv_data->cur_chip->ctl_reg);
131b17d4
BW		 933
934 dev_dbg(&drv_data->pdev->dev,
88b40369
BW		 935 "the first transfer len is %d\n",
936 drv_data->cur_transfer->len);
a5f6abd4
WB		 937
938 /* Mark as busy and launch transfers */
939 tasklet_schedule(&drv_data->pump_transfers);
940
941 drv_data->busy = 1;
942 spin_unlock_irqrestore(&drv_data->lock, flags);
943}
944
945/*
946 * got a msg to transfer, queue it in drv_data->queue.
947 * And kick off message pumper
948 */
949static int transfer(struct spi_device *spi, struct spi_message *msg)
950{
951 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
952 unsigned long flags;
953
954 spin_lock_irqsave(&drv_data->lock, flags);
955
956 if (drv_data->run == QUEUE_STOPPED) {
957 spin_unlock_irqrestore(&drv_data->lock, flags);
958 return -ESHUTDOWN;
959 }
960
961 msg->actual_length = 0;
962 msg->status = -EINPROGRESS;
963 msg->state = START_STATE;
964
88b40369 965 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
a5f6abd4
WB		 966 list_add_tail(&msg->queue, &drv_data->queue);
967
968 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
969 queue_work(drv_data->workqueue, &drv_data->pump_messages);
970
971 spin_unlock_irqrestore(&drv_data->lock, flags);
972
973 return 0;
974}
975
12e17c42
SZ		 976#define MAX_SPI_SSEL 7
977
978static u16 ssel[3][MAX_SPI_SSEL] = {
979 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
980 P_SPI0_SSEL4, P_SPI0_SSEL5,
981 P_SPI0_SSEL6, P_SPI0_SSEL7},
982
983 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
984 P_SPI1_SSEL4, P_SPI1_SSEL5,
985 P_SPI1_SSEL6, P_SPI1_SSEL7},
986
987 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
988 P_SPI2_SSEL4, P_SPI2_SSEL5,
989 P_SPI2_SSEL6, P_SPI2_SSEL7},
990};
991
a5f6abd4
WB		 992/* first setup for new devices */
993static int setup(struct spi_device *spi)
994{
995 struct bfin5xx_spi_chip *chip_info = NULL;
996 struct chip_data *chip;
997 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
998 u8 spi_flg;
999
1000 /* Abort device setup if requested features are not supported */
1001 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1002 dev_err(&spi->dev, "requested mode not fully supported\n");
1003 return -EINVAL;
1004 }
1005
1006 /* Zero (the default) here means 8 bits */
1007 if (!spi->bits_per_word)
1008 spi->bits_per_word = 8;
1009
1010 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1011 return -EINVAL;
1012
1013 /* Only alloc (or use chip_info) on first setup */
1014 chip = spi_get_ctldata(spi);
1015 if (chip == NULL) {
1016 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1017 if (!chip)
1018 return -ENOMEM;
1019
1020 chip->enable_dma = 0;
1021 chip_info = spi->controller_data;
1022 }
1023
1024 /* chip_info isn't always needed */
1025 if (chip_info) {
2ed35516
MF		 1026 /* Make sure people stop trying to set fields via ctl_reg
1027 * when they should actually be using common SPI framework.
1028 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1029 * Not sure if a user actually needs/uses any of these,
1030 * but let's assume (for now) they do.
1031 */
1032 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1033 dev_err(&spi->dev, "do not set bits in ctl_reg "
1034 "that the SPI framework manages\n");
1035 return -EINVAL;
1036 }
1037
a5f6abd4
WB		 1038 chip->enable_dma = chip_info->enable_dma != 0
1039 && drv_data->master_info->enable_dma;
1040 chip->ctl_reg = chip_info->ctl_reg;
1041 chip->bits_per_word = chip_info->bits_per_word;
1042 chip->cs_change_per_word = chip_info->cs_change_per_word;
1043 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1044 }
1045
1046 /* translate common spi framework into our register */
1047 if (spi->mode & SPI_CPOL)
1048 chip->ctl_reg |= CPOL;
1049 if (spi->mode & SPI_CPHA)
1050 chip->ctl_reg |= CPHA;
1051 if (spi->mode & SPI_LSB_FIRST)
1052 chip->ctl_reg |= LSBF;
1053 /* we dont support running in slave mode (yet?) */
1054 chip->ctl_reg |= MSTR;
1055
1056 /*
1057 * if any one SPI chip is registered and wants DMA, request the
1058 * DMA channel for it
1059 */
bb90eb00 1060 if (chip->enable_dma && !drv_data->dma_requested) {
a5f6abd4 1061 /* register dma irq handler */
bb90eb00 1062 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
88b40369
BW		 1063 dev_dbg(&spi->dev,
1064 "Unable to request BlackFin SPI DMA channel\n");
a5f6abd4
WB		 1065 return -ENODEV;
1066 }
bb90eb00
BW		 1067 if (set_dma_callback(drv_data->dma_channel,
1068 (void *)dma_irq_handler, drv_data) < 0) {
88b40369 1069 dev_dbg(&spi->dev, "Unable to set dma callback\n");
a5f6abd4
WB		 1070 return -EPERM;
1071 }
bb90eb00
BW		 1072 dma_disable_irq(drv_data->dma_channel);
1073 drv_data->dma_requested = 1;
a5f6abd4
WB		 1074 }
1075
1076 /*
1077 * Notice: for blackfin, the speed_hz is the value of register
1078 * SPI_BAUD, not the real baudrate
1079 */
1080 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1081 spi_flg = ~(1 << (spi->chip_select));
1082 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1083 chip->chip_select_num = spi->chip_select;
1084
1085 switch (chip->bits_per_word) {
1086 case 8:
1087 chip->n_bytes = 1;
1088 chip->width = CFG_SPI_WORDSIZE8;
1089 chip->read = chip->cs_change_per_word ?
1090 u8_cs_chg_reader : u8_reader;
1091 chip->write = chip->cs_change_per_word ?
1092 u8_cs_chg_writer : u8_writer;
1093 chip->duplex = chip->cs_change_per_word ?
1094 u8_cs_chg_duplex : u8_duplex;
1095 break;
1096
1097 case 16:
1098 chip->n_bytes = 2;
1099 chip->width = CFG_SPI_WORDSIZE16;
1100 chip->read = chip->cs_change_per_word ?
1101 u16_cs_chg_reader : u16_reader;
1102 chip->write = chip->cs_change_per_word ?
1103 u16_cs_chg_writer : u16_writer;
1104 chip->duplex = chip->cs_change_per_word ?
1105 u16_cs_chg_duplex : u16_duplex;
1106 break;
1107
1108 default:
1109 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1110 chip->bits_per_word);
1111 kfree(chip);
1112 return -ENODEV;
1113 }
1114
898eb71c 1115 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
a5f6abd4 1116 spi->modalias, chip->width, chip->enable_dma);
88b40369 1117 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
a5f6abd4
WB		 1118 chip->ctl_reg, chip->flag);
1119
1120 spi_set_ctldata(spi, chip);
1121
12e17c42
SZ		 1122 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1123 if ((chip->chip_select_num > 0)
1124 && (chip->chip_select_num <= spi->master->num_chipselect))
1125 peripheral_request(ssel[spi->master->bus_num]
aab0d83e 1126 [chip->chip_select_num-1], spi->modalias);
12e17c42 1127
07612e5f
SZ		 1128 cs_deactive(drv_data, chip);
1129
a5f6abd4
WB		 1130 return 0;
1131}
1132
1133/*
1134 * callback for spi framework.
1135 * clean driver specific data
1136 */
88b40369 1137static void cleanup(struct spi_device *spi)
a5f6abd4 1138{
27bb9e79 1139 struct chip_data *chip = spi_get_ctldata(spi);
a5f6abd4 1140
12e17c42
SZ		 1141 if ((chip->chip_select_num > 0)
1142 && (chip->chip_select_num <= spi->master->num_chipselect))
1143 peripheral_free(ssel[spi->master->bus_num]
1144 [chip->chip_select_num-1]);
1145
a5f6abd4
WB		 1146 kfree(chip);
1147}
1148
1149static inline int init_queue(struct driver_data *drv_data)
1150{
1151 INIT_LIST_HEAD(&drv_data->queue);
1152 spin_lock_init(&drv_data->lock);
1153
1154 drv_data->run = QUEUE_STOPPED;
1155 drv_data->busy = 0;
1156
1157 /* init transfer tasklet */
1158 tasklet_init(&drv_data->pump_transfers,
1159 pump_transfers, (unsigned long)drv_data);
1160
1161 /* init messages workqueue */
1162 INIT_WORK(&drv_data->pump_messages, pump_messages);
1163 drv_data->workqueue =
49dce689 1164 create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
a5f6abd4
WB		 1165 if (drv_data->workqueue == NULL)
1166 return -EBUSY;
1167
1168 return 0;
1169}
1170
1171static inline int start_queue(struct driver_data *drv_data)
1172{
1173 unsigned long flags;
1174
1175 spin_lock_irqsave(&drv_data->lock, flags);
1176
1177 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1178 spin_unlock_irqrestore(&drv_data->lock, flags);
1179 return -EBUSY;
1180 }
1181
1182 drv_data->run = QUEUE_RUNNING;
1183 drv_data->cur_msg = NULL;
1184 drv_data->cur_transfer = NULL;
1185 drv_data->cur_chip = NULL;
1186 spin_unlock_irqrestore(&drv_data->lock, flags);
1187
1188 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1189
1190 return 0;
1191}
1192
1193static inline int stop_queue(struct driver_data *drv_data)
1194{
1195 unsigned long flags;
1196 unsigned limit = 500;
1197 int status = 0;
1198
1199 spin_lock_irqsave(&drv_data->lock, flags);
1200
1201 /*
1202 * This is a bit lame, but is optimized for the common execution path.
1203 * A wait_queue on the drv_data->busy could be used, but then the common
1204 * execution path (pump_messages) would be required to call wake_up or
1205 * friends on every SPI message. Do this instead
1206 */
1207 drv_data->run = QUEUE_STOPPED;
1208 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1209 spin_unlock_irqrestore(&drv_data->lock, flags);
1210 msleep(10);
1211 spin_lock_irqsave(&drv_data->lock, flags);
1212 }
1213
1214 if (!list_empty(&drv_data->queue) || drv_data->busy)
1215 status = -EBUSY;
1216
1217 spin_unlock_irqrestore(&drv_data->lock, flags);
1218
1219 return status;
1220}
1221
1222static inline int destroy_queue(struct driver_data *drv_data)
1223{
1224 int status;
1225
1226 status = stop_queue(drv_data);
1227 if (status != 0)
1228 return status;
1229
1230 destroy_workqueue(drv_data->workqueue);
1231
1232 return 0;
1233}
1234
1235static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1236{
1237 struct device *dev = &pdev->dev;
1238 struct bfin5xx_spi_master *platform_info;
1239 struct spi_master *master;
1240 struct driver_data *drv_data = 0;
a32c691d 1241 struct resource *res;
a5f6abd4
WB		 1242 int status = 0;
1243
1244 platform_info = dev->platform_data;
1245
1246 /* Allocate master with space for drv_data */
1247 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1248 if (!master) {
1249 dev_err(&pdev->dev, "can not alloc spi_master\n");
1250 return -ENOMEM;
1251 }
131b17d4 1252
a5f6abd4
WB		 1253 drv_data = spi_master_get_devdata(master);
1254 drv_data->master = master;
1255 drv_data->master_info = platform_info;
1256 drv_data->pdev = pdev;
003d9226 1257 drv_data->pin_req = platform_info->pin_req;
a5f6abd4
WB		 1258
1259 master->bus_num = pdev->id;
1260 master->num_chipselect = platform_info->num_chipselect;
1261 master->cleanup = cleanup;
1262 master->setup = setup;
1263 master->transfer = transfer;
1264
a32c691d
BW		 1265 /* Find and map our resources */
1266 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1267 if (res == NULL) {
1268 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1269 status = -ENOENT;
1270 goto out_error_get_res;
1271 }
1272
f452126c
BW		 1273 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1274 if (drv_data->regs_base == NULL) {
a32c691d
BW		 1275 dev_err(dev, "Cannot map IO\n");
1276 status = -ENXIO;
1277 goto out_error_ioremap;
1278 }
1279
bb90eb00
BW		 1280 drv_data->dma_channel = platform_get_irq(pdev, 0);
1281 if (drv_data->dma_channel < 0) {
a32c691d
BW		 1282 dev_err(dev, "No DMA channel specified\n");
1283 status = -ENOENT;
1284 goto out_error_no_dma_ch;
1285 }
1286
a5f6abd4
WB		 1287 /* Initial and start queue */
1288 status = init_queue(drv_data);
1289 if (status != 0) {
a32c691d 1290 dev_err(dev, "problem initializing queue\n");
a5f6abd4
WB		 1291 goto out_error_queue_alloc;
1292 }
a32c691d 1293
a5f6abd4
WB		 1294 status = start_queue(drv_data);
1295 if (status != 0) {
a32c691d 1296 dev_err(dev, "problem starting queue\n");
a5f6abd4
WB		 1297 goto out_error_queue_alloc;
1298 }
1299
f9e522ca
VM		 1300 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1301 if (status != 0) {
1302 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1303 goto out_error_queue_alloc;
1304 }
1305
a5f6abd4
WB		 1306 /* Register with the SPI framework */
1307 platform_set_drvdata(pdev, drv_data);
1308 status = spi_register_master(master);
1309 if (status != 0) {
a32c691d 1310 dev_err(dev, "problem registering spi master\n");
a5f6abd4
WB		 1311 goto out_error_queue_alloc;
1312 }
a32c691d 1313
f452126c 1314 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
bb90eb00
BW		 1315 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1316 drv_data->dma_channel);
a5f6abd4
WB		 1317 return status;
1318
cc2f81a6 1319out_error_queue_alloc:
a5f6abd4 1320 destroy_queue(drv_data);
a32c691d 1321out_error_no_dma_ch:
bb90eb00 1322 iounmap((void *) drv_data->regs_base);
a32c691d
BW		 1323out_error_ioremap:
1324out_error_get_res:
a5f6abd4 1325 spi_master_put(master);
cc2f81a6 1326
a5f6abd4
WB		 1327 return status;
1328}
1329
1330/* stop hardware and remove the driver */
1331static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1332{
1333 struct driver_data *drv_data = platform_get_drvdata(pdev);
1334 int status = 0;
1335
1336 if (!drv_data)
1337 return 0;
1338
1339 /* Remove the queue */
1340 status = destroy_queue(drv_data);
1341 if (status != 0)
1342 return status;
1343
1344 /* Disable the SSP at the peripheral and SOC level */
1345 bfin_spi_disable(drv_data);
1346
1347 /* Release DMA */
1348 if (drv_data->master_info->enable_dma) {
bb90eb00
BW		 1349 if (dma_channel_active(drv_data->dma_channel))
1350 free_dma(drv_data->dma_channel);
a5f6abd4
WB		 1351 }
1352
1353 /* Disconnect from the SPI framework */
1354 spi_unregister_master(drv_data->master);
1355
003d9226 1356 peripheral_free_list(drv_data->pin_req);
cc2f81a6 1357
a5f6abd4
WB		 1358 /* Prevent double remove */
1359 platform_set_drvdata(pdev, NULL);
1360
1361 return 0;
1362}
1363
1364#ifdef CONFIG_PM
1365static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1366{
1367 struct driver_data *drv_data = platform_get_drvdata(pdev);
1368 int status = 0;
1369
1370 status = stop_queue(drv_data);
1371 if (status != 0)
1372 return status;
1373
1374 /* stop hardware */
1375 bfin_spi_disable(drv_data);
1376
1377 return 0;
1378}
1379
1380static int bfin5xx_spi_resume(struct platform_device *pdev)
1381{
1382 struct driver_data *drv_data = platform_get_drvdata(pdev);
1383 int status = 0;
1384
1385 /* Enable the SPI interface */
1386 bfin_spi_enable(drv_data);
1387
1388 /* Start the queue running */
1389 status = start_queue(drv_data);
1390 if (status != 0) {
1391 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1392 return status;
1393 }
1394
1395 return 0;
1396}
1397#else
1398#define bfin5xx_spi_suspend NULL
1399#define bfin5xx_spi_resume NULL
1400#endif /* CONFIG_PM */
1401
7e38c3c4 1402MODULE_ALIAS("platform:bfin-spi");
a5f6abd4 1403static struct platform_driver bfin5xx_spi_driver = {
fc3ba952 1404 .driver = {
a32c691d 1405 .name = DRV_NAME,
88b40369
BW		 1406 .owner = THIS_MODULE,
1407 },
1408 .suspend = bfin5xx_spi_suspend,
1409 .resume = bfin5xx_spi_resume,
1410 .remove = __devexit_p(bfin5xx_spi_remove),
a5f6abd4
WB		 1411};
1412
1413static int __init bfin5xx_spi_init(void)
1414{
88b40369 1415 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
a5f6abd4 1416}
a5f6abd4
WB		 1417module_init(bfin5xx_spi_init);
1418
1419static void __exit bfin5xx_spi_exit(void)
1420{
1421 platform_driver_unregister(&bfin5xx_spi_driver);
1422}
a5f6abd4 1423module_exit(bfin5xx_spi_exit);
Linux 6.x block layer and io_uring tree(s)