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Blackfin SPI Driver: do not check for SPI errors if DMA itself did not flag any
[linux-2.6-block.git] / drivers / spi / spi_bfin5xx.c
CommitLineData
a5f6abd4 1/*
26fdc1f0 2 * Blackfin On-Chip SPI Driver
a5f6abd4 3 *
131b17d4 4 * Copyright 2004-2007 Analog Devices Inc.
a5f6abd4 5 *
26fdc1f0 6 * Enter bugs at http://blackfin.uclinux.org/
a5f6abd4 7 *
26fdc1f0 8 * Licensed under the GPL-2 or later.
a5f6abd4
WB		 9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
131b17d4 13#include <linux/delay.h>
a5f6abd4 14#include <linux/device.h>
131b17d4 15#include <linux/io.h>
a5f6abd4 16#include <linux/ioport.h>
131b17d4 17#include <linux/irq.h>
a5f6abd4
WB		 18#include <linux/errno.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22#include <linux/spi/spi.h>
23#include <linux/workqueue.h>
a5f6abd4 24
a5f6abd4 25#include <asm/dma.h>
131b17d4 26#include <asm/portmux.h>
a5f6abd4 27#include <asm/bfin5xx_spi.h>
8cf5858c
VM		 28#include <asm/cacheflush.h>
29
a32c691d
BW		 30#define DRV_NAME "bfin-spi"
31#define DRV_AUTHOR "Bryan Wu, Luke Yang"
6b1a8028 32#define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
a32c691d
BW		 33#define DRV_VERSION "1.0"
34
35MODULE_AUTHOR(DRV_AUTHOR);
36MODULE_DESCRIPTION(DRV_DESC);
a5f6abd4
WB		 37MODULE_LICENSE("GPL");
38
bb90eb00 39#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
a5f6abd4 40
bb90eb00
BW		 41#define START_STATE ((void *)0)
42#define RUNNING_STATE ((void *)1)
43#define DONE_STATE ((void *)2)
44#define ERROR_STATE ((void *)-1)
45#define QUEUE_RUNNING 0
46#define QUEUE_STOPPED 1
a5f6abd4
WB		 47
48struct driver_data {
49 /* Driver model hookup */
50 struct platform_device *pdev;
51
52 /* SPI framework hookup */
53 struct spi_master *master;
54
bb90eb00 55 /* Regs base of SPI controller */
f452126c 56 void __iomem *regs_base;
bb90eb00 57
003d9226
BW		 58 /* Pin request list */
59 u16 *pin_req;
60
a5f6abd4
WB		 61 /* BFIN hookup */
62 struct bfin5xx_spi_master *master_info;
63
64 /* Driver message queue */
65 struct workqueue_struct *workqueue;
66 struct work_struct pump_messages;
67 spinlock_t lock;
68 struct list_head queue;
69 int busy;
70 int run;
71
72 /* Message Transfer pump */
73 struct tasklet_struct pump_transfers;
74
75 /* Current message transfer state info */
76 struct spi_message *cur_msg;
77 struct spi_transfer *cur_transfer;
78 struct chip_data *cur_chip;
79 size_t len_in_bytes;
80 size_t len;
81 void *tx;
82 void *tx_end;
83 void *rx;
84 void *rx_end;
bb90eb00
BW		 85
86 /* DMA stuffs */
87 int dma_channel;
a5f6abd4 88 int dma_mapped;
bb90eb00 89 int dma_requested;
a5f6abd4
WB		 90 dma_addr_t rx_dma;
91 dma_addr_t tx_dma;
bb90eb00 92
a5f6abd4
WB		 93 size_t rx_map_len;
94 size_t tx_map_len;
95 u8 n_bytes;
fad91c89 96 int cs_change;
a5f6abd4
WB		 97 void (*write) (struct driver_data *);
98 void (*read) (struct driver_data *);
99 void (*duplex) (struct driver_data *);
100};
101
102struct chip_data {
103 u16 ctl_reg;
104 u16 baud;
105 u16 flag;
106
107 u8 chip_select_num;
108 u8 n_bytes;
88b40369 109 u8 width; /* 0 or 1 */
a5f6abd4
WB		 110 u8 enable_dma;
111 u8 bits_per_word; /* 8 or 16 */
112 u8 cs_change_per_word;
62310e51 113 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
a5f6abd4
WB		 114 void (*write) (struct driver_data *);
115 void (*read) (struct driver_data *);
116 void (*duplex) (struct driver_data *);
117};
118
bb90eb00
BW		 119#define DEFINE_SPI_REG(reg, off) \
120static inline u16 read_##reg(struct driver_data *drv_data) \
121 { return bfin_read16(drv_data->regs_base + off); } \
122static inline void write_##reg(struct driver_data *drv_data, u16 v) \
123 { bfin_write16(drv_data->regs_base + off, v); }
124
125DEFINE_SPI_REG(CTRL, 0x00)
126DEFINE_SPI_REG(FLAG, 0x04)
127DEFINE_SPI_REG(STAT, 0x08)
128DEFINE_SPI_REG(TDBR, 0x0C)
129DEFINE_SPI_REG(RDBR, 0x10)
130DEFINE_SPI_REG(BAUD, 0x14)
131DEFINE_SPI_REG(SHAW, 0x18)
132
88b40369 133static void bfin_spi_enable(struct driver_data *drv_data)
a5f6abd4
WB		 134{
135 u16 cr;
136
bb90eb00
BW		 137 cr = read_CTRL(drv_data);
138 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
a5f6abd4
WB		 139}
140
88b40369 141static void bfin_spi_disable(struct driver_data *drv_data)
a5f6abd4
WB		 142{
143 u16 cr;
144
bb90eb00
BW		 145 cr = read_CTRL(drv_data);
146 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
a5f6abd4
WB		 147}
148
149/* Caculate the SPI_BAUD register value based on input HZ */
150static u16 hz_to_spi_baud(u32 speed_hz)
151{
152 u_long sclk = get_sclk();
153 u16 spi_baud = (sclk / (2 * speed_hz));
154
155 if ((sclk % (2 * speed_hz)) > 0)
156 spi_baud++;
157
7513e006
MH		 158 if (spi_baud < MIN_SPI_BAUD_VAL)
159 spi_baud = MIN_SPI_BAUD_VAL;
160
a5f6abd4
WB		 161 return spi_baud;
162}
163
164static int flush(struct driver_data *drv_data)
165{
166 unsigned long limit = loops_per_jiffy << 1;
167
168 /* wait for stop and clear stat */
bb90eb00 169 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
d8c05008 170 cpu_relax();
a5f6abd4 171
bb90eb00 172 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4
WB		 173
174 return limit;
175}
176
fad91c89 177/* Chip select operation functions for cs_change flag */
bb90eb00 178static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 179{
bb90eb00 180 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 181
182 flag |= chip->flag;
183 flag &= ~(chip->flag << 8);
184
bb90eb00 185 write_FLAG(drv_data, flag);
fad91c89
BW		 186}
187
bb90eb00 188static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 189{
bb90eb00 190 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 191
192 flag |= (chip->flag << 8);
193
bb90eb00 194 write_FLAG(drv_data, flag);
62310e51
BW		 195
196 /* Move delay here for consistency */
197 if (chip->cs_chg_udelay)
198 udelay(chip->cs_chg_udelay);
fad91c89
BW		 199}
200
7c4ef094 201#define MAX_SPI_SSEL 7
5fec5b5a 202
a5f6abd4 203/* stop controller and re-config current chip*/
8d20d0a7 204static void restore_state(struct driver_data *drv_data)
a5f6abd4
WB		 205{
206 struct chip_data *chip = drv_data->cur_chip;
12e17c42 207
a5f6abd4 208 /* Clear status and disable clock */
bb90eb00 209 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4 210 bfin_spi_disable(drv_data);
88b40369 211 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
a5f6abd4 212
5fec5b5a 213 /* Load the registers */
bb90eb00 214 write_CTRL(drv_data, chip->ctl_reg);
092e1fda 215 write_BAUD(drv_data, chip->baud);
cc487e73
SZ		 216
217 bfin_spi_enable(drv_data);
07612e5f 218 cs_active(drv_data, chip);
a5f6abd4
WB		 219}
220
221/* used to kick off transfer in rx mode */
bb90eb00 222static unsigned short dummy_read(struct driver_data *drv_data)
a5f6abd4
WB		 223{
224 unsigned short tmp;
bb90eb00 225 tmp = read_RDBR(drv_data);
a5f6abd4
WB		 226 return tmp;
227}
228
229static void null_writer(struct driver_data *drv_data)
230{
231 u8 n_bytes = drv_data->n_bytes;
232
233 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 234 write_TDBR(drv_data, 0);
235 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 236 cpu_relax();
a5f6abd4
WB		 237 drv_data->tx += n_bytes;
238 }
239}
240
241static void null_reader(struct driver_data *drv_data)
242{
243 u8 n_bytes = drv_data->n_bytes;
bb90eb00 244 dummy_read(drv_data);
a5f6abd4
WB		 245
246 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 247 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 248 cpu_relax();
bb90eb00 249 dummy_read(drv_data);
a5f6abd4
WB		 250 drv_data->rx += n_bytes;
251 }
252}
253
254static void u8_writer(struct driver_data *drv_data)
255{
131b17d4 256 dev_dbg(&drv_data->pdev->dev,
bb90eb00 257 "cr8-s is 0x%x\n", read_STAT(drv_data));
cc487e73 258
a5f6abd4 259 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 260 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
261 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 262 cpu_relax();
a5f6abd4
WB		 263 ++drv_data->tx;
264 }
13f3e642
SZ		 265
266 /* poll for SPI completion before return */
267 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
268 cpu_relax();
a5f6abd4
WB		 269}
270
271static void u8_cs_chg_writer(struct driver_data *drv_data)
272{
273 struct chip_data *chip = drv_data->cur_chip;
274
275 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 276 cs_active(drv_data, chip);
a5f6abd4 277
bb90eb00
BW		 278 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
279 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 280 cpu_relax();
e26aa015
BW		 281 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
282 cpu_relax();
62310e51 283
bb90eb00 284 cs_deactive(drv_data, chip);
5fec5b5a 285
a5f6abd4
WB		 286 ++drv_data->tx;
287 }
a5f6abd4
WB		 288}
289
290static void u8_reader(struct driver_data *drv_data)
291{
131b17d4 292 dev_dbg(&drv_data->pdev->dev,
bb90eb00 293 "cr-8 is 0x%x\n", read_STAT(drv_data));
a5f6abd4 294
3f479a65 295 /* poll for SPI completion before start */
bb90eb00 296 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 297 cpu_relax();
3f479a65 298
a5f6abd4 299 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 300 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 301
bb90eb00 302 dummy_read(drv_data);
cc487e73 303
a5f6abd4 304 while (drv_data->rx < drv_data->rx_end - 1) {
bb90eb00 305 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 306 cpu_relax();
bb90eb00 307 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 308 ++drv_data->rx;
309 }
310
bb90eb00 311 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 312 cpu_relax();
bb90eb00 313 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 314 ++drv_data->rx;
315}
316
317static void u8_cs_chg_reader(struct driver_data *drv_data)
318{
319 struct chip_data *chip = drv_data->cur_chip;
320
e26aa015
BW		 321 while (drv_data->rx < drv_data->rx_end) {
322 cs_active(drv_data, chip);
323 read_RDBR(drv_data); /* kick off */
a5f6abd4 324
e26aa015
BW		 325 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
326 cpu_relax();
327 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
328 cpu_relax();
cc487e73 329
e26aa015 330 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
bb90eb00 331 cs_deactive(drv_data, chip);
5fec5b5a 332
a5f6abd4
WB		 333 ++drv_data->rx;
334 }
a5f6abd4
WB		 335}
336
337static void u8_duplex(struct driver_data *drv_data)
338{
339 /* in duplex mode, clk is triggered by writing of TDBR */
340 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 341 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
4fd432d9 342 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 343 cpu_relax();
bb90eb00 344 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 345 cpu_relax();
bb90eb00 346 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 347 ++drv_data->rx;
348 ++drv_data->tx;
349 }
350}
351
352static void u8_cs_chg_duplex(struct driver_data *drv_data)
353{
354 struct chip_data *chip = drv_data->cur_chip;
355
356 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 357 cs_active(drv_data, chip);
5fec5b5a 358
bb90eb00 359 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
e26aa015
BW		 360
361 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 362 cpu_relax();
bb90eb00 363 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 364 cpu_relax();
bb90eb00 365 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 366
bb90eb00 367 cs_deactive(drv_data, chip);
5fec5b5a 368
a5f6abd4
WB		 369 ++drv_data->rx;
370 ++drv_data->tx;
371 }
a5f6abd4
WB		 372}
373
374static void u16_writer(struct driver_data *drv_data)
375{
131b17d4 376 dev_dbg(&drv_data->pdev->dev,
bb90eb00 377 "cr16 is 0x%x\n", read_STAT(drv_data));
88b40369 378
a5f6abd4 379 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 380 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
381 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 382 cpu_relax();
a5f6abd4
WB		 383 drv_data->tx += 2;
384 }
13f3e642
SZ		 385
386 /* poll for SPI completion before return */
387 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
388 cpu_relax();
a5f6abd4
WB		 389}
390
391static void u16_cs_chg_writer(struct driver_data *drv_data)
392{
393 struct chip_data *chip = drv_data->cur_chip;
394
395 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 396 cs_active(drv_data, chip);
a5f6abd4 397
bb90eb00
BW		 398 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
399 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 400 cpu_relax();
13f3e642
SZ		 401 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
402 cpu_relax();
62310e51 403
bb90eb00 404 cs_deactive(drv_data, chip);
5fec5b5a 405
a5f6abd4
WB		 406 drv_data->tx += 2;
407 }
a5f6abd4
WB		 408}
409
410static void u16_reader(struct driver_data *drv_data)
411{
88b40369 412 dev_dbg(&drv_data->pdev->dev,
bb90eb00 413 "cr-16 is 0x%x\n", read_STAT(drv_data));
cc487e73 414
3f479a65 415 /* poll for SPI completion before start */
bb90eb00 416 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 417 cpu_relax();
3f479a65 418
cc487e73 419 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 420 write_TDBR(drv_data, 0xFFFF);
cc487e73 421
bb90eb00 422 dummy_read(drv_data);
a5f6abd4
WB		 423
424 while (drv_data->rx < (drv_data->rx_end - 2)) {
bb90eb00 425 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 426 cpu_relax();
bb90eb00 427 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 428 drv_data->rx += 2;
429 }
430
bb90eb00 431 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 432 cpu_relax();
bb90eb00 433 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 434 drv_data->rx += 2;
435}
436
437static void u16_cs_chg_reader(struct driver_data *drv_data)
438{
439 struct chip_data *chip = drv_data->cur_chip;
440
3f479a65 441 /* poll for SPI completion before start */
bb90eb00 442 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 443 cpu_relax();
3f479a65 444
cc487e73 445 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 446 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 447
bb90eb00
BW		 448 cs_active(drv_data, chip);
449 dummy_read(drv_data);
cc487e73 450
c3061abb 451 while (drv_data->rx < drv_data->rx_end - 2) {
bb90eb00 452 cs_deactive(drv_data, chip);
5fec5b5a 453
bb90eb00 454 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 455 cpu_relax();
bb90eb00
BW		 456 cs_active(drv_data, chip);
457 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 458 drv_data->rx += 2;
459 }
bb90eb00 460 cs_deactive(drv_data, chip);
cc487e73 461
bb90eb00 462 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 463 cpu_relax();
bb90eb00 464 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
cc487e73 465 drv_data->rx += 2;
a5f6abd4
WB		 466}
467
468static void u16_duplex(struct driver_data *drv_data)
469{
470 /* in duplex mode, clk is triggered by writing of TDBR */
471 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 472 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
4fd432d9 473 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 474 cpu_relax();
bb90eb00 475 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 476 cpu_relax();
bb90eb00 477 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 478 drv_data->rx += 2;
479 drv_data->tx += 2;
480 }
481}
482
483static void u16_cs_chg_duplex(struct driver_data *drv_data)
484{
485 struct chip_data *chip = drv_data->cur_chip;
486
487 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 488 cs_active(drv_data, chip);
a5f6abd4 489
bb90eb00 490 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
4fd432d9 491 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 492 cpu_relax();
bb90eb00 493 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 494 cpu_relax();
bb90eb00 495 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 496
bb90eb00 497 cs_deactive(drv_data, chip);
5fec5b5a 498
a5f6abd4
WB		 499 drv_data->rx += 2;
500 drv_data->tx += 2;
501 }
a5f6abd4
WB		 502}
503
504/* test if ther is more transfer to be done */
505static void *next_transfer(struct driver_data *drv_data)
506{
507 struct spi_message *msg = drv_data->cur_msg;
508 struct spi_transfer *trans = drv_data->cur_transfer;
509
510 /* Move to next transfer */
511 if (trans->transfer_list.next != &msg->transfers) {
512 drv_data->cur_transfer =
513 list_entry(trans->transfer_list.next,
514 struct spi_transfer, transfer_list);
515 return RUNNING_STATE;
516 } else
517 return DONE_STATE;
518}
519
520/*
521 * caller already set message->status;
522 * dma and pio irqs are blocked give finished message back
523 */
524static void giveback(struct driver_data *drv_data)
525{
fad91c89 526 struct chip_data *chip = drv_data->cur_chip;
a5f6abd4
WB		 527 struct spi_transfer *last_transfer;
528 unsigned long flags;
529 struct spi_message *msg;
530
531 spin_lock_irqsave(&drv_data->lock, flags);
532 msg = drv_data->cur_msg;
533 drv_data->cur_msg = NULL;
534 drv_data->cur_transfer = NULL;
535 drv_data->cur_chip = NULL;
536 queue_work(drv_data->workqueue, &drv_data->pump_messages);
537 spin_unlock_irqrestore(&drv_data->lock, flags);
538
539 last_transfer = list_entry(msg->transfers.prev,
540 struct spi_transfer, transfer_list);
541
542 msg->state = NULL;
543
544 /* disable chip select signal. And not stop spi in autobuffer mode */
545 if (drv_data->tx_dma != 0xFFFF) {
bb90eb00 546 cs_deactive(drv_data, chip);
a5f6abd4
WB		 547 bfin_spi_disable(drv_data);
548 }
549
fad91c89 550 if (!drv_data->cs_change)
bb90eb00 551 cs_deactive(drv_data, chip);
fad91c89 552
a5f6abd4
WB		 553 if (msg->complete)
554 msg->complete(msg->context);
555}
556
88b40369 557static irqreturn_t dma_irq_handler(int irq, void *dev_id)
a5f6abd4 558{
15aafa2f 559 struct driver_data *drv_data = dev_id;
fad91c89 560 struct chip_data *chip = drv_data->cur_chip;
bb90eb00 561 struct spi_message *msg = drv_data->cur_msg;
d24bd1d0 562 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
04b95d2f 563 u16 spistat = read_STAT(drv_data);
a5f6abd4 564
d24bd1d0
MF		 565 dev_dbg(&drv_data->pdev->dev,
566 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
567 dmastat, spistat);
568
bb90eb00 569 clear_dma_irqstat(drv_data->dma_channel);
a5f6abd4 570
d6fe89b0 571 /* Wait for DMA to complete */
bb90eb00 572 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
d8c05008 573 cpu_relax();
d6fe89b0 574
a5f6abd4 575 /*
d6fe89b0
BW		 576 * wait for the last transaction shifted out. HRM states:
577 * at this point there may still be data in the SPI DMA FIFO waiting
578 * to be transmitted ... software needs to poll TXS in the SPI_STAT
579 * register until it goes low for 2 successive reads
a5f6abd4
WB		 580 */
581 if (drv_data->tx != NULL) {
bb90eb00
BW		 582 while ((read_STAT(drv_data) & TXS) ||
583 (read_STAT(drv_data) & TXS))
d8c05008 584 cpu_relax();
a5f6abd4
WB		 585 }
586
bb90eb00 587 while (!(read_STAT(drv_data) & SPIF))
d8c05008 588 cpu_relax();
a5f6abd4 589
40a2945b 590 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
04b95d2f
MF		 591 msg->state = ERROR_STATE;
592 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
593 } else {
594 msg->actual_length += drv_data->len_in_bytes;
a5f6abd4 595
04b95d2f
MF		 596 if (drv_data->cs_change)
597 cs_deactive(drv_data, chip);
fad91c89 598
04b95d2f
MF		 599 /* Move to next transfer */
600 msg->state = next_transfer(drv_data);
601 }
a5f6abd4
WB		 602
603 /* Schedule transfer tasklet */
604 tasklet_schedule(&drv_data->pump_transfers);
605
606 /* free the irq handler before next transfer */
88b40369
BW		 607 dev_dbg(&drv_data->pdev->dev,
608 "disable dma channel irq%d\n",
bb90eb00
BW		 609 drv_data->dma_channel);
610 dma_disable_irq(drv_data->dma_channel);
a5f6abd4
WB		 611
612 return IRQ_HANDLED;
613}
614
615static void pump_transfers(unsigned long data)
616{
617 struct driver_data *drv_data = (struct driver_data *)data;
618 struct spi_message *message = NULL;
619 struct spi_transfer *transfer = NULL;
620 struct spi_transfer *previous = NULL;
621 struct chip_data *chip = NULL;
88b40369
BW		 622 u8 width;
623 u16 cr, dma_width, dma_config;
a5f6abd4 624 u32 tranf_success = 1;
8eeb12e5 625 u8 full_duplex = 0;
a5f6abd4
WB		 626
627 /* Get current state information */
628 message = drv_data->cur_msg;
629 transfer = drv_data->cur_transfer;
630 chip = drv_data->cur_chip;
092e1fda 631
a5f6abd4
WB		 632 /*
633 * if msg is error or done, report it back using complete() callback
634 */
635
636 /* Handle for abort */
637 if (message->state == ERROR_STATE) {
d24bd1d0 638 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
a5f6abd4
WB		 639 message->status = -EIO;
640 giveback(drv_data);
641 return;
642 }
643
644 /* Handle end of message */
645 if (message->state == DONE_STATE) {
d24bd1d0 646 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
a5f6abd4
WB		 647 message->status = 0;
648 giveback(drv_data);
649 return;
650 }
651
652 /* Delay if requested at end of transfer */
653 if (message->state == RUNNING_STATE) {
d24bd1d0 654 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
a5f6abd4
WB		 655 previous = list_entry(transfer->transfer_list.prev,
656 struct spi_transfer, transfer_list);
657 if (previous->delay_usecs)
658 udelay(previous->delay_usecs);
659 }
660
661 /* Setup the transfer state based on the type of transfer */
662 if (flush(drv_data) == 0) {
663 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
664 message->status = -EIO;
665 giveback(drv_data);
666 return;
667 }
668
669 if (transfer->tx_buf != NULL) {
670 drv_data->tx = (void *)transfer->tx_buf;
671 drv_data->tx_end = drv_data->tx + transfer->len;
88b40369
BW		 672 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
673 transfer->tx_buf, drv_data->tx_end);
a5f6abd4
WB		 674 } else {
675 drv_data->tx = NULL;
676 }
677
678 if (transfer->rx_buf != NULL) {
8eeb12e5 679 full_duplex = transfer->tx_buf != NULL;
a5f6abd4
WB		 680 drv_data->rx = transfer->rx_buf;
681 drv_data->rx_end = drv_data->rx + transfer->len;
88b40369
BW		 682 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
683 transfer->rx_buf, drv_data->rx_end);
a5f6abd4
WB		 684 } else {
685 drv_data->rx = NULL;
686 }
687
688 drv_data->rx_dma = transfer->rx_dma;
689 drv_data->tx_dma = transfer->tx_dma;
690 drv_data->len_in_bytes = transfer->len;
fad91c89 691 drv_data->cs_change = transfer->cs_change;
a5f6abd4 692
092e1fda
BW		 693 /* Bits per word setup */
694 switch (transfer->bits_per_word) {
695 case 8:
696 drv_data->n_bytes = 1;
697 width = CFG_SPI_WORDSIZE8;
698 drv_data->read = chip->cs_change_per_word ?
699 u8_cs_chg_reader : u8_reader;
700 drv_data->write = chip->cs_change_per_word ?
701 u8_cs_chg_writer : u8_writer;
702 drv_data->duplex = chip->cs_change_per_word ?
703 u8_cs_chg_duplex : u8_duplex;
704 break;
705
706 case 16:
707 drv_data->n_bytes = 2;
708 width = CFG_SPI_WORDSIZE16;
709 drv_data->read = chip->cs_change_per_word ?
710 u16_cs_chg_reader : u16_reader;
711 drv_data->write = chip->cs_change_per_word ?
712 u16_cs_chg_writer : u16_writer;
713 drv_data->duplex = chip->cs_change_per_word ?
714 u16_cs_chg_duplex : u16_duplex;
715 break;
716
717 default:
718 /* No change, the same as default setting */
719 drv_data->n_bytes = chip->n_bytes;
720 width = chip->width;
721 drv_data->write = drv_data->tx ? chip->write : null_writer;
722 drv_data->read = drv_data->rx ? chip->read : null_reader;
723 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
724 break;
725 }
726 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
727 cr |= (width << 8);
728 write_CTRL(drv_data, cr);
729
a5f6abd4
WB		 730 if (width == CFG_SPI_WORDSIZE16) {
731 drv_data->len = (transfer->len) >> 1;
732 } else {
733 drv_data->len = transfer->len;
734 }
4fb98efa
MF		 735 dev_dbg(&drv_data->pdev->dev,
736 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
131b17d4 737 drv_data->write, chip->write, null_writer);
a5f6abd4
WB		 738
739 /* speed and width has been set on per message */
740 message->state = RUNNING_STATE;
741 dma_config = 0;
742
092e1fda
BW		 743 /* Speed setup (surely valid because already checked) */
744 if (transfer->speed_hz)
745 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
746 else
747 write_BAUD(drv_data, chip->baud);
748
bb90eb00
BW		 749 write_STAT(drv_data, BIT_STAT_CLR);
750 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
751 cs_active(drv_data, chip);
a5f6abd4 752
88b40369
BW		 753 dev_dbg(&drv_data->pdev->dev,
754 "now pumping a transfer: width is %d, len is %d\n",
755 width, transfer->len);
a5f6abd4
WB		 756
757 /*
8cf5858c
VM		 758 * Try to map dma buffer and do a dma transfer. If successful use,
759 * different way to r/w according to the enable_dma settings and if
760 * we are not doing a full duplex transfer (since the hardware does
761 * not support full duplex DMA transfers).
a5f6abd4 762 */
8eeb12e5
VM		 763 if (!full_duplex && drv_data->cur_chip->enable_dma
764 && drv_data->len > 6) {
a5f6abd4 765
7aec3566
MF		 766 unsigned long dma_start_addr;
767
bb90eb00
BW		 768 disable_dma(drv_data->dma_channel);
769 clear_dma_irqstat(drv_data->dma_channel);
07612e5f 770 bfin_spi_disable(drv_data);
a5f6abd4
WB		 771
772 /* config dma channel */
88b40369 773 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
7aec3566 774 set_dma_x_count(drv_data->dma_channel, drv_data->len);
a5f6abd4 775 if (width == CFG_SPI_WORDSIZE16) {
bb90eb00 776 set_dma_x_modify(drv_data->dma_channel, 2);
a5f6abd4
WB		 777 dma_width = WDSIZE_16;
778 } else {
bb90eb00 779 set_dma_x_modify(drv_data->dma_channel, 1);
a5f6abd4
WB		 780 dma_width = WDSIZE_8;
781 }
782
3f479a65 783 /* poll for SPI completion before start */
bb90eb00 784 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 785 cpu_relax();
3f479a65 786
a5f6abd4
WB		 787 /* dirty hack for autobuffer DMA mode */
788 if (drv_data->tx_dma == 0xFFFF) {
88b40369
BW		 789 dev_dbg(&drv_data->pdev->dev,
790 "doing autobuffer DMA out.\n");
a5f6abd4
WB		 791
792 /* no irq in autobuffer mode */
793 dma_config =
794 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
bb90eb00
BW		 795 set_dma_config(drv_data->dma_channel, dma_config);
796 set_dma_start_addr(drv_data->dma_channel,
a32c691d 797 (unsigned long)drv_data->tx);
bb90eb00 798 enable_dma(drv_data->dma_channel);
a5f6abd4 799
07612e5f
SZ		 800 /* start SPI transfer */
801 write_CTRL(drv_data,
802 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
803
804 /* just return here, there can only be one transfer
805 * in this mode
806 */
a5f6abd4
WB		 807 message->status = 0;
808 giveback(drv_data);
809 return;
810 }
811
812 /* In dma mode, rx or tx must be NULL in one transfer */
7aec3566 813 dma_config = (RESTART | dma_width | DI_EN);
a5f6abd4
WB		 814 if (drv_data->rx != NULL) {
815 /* set transfer mode, and enable SPI */
d24bd1d0
MF		 816 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
817 drv_data->rx, drv_data->len_in_bytes);
a5f6abd4 818
8cf5858c
VM		 819 /* invalidate caches, if needed */
820 if (bfin_addr_dcachable((unsigned long) drv_data->rx))
821 invalidate_dcache_range((unsigned long) drv_data->rx,
822 (unsigned long) (drv_data->rx +
ace32865 823 drv_data->len_in_bytes));
8cf5858c 824
a5f6abd4 825 /* clear tx reg soformer data is not shifted out */
bb90eb00 826 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 827
7aec3566
MF		 828 dma_config |= WNR;
829 dma_start_addr = (unsigned long)drv_data->rx;
830 cr |= CFG_SPI_DMAREAD;
07612e5f 831
a5f6abd4 832 } else if (drv_data->tx != NULL) {
88b40369 833 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
a5f6abd4 834
8cf5858c
VM		 835 /* flush caches, if needed */
836 if (bfin_addr_dcachable((unsigned long) drv_data->tx))
837 flush_dcache_range((unsigned long) drv_data->tx,
838 (unsigned long) (drv_data->tx +
ace32865 839 drv_data->len_in_bytes));
8cf5858c 840
7aec3566
MF		 841 dma_start_addr = (unsigned long)drv_data->tx;
842 cr |= CFG_SPI_DMAWRITE;
843
844 } else
845 BUG();
846
847 /* start dma */
848 dma_enable_irq(drv_data->dma_channel);
849 set_dma_config(drv_data->dma_channel, dma_config);
850 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
851 enable_dma(drv_data->dma_channel);
852
853 /* start SPI transfer */
854 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
07612e5f 855
a5f6abd4
WB		 856 } else {
857 /* IO mode write then read */
88b40369 858 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
a5f6abd4 859
8eeb12e5 860 if (full_duplex) {
a5f6abd4
WB		 861 /* full duplex mode */
862 BUG_ON((drv_data->tx_end - drv_data->tx) !=
863 (drv_data->rx_end - drv_data->rx));
88b40369
BW		 864 dev_dbg(&drv_data->pdev->dev,
865 "IO duplex: cr is 0x%x\n", cr);
a5f6abd4 866
cc487e73 867 /* set SPI transfer mode */
bb90eb00 868 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 869
870 drv_data->duplex(drv_data);
871
872 if (drv_data->tx != drv_data->tx_end)
873 tranf_success = 0;
874 } else if (drv_data->tx != NULL) {
875 /* write only half duplex */
131b17d4 876 dev_dbg(&drv_data->pdev->dev,
88b40369 877 "IO write: cr is 0x%x\n", cr);
a5f6abd4 878
cc487e73 879 /* set SPI transfer mode */
bb90eb00 880 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 881
882 drv_data->write(drv_data);
883
884 if (drv_data->tx != drv_data->tx_end)
885 tranf_success = 0;
886 } else if (drv_data->rx != NULL) {
887 /* read only half duplex */
131b17d4 888 dev_dbg(&drv_data->pdev->dev,
88b40369 889 "IO read: cr is 0x%x\n", cr);
a5f6abd4 890
cc487e73 891 /* set SPI transfer mode */
bb90eb00 892 write_CTRL(drv_data, (cr | CFG_SPI_READ));
a5f6abd4
WB		 893
894 drv_data->read(drv_data);
895 if (drv_data->rx != drv_data->rx_end)
896 tranf_success = 0;
897 }
898
899 if (!tranf_success) {
131b17d4 900 dev_dbg(&drv_data->pdev->dev,
88b40369 901 "IO write error!\n");
a5f6abd4
WB		 902 message->state = ERROR_STATE;
903 } else {
904 /* Update total byte transfered */
ace32865 905 message->actual_length += drv_data->len_in_bytes;
a5f6abd4
WB		 906
907 /* Move to next transfer of this msg */
908 message->state = next_transfer(drv_data);
909 }
910
911 /* Schedule next transfer tasklet */
912 tasklet_schedule(&drv_data->pump_transfers);
913
914 }
915}
916
917/* pop a msg from queue and kick off real transfer */
918static void pump_messages(struct work_struct *work)
919{
131b17d4 920 struct driver_data *drv_data;
a5f6abd4
WB		 921 unsigned long flags;
922
131b17d4
BW		 923 drv_data = container_of(work, struct driver_data, pump_messages);
924
a5f6abd4
WB		 925 /* Lock queue and check for queue work */
926 spin_lock_irqsave(&drv_data->lock, flags);
927 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
928 /* pumper kicked off but no work to do */
929 drv_data->busy = 0;
930 spin_unlock_irqrestore(&drv_data->lock, flags);
931 return;
932 }
933
934 /* Make sure we are not already running a message */
935 if (drv_data->cur_msg) {
936 spin_unlock_irqrestore(&drv_data->lock, flags);
937 return;
938 }
939
940 /* Extract head of queue */
941 drv_data->cur_msg = list_entry(drv_data->queue.next,
942 struct spi_message, queue);
5fec5b5a
BW		 943
944 /* Setup the SSP using the per chip configuration */
945 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
8d20d0a7 946 restore_state(drv_data);
5fec5b5a 947
a5f6abd4
WB		 948 list_del_init(&drv_data->cur_msg->queue);
949
950 /* Initial message state */
951 drv_data->cur_msg->state = START_STATE;
952 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
953 struct spi_transfer, transfer_list);
954
5fec5b5a
BW		 955 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
956 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
957 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
958 drv_data->cur_chip->ctl_reg);
131b17d4
BW		 959
960 dev_dbg(&drv_data->pdev->dev,
88b40369
BW		 961 "the first transfer len is %d\n",
962 drv_data->cur_transfer->len);
a5f6abd4
WB		 963
964 /* Mark as busy and launch transfers */
965 tasklet_schedule(&drv_data->pump_transfers);
966
967 drv_data->busy = 1;
968 spin_unlock_irqrestore(&drv_data->lock, flags);
969}
970
971/*
972 * got a msg to transfer, queue it in drv_data->queue.
973 * And kick off message pumper
974 */
975static int transfer(struct spi_device *spi, struct spi_message *msg)
976{
977 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
978 unsigned long flags;
979
980 spin_lock_irqsave(&drv_data->lock, flags);
981
982 if (drv_data->run == QUEUE_STOPPED) {
983 spin_unlock_irqrestore(&drv_data->lock, flags);
984 return -ESHUTDOWN;
985 }
986
987 msg->actual_length = 0;
988 msg->status = -EINPROGRESS;
989 msg->state = START_STATE;
990
88b40369 991 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
a5f6abd4
WB		 992 list_add_tail(&msg->queue, &drv_data->queue);
993
994 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
995 queue_work(drv_data->workqueue, &drv_data->pump_messages);
996
997 spin_unlock_irqrestore(&drv_data->lock, flags);
998
999 return 0;
1000}
1001
12e17c42
SZ		 1002#define MAX_SPI_SSEL 7
1003
1004static u16 ssel[3][MAX_SPI_SSEL] = {
1005 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1006 P_SPI0_SSEL4, P_SPI0_SSEL5,
1007 P_SPI0_SSEL6, P_SPI0_SSEL7},
1008
1009 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1010 P_SPI1_SSEL4, P_SPI1_SSEL5,
1011 P_SPI1_SSEL6, P_SPI1_SSEL7},
1012
1013 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1014 P_SPI2_SSEL4, P_SPI2_SSEL5,
1015 P_SPI2_SSEL6, P_SPI2_SSEL7},
1016};
1017
a5f6abd4
WB		 1018/* first setup for new devices */
1019static int setup(struct spi_device *spi)
1020{
1021 struct bfin5xx_spi_chip *chip_info = NULL;
1022 struct chip_data *chip;
1023 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1024 u8 spi_flg;
1025
1026 /* Abort device setup if requested features are not supported */
1027 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1028 dev_err(&spi->dev, "requested mode not fully supported\n");
1029 return -EINVAL;
1030 }
1031
1032 /* Zero (the default) here means 8 bits */
1033 if (!spi->bits_per_word)
1034 spi->bits_per_word = 8;
1035
1036 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1037 return -EINVAL;
1038
1039 /* Only alloc (or use chip_info) on first setup */
1040 chip = spi_get_ctldata(spi);
1041 if (chip == NULL) {
1042 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1043 if (!chip)
1044 return -ENOMEM;
1045
1046 chip->enable_dma = 0;
1047 chip_info = spi->controller_data;
1048 }
1049
1050 /* chip_info isn't always needed */
1051 if (chip_info) {
2ed35516
MF		 1052 /* Make sure people stop trying to set fields via ctl_reg
1053 * when they should actually be using common SPI framework.
1054 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1055 * Not sure if a user actually needs/uses any of these,
1056 * but let's assume (for now) they do.
1057 */
1058 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1059 dev_err(&spi->dev, "do not set bits in ctl_reg "
1060 "that the SPI framework manages\n");
1061 return -EINVAL;
1062 }
1063
a5f6abd4
WB		 1064 chip->enable_dma = chip_info->enable_dma != 0
1065 && drv_data->master_info->enable_dma;
1066 chip->ctl_reg = chip_info->ctl_reg;
1067 chip->bits_per_word = chip_info->bits_per_word;
1068 chip->cs_change_per_word = chip_info->cs_change_per_word;
1069 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1070 }
1071
1072 /* translate common spi framework into our register */
1073 if (spi->mode & SPI_CPOL)
1074 chip->ctl_reg |= CPOL;
1075 if (spi->mode & SPI_CPHA)
1076 chip->ctl_reg |= CPHA;
1077 if (spi->mode & SPI_LSB_FIRST)
1078 chip->ctl_reg |= LSBF;
1079 /* we dont support running in slave mode (yet?) */
1080 chip->ctl_reg |= MSTR;
1081
1082 /*
1083 * if any one SPI chip is registered and wants DMA, request the
1084 * DMA channel for it
1085 */
bb90eb00 1086 if (chip->enable_dma && !drv_data->dma_requested) {
a5f6abd4 1087 /* register dma irq handler */
59bfcc66 1088 if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) {
88b40369
BW		 1089 dev_dbg(&spi->dev,
1090 "Unable to request BlackFin SPI DMA channel\n");
a5f6abd4
WB		 1091 return -ENODEV;
1092 }
bb90eb00 1093 if (set_dma_callback(drv_data->dma_channel,
59bfcc66 1094 dma_irq_handler, drv_data) < 0) {
88b40369 1095 dev_dbg(&spi->dev, "Unable to set dma callback\n");
a5f6abd4
WB		 1096 return -EPERM;
1097 }
bb90eb00
BW		 1098 dma_disable_irq(drv_data->dma_channel);
1099 drv_data->dma_requested = 1;
a5f6abd4
WB		 1100 }
1101
1102 /*
1103 * Notice: for blackfin, the speed_hz is the value of register
1104 * SPI_BAUD, not the real baudrate
1105 */
1106 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1107 spi_flg = ~(1 << (spi->chip_select));
1108 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1109 chip->chip_select_num = spi->chip_select;
1110
1111 switch (chip->bits_per_word) {
1112 case 8:
1113 chip->n_bytes = 1;
1114 chip->width = CFG_SPI_WORDSIZE8;
1115 chip->read = chip->cs_change_per_word ?
1116 u8_cs_chg_reader : u8_reader;
1117 chip->write = chip->cs_change_per_word ?
1118 u8_cs_chg_writer : u8_writer;
1119 chip->duplex = chip->cs_change_per_word ?
1120 u8_cs_chg_duplex : u8_duplex;
1121 break;
1122
1123 case 16:
1124 chip->n_bytes = 2;
1125 chip->width = CFG_SPI_WORDSIZE16;
1126 chip->read = chip->cs_change_per_word ?
1127 u16_cs_chg_reader : u16_reader;
1128 chip->write = chip->cs_change_per_word ?
1129 u16_cs_chg_writer : u16_writer;
1130 chip->duplex = chip->cs_change_per_word ?
1131 u16_cs_chg_duplex : u16_duplex;
1132 break;
1133
1134 default:
1135 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1136 chip->bits_per_word);
1137 kfree(chip);
1138 return -ENODEV;
1139 }
1140
898eb71c 1141 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
a5f6abd4 1142 spi->modalias, chip->width, chip->enable_dma);
88b40369 1143 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
a5f6abd4
WB		 1144 chip->ctl_reg, chip->flag);
1145
1146 spi_set_ctldata(spi, chip);
1147
12e17c42
SZ		 1148 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1149 if ((chip->chip_select_num > 0)
1150 && (chip->chip_select_num <= spi->master->num_chipselect))
1151 peripheral_request(ssel[spi->master->bus_num]
aab0d83e 1152 [chip->chip_select_num-1], spi->modalias);
12e17c42 1153
07612e5f
SZ		 1154 cs_deactive(drv_data, chip);
1155
a5f6abd4
WB		 1156 return 0;
1157}
1158
1159/*
1160 * callback for spi framework.
1161 * clean driver specific data
1162 */
88b40369 1163static void cleanup(struct spi_device *spi)
a5f6abd4 1164{
27bb9e79 1165 struct chip_data *chip = spi_get_ctldata(spi);
a5f6abd4 1166
12e17c42
SZ		 1167 if ((chip->chip_select_num > 0)
1168 && (chip->chip_select_num <= spi->master->num_chipselect))
1169 peripheral_free(ssel[spi->master->bus_num]
1170 [chip->chip_select_num-1]);
1171
a5f6abd4
WB		 1172 kfree(chip);
1173}
1174
1175static inline int init_queue(struct driver_data *drv_data)
1176{
1177 INIT_LIST_HEAD(&drv_data->queue);
1178 spin_lock_init(&drv_data->lock);
1179
1180 drv_data->run = QUEUE_STOPPED;
1181 drv_data->busy = 0;
1182
1183 /* init transfer tasklet */
1184 tasklet_init(&drv_data->pump_transfers,
1185 pump_transfers, (unsigned long)drv_data);
1186
1187 /* init messages workqueue */
1188 INIT_WORK(&drv_data->pump_messages, pump_messages);
6c7377ab
KS		 1189 drv_data->workqueue = create_singlethread_workqueue(
1190 dev_name(drv_data->master->dev.parent));
a5f6abd4
WB		 1191 if (drv_data->workqueue == NULL)
1192 return -EBUSY;
1193
1194 return 0;
1195}
1196
1197static inline int start_queue(struct driver_data *drv_data)
1198{
1199 unsigned long flags;
1200
1201 spin_lock_irqsave(&drv_data->lock, flags);
1202
1203 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1204 spin_unlock_irqrestore(&drv_data->lock, flags);
1205 return -EBUSY;
1206 }
1207
1208 drv_data->run = QUEUE_RUNNING;
1209 drv_data->cur_msg = NULL;
1210 drv_data->cur_transfer = NULL;
1211 drv_data->cur_chip = NULL;
1212 spin_unlock_irqrestore(&drv_data->lock, flags);
1213
1214 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1215
1216 return 0;
1217}
1218
1219static inline int stop_queue(struct driver_data *drv_data)
1220{
1221 unsigned long flags;
1222 unsigned limit = 500;
1223 int status = 0;
1224
1225 spin_lock_irqsave(&drv_data->lock, flags);
1226
1227 /*
1228 * This is a bit lame, but is optimized for the common execution path.
1229 * A wait_queue on the drv_data->busy could be used, but then the common
1230 * execution path (pump_messages) would be required to call wake_up or
1231 * friends on every SPI message. Do this instead
1232 */
1233 drv_data->run = QUEUE_STOPPED;
1234 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1235 spin_unlock_irqrestore(&drv_data->lock, flags);
1236 msleep(10);
1237 spin_lock_irqsave(&drv_data->lock, flags);
1238 }
1239
1240 if (!list_empty(&drv_data->queue) || drv_data->busy)
1241 status = -EBUSY;
1242
1243 spin_unlock_irqrestore(&drv_data->lock, flags);
1244
1245 return status;
1246}
1247
1248static inline int destroy_queue(struct driver_data *drv_data)
1249{
1250 int status;
1251
1252 status = stop_queue(drv_data);
1253 if (status != 0)
1254 return status;
1255
1256 destroy_workqueue(drv_data->workqueue);
1257
1258 return 0;
1259}
1260
1261static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1262{
1263 struct device *dev = &pdev->dev;
1264 struct bfin5xx_spi_master *platform_info;
1265 struct spi_master *master;
1266 struct driver_data *drv_data = 0;
a32c691d 1267 struct resource *res;
a5f6abd4
WB		 1268 int status = 0;
1269
1270 platform_info = dev->platform_data;
1271
1272 /* Allocate master with space for drv_data */
1273 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1274 if (!master) {
1275 dev_err(&pdev->dev, "can not alloc spi_master\n");
1276 return -ENOMEM;
1277 }
131b17d4 1278
a5f6abd4
WB		 1279 drv_data = spi_master_get_devdata(master);
1280 drv_data->master = master;
1281 drv_data->master_info = platform_info;
1282 drv_data->pdev = pdev;
003d9226 1283 drv_data->pin_req = platform_info->pin_req;
a5f6abd4
WB		 1284
1285 master->bus_num = pdev->id;
1286 master->num_chipselect = platform_info->num_chipselect;
1287 master->cleanup = cleanup;
1288 master->setup = setup;
1289 master->transfer = transfer;
1290
a32c691d
BW		 1291 /* Find and map our resources */
1292 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1293 if (res == NULL) {
1294 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1295 status = -ENOENT;
1296 goto out_error_get_res;
1297 }
1298
f452126c
BW		 1299 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1300 if (drv_data->regs_base == NULL) {
a32c691d
BW		 1301 dev_err(dev, "Cannot map IO\n");
1302 status = -ENXIO;
1303 goto out_error_ioremap;
1304 }
1305
bb90eb00
BW		 1306 drv_data->dma_channel = platform_get_irq(pdev, 0);
1307 if (drv_data->dma_channel < 0) {
a32c691d
BW		 1308 dev_err(dev, "No DMA channel specified\n");
1309 status = -ENOENT;
1310 goto out_error_no_dma_ch;
1311 }
1312
a5f6abd4
WB		 1313 /* Initial and start queue */
1314 status = init_queue(drv_data);
1315 if (status != 0) {
a32c691d 1316 dev_err(dev, "problem initializing queue\n");
a5f6abd4
WB		 1317 goto out_error_queue_alloc;
1318 }
a32c691d 1319
a5f6abd4
WB		 1320 status = start_queue(drv_data);
1321 if (status != 0) {
a32c691d 1322 dev_err(dev, "problem starting queue\n");
a5f6abd4
WB		 1323 goto out_error_queue_alloc;
1324 }
1325
f9e522ca
VM		 1326 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1327 if (status != 0) {
1328 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1329 goto out_error_queue_alloc;
1330 }
1331
a5f6abd4
WB		 1332 /* Register with the SPI framework */
1333 platform_set_drvdata(pdev, drv_data);
1334 status = spi_register_master(master);
1335 if (status != 0) {
a32c691d 1336 dev_err(dev, "problem registering spi master\n");
a5f6abd4
WB		 1337 goto out_error_queue_alloc;
1338 }
a32c691d 1339
f452126c 1340 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
bb90eb00
BW		 1341 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1342 drv_data->dma_channel);
a5f6abd4
WB		 1343 return status;
1344
cc2f81a6 1345out_error_queue_alloc:
a5f6abd4 1346 destroy_queue(drv_data);
a32c691d 1347out_error_no_dma_ch:
bb90eb00 1348 iounmap((void *) drv_data->regs_base);
a32c691d
BW		 1349out_error_ioremap:
1350out_error_get_res:
a5f6abd4 1351 spi_master_put(master);
cc2f81a6 1352
a5f6abd4
WB		 1353 return status;
1354}
1355
1356/* stop hardware and remove the driver */
1357static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1358{
1359 struct driver_data *drv_data = platform_get_drvdata(pdev);
1360 int status = 0;
1361
1362 if (!drv_data)
1363 return 0;
1364
1365 /* Remove the queue */
1366 status = destroy_queue(drv_data);
1367 if (status != 0)
1368 return status;
1369
1370 /* Disable the SSP at the peripheral and SOC level */
1371 bfin_spi_disable(drv_data);
1372
1373 /* Release DMA */
1374 if (drv_data->master_info->enable_dma) {
bb90eb00
BW		 1375 if (dma_channel_active(drv_data->dma_channel))
1376 free_dma(drv_data->dma_channel);
a5f6abd4
WB		 1377 }
1378
1379 /* Disconnect from the SPI framework */
1380 spi_unregister_master(drv_data->master);
1381
003d9226 1382 peripheral_free_list(drv_data->pin_req);
cc2f81a6 1383
a5f6abd4
WB		 1384 /* Prevent double remove */
1385 platform_set_drvdata(pdev, NULL);
1386
1387 return 0;
1388}
1389
1390#ifdef CONFIG_PM
1391static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1392{
1393 struct driver_data *drv_data = platform_get_drvdata(pdev);
1394 int status = 0;
1395
1396 status = stop_queue(drv_data);
1397 if (status != 0)
1398 return status;
1399
1400 /* stop hardware */
1401 bfin_spi_disable(drv_data);
1402
1403 return 0;
1404}
1405
1406static int bfin5xx_spi_resume(struct platform_device *pdev)
1407{
1408 struct driver_data *drv_data = platform_get_drvdata(pdev);
1409 int status = 0;
1410
1411 /* Enable the SPI interface */
1412 bfin_spi_enable(drv_data);
1413
1414 /* Start the queue running */
1415 status = start_queue(drv_data);
1416 if (status != 0) {
1417 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1418 return status;
1419 }
1420
1421 return 0;
1422}
1423#else
1424#define bfin5xx_spi_suspend NULL
1425#define bfin5xx_spi_resume NULL
1426#endif /* CONFIG_PM */
1427
7e38c3c4 1428MODULE_ALIAS("platform:bfin-spi");
a5f6abd4 1429static struct platform_driver bfin5xx_spi_driver = {
fc3ba952 1430 .driver = {
a32c691d 1431 .name = DRV_NAME,
88b40369
BW		 1432 .owner = THIS_MODULE,
1433 },
1434 .suspend = bfin5xx_spi_suspend,
1435 .resume = bfin5xx_spi_resume,
1436 .remove = __devexit_p(bfin5xx_spi_remove),
a5f6abd4
WB		 1437};
1438
1439static int __init bfin5xx_spi_init(void)
1440{
88b40369 1441 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
a5f6abd4 1442}
a5f6abd4
WB		 1443module_init(bfin5xx_spi_init);
1444
1445static void __exit bfin5xx_spi_exit(void)
1446{
1447 platform_driver_unregister(&bfin5xx_spi_driver);
1448}
a5f6abd4 1449module_exit(bfin5xx_spi_exit);
Linux 6.x block layer and io_uring tree(s)