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pinctrl: sh-pfc: r8a77965: Add PWM pins, groups and functions
[linux-2.6-block.git] / drivers / pinctrl / sh-pfc / pfc-r8a77965.c
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JM		 1// SPDX-License-Identifier: GPL-2.
2/*
3 * R8A77965 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Copyright (C) 2016 Renesas Electronics Corp.
7 *
8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15#include <linux/kernel.h>
16
17#include "core.h"
18#include "sh_pfc.h"
19
20#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
21 SH_PFC_PIN_CFG_PULL_UP | \
22 SH_PFC_PIN_CFG_PULL_DOWN)
23
24#define CPU_ALL_PORT(fn, sfx) \
25 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
29 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
34 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
37/*
38 * F_() : just information
39 * FM() : macro for FN_xxx / xxx_MARK
40 */
41
42/* GPSR0 */
43#define GPSR0_15 F_(D15, IP7_11_8)
44#define GPSR0_14 F_(D14, IP7_7_4)
45#define GPSR0_13 F_(D13, IP7_3_0)
46#define GPSR0_12 F_(D12, IP6_31_28)
47#define GPSR0_11 F_(D11, IP6_27_24)
48#define GPSR0_10 F_(D10, IP6_23_20)
49#define GPSR0_9 F_(D9, IP6_19_16)
50#define GPSR0_8 F_(D8, IP6_15_12)
51#define GPSR0_7 F_(D7, IP6_11_8)
52#define GPSR0_6 F_(D6, IP6_7_4)
53#define GPSR0_5 F_(D5, IP6_3_0)
54#define GPSR0_4 F_(D4, IP5_31_28)
55#define GPSR0_3 F_(D3, IP5_27_24)
56#define GPSR0_2 F_(D2, IP5_23_20)
57#define GPSR0_1 F_(D1, IP5_19_16)
58#define GPSR0_0 F_(D0, IP5_15_12)
59
60/* GPSR1 */
61#define GPSR1_28 FM(CLKOUT)
62#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
63#define GPSR1_26 F_(WE1_N, IP5_7_4)
64#define GPSR1_25 F_(WE0_N, IP5_3_0)
65#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
66#define GPSR1_23 F_(RD_N, IP4_27_24)
67#define GPSR1_22 F_(BS_N, IP4_23_20)
68#define GPSR1_21 F_(CS1_N, IP4_19_16)
69#define GPSR1_20 F_(CS0_N, IP4_15_12)
70#define GPSR1_19 F_(A19, IP4_11_8)
71#define GPSR1_18 F_(A18, IP4_7_4)
72#define GPSR1_17 F_(A17, IP4_3_0)
73#define GPSR1_16 F_(A16, IP3_31_28)
74#define GPSR1_15 F_(A15, IP3_27_24)
75#define GPSR1_14 F_(A14, IP3_23_20)
76#define GPSR1_13 F_(A13, IP3_19_16)
77#define GPSR1_12 F_(A12, IP3_15_12)
78#define GPSR1_11 F_(A11, IP3_11_8)
79#define GPSR1_10 F_(A10, IP3_7_4)
80#define GPSR1_9 F_(A9, IP3_3_0)
81#define GPSR1_8 F_(A8, IP2_31_28)
82#define GPSR1_7 F_(A7, IP2_27_24)
83#define GPSR1_6 F_(A6, IP2_23_20)
84#define GPSR1_5 F_(A5, IP2_19_16)
85#define GPSR1_4 F_(A4, IP2_15_12)
86#define GPSR1_3 F_(A3, IP2_11_8)
87#define GPSR1_2 F_(A2, IP2_7_4)
88#define GPSR1_1 F_(A1, IP2_3_0)
89#define GPSR1_0 F_(A0, IP1_31_28)
90
91/* GPSR2 */
92#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
93#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
94#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
95#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
96#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
97#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
98#define GPSR2_8 F_(PWM2_A, IP1_27_24)
99#define GPSR2_7 F_(PWM1_A, IP1_23_20)
100#define GPSR2_6 F_(PWM0, IP1_19_16)
101#define GPSR2_5 F_(IRQ5, IP1_15_12)
102#define GPSR2_4 F_(IRQ4, IP1_11_8)
103#define GPSR2_3 F_(IRQ3, IP1_7_4)
104#define GPSR2_2 F_(IRQ2, IP1_3_0)
105#define GPSR2_1 F_(IRQ1, IP0_31_28)
106#define GPSR2_0 F_(IRQ0, IP0_27_24)
107
108/* GPSR3 */
109#define GPSR3_15 F_(SD1_WP, IP11_23_20)
110#define GPSR3_14 F_(SD1_CD, IP11_19_16)
111#define GPSR3_13 F_(SD0_WP, IP11_15_12)
112#define GPSR3_12 F_(SD0_CD, IP11_11_8)
113#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
114#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
115#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
116#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
117#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
118#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
119#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
120#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
121#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
122#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
123#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
124#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
125
126/* GPSR4 */
127#define GPSR4_17 F_(SD3_DS, IP11_7_4)
128#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
129#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
130#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
131#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
132#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
133#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
134#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
135#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
136#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
137#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
138#define GPSR4_6 F_(SD2_DS, IP9_27_24)
139#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
140#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
141#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
142#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
143#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
144#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
145
146/* GPSR5 */
147#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
148#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
149#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
150#define GPSR5_22 FM(MSIOF0_RXD)
151#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
152#define GPSR5_20 FM(MSIOF0_TXD)
153#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
154#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
155#define GPSR5_17 FM(MSIOF0_SCK)
156#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
157#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
158#define GPSR5_14 F_(HTX0, IP13_19_16)
159#define GPSR5_13 F_(HRX0, IP13_15_12)
160#define GPSR5_12 F_(HSCK0, IP13_11_8)
161#define GPSR5_11 F_(RX2_A, IP13_7_4)
162#define GPSR5_10 F_(TX2_A, IP13_3_0)
163#define GPSR5_9 F_(SCK2, IP12_31_28)
164#define GPSR5_8 F_(RTS1_N, IP12_27_24)
165#define GPSR5_7 F_(CTS1_N, IP12_23_20)
166#define GPSR5_6 F_(TX1_A, IP12_19_16)
167#define GPSR5_5 F_(RX1_A, IP12_15_12)
168#define GPSR5_4 F_(RTS0_N, IP12_11_8)
169#define GPSR5_3 F_(CTS0_N, IP12_7_4)
170#define GPSR5_2 F_(TX0, IP12_3_0)
171#define GPSR5_1 F_(RX0, IP11_31_28)
172#define GPSR5_0 F_(SCK0, IP11_27_24)
173
174/* GPSR6 */
175#define GPSR6_31 F_(GP6_31, IP18_7_4)
176#define GPSR6_30 F_(GP6_30, IP18_3_0)
177#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
178#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
179#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
180#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
181#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
182#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
183#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
184#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
185#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
186#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
187#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
188#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
189#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
190#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
191#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
192#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
193#define GPSR6_13 FM(SSI_SDATA5)
194#define GPSR6_12 FM(SSI_WS5)
195#define GPSR6_11 FM(SSI_SCK5)
196#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
197#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
198#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
199#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
200#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
201#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
202#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
203#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
204#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
205#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
206#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
207
208/* GPSR7 */
209#define GPSR7_3 FM(GP7_03)
210#define GPSR7_2 FM(HDMI0_CEC)
211#define GPSR7_1 FM(AVS2)
212#define GPSR7_0 FM(AVS1)
213
214
215/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
216#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243
244/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
245#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310
311/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
312#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
333#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340
341/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
342#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
362#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
363#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
364#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
365#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
366#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
368#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
369
370#define PINMUX_GPSR \
371\
372 GPSR6_31 \
373 GPSR6_30 \
374 GPSR6_29 \
375 GPSR1_28 GPSR6_28 \
376 GPSR1_27 GPSR6_27 \
377 GPSR1_26 GPSR6_26 \
378 GPSR1_25 GPSR5_25 GPSR6_25 \
379 GPSR1_24 GPSR5_24 GPSR6_24 \
380 GPSR1_23 GPSR5_23 GPSR6_23 \
381 GPSR1_22 GPSR5_22 GPSR6_22 \
382 GPSR1_21 GPSR5_21 GPSR6_21 \
383 GPSR1_20 GPSR5_20 GPSR6_20 \
384 GPSR1_19 GPSR5_19 GPSR6_19 \
385 GPSR1_18 GPSR5_18 GPSR6_18 \
386 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
387 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
388GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
389GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
390GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
391GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
392GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
393GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
394GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
395GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
396GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
397GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
398GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
399GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
400GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
401GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
402GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
403GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
404
405#define PINMUX_IPSR \
406\
407FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
408FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
409FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
410FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
411FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
412FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
413FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
414FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
415\
416FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
417FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
418FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
419FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
420FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
421FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
422FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
423FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
424\
425FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
426FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
427FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
428FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
429FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
430FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
431FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
432FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
433\
434FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
435FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
436FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
437FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
438FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
439FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
440FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
441FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
442\
443FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
444FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
445FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
446FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
447FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
448FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
449FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
450FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
451
452/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
453#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
454#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
455#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
456#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
457#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
458#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
459#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
460#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
461#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
462#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
463#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
464#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
465#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
466#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
467#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
468#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
469#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
470#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
471
472/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
473#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
474#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
476#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
477#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
478#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
479#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
480#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
481#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
482#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
483#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
484#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
485#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
486#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
487#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
488#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
489#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
490#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
491#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
492#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
493#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
494#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
495
496/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
497#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
498#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
499#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
500#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
501#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
502#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
503#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
504#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
505#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
506#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
507#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
508#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
509#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
510
511#define PINMUX_MOD_SELS \
512\
513MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
514 MOD_SEL2_30 \
515 MOD_SEL1_29_28_27 MOD_SEL2_29 \
516MOD_SEL0_28_27 MOD_SEL2_28_27 \
517MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
518 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
519MOD_SEL0_23 MOD_SEL1_23_22_21 \
520MOD_SEL0_22 MOD_SEL2_22 \
521MOD_SEL0_21 MOD_SEL2_21 \
522MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
523MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
524MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
525 MOD_SEL2_17 \
526MOD_SEL0_16 MOD_SEL1_16 \
527 MOD_SEL1_15_14 \
528MOD_SEL0_14_13 \
529 MOD_SEL1_13 \
530MOD_SEL0_12 MOD_SEL1_12 \
531MOD_SEL0_11 MOD_SEL1_11 \
532MOD_SEL0_10 MOD_SEL1_10 \
533MOD_SEL0_9_8 MOD_SEL1_9 \
534MOD_SEL0_7_6 \
535 MOD_SEL1_6 \
536MOD_SEL0_5 MOD_SEL1_5 \
537MOD_SEL0_4_3 MOD_SEL1_4 \
538 MOD_SEL1_3 \
539 MOD_SEL1_2 \
540 MOD_SEL1_1 \
541 MOD_SEL1_0 MOD_SEL2_0
542
543/*
544 * These pins are not able to be muxed but have other properties
545 * that can be set, such as drive-strength or pull-up/pull-down enable.
546 */
547#define PINMUX_STATIC \
548 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
549 FM(QSPI0_IO2) FM(QSPI0_IO3) \
550 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
551 FM(QSPI1_IO2) FM(QSPI1_IO3) \
552 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
553 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
554 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
555 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
556 FM(PRESETOUT) \
557 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
558 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
559
560enum {
561 PINMUX_RESERVED = 0,
562
563 PINMUX_DATA_BEGIN,
564 GP_ALL(DATA),
565 PINMUX_DATA_END,
566
567#define F_(x, y)
568#define FM(x) FN_##x,
569 PINMUX_FUNCTION_BEGIN,
570 GP_ALL(FN),
571 PINMUX_GPSR
572 PINMUX_IPSR
573 PINMUX_MOD_SELS
574 PINMUX_FUNCTION_END,
575#undef F_
576#undef FM
577
578#define F_(x, y)
579#define FM(x) x##_MARK,
580 PINMUX_MARK_BEGIN,
581 PINMUX_GPSR
582 PINMUX_IPSR
583 PINMUX_MOD_SELS
584 PINMUX_STATIC
585 PINMUX_MARK_END,
586#undef F_
587#undef FM
588};
589
590static const u16 pinmux_data[] = {
591 PINMUX_DATA_GP_ALL(),
592
593 PINMUX_SINGLE(AVS1),
594 PINMUX_SINGLE(AVS2),
595 PINMUX_SINGLE(CLKOUT),
596 PINMUX_SINGLE(GP7_03),
597 PINMUX_SINGLE(HDMI0_CEC),
598 PINMUX_SINGLE(MSIOF0_RXD),
599 PINMUX_SINGLE(MSIOF0_SCK),
600 PINMUX_SINGLE(MSIOF0_TXD),
601 PINMUX_SINGLE(SSI_SCK5),
602 PINMUX_SINGLE(SSI_SDATA5),
603 PINMUX_SINGLE(SSI_WS5),
604
605 /* IPSR0 */
606 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
607 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
608
609 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
610 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
611 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
612
613 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
614 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
615 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
616
617 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
618 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
619 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
620 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
621
622 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
623 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
624 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
625
626 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
627 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
628 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
629
630 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
631 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
632 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
633 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
635 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
636 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
637
638 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
639 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
640 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
641 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
644 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
645
646 /* IPSR1 */
647 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
648 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
649 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
650 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
651 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
652 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
653
654 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
655 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
656 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
657 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
658 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
659 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
660
661 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
662 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
663 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
664 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
665 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
666 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
667
668 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
669 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
670 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
671 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
672 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
673 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
674 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
675
676 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
677 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
678 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
679 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
680
681 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
682 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
683 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
685
686 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
687 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
688 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
689
690 PINMUX_IPSR_GPSR(IP1_31_28, A0),
691 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
692 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
693 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
694 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
695 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
696
697 /* IPSR2 */
698 PINMUX_IPSR_GPSR(IP2_3_0, A1),
699 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
700 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
701 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
702 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
703 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
704
705 PINMUX_IPSR_GPSR(IP2_7_4, A2),
706 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
707 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
708 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
709 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
710 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
711
712 PINMUX_IPSR_GPSR(IP2_11_8, A3),
713 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
714 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
715 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
716 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
717 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
718
719 PINMUX_IPSR_GPSR(IP2_15_12, A4),
720 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
721 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
722 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
723 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
724 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
725
726 PINMUX_IPSR_GPSR(IP2_19_16, A5),
727 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
728 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
729 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
730 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
731 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
732 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
733
734 PINMUX_IPSR_GPSR(IP2_23_20, A6),
735 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
736 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
737 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
738 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
739 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
740 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
741
742 PINMUX_IPSR_GPSR(IP2_27_24, A7),
743 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
744 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
745 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
746 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
747 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
748 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
749
750 PINMUX_IPSR_GPSR(IP2_31_28, A8),
751 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
752 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
753 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
754 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
755 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
756 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
757
758 /* IPSR3 */
759 PINMUX_IPSR_GPSR(IP3_3_0, A9),
760 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
761 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
762 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
763
764 PINMUX_IPSR_GPSR(IP3_7_4, A10),
765 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
766 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
767 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
768
769 PINMUX_IPSR_GPSR(IP3_11_8, A11),
770 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
771 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
772 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
773 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
774 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
775 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
776 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
777 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
778
779 PINMUX_IPSR_GPSR(IP3_15_12, A12),
780 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
781 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
782 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
783 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
784 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
785
786 PINMUX_IPSR_GPSR(IP3_19_16, A13),
787 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
788 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
789 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
790 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
791 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
792
793 PINMUX_IPSR_GPSR(IP3_23_20, A14),
794 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
795 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
796 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
797 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
798 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
799
800 PINMUX_IPSR_GPSR(IP3_27_24, A15),
801 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
802 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
803 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
804 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
805 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
806
807 PINMUX_IPSR_GPSR(IP3_31_28, A16),
808 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
809 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
810 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
811
812 /* IPSR4 */
813 PINMUX_IPSR_GPSR(IP4_3_0, A17),
814 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
815 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
816 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
817
818 PINMUX_IPSR_GPSR(IP4_7_4, A18),
819 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
820 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
821 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
822
823 PINMUX_IPSR_GPSR(IP4_11_8, A19),
824 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
825 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
826 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
827
828 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
829 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
830
831 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
832 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
833 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
834
835 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
836 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
837 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
838 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
839 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
840 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
841 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
842 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
843
844 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
845 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
846 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
847 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
848 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
849 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
850
851 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
852 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
853 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
854 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
855 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
856 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
857
858 /* IPSR5 */
859 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
860 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
861 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
862 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
863 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
864 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
865 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
866
867 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
868 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
869 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
870 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
871 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
872 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
873 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
874 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
875
876 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
877 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
878 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
879 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
880
881 PINMUX_IPSR_GPSR(IP5_15_12, D0),
882 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
883 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
884 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
885 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
886
887 PINMUX_IPSR_GPSR(IP5_19_16, D1),
888 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
889 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
890 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
891 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
892
893 PINMUX_IPSR_GPSR(IP5_23_20, D2),
894 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
895 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
896 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
897
898 PINMUX_IPSR_GPSR(IP5_27_24, D3),
899 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
900 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
901 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
902
903 PINMUX_IPSR_GPSR(IP5_31_28, D4),
904 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
905 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
906 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
907
908 /* IPSR6 */
909 PINMUX_IPSR_GPSR(IP6_3_0, D5),
910 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
911 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
912 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
913
914 PINMUX_IPSR_GPSR(IP6_7_4, D6),
915 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
916 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
917 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
918
919 PINMUX_IPSR_GPSR(IP6_11_8, D7),
920 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
921 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
922 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
923
924 PINMUX_IPSR_GPSR(IP6_15_12, D8),
925 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
926 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
927 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
928 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
929 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
930
931 PINMUX_IPSR_GPSR(IP6_19_16, D9),
932 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
933 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
934 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
935 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
936
937 PINMUX_IPSR_GPSR(IP6_23_20, D10),
938 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
939 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
940 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
941 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
942 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
943 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
944
945 PINMUX_IPSR_GPSR(IP6_27_24, D11),
946 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
947 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
948 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
949 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
950 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
951 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
952
953 PINMUX_IPSR_GPSR(IP6_31_28, D12),
954 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
955 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
956 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
957 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
958 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
959
960 /* IPSR7 */
961 PINMUX_IPSR_GPSR(IP7_3_0, D13),
962 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
963 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
964 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
965 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
966 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
967
968 PINMUX_IPSR_GPSR(IP7_7_4, D14),
969 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
970 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
971 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
972 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
973 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
974 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
975
976 PINMUX_IPSR_GPSR(IP7_11_8, D15),
977 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
978 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
979 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
980 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
981 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
982 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
983
984 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
985 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
986 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
987
988 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
989 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
990 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
991
992 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
993 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
994 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
995 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
996
997 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
998 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
999 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1000 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1001
1002 /* IPSR8 */
1003 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1004 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1005 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1006 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1007
1008 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1009 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1010 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1011 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1012
1013 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1014 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1015 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1016
1017 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1018 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1019 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
1020 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1021 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1022
1023 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1024 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1025 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1026 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
1027 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1028 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1029
1030 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1031 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1032 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1033 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
1034 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1035 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1036
1037 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1038 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1039 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1040 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
1041 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1042 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1043
1044 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1045 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1046 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1047 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
1048 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1049 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1050
1051 /* IPSR9 */
1052 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1053 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1054
1055 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1056 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1057
1058 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1059 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1060
1061 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1062 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1063
1064 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1065 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1066
1067 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1068 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1069
1070 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1071 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1072 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1073
1074 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1075 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1076
1077 /* IPSR10 */
1078 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1079 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1080
1081 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1082 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1083
1084 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1085 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1086
1087 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1088 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1089
1090 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1091 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1092
1093 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1094 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1095 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1096
1097 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1098 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1099 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1100
1101 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1102 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1103 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1104
1105 /* IPSR11 */
1106 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1107 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1108 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1109
1110 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1111 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1112
1113 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1114 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
1115 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1116 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1117
1118 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1119 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
1120 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1121
1122 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1123 PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
1124 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1125
1126 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1127 PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
1128 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1129
1130 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1131 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1135 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1136 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1137 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1138 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1139 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1140
1141 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1142 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1143 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1144 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1145 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1146
1147 /* IPSR12 */
1148 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1149 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1150 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1151 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1152 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1153
1154 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1155 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1156 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1157 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1158 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1159 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1160 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1161 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1162
1163 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1164 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1167 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1168 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1169 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1170 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1171
1172 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1174 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1175 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1176 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1177
1178 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1179 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1180 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1181 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1182 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1183
1184 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1185 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1186 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1187 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1188 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1189 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1190 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1191
1192 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1193 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1194 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1195 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1196 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1197 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1198 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1199
1200 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1201 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1202 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1203 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1205 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1206 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1207
1208 /* IPSR13 */
1209 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1210 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1211 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1212 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1213 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1214 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1215
1216 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1217 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1218 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1219 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1220 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1221 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1222
1223 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1224 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1225 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1226 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1227 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1229 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1230 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1231
1232 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1233 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1234 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1235 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1236 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1237 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1238
1239 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1240 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1241 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1242 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1243 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1244 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1245
1246 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1247 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1248 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1249 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1250 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1251 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1252 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1253 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1254
1255 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1256 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1257 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1258 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1259 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1260 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1261 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1262
1263 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1264 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1265 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1266 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1267
1268 /* IPSR14 */
1269 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1270 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1271 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
1272 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1273 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1274 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1275 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1276 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1277
1278 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1279 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1280 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1281 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1282 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1283 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1284 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1285 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1286
1287 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1288 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1289 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1290
1291 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1292 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1293 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1294 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1295
1296 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1297 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1298 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1299
1300 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1301 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1302
1303 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1304 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1305
1306 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1307 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1308
1309 /* IPSR15 */
1310 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1311
1312 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1313 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1314
1315 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1316 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1317 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1318
1319 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1320 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1321 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1322 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1323
1324 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1325 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1331
1332 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1333 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1339
1340 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1341 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1347
1348 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1349 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1355
1356 /* IPSR16 */
1357 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1358 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1359
1360 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1361 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1362
1363 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1364 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1365 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1366
1367 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1368 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1369 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1370 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1371 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1372 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1373 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1374
1375 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1376 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1377 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1378 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1379 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1380 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1382
1383 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1384 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1385 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1386 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1387 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1388 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1391
1392 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1393 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1394 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1395 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1396 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1397 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1398 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1399
1400 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1401 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1402 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1403 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1404 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1405 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1406 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1407 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1408
1409 /* IPSR17 */
1410 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1411 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1412
1413 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1414 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1415 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1416 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1417 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1418
1419 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1420 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1421 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1422 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1423 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1424 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1425 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1426
1427 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1428 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1429 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1430 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1431 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1432 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1433
1434 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1435 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1436 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1437 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1438 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1439 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1440 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1441 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1442 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1443
1444 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1445 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1446 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1447 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1448 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1449 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1450 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1451 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1453
1454 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1455 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1456 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1457 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1458 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1460 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1461 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1462 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1463 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1464 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1465
1466 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1467 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1468 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1469 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1470 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1472 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1473 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1474 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1475
1476 /* IPSR18 */
1477 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1478 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1479 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1480 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1481 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1482 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1483 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1484 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1486
1487 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1488 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1489 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1490 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1491 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1492 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1493 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1494 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1496
1497 /* I2C */
1498 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1499 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1500 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1501
1502/*
1503 * Static pins can not be muxed between different functions but
1504 * still needs a mark entry in the pinmux list. Add each static
1505 * pin to the list without an associated function. The sh-pfc
1506 * core will do the right thing and skip trying to mux then pin
1507 * while still applying configuration to it
1508 */
1509#define FM(x) PINMUX_DATA(x##_MARK, 0),
1510 PINMUX_STATIC
1511#undef FM
1512};
1513
1514/*
1515 * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1516 * Physical layout rows: A - AW, cols: 1 - 39.
1517 */
1518#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521#define PIN_NONE U16_MAX
1522
1523static const struct sh_pfc_pin pinmux_pins[] = {
1524 PINMUX_GPIO_GP_ALL(),
1525
1526 /*
1527 * Pins not associated with a GPIO port.
1528 *
1529 * The pin positions are different between different r8a77965
1530 * packages, all that is needed for the pfc driver is a unique
1531 * number for each pin. To this end use the pin layout from
1532 * R-Car M3SiP to calculate a unique number for each pin.
1533 */
1534 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1576};
1577
fa3e8b71
JM		 1578/* - EtherAVB --------------------------------------------------------------- */
1579static const unsigned int avb_link_pins[] = {
1580 /* AVB_LINK */
1581 RCAR_GP_PIN(2, 12),
1582};
1583static const unsigned int avb_link_mux[] = {
1584 AVB_LINK_MARK,
1585};
1586static const unsigned int avb_magic_pins[] = {
1587 /* AVB_MAGIC_ */
1588 RCAR_GP_PIN(2, 10),
1589};
1590static const unsigned int avb_magic_mux[] = {
1591 AVB_MAGIC_MARK,
1592};
1593static const unsigned int avb_phy_int_pins[] = {
1594 /* AVB_PHY_INT */
1595 RCAR_GP_PIN(2, 11),
1596};
1597static const unsigned int avb_phy_int_mux[] = {
1598 AVB_PHY_INT_MARK,
1599};
f7ce295c 1600static const unsigned int avb_mdio_pins[] = {
fa3e8b71
JM		 1601 /* AVB_MDC, AVB_MDIO */
1602 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1603};
f7ce295c 1604static const unsigned int avb_mdio_mux[] = {
fa3e8b71
JM		 1605 AVB_MDC_MARK, AVB_MDIO_MARK,
1606};
1607static const unsigned int avb_mii_pins[] = {
1608 /*
1609 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1610 * AVB_TD1, AVB_TD2, AVB_TD3,
1611 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1612 * AVB_RD1, AVB_RD2, AVB_RD3,
1613 * AVB_TXCREFCLK
1614 */
1615 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1616 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1617 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1618 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1619 PIN_NUMBER('A', 12),
1620
1621};
1622static const unsigned int avb_mii_mux[] = {
1623 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1624 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1625 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1626 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1627 AVB_TXCREFCLK_MARK,
1628};
1629static const unsigned int avb_avtp_pps_pins[] = {
1630 /* AVB_AVTP_PPS */
1631 RCAR_GP_PIN(2, 6),
1632};
1633static const unsigned int avb_avtp_pps_mux[] = {
1634 AVB_AVTP_PPS_MARK,
1635};
1636static const unsigned int avb_avtp_match_a_pins[] = {
1637 /* AVB_AVTP_MATCH_A */
1638 RCAR_GP_PIN(2, 13),
1639};
1640static const unsigned int avb_avtp_match_a_mux[] = {
1641 AVB_AVTP_MATCH_A_MARK,
1642};
1643static const unsigned int avb_avtp_capture_a_pins[] = {
1644 /* AVB_AVTP_CAPTURE_A */
1645 RCAR_GP_PIN(2, 14),
1646};
1647static const unsigned int avb_avtp_capture_a_mux[] = {
1648 AVB_AVTP_CAPTURE_A_MARK,
1649};
1650static const unsigned int avb_avtp_match_b_pins[] = {
1651 /* AVB_AVTP_MATCH_B */
1652 RCAR_GP_PIN(1, 8),
1653};
1654static const unsigned int avb_avtp_match_b_mux[] = {
1655 AVB_AVTP_MATCH_B_MARK,
1656};
1657static const unsigned int avb_avtp_capture_b_pins[] = {
1658 /* AVB_AVTP_CAPTURE_B */
1659 RCAR_GP_PIN(1, 11),
1660};
1661static const unsigned int avb_avtp_capture_b_mux[] = {
1662 AVB_AVTP_CAPTURE_B_MARK,
1663};
a8ab4f2b
TK		 1664
1665/* - INTC-EX ---------------------------------------------------------------- */
1666static const unsigned int intc_ex_irq0_pins[] = {
1667 /* IRQ0 */
1668 RCAR_GP_PIN(2, 0),
1669};
1670static const unsigned int intc_ex_irq0_mux[] = {
1671 IRQ0_MARK,
1672};
1673static const unsigned int intc_ex_irq1_pins[] = {
1674 /* IRQ1 */
1675 RCAR_GP_PIN(2, 1),
1676};
1677static const unsigned int intc_ex_irq1_mux[] = {
1678 IRQ1_MARK,
1679};
1680static const unsigned int intc_ex_irq2_pins[] = {
1681 /* IRQ2 */
1682 RCAR_GP_PIN(2, 2),
1683};
1684static const unsigned int intc_ex_irq2_mux[] = {
1685 IRQ2_MARK,
1686};
1687static const unsigned int intc_ex_irq3_pins[] = {
1688 /* IRQ3 */
1689 RCAR_GP_PIN(2, 3),
1690};
1691static const unsigned int intc_ex_irq3_mux[] = {
1692 IRQ3_MARK,
1693};
1694static const unsigned int intc_ex_irq4_pins[] = {
1695 /* IRQ4 */
1696 RCAR_GP_PIN(2, 4),
1697};
1698static const unsigned int intc_ex_irq4_mux[] = {
1699 IRQ4_MARK,
1700};
1701static const unsigned int intc_ex_irq5_pins[] = {
1702 /* IRQ5 */
1703 RCAR_GP_PIN(2, 5),
1704};
1705static const unsigned int intc_ex_irq5_mux[] = {
1706 IRQ5_MARK,
1707};
1708
2c77aa3d
TK		 1709/* - MSIOF0 ----------------------------------------------------------------- */
1710static const unsigned int msiof0_clk_pins[] = {
1711 /* SCK */
1712 RCAR_GP_PIN(5, 17),
1713};
1714static const unsigned int msiof0_clk_mux[] = {
1715 MSIOF0_SCK_MARK,
1716};
1717static const unsigned int msiof0_sync_pins[] = {
1718 /* SYNC */
1719 RCAR_GP_PIN(5, 18),
1720};
1721static const unsigned int msiof0_sync_mux[] = {
1722 MSIOF0_SYNC_MARK,
1723};
1724static const unsigned int msiof0_ss1_pins[] = {
1725 /* SS1 */
1726 RCAR_GP_PIN(5, 19),
1727};
1728static const unsigned int msiof0_ss1_mux[] = {
1729 MSIOF0_SS1_MARK,
1730};
1731static const unsigned int msiof0_ss2_pins[] = {
1732 /* SS2 */
1733 RCAR_GP_PIN(5, 21),
1734};
1735static const unsigned int msiof0_ss2_mux[] = {
1736 MSIOF0_SS2_MARK,
1737};
1738static const unsigned int msiof0_txd_pins[] = {
1739 /* TXD */
1740 RCAR_GP_PIN(5, 20),
1741};
1742static const unsigned int msiof0_txd_mux[] = {
1743 MSIOF0_TXD_MARK,
1744};
1745static const unsigned int msiof0_rxd_pins[] = {
1746 /* RXD */
1747 RCAR_GP_PIN(5, 22),
1748};
1749static const unsigned int msiof0_rxd_mux[] = {
1750 MSIOF0_RXD_MARK,
1751};
1752/* - MSIOF1 ----------------------------------------------------------------- */
1753static const unsigned int msiof1_clk_a_pins[] = {
1754 /* SCK */
1755 RCAR_GP_PIN(6, 8),
1756};
1757static const unsigned int msiof1_clk_a_mux[] = {
1758 MSIOF1_SCK_A_MARK,
1759};
1760static const unsigned int msiof1_sync_a_pins[] = {
1761 /* SYNC */
1762 RCAR_GP_PIN(6, 9),
1763};
1764static const unsigned int msiof1_sync_a_mux[] = {
1765 MSIOF1_SYNC_A_MARK,
1766};
1767static const unsigned int msiof1_ss1_a_pins[] = {
1768 /* SS1 */
1769 RCAR_GP_PIN(6, 5),
1770};
1771static const unsigned int msiof1_ss1_a_mux[] = {
1772 MSIOF1_SS1_A_MARK,
1773};
1774static const unsigned int msiof1_ss2_a_pins[] = {
1775 /* SS2 */
1776 RCAR_GP_PIN(6, 6),
1777};
1778static const unsigned int msiof1_ss2_a_mux[] = {
1779 MSIOF1_SS2_A_MARK,
1780};
1781static const unsigned int msiof1_txd_a_pins[] = {
1782 /* TXD */
1783 RCAR_GP_PIN(6, 7),
1784};
1785static const unsigned int msiof1_txd_a_mux[] = {
1786 MSIOF1_TXD_A_MARK,
1787};
1788static const unsigned int msiof1_rxd_a_pins[] = {
1789 /* RXD */
1790 RCAR_GP_PIN(6, 10),
1791};
1792static const unsigned int msiof1_rxd_a_mux[] = {
1793 MSIOF1_RXD_A_MARK,
1794};
1795static const unsigned int msiof1_clk_b_pins[] = {
1796 /* SCK */
1797 RCAR_GP_PIN(5, 9),
1798};
1799static const unsigned int msiof1_clk_b_mux[] = {
1800 MSIOF1_SCK_B_MARK,
1801};
1802static const unsigned int msiof1_sync_b_pins[] = {
1803 /* SYNC */
1804 RCAR_GP_PIN(5, 3),
1805};
1806static const unsigned int msiof1_sync_b_mux[] = {
1807 MSIOF1_SYNC_B_MARK,
1808};
1809static const unsigned int msiof1_ss1_b_pins[] = {
1810 /* SS1 */
1811 RCAR_GP_PIN(5, 4),
1812};
1813static const unsigned int msiof1_ss1_b_mux[] = {
1814 MSIOF1_SS1_B_MARK,
1815};
1816static const unsigned int msiof1_ss2_b_pins[] = {
1817 /* SS2 */
1818 RCAR_GP_PIN(5, 0),
1819};
1820static const unsigned int msiof1_ss2_b_mux[] = {
1821 MSIOF1_SS2_B_MARK,
1822};
1823static const unsigned int msiof1_txd_b_pins[] = {
1824 /* TXD */
1825 RCAR_GP_PIN(5, 8),
1826};
1827static const unsigned int msiof1_txd_b_mux[] = {
1828 MSIOF1_TXD_B_MARK,
1829};
1830static const unsigned int msiof1_rxd_b_pins[] = {
1831 /* RXD */
1832 RCAR_GP_PIN(5, 7),
1833};
1834static const unsigned int msiof1_rxd_b_mux[] = {
1835 MSIOF1_RXD_B_MARK,
1836};
1837static const unsigned int msiof1_clk_c_pins[] = {
1838 /* SCK */
1839 RCAR_GP_PIN(6, 17),
1840};
1841static const unsigned int msiof1_clk_c_mux[] = {
1842 MSIOF1_SCK_C_MARK,
1843};
1844static const unsigned int msiof1_sync_c_pins[] = {
1845 /* SYNC */
1846 RCAR_GP_PIN(6, 18),
1847};
1848static const unsigned int msiof1_sync_c_mux[] = {
1849 MSIOF1_SYNC_C_MARK,
1850};
1851static const unsigned int msiof1_ss1_c_pins[] = {
1852 /* SS1 */
1853 RCAR_GP_PIN(6, 21),
1854};
1855static const unsigned int msiof1_ss1_c_mux[] = {
1856 MSIOF1_SS1_C_MARK,
1857};
1858static const unsigned int msiof1_ss2_c_pins[] = {
1859 /* SS2 */
1860 RCAR_GP_PIN(6, 27),
1861};
1862static const unsigned int msiof1_ss2_c_mux[] = {
1863 MSIOF1_SS2_C_MARK,
1864};
1865static const unsigned int msiof1_txd_c_pins[] = {
1866 /* TXD */
1867 RCAR_GP_PIN(6, 20),
1868};
1869static const unsigned int msiof1_txd_c_mux[] = {
1870 MSIOF1_TXD_C_MARK,
1871};
1872static const unsigned int msiof1_rxd_c_pins[] = {
1873 /* RXD */
1874 RCAR_GP_PIN(6, 19),
1875};
1876static const unsigned int msiof1_rxd_c_mux[] = {
1877 MSIOF1_RXD_C_MARK,
1878};
1879static const unsigned int msiof1_clk_d_pins[] = {
1880 /* SCK */
1881 RCAR_GP_PIN(5, 12),
1882};
1883static const unsigned int msiof1_clk_d_mux[] = {
1884 MSIOF1_SCK_D_MARK,
1885};
1886static const unsigned int msiof1_sync_d_pins[] = {
1887 /* SYNC */
1888 RCAR_GP_PIN(5, 15),
1889};
1890static const unsigned int msiof1_sync_d_mux[] = {
1891 MSIOF1_SYNC_D_MARK,
1892};
1893static const unsigned int msiof1_ss1_d_pins[] = {
1894 /* SS1 */
1895 RCAR_GP_PIN(5, 16),
1896};
1897static const unsigned int msiof1_ss1_d_mux[] = {
1898 MSIOF1_SS1_D_MARK,
1899};
1900static const unsigned int msiof1_ss2_d_pins[] = {
1901 /* SS2 */
1902 RCAR_GP_PIN(5, 21),
1903};
1904static const unsigned int msiof1_ss2_d_mux[] = {
1905 MSIOF1_SS2_D_MARK,
1906};
1907static const unsigned int msiof1_txd_d_pins[] = {
1908 /* TXD */
1909 RCAR_GP_PIN(5, 14),
1910};
1911static const unsigned int msiof1_txd_d_mux[] = {
1912 MSIOF1_TXD_D_MARK,
1913};
1914static const unsigned int msiof1_rxd_d_pins[] = {
1915 /* RXD */
1916 RCAR_GP_PIN(5, 13),
1917};
1918static const unsigned int msiof1_rxd_d_mux[] = {
1919 MSIOF1_RXD_D_MARK,
1920};
1921static const unsigned int msiof1_clk_e_pins[] = {
1922 /* SCK */
1923 RCAR_GP_PIN(3, 0),
1924};
1925static const unsigned int msiof1_clk_e_mux[] = {
1926 MSIOF1_SCK_E_MARK,
1927};
1928static const unsigned int msiof1_sync_e_pins[] = {
1929 /* SYNC */
1930 RCAR_GP_PIN(3, 1),
1931};
1932static const unsigned int msiof1_sync_e_mux[] = {
1933 MSIOF1_SYNC_E_MARK,
1934};
1935static const unsigned int msiof1_ss1_e_pins[] = {
1936 /* SS1 */
1937 RCAR_GP_PIN(3, 4),
1938};
1939static const unsigned int msiof1_ss1_e_mux[] = {
1940 MSIOF1_SS1_E_MARK,
1941};
1942static const unsigned int msiof1_ss2_e_pins[] = {
1943 /* SS2 */
1944 RCAR_GP_PIN(3, 5),
1945};
1946static const unsigned int msiof1_ss2_e_mux[] = {
1947 MSIOF1_SS2_E_MARK,
1948};
1949static const unsigned int msiof1_txd_e_pins[] = {
1950 /* TXD */
1951 RCAR_GP_PIN(3, 3),
1952};
1953static const unsigned int msiof1_txd_e_mux[] = {
1954 MSIOF1_TXD_E_MARK,
1955};
1956static const unsigned int msiof1_rxd_e_pins[] = {
1957 /* RXD */
1958 RCAR_GP_PIN(3, 2),
1959};
1960static const unsigned int msiof1_rxd_e_mux[] = {
1961 MSIOF1_RXD_E_MARK,
1962};
1963static const unsigned int msiof1_clk_f_pins[] = {
1964 /* SCK */
1965 RCAR_GP_PIN(5, 23),
1966};
1967static const unsigned int msiof1_clk_f_mux[] = {
1968 MSIOF1_SCK_F_MARK,
1969};
1970static const unsigned int msiof1_sync_f_pins[] = {
1971 /* SYNC */
1972 RCAR_GP_PIN(5, 24),
1973};
1974static const unsigned int msiof1_sync_f_mux[] = {
1975 MSIOF1_SYNC_F_MARK,
1976};
1977static const unsigned int msiof1_ss1_f_pins[] = {
1978 /* SS1 */
1979 RCAR_GP_PIN(6, 1),
1980};
1981static const unsigned int msiof1_ss1_f_mux[] = {
1982 MSIOF1_SS1_F_MARK,
1983};
1984static const unsigned int msiof1_ss2_f_pins[] = {
1985 /* SS2 */
1986 RCAR_GP_PIN(6, 2),
1987};
1988static const unsigned int msiof1_ss2_f_mux[] = {
1989 MSIOF1_SS2_F_MARK,
1990};
1991static const unsigned int msiof1_txd_f_pins[] = {
1992 /* TXD */
1993 RCAR_GP_PIN(6, 0),
1994};
1995static const unsigned int msiof1_txd_f_mux[] = {
1996 MSIOF1_TXD_F_MARK,
1997};
1998static const unsigned int msiof1_rxd_f_pins[] = {
1999 /* RXD */
2000 RCAR_GP_PIN(5, 25),
2001};
2002static const unsigned int msiof1_rxd_f_mux[] = {
2003 MSIOF1_RXD_F_MARK,
2004};
2005static const unsigned int msiof1_clk_g_pins[] = {
2006 /* SCK */
2007 RCAR_GP_PIN(3, 6),
2008};
2009static const unsigned int msiof1_clk_g_mux[] = {
2010 MSIOF1_SCK_G_MARK,
2011};
2012static const unsigned int msiof1_sync_g_pins[] = {
2013 /* SYNC */
2014 RCAR_GP_PIN(3, 7),
2015};
2016static const unsigned int msiof1_sync_g_mux[] = {
2017 MSIOF1_SYNC_G_MARK,
2018};
2019static const unsigned int msiof1_ss1_g_pins[] = {
2020 /* SS1 */
2021 RCAR_GP_PIN(3, 10),
2022};
2023static const unsigned int msiof1_ss1_g_mux[] = {
2024 MSIOF1_SS1_G_MARK,
2025};
2026static const unsigned int msiof1_ss2_g_pins[] = {
2027 /* SS2 */
2028 RCAR_GP_PIN(3, 11),
2029};
2030static const unsigned int msiof1_ss2_g_mux[] = {
2031 MSIOF1_SS2_G_MARK,
2032};
2033static const unsigned int msiof1_txd_g_pins[] = {
2034 /* TXD */
2035 RCAR_GP_PIN(3, 9),
2036};
2037static const unsigned int msiof1_txd_g_mux[] = {
2038 MSIOF1_TXD_G_MARK,
2039};
2040static const unsigned int msiof1_rxd_g_pins[] = {
2041 /* RXD */
2042 RCAR_GP_PIN(3, 8),
2043};
2044static const unsigned int msiof1_rxd_g_mux[] = {
2045 MSIOF1_RXD_G_MARK,
2046};
2047/* - MSIOF2 ----------------------------------------------------------------- */
2048static const unsigned int msiof2_clk_a_pins[] = {
2049 /* SCK */
2050 RCAR_GP_PIN(1, 9),
2051};
2052static const unsigned int msiof2_clk_a_mux[] = {
2053 MSIOF2_SCK_A_MARK,
2054};
2055static const unsigned int msiof2_sync_a_pins[] = {
2056 /* SYNC */
2057 RCAR_GP_PIN(1, 8),
2058};
2059static const unsigned int msiof2_sync_a_mux[] = {
2060 MSIOF2_SYNC_A_MARK,
2061};
2062static const unsigned int msiof2_ss1_a_pins[] = {
2063 /* SS1 */
2064 RCAR_GP_PIN(1, 6),
2065};
2066static const unsigned int msiof2_ss1_a_mux[] = {
2067 MSIOF2_SS1_A_MARK,
2068};
2069static const unsigned int msiof2_ss2_a_pins[] = {
2070 /* SS2 */
2071 RCAR_GP_PIN(1, 7),
2072};
2073static const unsigned int msiof2_ss2_a_mux[] = {
2074 MSIOF2_SS2_A_MARK,
2075};
2076static const unsigned int msiof2_txd_a_pins[] = {
2077 /* TXD */
2078 RCAR_GP_PIN(1, 11),
2079};
2080static const unsigned int msiof2_txd_a_mux[] = {
2081 MSIOF2_TXD_A_MARK,
2082};
2083static const unsigned int msiof2_rxd_a_pins[] = {
2084 /* RXD */
2085 RCAR_GP_PIN(1, 10),
2086};
2087static const unsigned int msiof2_rxd_a_mux[] = {
2088 MSIOF2_RXD_A_MARK,
2089};
2090static const unsigned int msiof2_clk_b_pins[] = {
2091 /* SCK */
2092 RCAR_GP_PIN(0, 4),
2093};
2094static const unsigned int msiof2_clk_b_mux[] = {
2095 MSIOF2_SCK_B_MARK,
2096};
2097static const unsigned int msiof2_sync_b_pins[] = {
2098 /* SYNC */
2099 RCAR_GP_PIN(0, 5),
2100};
2101static const unsigned int msiof2_sync_b_mux[] = {
2102 MSIOF2_SYNC_B_MARK,
2103};
2104static const unsigned int msiof2_ss1_b_pins[] = {
2105 /* SS1 */
2106 RCAR_GP_PIN(0, 0),
2107};
2108static const unsigned int msiof2_ss1_b_mux[] = {
2109 MSIOF2_SS1_B_MARK,
2110};
2111static const unsigned int msiof2_ss2_b_pins[] = {
2112 /* SS2 */
2113 RCAR_GP_PIN(0, 1),
2114};
2115static const unsigned int msiof2_ss2_b_mux[] = {
2116 MSIOF2_SS2_B_MARK,
2117};
2118static const unsigned int msiof2_txd_b_pins[] = {
2119 /* TXD */
2120 RCAR_GP_PIN(0, 7),
2121};
2122static const unsigned int msiof2_txd_b_mux[] = {
2123 MSIOF2_TXD_B_MARK,
2124};
2125static const unsigned int msiof2_rxd_b_pins[] = {
2126 /* RXD */
2127 RCAR_GP_PIN(0, 6),
2128};
2129static const unsigned int msiof2_rxd_b_mux[] = {
2130 MSIOF2_RXD_B_MARK,
2131};
2132static const unsigned int msiof2_clk_c_pins[] = {
2133 /* SCK */
2134 RCAR_GP_PIN(2, 12),
2135};
2136static const unsigned int msiof2_clk_c_mux[] = {
2137 MSIOF2_SCK_C_MARK,
2138};
2139static const unsigned int msiof2_sync_c_pins[] = {
2140 /* SYNC */
2141 RCAR_GP_PIN(2, 11),
2142};
2143static const unsigned int msiof2_sync_c_mux[] = {
2144 MSIOF2_SYNC_C_MARK,
2145};
2146static const unsigned int msiof2_ss1_c_pins[] = {
2147 /* SS1 */
2148 RCAR_GP_PIN(2, 10),
2149};
2150static const unsigned int msiof2_ss1_c_mux[] = {
2151 MSIOF2_SS1_C_MARK,
2152};
2153static const unsigned int msiof2_ss2_c_pins[] = {
2154 /* SS2 */
2155 RCAR_GP_PIN(2, 9),
2156};
2157static const unsigned int msiof2_ss2_c_mux[] = {
2158 MSIOF2_SS2_C_MARK,
2159};
2160static const unsigned int msiof2_txd_c_pins[] = {
2161 /* TXD */
2162 RCAR_GP_PIN(2, 14),
2163};
2164static const unsigned int msiof2_txd_c_mux[] = {
2165 MSIOF2_TXD_C_MARK,
2166};
2167static const unsigned int msiof2_rxd_c_pins[] = {
2168 /* RXD */
2169 RCAR_GP_PIN(2, 13),
2170};
2171static const unsigned int msiof2_rxd_c_mux[] = {
2172 MSIOF2_RXD_C_MARK,
2173};
2174static const unsigned int msiof2_clk_d_pins[] = {
2175 /* SCK */
2176 RCAR_GP_PIN(0, 8),
2177};
2178static const unsigned int msiof2_clk_d_mux[] = {
2179 MSIOF2_SCK_D_MARK,
2180};
2181static const unsigned int msiof2_sync_d_pins[] = {
2182 /* SYNC */
2183 RCAR_GP_PIN(0, 9),
2184};
2185static const unsigned int msiof2_sync_d_mux[] = {
2186 MSIOF2_SYNC_D_MARK,
2187};
2188static const unsigned int msiof2_ss1_d_pins[] = {
2189 /* SS1 */
2190 RCAR_GP_PIN(0, 12),
2191};
2192static const unsigned int msiof2_ss1_d_mux[] = {
2193 MSIOF2_SS1_D_MARK,
2194};
2195static const unsigned int msiof2_ss2_d_pins[] = {
2196 /* SS2 */
2197 RCAR_GP_PIN(0, 13),
2198};
2199static const unsigned int msiof2_ss2_d_mux[] = {
2200 MSIOF2_SS2_D_MARK,
2201};
2202static const unsigned int msiof2_txd_d_pins[] = {
2203 /* TXD */
2204 RCAR_GP_PIN(0, 11),
2205};
2206static const unsigned int msiof2_txd_d_mux[] = {
2207 MSIOF2_TXD_D_MARK,
2208};
2209static const unsigned int msiof2_rxd_d_pins[] = {
2210 /* RXD */
2211 RCAR_GP_PIN(0, 10),
2212};
2213static const unsigned int msiof2_rxd_d_mux[] = {
2214 MSIOF2_RXD_D_MARK,
2215};
2216/* - MSIOF3 ----------------------------------------------------------------- */
2217static const unsigned int msiof3_clk_a_pins[] = {
2218 /* SCK */
2219 RCAR_GP_PIN(0, 0),
2220};
2221static const unsigned int msiof3_clk_a_mux[] = {
2222 MSIOF3_SCK_A_MARK,
2223};
2224static const unsigned int msiof3_sync_a_pins[] = {
2225 /* SYNC */
2226 RCAR_GP_PIN(0, 1),
2227};
2228static const unsigned int msiof3_sync_a_mux[] = {
2229 MSIOF3_SYNC_A_MARK,
2230};
2231static const unsigned int msiof3_ss1_a_pins[] = {
2232 /* SS1 */
2233 RCAR_GP_PIN(0, 14),
2234};
2235static const unsigned int msiof3_ss1_a_mux[] = {
2236 MSIOF3_SS1_A_MARK,
2237};
2238static const unsigned int msiof3_ss2_a_pins[] = {
2239 /* SS2 */
2240 RCAR_GP_PIN(0, 15),
2241};
2242static const unsigned int msiof3_ss2_a_mux[] = {
2243 MSIOF3_SS2_A_MARK,
2244};
2245static const unsigned int msiof3_txd_a_pins[] = {
2246 /* TXD */
2247 RCAR_GP_PIN(0, 3),
2248};
2249static const unsigned int msiof3_txd_a_mux[] = {
2250 MSIOF3_TXD_A_MARK,
2251};
2252static const unsigned int msiof3_rxd_a_pins[] = {
2253 /* RXD */
2254 RCAR_GP_PIN(0, 2),
2255};
2256static const unsigned int msiof3_rxd_a_mux[] = {
2257 MSIOF3_RXD_A_MARK,
2258};
2259static const unsigned int msiof3_clk_b_pins[] = {
2260 /* SCK */
2261 RCAR_GP_PIN(1, 2),
2262};
2263static const unsigned int msiof3_clk_b_mux[] = {
2264 MSIOF3_SCK_B_MARK,
2265};
2266static const unsigned int msiof3_sync_b_pins[] = {
2267 /* SYNC */
2268 RCAR_GP_PIN(1, 0),
2269};
2270static const unsigned int msiof3_sync_b_mux[] = {
2271 MSIOF3_SYNC_B_MARK,
2272};
2273static const unsigned int msiof3_ss1_b_pins[] = {
2274 /* SS1 */
2275 RCAR_GP_PIN(1, 4),
2276};
2277static const unsigned int msiof3_ss1_b_mux[] = {
2278 MSIOF3_SS1_B_MARK,
2279};
2280static const unsigned int msiof3_ss2_b_pins[] = {
2281 /* SS2 */
2282 RCAR_GP_PIN(1, 5),
2283};
2284static const unsigned int msiof3_ss2_b_mux[] = {
2285 MSIOF3_SS2_B_MARK,
2286};
2287static const unsigned int msiof3_txd_b_pins[] = {
2288 /* TXD */
2289 RCAR_GP_PIN(1, 1),
2290};
2291static const unsigned int msiof3_txd_b_mux[] = {
2292 MSIOF3_TXD_B_MARK,
2293};
2294static const unsigned int msiof3_rxd_b_pins[] = {
2295 /* RXD */
2296 RCAR_GP_PIN(1, 3),
2297};
2298static const unsigned int msiof3_rxd_b_mux[] = {
2299 MSIOF3_RXD_B_MARK,
2300};
2301static const unsigned int msiof3_clk_c_pins[] = {
2302 /* SCK */
2303 RCAR_GP_PIN(1, 12),
2304};
2305static const unsigned int msiof3_clk_c_mux[] = {
2306 MSIOF3_SCK_C_MARK,
2307};
2308static const unsigned int msiof3_sync_c_pins[] = {
2309 /* SYNC */
2310 RCAR_GP_PIN(1, 13),
2311};
2312static const unsigned int msiof3_sync_c_mux[] = {
2313 MSIOF3_SYNC_C_MARK,
2314};
2315static const unsigned int msiof3_txd_c_pins[] = {
2316 /* TXD */
2317 RCAR_GP_PIN(1, 15),
2318};
2319static const unsigned int msiof3_txd_c_mux[] = {
2320 MSIOF3_TXD_C_MARK,
2321};
2322static const unsigned int msiof3_rxd_c_pins[] = {
2323 /* RXD */
2324 RCAR_GP_PIN(1, 14),
2325};
2326static const unsigned int msiof3_rxd_c_mux[] = {
2327 MSIOF3_RXD_C_MARK,
2328};
2329static const unsigned int msiof3_clk_d_pins[] = {
2330 /* SCK */
2331 RCAR_GP_PIN(1, 22),
2332};
2333static const unsigned int msiof3_clk_d_mux[] = {
2334 MSIOF3_SCK_D_MARK,
2335};
2336static const unsigned int msiof3_sync_d_pins[] = {
2337 /* SYNC */
2338 RCAR_GP_PIN(1, 23),
2339};
2340static const unsigned int msiof3_sync_d_mux[] = {
2341 MSIOF3_SYNC_D_MARK,
2342};
2343static const unsigned int msiof3_ss1_d_pins[] = {
2344 /* SS1 */
2345 RCAR_GP_PIN(1, 26),
2346};
2347static const unsigned int msiof3_ss1_d_mux[] = {
2348 MSIOF3_SS1_D_MARK,
2349};
2350static const unsigned int msiof3_txd_d_pins[] = {
2351 /* TXD */
2352 RCAR_GP_PIN(1, 25),
2353};
2354static const unsigned int msiof3_txd_d_mux[] = {
2355 MSIOF3_TXD_D_MARK,
2356};
2357static const unsigned int msiof3_rxd_d_pins[] = {
2358 /* RXD */
2359 RCAR_GP_PIN(1, 24),
2360};
2361static const unsigned int msiof3_rxd_d_mux[] = {
2362 MSIOF3_RXD_D_MARK,
2363};
2364static const unsigned int msiof3_clk_e_pins[] = {
2365 /* SCK */
2366 RCAR_GP_PIN(2, 3),
2367};
2368static const unsigned int msiof3_clk_e_mux[] = {
2369 MSIOF3_SCK_E_MARK,
2370};
2371static const unsigned int msiof3_sync_e_pins[] = {
2372 /* SYNC */
2373 RCAR_GP_PIN(2, 2),
2374};
2375static const unsigned int msiof3_sync_e_mux[] = {
2376 MSIOF3_SYNC_E_MARK,
2377};
2378static const unsigned int msiof3_ss1_e_pins[] = {
2379 /* SS1 */
2380 RCAR_GP_PIN(2, 1),
2381};
2382static const unsigned int msiof3_ss1_e_mux[] = {
2383 MSIOF3_SS1_E_MARK,
2384};
2385static const unsigned int msiof3_ss2_e_pins[] = {
2386 /* SS2 */
2387 RCAR_GP_PIN(2, 0),
2388};
2389static const unsigned int msiof3_ss2_e_mux[] = {
2390 MSIOF3_SS2_E_MARK,
2391};
2392static const unsigned int msiof3_txd_e_pins[] = {
2393 /* TXD */
2394 RCAR_GP_PIN(2, 5),
2395};
2396static const unsigned int msiof3_txd_e_mux[] = {
2397 MSIOF3_TXD_E_MARK,
2398};
2399static const unsigned int msiof3_rxd_e_pins[] = {
2400 /* RXD */
2401 RCAR_GP_PIN(2, 4),
2402};
2403static const unsigned int msiof3_rxd_e_mux[] = {
2404 MSIOF3_RXD_E_MARK,
2405};
2406
54b7f2da
TK		 2407/* - PWM0 --------------------------------------------------------------------*/
2408static const unsigned int pwm0_pins[] = {
2409 /* PWM */
2410 RCAR_GP_PIN(2, 6),
2411};
2412static const unsigned int pwm0_mux[] = {
2413 PWM0_MARK,
2414};
2415/* - PWM1 --------------------------------------------------------------------*/
2416static const unsigned int pwm1_a_pins[] = {
2417 /* PWM */
2418 RCAR_GP_PIN(2, 7),
2419};
2420static const unsigned int pwm1_a_mux[] = {
2421 PWM1_A_MARK,
2422};
2423static const unsigned int pwm1_b_pins[] = {
2424 /* PWM */
2425 RCAR_GP_PIN(1, 8),
2426};
2427static const unsigned int pwm1_b_mux[] = {
2428 PWM1_B_MARK,
2429};
2430/* - PWM2 --------------------------------------------------------------------*/
2431static const unsigned int pwm2_a_pins[] = {
2432 /* PWM */
2433 RCAR_GP_PIN(2, 8),
2434};
2435static const unsigned int pwm2_a_mux[] = {
2436 PWM2_A_MARK,
2437};
2438static const unsigned int pwm2_b_pins[] = {
2439 /* PWM */
2440 RCAR_GP_PIN(1, 11),
2441};
2442static const unsigned int pwm2_b_mux[] = {
2443 PWM2_B_MARK,
2444};
2445/* - PWM3 --------------------------------------------------------------------*/
2446static const unsigned int pwm3_a_pins[] = {
2447 /* PWM */
2448 RCAR_GP_PIN(1, 0),
2449};
2450static const unsigned int pwm3_a_mux[] = {
2451 PWM3_A_MARK,
2452};
2453static const unsigned int pwm3_b_pins[] = {
2454 /* PWM */
2455 RCAR_GP_PIN(2, 2),
2456};
2457static const unsigned int pwm3_b_mux[] = {
2458 PWM3_B_MARK,
2459};
2460/* - PWM4 --------------------------------------------------------------------*/
2461static const unsigned int pwm4_a_pins[] = {
2462 /* PWM */
2463 RCAR_GP_PIN(1, 1),
2464};
2465static const unsigned int pwm4_a_mux[] = {
2466 PWM4_A_MARK,
2467};
2468static const unsigned int pwm4_b_pins[] = {
2469 /* PWM */
2470 RCAR_GP_PIN(2, 3),
2471};
2472static const unsigned int pwm4_b_mux[] = {
2473 PWM4_B_MARK,
2474};
2475/* - PWM5 --------------------------------------------------------------------*/
2476static const unsigned int pwm5_a_pins[] = {
2477 /* PWM */
2478 RCAR_GP_PIN(1, 2),
2479};
2480static const unsigned int pwm5_a_mux[] = {
2481 PWM5_A_MARK,
2482};
2483static const unsigned int pwm5_b_pins[] = {
2484 /* PWM */
2485 RCAR_GP_PIN(2, 4),
2486};
2487static const unsigned int pwm5_b_mux[] = {
2488 PWM5_B_MARK,
2489};
2490/* - PWM6 --------------------------------------------------------------------*/
2491static const unsigned int pwm6_a_pins[] = {
2492 /* PWM */
2493 RCAR_GP_PIN(1, 3),
2494};
2495static const unsigned int pwm6_a_mux[] = {
2496 PWM6_A_MARK,
2497};
2498static const unsigned int pwm6_b_pins[] = {
2499 /* PWM */
2500 RCAR_GP_PIN(2, 5),
2501};
2502static const unsigned int pwm6_b_mux[] = {
2503 PWM6_B_MARK,
2504};
2505
58cfd7f3
JM		 2506/* - SCIF0 ------------------------------------------------------------------ */
2507static const unsigned int scif0_data_pins[] = {
2508 /* RX, TX */
2509 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2510};
2511static const unsigned int scif0_data_mux[] = {
2512 RX0_MARK, TX0_MARK,
2513};
2514static const unsigned int scif0_clk_pins[] = {
2515 /* SCK */
2516 RCAR_GP_PIN(5, 0),
2517};
2518static const unsigned int scif0_clk_mux[] = {
2519 SCK0_MARK,
2520};
2521static const unsigned int scif0_ctrl_pins[] = {
2522 /* RTS, CTS */
2523 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2524};
2525static const unsigned int scif0_ctrl_mux[] = {
2526 RTS0_N_MARK, CTS0_N_MARK,
2527};
2528/* - SCIF1 ------------------------------------------------------------------ */
2529static const unsigned int scif1_data_a_pins[] = {
2530 /* RX, TX */
2531 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2532};
2533static const unsigned int scif1_data_a_mux[] = {
2534 RX1_A_MARK, TX1_A_MARK,
2535};
2536static const unsigned int scif1_clk_pins[] = {
2537 /* SCK */
2538 RCAR_GP_PIN(6, 21),
2539};
2540static const unsigned int scif1_clk_mux[] = {
2541 SCK1_MARK,
2542};
2543static const unsigned int scif1_ctrl_pins[] = {
2544 /* RTS, CTS */
2545 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2546};
2547static const unsigned int scif1_ctrl_mux[] = {
2548 RTS1_N_MARK, CTS1_N_MARK,
2549};
2550static const unsigned int scif1_data_b_pins[] = {
2551 /* RX, TX */
2552 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2553};
2554static const unsigned int scif1_data_b_mux[] = {
2555 RX1_B_MARK, TX1_B_MARK,
2556};
2557/* - SCIF2 ------------------------------------------------------------------ */
2558static const unsigned int scif2_data_a_pins[] = {
2559 /* RX, TX */
2560 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2561};
2562static const unsigned int scif2_data_a_mux[] = {
2563 RX2_A_MARK, TX2_A_MARK,
2564};
2565static const unsigned int scif2_clk_pins[] = {
2566 /* SCK */
2567 RCAR_GP_PIN(5, 9),
2568};
2569static const unsigned int scif2_clk_mux[] = {
2570 SCK2_MARK,
2571};
2572static const unsigned int scif2_data_b_pins[] = {
2573 /* RX, TX */
2574 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2575};
2576static const unsigned int scif2_data_b_mux[] = {
2577 RX2_B_MARK, TX2_B_MARK,
2578};
2579/* - SCIF3 ------------------------------------------------------------------ */
2580static const unsigned int scif3_data_a_pins[] = {
2581 /* RX, TX */
2582 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2583};
2584static const unsigned int scif3_data_a_mux[] = {
2585 RX3_A_MARK, TX3_A_MARK,
2586};
2587static const unsigned int scif3_clk_pins[] = {
2588 /* SCK */
2589 RCAR_GP_PIN(1, 22),
2590};
2591static const unsigned int scif3_clk_mux[] = {
2592 SCK3_MARK,
2593};
2594static const unsigned int scif3_ctrl_pins[] = {
2595 /* RTS, CTS */
2596 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2597};
2598static const unsigned int scif3_ctrl_mux[] = {
2599 RTS3_N_MARK, CTS3_N_MARK,
2600};
2601static const unsigned int scif3_data_b_pins[] = {
2602 /* RX, TX */
2603 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2604};
2605static const unsigned int scif3_data_b_mux[] = {
2606 RX3_B_MARK, TX3_B_MARK,
2607};
2608/* - SCIF4 ------------------------------------------------------------------ */
2609static const unsigned int scif4_data_a_pins[] = {
2610 /* RX, TX */
2611 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2612};
2613static const unsigned int scif4_data_a_mux[] = {
2614 RX4_A_MARK, TX4_A_MARK,
2615};
2616static const unsigned int scif4_clk_a_pins[] = {
2617 /* SCK */
2618 RCAR_GP_PIN(2, 10),
2619};
2620static const unsigned int scif4_clk_a_mux[] = {
2621 SCK4_A_MARK,
2622};
2623static const unsigned int scif4_ctrl_a_pins[] = {
2624 /* RTS, CTS */
2625 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2626};
2627static const unsigned int scif4_ctrl_a_mux[] = {
2628 RTS4_N_A_MARK, CTS4_N_A_MARK,
2629};
2630static const unsigned int scif4_data_b_pins[] = {
2631 /* RX, TX */
2632 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2633};
2634static const unsigned int scif4_data_b_mux[] = {
2635 RX4_B_MARK, TX4_B_MARK,
2636};
2637static const unsigned int scif4_clk_b_pins[] = {
2638 /* SCK */
2639 RCAR_GP_PIN(1, 5),
2640};
2641static const unsigned int scif4_clk_b_mux[] = {
2642 SCK4_B_MARK,
2643};
2644static const unsigned int scif4_ctrl_b_pins[] = {
2645 /* RTS, CTS */
2646 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
2647};
2648static const unsigned int scif4_ctrl_b_mux[] = {
2649 RTS4_N_B_MARK, CTS4_N_B_MARK,
2650};
2651static const unsigned int scif4_data_c_pins[] = {
2652 /* RX, TX */
2653 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
2654};
2655static const unsigned int scif4_data_c_mux[] = {
2656 RX4_C_MARK, TX4_C_MARK,
2657};
2658static const unsigned int scif4_clk_c_pins[] = {
2659 /* SCK */
2660 RCAR_GP_PIN(0, 8),
2661};
2662static const unsigned int scif4_clk_c_mux[] = {
2663 SCK4_C_MARK,
2664};
2665static const unsigned int scif4_ctrl_c_pins[] = {
2666 /* RTS, CTS */
2667 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2668};
2669static const unsigned int scif4_ctrl_c_mux[] = {
2670 RTS4_N_C_MARK, CTS4_N_C_MARK,
2671};
2672/* - SCIF5 ------------------------------------------------------------------ */
2673static const unsigned int scif5_data_a_pins[] = {
2674 /* RX, TX */
2675 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
2676};
2677static const unsigned int scif5_data_a_mux[] = {
2678 RX5_A_MARK, TX5_A_MARK,
2679};
2680static const unsigned int scif5_clk_a_pins[] = {
2681 /* SCK */
2682 RCAR_GP_PIN(6, 21),
2683};
2684static const unsigned int scif5_clk_a_mux[] = {
2685 SCK5_A_MARK,
2686};
2687static const unsigned int scif5_data_b_pins[] = {
2688 /* RX, TX */
2689 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
2690};
2691static const unsigned int scif5_data_b_mux[] = {
2692 RX5_B_MARK, TX5_B_MARK,
2693};
2694static const unsigned int scif5_clk_b_pins[] = {
2695 /* SCK */
2696 RCAR_GP_PIN(5, 0),
2697};
2698static const unsigned int scif5_clk_b_mux[] = {
2699 SCK5_B_MARK,
2700};
2701/* - SCIF Clock ------------------------------------------------------------- */
2702static const unsigned int scif_clk_a_pins[] = {
2703 /* SCIF_CLK */
2704 RCAR_GP_PIN(6, 23),
2705};
2706static const unsigned int scif_clk_a_mux[] = {
2707 SCIF_CLK_A_MARK,
2708};
2709static const unsigned int scif_clk_b_pins[] = {
2710 /* SCIF_CLK */
2711 RCAR_GP_PIN(5, 9),
2712};
2713static const unsigned int scif_clk_b_mux[] = {
2714 SCIF_CLK_B_MARK,
2715};
2716
0d75f8da
TK		 2717/* - USB0 ------------------------------------------------------------------- */
2718static const unsigned int usb0_pins[] = {
2719 /* PWEN, OVC */
2720 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2721};
2722
2723static const unsigned int usb0_mux[] = {
2724 USB0_PWEN_MARK, USB0_OVC_MARK,
2725};
2726
2727/* - USB1 ------------------------------------------------------------------- */
2728static const unsigned int usb1_pins[] = {
2729 /* PWEN, OVC */
2730 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2731};
2732
2733static const unsigned int usb1_mux[] = {
2734 USB1_PWEN_MARK, USB1_OVC_MARK,
2735};
2736
c490b28f
TK		 2737/* - USB30 ------------------------------------------------------------------ */
2738static const unsigned int usb30_pins[] = {
2739 /* PWEN, OVC */
2740 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2741};
2742
2743static const unsigned int usb30_mux[] = {
2744 USB30_PWEN_MARK, USB30_OVC_MARK,
2745};
2746
490e687e 2747static const struct sh_pfc_pin_group pinmux_groups[] = {
fa3e8b71
JM		 2748 SH_PFC_PIN_GROUP(avb_link),
2749 SH_PFC_PIN_GROUP(avb_magic),
2750 SH_PFC_PIN_GROUP(avb_phy_int),
f7ce295c
GU		 2751 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
2752 SH_PFC_PIN_GROUP(avb_mdio),
fa3e8b71
JM		 2753 SH_PFC_PIN_GROUP(avb_mii),
2754 SH_PFC_PIN_GROUP(avb_avtp_pps),
2755 SH_PFC_PIN_GROUP(avb_avtp_match_a),
2756 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
2757 SH_PFC_PIN_GROUP(avb_avtp_match_b),
2758 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
a8ab4f2b
TK		 2759 SH_PFC_PIN_GROUP(intc_ex_irq0),
2760 SH_PFC_PIN_GROUP(intc_ex_irq1),
2761 SH_PFC_PIN_GROUP(intc_ex_irq2),
2762 SH_PFC_PIN_GROUP(intc_ex_irq3),
2763 SH_PFC_PIN_GROUP(intc_ex_irq4),
2764 SH_PFC_PIN_GROUP(intc_ex_irq5),
2c77aa3d
TK		 2765 SH_PFC_PIN_GROUP(msiof0_clk),
2766 SH_PFC_PIN_GROUP(msiof0_sync),
2767 SH_PFC_PIN_GROUP(msiof0_ss1),
2768 SH_PFC_PIN_GROUP(msiof0_ss2),
2769 SH_PFC_PIN_GROUP(msiof0_txd),
2770 SH_PFC_PIN_GROUP(msiof0_rxd),
2771 SH_PFC_PIN_GROUP(msiof1_clk_a),
2772 SH_PFC_PIN_GROUP(msiof1_sync_a),
2773 SH_PFC_PIN_GROUP(msiof1_ss1_a),
2774 SH_PFC_PIN_GROUP(msiof1_ss2_a),
2775 SH_PFC_PIN_GROUP(msiof1_txd_a),
2776 SH_PFC_PIN_GROUP(msiof1_rxd_a),
2777 SH_PFC_PIN_GROUP(msiof1_clk_b),
2778 SH_PFC_PIN_GROUP(msiof1_sync_b),
2779 SH_PFC_PIN_GROUP(msiof1_ss1_b),
2780 SH_PFC_PIN_GROUP(msiof1_ss2_b),
2781 SH_PFC_PIN_GROUP(msiof1_txd_b),
2782 SH_PFC_PIN_GROUP(msiof1_rxd_b),
2783 SH_PFC_PIN_GROUP(msiof1_clk_c),
2784 SH_PFC_PIN_GROUP(msiof1_sync_c),
2785 SH_PFC_PIN_GROUP(msiof1_ss1_c),
2786 SH_PFC_PIN_GROUP(msiof1_ss2_c),
2787 SH_PFC_PIN_GROUP(msiof1_txd_c),
2788 SH_PFC_PIN_GROUP(msiof1_rxd_c),
2789 SH_PFC_PIN_GROUP(msiof1_clk_d),
2790 SH_PFC_PIN_GROUP(msiof1_sync_d),
2791 SH_PFC_PIN_GROUP(msiof1_ss1_d),
2792 SH_PFC_PIN_GROUP(msiof1_ss2_d),
2793 SH_PFC_PIN_GROUP(msiof1_txd_d),
2794 SH_PFC_PIN_GROUP(msiof1_rxd_d),
2795 SH_PFC_PIN_GROUP(msiof1_clk_e),
2796 SH_PFC_PIN_GROUP(msiof1_sync_e),
2797 SH_PFC_PIN_GROUP(msiof1_ss1_e),
2798 SH_PFC_PIN_GROUP(msiof1_ss2_e),
2799 SH_PFC_PIN_GROUP(msiof1_txd_e),
2800 SH_PFC_PIN_GROUP(msiof1_rxd_e),
2801 SH_PFC_PIN_GROUP(msiof1_clk_f),
2802 SH_PFC_PIN_GROUP(msiof1_sync_f),
2803 SH_PFC_PIN_GROUP(msiof1_ss1_f),
2804 SH_PFC_PIN_GROUP(msiof1_ss2_f),
2805 SH_PFC_PIN_GROUP(msiof1_txd_f),
2806 SH_PFC_PIN_GROUP(msiof1_rxd_f),
2807 SH_PFC_PIN_GROUP(msiof1_clk_g),
2808 SH_PFC_PIN_GROUP(msiof1_sync_g),
2809 SH_PFC_PIN_GROUP(msiof1_ss1_g),
2810 SH_PFC_PIN_GROUP(msiof1_ss2_g),
2811 SH_PFC_PIN_GROUP(msiof1_txd_g),
2812 SH_PFC_PIN_GROUP(msiof1_rxd_g),
2813 SH_PFC_PIN_GROUP(msiof2_clk_a),
2814 SH_PFC_PIN_GROUP(msiof2_sync_a),
2815 SH_PFC_PIN_GROUP(msiof2_ss1_a),
2816 SH_PFC_PIN_GROUP(msiof2_ss2_a),
2817 SH_PFC_PIN_GROUP(msiof2_txd_a),
2818 SH_PFC_PIN_GROUP(msiof2_rxd_a),
2819 SH_PFC_PIN_GROUP(msiof2_clk_b),
2820 SH_PFC_PIN_GROUP(msiof2_sync_b),
2821 SH_PFC_PIN_GROUP(msiof2_ss1_b),
2822 SH_PFC_PIN_GROUP(msiof2_ss2_b),
2823 SH_PFC_PIN_GROUP(msiof2_txd_b),
2824 SH_PFC_PIN_GROUP(msiof2_rxd_b),
2825 SH_PFC_PIN_GROUP(msiof2_clk_c),
2826 SH_PFC_PIN_GROUP(msiof2_sync_c),
2827 SH_PFC_PIN_GROUP(msiof2_ss1_c),
2828 SH_PFC_PIN_GROUP(msiof2_ss2_c),
2829 SH_PFC_PIN_GROUP(msiof2_txd_c),
2830 SH_PFC_PIN_GROUP(msiof2_rxd_c),
2831 SH_PFC_PIN_GROUP(msiof2_clk_d),
2832 SH_PFC_PIN_GROUP(msiof2_sync_d),
2833 SH_PFC_PIN_GROUP(msiof2_ss1_d),
2834 SH_PFC_PIN_GROUP(msiof2_ss2_d),
2835 SH_PFC_PIN_GROUP(msiof2_txd_d),
2836 SH_PFC_PIN_GROUP(msiof2_rxd_d),
2837 SH_PFC_PIN_GROUP(msiof3_clk_a),
2838 SH_PFC_PIN_GROUP(msiof3_sync_a),
2839 SH_PFC_PIN_GROUP(msiof3_ss1_a),
2840 SH_PFC_PIN_GROUP(msiof3_ss2_a),
2841 SH_PFC_PIN_GROUP(msiof3_txd_a),
2842 SH_PFC_PIN_GROUP(msiof3_rxd_a),
2843 SH_PFC_PIN_GROUP(msiof3_clk_b),
2844 SH_PFC_PIN_GROUP(msiof3_sync_b),
2845 SH_PFC_PIN_GROUP(msiof3_ss1_b),
2846 SH_PFC_PIN_GROUP(msiof3_ss2_b),
2847 SH_PFC_PIN_GROUP(msiof3_txd_b),
2848 SH_PFC_PIN_GROUP(msiof3_rxd_b),
2849 SH_PFC_PIN_GROUP(msiof3_clk_c),
2850 SH_PFC_PIN_GROUP(msiof3_sync_c),
2851 SH_PFC_PIN_GROUP(msiof3_txd_c),
2852 SH_PFC_PIN_GROUP(msiof3_rxd_c),
2853 SH_PFC_PIN_GROUP(msiof3_clk_d),
2854 SH_PFC_PIN_GROUP(msiof3_sync_d),
2855 SH_PFC_PIN_GROUP(msiof3_ss1_d),
2856 SH_PFC_PIN_GROUP(msiof3_txd_d),
2857 SH_PFC_PIN_GROUP(msiof3_rxd_d),
2858 SH_PFC_PIN_GROUP(msiof3_clk_e),
2859 SH_PFC_PIN_GROUP(msiof3_sync_e),
2860 SH_PFC_PIN_GROUP(msiof3_ss1_e),
2861 SH_PFC_PIN_GROUP(msiof3_ss2_e),
2862 SH_PFC_PIN_GROUP(msiof3_txd_e),
2863 SH_PFC_PIN_GROUP(msiof3_rxd_e),
54b7f2da
TK		 2864 SH_PFC_PIN_GROUP(pwm0),
2865 SH_PFC_PIN_GROUP(pwm1_a),
2866 SH_PFC_PIN_GROUP(pwm1_b),
2867 SH_PFC_PIN_GROUP(pwm2_a),
2868 SH_PFC_PIN_GROUP(pwm2_b),
2869 SH_PFC_PIN_GROUP(pwm3_a),
2870 SH_PFC_PIN_GROUP(pwm3_b),
2871 SH_PFC_PIN_GROUP(pwm4_a),
2872 SH_PFC_PIN_GROUP(pwm4_b),
2873 SH_PFC_PIN_GROUP(pwm5_a),
2874 SH_PFC_PIN_GROUP(pwm5_b),
2875 SH_PFC_PIN_GROUP(pwm6_a),
2876 SH_PFC_PIN_GROUP(pwm6_b),
58cfd7f3
JM		 2877 SH_PFC_PIN_GROUP(scif0_data),
2878 SH_PFC_PIN_GROUP(scif0_clk),
2879 SH_PFC_PIN_GROUP(scif0_ctrl),
2880 SH_PFC_PIN_GROUP(scif1_data_a),
2881 SH_PFC_PIN_GROUP(scif1_clk),
2882 SH_PFC_PIN_GROUP(scif1_ctrl),
2883 SH_PFC_PIN_GROUP(scif1_data_b),
2884 SH_PFC_PIN_GROUP(scif2_data_a),
2885 SH_PFC_PIN_GROUP(scif2_clk),
2886 SH_PFC_PIN_GROUP(scif2_data_b),
2887 SH_PFC_PIN_GROUP(scif3_data_a),
2888 SH_PFC_PIN_GROUP(scif3_clk),
2889 SH_PFC_PIN_GROUP(scif3_ctrl),
2890 SH_PFC_PIN_GROUP(scif3_data_b),
2891 SH_PFC_PIN_GROUP(scif4_data_a),
2892 SH_PFC_PIN_GROUP(scif4_clk_a),
2893 SH_PFC_PIN_GROUP(scif4_ctrl_a),
2894 SH_PFC_PIN_GROUP(scif4_data_b),
2895 SH_PFC_PIN_GROUP(scif4_clk_b),
2896 SH_PFC_PIN_GROUP(scif4_ctrl_b),
2897 SH_PFC_PIN_GROUP(scif4_data_c),
2898 SH_PFC_PIN_GROUP(scif4_clk_c),
2899 SH_PFC_PIN_GROUP(scif4_ctrl_c),
2900 SH_PFC_PIN_GROUP(scif5_data_a),
2901 SH_PFC_PIN_GROUP(scif5_clk_a),
2902 SH_PFC_PIN_GROUP(scif5_data_b),
2903 SH_PFC_PIN_GROUP(scif5_clk_b),
2904 SH_PFC_PIN_GROUP(scif_clk_a),
2905 SH_PFC_PIN_GROUP(scif_clk_b),
0d75f8da
TK		 2906 SH_PFC_PIN_GROUP(usb0),
2907 SH_PFC_PIN_GROUP(usb1),
c490b28f 2908 SH_PFC_PIN_GROUP(usb30),
58cfd7f3
JM		 2909};
2910
fa3e8b71
JM		 2911static const char * const avb_groups[] = {
2912 "avb_link",
2913 "avb_magic",
2914 "avb_phy_int",
f7ce295c
GU		 2915 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
2916 "avb_mdio",
fa3e8b71
JM		 2917 "avb_mii",
2918 "avb_avtp_pps",
2919 "avb_avtp_match_a",
2920 "avb_avtp_capture_a",
2921 "avb_avtp_match_b",
2922 "avb_avtp_capture_b",
2923};
2924
a8ab4f2b
TK		 2925static const char * const intc_ex_groups[] = {
2926 "intc_ex_irq0",
2927 "intc_ex_irq1",
2928 "intc_ex_irq2",
2929 "intc_ex_irq3",
2930 "intc_ex_irq4",
2931 "intc_ex_irq5",
2932};
2933
2c77aa3d
TK		 2934static const char * const msiof0_groups[] = {
2935 "msiof0_clk",
2936 "msiof0_sync",
2937 "msiof0_ss1",
2938 "msiof0_ss2",
2939 "msiof0_txd",
2940 "msiof0_rxd",
2941};
2942
2943static const char * const msiof1_groups[] = {
2944 "msiof1_clk_a",
2945 "msiof1_sync_a",
2946 "msiof1_ss1_a",
2947 "msiof1_ss2_a",
2948 "msiof1_txd_a",
2949 "msiof1_rxd_a",
2950 "msiof1_clk_b",
2951 "msiof1_sync_b",
2952 "msiof1_ss1_b",
2953 "msiof1_ss2_b",
2954 "msiof1_txd_b",
2955 "msiof1_rxd_b",
2956 "msiof1_clk_c",
2957 "msiof1_sync_c",
2958 "msiof1_ss1_c",
2959 "msiof1_ss2_c",
2960 "msiof1_txd_c",
2961 "msiof1_rxd_c",
2962 "msiof1_clk_d",
2963 "msiof1_sync_d",
2964 "msiof1_ss1_d",
2965 "msiof1_ss2_d",
2966 "msiof1_txd_d",
2967 "msiof1_rxd_d",
2968 "msiof1_clk_e",
2969 "msiof1_sync_e",
2970 "msiof1_ss1_e",
2971 "msiof1_ss2_e",
2972 "msiof1_txd_e",
2973 "msiof1_rxd_e",
2974 "msiof1_clk_f",
2975 "msiof1_sync_f",
2976 "msiof1_ss1_f",
2977 "msiof1_ss2_f",
2978 "msiof1_txd_f",
2979 "msiof1_rxd_f",
2980 "msiof1_clk_g",
2981 "msiof1_sync_g",
2982 "msiof1_ss1_g",
2983 "msiof1_ss2_g",
2984 "msiof1_txd_g",
2985 "msiof1_rxd_g",
2986};
2987
2988static const char * const msiof2_groups[] = {
2989 "msiof2_clk_a",
2990 "msiof2_sync_a",
2991 "msiof2_ss1_a",
2992 "msiof2_ss2_a",
2993 "msiof2_txd_a",
2994 "msiof2_rxd_a",
2995 "msiof2_clk_b",
2996 "msiof2_sync_b",
2997 "msiof2_ss1_b",
2998 "msiof2_ss2_b",
2999 "msiof2_txd_b",
3000 "msiof2_rxd_b",
3001 "msiof2_clk_c",
3002 "msiof2_sync_c",
3003 "msiof2_ss1_c",
3004 "msiof2_ss2_c",
3005 "msiof2_txd_c",
3006 "msiof2_rxd_c",
3007 "msiof2_clk_d",
3008 "msiof2_sync_d",
3009 "msiof2_ss1_d",
3010 "msiof2_ss2_d",
3011 "msiof2_txd_d",
3012 "msiof2_rxd_d",
3013};
3014
3015static const char * const msiof3_groups[] = {
3016 "msiof3_clk_a",
3017 "msiof3_sync_a",
3018 "msiof3_ss1_a",
3019 "msiof3_ss2_a",
3020 "msiof3_txd_a",
3021 "msiof3_rxd_a",
3022 "msiof3_clk_b",
3023 "msiof3_sync_b",
3024 "msiof3_ss1_b",
3025 "msiof3_ss2_b",
3026 "msiof3_txd_b",
3027 "msiof3_rxd_b",
3028 "msiof3_clk_c",
3029 "msiof3_sync_c",
3030 "msiof3_txd_c",
3031 "msiof3_rxd_c",
3032 "msiof3_clk_d",
3033 "msiof3_sync_d",
3034 "msiof3_ss1_d",
3035 "msiof3_txd_d",
3036 "msiof3_rxd_d",
3037 "msiof3_clk_e",
3038 "msiof3_sync_e",
3039 "msiof3_ss1_e",
3040 "msiof3_ss2_e",
3041 "msiof3_txd_e",
3042 "msiof3_rxd_e",
3043};
3044
54b7f2da
TK		 3045static const char * const pwm0_groups[] = {
3046 "pwm0",
3047};
3048
3049static const char * const pwm1_groups[] = {
3050 "pwm1_a",
3051 "pwm1_b",
3052};
3053
3054static const char * const pwm2_groups[] = {
3055 "pwm2_a",
3056 "pwm2_b",
3057};
3058
3059static const char * const pwm3_groups[] = {
3060 "pwm3_a",
3061 "pwm3_b",
3062};
3063
3064static const char * const pwm4_groups[] = {
3065 "pwm4_a",
3066 "pwm4_b",
3067};
3068
3069static const char * const pwm5_groups[] = {
3070 "pwm5_a",
3071 "pwm5_b",
3072};
3073
3074static const char * const pwm6_groups[] = {
3075 "pwm6_a",
3076 "pwm6_b",
3077};
3078
58cfd7f3
JM		 3079static const char * const scif0_groups[] = {
3080 "scif0_data",
3081 "scif0_clk",
3082 "scif0_ctrl",
3083};
3084
3085static const char * const scif1_groups[] = {
3086 "scif1_data_a",
3087 "scif1_clk",
3088 "scif1_ctrl",
3089 "scif1_data_b",
3090};
3091static const char * const scif2_groups[] = {
3092 "scif2_data_a",
3093 "scif2_clk",
3094 "scif2_data_b",
3095};
3096
3097static const char * const scif3_groups[] = {
3098 "scif3_data_a",
3099 "scif3_clk",
3100 "scif3_ctrl",
3101 "scif3_data_b",
3102};
3103
3104static const char * const scif4_groups[] = {
3105 "scif4_data_a",
3106 "scif4_clk_a",
3107 "scif4_ctrl_a",
3108 "scif4_data_b",
3109 "scif4_clk_b",
3110 "scif4_ctrl_b",
3111 "scif4_data_c",
3112 "scif4_clk_c",
3113 "scif4_ctrl_c",
3114};
3115
3116static const char * const scif5_groups[] = {
3117 "scif5_data_a",
3118 "scif5_clk_a",
3119 "scif5_data_b",
3120 "scif5_clk_b",
3121};
3122
3123static const char * const scif_clk_groups[] = {
3124 "scif_clk_a",
3125 "scif_clk_b",
490e687e
JM		 3126};
3127
0d75f8da
TK		 3128static const char * const usb0_groups[] = {
3129 "usb0",
3130};
3131
3132static const char * const usb1_groups[] = {
3133 "usb1",
3134};
3135
c490b28f
TK		 3136static const char * const usb30_groups[] = {
3137 "usb30",
3138};
3139
490e687e 3140static const struct sh_pfc_function pinmux_functions[] = {
fa3e8b71 3141 SH_PFC_FUNCTION(avb),
a8ab4f2b 3142 SH_PFC_FUNCTION(intc_ex),
2c77aa3d
TK		 3143 SH_PFC_FUNCTION(msiof0),
3144 SH_PFC_FUNCTION(msiof1),
3145 SH_PFC_FUNCTION(msiof2),
3146 SH_PFC_FUNCTION(msiof3),
54b7f2da
TK		 3147 SH_PFC_FUNCTION(pwm0),
3148 SH_PFC_FUNCTION(pwm1),
3149 SH_PFC_FUNCTION(pwm2),
3150 SH_PFC_FUNCTION(pwm3),
3151 SH_PFC_FUNCTION(pwm4),
3152 SH_PFC_FUNCTION(pwm5),
3153 SH_PFC_FUNCTION(pwm6),
58cfd7f3
JM		 3154 SH_PFC_FUNCTION(scif0),
3155 SH_PFC_FUNCTION(scif1),
3156 SH_PFC_FUNCTION(scif2),
3157 SH_PFC_FUNCTION(scif3),
3158 SH_PFC_FUNCTION(scif4),
3159 SH_PFC_FUNCTION(scif5),
3160 SH_PFC_FUNCTION(scif_clk),
0d75f8da
TK		 3161 SH_PFC_FUNCTION(usb0),
3162 SH_PFC_FUNCTION(usb1),
c490b28f 3163 SH_PFC_FUNCTION(usb30),
490e687e
JM		 3164};
3165
3166static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3167#define F_(x, y) FN_##y
3168#define FM(x) FN_##x
3169 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
3170 0, 0,
3171 0, 0,
3172 0, 0,
3173 0, 0,
3174 0, 0,
3175 0, 0,
3176 0, 0,
3177 0, 0,
3178 0, 0,
3179 0, 0,
3180 0, 0,
3181 0, 0,
3182 0, 0,
3183 0, 0,
3184 0, 0,
3185 0, 0,
3186 GP_0_15_FN, GPSR0_15,
3187 GP_0_14_FN, GPSR0_14,
3188 GP_0_13_FN, GPSR0_13,
3189 GP_0_12_FN, GPSR0_12,
3190 GP_0_11_FN, GPSR0_11,
3191 GP_0_10_FN, GPSR0_10,
3192 GP_0_9_FN, GPSR0_9,
3193 GP_0_8_FN, GPSR0_8,
3194 GP_0_7_FN, GPSR0_7,
3195 GP_0_6_FN, GPSR0_6,
3196 GP_0_5_FN, GPSR0_5,
3197 GP_0_4_FN, GPSR0_4,
3198 GP_0_3_FN, GPSR0_3,
3199 GP_0_2_FN, GPSR0_2,
3200 GP_0_1_FN, GPSR0_1,
3201 GP_0_0_FN, GPSR0_0, }
3202 },
3203 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
3204 0, 0,
3205 0, 0,
3206 0, 0,
3207 GP_1_28_FN, GPSR1_28,
3208 GP_1_27_FN, GPSR1_27,
3209 GP_1_26_FN, GPSR1_26,
3210 GP_1_25_FN, GPSR1_25,
3211 GP_1_24_FN, GPSR1_24,
3212 GP_1_23_FN, GPSR1_23,
3213 GP_1_22_FN, GPSR1_22,
3214 GP_1_21_FN, GPSR1_21,
3215 GP_1_20_FN, GPSR1_20,
3216 GP_1_19_FN, GPSR1_19,
3217 GP_1_18_FN, GPSR1_18,
3218 GP_1_17_FN, GPSR1_17,
3219 GP_1_16_FN, GPSR1_16,
3220 GP_1_15_FN, GPSR1_15,
3221 GP_1_14_FN, GPSR1_14,
3222 GP_1_13_FN, GPSR1_13,
3223 GP_1_12_FN, GPSR1_12,
3224 GP_1_11_FN, GPSR1_11,
3225 GP_1_10_FN, GPSR1_10,
3226 GP_1_9_FN, GPSR1_9,
3227 GP_1_8_FN, GPSR1_8,
3228 GP_1_7_FN, GPSR1_7,
3229 GP_1_6_FN, GPSR1_6,
3230 GP_1_5_FN, GPSR1_5,
3231 GP_1_4_FN, GPSR1_4,
3232 GP_1_3_FN, GPSR1_3,
3233 GP_1_2_FN, GPSR1_2,
3234 GP_1_1_FN, GPSR1_1,
3235 GP_1_0_FN, GPSR1_0, }
3236 },
3237 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
3238 0, 0,
3239 0, 0,
3240 0, 0,
3241 0, 0,
3242 0, 0,
3243 0, 0,
3244 0, 0,
3245 0, 0,
3246 0, 0,
3247 0, 0,
3248 0, 0,
3249 0, 0,
3250 0, 0,
3251 0, 0,
3252 0, 0,
3253 0, 0,
3254 0, 0,
3255 GP_2_14_FN, GPSR2_14,
3256 GP_2_13_FN, GPSR2_13,
3257 GP_2_12_FN, GPSR2_12,
3258 GP_2_11_FN, GPSR2_11,
3259 GP_2_10_FN, GPSR2_10,
3260 GP_2_9_FN, GPSR2_9,
3261 GP_2_8_FN, GPSR2_8,
3262 GP_2_7_FN, GPSR2_7,
3263 GP_2_6_FN, GPSR2_6,
3264 GP_2_5_FN, GPSR2_5,
3265 GP_2_4_FN, GPSR2_4,
3266 GP_2_3_FN, GPSR2_3,
3267 GP_2_2_FN, GPSR2_2,
3268 GP_2_1_FN, GPSR2_1,
3269 GP_2_0_FN, GPSR2_0, }
3270 },
3271 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
3272 0, 0,
3273 0, 0,
3274 0, 0,
3275 0, 0,
3276 0, 0,
3277 0, 0,
3278 0, 0,
3279 0, 0,
3280 0, 0,
3281 0, 0,
3282 0, 0,
3283 0, 0,
3284 0, 0,
3285 0, 0,
3286 0, 0,
3287 0, 0,
3288 GP_3_15_FN, GPSR3_15,
3289 GP_3_14_FN, GPSR3_14,
3290 GP_3_13_FN, GPSR3_13,
3291 GP_3_12_FN, GPSR3_12,
3292 GP_3_11_FN, GPSR3_11,
3293 GP_3_10_FN, GPSR3_10,
3294 GP_3_9_FN, GPSR3_9,
3295 GP_3_8_FN, GPSR3_8,
3296 GP_3_7_FN, GPSR3_7,
3297 GP_3_6_FN, GPSR3_6,
3298 GP_3_5_FN, GPSR3_5,
3299 GP_3_4_FN, GPSR3_4,
3300 GP_3_3_FN, GPSR3_3,
3301 GP_3_2_FN, GPSR3_2,
3302 GP_3_1_FN, GPSR3_1,
3303 GP_3_0_FN, GPSR3_0, }
3304 },
3305 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
3306 0, 0,
3307 0, 0,
3308 0, 0,
3309 0, 0,
3310 0, 0,
3311 0, 0,
3312 0, 0,
3313 0, 0,
3314 0, 0,
3315 0, 0,
3316 0, 0,
3317 0, 0,
3318 0, 0,
3319 0, 0,
3320 GP_4_17_FN, GPSR4_17,
3321 GP_4_16_FN, GPSR4_16,
3322 GP_4_15_FN, GPSR4_15,
3323 GP_4_14_FN, GPSR4_14,
3324 GP_4_13_FN, GPSR4_13,
3325 GP_4_12_FN, GPSR4_12,
3326 GP_4_11_FN, GPSR4_11,
3327 GP_4_10_FN, GPSR4_10,
3328 GP_4_9_FN, GPSR4_9,
3329 GP_4_8_FN, GPSR4_8,
3330 GP_4_7_FN, GPSR4_7,
3331 GP_4_6_FN, GPSR4_6,
3332 GP_4_5_FN, GPSR4_5,
3333 GP_4_4_FN, GPSR4_4,
3334 GP_4_3_FN, GPSR4_3,
3335 GP_4_2_FN, GPSR4_2,
3336 GP_4_1_FN, GPSR4_1,
3337 GP_4_0_FN, GPSR4_0, }
3338 },
3339 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
3340 0, 0,
3341 0, 0,
3342 0, 0,
3343 0, 0,
3344 0, 0,
3345 0, 0,
3346 GP_5_25_FN, GPSR5_25,
3347 GP_5_24_FN, GPSR5_24,
3348 GP_5_23_FN, GPSR5_23,
3349 GP_5_22_FN, GPSR5_22,
3350 GP_5_21_FN, GPSR5_21,
3351 GP_5_20_FN, GPSR5_20,
3352 GP_5_19_FN, GPSR5_19,
3353 GP_5_18_FN, GPSR5_18,
3354 GP_5_17_FN, GPSR5_17,
3355 GP_5_16_FN, GPSR5_16,
3356 GP_5_15_FN, GPSR5_15,
3357 GP_5_14_FN, GPSR5_14,
3358 GP_5_13_FN, GPSR5_13,
3359 GP_5_12_FN, GPSR5_12,
3360 GP_5_11_FN, GPSR5_11,
3361 GP_5_10_FN, GPSR5_10,
3362 GP_5_9_FN, GPSR5_9,
3363 GP_5_8_FN, GPSR5_8,
3364 GP_5_7_FN, GPSR5_7,
3365 GP_5_6_FN, GPSR5_6,
3366 GP_5_5_FN, GPSR5_5,
3367 GP_5_4_FN, GPSR5_4,
3368 GP_5_3_FN, GPSR5_3,
3369 GP_5_2_FN, GPSR5_2,
3370 GP_5_1_FN, GPSR5_1,
3371 GP_5_0_FN, GPSR5_0, }
3372 },
3373 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
3374 GP_6_31_FN, GPSR6_31,
3375 GP_6_30_FN, GPSR6_30,
3376 GP_6_29_FN, GPSR6_29,
3377 GP_6_28_FN, GPSR6_28,
3378 GP_6_27_FN, GPSR6_27,
3379 GP_6_26_FN, GPSR6_26,
3380 GP_6_25_FN, GPSR6_25,
3381 GP_6_24_FN, GPSR6_24,
3382 GP_6_23_FN, GPSR6_23,
3383 GP_6_22_FN, GPSR6_22,
3384 GP_6_21_FN, GPSR6_21,
3385 GP_6_20_FN, GPSR6_20,
3386 GP_6_19_FN, GPSR6_19,
3387 GP_6_18_FN, GPSR6_18,
3388 GP_6_17_FN, GPSR6_17,
3389 GP_6_16_FN, GPSR6_16,
3390 GP_6_15_FN, GPSR6_15,
3391 GP_6_14_FN, GPSR6_14,
3392 GP_6_13_FN, GPSR6_13,
3393 GP_6_12_FN, GPSR6_12,
3394 GP_6_11_FN, GPSR6_11,
3395 GP_6_10_FN, GPSR6_10,
3396 GP_6_9_FN, GPSR6_9,
3397 GP_6_8_FN, GPSR6_8,
3398 GP_6_7_FN, GPSR6_7,
3399 GP_6_6_FN, GPSR6_6,
3400 GP_6_5_FN, GPSR6_5,
3401 GP_6_4_FN, GPSR6_4,
3402 GP_6_3_FN, GPSR6_3,
3403 GP_6_2_FN, GPSR6_2,
3404 GP_6_1_FN, GPSR6_1,
3405 GP_6_0_FN, GPSR6_0, }
3406 },
3407 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
3408 0, 0,
3409 0, 0,
3410 0, 0,
3411 0, 0,
3412 0, 0,
3413 0, 0,
3414 0, 0,
3415 0, 0,
3416 0, 0,
3417 0, 0,
3418 0, 0,
3419 0, 0,
3420 0, 0,
3421 0, 0,
3422 0, 0,
3423 0, 0,
3424 0, 0,
3425 0, 0,
3426 0, 0,
3427 0, 0,
3428 0, 0,
3429 0, 0,
3430 0, 0,
3431 0, 0,
3432 0, 0,
3433 0, 0,
3434 0, 0,
3435 0, 0,
3436 GP_7_3_FN, GPSR7_3,
3437 GP_7_2_FN, GPSR7_2,
3438 GP_7_1_FN, GPSR7_1,
3439 GP_7_0_FN, GPSR7_0, }
3440 },
3441#undef F_
3442#undef FM
3443
3444#define F_(x, y) x,
3445#define FM(x) FN_##x,
3446 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
3447 IP0_31_28
3448 IP0_27_24
3449 IP0_23_20
3450 IP0_19_16
3451 IP0_15_12
3452 IP0_11_8
3453 IP0_7_4
3454 IP0_3_0 }
3455 },
3456 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
3457 IP1_31_28
3458 IP1_27_24
3459 IP1_23_20
3460 IP1_19_16
3461 IP1_15_12
3462 IP1_11_8
3463 IP1_7_4
3464 IP1_3_0 }
3465 },
3466 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
3467 IP2_31_28
3468 IP2_27_24
3469 IP2_23_20
3470 IP2_19_16
3471 IP2_15_12
3472 IP2_11_8
3473 IP2_7_4
3474 IP2_3_0 }
3475 },
3476 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
3477 IP3_31_28
3478 IP3_27_24
3479 IP3_23_20
3480 IP3_19_16
3481 IP3_15_12
3482 IP3_11_8
3483 IP3_7_4
3484 IP3_3_0 }
3485 },
3486 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
3487 IP4_31_28
3488 IP4_27_24
3489 IP4_23_20
3490 IP4_19_16
3491 IP4_15_12
3492 IP4_11_8
3493 IP4_7_4
3494 IP4_3_0 }
3495 },
3496 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
3497 IP5_31_28
3498 IP5_27_24
3499 IP5_23_20
3500 IP5_19_16
3501 IP5_15_12
3502 IP5_11_8
3503 IP5_7_4
3504 IP5_3_0 }
3505 },
3506 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
3507 IP6_31_28
3508 IP6_27_24
3509 IP6_23_20
3510 IP6_19_16
3511 IP6_15_12
3512 IP6_11_8
3513 IP6_7_4
3514 IP6_3_0 }
3515 },
3516 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
3517 IP7_31_28
3518 IP7_27_24
3519 IP7_23_20
3520 IP7_19_16
3521 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3522 IP7_11_8
3523 IP7_7_4
3524 IP7_3_0 }
3525 },
3526 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
3527 IP8_31_28
3528 IP8_27_24
3529 IP8_23_20
3530 IP8_19_16
3531 IP8_15_12
3532 IP8_11_8
3533 IP8_7_4
3534 IP8_3_0 }
3535 },
3536 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
3537 IP9_31_28
3538 IP9_27_24
3539 IP9_23_20
3540 IP9_19_16
3541 IP9_15_12
3542 IP9_11_8
3543 IP9_7_4
3544 IP9_3_0 }
3545 },
3546 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
3547 IP10_31_28
3548 IP10_27_24
3549 IP10_23_20
3550 IP10_19_16
3551 IP10_15_12
3552 IP10_11_8
3553 IP10_7_4
3554 IP10_3_0 }
3555 },
3556 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
3557 IP11_31_28
3558 IP11_27_24
3559 IP11_23_20
3560 IP11_19_16
3561 IP11_15_12
3562 IP11_11_8
3563 IP11_7_4
3564 IP11_3_0 }
3565 },
3566 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
3567 IP12_31_28
3568 IP12_27_24
3569 IP12_23_20
3570 IP12_19_16
3571 IP12_15_12
3572 IP12_11_8
3573 IP12_7_4
3574 IP12_3_0 }
3575 },
3576 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
3577 IP13_31_28
3578 IP13_27_24
3579 IP13_23_20
3580 IP13_19_16
3581 IP13_15_12
3582 IP13_11_8
3583 IP13_7_4
3584 IP13_3_0 }
3585 },
3586 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
3587 IP14_31_28
3588 IP14_27_24
3589 IP14_23_20
3590 IP14_19_16
3591 IP14_15_12
3592 IP14_11_8
3593 IP14_7_4
3594 IP14_3_0 }
3595 },
3596 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
3597 IP15_31_28
3598 IP15_27_24
3599 IP15_23_20
3600 IP15_19_16
3601 IP15_15_12
3602 IP15_11_8
3603 IP15_7_4
3604 IP15_3_0 }
3605 },
3606 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
3607 IP16_31_28
3608 IP16_27_24
3609 IP16_23_20
3610 IP16_19_16
3611 IP16_15_12
3612 IP16_11_8
3613 IP16_7_4
3614 IP16_3_0 }
3615 },
3616 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
3617 IP17_31_28
3618 IP17_27_24
3619 IP17_23_20
3620 IP17_19_16
3621 IP17_15_12
3622 IP17_11_8
3623 IP17_7_4
3624 IP17_3_0 }
3625 },
3626 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
3627 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3628 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3629 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3630 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3631 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3632 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3633 IP18_7_4
3634 IP18_3_0 }
3635 },
3636#undef F_
3637#undef FM
3638
3639#define F_(x, y) x,
3640#define FM(x) FN_##x,
3641 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
3642 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
3643 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
3644 MOD_SEL0_31_30_29
3645 MOD_SEL0_28_27
3646 MOD_SEL0_26_25_24
3647 MOD_SEL0_23
3648 MOD_SEL0_22
3649 MOD_SEL0_21
3650 MOD_SEL0_20
3651 MOD_SEL0_19
3652 MOD_SEL0_18_17
3653 MOD_SEL0_16
3654 0, 0, /* RESERVED 15 */
3655 MOD_SEL0_14_13
3656 MOD_SEL0_12
3657 MOD_SEL0_11
3658 MOD_SEL0_10
3659 MOD_SEL0_9_8
3660 MOD_SEL0_7_6
3661 MOD_SEL0_5
3662 MOD_SEL0_4_3
3663 /* RESERVED 2, 1, 0 */
3664 0, 0, 0, 0, 0, 0, 0, 0 }
3665 },
3666 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
3667 2, 3, 1, 2, 3, 1, 1, 2, 1,
3668 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
3669 MOD_SEL1_31_30
3670 MOD_SEL1_29_28_27
3671 MOD_SEL1_26
3672 MOD_SEL1_25_24
3673 MOD_SEL1_23_22_21
3674 MOD_SEL1_20
3675 MOD_SEL1_19
3676 MOD_SEL1_18_17
3677 MOD_SEL1_16
3678 MOD_SEL1_15_14
3679 MOD_SEL1_13
3680 MOD_SEL1_12
3681 MOD_SEL1_11
3682 MOD_SEL1_10
3683 MOD_SEL1_9
3684 0, 0, 0, 0, /* RESERVED 8, 7 */
3685 MOD_SEL1_6
3686 MOD_SEL1_5
3687 MOD_SEL1_4
3688 MOD_SEL1_3
3689 MOD_SEL1_2
3690 MOD_SEL1_1
3691 MOD_SEL1_0 }
3692 },
3693 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
3694 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
3695 4, 4, 4, 3, 1) {
3696 MOD_SEL2_31
3697 MOD_SEL2_30
3698 MOD_SEL2_29
3699 MOD_SEL2_28_27
3700 MOD_SEL2_26
3701 MOD_SEL2_25_24_23
3702 MOD_SEL2_22
3703 MOD_SEL2_21
3704 MOD_SEL2_20
3705 MOD_SEL2_19
3706 MOD_SEL2_18
3707 MOD_SEL2_17
3708 /* RESERVED 16 */
3709 0, 0,
3710 /* RESERVED 15, 14, 13, 12 */
3711 0, 0, 0, 0, 0, 0, 0, 0,
3712 0, 0, 0, 0, 0, 0, 0, 0,
3713 /* RESERVED 11, 10, 9, 8 */
3714 0, 0, 0, 0, 0, 0, 0, 0,
3715 0, 0, 0, 0, 0, 0, 0, 0,
3716 /* RESERVED 7, 6, 5, 4 */
3717 0, 0, 0, 0, 0, 0, 0, 0,
3718 0, 0, 0, 0, 0, 0, 0, 0,
3719 /* RESERVED 3, 2, 1 */
3720 0, 0, 0, 0, 0, 0, 0, 0,
3721 MOD_SEL2_0 }
3722 },
3723 { },
3724};
3725
3726static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3727 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
3728 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
3729 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
3730 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
3731 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
3732 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
3733 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
3734 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
3735 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
3736 } },
3737 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
3738 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
3739 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
3740 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
3741 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
3742 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
3743 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
3744 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
3745 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
3746 } },
3747 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
3748 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
3749 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
3750 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
3751 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
3752 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
3753 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
3754 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
3755 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
3756 } },
3757 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
3758 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
3759 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
3760 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
3761 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
3762 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
3763 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
3764 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
3765 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
3766 } },
3767 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
3768 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
3769 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
3770 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
3771 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
3772 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
3773 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
3774 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
3775 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
3776 } },
3777 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
3778 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
3779 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
3780 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
3781 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
3782 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
3783 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
3784 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
3785 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
3786 } },
3787 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
3788 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
3789 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
3790 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
3791 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
3792 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
3793 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
3794 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
3795 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
3796 } },
3797 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
3798 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
3799 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
3800 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
3801 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
3802 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
3803 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
3804 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
3805 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
3806 } },
3807 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
3808 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
3809 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
3810 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
3811 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
3812 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
3813 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
3814 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
3815 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
3816 } },
3817 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
3818 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
3819 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
3820 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
3821 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
3822 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
3823 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
3824 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
3825 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
3826 } },
3827 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
3828 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
3829 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
3830 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
3831 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
3832 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
3833 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
3834 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
3835 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
3836 } },
3837 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
3838 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
3839 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
3840 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
3841 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
3842 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
3843 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
3844 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
3845 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
3846 } },
3847 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
3848 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN3 */
3849 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
3850 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
3851 } },
3852 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
3853 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
3854 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
3855 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
3856 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
3857 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
3858 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
3859 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
3860 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
3861 } },
3862 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
3863 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
3864 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
3865 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
3866 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
3867 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
3868 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
3869 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
3870 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
3871 } },
3872 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
3873 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
3874 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
3875 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
3876 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
3877 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
3878 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
3879 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
3880 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
3881 } },
3882 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
3883 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
3884 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
3885 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
3886 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
3887 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
3888 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
3889 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
3890 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
3891 } },
3892 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
3893 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
3894 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
3895 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
3896 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
3897 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
3898 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
3899 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
3900 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
3901 } },
3902 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
3903 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
3904 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
3905 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
3906 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
3907 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
3908 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
3909 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
3910 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
3911 } },
3912 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
3913 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
3914 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
3915 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
3916 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
3917 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
3918 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
3919 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
3920 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
3921 } },
3922 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
3923 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
3924 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
3925 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
3926 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
3927 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
3928 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
3929 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
3930 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
3931 } },
3932 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
3933 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
3934 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
3935 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
3936 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
3937 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
3938 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
3939 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
3940 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
3941 } },
3942 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
3943 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
3944 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
3945 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
3946 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
3947 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
3948 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
3949 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
3950 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
3951 } },
3952 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
3953 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
3954 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
3955 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
3956 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
3957 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
3958 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
3959 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
3960 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
3961 } },
3962 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
3963 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
3964 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
3965 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
3966 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
3967 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
3968 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
3969 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
3970 } },
3971 { },
3972};
3973
3974enum ioctrl_regs {
3975 POCCTRL,
3976};
3977
3978static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
3979 [POCCTRL] = { 0xe6060380, },
3980 { /* sentinel */ },
3981};
3982
3983static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
3984{
3985 int bit = -EINVAL;
3986
3987 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
3988
3989 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
3990 bit = pin & 0x1f;
3991
3992 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
3993 bit = (pin & 0x1f) + 12;
3994
3995 return bit;
3996}
3997
3998static const struct pinmux_bias_reg pinmux_bias_regs[] = {
3999 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
4000 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
4001 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
4002 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
4003 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
4004 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
4005 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
4006 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
4007 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
4008 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
4009 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
4010 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
4011 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
4012 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
4013 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
4014 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
4015 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
4016 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
4017 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
4018 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
4019 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
4020 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
4021 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
4022 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
4023 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
4024 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
4025 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
4026 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
4027 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
4028 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
4029 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
4030 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
4031 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
4032 } },
4033 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
4034 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
4035 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
4036 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
4037 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
4038 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
4039 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
4040 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
4041 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
4042 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
4043 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
4044 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
4045 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
4046 [12] = RCAR_GP_PIN(1, 0), /* A0 */
4047 [13] = RCAR_GP_PIN(1, 1), /* A1 */
4048 [14] = RCAR_GP_PIN(1, 2), /* A2 */
4049 [15] = RCAR_GP_PIN(1, 3), /* A3 */
4050 [16] = RCAR_GP_PIN(1, 4), /* A4 */
4051 [17] = RCAR_GP_PIN(1, 5), /* A5 */
4052 [18] = RCAR_GP_PIN(1, 6), /* A6 */
4053 [19] = RCAR_GP_PIN(1, 7), /* A7 */
4054 [20] = RCAR_GP_PIN(1, 8), /* A8 */
4055 [21] = RCAR_GP_PIN(1, 9), /* A9 */
4056 [22] = RCAR_GP_PIN(1, 10), /* A10 */
4057 [23] = RCAR_GP_PIN(1, 11), /* A11 */
4058 [24] = RCAR_GP_PIN(1, 12), /* A12 */
4059 [25] = RCAR_GP_PIN(1, 13), /* A13 */
4060 [26] = RCAR_GP_PIN(1, 14), /* A14 */
4061 [27] = RCAR_GP_PIN(1, 15), /* A15 */
4062 [28] = RCAR_GP_PIN(1, 16), /* A16 */
4063 [29] = RCAR_GP_PIN(1, 17), /* A17 */
4064 [30] = RCAR_GP_PIN(1, 18), /* A18 */
4065 [31] = RCAR_GP_PIN(1, 19), /* A19 */
4066 } },
4067 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
4068 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
4069 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
4070 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
4071 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
4072 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
4073 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
4074 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
4075 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
4076 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
4077 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
4078 [10] = RCAR_GP_PIN(0, 0), /* D0 */
4079 [11] = RCAR_GP_PIN(0, 1), /* D1 */
4080 [12] = RCAR_GP_PIN(0, 2), /* D2 */
4081 [13] = RCAR_GP_PIN(0, 3), /* D3 */
4082 [14] = RCAR_GP_PIN(0, 4), /* D4 */
4083 [15] = RCAR_GP_PIN(0, 5), /* D5 */
4084 [16] = RCAR_GP_PIN(0, 6), /* D6 */
4085 [17] = RCAR_GP_PIN(0, 7), /* D7 */
4086 [18] = RCAR_GP_PIN(0, 8), /* D8 */
4087 [19] = RCAR_GP_PIN(0, 9), /* D9 */
4088 [20] = RCAR_GP_PIN(0, 10), /* D10 */
4089 [21] = RCAR_GP_PIN(0, 11), /* D11 */
4090 [22] = RCAR_GP_PIN(0, 12), /* D12 */
4091 [23] = RCAR_GP_PIN(0, 13), /* D13 */
4092 [24] = RCAR_GP_PIN(0, 14), /* D14 */
4093 [25] = RCAR_GP_PIN(0, 15), /* D15 */
4094 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
4095 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
4096 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
4097 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
4098 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
4099 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
4100 } },
4101 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
4102 [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
4103 [ 1] = PIN_NONE,
4104 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
4105 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
4106 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
4107 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
4108 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
4109 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
4110 [ 8] = PIN_NONE,
4111 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
4112 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
4113 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
4114 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
4115 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
4116 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
4117 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
4118 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
4119 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
4120 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
4121 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
4122 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
4123 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
4124 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
4125 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
4126 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
4127 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
4128 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
4129 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
4130 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
4131 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
4132 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
4133 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
4134 } },
4135 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
4136 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
4137 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
4138 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
4139 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
4140 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
4141 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
4142 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
4143 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
4144 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
4145 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
4146 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
4147 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
4148 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
4149 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
4150 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
4151 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
4152 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
4153 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
4154 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
4155 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
4156 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
4157 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
4158 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
4159 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
4160 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
4161 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
4162 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
4163 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
4164 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
4165 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
4166 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
4167 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
4168 } },
4169 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
4170 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
4171 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
4172 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
4173 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
4174 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
4175 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
4176 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
4177 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
4178 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
4179 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
4180 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
4181 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
4182 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
4183 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
4184 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
4185 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
4186 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
4187 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
4188 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
4189 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
4190 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
4191 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
4192 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
4193 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
4194 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
4195 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
4196 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
4197 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
4198 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
4199 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
4200 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
4201 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
4202 } },
4203 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
4204 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
4205 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
4206 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
4207 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
4208 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
4209 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
4210 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
4211 [ 7] = PIN_NONE,
4212 [ 8] = PIN_NONE,
4213 [ 9] = PIN_NONE,
4214 [10] = PIN_NONE,
4215 [11] = PIN_NONE,
4216 [12] = PIN_NONE,
4217 [13] = PIN_NONE,
4218 [14] = PIN_NONE,
4219 [15] = PIN_NONE,
4220 [16] = PIN_NONE,
4221 [17] = PIN_NONE,
4222 [18] = PIN_NONE,
4223 [19] = PIN_NONE,
4224 [20] = PIN_NONE,
4225 [21] = PIN_NONE,
4226 [22] = PIN_NONE,
4227 [23] = PIN_NONE,
4228 [24] = PIN_NONE,
4229 [25] = PIN_NONE,
4230 [26] = PIN_NONE,
4231 [27] = PIN_NONE,
4232 [28] = PIN_NONE,
4233 [29] = PIN_NONE,
4234 [30] = PIN_NONE,
4235 [31] = PIN_NONE,
4236 } },
4237 { /* sentinel */ },
4238};
4239
4240static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
4241 unsigned int pin)
4242{
4243 const struct pinmux_bias_reg *reg;
4244 unsigned int bit;
4245
4246 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
4247 if (!reg)
4248 return PIN_CONFIG_BIAS_DISABLE;
4249
4250 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
4251 return PIN_CONFIG_BIAS_DISABLE;
4252 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
4253 return PIN_CONFIG_BIAS_PULL_UP;
4254 else
4255 return PIN_CONFIG_BIAS_PULL_DOWN;
4256}
4257
4258static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
4259 unsigned int bias)
4260{
4261 const struct pinmux_bias_reg *reg;
4262 u32 enable, updown;
4263 unsigned int bit;
4264
4265 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
4266 if (!reg)
4267 return;
4268
4269 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
4270 if (bias != PIN_CONFIG_BIAS_DISABLE)
4271 enable |= BIT(bit);
4272
4273 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
4274 if (bias == PIN_CONFIG_BIAS_PULL_UP)
4275 updown |= BIT(bit);
4276
4277 sh_pfc_write(pfc, reg->pud, updown);
4278 sh_pfc_write(pfc, reg->puen, enable);
4279}
4280
4281static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
4282 .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
4283 .get_bias = r8a77965_pinmux_get_bias,
4284 .set_bias = r8a77965_pinmux_set_bias,
4285};
4286
4287const struct sh_pfc_soc_info r8a77965_pinmux_info = {
4288 .name = "r8a77965_pfc",
4289 .ops = &r8a77965_pinmux_ops,
4290 .unlock_reg = 0xe6060000, /* PMMR */
4291
4292 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4293
4294 .pins = pinmux_pins,
4295 .nr_pins = ARRAY_SIZE(pinmux_pins),
4296 .groups = pinmux_groups,
4297 .nr_groups = ARRAY_SIZE(pinmux_groups),
4298 .functions = pinmux_functions,
4299 .nr_functions = ARRAY_SIZE(pinmux_functions),
4300
4301 .cfg_regs = pinmux_config_regs,
4302 .drive_regs = pinmux_drive_regs,
4303 .bias_regs = pinmux_bias_regs,
4304 .ioctrl_regs = pinmux_ioctrl_regs,
4305
4306 .pinmux_data = pinmux_data,
4307 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
4308};
Linux 6.x block layer and io_uring tree(s)