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Merge tag 'mm-nonmm-stable-2024-05-22-17-30' of git://git.kernel.org/pub/scm/linux...
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
fe45e630 12#include <linux/blk-integrity.h>
ff5350a8 13#include <linux/dmi.h>
b60503ba
MW		 14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
99722c8a 17#include <linux/kstrtox.h>
dc90f084 18#include <linux/memremap.h>
b60503ba
MW		 19#include <linux/mm.h>
20#include <linux/module.h>
77bf25ea 21#include <linux/mutex.h>
d0877473 22#include <linux/once.h>
b60503ba 23#include <linux/pci.h>
d916b1be 24#include <linux/suspend.h>
e1e5e564 25#include <linux/t10-pi.h>
b60503ba 26#include <linux/types.h>
2f8e2c87 27#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 28#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 29#include <linux/sed-opal.h>
0f238ff5 30#include <linux/pci-p2pdma.h>
797a796a 31
604c01d5 32#include "trace.h"
f11bb3e2
CH		 33#include "nvme.h"
34
c1e0cc7e 35#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 36#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 37
84173423 38#define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 39
943e942e
JA		 40/*
41 * These can be higher, but we need to ensure that any command doesn't
42 * require an sg allocation that needs more than a page of data.
43 */
7846c1b5
KB		 44#define NVME_MAX_KB_SZ 8192
45#define NVME_MAX_SEGS 128
46#define NVME_MAX_NR_ALLOCATIONS 5
943e942e 47
58ffacb5 48static int use_threaded_interrupts;
2e21e445 49module_param(use_threaded_interrupts, int, 0444);
58ffacb5 50
8ffaadf7 51static bool use_cmb_sqes = true;
69f4eb9f 52module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 53MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54
87ad72a5
CH		 55static unsigned int max_host_mem_size_mb = 128;
56module_param(max_host_mem_size_mb, uint, 0444);
57MODULE_PARM_DESC(max_host_mem_size_mb,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 59
a7a7cbe3
CK		 60static unsigned int sgl_threshold = SZ_32K;
61module_param(sgl_threshold, uint, 0644);
62MODULE_PARM_DESC(sgl_threshold,
63 "Use SGLs when average request segment size is larger or equal to "
64 "this size. Use 0 to disable SGLs.");
65
27453b45
SG		 66#define NVME_PCI_MIN_QUEUE_SIZE 2
67#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 68static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
61f3b896 71 .get = param_get_uint,
b27c1e68 72};
73
61f3b896 74static unsigned int io_queue_depth = 1024;
b27c1e68 75module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 76MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 77
9c9e76d5
WZ		 78static int io_queue_count_set(const char *val, const struct kernel_param *kp)
79{
80 unsigned int n;
81 int ret;
82
83 ret = kstrtouint(val, 10, &n);
84 if (ret != 0 || n > num_possible_cpus())
85 return -EINVAL;
86 return param_set_uint(val, kp);
87}
88
89static const struct kernel_param_ops io_queue_count_ops = {
90 .set = io_queue_count_set,
91 .get = param_get_uint,
92};
93
3f68baf7 94static unsigned int write_queues;
9c9e76d5 95module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 96MODULE_PARM_DESC(write_queues,
97 "Number of queues to use for writes. If not set, reads and writes "
98 "will share a queue set.");
99
3f68baf7 100static unsigned int poll_queues;
9c9e76d5 101module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 102MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
103
df4f9bc4
DB		 104static bool noacpi;
105module_param(noacpi, bool, 0444);
106MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
107
1c63dc66
CH		 108struct nvme_dev;
109struct nvme_queue;
b3fffdef 110
a5cdb68c 111static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
7d879c90 112static void nvme_delete_io_queues(struct nvme_dev *dev);
e917a849 113static void nvme_update_attrs(struct nvme_dev *dev);
d4b4ff8e 114
1c63dc66
CH		 115/*
116 * Represents an NVM Express device. Each nvme_dev is a PCI function.
117 */
118struct nvme_dev {
147b27e4 119 struct nvme_queue *queues;
1c63dc66
CH		 120 struct blk_mq_tag_set tagset;
121 struct blk_mq_tag_set admin_tagset;
122 u32 __iomem *dbs;
123 struct device *dev;
124 struct dma_pool *prp_page_pool;
125 struct dma_pool *prp_small_pool;
1c63dc66
CH		 126 unsigned online_queues;
127 unsigned max_qid;
e20ba6e1 128 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 129 unsigned int num_vecs;
7442ddce 130 u32 q_depth;
c1e0cc7e 131 int io_sqes;
1c63dc66 132 u32 db_stride;
1c63dc66 133 void __iomem *bar;
97f6ef64 134 unsigned long bar_mapped_size;
77bf25ea 135 struct mutex shutdown_lock;
1c63dc66 136 bool subsystem;
1c63dc66 137 u64 cmb_size;
0f238ff5 138 bool cmb_use_sqes;
1c63dc66 139 u32 cmbsz;
202021c1 140 u32 cmbloc;
1c63dc66 141 struct nvme_ctrl ctrl;
d916b1be 142 u32 last_ps;
a5df5e79 143 bool hmb;
87ad72a5 144
943e942e
JA		 145 mempool_t *iod_mempool;
146
87ad72a5 147 /* shadow doorbell buffer support: */
b5f96cb7 148 __le32 *dbbuf_dbs;
f9f38e33 149 dma_addr_t dbbuf_dbs_dma_addr;
b5f96cb7 150 __le32 *dbbuf_eis;
f9f38e33 151 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 152
153 /* host memory buffer support: */
154 u64 host_mem_size;
155 u32 nr_host_mem_descs;
4033f35d 156 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 157 struct nvme_host_mem_buf_desc *host_mem_descs;
158 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 159 unsigned int nr_allocated_queues;
160 unsigned int nr_write_queues;
161 unsigned int nr_poll_queues;
4d115420 162};
1fa6aead 163
b27c1e68 164static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
165{
27453b45
SG		 166 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
167 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 168}
169
f9f38e33
HK		 170static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171{
172 return qid * 2 * stride;
173}
174
175static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176{
177 return (qid * 2 + 1) * stride;
178}
179
1c63dc66
CH		 180static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181{
182 return container_of(ctrl, struct nvme_dev, ctrl);
183}
184
b60503ba
MW		 185/*
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
188 */
189struct nvme_queue {
091b6092 190 struct nvme_dev *dev;
1ab0cd69 191 spinlock_t sq_lock;
c1e0cc7e 192 void *sq_cmds;
3a7afd8e
CH		 193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 195 struct nvme_completion *cqes;
b60503ba
MW		 196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
b60503ba 198 u32 __iomem *q_db;
7442ddce 199 u32 q_depth;
7c349dde 200 u16 cq_vector;
b60503ba 201 u16 sq_tail;
38210800 202 u16 last_sq_tail;
b60503ba 203 u16 cq_head;
c30341dc 204 u16 qid;
e9539f47 205 u8 cq_phase;
c1e0cc7e 206 u8 sqes;
4e224106
CH		 207 unsigned long flags;
208#define NVMEQ_ENABLED 0
63223078 209#define NVMEQ_SQ_CMB 1
d1ed6aa1 210#define NVMEQ_DELETE_ERROR 2
7c349dde 211#define NVMEQ_POLLED 3
b5f96cb7
KJ		 212 __le32 *dbbuf_sq_db;
213 __le32 *dbbuf_cq_db;
214 __le32 *dbbuf_sq_ei;
215 __le32 *dbbuf_cq_ei;
d1ed6aa1 216 struct completion delete_done;
b60503ba
MW		 217};
218
7846c1b5
KB		 219union nvme_descriptor {
220 struct nvme_sgl_desc *sg_list;
221 __le64 *prp_list;
222};
223
71bd150c 224/*
9b048119
CH		 225 * The nvme_iod describes the data in an I/O.
226 *
227 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
228 * to the actual struct scatterlist.
71bd150c
CH		 229 */
230struct nvme_iod {
d49187e9 231 struct nvme_request req;
af7fae85 232 struct nvme_command cmd;
52da4f3f 233 bool aborted;
c372cdd1
KB		 234 s8 nr_allocations; /* PRP list pool allocations. 0 means small
235 pool in use */
dff824b2 236 unsigned int dma_len; /* length of single DMA segment mapping */
c4c22c52 237 dma_addr_t first_dma;
783b94bd 238 dma_addr_t meta_dma;
91fb2b60 239 struct sg_table sgt;
7846c1b5 240 union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS];
b60503ba
MW		 241};
242
2a5bcfdd 243static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 244{
2a5bcfdd 245 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 246}
247
65a54646 248static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
f9f38e33 249{
2a5bcfdd 250 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 251
65a54646
CH		 252 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
253 return;
254
58847f12
KB		 255 if (dev->dbbuf_dbs) {
256 /*
257 * Clear the dbbuf memory so the driver doesn't observe stale
258 * values from the previous instantiation.
259 */
260 memset(dev->dbbuf_dbs, 0, mem_size);
261 memset(dev->dbbuf_eis, 0, mem_size);
65a54646 262 return;
58847f12 263 }
f9f38e33
HK		 264
265 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
266 &dev->dbbuf_dbs_dma_addr,
267 GFP_KERNEL);
268 if (!dev->dbbuf_dbs)
65a54646 269 goto fail;
f9f38e33
HK		 270 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
271 &dev->dbbuf_eis_dma_addr,
272 GFP_KERNEL);
65a54646
CH		 273 if (!dev->dbbuf_eis)
274 goto fail_free_dbbuf_dbs;
275 return;
f9f38e33 276
65a54646
CH		 277fail_free_dbbuf_dbs:
278 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
279 dev->dbbuf_dbs_dma_addr);
280 dev->dbbuf_dbs = NULL;
281fail:
282 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
f9f38e33
HK		 283}
284
285static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
286{
2a5bcfdd 287 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 288
289 if (dev->dbbuf_dbs) {
290 dma_free_coherent(dev->dev, mem_size,
291 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
292 dev->dbbuf_dbs = NULL;
293 }
294 if (dev->dbbuf_eis) {
295 dma_free_coherent(dev->dev, mem_size,
296 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
297 dev->dbbuf_eis = NULL;
298 }
299}
300
301static void nvme_dbbuf_init(struct nvme_dev *dev,
302 struct nvme_queue *nvmeq, int qid)
303{
304 if (!dev->dbbuf_dbs || !qid)
305 return;
306
307 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
308 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
309 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
310 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
311}
312
0f0d2c87
MI		 313static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
314{
315 if (!nvmeq->qid)
316 return;
317
318 nvmeq->dbbuf_sq_db = NULL;
319 nvmeq->dbbuf_cq_db = NULL;
320 nvmeq->dbbuf_sq_ei = NULL;
321 nvmeq->dbbuf_cq_ei = NULL;
322}
323
f9f38e33
HK		 324static void nvme_dbbuf_set(struct nvme_dev *dev)
325{
f66e2804 326 struct nvme_command c = { };
0f0d2c87 327 unsigned int i;
f9f38e33
HK		 328
329 if (!dev->dbbuf_dbs)
330 return;
331
f9f38e33
HK		 332 c.dbbuf.opcode = nvme_admin_dbbuf;
333 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
334 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
335
336 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 337 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 338 /* Free memory and continue on */
339 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 340
341 for (i = 1; i <= dev->online_queues; i++)
342 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 343 }
344}
345
346static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
347{
348 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
349}
350
351/* Update dbbuf and return true if an MMIO is required */
b5f96cb7
KJ		 352static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
353 volatile __le32 *dbbuf_ei)
f9f38e33
HK		 354{
355 if (dbbuf_db) {
b5f96cb7 356 u16 old_value, event_idx;
f9f38e33
HK		 357
358 /*
359 * Ensure that the queue is written before updating
360 * the doorbell in memory
361 */
362 wmb();
363
b5f96cb7
KJ		 364 old_value = le32_to_cpu(*dbbuf_db);
365 *dbbuf_db = cpu_to_le32(value);
f9f38e33 366
f1ed3df2
MW		 367 /*
368 * Ensure that the doorbell is updated before reading the event
369 * index from memory. The controller needs to provide similar
370 * ordering to ensure the envent index is updated before reading
371 * the doorbell.
372 */
373 mb();
374
b5f96cb7
KJ		 375 event_idx = le32_to_cpu(*dbbuf_ei);
376 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
f9f38e33
HK		 377 return false;
378 }
379
380 return true;
b60503ba
MW		 381}
382
ac3dd5bd
JA		 383/*
384 * Will slightly overestimate the number of pages needed. This is OK
385 * as it only leads to a small amount of wasted memory for the lifetime of
386 * the I/O.
387 */
b13c6393 388static int nvme_pci_npages_prp(void)
ac3dd5bd 389{
c89a529e
KB		 390 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
391 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
84173423 392 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
ac3dd5bd
JA		 393}
394
a4aea562
MB		 395static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
396 unsigned int hctx_idx)
e85248e5 397{
0da7feaa 398 struct nvme_dev *dev = to_nvme_dev(data);
147b27e4 399 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 400
42483228
KB		 401 WARN_ON(hctx_idx != 0);
402 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 403
a4aea562
MB		 404 hctx->driver_data = nvmeq;
405 return 0;
e85248e5
MW		 406}
407
a4aea562
MB		 408static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
409 unsigned int hctx_idx)
b60503ba 410{
0da7feaa 411 struct nvme_dev *dev = to_nvme_dev(data);
147b27e4 412 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 413
42483228 414 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 415 hctx->driver_data = nvmeq;
416 return 0;
b60503ba
MW		 417}
418
e559398f
CH		 419static int nvme_pci_init_request(struct blk_mq_tag_set *set,
420 struct request *req, unsigned int hctx_idx,
421 unsigned int numa_node)
b60503ba 422{
f4800d6d 423 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
59e29ce6 424
4a4d9bc0 425 nvme_req(req)->ctrl = set->driver_data;
f4b9e6c9 426 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 427 return 0;
428}
429
3b6592f7
JA		 430static int queue_irq_offset(struct nvme_dev *dev)
431{
432 /* if we have more than 1 vec, admin queue offsets us by 1 */
433 if (dev->num_vecs > 1)
434 return 1;
435
436 return 0;
437}
438
a4e1d0b7 439static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
dca51e78 440{
0da7feaa 441 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
3b6592f7
JA		 442 int i, qoff, offset;
443
444 offset = queue_irq_offset(dev);
445 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
446 struct blk_mq_queue_map *map = &set->map[i];
447
448 map->nr_queues = dev->io_queues[i];
449 if (!map->nr_queues) {
e20ba6e1 450 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 451 continue;
3b6592f7
JA		 452 }
453
4b04cc6a
JA		 454 /*
455 * The poll queue(s) doesn't have an IRQ (and hence IRQ
456 * affinity), so use the regular blk-mq cpu mapping
457 */
3b6592f7 458 map->queue_offset = qoff;
cb9e0e50 459 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 460 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
461 else
462 blk_mq_map_queues(map);
3b6592f7
JA		 463 qoff += map->nr_queues;
464 offset += map->nr_queues;
465 }
dca51e78
CH		 466}
467
38210800
KB		 468/*
469 * Write sq tail if we are asked to, or if the next command would wrap.
470 */
471static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 472{
38210800
KB		 473 if (!write_sq) {
474 u16 next_tail = nvmeq->sq_tail + 1;
475
476 if (next_tail == nvmeq->q_depth)
477 next_tail = 0;
478 if (next_tail != nvmeq->last_sq_tail)
479 return;
480 }
481
04f3eafd
JA		 482 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
483 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
484 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 485 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 486}
487
3233b94c
JA		 488static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
489 struct nvme_command *cmd)
b60503ba 490{
c1e0cc7e 491 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 492 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 493 if (++nvmeq->sq_tail == nvmeq->q_depth)
494 nvmeq->sq_tail = 0;
04f3eafd
JA		 495}
496
497static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
498{
499 struct nvme_queue *nvmeq = hctx->driver_data;
500
501 spin_lock(&nvmeq->sq_lock);
38210800
KB		 502 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
503 nvme_write_sq_db(nvmeq, true);
90ea5ca4 504 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 505}
506
ae582935
KB		 507static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req,
508 int nseg)
955b1b5a 509{
a53232cb 510 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
955b1b5a
MI		 511 unsigned int avg_seg_size;
512
20469a37 513 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 514
253a0b76 515 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a 516 return false;
a53232cb 517 if (!nvmeq->qid)
955b1b5a
MI		 518 return false;
519 if (!sgl_threshold || avg_seg_size < sgl_threshold)
520 return false;
521 return true;
522}
523
9275c206 524static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 525{
6c3c05b0 526 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 527 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
528 dma_addr_t dma_addr = iod->first_dma;
eca18b23 529 int i;
eca18b23 530
c372cdd1 531 for (i = 0; i < iod->nr_allocations; i++) {
7846c1b5 532 __le64 *prp_list = iod->list[i].prp_list;
9275c206
CH		 533 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
534
535 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
536 dma_addr = next_dma_addr;
7fe07d14 537 }
9275c206 538}
dff824b2 539
9275c206
CH		 540static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
541{
542 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 543
9275c206
CH		 544 if (iod->dma_len) {
545 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
546 rq_dma_dir(req));
547 return;
eca18b23 548 }
ac3dd5bd 549
91fb2b60
LG		 550 WARN_ON_ONCE(!iod->sgt.nents);
551
552 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
9275c206 553
c372cdd1 554 if (iod->nr_allocations == 0)
7846c1b5 555 dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list,
9275c206 556 iod->first_dma);
8f0edf45 557 else if (iod->nr_allocations == 1)
7846c1b5 558 dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list,
9275c206 559 iod->first_dma);
9275c206
CH		 560 else
561 nvme_free_prps(dev, req);
91fb2b60 562 mempool_free(iod->sgt.sgl, dev->iod_mempool);
b4ff9c8d
KB		 563}
564
d0877473
KB		 565static void nvme_print_sgl(struct scatterlist *sgl, int nents)
566{
567 int i;
568 struct scatterlist *sg;
569
570 for_each_sg(sgl, sg, nents, i) {
571 dma_addr_t phys = sg_phys(sg);
572 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
573 "dma_address:%pad dma_length:%d\n",
574 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
575 sg_dma_len(sg));
576 }
577}
578
a7a7cbe3
CK		 579static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
580 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 581{
f4800d6d 582 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 583 struct dma_pool *pool;
b131c61d 584 int length = blk_rq_payload_bytes(req);
91fb2b60 585 struct scatterlist *sg = iod->sgt.sgl;
ff22b54f
MW		 586 int dma_len = sg_dma_len(sg);
587 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 588 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c
SMM		 589 __le64 *prp_list;
590 dma_addr_t prp_dma;
eca18b23 591 int nprps, i;
ff22b54f 592
6c3c05b0 593 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 594 if (length <= 0) {
595 iod->first_dma = 0;
a7a7cbe3 596 goto done;
5228b328 597 }
ff22b54f 598
6c3c05b0 599 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 600 if (dma_len) {
6c3c05b0 601 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 602 } else {
603 sg = sg_next(sg);
604 dma_addr = sg_dma_address(sg);
605 dma_len = sg_dma_len(sg);
606 }
607
6c3c05b0 608 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 609 iod->first_dma = dma_addr;
a7a7cbe3 610 goto done;
e025344c
SMM		 611 }
612
6c3c05b0 613 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 614 if (nprps <= (256 / 8)) {
615 pool = dev->prp_small_pool;
c372cdd1 616 iod->nr_allocations = 0;
99802a7a
MW		 617 } else {
618 pool = dev->prp_page_pool;
c372cdd1 619 iod->nr_allocations = 1;
99802a7a
MW		 620 }
621
69d2b571 622 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 623 if (!prp_list) {
c372cdd1 624 iod->nr_allocations = -1;
86eea289 625 return BLK_STS_RESOURCE;
b77954cb 626 }
7846c1b5 627 iod->list[0].prp_list = prp_list;
eca18b23 628 iod->first_dma = prp_dma;
e025344c
SMM		 629 i = 0;
630 for (;;) {
6c3c05b0 631 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 632 __le64 *old_prp_list = prp_list;
69d2b571 633 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 634 if (!prp_list)
fa073216 635 goto free_prps;
7846c1b5 636 iod->list[iod->nr_allocations++].prp_list = prp_list;
7523d834
MW		 637 prp_list[0] = old_prp_list[i - 1];
638 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
639 i = 1;
e025344c
SMM		 640 }
641 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 642 dma_len -= NVME_CTRL_PAGE_SIZE;
643 dma_addr += NVME_CTRL_PAGE_SIZE;
644 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 645 if (length <= 0)
646 break;
647 if (dma_len > 0)
648 continue;
86eea289
KB		 649 if (unlikely(dma_len < 0))
650 goto bad_sgl;
e025344c
SMM		 651 sg = sg_next(sg);
652 dma_addr = sg_dma_address(sg);
653 dma_len = sg_dma_len(sg);
ff22b54f 654 }
a7a7cbe3 655done:
91fb2b60 656 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
a7a7cbe3 657 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 658 return BLK_STS_OK;
fa073216
CH		 659free_prps:
660 nvme_free_prps(dev, req);
661 return BLK_STS_RESOURCE;
662bad_sgl:
91fb2b60 663 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
d0877473 664 "Invalid SGL for payload:%d nents:%d\n",
91fb2b60 665 blk_rq_payload_bytes(req), iod->sgt.nents);
86eea289 666 return BLK_STS_IOERR;
ff22b54f
MW		 667}
668
a7a7cbe3
CK		 669static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
670 struct scatterlist *sg)
671{
672 sge->addr = cpu_to_le64(sg_dma_address(sg));
673 sge->length = cpu_to_le32(sg_dma_len(sg));
674 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
675}
676
677static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
678 dma_addr_t dma_addr, int entries)
679{
680 sge->addr = cpu_to_le64(dma_addr);
01df742d
KB		 681 sge->length = cpu_to_le32(entries * sizeof(*sge));
682 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
a7a7cbe3
CK		 683}
684
685static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
91fb2b60 686 struct request *req, struct nvme_rw_command *cmd)
a7a7cbe3
CK		 687{
688 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 689 struct dma_pool *pool;
690 struct nvme_sgl_desc *sg_list;
91fb2b60
LG		 691 struct scatterlist *sg = iod->sgt.sgl;
692 unsigned int entries = iod->sgt.nents;
a7a7cbe3 693 dma_addr_t sgl_dma;
b0f2853b 694 int i = 0;
a7a7cbe3 695
a7a7cbe3
CK		 696 /* setting the transfer type as SGL */
697 cmd->flags = NVME_CMD_SGL_METABUF;
698
b0f2853b 699 if (entries == 1) {
a7a7cbe3
CK		 700 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
701 return BLK_STS_OK;
702 }
703
704 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
705 pool = dev->prp_small_pool;
c372cdd1 706 iod->nr_allocations = 0;
a7a7cbe3
CK		 707 } else {
708 pool = dev->prp_page_pool;
c372cdd1 709 iod->nr_allocations = 1;
a7a7cbe3
CK		 710 }
711
712 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
713 if (!sg_list) {
c372cdd1 714 iod->nr_allocations = -1;
a7a7cbe3
CK		 715 return BLK_STS_RESOURCE;
716 }
717
7846c1b5 718 iod->list[0].sg_list = sg_list;
a7a7cbe3
CK		 719 iod->first_dma = sgl_dma;
720
721 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
a7a7cbe3 722 do {
a7a7cbe3 723 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 724 sg = sg_next(sg);
b0f2853b 725 } while (--entries > 0);
a7a7cbe3 726
a7a7cbe3
CK		 727 return BLK_STS_OK;
728}
729
dff824b2
CH		 730static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
731 struct request *req, struct nvme_rw_command *cmnd,
732 struct bio_vec *bv)
733{
734 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 735 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
736 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 737
738 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
739 if (dma_mapping_error(dev->dev, iod->first_dma))
740 return BLK_STS_RESOURCE;
741 iod->dma_len = bv->bv_len;
742
743 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
744 if (bv->bv_len > first_prp_len)
745 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
a56ea614
LR		 746 else
747 cmnd->dptr.prp2 = 0;
359c1f88 748 return BLK_STS_OK;
dff824b2
CH		 749}
750
29791057
CH		 751static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
752 struct request *req, struct nvme_rw_command *cmnd,
753 struct bio_vec *bv)
754{
755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
756
757 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
758 if (dma_mapping_error(dev->dev, iod->first_dma))
759 return BLK_STS_RESOURCE;
760 iod->dma_len = bv->bv_len;
761
049bf372 762 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 763 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
764 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
765 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 766 return BLK_STS_OK;
29791057
CH		 767}
768
fc17b653 769static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 770 struct nvme_command *cmnd)
d29ec824 771{
f4800d6d 772 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 773 blk_status_t ret = BLK_STS_RESOURCE;
91fb2b60 774 int rc;
d29ec824 775
dff824b2 776 if (blk_rq_nr_phys_segments(req) == 1) {
a53232cb 777 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
dff824b2
CH		 778 struct bio_vec bv = req_bvec(req);
779
780 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 781 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 782 return nvme_setup_prp_simple(dev, req,
783 &cmnd->rw, &bv);
29791057 784
a53232cb 785 if (nvmeq->qid && sgl_threshold &&
253a0b76 786 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 787 return nvme_setup_sgl_simple(dev, req,
788 &cmnd->rw, &bv);
dff824b2
CH		 789 }
790 }
791
792 iod->dma_len = 0;
91fb2b60
LG		 793 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
794 if (!iod->sgt.sgl)
d43f1ccf 795 return BLK_STS_RESOURCE;
91fb2b60
LG		 796 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
797 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
798 if (!iod->sgt.orig_nents)
fa073216 799 goto out_free_sg;
d29ec824 800
91fb2b60
LG		 801 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
802 DMA_ATTR_NO_WARN);
803 if (rc) {
804 if (rc == -EREMOTEIO)
805 ret = BLK_STS_TARGET;
fa073216 806 goto out_free_sg;
91fb2b60 807 }
d29ec824 808
b6c0c237 809 if (nvme_pci_use_sgls(dev, req, iod->sgt.nents))
91fb2b60 810 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
a7a7cbe3
CK		 811 else
812 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 813 if (ret != BLK_STS_OK)
fa073216
CH		 814 goto out_unmap_sg;
815 return BLK_STS_OK;
816
817out_unmap_sg:
91fb2b60 818 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
fa073216 819out_free_sg:
91fb2b60 820 mempool_free(iod->sgt.sgl, dev->iod_mempool);
4aedb705
CH		 821 return ret;
822}
3045c0d0 823
4aedb705
CH		 824static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
825 struct nvme_command *cmnd)
826{
827 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 828
4aedb705
CH		 829 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
830 rq_dma_dir(req), 0);
831 if (dma_mapping_error(dev->dev, iod->meta_dma))
832 return BLK_STS_IOERR;
833 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 834 return BLK_STS_OK;
00df5cb4
MW		 835}
836
62451a2b 837static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
edd10d33 838{
9b048119 839 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ebe6d874 840 blk_status_t ret;
e1e5e564 841
52da4f3f 842 iod->aborted = false;
c372cdd1 843 iod->nr_allocations = -1;
91fb2b60 844 iod->sgt.nents = 0;
9b048119 845
62451a2b 846 ret = nvme_setup_cmd(req->q->queuedata, req);
fc17b653 847 if (ret)
f4800d6d 848 return ret;
a4aea562 849
fc17b653 850 if (blk_rq_nr_phys_segments(req)) {
62451a2b 851 ret = nvme_map_data(dev, req, &iod->cmd);
fc17b653 852 if (ret)
9b048119 853 goto out_free_cmd;
fc17b653 854 }
a4aea562 855
4aedb705 856 if (blk_integrity_rq(req)) {
62451a2b 857 ret = nvme_map_metadata(dev, req, &iod->cmd);
4aedb705
CH		 858 if (ret)
859 goto out_unmap_data;
860 }
861
6887fc64 862 nvme_start_request(req);
fc17b653 863 return BLK_STS_OK;
4aedb705
CH		 864out_unmap_data:
865 nvme_unmap_data(dev, req);
f9d03f96
CH		 866out_free_cmd:
867 nvme_cleanup_cmd(req);
ba1ca37e 868 return ret;
b60503ba 869}
e1e5e564 870
62451a2b
JA		 871/*
872 * NOTE: ns is NULL when called on the admin queue.
873 */
874static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
875 const struct blk_mq_queue_data *bd)
876{
877 struct nvme_queue *nvmeq = hctx->driver_data;
878 struct nvme_dev *dev = nvmeq->dev;
879 struct request *req = bd->rq;
880 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
881 blk_status_t ret;
882
883 /*
884 * We should not need to do this, but we're still using this to
885 * ensure we can drain requests on a dying queue.
886 */
887 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
888 return BLK_STS_IOERR;
889
890 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
891 return nvme_fail_nonready_command(&dev->ctrl, req);
892
893 ret = nvme_prep_rq(dev, req);
894 if (unlikely(ret))
895 return ret;
896 spin_lock(&nvmeq->sq_lock);
897 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
898 nvme_write_sq_db(nvmeq, bd->last);
899 spin_unlock(&nvmeq->sq_lock);
900 return BLK_STS_OK;
901}
902
d62cbcf6
JA		 903static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
904{
905 spin_lock(&nvmeq->sq_lock);
906 while (!rq_list_empty(*rqlist)) {
907 struct request *req = rq_list_pop(rqlist);
908 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
909
910 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
911 }
912 nvme_write_sq_db(nvmeq, true);
913 spin_unlock(&nvmeq->sq_lock);
914}
915
916static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
917{
918 /*
919 * We should not need to do this, but we're still using this to
920 * ensure we can drain requests on a dying queue.
921 */
922 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
923 return false;
924 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
925 return false;
926
d62cbcf6
JA		 927 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
928}
929
930static void nvme_queue_rqs(struct request **rqlist)
931{
6bfec799 932 struct request *req, *next, *prev = NULL;
d62cbcf6
JA		 933 struct request *requeue_list = NULL;
934
6bfec799 935 rq_list_for_each_safe(rqlist, req, next) {
d62cbcf6
JA		 936 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
937
938 if (!nvme_prep_rq_batch(nvmeq, req)) {
939 /* detach 'req' and add to remainder list */
6bfec799
KB		 940 rq_list_move(rqlist, &requeue_list, req, prev);
941
942 req = prev;
943 if (!req)
944 continue;
d62cbcf6
JA		 945 }
946
6bfec799 947 if (!next || req->mq_hctx != next->mq_hctx) {
d62cbcf6 948 /* detach rest of list, and submit */
6bfec799 949 req->rq_next = NULL;
d62cbcf6 950 nvme_submit_cmds(nvmeq, rqlist);
6bfec799
KB		 951 *rqlist = next;
952 prev = NULL;
953 } else
954 prev = req;
955 }
d62cbcf6
JA		 956
957 *rqlist = requeue_list;
958}
959
c234a653 960static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 961{
a53232cb
KB		 962 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
963 struct nvme_dev *dev = nvmeq->dev;
964
965 if (blk_integrity_rq(req)) {
966 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 967
4aedb705 968 dma_unmap_page(dev->dev, iod->meta_dma,
b8f6446b 969 rq_integrity_vec(req)->bv_len, rq_dma_dir(req));
a53232cb
KB		 970 }
971
b15c592d 972 if (blk_rq_nr_phys_segments(req))
4aedb705 973 nvme_unmap_data(dev, req);
c234a653
JA		 974}
975
976static void nvme_pci_complete_rq(struct request *req)
977{
978 nvme_pci_unmap_rq(req);
77f02a7a 979 nvme_complete_rq(req);
b60503ba
MW		 980}
981
c234a653
JA		 982static void nvme_pci_complete_batch(struct io_comp_batch *iob)
983{
984 nvme_complete_batch(iob, nvme_pci_unmap_rq);
985}
986
d783e0bd 987/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 988static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 989{
74943d45
KB		 990 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
991
992 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 993}
994
eb281c82 995static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 996{
eb281c82 997 u16 head = nvmeq->cq_head;
adf68f21 998
397c699f
KB		 999 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1000 nvmeq->dbbuf_cq_ei))
1001 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1002}
aae239e1 1003
cfa27356
CH		 1004static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1005{
1006 if (!nvmeq->qid)
1007 return nvmeq->dev->admin_tagset.tags[0];
1008 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1009}
1010
c234a653
JA		 1011static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1012 struct io_comp_batch *iob, u16 idx)
83a12fb7 1013{
74943d45 1014 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1015 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1016 struct request *req;
adf68f21 1017
83a12fb7
SG		 1018 /*
1019 * AEN requests are special as they don't time out and can
1020 * survive any kind of queue freeze and often don't respond to
1021 * aborts. We don't even bother to allocate a struct request
1022 * for them but rather special case them here.
1023 */
62df8016 1024 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1025 nvme_complete_async_event(&nvmeq->dev->ctrl,
1026 cqe->status, &cqe->result);
a0fa9647 1027 return;
83a12fb7 1028 }
b60503ba 1029
e7006de6 1030 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1031 if (unlikely(!req)) {
1032 dev_warn(nvmeq->dev->ctrl.device,
1033 "invalid id %d completed on queue %d\n",
62df8016 1034 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1035 return;
1036 }
1037
604c01d5 1038 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1039 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1040 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1041 nvme_pci_complete_batch))
ff029451 1042 nvme_pci_complete_rq(req);
83a12fb7 1043}
b60503ba 1044
5cb525c8
JA		 1045static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1046{
a0aac973 1047 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1048
1049 if (tmp == nvmeq->q_depth) {
5cb525c8 1050 nvmeq->cq_head = 0;
e2a366a4 1051 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1052 } else {
1053 nvmeq->cq_head = tmp;
b60503ba 1054 }
a0fa9647
JA		 1055}
1056
c234a653
JA		 1057static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1058 struct io_comp_batch *iob)
a0fa9647 1059{
1052b8ac 1060 int found = 0;
b60503ba 1061
1052b8ac 1062 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1063 found++;
b69e2ef2
KB		 1064 /*
1065 * load-load control dependency between phase and the rest of
1066 * the cqe requires a full read memory barrier
1067 */
1068 dma_rmb();
c234a653 1069 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1070 nvme_update_cq_head(nvmeq);
920d13a8 1071 }
eb281c82 1072
324b494c 1073 if (found)
920d13a8 1074 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1075 return found;
b60503ba
MW		 1076}
1077
1078static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1079{
58ffacb5 1080 struct nvme_queue *nvmeq = data;
4f502245 1081 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1082
4f502245
JA		 1083 if (nvme_poll_cq(nvmeq, &iob)) {
1084 if (!rq_list_empty(iob.req_list))
1085 nvme_pci_complete_batch(&iob);
05fae499 1086 return IRQ_HANDLED;
4f502245 1087 }
05fae499 1088 return IRQ_NONE;
58ffacb5
MW		 1089}
1090
1091static irqreturn_t nvme_irq_check(int irq, void *data)
1092{
1093 struct nvme_queue *nvmeq = data;
4e523547 1094
750dde44 1095 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1096 return IRQ_WAKE_THREAD;
1097 return IRQ_NONE;
58ffacb5
MW		 1098}
1099
0b2a8a9f 1100/*
fa059b85 1101 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1102 * Can be called from any context.
1103 */
fa059b85 1104static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1105{
3a7afd8e 1106 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1107
fa059b85 1108 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1109
fa059b85 1110 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1111 nvme_poll_cq(nvmeq, NULL);
fa059b85 1112 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1113}
1114
5a72e899 1115static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1116{
1117 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1118 bool found;
1119
1120 if (!nvme_cqe_pending(nvmeq))
1121 return 0;
1122
3a7afd8e 1123 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1124 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1125 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1126
dabcefab
JA		 1127 return found;
1128}
1129
ad22c355 1130static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1131{
f866fc42 1132 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1133 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1134 struct nvme_command c = { };
b60503ba 1135
a4aea562 1136 c.common.opcode = nvme_admin_async_event;
ad22c355 1137 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1138
1139 spin_lock(&nvmeq->sq_lock);
1140 nvme_sq_copy_cmd(nvmeq, &c);
1141 nvme_write_sq_db(nvmeq, true);
1142 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1143}
1144
b60503ba 1145static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1146{
f66e2804 1147 struct nvme_command c = { };
b60503ba 1148
b60503ba
MW		 1149 c.delete_queue.opcode = opcode;
1150 c.delete_queue.qid = cpu_to_le16(id);
1151
1c63dc66 1152 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1153}
1154
b60503ba 1155static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1156 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1157{
f66e2804 1158 struct nvme_command c = { };
4b04cc6a
JA		 1159 int flags = NVME_QUEUE_PHYS_CONTIG;
1160
7c349dde 1161 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1162 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1163
d29ec824 1164 /*
16772ae6 1165 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1166 * is attached to the request.
1167 */
b60503ba
MW		 1168 c.create_cq.opcode = nvme_admin_create_cq;
1169 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1170 c.create_cq.cqid = cpu_to_le16(qid);
1171 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1172 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1173 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1174
1c63dc66 1175 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1176}
1177
1178static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1179 struct nvme_queue *nvmeq)
1180{
9abd68ef 1181 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1182 struct nvme_command c = { };
81c1cd98 1183 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1184
9abd68ef
JA		 1185 /*
1186 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1187 * set. Since URGENT priority is zeroes, it makes all queues
1188 * URGENT.
1189 */
1190 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1191 flags |= NVME_SQ_PRIO_MEDIUM;
1192
d29ec824 1193 /*
16772ae6 1194 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1195 * is attached to the request.
1196 */
b60503ba
MW		 1197 c.create_sq.opcode = nvme_admin_create_sq;
1198 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1199 c.create_sq.sqid = cpu_to_le16(qid);
1200 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1201 c.create_sq.sq_flags = cpu_to_le16(flags);
1202 c.create_sq.cqid = cpu_to_le16(qid);
1203
1c63dc66 1204 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1205}
1206
1207static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1208{
1209 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1210}
1211
1212static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1213{
1214 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1215}
1216
de671d61 1217static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1218{
a53232cb 1219 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
e44ac588 1220
27fa9bc5
CH		 1221 dev_warn(nvmeq->dev->ctrl.device,
1222 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1223 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1224 blk_mq_free_request(req);
de671d61 1225 return RQ_END_IO_NONE;
bc5fc7e4
MW		 1226}
1227
b2a0eb1a
KB		 1228static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1229{
b2a0eb1a
KB		 1230 /* If true, indicates loss of adapter communication, possibly by a
1231 * NVMe Subsystem reset.
1232 */
1233 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1234
ad70062c 1235 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
e6e7f7ac 1236 switch (nvme_ctrl_state(&dev->ctrl)) {
ad70062c 1237 case NVME_CTRL_RESETTING:
ad6a0a52 1238 case NVME_CTRL_CONNECTING:
b2a0eb1a 1239 return false;
ad70062c
JW		 1240 default:
1241 break;
1242 }
b2a0eb1a
KB		 1243
1244 /* We shouldn't reset unless the controller is on fatal error state
1245 * _or_ if we lost the communication with it.
1246 */
1247 if (!(csts & NVME_CSTS_CFS) && !nssro)
1248 return false;
1249
b2a0eb1a
KB		 1250 return true;
1251}
1252
1253static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1254{
1255 /* Read a config register to help see what died. */
1256 u16 pci_status;
1257 int result;
1258
1259 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1260 &pci_status);
1261 if (result == PCIBIOS_SUCCESSFUL)
1262 dev_warn(dev->ctrl.device,
1263 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1264 csts, pci_status);
1265 else
1266 dev_warn(dev->ctrl.device,
1267 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1268 csts, result);
4641a8e6
KB		 1269
1270 if (csts != ~0)
1271 return;
1272
1273 dev_warn(dev->ctrl.device,
1274 "Does your device have a faulty power saving mode enabled?\n");
1275 dev_warn(dev->ctrl.device,
1276 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
b2a0eb1a
KB		 1277}
1278
9bdb4833 1279static enum blk_eh_timer_return nvme_timeout(struct request *req)
c30341dc 1280{
f4800d6d 1281 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a53232cb 1282 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
c30341dc 1283 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1284 struct request *abort_req;
f66e2804 1285 struct nvme_command cmd = { };
b2a0eb1a 1286 u32 csts = readl(dev->bar + NVME_REG_CSTS);
172fb496 1287 u8 opcode;
b2a0eb1a 1288
25bb3534
NS		 1289 if (nvme_state_terminal(&dev->ctrl))
1290 goto disable;
1291
651438bb
WX		 1292 /* If PCI error recovery process is happening, we cannot reset or
1293 * the recovery mechanism will surely fail.
1294 */
1295 mb();
1296 if (pci_channel_offline(to_pci_dev(dev->dev)))
1297 return BLK_EH_RESET_TIMER;
1298
b2a0eb1a
KB		 1299 /*
1300 * Reset immediately if the controller is failed
1301 */
1302 if (nvme_should_reset(dev, csts)) {
1303 nvme_warn_reset(dev, csts);
71a5bb15 1304 goto disable;
b2a0eb1a 1305 }
c30341dc 1306
7776db1c
KB		 1307 /*
1308 * Did we miss an interrupt?
1309 */
fa059b85 1310 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1311 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1312 else
1313 nvme_poll_irqdisable(nvmeq);
1314
1c584208 1315 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
7776db1c 1316 dev_warn(dev->ctrl.device,
172fb496
KB		 1317 "I/O tag %d (%04x) QID %d timeout, completion polled\n",
1318 req->tag, nvme_cid(req), nvmeq->qid);
db8c48e4 1319 return BLK_EH_DONE;
7776db1c
KB		 1320 }
1321
31c7c7d2 1322 /*
fd634f41
CH		 1323 * Shutdown immediately if controller times out while starting. The
1324 * reset work will see the pci device disabled when it gets the forced
1325 * cancellation error. All outstanding requests are completed on
db8c48e4 1326 * shutdown, so we return BLK_EH_DONE.
fd634f41 1327 */
e6e7f7ac 1328 switch (nvme_ctrl_state(&dev->ctrl)) {
4244140d 1329 case NVME_CTRL_CONNECTING:
2036f726 1330 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1331 fallthrough;
2036f726 1332 case NVME_CTRL_DELETING:
b9cac43c 1333 dev_warn_ratelimited(dev->ctrl.device,
172fb496
KB		 1334 "I/O tag %d (%04x) QID %d timeout, disable controller\n",
1335 req->tag, nvme_cid(req), nvmeq->qid);
27fa9bc5 1336 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1337 nvme_dev_disable(dev, true);
db8c48e4 1338 return BLK_EH_DONE;
39a9dd81
KB		 1339 case NVME_CTRL_RESETTING:
1340 return BLK_EH_RESET_TIMER;
4244140d
KB		 1341 default:
1342 break;
c30341dc
KB		 1343 }
1344
fd634f41 1345 /*
ee0d96d3
BW		 1346 * Shutdown the controller immediately and schedule a reset if the
1347 * command was already aborted once before and still hasn't been
1348 * returned to the driver, or if this is the admin queue.
31c7c7d2 1349 */
172fb496 1350 opcode = nvme_req(req)->cmd->common.opcode;
f4800d6d 1351 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1352 dev_warn(dev->ctrl.device,
172fb496
KB		 1353 "I/O tag %d (%04x) opcode %#x (%s) QID %d timeout, reset controller\n",
1354 req->tag, nvme_cid(req), opcode,
7d23e836 1355 nvme_opcode_str(nvmeq->qid, opcode), nvmeq->qid);
7ad92f65 1356 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
71a5bb15 1357 goto disable;
c30341dc 1358 }
c30341dc 1359
e7a2a87d 1360 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1361 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1362 return BLK_EH_RESET_TIMER;
6bf25d16 1363 }
52da4f3f 1364 iod->aborted = true;
a4aea562 1365
c30341dc 1366 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1367 cmd.abort.cid = nvme_cid(req);
c30341dc 1368 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1369
1b3c47c1 1370 dev_warn(nvmeq->dev->ctrl.device,
172fb496
KB		 1371 "I/O tag %d (%04x) opcode %#x (%s) QID %d timeout, aborting req_op:%s(%u) size:%u\n",
1372 req->tag, nvme_cid(req), opcode, nvme_get_opcode_str(opcode),
1373 nvmeq->qid, blk_op_str(req_op(req)), req_op(req),
1374 blk_rq_bytes(req));
e7a2a87d 1375
e559398f
CH		 1376 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1377 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1378 if (IS_ERR(abort_req)) {
1379 atomic_inc(&dev->ctrl.abort_limit);
1380 return BLK_EH_RESET_TIMER;
1381 }
e559398f 1382 nvme_init_request(abort_req, &cmd);
e7a2a87d 1383
e2e53086 1384 abort_req->end_io = abort_endio;
e7a2a87d 1385 abort_req->end_io_data = NULL;
e2e53086 1386 blk_execute_rq_nowait(abort_req, false);
c30341dc 1387
31c7c7d2
CH		 1388 /*
1389 * The aborted req will be completed on receiving the abort req.
1390 * We enable the timer again. If hit twice, it'll cause a device reset,
1391 * as the device then is in a faulty state.
1392 */
1393 return BLK_EH_RESET_TIMER;
71a5bb15
KB		 1394
1395disable:
25bb3534
NS		 1396 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
1397 if (nvme_state_terminal(&dev->ctrl))
1398 nvme_dev_disable(dev, true);
71a5bb15 1399 return BLK_EH_DONE;
25bb3534 1400 }
71a5bb15
KB		 1401
1402 nvme_dev_disable(dev, false);
1403 if (nvme_try_sched_reset(&dev->ctrl))
1404 nvme_unquiesce_io_queues(&dev->ctrl);
1405 return BLK_EH_DONE;
c30341dc
KB		 1406}
1407
a4aea562
MB		 1408static void nvme_free_queue(struct nvme_queue *nvmeq)
1409{
8a1d09a6 1410 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1411 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1412 if (!nvmeq->sq_cmds)
1413 return;
0f238ff5 1414
63223078 1415 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1416 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1417 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1418 } else {
8a1d09a6 1419 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1420 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1421 }
9e866774
MW		 1422}
1423
a1a5ef99 1424static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1425{
1426 int i;
1427
d858e5f0 1428 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1429 dev->ctrl.queue_count--;
147b27e4 1430 nvme_free_queue(&dev->queues[i]);
121c7ad4 1431 }
22404274
KB		 1432}
1433
10981f23 1434static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
b60503ba 1435{
10981f23
CH		 1436 struct nvme_queue *nvmeq = &dev->queues[qid];
1437
4e224106 1438 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
10981f23 1439 return;
a09115b2 1440
4e224106 1441 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1442 mb();
a09115b2 1443
4e224106 1444 nvmeq->dev->online_queues--;
1c63dc66 1445 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
9f27bd70 1446 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
7c349dde 1447 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
10981f23 1448 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
4d115420 1449}
b60503ba 1450
8fae268b
KB		 1451static void nvme_suspend_io_queues(struct nvme_dev *dev)
1452{
1453 int i;
1454
1455 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
10981f23 1456 nvme_suspend_queue(dev, i);
b60503ba
MW		 1457}
1458
fa46c6fb
KB		 1459/*
1460 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1461 * that can check this device's completion queues have synced, except
1462 * nvme_poll(). This is the last chance for the driver to see a natural
1463 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1464 */
1465static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1466{
fa46c6fb
KB		 1467 int i;
1468
9210c075
DZ		 1469 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1470 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1471 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1472 spin_unlock(&dev->queues[i].cq_poll_lock);
1473 }
fa46c6fb
KB		 1474}
1475
8ffaadf7
JD		 1476static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1477 int entry_size)
1478{
1479 int q_depth = dev->q_depth;
5fd4ce1b 1480 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1481 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1482
1483 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1484 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1485
6c3c05b0 1486 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1487 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1488
1489 /*
1490 * Ensure the reduced q_depth is above some threshold where it
1491 * would be better to map queues in system memory with the
1492 * original depth
1493 */
1494 if (q_depth < 64)
1495 return -ENOMEM;
1496 }
1497
1498 return q_depth;
1499}
1500
1501static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1502 int qid)
8ffaadf7 1503{
0f238ff5
LG		 1504 struct pci_dev *pdev = to_pci_dev(dev->dev);
1505
1506 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1507 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1508 if (nvmeq->sq_cmds) {
1509 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1510 nvmeq->sq_cmds);
1511 if (nvmeq->sq_dma_addr) {
1512 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1513 return 0;
1514 }
1515
8a1d09a6 1516 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1517 }
0f238ff5 1518 }
8ffaadf7 1519
8a1d09a6 1520 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1521 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1522 if (!nvmeq->sq_cmds)
1523 return -ENOMEM;
8ffaadf7
JD		 1524 return 0;
1525}
1526
a6ff7262 1527static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1528{
147b27e4 1529 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1530
62314e40
KB		 1531 if (dev->ctrl.queue_count > qid)
1532 return 0;
b60503ba 1533
c1e0cc7e 1534 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1535 nvmeq->q_depth = depth;
1536 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1537 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1538 if (!nvmeq->cqes)
1539 goto free_nvmeq;
b60503ba 1540
8a1d09a6 1541 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1542 goto free_cqdma;
1543
091b6092 1544 nvmeq->dev = dev;
1ab0cd69 1545 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1546 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1547 nvmeq->cq_head = 0;
82123460 1548 nvmeq->cq_phase = 1;
b80d5ccc 1549 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1550 nvmeq->qid = qid;
d858e5f0 1551 dev->ctrl.queue_count++;
36a7e993 1552
147b27e4 1553 return 0;
b60503ba
MW		 1554
1555 free_cqdma:
8a1d09a6
BH		 1556 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1557 nvmeq->cq_dma_addr);
b60503ba 1558 free_nvmeq:
147b27e4 1559 return -ENOMEM;
b60503ba
MW		 1560}
1561
dca51e78 1562static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1563{
0ff199cb
CH		 1564 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1565 int nr = nvmeq->dev->ctrl.instance;
1566
1567 if (use_threaded_interrupts) {
1568 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1569 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1570 } else {
1571 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1572 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1573 }
3001082c
MW		 1574}
1575
22404274 1576static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1577{
22404274 1578 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1579
22404274 1580 nvmeq->sq_tail = 0;
38210800 1581 nvmeq->last_sq_tail = 0;
22404274
KB		 1582 nvmeq->cq_head = 0;
1583 nvmeq->cq_phase = 1;
b80d5ccc 1584 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1585 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1586 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1587 dev->online_queues++;
3a7afd8e 1588 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1589}
1590
e4b9852a
CC		 1591/*
1592 * Try getting shutdown_lock while setting up IO queues.
1593 */
1594static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1595{
1596 /*
1597 * Give up if the lock is being held by nvme_dev_disable.
1598 */
1599 if (!mutex_trylock(&dev->shutdown_lock))
1600 return -ENODEV;
1601
1602 /*
1603 * Controller is in wrong state, fail early.
1604 */
e6e7f7ac 1605 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_CONNECTING) {
e4b9852a
CC		 1606 mutex_unlock(&dev->shutdown_lock);
1607 return -ENODEV;
1608 }
1609
1610 return 0;
1611}
1612
4b04cc6a 1613static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1614{
1615 struct nvme_dev *dev = nvmeq->dev;
1616 int result;
7c349dde 1617 u16 vector = 0;
3f85d50b 1618
d1ed6aa1
CH		 1619 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1620
22b55601
KB		 1621 /*
1622 * A queue's vector matches the queue identifier unless the controller
1623 * has only one vector available.
1624 */
4b04cc6a
JA		 1625 if (!polled)
1626 vector = dev->num_vecs == 1 ? 0 : qid;
1627 else
7c349dde 1628 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1629
a8e3e0bb 1630 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1631 if (result)
1632 return result;
b60503ba
MW		 1633
1634 result = adapter_alloc_sq(dev, qid, nvmeq);
1635 if (result < 0)
ded45505 1636 return result;
c80b36cd 1637 if (result)
b60503ba
MW		 1638 goto release_cq;
1639
a8e3e0bb 1640 nvmeq->cq_vector = vector;
4b04cc6a 1641
e4b9852a
CC		 1642 result = nvme_setup_io_queues_trylock(dev);
1643 if (result)
1644 return result;
1645 nvme_init_queue(nvmeq, qid);
7c349dde 1646 if (!polled) {
4b04cc6a
JA		 1647 result = queue_request_irq(nvmeq);
1648 if (result < 0)
1649 goto release_sq;
1650 }
b60503ba 1651
4e224106 1652 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1653 mutex_unlock(&dev->shutdown_lock);
22404274 1654 return result;
b60503ba 1655
a8e3e0bb 1656release_sq:
f25a2dfc 1657 dev->online_queues--;
e4b9852a 1658 mutex_unlock(&dev->shutdown_lock);
b60503ba 1659 adapter_delete_sq(dev, qid);
a8e3e0bb 1660release_cq:
b60503ba 1661 adapter_delete_cq(dev, qid);
22404274 1662 return result;
b60503ba
MW		 1663}
1664
f363b089 1665static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1666 .queue_rq = nvme_queue_rq,
77f02a7a 1667 .complete = nvme_pci_complete_rq,
a4aea562 1668 .init_hctx = nvme_admin_init_hctx,
e559398f 1669 .init_request = nvme_pci_init_request,
a4aea562
MB		 1670 .timeout = nvme_timeout,
1671};
1672
f363b089 1673static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8 1674 .queue_rq = nvme_queue_rq,
d62cbcf6 1675 .queue_rqs = nvme_queue_rqs,
376f7ef8
CH		 1676 .complete = nvme_pci_complete_rq,
1677 .commit_rqs = nvme_commit_rqs,
1678 .init_hctx = nvme_init_hctx,
e559398f 1679 .init_request = nvme_pci_init_request,
376f7ef8
CH		 1680 .map_queues = nvme_pci_map_queues,
1681 .timeout = nvme_timeout,
1682 .poll = nvme_poll,
dabcefab
JA		 1683};
1684
ea191d2f
KB		 1685static void nvme_dev_remove_admin(struct nvme_dev *dev)
1686{
1c63dc66 1687 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1688 /*
1689 * If the controller was reset during removal, it's possible
1690 * user requests may be waiting on a stopped queue. Start the
1691 * queue to flush these to completion.
1692 */
9f27bd70 1693 nvme_unquiesce_admin_queue(&dev->ctrl);
0da7feaa 1694 nvme_remove_admin_tag_set(&dev->ctrl);
ea191d2f
KB		 1695 }
1696}
1697
97f6ef64
XY		 1698static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1699{
1700 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1701}
1702
1703static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1704{
1705 struct pci_dev *pdev = to_pci_dev(dev->dev);
1706
1707 if (size <= dev->bar_mapped_size)
1708 return 0;
1709 if (size > pci_resource_len(pdev, 0))
1710 return -ENOMEM;
1711 if (dev->bar)
1712 iounmap(dev->bar);
1713 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1714 if (!dev->bar) {
1715 dev->bar_mapped_size = 0;
1716 return -ENOMEM;
1717 }
1718 dev->bar_mapped_size = size;
1719 dev->dbs = dev->bar + NVME_REG_DBS;
1720
1721 return 0;
1722}
1723
01ad0990 1724static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1725{
ba47e386 1726 int result;
b60503ba
MW		 1727 u32 aqa;
1728 struct nvme_queue *nvmeq;
1729
97f6ef64
XY		 1730 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1731 if (result < 0)
1732 return result;
1733
8ef2074d 1734 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1735 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1736
7a67cbea
CH		 1737 if (dev->subsystem &&
1738 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1739 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1740
285b6e9b
CH		 1741 /*
1742 * If the device has been passed off to us in an enabled state, just
1743 * clear the enabled bit. The spec says we should set the 'shutdown
1744 * notification bits', but doing so may cause the device to complete
1745 * commands to the admin queue ... and we don't know what memory that
1746 * might be pointing at!
1747 */
1748 result = nvme_disable_ctrl(&dev->ctrl, false);
ba47e386
MW		 1749 if (result < 0)
1750 return result;
b60503ba 1751
a6ff7262 1752 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1753 if (result)
1754 return result;
b60503ba 1755
635333e4
MG		 1756 dev->ctrl.numa_node = dev_to_node(dev->dev);
1757
147b27e4 1758 nvmeq = &dev->queues[0];
b60503ba
MW		 1759 aqa = nvmeq->q_depth - 1;
1760 aqa |= aqa << 16;
1761
7a67cbea
CH		 1762 writel(aqa, dev->bar + NVME_REG_AQA);
1763 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1764 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1765
c0f2f45b 1766 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1767 if (result)
d4875622 1768 return result;
a4aea562 1769
2b25d981 1770 nvmeq->cq_vector = 0;
161b8be2 1771 nvme_init_queue(nvmeq, 0);
dca51e78 1772 result = queue_request_irq(nvmeq);
758dd7fd 1773 if (result) {
7c349dde 1774 dev->online_queues--;
d4875622 1775 return result;
758dd7fd 1776 }
025c557a 1777
4e224106 1778 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1779 return result;
1780}
1781
749941f2 1782static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1783{
4b04cc6a 1784 unsigned i, max, rw_queues;
749941f2 1785 int ret = 0;
42f61420 1786
d858e5f0 1787 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1788 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1789 ret = -ENOMEM;
42f61420 1790 break;
749941f2
CH		 1791 }
1792 }
42f61420 1793
d858e5f0 1794 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1795 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1796 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1797 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1798 } else {
1799 rw_queues = max;
1800 }
1801
949928c1 1802 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1803 bool polled = i > rw_queues;
1804
1805 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1806 if (ret)
42f61420 1807 break;
27e8166c 1808 }
749941f2
CH		 1809
1810 /*
1811 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1812 * than the desired amount of queues, and even a controller without
1813 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1814 * be useful to upgrade a buggy firmware for example.
1815 */
1816 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1817}
1818
88de4598 1819static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1820{
88de4598
CH		 1821 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1822
1823 return 1ULL << (12 + 4 * szu);
1824}
1825
1826static u32 nvme_cmb_size(struct nvme_dev *dev)
1827{
1828 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1829}
1830
f65efd6d 1831static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1832{
88de4598 1833 u64 size, offset;
8ffaadf7
JD		 1834 resource_size_t bar_size;
1835 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1836 int bar;
8ffaadf7 1837
9fe5c59f
KB		 1838 if (dev->cmb_size)
1839 return;
1840
20d3bb92
KJ		 1841 if (NVME_CAP_CMBS(dev->ctrl.cap))
1842 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1843
7a67cbea 1844 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1845 if (!dev->cmbsz)
1846 return;
202021c1 1847 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1848
88de4598
CH		 1849 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1850 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1851 bar = NVME_CMB_BIR(dev->cmbloc);
1852 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1853
1854 if (offset > bar_size)
f65efd6d 1855 return;
8ffaadf7 1856
20d3bb92
KJ		 1857 /*
1858 * Tell the controller about the host side address mapping the CMB,
1859 * and enable CMB decoding for the NVMe 1.4+ scheme:
1860 */
1861 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1862 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1863 (pci_bus_address(pdev, bar) + offset),
1864 dev->bar + NVME_REG_CMBMSC);
1865 }
1866
8ffaadf7
JD		 1867 /*
1868 * Controllers may support a CMB size larger than their BAR,
1869 * for example, due to being behind a bridge. Reduce the CMB to
1870 * the reported size of the BAR
1871 */
1872 if (size > bar_size - offset)
1873 size = bar_size - offset;
1874
0f238ff5
LG		 1875 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1876 dev_warn(dev->ctrl.device,
1877 "failed to register the CMB\n");
f65efd6d 1878 return;
0f238ff5
LG		 1879 }
1880
8ffaadf7 1881 dev->cmb_size = size;
0f238ff5
LG		 1882 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1883
1884 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1885 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1886 pci_p2pmem_publish(pdev, true);
e917a849
KB		 1887
1888 nvme_update_attrs(dev);
8ffaadf7
JD		 1889}
1890
87ad72a5
CH		 1891static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1892{
6c3c05b0 1893 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1894 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1895 struct nvme_command c = { };
87ad72a5
CH		 1896 int ret;
1897
87ad72a5
CH		 1898 c.features.opcode = nvme_admin_set_features;
1899 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1900 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1901 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1902 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1903 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1904 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1905
1906 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1907 if (ret) {
1908 dev_warn(dev->ctrl.device,
1909 "failed to set host mem (err %d, flags %#x).\n",
1910 ret, bits);
a5df5e79
KB		 1911 } else
1912 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1913
87ad72a5
CH		 1914 return ret;
1915}
1916
1917static void nvme_free_host_mem(struct nvme_dev *dev)
1918{
1919 int i;
1920
1921 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1922 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1923 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1924
cc667f6d
LD		 1925 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1926 le64_to_cpu(desc->addr),
1927 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1928 }
1929
1930 kfree(dev->host_mem_desc_bufs);
1931 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1932 dma_free_coherent(dev->dev,
1933 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1934 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1935 dev->host_mem_descs = NULL;
7e5dd57e 1936 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1937}
1938
92dc6895
CH		 1939static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1940 u32 chunk_size)
9d713c2b 1941{
87ad72a5 1942 struct nvme_host_mem_buf_desc *descs;
92dc6895 1943 u32 max_entries, len;
4033f35d 1944 dma_addr_t descs_dma;
2ee0e4ed 1945 int i = 0;
87ad72a5 1946 void **bufs;
6fbcde66 1947 u64 size, tmp;
87ad72a5 1948
87ad72a5
CH		 1949 tmp = (preferred + chunk_size - 1);
1950 do_div(tmp, chunk_size);
1951 max_entries = tmp;
044a9df1
CH		 1952
1953 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1954 max_entries = dev->ctrl.hmmaxd;
1955
750afb08
LC		 1956 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1957 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1958 if (!descs)
1959 goto out;
1960
1961 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1962 if (!bufs)
1963 goto out_free_descs;
1964
244a8fe4 1965 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1966 dma_addr_t dma_addr;
1967
50cdb7c6 1968 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1969 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1970 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1971 if (!bufs[i])
1972 break;
1973
1974 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1975 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1976 i++;
1977 }
1978
92dc6895 1979 if (!size)
87ad72a5 1980 goto out_free_bufs;
87ad72a5 1981
87ad72a5
CH		 1982 dev->nr_host_mem_descs = i;
1983 dev->host_mem_size = size;
1984 dev->host_mem_descs = descs;
4033f35d 1985 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1986 dev->host_mem_desc_bufs = bufs;
1987 return 0;
1988
1989out_free_bufs:
1990 while (--i >= 0) {
6c3c05b0 1991 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1992
cc667f6d
LD		 1993 dma_free_attrs(dev->dev, size, bufs[i],
1994 le64_to_cpu(descs[i].addr),
1995 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1996 }
1997
1998 kfree(bufs);
1999out_free_descs:
4033f35d
CH		 2000 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2001 descs_dma);
87ad72a5 2002out:
87ad72a5
CH		 2003 dev->host_mem_descs = NULL;
2004 return -ENOMEM;
2005}
2006
92dc6895
CH		 2007static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2008{
9dc54a0d
CK		 2009 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2010 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2011 u64 chunk_size;
92dc6895
CH		 2012
2013 /* start big and work our way down */
9dc54a0d 2014 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2015 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2016 if (!min || dev->host_mem_size >= min)
2017 return 0;
2018 nvme_free_host_mem(dev);
2019 }
2020 }
2021
2022 return -ENOMEM;
2023}
2024
9620cfba 2025static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2026{
2027 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2028 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2029 u64 min = (u64)dev->ctrl.hmmin * 4096;
2030 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2031 int ret;
87ad72a5 2032
acb71e53
CH		 2033 if (!dev->ctrl.hmpre)
2034 return 0;
2035
87ad72a5
CH		 2036 preferred = min(preferred, max);
2037 if (min > max) {
2038 dev_warn(dev->ctrl.device,
2039 "min host memory (%lld MiB) above limit (%d MiB).\n",
2040 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2041 nvme_free_host_mem(dev);
9620cfba 2042 return 0;
87ad72a5
CH		 2043 }
2044
2045 /*
2046 * If we already have a buffer allocated check if we can reuse it.
2047 */
2048 if (dev->host_mem_descs) {
2049 if (dev->host_mem_size >= min)
2050 enable_bits |= NVME_HOST_MEM_RETURN;
2051 else
2052 nvme_free_host_mem(dev);
2053 }
2054
2055 if (!dev->host_mem_descs) {
92dc6895
CH		 2056 if (nvme_alloc_host_mem(dev, min, preferred)) {
2057 dev_warn(dev->ctrl.device,
2058 "failed to allocate host memory buffer.\n");
9620cfba 2059 return 0; /* controller must work without HMB */
92dc6895
CH		 2060 }
2061
2062 dev_info(dev->ctrl.device,
2063 "allocated %lld MiB host memory buffer.\n",
2064 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2065 }
2066
9620cfba
CH		 2067 ret = nvme_set_host_mem(dev, enable_bits);
2068 if (ret)
87ad72a5 2069 nvme_free_host_mem(dev);
9620cfba 2070 return ret;
9d713c2b
KB		 2071}
2072
0521905e
KB		 2073static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2074 char *buf)
2075{
2076 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2077
2078 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2079 ndev->cmbloc, ndev->cmbsz);
2080}
2081static DEVICE_ATTR_RO(cmb);
2082
1751e97a
KB		 2083static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2084 char *buf)
2085{
2086 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2087
2088 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2089}
2090static DEVICE_ATTR_RO(cmbloc);
2091
2092static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2093 char *buf)
2094{
2095 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2096
2097 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2098}
2099static DEVICE_ATTR_RO(cmbsz);
2100
a5df5e79
KB		 2101static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2102 char *buf)
2103{
2104 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2105
2106 return sysfs_emit(buf, "%d\n", ndev->hmb);
2107}
2108
2109static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2110 const char *buf, size_t count)
2111{
2112 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2113 bool new;
2114 int ret;
2115
99722c8a 2116 if (kstrtobool(buf, &new) < 0)
a5df5e79
KB		 2117 return -EINVAL;
2118
2119 if (new == ndev->hmb)
2120 return count;
2121
2122 if (new) {
2123 ret = nvme_setup_host_mem(ndev);
2124 } else {
2125 ret = nvme_set_host_mem(ndev, 0);
2126 if (!ret)
2127 nvme_free_host_mem(ndev);
2128 }
2129
2130 if (ret < 0)
2131 return ret;
2132
2133 return count;
2134}
2135static DEVICE_ATTR_RW(hmb);
2136
0521905e
KB		 2137static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2138 struct attribute *a, int n)
2139{
2140 struct nvme_ctrl *ctrl =
2141 dev_get_drvdata(container_of(kobj, struct device, kobj));
2142 struct nvme_dev *dev = to_nvme_dev(ctrl);
2143
1751e97a
KB		 2144 if (a == &dev_attr_cmb.attr ||
2145 a == &dev_attr_cmbloc.attr ||
2146 a == &dev_attr_cmbsz.attr) {
2147 if (!dev->cmbsz)
2148 return 0;
2149 }
a5df5e79
KB		 2150 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2151 return 0;
2152
0521905e
KB		 2153 return a->mode;
2154}
2155
2156static struct attribute *nvme_pci_attrs[] = {
2157 &dev_attr_cmb.attr,
1751e97a
KB		 2158 &dev_attr_cmbloc.attr,
2159 &dev_attr_cmbsz.attr,
a5df5e79 2160 &dev_attr_hmb.attr,
0521905e
KB		 2161 NULL,
2162};
2163
86adbf0c 2164static const struct attribute_group nvme_pci_dev_attrs_group = {
0521905e
KB		 2165 .attrs = nvme_pci_attrs,
2166 .is_visible = nvme_pci_attrs_are_visible,
2167};
2168
86adbf0c
CH		 2169static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2170 &nvme_dev_attrs_group,
2171 &nvme_pci_dev_attrs_group,
2172 NULL,
2173};
2174
e917a849
KB		 2175static void nvme_update_attrs(struct nvme_dev *dev)
2176{
2177 sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group);
2178}
2179
612b7286
ML		 2180/*
2181 * nirqs is the number of interrupts available for write and read
2182 * queues. The core already reserved an interrupt for the admin queue.
2183 */
2184static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2185{
612b7286 2186 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2187 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2188
2189 /*
ee0d96d3 2190 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2191 * the default queue is set to 1. The affinity set size is
2192 * also set to one, but the irq core ignores it for this case.
2193 *
2194 * If only one interrupt is available or 'write_queue' == 0, combine
2195 * write and read queues.
2196 *
2197 * If 'write_queues' > 0, ensure it leaves room for at least one read
2198 * queue.
3b6592f7 2199 */
612b7286
ML		 2200 if (!nrirqs) {
2201 nrirqs = 1;
2202 nr_read_queues = 0;
2a5bcfdd 2203 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2204 nr_read_queues = 0;
2a5bcfdd 2205 } else if (nr_write_queues >= nrirqs) {
612b7286 2206 nr_read_queues = 1;
3b6592f7 2207 } else {
2a5bcfdd 2208 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2209 }
612b7286
ML		 2210
2211 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2212 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2213 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2214 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2215 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2216}
2217
6451fe73 2218static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2219{
2220 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2221 struct irq_affinity affd = {
9cfef55b 2222 .pre_vectors = 1,
612b7286
ML		 2223 .calc_sets = nvme_calc_irq_sets,
2224 .priv = dev,
3b6592f7 2225 };
21cc2f3f 2226 unsigned int irq_queues, poll_queues;
d5887dc6 2227 unsigned int flags = PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY;
6451fe73
JA		 2228
2229 /*
21cc2f3f
JX		 2230 * Poll queues don't need interrupts, but we need at least one I/O queue
2231 * left over for non-polled I/O.
6451fe73 2232 */
21cc2f3f
JX		 2233 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2234 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2235
21cc2f3f
JX		 2236 /*
2237 * Initialize for the single interrupt case, will be updated in
2238 * nvme_calc_irq_sets().
2239 */
612b7286
ML		 2240 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2241 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2242
66341331 2243 /*
21cc2f3f
JX		 2244 * We need interrupts for the admin queue and each non-polled I/O queue,
2245 * but some Apple controllers require all queues to use the first
2246 * vector.
66341331 2247 */
21cc2f3f
JX		 2248 irq_queues = 1;
2249 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2250 irq_queues += (nr_io_queues - poll_queues);
d5887dc6
SA		 2251 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2252 flags &= ~PCI_IRQ_MSI;
2253 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, flags,
2254 &affd);
3b6592f7
JA		 2255}
2256
2a5bcfdd
WZ		 2257static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2258{
e3aef095
NS		 2259 /*
2260 * If tags are shared with admin queue (Apple bug), then
2261 * make sure we only use one IO queue.
2262 */
2263 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2264 return 1;
2a5bcfdd
WZ		 2265 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2266}
2267
8d85fce7 2268static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2269{
147b27e4 2270 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2271 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2272 unsigned int nr_io_queues;
97f6ef64 2273 unsigned long size;
2a5bcfdd 2274 int result;
b60503ba 2275
2a5bcfdd
WZ		 2276 /*
2277 * Sample the module parameters once at reset time so that we have
2278 * stable values to work with.
2279 */
2280 dev->nr_write_queues = write_queues;
2281 dev->nr_poll_queues = poll_queues;
d38e9f04 2282
e3aef095 2283 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2284 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2285 if (result < 0)
1b23484b 2286 return result;
9a0be7ab 2287
f5fa90dc 2288 if (nr_io_queues == 0)
a5229050 2289 return 0;
53dc180e 2290
e4b9852a
CC		 2291 /*
2292 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2293 * from set to unset. If there is a window to it is truely freed,
2294 * pci_free_irq_vectors() jumping into this window will crash.
2295 * And take lock to avoid racing with pci_free_irq_vectors() in
2296 * nvme_dev_disable() path.
2297 */
2298 result = nvme_setup_io_queues_trylock(dev);
2299 if (result)
2300 return result;
2301 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2302 pci_free_irq(pdev, 0, adminq);
b60503ba 2303
0f238ff5 2304 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2305 result = nvme_cmb_qdepth(dev, nr_io_queues,
2306 sizeof(struct nvme_command));
88d356ca 2307 if (result > 0) {
8ffaadf7 2308 dev->q_depth = result;
88d356ca
CH		 2309 dev->ctrl.sqsize = result - 1;
2310 } else {
0f238ff5 2311 dev->cmb_use_sqes = false;
88d356ca 2312 }
8ffaadf7
JD		 2313 }
2314
97f6ef64
XY		 2315 do {
2316 size = db_bar_size(dev, nr_io_queues);
2317 result = nvme_remap_bar(dev, size);
2318 if (!result)
2319 break;
e4b9852a
CC		 2320 if (!--nr_io_queues) {
2321 result = -ENOMEM;
2322 goto out_unlock;
2323 }
97f6ef64
XY		 2324 } while (1);
2325 adminq->q_db = dev->dbs;
f1938f6e 2326
8fae268b 2327 retry:
9d713c2b 2328 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2329 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2330 pci_free_irq(pdev, 0, adminq);
9d713c2b 2331
e32efbfc
JA		 2332 /*
2333 * If we enable msix early due to not intx, disable it again before
2334 * setting up the full range we need.
2335 */
dca51e78 2336 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2337
2338 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2339 if (result <= 0) {
2340 result = -EIO;
2341 goto out_unlock;
2342 }
3b6592f7 2343
22b55601 2344 dev->num_vecs = result;
4b04cc6a 2345 result = max(result - 1, 1);
e20ba6e1 2346 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2347
063a8096
MW		 2348 /*
2349 * Should investigate if there's a performance win from allocating
2350 * more queues than interrupt vectors; it might allow the submission
2351 * path to scale better, even if the receive path is limited by the
2352 * number of interrupts.
2353 */
dca51e78 2354 result = queue_request_irq(adminq);
7c349dde 2355 if (result)
e4b9852a 2356 goto out_unlock;
4e224106 2357 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2358 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2359
2360 result = nvme_create_io_queues(dev);
2361 if (result || dev->online_queues < 2)
2362 return result;
2363
2364 if (dev->online_queues - 1 < dev->max_qid) {
2365 nr_io_queues = dev->online_queues - 1;
7d879c90 2366 nvme_delete_io_queues(dev);
e4b9852a
CC		 2367 result = nvme_setup_io_queues_trylock(dev);
2368 if (result)
2369 return result;
8fae268b
KB		 2370 nvme_suspend_io_queues(dev);
2371 goto retry;
2372 }
2373 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2374 dev->io_queues[HCTX_TYPE_DEFAULT],
2375 dev->io_queues[HCTX_TYPE_READ],
2376 dev->io_queues[HCTX_TYPE_POLL]);
2377 return 0;
e4b9852a
CC		 2378out_unlock:
2379 mutex_unlock(&dev->shutdown_lock);
2380 return result;
b60503ba
MW		 2381}
2382
de671d61
JA		 2383static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2384 blk_status_t error)
a5768aa8 2385{
db3cbfff 2386 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2387
db3cbfff 2388 blk_mq_free_request(req);
d1ed6aa1 2389 complete(&nvmeq->delete_done);
de671d61 2390 return RQ_END_IO_NONE;
a5768aa8
KB		 2391}
2392
de671d61
JA		 2393static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2394 blk_status_t error)
a5768aa8 2395{
db3cbfff 2396 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2397
d1ed6aa1
CH		 2398 if (error)
2399 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff 2400
de671d61 2401 return nvme_del_queue_end(req, error);
a5768aa8
KB		 2402}
2403
db3cbfff 2404static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2405{
db3cbfff
KB		 2406 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2407 struct request *req;
f66e2804 2408 struct nvme_command cmd = { };
bda4e0fb 2409
db3cbfff
KB		 2410 cmd.delete_queue.opcode = opcode;
2411 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2412
e559398f 2413 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2414 if (IS_ERR(req))
2415 return PTR_ERR(req);
e559398f 2416 nvme_init_request(req, &cmd);
bda4e0fb 2417
e2e53086
CH		 2418 if (opcode == nvme_admin_delete_cq)
2419 req->end_io = nvme_del_cq_end;
2420 else
2421 req->end_io = nvme_del_queue_end;
db3cbfff
KB		 2422 req->end_io_data = nvmeq;
2423
d1ed6aa1 2424 init_completion(&nvmeq->delete_done);
e2e53086 2425 blk_execute_rq_nowait(req, false);
db3cbfff 2426 return 0;
bda4e0fb
KB		 2427}
2428
7d879c90 2429static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2430{
5271edd4 2431 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2432 unsigned long timeout;
a5768aa8 2433
db3cbfff 2434 retry:
dc96f938 2435 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2436 while (nr_queues > 0) {
2437 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2438 break;
2439 nr_queues--;
2440 sent++;
db3cbfff 2441 }
d1ed6aa1
CH		 2442 while (sent) {
2443 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2444
2445 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2446 timeout);
2447 if (timeout == 0)
2448 return false;
d1ed6aa1 2449
d1ed6aa1 2450 sent--;
5271edd4
CH		 2451 if (nr_queues)
2452 goto retry;
2453 }
2454 return true;
a5768aa8
KB		 2455}
2456
7d879c90 2457static void nvme_delete_io_queues(struct nvme_dev *dev)
b60503ba 2458{
7d879c90
CH		 2459 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2460 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2461}
2b1b7e78 2462
0da7feaa 2463static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
b60503ba 2464{
2455a4b7 2465 if (dev->io_queues[HCTX_TYPE_POLL])
0da7feaa
CH		 2466 return 3;
2467 if (dev->io_queues[HCTX_TYPE_READ])
2468 return 2;
2469 return 1;
2455a4b7 2470}
949928c1 2471
2455a4b7
CH		 2472static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2473{
2474 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2475 /* free previously allocated queues that are no longer usable */
2476 nvme_free_queues(dev, dev->online_queues);
b60503ba
MW		 2477}
2478
b00a726a 2479static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2480{
b00a726a 2481 int result = -ENOMEM;
e75ec752 2482 struct pci_dev *pdev = to_pci_dev(dev->dev);
d5887dc6 2483 unsigned int flags = PCI_IRQ_ALL_TYPES;
0877cb0d
KB		 2484
2485 if (pci_enable_device_mem(pdev))
2486 return result;
2487
0877cb0d 2488 pci_set_master(pdev);
0877cb0d 2489
7a67cbea 2490 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2491 result = -ENODEV;
b00a726a 2492 goto disable;
0e53d180 2493 }
e32efbfc
JA		 2494
2495 /*
a5229050
KB		 2496 * Some devices and/or platforms don't advertise or work with INTx
2497 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2498 * adjust this later.
e32efbfc 2499 */
d5887dc6
SA		 2500 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2501 flags &= ~PCI_IRQ_MSI;
2502 result = pci_alloc_irq_vectors(pdev, 1, 1, flags);
dca51e78 2503 if (result < 0)
09113abf 2504 goto disable;
e32efbfc 2505
20d0dfe6 2506 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2507
7442ddce 2508 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2509 io_queue_depth);
20d0dfe6 2510 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2511 dev->dbs = dev->bar + 4096;
1f390c1f 2512
66341331
BH		 2513 /*
2514 * Some Apple controllers require a non-standard SQE size.
2515 * Interestingly they also seem to ignore the CC:IOSQES register
2516 * so we don't bother updating it here.
2517 */
2518 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2519 dev->io_sqes = 7;
2520 else
2521 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2522
2523 /*
2524 * Temporary fix for the Apple controller found in the MacBook8,1 and
2525 * some MacBook7,1 to avoid controller resets and data loss.
2526 */
2527 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2528 dev->q_depth = 2;
9bdcfb10
CH		 2529 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2530 "set queue depth=%u to work around controller resets\n",
1f390c1f 2531 dev->q_depth);
d554b5e1
MP		 2532 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2533 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2534 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2535 dev->q_depth = 64;
2536 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2537 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2538 }
2539
d38e9f04
BH		 2540 /*
2541 * Controllers with the shared tags quirk need the IO queue to be
2542 * big enough so that we get 32 tags for the admin queue
2543 */
2544 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2545 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2546 dev->q_depth = NVME_AQ_DEPTH + 2;
2547 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2548 dev->q_depth);
2549 }
88d356ca 2550 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
d38e9f04 2551
f65efd6d 2552 nvme_map_cmb(dev);
202021c1 2553
a0a3408e 2554 pci_save_state(pdev);
a6ee7f19 2555
09113abf
TZ		 2556 result = nvme_pci_configure_admin_queue(dev);
2557 if (result)
2558 goto free_irq;
2559 return result;
0877cb0d 2560
09113abf
TZ		 2561 free_irq:
2562 pci_free_irq_vectors(pdev);
0877cb0d 2563 disable:
0877cb0d
KB		 2564 pci_disable_device(pdev);
2565 return result;
2566}
2567
2568static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2569{
2570 if (dev->bar)
2571 iounmap(dev->bar);
a1f447b3 2572 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2573}
2574
68e81eba 2575static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
0877cb0d 2576{
e75ec752 2577 struct pci_dev *pdev = to_pci_dev(dev->dev);
68e81eba 2578 u32 csts;
e75ec752 2579
68e81eba
CH		 2580 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2581 return true;
2582 if (pdev->error_state != pci_channel_io_normal)
2583 return true;
0877cb0d 2584
68e81eba
CH		 2585 csts = readl(dev->bar + NVME_REG_CSTS);
2586 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
4d115420
KB		 2587}
2588
a5cdb68c 2589static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2590{
e6e7f7ac 2591 enum nvme_ctrl_state state = nvme_ctrl_state(&dev->ctrl);
302ad8cc 2592 struct pci_dev *pdev = to_pci_dev(dev->dev);
68e81eba 2593 bool dead;
22404274 2594
77bf25ea 2595 mutex_lock(&dev->shutdown_lock);
68e81eba 2596 dead = nvme_pci_ctrl_is_dead(dev);
e6e7f7ac 2597 if (state == NVME_CTRL_LIVE || state == NVME_CTRL_RESETTING) {
68e81eba 2598 if (pci_is_enabled(pdev))
302ad8cc 2599 nvme_start_freeze(&dev->ctrl);
68e81eba
CH		 2600 /*
2601 * Give the controller a chance to complete all entered requests
2602 * if doing a safe shutdown.
2603 */
2604 if (!dead && shutdown)
2605 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
c9d3bf88 2606 }
c21377f8 2607
9f27bd70 2608 nvme_quiesce_io_queues(&dev->ctrl);
87ad72a5 2609
64ee0ac0 2610 if (!dead && dev->ctrl.queue_count > 0) {
7d879c90 2611 nvme_delete_io_queues(dev);
47d42d22
CH		 2612 nvme_disable_ctrl(&dev->ctrl, shutdown);
2613 nvme_poll_irqdisable(&dev->queues[0]);
4d115420 2614 }
8fae268b 2615 nvme_suspend_io_queues(dev);
10981f23 2616 nvme_suspend_queue(dev, 0);
c80767f7 2617 pci_free_irq_vectors(pdev);
1ad11eaf 2618 if (pci_is_enabled(pdev))
c80767f7 2619 pci_disable_device(pdev);
fa46c6fb 2620 nvme_reap_pending_cqes(dev);
07836e65 2621
1fcfca78
GL		 2622 nvme_cancel_tagset(&dev->ctrl);
2623 nvme_cancel_admin_tagset(&dev->ctrl);
302ad8cc
KB		 2624
2625 /*
2626 * The driver will not be starting up queues again if shutting down so
2627 * must flush all entered requests to their failed completion to avoid
2628 * deadlocking blk-mq hot-cpu notifier.
2629 */
c8e9e9b7 2630 if (shutdown) {
9f27bd70 2631 nvme_unquiesce_io_queues(&dev->ctrl);
c8e9e9b7 2632 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
9f27bd70 2633 nvme_unquiesce_admin_queue(&dev->ctrl);
c8e9e9b7 2634 }
77bf25ea 2635 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2636}
2637
c1ac9a4b
KB		 2638static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2639{
2640 if (!nvme_wait_reset(&dev->ctrl))
2641 return -EBUSY;
2642 nvme_dev_disable(dev, shutdown);
2643 return 0;
2644}
2645
091b6092
MW		 2646static int nvme_setup_prp_pools(struct nvme_dev *dev)
2647{
e75ec752 2648 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2649 NVME_CTRL_PAGE_SIZE,
2650 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2651 if (!dev->prp_page_pool)
2652 return -ENOMEM;
2653
99802a7a 2654 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2655 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2656 256, 256, 0);
2657 if (!dev->prp_small_pool) {
2658 dma_pool_destroy(dev->prp_page_pool);
2659 return -ENOMEM;
2660 }
091b6092
MW		 2661 return 0;
2662}
2663
2664static void nvme_release_prp_pools(struct nvme_dev *dev)
2665{
2666 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2667 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2668}
2669
081a7d95
CH		 2670static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2671{
7846c1b5 2672 size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS;
081a7d95 2673
081a7d95
CH		 2674 dev->iod_mempool = mempool_create_node(1,
2675 mempool_kmalloc, mempool_kfree,
2676 (void *)alloc_size, GFP_KERNEL,
2677 dev_to_node(dev->dev));
2678 if (!dev->iod_mempool)
2679 return -ENOMEM;
2680 return 0;
2681}
2682
770597ec
KB		 2683static void nvme_free_tagset(struct nvme_dev *dev)
2684{
2685 if (dev->tagset.tags)
0da7feaa 2686 nvme_remove_io_tag_set(&dev->ctrl);
770597ec
KB		 2687 dev->ctrl.tagset = NULL;
2688}
2689
2e87570b 2690/* pairs with nvme_pci_alloc_dev */
1673f1f0 2691static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2692{
1673f1f0 2693 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2694
770597ec 2695 nvme_free_tagset(dev);
253fd4ac
IR		 2696 put_device(dev->dev);
2697 kfree(dev->queues);
5e82e952
KB		 2698 kfree(dev);
2699}
2700
fd634f41 2701static void nvme_reset_work(struct work_struct *work)
5e82e952 2702{
d86c4d8e
CH		 2703 struct nvme_dev *dev =
2704 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2705 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2706 int result;
5e82e952 2707
e6e7f7ac 2708 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_RESETTING) {
7764656b
ZC		 2709 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2710 dev->ctrl.state);
4e69d4da
KB		 2711 result = -ENODEV;
2712 goto out;
e71afda4 2713 }
5e82e952 2714
fd634f41
CH		 2715 /*
2716 * If we're called to reset a live controller first shut it down before
2717 * moving on.
2718 */
b00a726a 2719 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2720 nvme_dev_disable(dev, false);
d6135c3a 2721 nvme_sync_queues(&dev->ctrl);
5e82e952 2722
5c959d73 2723 mutex_lock(&dev->shutdown_lock);
b00a726a 2724 result = nvme_pci_enable(dev);
f0b50732 2725 if (result)
4726bcf3 2726 goto out_unlock;
9f27bd70 2727 nvme_unquiesce_admin_queue(&dev->ctrl);
5c959d73
KB		 2728 mutex_unlock(&dev->shutdown_lock);
2729
2730 /*
2731 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2732 * initializing procedure here.
2733 */
2734 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2735 dev_warn(dev->ctrl.device,
2736 "failed to mark controller CONNECTING\n");
cee6c269 2737 result = -EBUSY;
5c959d73
KB		 2738 goto out;
2739 }
943e942e 2740
94cc781f 2741 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
ce4541f4 2742 if (result)
f58944e2 2743 goto out;
ce4541f4 2744
65a54646 2745 nvme_dbbuf_dma_alloc(dev);
f9f38e33 2746
acb71e53
CH		 2747 result = nvme_setup_host_mem(dev);
2748 if (result < 0)
2749 goto out;
87ad72a5 2750
f0b50732 2751 result = nvme_setup_io_queues(dev);
badc34d4 2752 if (result)
f58944e2 2753 goto out;
f0b50732 2754
2659e57b 2755 /*
eac3ef26
CH		 2756 * Freeze and update the number of I/O queues as thos might have
2757 * changed. If there are no I/O queues left after this reset, keep the
2758 * controller around but remove all namespaces.
2659e57b 2759 */
eac3ef26 2760 if (dev->online_queues > 1) {
06c59d42 2761 nvme_dbbuf_set(dev);
9f27bd70 2762 nvme_unquiesce_io_queues(&dev->ctrl);
302ad8cc 2763 nvme_wait_freeze(&dev->ctrl);
eac3ef26 2764 nvme_pci_update_nr_queues(dev);
302ad8cc 2765 nvme_unfreeze(&dev->ctrl);
3cf519b5 2766 } else {
eac3ef26
CH		 2767 dev_warn(dev->ctrl.device, "IO queues lost\n");
2768 nvme_mark_namespaces_dead(&dev->ctrl);
9f27bd70 2769 nvme_unquiesce_io_queues(&dev->ctrl);
eac3ef26
CH		 2770 nvme_remove_namespaces(&dev->ctrl);
2771 nvme_free_tagset(dev);
3cf519b5
CH		 2772 }
2773
2b1b7e78
JW		 2774 /*
2775 * If only admin queue live, keep it to do further investigation or
2776 * recovery.
2777 */
5d02a5c1 2778 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2779 dev_warn(dev->ctrl.device,
5d02a5c1 2780 "failed to mark controller live state\n");
e71afda4 2781 result = -ENODEV;
bb8d261e
CH		 2782 goto out;
2783 }
92911a55 2784
d09f2b45 2785 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2786 return;
f0b50732 2787
4726bcf3
KB		 2788 out_unlock:
2789 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2790 out:
c7c16c5b
CH		 2791 /*
2792 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2793 * may be holding this pci_dev's device lock.
2794 */
2795 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2796 result);
2797 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2798 nvme_dev_disable(dev, true);
a2b5d544 2799 nvme_sync_queues(&dev->ctrl);
c7c16c5b 2800 nvme_mark_namespaces_dead(&dev->ctrl);
2ab4e5f4 2801 nvme_unquiesce_io_queues(&dev->ctrl);
c7c16c5b 2802 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
9a6b9458
KB		 2803}
2804
1c63dc66 2805static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2806{
1c63dc66 2807 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2808 return 0;
9ca97374
TH		 2809}
2810
5fd4ce1b 2811static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2812{
5fd4ce1b
CH		 2813 writel(val, to_nvme_dev(ctrl)->bar + off);
2814 return 0;
2815}
4cc06521 2816
7fd8930f
CH		 2817static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2818{
3a8ecc93 2819 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2820 return 0;
4cc06521
KB		 2821}
2822
97c12223
KB		 2823static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2824{
2825 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2826
2db24e4a 2827 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2828}
2829
2f0dad17
KB		 2830static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2831{
2832 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2833 struct nvme_subsystem *subsys = ctrl->subsys;
2834
2835 dev_err(ctrl->device,
2836 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2837 pdev->vendor, pdev->device,
2838 nvme_strlen(subsys->model, sizeof(subsys->model)),
2839 subsys->model, nvme_strlen(subsys->firmware_rev,
2840 sizeof(subsys->firmware_rev)),
2841 subsys->firmware_rev);
2842}
2843
2f859441
LG		 2844static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2845{
2846 struct nvme_dev *dev = to_nvme_dev(ctrl);
2847
2848 return dma_pci_p2pdma_supported(dev->dev);
2849}
2850
1c63dc66 2851static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2852 .name = "pcie",
e439bb12 2853 .module = THIS_MODULE,
2f859441 2854 .flags = NVME_F_METADATA_SUPPORTED,
86adbf0c 2855 .dev_attr_groups = nvme_pci_dev_attr_groups,
1c63dc66 2856 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2857 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2858 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2859 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2860 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2861 .get_address = nvme_pci_get_address,
2f0dad17 2862 .print_device_info = nvme_pci_print_device_info,
2f859441 2863 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
1c63dc66 2864};
4cc06521 2865
b00a726a
KB		 2866static int nvme_dev_map(struct nvme_dev *dev)
2867{
b00a726a
KB		 2868 struct pci_dev *pdev = to_pci_dev(dev->dev);
2869
a1f447b3 2870 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2871 return -ENODEV;
2872
97f6ef64 2873 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2874 goto release;
2875
9fa196e7 2876 return 0;
b00a726a 2877 release:
9fa196e7
MG		 2878 pci_release_mem_regions(pdev);
2879 return -ENODEV;
b00a726a
KB		 2880}
2881
8427bbc2 2882static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2883{
2884 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2885 /*
2886 * Several Samsung devices seem to drop off the PCIe bus
2887 * randomly when APST is on and uses the deepest sleep state.
2888 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2889 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2890 * 950 PRO 256GB", but it seems to be restricted to two Dell
2891 * laptops.
2892 */
2893 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2894 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2895 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2896 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2897 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2898 /*
2899 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2900 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2901 * within few minutes after bootup on a Coffee Lake board -
2902 * ASUS PRIME Z370-A
8427bbc2
KHF		 2903 */
2904 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2905 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2906 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2907 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2908 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2909 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2910 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2911 /*
2912 * Forcing to use host managed nvme power settings for
2913 * lowest idle power with quick resume latency on
2914 * Samsung and Toshiba SSDs based on suspend behavior
2915 * on Coffee Lake board for LENOVO C640
2916 */
2917 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2918 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2919 return NVME_QUIRK_SIMPLE_SUSPEND;
107b4e06
GG		 2920 } else if (pdev->vendor == 0x2646 && (pdev->device == 0x2263 ||
2921 pdev->device == 0x500f)) {
2922 /*
2923 * Exclude some Kingston NV1 and A2000 devices from
2924 * NVME_QUIRK_SIMPLE_SUSPEND. Do a full suspend to save a
2925 * lot fo energy with s2idle sleep on some TUXEDO platforms.
2926 */
2927 if (dmi_match(DMI_BOARD_NAME, "NS5X_NS7XAU") ||
2928 dmi_match(DMI_BOARD_NAME, "NS5x_7xAU") ||
2929 dmi_match(DMI_BOARD_NAME, "NS5x_7xPU") ||
2930 dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1"))
2931 return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
ff5350a8
AL		 2932 }
2933
2934 return 0;
2935}
2936
2e87570b
CH		 2937static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2938 const struct pci_device_id *id)
18119775 2939{
ff5350a8 2940 unsigned long quirks = id->driver_data;
2e87570b
CH		 2941 int node = dev_to_node(&pdev->dev);
2942 struct nvme_dev *dev;
2943 int ret = -ENOMEM;
b60503ba 2944
a4aea562 2945 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba 2946 if (!dev)
dc785d69 2947 return ERR_PTR(-ENOMEM);
2e87570b 2948 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2e87570b 2949 mutex_init(&dev->shutdown_lock);
147b27e4 2950
2a5bcfdd
WZ		 2951 dev->nr_write_queues = write_queues;
2952 dev->nr_poll_queues = poll_queues;
2953 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2954 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2955 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba 2956 if (!dev->queues)
2e87570b 2957 goto out_free_dev;
b60503ba 2958
e75ec752 2959 dev->dev = get_device(&pdev->dev);
4cc06521 2960
8427bbc2 2961 quirks |= check_vendor_combination_bug(pdev);
107b4e06
GG		 2962 if (!noacpi &&
2963 !(quirks & NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND) &&
2964 acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 2965 /*
2966 * Some systems use a bios work around to ask for D3 on
2967 * platforms that support kernel managed suspend.
2968 */
2969 dev_info(&pdev->dev,
2970 "platform quirk: setting simple suspend\n");
2971 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2972 }
2e87570b
CH		 2973 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2974 quirks);
2975 if (ret)
2976 goto out_put_device;
924bd96e
CH		 2977
2978 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2979 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
2980 else
2981 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3f30a79c
CH		 2982 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
2983 dma_set_max_seg_size(&pdev->dev, 0xffffffff);
df4f9bc4 2984
943e942e 2985 /*
3f30a79c
CH		 2986 * Limit the max command size to prevent iod->sg allocations going
2987 * over a single page.
943e942e 2988 */
3f30a79c 2989 dev->ctrl.max_hw_sectors = min_t(u32,
3710e2b0 2990 NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9);
3f30a79c 2991 dev->ctrl.max_segments = NVME_MAX_SEGS;
943e942e 2992
3f30a79c
CH		 2993 /*
2994 * There is no support for SGLs for metadata (yet), so we are limited to
2995 * a single integrity segment for the separate metadata pointer.
2996 */
2997 dev->ctrl.max_integrity_segments = 1;
2e87570b 2998 return dev;
df4f9bc4 2999
2e87570b
CH		 3000out_put_device:
3001 put_device(dev->dev);
3002 kfree(dev->queues);
3003out_free_dev:
3004 kfree(dev);
3005 return ERR_PTR(ret);
3006}
943e942e 3007
2e87570b
CH		 3008static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3009{
3010 struct nvme_dev *dev;
3011 int result = -ENOMEM;
3012
3013 dev = nvme_pci_alloc_dev(pdev, id);
dc785d69
IC		 3014 if (IS_ERR(dev))
3015 return PTR_ERR(dev);
2e87570b
CH		 3016
3017 result = nvme_dev_map(dev);
b6e44b4c 3018 if (result)
2e87570b
CH		 3019 goto out_uninit_ctrl;
3020
3021 result = nvme_setup_prp_pools(dev);
081a7d95 3022 if (result)
2e87570b 3023 goto out_dev_unmap;
943e942e 3024
2e87570b 3025 result = nvme_pci_alloc_iod_mempool(dev);
b6e44b4c 3026 if (result)
2e87570b 3027 goto out_release_prp_pools;
b6e44b4c 3028
1b3c47c1
SG		 3029 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3030
eac3ef26
CH		 3031 result = nvme_pci_enable(dev);
3032 if (result)
3033 goto out_release_iod_mempool;
3034
0da7feaa
CH		 3035 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3036 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
eac3ef26
CH		 3037 if (result)
3038 goto out_disable;
3039
3040 /*
3041 * Mark the controller as connecting before sending admin commands to
3042 * allow the timeout handler to do the right thing.
3043 */
3044 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3045 dev_warn(dev->ctrl.device,
3046 "failed to mark controller CONNECTING\n");
3047 result = -EBUSY;
3048 goto out_disable;
3049 }
3050
3051 result = nvme_init_ctrl_finish(&dev->ctrl, false);
3052 if (result)
3053 goto out_disable;
3054
3055 nvme_dbbuf_dma_alloc(dev);
3056
3057 result = nvme_setup_host_mem(dev);
3058 if (result < 0)
3059 goto out_disable;
3060
3061 result = nvme_setup_io_queues(dev);
3062 if (result)
3063 goto out_disable;
4caff8fc 3064
eac3ef26 3065 if (dev->online_queues > 1) {
0da7feaa
CH		 3066 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3067 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
eac3ef26 3068 nvme_dbbuf_set(dev);
eac3ef26
CH		 3069 }
3070
0da7feaa
CH		 3071 if (!dev->ctrl.tagset)
3072 dev_warn(dev->ctrl.device, "IO queues not created\n");
3073
eac3ef26
CH		 3074 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3075 dev_warn(dev->ctrl.device,
3076 "failed to mark controller live state\n");
3077 result = -ENODEV;
3078 goto out_disable;
3079 }
3080
2e87570b 3081 pci_set_drvdata(pdev, dev);
1b3c47c1 3082
eac3ef26
CH		 3083 nvme_start_ctrl(&dev->ctrl);
3084 nvme_put_ctrl(&dev->ctrl);
5a5754a4 3085 flush_work(&dev->ctrl.scan_work);
b60503ba
MW		 3086 return 0;
3087
eac3ef26
CH		 3088out_disable:
3089 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3090 nvme_dev_disable(dev, true);
3091 nvme_free_host_mem(dev);
3092 nvme_dev_remove_admin(dev);
3093 nvme_dbbuf_dma_free(dev);
3094 nvme_free_queues(dev, 0);
3095out_release_iod_mempool:
b6e44b4c 3096 mempool_destroy(dev->iod_mempool);
2e87570b 3097out_release_prp_pools:
091b6092 3098 nvme_release_prp_pools(dev);
2e87570b 3099out_dev_unmap:
b00c9b7a 3100 nvme_dev_unmap(dev);
2e87570b
CH		 3101out_uninit_ctrl:
3102 nvme_uninit_ctrl(&dev->ctrl);
a61d2655 3103 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 3104 return result;
3105}
3106
775755ed 3107static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3108{
a6739479 3109 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3110
3111 /*
3112 * We don't need to check the return value from waiting for the reset
3113 * state as pci_dev device lock is held, making it impossible to race
3114 * with ->remove().
3115 */
3116 nvme_disable_prepare_reset(dev, false);
3117 nvme_sync_queues(&dev->ctrl);
775755ed 3118}
f0d54a54 3119
775755ed
CH		 3120static void nvme_reset_done(struct pci_dev *pdev)
3121{
f263fbb8 3122 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3123
3124 if (!nvme_try_sched_reset(&dev->ctrl))
3125 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3126}
3127
09ece142
KB		 3128static void nvme_shutdown(struct pci_dev *pdev)
3129{
3130 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3131
c1ac9a4b 3132 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3133}
3134
f58944e2
KB		 3135/*
3136 * The driver's remove may be called on a device in a partially initialized
3137 * state. This function must not have any dependencies on the device state in
3138 * order to proceed.
3139 */
8d85fce7 3140static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3141{
3142 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3143
bb8d261e 3144 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3145 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3146
6db28eda 3147 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3148 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3149 nvme_dev_disable(dev, true);
6db28eda 3150 }
0ff9d4e1 3151
d86c4d8e 3152 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3153 nvme_stop_ctrl(&dev->ctrl);
3154 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3155 nvme_dev_disable(dev, true);
87ad72a5 3156 nvme_free_host_mem(dev);
a4aea562 3157 nvme_dev_remove_admin(dev);
c11b7716 3158 nvme_dbbuf_dma_free(dev);
a1a5ef99 3159 nvme_free_queues(dev, 0);
c11b7716 3160 mempool_destroy(dev->iod_mempool);
9a6b9458 3161 nvme_release_prp_pools(dev);
b00a726a 3162 nvme_dev_unmap(dev);
726612b6 3163 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3164}
3165
671a6018 3166#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3167static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3168{
3169 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3170}
3171
3172static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3173{
3174 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3175}
3176
3177static int nvme_resume(struct device *dev)
3178{
3179 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3180 struct nvme_ctrl *ctrl = &ndev->ctrl;
3181
4eaefe8c 3182 if (ndev->last_ps == U32_MAX ||
d916b1be 3183 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3184 goto reset;
3185 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3186 goto reset;
3187
d916b1be 3188 return 0;
e5ad96f3
KB		 3189reset:
3190 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3191}
3192
cd638946
KB		 3193static int nvme_suspend(struct device *dev)
3194{
3195 struct pci_dev *pdev = to_pci_dev(dev);
3196 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3197 struct nvme_ctrl *ctrl = &ndev->ctrl;
3198 int ret = -EBUSY;
3199
4eaefe8c
RW		 3200 ndev->last_ps = U32_MAX;
3201
d916b1be
KB		 3202 /*
3203 * The platform does not remove power for a kernel managed suspend so
3204 * use host managed nvme power settings for lowest idle power if
3205 * possible. This should have quicker resume latency than a full device
3206 * shutdown. But if the firmware is involved after the suspend or the
3207 * device does not support any non-default power states, shut down the
3208 * device fully.
4eaefe8c
RW		 3209 *
3210 * If ASPM is not enabled for the device, shut down the device and allow
3211 * the PCI bus layer to put it into D3 in order to take the PCIe link
3212 * down, so as to allow the platform to achieve its minimum low-power
3213 * state (which may not be possible if the link is up).
d916b1be 3214 */
4eaefe8c 3215 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3216 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3217 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3218 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3219
3220 nvme_start_freeze(ctrl);
3221 nvme_wait_freeze(ctrl);
3222 nvme_sync_queues(ctrl);
3223
e6e7f7ac 3224 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE)
d916b1be
KB		 3225 goto unfreeze;
3226
e5ad96f3
KB		 3227 /*
3228 * Host memory access may not be successful in a system suspend state,
3229 * but the specification allows the controller to access memory in a
3230 * non-operational power state.
3231 */
3232 if (ndev->hmb) {
3233 ret = nvme_set_host_mem(ndev, 0);
3234 if (ret < 0)
3235 goto unfreeze;
3236 }
3237
d916b1be
KB		 3238 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3239 if (ret < 0)
3240 goto unfreeze;
3241
7cbb5c6f
ML		 3242 /*
3243 * A saved state prevents pci pm from generically controlling the
3244 * device's power. If we're using protocol specific settings, we don't
3245 * want pci interfering.
3246 */
3247 pci_save_state(pdev);
3248
d916b1be
KB		 3249 ret = nvme_set_power_state(ctrl, ctrl->npss);
3250 if (ret < 0)
3251 goto unfreeze;
3252
3253 if (ret) {
7cbb5c6f
ML		 3254 /* discard the saved state */
3255 pci_load_saved_state(pdev, NULL);
3256
d916b1be
KB		 3257 /*
3258 * Clearing npss forces a controller reset on resume. The
05d3046f 3259 * correct value will be rediscovered then.
d916b1be 3260 */
c1ac9a4b 3261 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3262 ctrl->npss = 0;
d916b1be 3263 }
d916b1be
KB		 3264unfreeze:
3265 nvme_unfreeze(ctrl);
3266 return ret;
3267}
3268
3269static int nvme_simple_suspend(struct device *dev)
3270{
3271 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3272
c1ac9a4b 3273 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3274}
3275
d916b1be 3276static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3277{
3278 struct pci_dev *pdev = to_pci_dev(dev);
3279 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3280
c1ac9a4b 3281 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3282}
3283
21774222 3284static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3285 .suspend = nvme_suspend,
3286 .resume = nvme_resume,
3287 .freeze = nvme_simple_suspend,
3288 .thaw = nvme_simple_resume,
3289 .poweroff = nvme_simple_suspend,
3290 .restore = nvme_simple_resume,
3291};
3292#endif /* CONFIG_PM_SLEEP */
b60503ba 3293
a0a3408e
KB		 3294static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3295 pci_channel_state_t state)
3296{
3297 struct nvme_dev *dev = pci_get_drvdata(pdev);
3298
3299 /*
3300 * A frozen channel requires a reset. When detected, this method will
3301 * shutdown the controller to quiesce. The controller will be restarted
3302 * after the slot reset through driver's slot_reset callback.
3303 */
a0a3408e
KB		 3304 switch (state) {
3305 case pci_channel_io_normal:
3306 return PCI_ERS_RESULT_CAN_RECOVER;
3307 case pci_channel_io_frozen:
d011fb31
KB		 3308 dev_warn(dev->ctrl.device,
3309 "frozen state error detected, reset controller\n");
71a5bb15
KB		 3310 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
3311 nvme_dev_disable(dev, true);
3312 return PCI_ERS_RESULT_DISCONNECT;
3313 }
a5cdb68c 3314 nvme_dev_disable(dev, false);
a0a3408e
KB		 3315 return PCI_ERS_RESULT_NEED_RESET;
3316 case pci_channel_io_perm_failure:
d011fb31
KB		 3317 dev_warn(dev->ctrl.device,
3318 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3319 return PCI_ERS_RESULT_DISCONNECT;
3320 }
3321 return PCI_ERS_RESULT_NEED_RESET;
3322}
3323
3324static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3325{
3326 struct nvme_dev *dev = pci_get_drvdata(pdev);
3327
1b3c47c1 3328 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3329 pci_restore_state(pdev);
71a5bb15
KB		 3330 if (!nvme_try_sched_reset(&dev->ctrl))
3331 nvme_unquiesce_io_queues(&dev->ctrl);
a0a3408e
KB		 3332 return PCI_ERS_RESULT_RECOVERED;
3333}
3334
3335static void nvme_error_resume(struct pci_dev *pdev)
3336{
72cd4cc2
KB		 3337 struct nvme_dev *dev = pci_get_drvdata(pdev);
3338
3339 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3340}
3341
1d352035 3342static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3343 .error_detected = nvme_error_detected,
b60503ba
MW		 3344 .slot_reset = nvme_slot_reset,
3345 .resume = nvme_error_resume,
775755ed
CH		 3346 .reset_prepare = nvme_reset_prepare,
3347 .reset_done = nvme_reset_done,
b60503ba
MW		 3348};
3349
6eb0d698 3350static const struct pci_device_id nvme_id_table[] = {
972b13e2 3351 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3352 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3353 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3354 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3355 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3356 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3357 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3358 .driver_data = NVME_QUIRK_STRIPE_SIZE |
25e58af4 3359 NVME_QUIRK_DEALLOCATE_ZEROES |
5c3f4066
KB		 3360 NVME_QUIRK_IGNORE_DEV_SUBNQN |
3361 NVME_QUIRK_BOGUS_NID, },
972b13e2 3362 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3363 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3364 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3365 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3366 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3367 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3368 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3369 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3370 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3371 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3372 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e 3373 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
66dd346b
CH		 3374 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3375 NVME_QUIRK_BOGUS_NID, },
3376 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3377 .driver_data = NVME_QUIRK_BOGUS_NID, },
e89086c4
JF		 3378 { PCI_DEVICE(0x126f, 0x2262), /* Silicon Motion generic */
3379 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3380 NVME_QUIRK_BOGUS_NID, },
5bedd3af 3381 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
c98a8793
KB		 3382 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3383 NVME_QUIRK_BOGUS_NID, },
0302ae60 3384 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3385 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3386 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3387 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3388 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3389 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3390 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3391 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3392 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3393 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3394 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3395 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3396 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3397 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3398 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
d5887dc6
SA		 3399 { PCI_DEVICE(0x15b7, 0x5008), /* Sandisk SN530 */
3400 .driver_data = NVME_QUIRK_BROKEN_MSI },
2cf7a77e
KB		 3401 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3402 .driver_data = NVME_QUIRK_BOGUS_NID, },
c9e95c39 3403 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
73029c9b
KB		 3404 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3405 NVME_QUIRK_BOGUS_NID, },
d14c2731
TH		 3406 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3407 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3408 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3409 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6e6a6828
PT		 3410 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3411 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3412 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
e1c70d79
LVS		 3413 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3414 .driver_data = NVME_QUIRK_BOGUS_NID, },
08b903b5 3415 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
1629de0e
PG		 3416 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3417 NVME_QUIRK_BOGUS_NID, },
5f69f009
DW		 3418 { PCI_DEVICE(0x10ec, 0x5763), /* ADATA SX6000PNP */
3419 .driver_data = NVME_QUIRK_BOGUS_NID, },
f03e42c6
GC		 3420 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3421 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3422 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
41f38043
LS		 3423 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3424 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
d5ceb4d1
BH		 3425 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
3426 .driver_data = NVME_QUIRK_BOGUS_NID, },
5611ec2b
KHF		 3427 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3428 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
c4f01a77
KB		 3429 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3430 .driver_data = NVME_QUIRK_BOGUS_NID, },
bd029a02
JL		 3431 { PCI_DEVICE(0x1c5c, 0x1D59), /* SK Hynix BC901 */
3432 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
02ca079c
KHF		 3433 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3434 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3435 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3436 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
43047e08 3437 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
688b419c
AW		 3438 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES |
3439 NVME_QUIRK_BOGUS_NID, },
43047e08 3440 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3441 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
e5bb0988
PR		 3442 { PCI_DEVICE(0x144d, 0xa802), /* Samsung SM953 */
3443 .driver_data = NVME_QUIRK_BOGUS_NID, },
43047e08 3444 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3445 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3446 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3447 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3448 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3449 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3450 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3451 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
bd375fee
HV		 3452 { PCI_DEVICE(0x2646, 0x5013), /* Kingston KC3000, Kingston FURY Renegade */
3453 .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, },
ac9b57d4
XL		 3454 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3455 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3456 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3457 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3458 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3459 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3460 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3461 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3462 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3463 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
9630d806
EMMG		 3464 { PCI_DEVICE(0x1f40, 0x1202), /* Netac Technologies Co. NV3000 NVMe SSD */
3465 .driver_data = NVME_QUIRK_BOGUS_NID, },
8d6e38f6
TDF		 3466 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
3467 .driver_data = NVME_QUIRK_BOGUS_NID, },
70ce3455
CH		 3468 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3469 .driver_data = NVME_QUIRK_BOGUS_NID, },
a98a945b
CH		 3470 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3471 .driver_data = NVME_QUIRK_BOGUS_NID, },
3472 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3473 .driver_data = NVME_QUIRK_BOGUS_NID, },
a3a9d63d
TS		 3474 { PCI_DEVICE(0x1e4B, 0x1602), /* MAXIO MAP1602 */
3475 .driver_data = NVME_QUIRK_BOGUS_NID, },
3765fad5
SR		 3476 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3477 .driver_data = NVME_QUIRK_BOGUS_NID, },
f37527a0
DK		 3478 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3479 .driver_data = NVME_QUIRK_BOGUS_NID, },
d5d3c100
XR		 3480 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3481 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
6b961bce
NW		 3482 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3483 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
d6c52fa3
TG		 3484 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3485 .driver_data = NVME_QUIRK_BOGUS_NID, },
200dccd0
SA		 3486 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3487 .driver_data = NVME_QUIRK_BOGUS_NID, },
b65d44fa
PG		 3488 { PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */
3489 .driver_data = NVME_QUIRK_BOGUS_NID, },
80b26240 3490 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
1231363a
JP		 3491 .driver_data = NVME_QUIRK_BOGUS_NID |
3492 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
74391b3e
DT		 3493 { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
3494 .driver_data = NVME_QUIRK_BOGUS_NID, },
1616d6c3
SG		 3495 { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */
3496 .driver_data = NVME_QUIRK_BOGUS_NID, },
06497281
DS		 3497 { PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */
3498 .driver_data = NVME_QUIRK_BOGUS_NID, },
4bdf2603
FS		 3499 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3500 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3501 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3502 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3503 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3504 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3505 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3506 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3507 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3508 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3509 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3510 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3511 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3512 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3513 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3514 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3515 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3516 NVME_QUIRK_128_BYTES_SQES |
a2941f6a 3517 NVME_QUIRK_SHARED_TAGS |
453116a4
HM		 3518 NVME_QUIRK_SKIP_CID_GEN |
3519 NVME_QUIRK_IDENTIFY_CNS },
0b85f59d 3520 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3521 { 0, }
3522};
3523MODULE_DEVICE_TABLE(pci, nvme_id_table);
3524
3525static struct pci_driver nvme_driver = {
3526 .name = "nvme",
3527 .id_table = nvme_id_table,
3528 .probe = nvme_probe,
8d85fce7 3529 .remove = nvme_remove,
09ece142 3530 .shutdown = nvme_shutdown,
cd638946 3531 .driver = {
eac3ef26
CH		 3532 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3533#ifdef CONFIG_PM_SLEEP
3534 .pm = &nvme_dev_pm_ops,
d916b1be 3535#endif
eac3ef26 3536 },
74d986ab 3537 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3538 .err_handler = &nvme_err_handler,
3539};
3540
3541static int __init nvme_init(void)
3542{
81101540
CH		 3543 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3544 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3545 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3546 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
01df742d 3547 BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE);
7846c1b5
KB		 3548 BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE);
3549 BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS);
17c33167 3550
9a6327d2 3551 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3552}
3553
3554static void __exit nvme_exit(void)
3555{
3556 pci_unregister_driver(&nvme_driver);
03e0f3a6 3557 flush_workqueue(nvme_wq);
b60503ba
MW		 3558}
3559
3560MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3561MODULE_LICENSE("GPL");
c78b4713 3562MODULE_VERSION("1.0");
92b0b0ff 3563MODULE_DESCRIPTION("NVMe host PCIe transport driver");
b60503ba
MW		 3564module_init(nvme_init);
3565module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)