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nvme: move struct nvme_iod to pci.c
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
8de05535 15#include <linux/bitops.h>
b60503ba 16#include <linux/blkdev.h>
a4aea562 17#include <linux/blk-mq.h>
42f61420 18#include <linux/cpu.h>
fd63e9ce 19#include <linux/delay.h>
b60503ba
MW		 20#include <linux/errno.h>
21#include <linux/fs.h>
22#include <linux/genhd.h>
4cc09e2d 23#include <linux/hdreg.h>
5aff9382 24#include <linux/idr.h>
b60503ba
MW		 25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kdev_t.h>
1fa6aead 29#include <linux/kthread.h>
b60503ba 30#include <linux/kernel.h>
a5768aa8 31#include <linux/list_sort.h>
b60503ba
MW		 32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
e1e5e564 40#include <linux/t10-pi.h>
b60503ba 41#include <linux/types.h>
1d277a63 42#include <linux/pr.h>
5d0f6131 43#include <scsi/sg.h>
2f8e2c87 44#include <linux/io-64-nonatomic-lo-hi.h>
1d277a63 45#include <asm/unaligned.h>
797a796a 46
9d99a8dd 47#include <uapi/linux/nvme_ioctl.h>
f11bb3e2
CH		 48#include "nvme.h"
49
b3fffdef 50#define NVME_MINORS (1U << MINORBITS)
9d43cf64 51#define NVME_Q_DEPTH 1024
d31af0a3 52#define NVME_AQ_DEPTH 256
b60503ba
MW		 53#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
54#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 55#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 56#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 57
58static unsigned char admin_timeout = 60;
59module_param(admin_timeout, byte, 0644);
60MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 61
bd67608a
MW		 62unsigned char nvme_io_timeout = 30;
63module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 64MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 65
2484f407
DM		 66static unsigned char shutdown_timeout = 5;
67module_param(shutdown_timeout, byte, 0644);
68MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
69
b60503ba
MW		 70static int nvme_major;
71module_param(nvme_major, int, 0);
72
b3fffdef
KB		 73static int nvme_char_major;
74module_param(nvme_char_major, int, 0);
75
58ffacb5
MW		 76static int use_threaded_interrupts;
77module_param(use_threaded_interrupts, int, 0);
78
8ffaadf7
JD		 79static bool use_cmb_sqes = true;
80module_param(use_cmb_sqes, bool, 0644);
81MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
82
1fa6aead
MW		 83static DEFINE_SPINLOCK(dev_list_lock);
84static LIST_HEAD(dev_list);
85static struct task_struct *nvme_thread;
9a6b9458 86static struct workqueue_struct *nvme_workq;
b9afca3e 87static wait_queue_head_t nvme_kthread_wait;
1fa6aead 88
b3fffdef
KB		 89static struct class *nvme_class;
90
90667892 91static int __nvme_reset(struct nvme_dev *dev);
4cc06521 92static int nvme_reset(struct nvme_dev *dev);
a0fa9647 93static void nvme_process_cq(struct nvme_queue *nvmeq);
3cf519b5 94static void nvme_dead_ctrl(struct nvme_dev *dev);
d4b4ff8e 95
4d115420
KB		 96struct async_cmd_info {
97 struct kthread_work work;
98 struct kthread_worker *worker;
a4aea562 99 struct request *req;
4d115420
KB		 100 u32 result;
101 int status;
102 void *ctx;
103};
1fa6aead 104
b60503ba
MW		 105/*
106 * An NVM Express queue. Each device has at least two (one for admin
107 * commands and one for I/O commands).
108 */
109struct nvme_queue {
110 struct device *q_dmadev;
091b6092 111 struct nvme_dev *dev;
3193f07b 112 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 113 spinlock_t q_lock;
114 struct nvme_command *sq_cmds;
8ffaadf7 115 struct nvme_command __iomem *sq_cmds_io;
b60503ba 116 volatile struct nvme_completion *cqes;
42483228 117 struct blk_mq_tags **tags;
b60503ba
MW		 118 dma_addr_t sq_dma_addr;
119 dma_addr_t cq_dma_addr;
b60503ba
MW		 120 u32 __iomem *q_db;
121 u16 q_depth;
6222d172 122 s16 cq_vector;
b60503ba
MW		 123 u16 sq_head;
124 u16 sq_tail;
125 u16 cq_head;
c30341dc 126 u16 qid;
e9539f47
MW		 127 u8 cq_phase;
128 u8 cqe_seen;
4d115420 129 struct async_cmd_info cmdinfo;
b60503ba
MW		 130};
131
71bd150c
CH		 132/*
133 * The nvme_iod describes the data in an I/O, including the list of PRP
134 * entries. You can't see it in this data structure because C doesn't let
135 * me express that. Use nvme_alloc_iod to ensure there's enough space
136 * allocated to store the PRP list.
137 */
138struct nvme_iod {
139 unsigned long private; /* For the use of the submitter of the I/O */
140 int npages; /* In the PRP list. 0 means small pool in use */
141 int offset; /* Of PRP list */
142 int nents; /* Used in scatterlist */
143 int length; /* Of data, in bytes */
144 dma_addr_t first_dma;
145 struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
146 struct scatterlist sg[0];
147};
148
b60503ba
MW		 149/*
150 * Check we didin't inadvertently grow the command struct
151 */
152static inline void _nvme_check_size(void)
153{
154 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
155 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
156 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
157 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
158 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 159 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 160 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 161 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
162 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
163 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
164 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 165 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 166}
167
edd10d33 168typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 169 struct nvme_completion *);
170
e85248e5 171struct nvme_cmd_info {
c2f5b650
MW		 172 nvme_completion_fn fn;
173 void *ctx;
c30341dc 174 int aborted;
a4aea562 175 struct nvme_queue *nvmeq;
ac3dd5bd 176 struct nvme_iod iod[0];
e85248e5
MW		 177};
178
ac3dd5bd
JA		 179/*
180 * Max size of iod being embedded in the request payload
181 */
182#define NVME_INT_PAGES 2
183#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
fda631ff 184#define NVME_INT_MASK 0x01
ac3dd5bd
JA		 185
186/*
187 * Will slightly overestimate the number of pages needed. This is OK
188 * as it only leads to a small amount of wasted memory for the lifetime of
189 * the I/O.
190 */
191static int nvme_npages(unsigned size, struct nvme_dev *dev)
192{
193 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
194 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
195}
196
197static unsigned int nvme_cmd_size(struct nvme_dev *dev)
198{
199 unsigned int ret = sizeof(struct nvme_cmd_info);
200
201 ret += sizeof(struct nvme_iod);
202 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
203 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
204
205 return ret;
206}
207
a4aea562
MB		 208static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
209 unsigned int hctx_idx)
e85248e5 210{
a4aea562
MB		 211 struct nvme_dev *dev = data;
212 struct nvme_queue *nvmeq = dev->queues[0];
213
42483228
KB		 214 WARN_ON(hctx_idx != 0);
215 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
216 WARN_ON(nvmeq->tags);
217
a4aea562 218 hctx->driver_data = nvmeq;
42483228 219 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 220 return 0;
e85248e5
MW		 221}
222
4af0e21c
KB		 223static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
224{
225 struct nvme_queue *nvmeq = hctx->driver_data;
226
227 nvmeq->tags = NULL;
228}
229
a4aea562
MB		 230static int nvme_admin_init_request(void *data, struct request *req,
231 unsigned int hctx_idx, unsigned int rq_idx,
232 unsigned int numa_node)
22404274 233{
a4aea562
MB		 234 struct nvme_dev *dev = data;
235 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
236 struct nvme_queue *nvmeq = dev->queues[0];
237
238 BUG_ON(!nvmeq);
239 cmd->nvmeq = nvmeq;
240 return 0;
22404274
KB		 241}
242
a4aea562
MB		 243static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
244 unsigned int hctx_idx)
b60503ba 245{
a4aea562 246 struct nvme_dev *dev = data;
42483228 247 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
a4aea562 248
42483228
KB		 249 if (!nvmeq->tags)
250 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 251
42483228 252 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 253 hctx->driver_data = nvmeq;
254 return 0;
b60503ba
MW		 255}
256
a4aea562
MB		 257static int nvme_init_request(void *data, struct request *req,
258 unsigned int hctx_idx, unsigned int rq_idx,
259 unsigned int numa_node)
b60503ba 260{
a4aea562
MB		 261 struct nvme_dev *dev = data;
262 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
263 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
264
265 BUG_ON(!nvmeq);
266 cmd->nvmeq = nvmeq;
267 return 0;
268}
269
270static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
271 nvme_completion_fn handler)
272{
273 cmd->fn = handler;
274 cmd->ctx = ctx;
275 cmd->aborted = 0;
c917dfe5 276 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 277}
278
ac3dd5bd
JA		 279static void *iod_get_private(struct nvme_iod *iod)
280{
281 return (void *) (iod->private & ~0x1UL);
282}
283
284/*
285 * If bit 0 is set, the iod is embedded in the request payload.
286 */
287static bool iod_should_kfree(struct nvme_iod *iod)
288{
fda631ff 289 return (iod->private & NVME_INT_MASK) == 0;
ac3dd5bd
JA		 290}
291
c2f5b650
MW		 292/* Special values must be less than 0x1000 */
293#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 294#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
295#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
296#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 297
edd10d33 298static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 299 struct nvme_completion *cqe)
300{
301 if (ctx == CMD_CTX_CANCELLED)
302 return;
c2f5b650 303 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 304 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 305 "completed id %d twice on queue %d\n",
306 cqe->command_id, le16_to_cpup(&cqe->sq_id));
307 return;
308 }
309 if (ctx == CMD_CTX_INVALID) {
edd10d33 310 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 311 "invalid id %d completed on queue %d\n",
312 cqe->command_id, le16_to_cpup(&cqe->sq_id));
313 return;
314 }
edd10d33 315 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 316}
317
a4aea562 318static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 319{
c2f5b650 320 void *ctx;
b60503ba 321
859361a2 322 if (fn)
a4aea562
MB		 323 *fn = cmd->fn;
324 ctx = cmd->ctx;
325 cmd->fn = special_completion;
326 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 327 return ctx;
b60503ba
MW		 328}
329
a4aea562
MB		 330static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
331 struct nvme_completion *cqe)
3c0cf138 332{
a4aea562
MB		 333 u32 result = le32_to_cpup(&cqe->result);
334 u16 status = le16_to_cpup(&cqe->status) >> 1;
335
336 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
337 ++nvmeq->dev->event_limit;
a5768aa8
KB		 338 if (status != NVME_SC_SUCCESS)
339 return;
340
341 switch (result & 0xff07) {
342 case NVME_AER_NOTICE_NS_CHANGED:
343 dev_info(nvmeq->q_dmadev, "rescanning\n");
344 schedule_work(&nvmeq->dev->scan_work);
345 default:
346 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
347 }
b60503ba
MW		 348}
349
a4aea562
MB		 350static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
351 struct nvme_completion *cqe)
5a92e700 352{
a4aea562
MB		 353 struct request *req = ctx;
354
355 u16 status = le16_to_cpup(&cqe->status) >> 1;
356 u32 result = le32_to_cpup(&cqe->result);
a51afb54 357
42483228 358 blk_mq_free_request(req);
a51afb54 359
a4aea562
MB		 360 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
361 ++nvmeq->dev->abort_limit;
5a92e700
KB		 362}
363
a4aea562
MB		 364static void async_completion(struct nvme_queue *nvmeq, void *ctx,
365 struct nvme_completion *cqe)
b60503ba 366{
a4aea562
MB		 367 struct async_cmd_info *cmdinfo = ctx;
368 cmdinfo->result = le32_to_cpup(&cqe->result);
369 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
370 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
42483228 371 blk_mq_free_request(cmdinfo->req);
b60503ba
MW		 372}
373
a4aea562
MB		 374static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
375 unsigned int tag)
b60503ba 376{
42483228 377 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
a51afb54 378
a4aea562 379 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 380}
381
a4aea562
MB		 382/*
383 * Called with local interrupts disabled and the q_lock held. May not sleep.
384 */
385static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
386 nvme_completion_fn *fn)
4f5099af 387{
a4aea562
MB		 388 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
389 void *ctx;
390 if (tag >= nvmeq->q_depth) {
391 *fn = special_completion;
392 return CMD_CTX_INVALID;
393 }
394 if (fn)
395 *fn = cmd->fn;
396 ctx = cmd->ctx;
397 cmd->fn = special_completion;
398 cmd->ctx = CMD_CTX_COMPLETED;
399 return ctx;
b60503ba
MW		 400}
401
402/**
714a7a22 403 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 404 * @nvmeq: The queue to use
405 * @cmd: The command to send
406 *
407 * Safe to use from interrupt context
408 */
e3f879bf
SB		 409static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
410 struct nvme_command *cmd)
b60503ba 411{
a4aea562
MB		 412 u16 tail = nvmeq->sq_tail;
413
8ffaadf7
JD		 414 if (nvmeq->sq_cmds_io)
415 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
416 else
417 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
418
b60503ba
MW		 419 if (++tail == nvmeq->q_depth)
420 tail = 0;
7547881d 421 writel(tail, nvmeq->q_db);
b60503ba 422 nvmeq->sq_tail = tail;
b60503ba
MW		 423}
424
e3f879bf 425static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
a4aea562
MB		 426{
427 unsigned long flags;
a4aea562 428 spin_lock_irqsave(&nvmeq->q_lock, flags);
e3f879bf 429 __nvme_submit_cmd(nvmeq, cmd);
a4aea562 430 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
a4aea562
MB		 431}
432
eca18b23 433static __le64 **iod_list(struct nvme_iod *iod)
e025344c 434{
eca18b23 435 return ((void *)iod) + iod->offset;
e025344c
SMM		 436}
437
ac3dd5bd
JA		 438static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
439 unsigned nseg, unsigned long private)
eca18b23 440{
ac3dd5bd
JA		 441 iod->private = private;
442 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
443 iod->npages = -1;
444 iod->length = nbytes;
445 iod->nents = 0;
eca18b23 446}
b60503ba 447
eca18b23 448static struct nvme_iod *
ac3dd5bd
JA		 449__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
450 unsigned long priv, gfp_t gfp)
b60503ba 451{
eca18b23 452 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 453 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 454 sizeof(struct scatterlist) * nseg, gfp);
455
ac3dd5bd
JA		 456 if (iod)
457 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 458
459 return iod;
b60503ba
MW		 460}
461
ac3dd5bd
JA		 462static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
463 gfp_t gfp)
464{
465 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
466 sizeof(struct nvme_dsm_range);
ac3dd5bd
JA		 467 struct nvme_iod *iod;
468
469 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
470 size <= NVME_INT_BYTES(dev)) {
471 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
472
473 iod = cmd->iod;
ac3dd5bd 474 iod_init(iod, size, rq->nr_phys_segments,
fda631ff 475 (unsigned long) rq | NVME_INT_MASK);
ac3dd5bd
JA		 476 return iod;
477 }
478
479 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
480 (unsigned long) rq, gfp);
481}
482
d29ec824 483static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 484{
1d090624 485 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 486 int i;
487 __le64 **list = iod_list(iod);
488 dma_addr_t prp_dma = iod->first_dma;
489
490 if (iod->npages == 0)
491 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
492 for (i = 0; i < iod->npages; i++) {
493 __le64 *prp_list = list[i];
494 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
495 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
496 prp_dma = next_prp_dma;
497 }
ac3dd5bd
JA		 498
499 if (iod_should_kfree(iod))
500 kfree(iod);
b60503ba
MW		 501}
502
b4ff9c8d
KB		 503static int nvme_error_status(u16 status)
504{
505 switch (status & 0x7ff) {
506 case NVME_SC_SUCCESS:
507 return 0;
508 case NVME_SC_CAP_EXCEEDED:
509 return -ENOSPC;
510 default:
511 return -EIO;
512 }
513}
514
52b68d7e 515#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 516static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
517{
518 if (be32_to_cpu(pi->ref_tag) == v)
519 pi->ref_tag = cpu_to_be32(p);
520}
521
522static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
523{
524 if (be32_to_cpu(pi->ref_tag) == p)
525 pi->ref_tag = cpu_to_be32(v);
526}
527
528/**
529 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
530 *
531 * The virtual start sector is the one that was originally submitted by the
532 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
533 * start sector may be different. Remap protection information to match the
534 * physical LBA on writes, and back to the original seed on reads.
535 *
536 * Type 0 and 3 do not have a ref tag, so no remapping required.
537 */
538static void nvme_dif_remap(struct request *req,
539 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
540{
541 struct nvme_ns *ns = req->rq_disk->private_data;
542 struct bio_integrity_payload *bip;
543 struct t10_pi_tuple *pi;
544 void *p, *pmap;
545 u32 i, nlb, ts, phys, virt;
546
547 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
548 return;
549
550 bip = bio_integrity(req->bio);
551 if (!bip)
552 return;
553
554 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 555
556 p = pmap;
557 virt = bip_get_seed(bip);
558 phys = nvme_block_nr(ns, blk_rq_pos(req));
559 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
ac6fc48c 560 ts = ns->disk->queue->integrity.tuple_size;
e1e5e564
KB		 561
562 for (i = 0; i < nlb; i++, virt++, phys++) {
563 pi = (struct t10_pi_tuple *)p;
564 dif_swap(phys, virt, pi);
565 p += ts;
566 }
567 kunmap_atomic(pmap);
568}
569
52b68d7e
KB		 570static void nvme_init_integrity(struct nvme_ns *ns)
571{
572 struct blk_integrity integrity;
573
574 switch (ns->pi_type) {
575 case NVME_NS_DPS_PI_TYPE3:
0f8087ec 576 integrity.profile = &t10_pi_type3_crc;
52b68d7e
KB		 577 break;
578 case NVME_NS_DPS_PI_TYPE1:
579 case NVME_NS_DPS_PI_TYPE2:
0f8087ec 580 integrity.profile = &t10_pi_type1_crc;
52b68d7e
KB		 581 break;
582 default:
4125a09b 583 integrity.profile = NULL;
52b68d7e
KB		 584 break;
585 }
586 integrity.tuple_size = ns->ms;
587 blk_integrity_register(ns->disk, &integrity);
588 blk_queue_max_integrity_segments(ns->queue, 1);
589}
590#else /* CONFIG_BLK_DEV_INTEGRITY */
591static void nvme_dif_remap(struct request *req,
592 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
593{
594}
595static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
596{
597}
598static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
599{
600}
601static void nvme_init_integrity(struct nvme_ns *ns)
602{
603}
604#endif
605
a4aea562 606static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 607 struct nvme_completion *cqe)
608{
eca18b23 609 struct nvme_iod *iod = ctx;
ac3dd5bd 610 struct request *req = iod_get_private(iod);
a4aea562 611 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
b60503ba 612 u16 status = le16_to_cpup(&cqe->status) >> 1;
0dfc70c3 613 bool requeue = false;
81c04b94 614 int error = 0;
b60503ba 615
edd10d33 616 if (unlikely(status)) {
a4aea562
MB		 617 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
618 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 619 unsigned long flags;
620
0dfc70c3 621 requeue = true;
a4aea562 622 blk_mq_requeue_request(req);
c9d3bf88
KB		 623 spin_lock_irqsave(req->q->queue_lock, flags);
624 if (!blk_queue_stopped(req->q))
625 blk_mq_kick_requeue_list(req->q);
626 spin_unlock_irqrestore(req->q->queue_lock, flags);
0dfc70c3 627 goto release_iod;
edd10d33 628 }
f4829a9b 629
d29ec824 630 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
17188bb4 631 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
81c04b94
CH		 632 error = -EINTR;
633 else
634 error = status;
d29ec824 635 } else {
81c04b94 636 error = nvme_error_status(status);
d29ec824 637 }
f4829a9b
CH		 638 }
639
a0a931d6
KB		 640 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
641 u32 result = le32_to_cpup(&cqe->result);
642 req->special = (void *)(uintptr_t)result;
643 }
a4aea562
MB		 644
645 if (cmd_rq->aborted)
e75ec752 646 dev_warn(nvmeq->dev->dev,
a4aea562 647 "completing aborted command with status:%04x\n",
81c04b94 648 error);
a4aea562 649
0dfc70c3 650release_iod:
e1e5e564 651 if (iod->nents) {
e75ec752 652 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
a4aea562 653 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
e1e5e564
KB		 654 if (blk_integrity_rq(req)) {
655 if (!rq_data_dir(req))
656 nvme_dif_remap(req, nvme_dif_complete);
e75ec752 657 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
e1e5e564
KB		 658 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
659 }
660 }
edd10d33 661 nvme_free_iod(nvmeq->dev, iod);
3291fa57 662
0dfc70c3
KB		 663 if (likely(!requeue))
664 blk_mq_complete_request(req, error);
b60503ba
MW		 665}
666
184d2944 667/* length is in bytes. gfp flags indicates whether we may sleep. */
d29ec824
CH		 668static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
669 int total_len, gfp_t gfp)
ff22b54f 670{
99802a7a 671 struct dma_pool *pool;
eca18b23
MW		 672 int length = total_len;
673 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 674 int dma_len = sg_dma_len(sg);
675 u64 dma_addr = sg_dma_address(sg);
f137e0f1
MI		 676 u32 page_size = dev->page_size;
677 int offset = dma_addr & (page_size - 1);
e025344c 678 __le64 *prp_list;
eca18b23 679 __le64 **list = iod_list(iod);
e025344c 680 dma_addr_t prp_dma;
eca18b23 681 int nprps, i;
ff22b54f 682
1d090624 683 length -= (page_size - offset);
ff22b54f 684 if (length <= 0)
eca18b23 685 return total_len;
ff22b54f 686
1d090624 687 dma_len -= (page_size - offset);
ff22b54f 688 if (dma_len) {
1d090624 689 dma_addr += (page_size - offset);
ff22b54f
MW		 690 } else {
691 sg = sg_next(sg);
692 dma_addr = sg_dma_address(sg);
693 dma_len = sg_dma_len(sg);
694 }
695
1d090624 696 if (length <= page_size) {
edd10d33 697 iod->first_dma = dma_addr;
eca18b23 698 return total_len;
e025344c
SMM		 699 }
700
1d090624 701 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 702 if (nprps <= (256 / 8)) {
703 pool = dev->prp_small_pool;
eca18b23 704 iod->npages = 0;
99802a7a
MW		 705 } else {
706 pool = dev->prp_page_pool;
eca18b23 707 iod->npages = 1;
99802a7a
MW		 708 }
709
b77954cb
MW		 710 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
711 if (!prp_list) {
edd10d33 712 iod->first_dma = dma_addr;
eca18b23 713 iod->npages = -1;
1d090624 714 return (total_len - length) + page_size;
b77954cb 715 }
eca18b23
MW		 716 list[0] = prp_list;
717 iod->first_dma = prp_dma;
e025344c
SMM		 718 i = 0;
719 for (;;) {
1d090624 720 if (i == page_size >> 3) {
e025344c 721 __le64 *old_prp_list = prp_list;
b77954cb 722 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 723 if (!prp_list)
724 return total_len - length;
725 list[iod->npages++] = prp_list;
7523d834
MW		 726 prp_list[0] = old_prp_list[i - 1];
727 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
728 i = 1;
e025344c
SMM		 729 }
730 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 731 dma_len -= page_size;
732 dma_addr += page_size;
733 length -= page_size;
e025344c
SMM		 734 if (length <= 0)
735 break;
736 if (dma_len > 0)
737 continue;
738 BUG_ON(dma_len < 0);
739 sg = sg_next(sg);
740 dma_addr = sg_dma_address(sg);
741 dma_len = sg_dma_len(sg);
ff22b54f
MW		 742 }
743
eca18b23 744 return total_len;
ff22b54f
MW		 745}
746
d29ec824
CH		 747static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
748 struct nvme_iod *iod)
749{
498c4394 750 struct nvme_command cmnd;
d29ec824 751
498c4394
JD		 752 memcpy(&cmnd, req->cmd, sizeof(cmnd));
753 cmnd.rw.command_id = req->tag;
d29ec824 754 if (req->nr_phys_segments) {
498c4394
JD		 755 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
756 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
d29ec824
CH		 757 }
758
498c4394 759 __nvme_submit_cmd(nvmeq, &cmnd);
d29ec824
CH		 760}
761
a4aea562
MB		 762/*
763 * We reuse the small pool to allocate the 16-byte range here as it is not
764 * worth having a special pool for these or additional cases to handle freeing
765 * the iod.
766 */
767static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
768 struct request *req, struct nvme_iod *iod)
0e5e4f0e 769{
edd10d33
KB		 770 struct nvme_dsm_range *range =
771 (struct nvme_dsm_range *)iod_list(iod)[0];
498c4394 772 struct nvme_command cmnd;
0e5e4f0e 773
0e5e4f0e 774 range->cattr = cpu_to_le32(0);
a4aea562
MB		 775 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
776 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e 777
498c4394
JD		 778 memset(&cmnd, 0, sizeof(cmnd));
779 cmnd.dsm.opcode = nvme_cmd_dsm;
780 cmnd.dsm.command_id = req->tag;
781 cmnd.dsm.nsid = cpu_to_le32(ns->ns_id);
782 cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma);
783 cmnd.dsm.nr = 0;
784 cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
0e5e4f0e 785
498c4394 786 __nvme_submit_cmd(nvmeq, &cmnd);
0e5e4f0e
KB		 787}
788
a4aea562 789static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 790 int cmdid)
791{
498c4394 792 struct nvme_command cmnd;
00df5cb4 793
498c4394
JD		 794 memset(&cmnd, 0, sizeof(cmnd));
795 cmnd.common.opcode = nvme_cmd_flush;
796 cmnd.common.command_id = cmdid;
797 cmnd.common.nsid = cpu_to_le32(ns->ns_id);
00df5cb4 798
498c4394 799 __nvme_submit_cmd(nvmeq, &cmnd);
00df5cb4
MW		 800}
801
a4aea562
MB		 802static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
803 struct nvme_ns *ns)
b60503ba 804{
ac3dd5bd 805 struct request *req = iod_get_private(iod);
498c4394 806 struct nvme_command cmnd;
a4aea562
MB		 807 u16 control = 0;
808 u32 dsmgmt = 0;
00df5cb4 809
a4aea562 810 if (req->cmd_flags & REQ_FUA)
b60503ba 811 control |= NVME_RW_FUA;
a4aea562 812 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 813 control |= NVME_RW_LR;
814
a4aea562 815 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 816 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
817
498c4394
JD		 818 memset(&cmnd, 0, sizeof(cmnd));
819 cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
820 cmnd.rw.command_id = req->tag;
821 cmnd.rw.nsid = cpu_to_le32(ns->ns_id);
822 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
823 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
824 cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
825 cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
b60503ba 826
e19b127f 827 if (ns->ms) {
e1e5e564
KB		 828 switch (ns->pi_type) {
829 case NVME_NS_DPS_PI_TYPE3:
830 control |= NVME_RW_PRINFO_PRCHK_GUARD;
831 break;
832 case NVME_NS_DPS_PI_TYPE1:
833 case NVME_NS_DPS_PI_TYPE2:
834 control |= NVME_RW_PRINFO_PRCHK_GUARD |
835 NVME_RW_PRINFO_PRCHK_REF;
498c4394 836 cmnd.rw.reftag = cpu_to_le32(
e1e5e564
KB		 837 nvme_block_nr(ns, blk_rq_pos(req)));
838 break;
839 }
e19b127f
AP		 840 if (blk_integrity_rq(req))
841 cmnd.rw.metadata =
842 cpu_to_le64(sg_dma_address(iod->meta_sg));
843 else
844 control |= NVME_RW_PRINFO_PRACT;
845 }
e1e5e564 846
498c4394
JD		 847 cmnd.rw.control = cpu_to_le16(control);
848 cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 849
498c4394 850 __nvme_submit_cmd(nvmeq, &cmnd);
b60503ba 851
1974b1ae 852 return 0;
edd10d33
KB		 853}
854
d29ec824
CH		 855/*
856 * NOTE: ns is NULL when called on the admin queue.
857 */
a4aea562
MB		 858static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
859 const struct blk_mq_queue_data *bd)
edd10d33 860{
a4aea562
MB		 861 struct nvme_ns *ns = hctx->queue->queuedata;
862 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 863 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 864 struct request *req = bd->rq;
865 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 866 struct nvme_iod *iod;
a4aea562 867 enum dma_data_direction dma_dir;
edd10d33 868
e1e5e564
KB		 869 /*
870 * If formated with metadata, require the block layer provide a buffer
871 * unless this namespace is formated such that the metadata can be
872 * stripped/generated by the controller with PRACT=1.
873 */
d29ec824 874 if (ns && ns->ms && !blk_integrity_rq(req)) {
71feb364
KB		 875 if (!(ns->pi_type && ns->ms == 8) &&
876 req->cmd_type != REQ_TYPE_DRV_PRIV) {
f4829a9b 877 blk_mq_complete_request(req, -EFAULT);
e1e5e564
KB		 878 return BLK_MQ_RQ_QUEUE_OK;
879 }
880 }
881
d29ec824 882 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
edd10d33 883 if (!iod)
fe54303e 884 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 885
a4aea562 886 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 887 void *range;
888 /*
889 * We reuse the small pool to allocate the 16-byte range here
890 * as it is not worth having a special pool for these or
891 * additional cases to handle freeing the iod.
892 */
d29ec824 893 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
edd10d33 894 &iod->first_dma);
a4aea562 895 if (!range)
fe54303e 896 goto retry_cmd;
edd10d33
KB		 897 iod_list(iod)[0] = (__le64 *)range;
898 iod->npages = 0;
ac3dd5bd 899 } else if (req->nr_phys_segments) {
a4aea562
MB		 900 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
901
ac3dd5bd 902 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 903 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 904 if (!iod->nents)
905 goto error_cmd;
a4aea562
MB		 906
907 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 908 goto retry_cmd;
a4aea562 909
fe54303e 910 if (blk_rq_bytes(req) !=
d29ec824
CH		 911 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
912 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
fe54303e
JA		 913 goto retry_cmd;
914 }
e1e5e564 915 if (blk_integrity_rq(req)) {
bf508e91
CH		 916 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1) {
917 dma_unmap_sg(dev->dev, iod->sg, iod->nents,
918 dma_dir);
e1e5e564 919 goto error_cmd;
bf508e91 920 }
e1e5e564
KB		 921
922 sg_init_table(iod->meta_sg, 1);
923 if (blk_rq_map_integrity_sg(
bf508e91
CH		 924 req->q, req->bio, iod->meta_sg) != 1) {
925 dma_unmap_sg(dev->dev, iod->sg, iod->nents,
926 dma_dir);
e1e5e564 927 goto error_cmd;
bf508e91 928 }
e1e5e564
KB		 929
930 if (rq_data_dir(req))
931 nvme_dif_remap(req, nvme_dif_prep);
932
bf508e91
CH		 933 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir)) {
934 dma_unmap_sg(dev->dev, iod->sg, iod->nents,
935 dma_dir);
e1e5e564 936 goto error_cmd;
bf508e91 937 }
e1e5e564 938 }
edd10d33 939 }
1974b1ae 940
9af8785a 941 nvme_set_info(cmd, iod, req_completion);
a4aea562 942 spin_lock_irq(&nvmeq->q_lock);
d29ec824
CH		 943 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
944 nvme_submit_priv(nvmeq, req, iod);
945 else if (req->cmd_flags & REQ_DISCARD)
a4aea562
MB		 946 nvme_submit_discard(nvmeq, ns, req, iod);
947 else if (req->cmd_flags & REQ_FLUSH)
948 nvme_submit_flush(nvmeq, ns, req->tag);
949 else
950 nvme_submit_iod(nvmeq, iod, ns);
951
952 nvme_process_cq(nvmeq);
953 spin_unlock_irq(&nvmeq->q_lock);
954 return BLK_MQ_RQ_QUEUE_OK;
955
fe54303e 956 error_cmd:
d29ec824 957 nvme_free_iod(dev, iod);
fe54303e
JA		 958 return BLK_MQ_RQ_QUEUE_ERROR;
959 retry_cmd:
d29ec824 960 nvme_free_iod(dev, iod);
fe54303e 961 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 962}
963
a0fa9647 964static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
b60503ba 965{
82123460 966 u16 head, phase;
b60503ba 967
b60503ba 968 head = nvmeq->cq_head;
82123460 969 phase = nvmeq->cq_phase;
b60503ba
MW		 970
971 for (;;) {
c2f5b650
MW		 972 void *ctx;
973 nvme_completion_fn fn;
b60503ba 974 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 975 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 976 break;
977 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
978 if (++head == nvmeq->q_depth) {
979 head = 0;
82123460 980 phase = !phase;
b60503ba 981 }
a0fa9647
JA		 982 if (tag && *tag == cqe.command_id)
983 *tag = -1;
a4aea562 984 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 985 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 986 }
987
988 /* If the controller ignores the cq head doorbell and continuously
989 * writes to the queue, it is theoretically possible to wrap around
990 * the queue twice and mistakenly return IRQ_NONE. Linux only
991 * requires that 0.1% of your interrupts are handled, so this isn't
992 * a big problem.
993 */
82123460 994 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
a0fa9647 995 return;
b60503ba 996
604e8c8d
KB		 997 if (likely(nvmeq->cq_vector >= 0))
998 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 999 nvmeq->cq_head = head;
82123460 1000 nvmeq->cq_phase = phase;
b60503ba 1001
e9539f47 1002 nvmeq->cqe_seen = 1;
a0fa9647
JA		 1003}
1004
1005static void nvme_process_cq(struct nvme_queue *nvmeq)
1006{
1007 __nvme_process_cq(nvmeq, NULL);
b60503ba
MW		 1008}
1009
1010static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 1011{
1012 irqreturn_t result;
1013 struct nvme_queue *nvmeq = data;
1014 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 1015 nvme_process_cq(nvmeq);
1016 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
1017 nvmeq->cqe_seen = 0;
58ffacb5
MW		 1018 spin_unlock(&nvmeq->q_lock);
1019 return result;
1020}
1021
1022static irqreturn_t nvme_irq_check(int irq, void *data)
1023{
1024 struct nvme_queue *nvmeq = data;
1025 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
1026 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
1027 return IRQ_NONE;
1028 return IRQ_WAKE_THREAD;
1029}
1030
a0fa9647
JA		 1031static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1032{
1033 struct nvme_queue *nvmeq = hctx->driver_data;
1034
1035 if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
1036 nvmeq->cq_phase) {
1037 spin_lock_irq(&nvmeq->q_lock);
1038 __nvme_process_cq(nvmeq, &tag);
1039 spin_unlock_irq(&nvmeq->q_lock);
1040
1041 if (tag == -1)
1042 return 1;
1043 }
1044
1045 return 0;
1046}
1047
b60503ba
MW		 1048/*
1049 * Returns 0 on success. If the result is negative, it's a Linux error code;
1050 * if the result is positive, it's an NVM Express status code
1051 */
d29ec824
CH		 1052int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1053 void *buffer, void __user *ubuffer, unsigned bufflen,
1054 u32 *result, unsigned timeout)
b60503ba 1055{
d29ec824
CH		 1056 bool write = cmd->common.opcode & 1;
1057 struct bio *bio = NULL;
f705f837 1058 struct request *req;
d29ec824 1059 int ret;
b60503ba 1060
6f3b0e8b 1061 req = blk_mq_alloc_request(q, write, 0);
f705f837
CH		 1062 if (IS_ERR(req))
1063 return PTR_ERR(req);
b60503ba 1064
d29ec824 1065 req->cmd_type = REQ_TYPE_DRV_PRIV;
e112af0d 1066 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d29ec824
CH		 1067 req->__data_len = 0;
1068 req->__sector = (sector_t) -1;
1069 req->bio = req->biotail = NULL;
b60503ba 1070
f4ff414a 1071 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
a4aea562 1072
d29ec824
CH		 1073 req->cmd = (unsigned char *)cmd;
1074 req->cmd_len = sizeof(struct nvme_command);
a0a931d6 1075 req->special = (void *)0;
b60503ba 1076
d29ec824 1077 if (buffer && bufflen) {
71baba4b
MG		 1078 ret = blk_rq_map_kern(q, req, buffer, bufflen,
1079 __GFP_DIRECT_RECLAIM);
d29ec824
CH		 1080 if (ret)
1081 goto out;
1082 } else if (ubuffer && bufflen) {
71baba4b
MG		 1083 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
1084 __GFP_DIRECT_RECLAIM);
d29ec824
CH		 1085 if (ret)
1086 goto out;
1087 bio = req->bio;
1088 }
3c0cf138 1089
d29ec824
CH		 1090 blk_execute_rq(req->q, NULL, req, 0);
1091 if (bio)
1092 blk_rq_unmap_user(bio);
b60503ba 1093 if (result)
a0a931d6 1094 *result = (u32)(uintptr_t)req->special;
d29ec824
CH		 1095 ret = req->errors;
1096 out:
f705f837 1097 blk_mq_free_request(req);
d29ec824 1098 return ret;
f705f837
CH		 1099}
1100
d29ec824
CH		 1101int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1102 void *buffer, unsigned bufflen)
f705f837 1103{
d29ec824 1104 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
b60503ba
MW		 1105}
1106
a4aea562
MB		 1107static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1108{
1109 struct nvme_queue *nvmeq = dev->queues[0];
1110 struct nvme_command c;
1111 struct nvme_cmd_info *cmd_info;
1112 struct request *req;
1113
6f3b0e8b
CH		 1114 req = blk_mq_alloc_request(dev->admin_q, WRITE,
1115 BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED);
9f173b33
DC		 1116 if (IS_ERR(req))
1117 return PTR_ERR(req);
a4aea562 1118
c917dfe5 1119 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562 1120 cmd_info = blk_mq_rq_to_pdu(req);
1efccc9d 1121 nvme_set_info(cmd_info, NULL, async_req_completion);
a4aea562
MB		 1122
1123 memset(&c, 0, sizeof(c));
1124 c.common.opcode = nvme_admin_async_event;
1125 c.common.command_id = req->tag;
1126
42483228 1127 blk_mq_free_request(req);
e3f879bf
SB		 1128 __nvme_submit_cmd(nvmeq, &c);
1129 return 0;
a4aea562
MB		 1130}
1131
1132static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 1133 struct nvme_command *cmd,
1134 struct async_cmd_info *cmdinfo, unsigned timeout)
1135{
a4aea562
MB		 1136 struct nvme_queue *nvmeq = dev->queues[0];
1137 struct request *req;
1138 struct nvme_cmd_info *cmd_rq;
4d115420 1139
6f3b0e8b 1140 req = blk_mq_alloc_request(dev->admin_q, WRITE, 0);
9f173b33
DC		 1141 if (IS_ERR(req))
1142 return PTR_ERR(req);
a4aea562
MB		 1143
1144 req->timeout = timeout;
1145 cmd_rq = blk_mq_rq_to_pdu(req);
1146 cmdinfo->req = req;
1147 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 1148 cmdinfo->status = -EINTR;
a4aea562
MB		 1149
1150 cmd->common.command_id = req->tag;
1151
e3f879bf
SB		 1152 nvme_submit_cmd(nvmeq, cmd);
1153 return 0;
4d115420
KB		 1154}
1155
b60503ba
MW		 1156static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1157{
b60503ba
MW		 1158 struct nvme_command c;
1159
1160 memset(&c, 0, sizeof(c));
1161 c.delete_queue.opcode = opcode;
1162 c.delete_queue.qid = cpu_to_le16(id);
1163
d29ec824 1164 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1165}
1166
1167static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1168 struct nvme_queue *nvmeq)
1169{
b60503ba
MW		 1170 struct nvme_command c;
1171 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1172
d29ec824
CH		 1173 /*
1174 * Note: we (ab)use the fact the the prp fields survive if no data
1175 * is attached to the request.
1176 */
b60503ba
MW		 1177 memset(&c, 0, sizeof(c));
1178 c.create_cq.opcode = nvme_admin_create_cq;
1179 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1180 c.create_cq.cqid = cpu_to_le16(qid);
1181 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1182 c.create_cq.cq_flags = cpu_to_le16(flags);
1183 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1184
d29ec824 1185 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1186}
1187
1188static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1189 struct nvme_queue *nvmeq)
1190{
b60503ba
MW		 1191 struct nvme_command c;
1192 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1193
d29ec824
CH		 1194 /*
1195 * Note: we (ab)use the fact the the prp fields survive if no data
1196 * is attached to the request.
1197 */
b60503ba
MW		 1198 memset(&c, 0, sizeof(c));
1199 c.create_sq.opcode = nvme_admin_create_sq;
1200 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1201 c.create_sq.sqid = cpu_to_le16(qid);
1202 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1203 c.create_sq.sq_flags = cpu_to_le16(flags);
1204 c.create_sq.cqid = cpu_to_le16(qid);
1205
d29ec824 1206 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1207}
1208
1209static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1210{
1211 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1212}
1213
1214static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1215{
1216 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1217}
1218
d29ec824 1219int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
bc5fc7e4 1220{
e44ac588 1221 struct nvme_command c = { };
d29ec824 1222 int error;
bc5fc7e4 1223
e44ac588
AM		 1224 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1225 c.identify.opcode = nvme_admin_identify;
1226 c.identify.cns = cpu_to_le32(1);
1227
d29ec824
CH		 1228 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1229 if (!*id)
1230 return -ENOMEM;
bc5fc7e4 1231
d29ec824
CH		 1232 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1233 sizeof(struct nvme_id_ctrl));
1234 if (error)
1235 kfree(*id);
1236 return error;
1237}
1238
1239int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1240 struct nvme_id_ns **id)
1241{
e44ac588 1242 struct nvme_command c = { };
d29ec824 1243 int error;
bc5fc7e4 1244
e44ac588
AM		 1245 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1246 c.identify.opcode = nvme_admin_identify,
1247 c.identify.nsid = cpu_to_le32(nsid),
1248
d29ec824
CH		 1249 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1250 if (!*id)
1251 return -ENOMEM;
1252
1253 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1254 sizeof(struct nvme_id_ns));
1255 if (error)
1256 kfree(*id);
1257 return error;
bc5fc7e4
MW		 1258}
1259
5d0f6131 1260int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1261 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1262{
1263 struct nvme_command c;
1264
1265 memset(&c, 0, sizeof(c));
1266 c.features.opcode = nvme_admin_get_features;
a42cecce 1267 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1268 c.features.prp1 = cpu_to_le64(dma_addr);
1269 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1270
d29ec824
CH		 1271 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1272 result, 0);
df348139
MW		 1273}
1274
5d0f6131
VV		 1275int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1276 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1277{
1278 struct nvme_command c;
1279
1280 memset(&c, 0, sizeof(c));
1281 c.features.opcode = nvme_admin_set_features;
1282 c.features.prp1 = cpu_to_le64(dma_addr);
1283 c.features.fid = cpu_to_le32(fid);
1284 c.features.dword11 = cpu_to_le32(dword11);
1285
d29ec824
CH		 1286 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1287 result, 0);
1288}
1289
1290int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1291{
e44ac588
AM		 1292 struct nvme_command c = { };
1293 int error;
1294
1295 c.common.opcode = nvme_admin_get_log_page,
1296 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
1297 c.common.cdw10[0] = cpu_to_le32(
d29ec824
CH		 1298 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1299 NVME_LOG_SMART),
d29ec824
CH		 1300
1301 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1302 if (!*log)
1303 return -ENOMEM;
1304
1305 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1306 sizeof(struct nvme_smart_log));
1307 if (error)
1308 kfree(*log);
1309 return error;
bc5fc7e4
MW		 1310}
1311
c30341dc 1312/**
a4aea562 1313 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1314 *
1315 * Schedule controller reset if the command was already aborted once before and
1316 * still hasn't been returned to the driver, or if this is the admin queue.
1317 */
a4aea562 1318static void nvme_abort_req(struct request *req)
c30341dc 1319{
a4aea562
MB		 1320 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1321 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1322 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1323 struct request *abort_req;
1324 struct nvme_cmd_info *abort_cmd;
1325 struct nvme_command cmd;
c30341dc 1326
a4aea562 1327 if (!nvmeq->qid || cmd_rq->aborted) {
90667892
CH		 1328 spin_lock(&dev_list_lock);
1329 if (!__nvme_reset(dev)) {
1330 dev_warn(dev->dev,
1331 "I/O %d QID %d timeout, reset controller\n",
1332 req->tag, nvmeq->qid);
1333 }
1334 spin_unlock(&dev_list_lock);
c30341dc
KB		 1335 return;
1336 }
1337
1338 if (!dev->abort_limit)
1339 return;
1340
6f3b0e8b
CH		 1341 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE,
1342 BLK_MQ_REQ_NOWAIT);
9f173b33 1343 if (IS_ERR(abort_req))
c30341dc
KB		 1344 return;
1345
a4aea562
MB		 1346 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1347 nvme_set_info(abort_cmd, abort_req, abort_completion);
1348
c30341dc
KB		 1349 memset(&cmd, 0, sizeof(cmd));
1350 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1351 cmd.abort.cid = req->tag;
c30341dc 1352 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1353 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1354
1355 --dev->abort_limit;
a4aea562 1356 cmd_rq->aborted = 1;
c30341dc 1357
a4aea562 1358 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1359 nvmeq->qid);
e3f879bf 1360 nvme_submit_cmd(dev->queues[0], &cmd);
c30341dc
KB		 1361}
1362
42483228 1363static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
a09115b2 1364{
a4aea562
MB		 1365 struct nvme_queue *nvmeq = data;
1366 void *ctx;
1367 nvme_completion_fn fn;
1368 struct nvme_cmd_info *cmd;
cef6a948
KB		 1369 struct nvme_completion cqe;
1370
1371 if (!blk_mq_request_started(req))
1372 return;
a09115b2 1373
a4aea562 1374 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1375
a4aea562
MB		 1376 if (cmd->ctx == CMD_CTX_CANCELLED)
1377 return;
1378
cef6a948
KB		 1379 if (blk_queue_dying(req->q))
1380 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1381 else
1382 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1383
1384
a4aea562
MB		 1385 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1386 req->tag, nvmeq->qid);
1387 ctx = cancel_cmd_info(cmd, &fn);
1388 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1389}
1390
a4aea562 1391static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1392{
a4aea562
MB		 1393 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1394 struct nvme_queue *nvmeq = cmd->nvmeq;
1395
1396 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1397 nvmeq->qid);
7a509a6b 1398 spin_lock_irq(&nvmeq->q_lock);
07836e65 1399 nvme_abort_req(req);
7a509a6b 1400 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1401
07836e65
KB		 1402 /*
1403 * The aborted req will be completed on receiving the abort req.
1404 * We enable the timer again. If hit twice, it'll cause a device reset,
1405 * as the device then is in a faulty state.
1406 */
1407 return BLK_EH_RESET_TIMER;
a4aea562 1408}
22404274 1409
a4aea562
MB		 1410static void nvme_free_queue(struct nvme_queue *nvmeq)
1411{
9e866774
MW		 1412 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1413 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD		 1414 if (nvmeq->sq_cmds)
1415 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774
MW		 1416 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1417 kfree(nvmeq);
1418}
1419
a1a5ef99 1420static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1421{
1422 int i;
1423
a1a5ef99 1424 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1425 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1426 dev->queue_count--;
a4aea562 1427 dev->queues[i] = NULL;
f435c282 1428 nvme_free_queue(nvmeq);
121c7ad4 1429 }
22404274
KB		 1430}
1431
4d115420
KB		 1432/**
1433 * nvme_suspend_queue - put queue into suspended state
1434 * @nvmeq - queue to suspend
4d115420
KB		 1435 */
1436static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1437{
2b25d981 1438 int vector;
b60503ba 1439
a09115b2 1440 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1441 if (nvmeq->cq_vector == -1) {
1442 spin_unlock_irq(&nvmeq->q_lock);
1443 return 1;
1444 }
1445 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1446 nvmeq->dev->online_queues--;
2b25d981 1447 nvmeq->cq_vector = -1;
a09115b2
MW		 1448 spin_unlock_irq(&nvmeq->q_lock);
1449
6df3dbc8
KB		 1450 if (!nvmeq->qid && nvmeq->dev->admin_q)
1451 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1452
aba2080f
MW		 1453 irq_set_affinity_hint(vector, NULL);
1454 free_irq(vector, nvmeq);
b60503ba 1455
4d115420
KB		 1456 return 0;
1457}
b60503ba 1458
4d115420
KB		 1459static void nvme_clear_queue(struct nvme_queue *nvmeq)
1460{
22404274 1461 spin_lock_irq(&nvmeq->q_lock);
42483228
KB		 1462 if (nvmeq->tags && *nvmeq->tags)
1463 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
22404274 1464 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1465}
1466
4d115420
KB		 1467static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1468{
a4aea562 1469 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1470
1471 if (!nvmeq)
1472 return;
1473 if (nvme_suspend_queue(nvmeq))
1474 return;
1475
0e53d180
KB		 1476 /* Don't tell the adapter to delete the admin queue.
1477 * Don't tell a removed adapter to delete IO queues. */
1478 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1479 adapter_delete_sq(dev, qid);
1480 adapter_delete_cq(dev, qid);
1481 }
07836e65
KB		 1482
1483 spin_lock_irq(&nvmeq->q_lock);
1484 nvme_process_cq(nvmeq);
1485 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1486}
1487
8ffaadf7
JD		 1488static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1489 int entry_size)
1490{
1491 int q_depth = dev->q_depth;
1492 unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size);
1493
1494 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99
JD		 1495 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1496 mem_per_q = round_down(mem_per_q, dev->page_size);
1497 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1498
1499 /*
1500 * Ensure the reduced q_depth is above some threshold where it
1501 * would be better to map queues in system memory with the
1502 * original depth
1503 */
1504 if (q_depth < 64)
1505 return -ENOMEM;
1506 }
1507
1508 return q_depth;
1509}
1510
1511static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1512 int qid, int depth)
1513{
1514 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1515 unsigned offset = (qid - 1) *
1516 roundup(SQ_SIZE(depth), dev->page_size);
1517 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1518 nvmeq->sq_cmds_io = dev->cmb + offset;
1519 } else {
1520 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1521 &nvmeq->sq_dma_addr, GFP_KERNEL);
1522 if (!nvmeq->sq_cmds)
1523 return -ENOMEM;
1524 }
1525
1526 return 0;
1527}
1528
b60503ba 1529static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1530 int depth)
b60503ba 1531{
a4aea562 1532 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1533 if (!nvmeq)
1534 return NULL;
1535
e75ec752 1536 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1537 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1538 if (!nvmeq->cqes)
1539 goto free_nvmeq;
b60503ba 1540
8ffaadf7 1541 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1542 goto free_cqdma;
1543
e75ec752 1544 nvmeq->q_dmadev = dev->dev;
091b6092 1545 nvmeq->dev = dev;
3193f07b
MW		 1546 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1547 dev->instance, qid);
b60503ba
MW		 1548 spin_lock_init(&nvmeq->q_lock);
1549 nvmeq->cq_head = 0;
82123460 1550 nvmeq->cq_phase = 1;
b80d5ccc 1551 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1552 nvmeq->q_depth = depth;
c30341dc 1553 nvmeq->qid = qid;
758dd7fd 1554 nvmeq->cq_vector = -1;
a4aea562 1555 dev->queues[qid] = nvmeq;
b60503ba 1556
36a7e993
JD		 1557 /* make sure queue descriptor is set before queue count, for kthread */
1558 mb();
1559 dev->queue_count++;
1560
b60503ba
MW		 1561 return nvmeq;
1562
1563 free_cqdma:
e75ec752 1564 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1565 nvmeq->cq_dma_addr);
1566 free_nvmeq:
1567 kfree(nvmeq);
1568 return NULL;
1569}
1570
3001082c
MW		 1571static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1572 const char *name)
1573{
58ffacb5
MW		 1574 if (use_threaded_interrupts)
1575 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1576 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1577 name, nvmeq);
3001082c 1578 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1579 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1580}
1581
22404274 1582static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1583{
22404274 1584 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1585
7be50e93 1586 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1587 nvmeq->sq_tail = 0;
1588 nvmeq->cq_head = 0;
1589 nvmeq->cq_phase = 1;
b80d5ccc 1590 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1591 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1592 dev->online_queues++;
7be50e93 1593 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1594}
1595
1596static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1597{
1598 struct nvme_dev *dev = nvmeq->dev;
1599 int result;
3f85d50b 1600
2b25d981 1601 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1602 result = adapter_alloc_cq(dev, qid, nvmeq);
1603 if (result < 0)
22404274 1604 return result;
b60503ba
MW		 1605
1606 result = adapter_alloc_sq(dev, qid, nvmeq);
1607 if (result < 0)
1608 goto release_cq;
1609
3193f07b 1610 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1611 if (result < 0)
1612 goto release_sq;
1613
22404274 1614 nvme_init_queue(nvmeq, qid);
22404274 1615 return result;
b60503ba
MW		 1616
1617 release_sq:
1618 adapter_delete_sq(dev, qid);
1619 release_cq:
1620 adapter_delete_cq(dev, qid);
22404274 1621 return result;
b60503ba
MW		 1622}
1623
ba47e386
MW		 1624static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1625{
1626 unsigned long timeout;
1627 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1628
1629 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1630
1631 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1632 msleep(100);
1633 if (fatal_signal_pending(current))
1634 return -EINTR;
1635 if (time_after(jiffies, timeout)) {
e75ec752 1636 dev_err(dev->dev,
27e8166c
MW		 1637 "Device not ready; aborting %s\n", enabled ?
1638 "initialisation" : "reset");
ba47e386
MW		 1639 return -ENODEV;
1640 }
1641 }
1642
1643 return 0;
1644}
1645
1646/*
1647 * If the device has been passed off to us in an enabled state, just clear
1648 * the enabled bit. The spec says we should set the 'shutdown notification
1649 * bits', but doing so may cause the device to complete commands to the
1650 * admin queue ... and we don't know what memory that might be pointing at!
1651 */
1652static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1653{
01079522
DM		 1654 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1655 dev->ctrl_config &= ~NVME_CC_ENABLE;
1656 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1657
ba47e386
MW		 1658 return nvme_wait_ready(dev, cap, false);
1659}
1660
1661static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1662{
01079522
DM		 1663 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1664 dev->ctrl_config |= NVME_CC_ENABLE;
1665 writel(dev->ctrl_config, &dev->bar->cc);
1666
ba47e386
MW		 1667 return nvme_wait_ready(dev, cap, true);
1668}
1669
1894d8f1
KB		 1670static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1671{
1672 unsigned long timeout;
1894d8f1 1673
01079522
DM		 1674 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1675 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1676
1677 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1678
2484f407 1679 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1680 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1681 NVME_CSTS_SHST_CMPLT) {
1682 msleep(100);
1683 if (fatal_signal_pending(current))
1684 return -EINTR;
1685 if (time_after(jiffies, timeout)) {
e75ec752 1686 dev_err(dev->dev,
1894d8f1
KB		 1687 "Device shutdown incomplete; abort shutdown\n");
1688 return -ENODEV;
1689 }
1690 }
1691
1692 return 0;
1693}
1694
a4aea562 1695static struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1696 .queue_rq = nvme_queue_rq,
a4aea562
MB		 1697 .map_queue = blk_mq_map_queue,
1698 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1699 .exit_hctx = nvme_admin_exit_hctx,
a4aea562
MB		 1700 .init_request = nvme_admin_init_request,
1701 .timeout = nvme_timeout,
1702};
1703
1704static struct blk_mq_ops nvme_mq_ops = {
1705 .queue_rq = nvme_queue_rq,
1706 .map_queue = blk_mq_map_queue,
1707 .init_hctx = nvme_init_hctx,
1708 .init_request = nvme_init_request,
1709 .timeout = nvme_timeout,
a0fa9647 1710 .poll = nvme_poll,
a4aea562
MB		 1711};
1712
ea191d2f
KB		 1713static void nvme_dev_remove_admin(struct nvme_dev *dev)
1714{
1715 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1716 blk_cleanup_queue(dev->admin_q);
1717 blk_mq_free_tag_set(&dev->admin_tagset);
1718 }
1719}
1720
a4aea562
MB		 1721static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1722{
1723 if (!dev->admin_q) {
1724 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1725 dev->admin_tagset.nr_hw_queues = 1;
1726 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1efccc9d 1727 dev->admin_tagset.reserved_tags = 1;
a4aea562 1728 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1729 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
ac3dd5bd 1730 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1731 dev->admin_tagset.driver_data = dev;
1732
1733 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1734 return -ENOMEM;
1735
1736 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1737 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1738 blk_mq_free_tag_set(&dev->admin_tagset);
1739 return -ENOMEM;
1740 }
ea191d2f
KB		 1741 if (!blk_get_queue(dev->admin_q)) {
1742 nvme_dev_remove_admin(dev);
4af0e21c 1743 dev->admin_q = NULL;
ea191d2f
KB		 1744 return -ENODEV;
1745 }
0fb59cbc
KB		 1746 } else
1747 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1748
1749 return 0;
1750}
1751
8d85fce7 1752static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1753{
ba47e386 1754 int result;
b60503ba 1755 u32 aqa;
a310acd7 1756 u64 cap = lo_hi_readq(&dev->bar->cap);
b60503ba 1757 struct nvme_queue *nvmeq;
c5c9f25b
NA		 1758 /*
1759 * default to a 4K page size, with the intention to update this
1760 * path in the future to accomodate architectures with differing
1761 * kernel and IO page sizes.
1762 */
1763 unsigned page_shift = 12;
1d090624 1764 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1d090624
KB		 1765
1766 if (page_shift < dev_page_min) {
e75ec752 1767 dev_err(dev->dev,
1d090624
KB		 1768 "Minimum device page size (%u) too large for "
1769 "host (%u)\n", 1 << dev_page_min,
1770 1 << page_shift);
1771 return -ENODEV;
1772 }
b60503ba 1773
dfbac8c7
KB		 1774 dev->subsystem = readl(&dev->bar->vs) >= NVME_VS(1, 1) ?
1775 NVME_CAP_NSSRC(cap) : 0;
1776
1777 if (dev->subsystem && (readl(&dev->bar->csts) & NVME_CSTS_NSSRO))
1778 writel(NVME_CSTS_NSSRO, &dev->bar->csts);
1779
ba47e386
MW		 1780 result = nvme_disable_ctrl(dev, cap);
1781 if (result < 0)
1782 return result;
b60503ba 1783
a4aea562 1784 nvmeq = dev->queues[0];
cd638946 1785 if (!nvmeq) {
2b25d981 1786 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1787 if (!nvmeq)
1788 return -ENOMEM;
cd638946 1789 }
b60503ba
MW		 1790
1791 aqa = nvmeq->q_depth - 1;
1792 aqa |= aqa << 16;
1793
1d090624
KB		 1794 dev->page_size = 1 << page_shift;
1795
01079522 1796 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1797 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1798 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1799 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1800
1801 writel(aqa, &dev->bar->aqa);
a310acd7
SG		 1802 lo_hi_writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1803 lo_hi_writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1804
ba47e386 1805 result = nvme_enable_ctrl(dev, cap);
025c557a 1806 if (result)
a4aea562
MB		 1807 goto free_nvmeq;
1808
2b25d981 1809 nvmeq->cq_vector = 0;
3193f07b 1810 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
758dd7fd
JD		 1811 if (result) {
1812 nvmeq->cq_vector = -1;
0fb59cbc 1813 goto free_nvmeq;
758dd7fd 1814 }
025c557a 1815
b60503ba 1816 return result;
a4aea562 1817
a4aea562
MB		 1818 free_nvmeq:
1819 nvme_free_queues(dev, 0);
1820 return result;
b60503ba
MW		 1821}
1822
a53295b6
MW		 1823static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1824{
1825 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1826 struct nvme_user_io io;
1827 struct nvme_command c;
d29ec824 1828 unsigned length, meta_len;
a67a9513 1829 int status, write;
a67a9513
KB		 1830 dma_addr_t meta_dma = 0;
1831 void *meta = NULL;
fec558b5 1832 void __user *metadata;
a53295b6
MW		 1833
1834 if (copy_from_user(&io, uio, sizeof(io)))
1835 return -EFAULT;
6c7d4945
MW		 1836
1837 switch (io.opcode) {
1838 case nvme_cmd_write:
1839 case nvme_cmd_read:
6bbf1acd 1840 case nvme_cmd_compare:
6413214c 1841 break;
6c7d4945 1842 default:
6bbf1acd 1843 return -EINVAL;
6c7d4945
MW		 1844 }
1845
d29ec824
CH		 1846 length = (io.nblocks + 1) << ns->lba_shift;
1847 meta_len = (io.nblocks + 1) * ns->ms;
835da3f9 1848 metadata = (void __user *)(uintptr_t)io.metadata;
d29ec824 1849 write = io.opcode & 1;
a53295b6 1850
71feb364
KB		 1851 if (ns->ext) {
1852 length += meta_len;
1853 meta_len = 0;
a67a9513
KB		 1854 }
1855 if (meta_len) {
d29ec824
CH		 1856 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1857 return -EINVAL;
1858
e75ec752 1859 meta = dma_alloc_coherent(dev->dev, meta_len,
a67a9513 1860 &meta_dma, GFP_KERNEL);
fec558b5 1861
a67a9513
KB		 1862 if (!meta) {
1863 status = -ENOMEM;
1864 goto unmap;
1865 }
1866 if (write) {
fec558b5 1867 if (copy_from_user(meta, metadata, meta_len)) {
a67a9513
KB		 1868 status = -EFAULT;
1869 goto unmap;
1870 }
1871 }
1872 }
1873
a53295b6
MW		 1874 memset(&c, 0, sizeof(c));
1875 c.rw.opcode = io.opcode;
1876 c.rw.flags = io.flags;
6c7d4945 1877 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1878 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1879 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1880 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1881 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1882 c.rw.reftag = cpu_to_le32(io.reftag);
1883 c.rw.apptag = cpu_to_le16(io.apptag);
1884 c.rw.appmask = cpu_to_le16(io.appmask);
a67a9513 1885 c.rw.metadata = cpu_to_le64(meta_dma);
d29ec824
CH		 1886
1887 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
835da3f9 1888 (void __user *)(uintptr_t)io.addr, length, NULL, 0);
f410c680 1889 unmap:
a67a9513
KB		 1890 if (meta) {
1891 if (status == NVME_SC_SUCCESS && !write) {
fec558b5 1892 if (copy_to_user(metadata, meta, meta_len))
a67a9513
KB		 1893 status = -EFAULT;
1894 }
e75ec752 1895 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
f410c680 1896 }
a53295b6
MW		 1897 return status;
1898}
1899
a4aea562
MB		 1900static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1901 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1902{
7963e521 1903 struct nvme_passthru_cmd cmd;
6ee44cdc 1904 struct nvme_command c;
d29ec824
CH		 1905 unsigned timeout = 0;
1906 int status;
6ee44cdc 1907
6bbf1acd
MW		 1908 if (!capable(CAP_SYS_ADMIN))
1909 return -EACCES;
1910 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1911 return -EFAULT;
6ee44cdc
MW		 1912
1913 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1914 c.common.opcode = cmd.opcode;
1915 c.common.flags = cmd.flags;
1916 c.common.nsid = cpu_to_le32(cmd.nsid);
1917 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1918 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1919 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1920 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1921 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1922 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1923 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1924 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1925
d29ec824
CH		 1926 if (cmd.timeout_ms)
1927 timeout = msecs_to_jiffies(cmd.timeout_ms);
eca18b23 1928
f705f837 1929 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
835da3f9 1930 NULL, (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
d29ec824
CH		 1931 &cmd.result, timeout);
1932 if (status >= 0) {
1933 if (put_user(cmd.result, &ucmd->result))
1934 return -EFAULT;
6bbf1acd 1935 }
f4f117f6 1936
6ee44cdc
MW		 1937 return status;
1938}
1939
81f03fed
JD		 1940static int nvme_subsys_reset(struct nvme_dev *dev)
1941{
1942 if (!dev->subsystem)
1943 return -ENOTTY;
1944
1945 writel(0x4E564D65, &dev->bar->nssr); /* "NVMe" */
1946 return 0;
1947}
1948
b60503ba
MW		 1949static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1950 unsigned long arg)
1951{
1952 struct nvme_ns *ns = bdev->bd_disk->private_data;
1953
1954 switch (cmd) {
6bbf1acd 1955 case NVME_IOCTL_ID:
c3bfe717 1956 force_successful_syscall_return();
6bbf1acd
MW		 1957 return ns->ns_id;
1958 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1959 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1960 case NVME_IOCTL_IO_CMD:
a4aea562 1961 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1962 case NVME_IOCTL_SUBMIT_IO:
1963 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1964 case SG_GET_VERSION_NUM:
1965 return nvme_sg_get_version_num((void __user *)arg);
1966 case SG_IO:
1967 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1968 default:
1969 return -ENOTTY;
1970 }
1971}
1972
320a3827
KB		 1973#ifdef CONFIG_COMPAT
1974static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1975 unsigned int cmd, unsigned long arg)
1976{
320a3827
KB		 1977 switch (cmd) {
1978 case SG_IO:
e179729a 1979 return -ENOIOCTLCMD;
320a3827
KB		 1980 }
1981 return nvme_ioctl(bdev, mode, cmd, arg);
1982}
1983#else
1984#define nvme_compat_ioctl NULL
1985#endif
1986
5105aa55 1987static void nvme_free_dev(struct kref *kref);
188c3568
KB		 1988static void nvme_free_ns(struct kref *kref)
1989{
1990 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
1991
ca064085
MB		 1992 if (ns->type == NVME_NS_LIGHTNVM)
1993 nvme_nvm_unregister(ns->queue, ns->disk->disk_name);
1994
188c3568
KB		 1995 spin_lock(&dev_list_lock);
1996 ns->disk->private_data = NULL;
1997 spin_unlock(&dev_list_lock);
1998
5105aa55 1999 kref_put(&ns->dev->kref, nvme_free_dev);
188c3568
KB		 2000 put_disk(ns->disk);
2001 kfree(ns);
2002}
2003
9ac27090
KB		 2004static int nvme_open(struct block_device *bdev, fmode_t mode)
2005{
9e60352c
KB		 2006 int ret = 0;
2007 struct nvme_ns *ns;
9ac27090 2008
9e60352c
KB		 2009 spin_lock(&dev_list_lock);
2010 ns = bdev->bd_disk->private_data;
2011 if (!ns)
2012 ret = -ENXIO;
188c3568 2013 else if (!kref_get_unless_zero(&ns->kref))
9e60352c
KB		 2014 ret = -ENXIO;
2015 spin_unlock(&dev_list_lock);
2016
2017 return ret;
9ac27090
KB		 2018}
2019
9ac27090
KB		 2020static void nvme_release(struct gendisk *disk, fmode_t mode)
2021{
2022 struct nvme_ns *ns = disk->private_data;
188c3568 2023 kref_put(&ns->kref, nvme_free_ns);
9ac27090
KB		 2024}
2025
4cc09e2d
KB		 2026static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
2027{
2028 /* some standard values */
2029 geo->heads = 1 << 6;
2030 geo->sectors = 1 << 5;
2031 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
2032 return 0;
2033}
2034
e1e5e564
KB		 2035static void nvme_config_discard(struct nvme_ns *ns)
2036{
2037 u32 logical_block_size = queue_logical_block_size(ns->queue);
2038 ns->queue->limits.discard_zeroes_data = 0;
2039 ns->queue->limits.discard_alignment = logical_block_size;
2040 ns->queue->limits.discard_granularity = logical_block_size;
2bb4cd5c 2041 blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
e1e5e564
KB		 2042 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
2043}
2044
1b9dbf7f
KB		 2045static int nvme_revalidate_disk(struct gendisk *disk)
2046{
2047 struct nvme_ns *ns = disk->private_data;
2048 struct nvme_dev *dev = ns->dev;
2049 struct nvme_id_ns *id;
a67a9513
KB		 2050 u8 lbaf, pi_type;
2051 u16 old_ms;
e1e5e564 2052 unsigned short bs;
1b9dbf7f 2053
d29ec824 2054 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
a5768aa8
KB		 2055 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
2056 dev->instance, ns->ns_id);
2057 return -ENODEV;
1b9dbf7f 2058 }
a5768aa8
KB		 2059 if (id->ncap == 0) {
2060 kfree(id);
2061 return -ENODEV;
e1e5e564 2062 }
1b9dbf7f 2063
ca064085
MB		 2064 if (nvme_nvm_ns_supported(ns, id) && ns->type != NVME_NS_LIGHTNVM) {
2065 if (nvme_nvm_register(ns->queue, disk->disk_name)) {
2066 dev_warn(dev->dev,
2067 "%s: LightNVM init failure\n", __func__);
2068 kfree(id);
2069 return -ENODEV;
2070 }
2071 ns->type = NVME_NS_LIGHTNVM;
2072 }
2073
e1e5e564
KB		 2074 old_ms = ns->ms;
2075 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1b9dbf7f 2076 ns->lba_shift = id->lbaf[lbaf].ds;
e1e5e564 2077 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
a67a9513 2078 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
e1e5e564
KB		 2079
2080 /*
2081 * If identify namespace failed, use default 512 byte block size so
2082 * block layer can use before failing read/write for 0 capacity.
2083 */
2084 if (ns->lba_shift == 0)
2085 ns->lba_shift = 9;
2086 bs = 1 << ns->lba_shift;
2087
2088 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2089 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2090 id->dps & NVME_NS_DPS_PI_MASK : 0;
2091
4cfc766e 2092 blk_mq_freeze_queue(disk->queue);
52b68d7e
KB		 2093 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2094 ns->ms != old_ms ||
e1e5e564 2095 bs != queue_logical_block_size(disk->queue) ||
a67a9513 2096 (ns->ms && ns->ext)))
e1e5e564
KB		 2097 blk_integrity_unregister(disk);
2098
2099 ns->pi_type = pi_type;
2100 blk_queue_logical_block_size(ns->queue, bs);
2101
25520d55 2102 if (ns->ms && !ns->ext)
e1e5e564
KB		 2103 nvme_init_integrity(ns);
2104
ca064085
MB		 2105 if ((ns->ms && !(ns->ms == 8 && ns->pi_type) &&
2106 !blk_get_integrity(disk)) ||
2107 ns->type == NVME_NS_LIGHTNVM)
e1e5e564
KB		 2108 set_capacity(disk, 0);
2109 else
2110 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2111
2112 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2113 nvme_config_discard(ns);
4cfc766e 2114 blk_mq_unfreeze_queue(disk->queue);
1b9dbf7f 2115
d29ec824 2116 kfree(id);
1b9dbf7f
KB		 2117 return 0;
2118}
2119
1d277a63
KB		 2120static char nvme_pr_type(enum pr_type type)
2121{
2122 switch (type) {
2123 case PR_WRITE_EXCLUSIVE:
2124 return 1;
2125 case PR_EXCLUSIVE_ACCESS:
2126 return 2;
2127 case PR_WRITE_EXCLUSIVE_REG_ONLY:
2128 return 3;
2129 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
2130 return 4;
2131 case PR_WRITE_EXCLUSIVE_ALL_REGS:
2132 return 5;
2133 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
2134 return 6;
2135 default:
2136 return 0;
2137 }
2138};
2139
2140static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
2141 u64 key, u64 sa_key, u8 op)
2142{
2143 struct nvme_ns *ns = bdev->bd_disk->private_data;
2144 struct nvme_command c;
2145 u8 data[16] = { 0, };
2146
2147 put_unaligned_le64(key, &data[0]);
2148 put_unaligned_le64(sa_key, &data[8]);
2149
2150 memset(&c, 0, sizeof(c));
2151 c.common.opcode = op;
a6dd1020
CH		 2152 c.common.nsid = cpu_to_le32(ns->ns_id);
2153 c.common.cdw10[0] = cpu_to_le32(cdw10);
1d277a63
KB		 2154
2155 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
2156}
2157
2158static int nvme_pr_register(struct block_device *bdev, u64 old,
2159 u64 new, unsigned flags)
2160{
2161 u32 cdw10;
2162
2163 if (flags & ~PR_FL_IGNORE_KEY)
2164 return -EOPNOTSUPP;
2165
2166 cdw10 = old ? 2 : 0;
2167 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
2168 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
2169 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
2170}
2171
2172static int nvme_pr_reserve(struct block_device *bdev, u64 key,
2173 enum pr_type type, unsigned flags)
2174{
2175 u32 cdw10;
2176
2177 if (flags & ~PR_FL_IGNORE_KEY)
2178 return -EOPNOTSUPP;
2179
2180 cdw10 = nvme_pr_type(type) << 8;
2181 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
2182 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
2183}
2184
2185static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
2186 enum pr_type type, bool abort)
2187{
2188 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
2189 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
2190}
2191
2192static int nvme_pr_clear(struct block_device *bdev, u64 key)
2193{
73fcf4e2 2194 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1d277a63
KB		 2195 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
2196}
2197
2198static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
2199{
2200 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
2201 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
2202}
2203
2204static const struct pr_ops nvme_pr_ops = {
2205 .pr_register = nvme_pr_register,
2206 .pr_reserve = nvme_pr_reserve,
2207 .pr_release = nvme_pr_release,
2208 .pr_preempt = nvme_pr_preempt,
2209 .pr_clear = nvme_pr_clear,
2210};
2211
b60503ba
MW		 2212static const struct block_device_operations nvme_fops = {
2213 .owner = THIS_MODULE,
2214 .ioctl = nvme_ioctl,
320a3827 2215 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 2216 .open = nvme_open,
2217 .release = nvme_release,
4cc09e2d 2218 .getgeo = nvme_getgeo,
1b9dbf7f 2219 .revalidate_disk= nvme_revalidate_disk,
1d277a63 2220 .pr_ops = &nvme_pr_ops,
b60503ba
MW		 2221};
2222
1fa6aead
MW		 2223static int nvme_kthread(void *data)
2224{
d4b4ff8e 2225 struct nvme_dev *dev, *next;
1fa6aead
MW		 2226
2227 while (!kthread_should_stop()) {
564a232c 2228 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 2229 spin_lock(&dev_list_lock);
d4b4ff8e 2230 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 2231 int i;
dfbac8c7
KB		 2232 u32 csts = readl(&dev->bar->csts);
2233
2234 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
2235 csts & NVME_CSTS_CFS) {
90667892
CH		 2236 if (!__nvme_reset(dev)) {
2237 dev_warn(dev->dev,
2238 "Failed status: %x, reset controller\n",
2239 readl(&dev->bar->csts));
2240 }
d4b4ff8e
KB		 2241 continue;
2242 }
1fa6aead 2243 for (i = 0; i < dev->queue_count; i++) {
a4aea562 2244 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 2245 if (!nvmeq)
2246 continue;
1fa6aead 2247 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 2248 nvme_process_cq(nvmeq);
6fccf938
KB		 2249
2250 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 2251 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 2252 break;
2253 dev->event_limit--;
2254 }
1fa6aead
MW		 2255 spin_unlock_irq(&nvmeq->q_lock);
2256 }
2257 }
2258 spin_unlock(&dev_list_lock);
acb7aa0d 2259 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 2260 }
2261 return 0;
2262}
2263
e1e5e564 2264static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
b60503ba
MW		 2265{
2266 struct nvme_ns *ns;
2267 struct gendisk *disk;
e75ec752 2268 int node = dev_to_node(dev->dev);
b60503ba 2269
a4aea562 2270 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba 2271 if (!ns)
e1e5e564
KB		 2272 return;
2273
a4aea562 2274 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 2275 if (IS_ERR(ns->queue))
b60503ba 2276 goto out_free_ns;
4eeb9215
MW		 2277 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2278 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 2279 ns->dev = dev;
2280 ns->queue->queuedata = ns;
2281
a4aea562 2282 disk = alloc_disk_node(0, node);
b60503ba
MW		 2283 if (!disk)
2284 goto out_free_queue;
a4aea562 2285
188c3568 2286 kref_init(&ns->kref);
5aff9382 2287 ns->ns_id = nsid;
b60503ba 2288 ns->disk = disk;
e1e5e564
KB		 2289 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2290 list_add_tail(&ns->list, &dev->namespaces);
2291
e9ef4636 2292 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
e824410f 2293 if (dev->max_hw_sectors) {
8fc23e03 2294 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
e824410f 2295 blk_queue_max_segments(ns->queue,
6824c5ef 2296 (dev->max_hw_sectors / (dev->page_size >> 9)) + 1);
e824410f 2297 }
a4aea562
MB		 2298 if (dev->stripe_size)
2299 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2300 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2301 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
03100aad 2302 blk_queue_virt_boundary(ns->queue, dev->page_size - 1);
b60503ba
MW		 2303
2304 disk->major = nvme_major;
469071a3 2305 disk->first_minor = 0;
b60503ba
MW		 2306 disk->fops = &nvme_fops;
2307 disk->private_data = ns;
2308 disk->queue = ns->queue;
b3fffdef 2309 disk->driverfs_dev = dev->device;
469071a3 2310 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2311 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba 2312
e1e5e564
KB		 2313 /*
2314 * Initialize capacity to 0 until we establish the namespace format and
2315 * setup integrity extentions if necessary. The revalidate_disk after
2316 * add_disk allows the driver to register with integrity if the format
2317 * requires it.
2318 */
2319 set_capacity(disk, 0);
a5768aa8
KB		 2320 if (nvme_revalidate_disk(ns->disk))
2321 goto out_free_disk;
2322
5105aa55 2323 kref_get(&dev->kref);
ca064085
MB		 2324 if (ns->type != NVME_NS_LIGHTNVM) {
2325 add_disk(ns->disk);
2326 if (ns->ms) {
2327 struct block_device *bd = bdget_disk(ns->disk, 0);
2328 if (!bd)
2329 return;
2330 if (blkdev_get(bd, FMODE_READ, NULL)) {
2331 bdput(bd);
2332 return;
2333 }
2334 blkdev_reread_part(bd);
2335 blkdev_put(bd, FMODE_READ);
7bee6074 2336 }
7bee6074 2337 }
e1e5e564 2338 return;
a5768aa8
KB		 2339 out_free_disk:
2340 kfree(disk);
2341 list_del(&ns->list);
b60503ba
MW		 2342 out_free_queue:
2343 blk_cleanup_queue(ns->queue);
2344 out_free_ns:
2345 kfree(ns);
b60503ba
MW		 2346}
2347
2659e57b
CH		 2348/*
2349 * Create I/O queues. Failing to create an I/O queue is not an issue,
2350 * we can continue with less than the desired amount of queues, and
2351 * even a controller without I/O queues an still be used to issue
2352 * admin commands. This might be useful to upgrade a buggy firmware
2353 * for example.
2354 */
42f61420
KB		 2355static void nvme_create_io_queues(struct nvme_dev *dev)
2356{
a4aea562 2357 unsigned i;
42f61420 2358
a4aea562 2359 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2360 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2361 break;
2362
a4aea562 2363 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2659e57b
CH		 2364 if (nvme_create_queue(dev->queues[i], i)) {
2365 nvme_free_queues(dev, i);
42f61420 2366 break;
2659e57b 2367 }
42f61420
KB		 2368}
2369
b3b06812 2370static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2371{
2372 int status;
2373 u32 result;
b3b06812 2374 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2375
df348139 2376 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2377 &result);
27e8166c
MW		 2378 if (status < 0)
2379 return status;
2380 if (status > 0) {
e75ec752 2381 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
badc34d4 2382 return 0;
27e8166c 2383 }
b60503ba
MW		 2384 return min(result & 0xffff, result >> 16) + 1;
2385}
2386
8ffaadf7
JD		 2387static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
2388{
2389 u64 szu, size, offset;
2390 u32 cmbloc;
2391 resource_size_t bar_size;
2392 struct pci_dev *pdev = to_pci_dev(dev->dev);
2393 void __iomem *cmb;
2394 dma_addr_t dma_addr;
2395
2396 if (!use_cmb_sqes)
2397 return NULL;
2398
2399 dev->cmbsz = readl(&dev->bar->cmbsz);
2400 if (!(NVME_CMB_SZ(dev->cmbsz)))
2401 return NULL;
2402
2403 cmbloc = readl(&dev->bar->cmbloc);
2404
2405 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
2406 size = szu * NVME_CMB_SZ(dev->cmbsz);
2407 offset = szu * NVME_CMB_OFST(cmbloc);
2408 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
2409
2410 if (offset > bar_size)
2411 return NULL;
2412
2413 /*
2414 * Controllers may support a CMB size larger than their BAR,
2415 * for example, due to being behind a bridge. Reduce the CMB to
2416 * the reported size of the BAR
2417 */
2418 if (size > bar_size - offset)
2419 size = bar_size - offset;
2420
2421 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
2422 cmb = ioremap_wc(dma_addr, size);
2423 if (!cmb)
2424 return NULL;
2425
2426 dev->cmb_dma_addr = dma_addr;
2427 dev->cmb_size = size;
2428 return cmb;
2429}
2430
2431static inline void nvme_release_cmb(struct nvme_dev *dev)
2432{
2433 if (dev->cmb) {
2434 iounmap(dev->cmb);
2435 dev->cmb = NULL;
2436 }
2437}
2438
9d713c2b
KB		 2439static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2440{
b80d5ccc 2441 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2442}
2443
8d85fce7 2444static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2445{
a4aea562 2446 struct nvme_queue *adminq = dev->queues[0];
e75ec752 2447 struct pci_dev *pdev = to_pci_dev(dev->dev);
42f61420 2448 int result, i, vecs, nr_io_queues, size;
b60503ba 2449
42f61420 2450 nr_io_queues = num_possible_cpus();
b348b7d5 2451 result = set_queue_count(dev, nr_io_queues);
badc34d4 2452 if (result <= 0)
1b23484b 2453 return result;
b348b7d5
MW		 2454 if (result < nr_io_queues)
2455 nr_io_queues = result;
b60503ba 2456
8ffaadf7
JD		 2457 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
2458 result = nvme_cmb_qdepth(dev, nr_io_queues,
2459 sizeof(struct nvme_command));
2460 if (result > 0)
2461 dev->q_depth = result;
2462 else
2463 nvme_release_cmb(dev);
2464 }
2465
9d713c2b
KB		 2466 size = db_bar_size(dev, nr_io_queues);
2467 if (size > 8192) {
f1938f6e 2468 iounmap(dev->bar);
9d713c2b
KB		 2469 do {
2470 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2471 if (dev->bar)
2472 break;
2473 if (!--nr_io_queues)
2474 return -ENOMEM;
2475 size = db_bar_size(dev, nr_io_queues);
2476 } while (1);
f1938f6e 2477 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2478 adminq->q_db = dev->dbs;
f1938f6e
MW		 2479 }
2480
9d713c2b 2481 /* Deregister the admin queue's interrupt */
3193f07b 2482 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2483
e32efbfc
JA		 2484 /*
2485 * If we enable msix early due to not intx, disable it again before
2486 * setting up the full range we need.
2487 */
2488 if (!pdev->irq)
2489 pci_disable_msix(pdev);
2490
be577fab 2491 for (i = 0; i < nr_io_queues; i++)
1b23484b 2492 dev->entry[i].entry = i;
be577fab
AG		 2493 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2494 if (vecs < 0) {
2495 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2496 if (vecs < 0) {
2497 vecs = 1;
2498 } else {
2499 for (i = 0; i < vecs; i++)
2500 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2501 }
2502 }
2503
063a8096
MW		 2504 /*
2505 * Should investigate if there's a performance win from allocating
2506 * more queues than interrupt vectors; it might allow the submission
2507 * path to scale better, even if the receive path is limited by the
2508 * number of interrupts.
2509 */
2510 nr_io_queues = vecs;
42f61420 2511 dev->max_qid = nr_io_queues;
063a8096 2512
3193f07b 2513 result = queue_request_irq(dev, adminq, adminq->irqname);
758dd7fd
JD		 2514 if (result) {
2515 adminq->cq_vector = -1;
22404274 2516 goto free_queues;
758dd7fd 2517 }
1b23484b 2518
cd638946 2519 /* Free previously allocated queues that are no longer usable */
42f61420 2520 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2521 nvme_create_io_queues(dev);
9ecdc946 2522
22404274 2523 return 0;
b60503ba 2524
22404274 2525 free_queues:
a1a5ef99 2526 nvme_free_queues(dev, 1);
22404274 2527 return result;
b60503ba
MW		 2528}
2529
a5768aa8
KB		 2530static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2531{
2532 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2533 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2534
2535 return nsa->ns_id - nsb->ns_id;
2536}
2537
2538static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2539{
2540 struct nvme_ns *ns;
2541
2542 list_for_each_entry(ns, &dev->namespaces, list) {
2543 if (ns->ns_id == nsid)
2544 return ns;
2545 if (ns->ns_id > nsid)
2546 break;
2547 }
2548 return NULL;
2549}
2550
2551static inline bool nvme_io_incapable(struct nvme_dev *dev)
2552{
2553 return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
2554 dev->online_queues < 2);
2555}
2556
2557static void nvme_ns_remove(struct nvme_ns *ns)
2558{
2559 bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2560
2561 if (kill)
2562 blk_set_queue_dying(ns->queue);
9609b994 2563 if (ns->disk->flags & GENHD_FL_UP)
a5768aa8 2564 del_gendisk(ns->disk);
a5768aa8
KB		 2565 if (kill || !blk_queue_dying(ns->queue)) {
2566 blk_mq_abort_requeue_list(ns->queue);
2567 blk_cleanup_queue(ns->queue);
5105aa55
KB		 2568 }
2569 list_del_init(&ns->list);
2570 kref_put(&ns->kref, nvme_free_ns);
a5768aa8
KB		 2571}
2572
2573static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2574{
2575 struct nvme_ns *ns, *next;
2576 unsigned i;
2577
2578 for (i = 1; i <= nn; i++) {
2579 ns = nvme_find_ns(dev, i);
2580 if (ns) {
5105aa55 2581 if (revalidate_disk(ns->disk))
a5768aa8 2582 nvme_ns_remove(ns);
a5768aa8
KB		 2583 } else
2584 nvme_alloc_ns(dev, i);
2585 }
2586 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
5105aa55 2587 if (ns->ns_id > nn)
a5768aa8 2588 nvme_ns_remove(ns);
a5768aa8
KB		 2589 }
2590 list_sort(NULL, &dev->namespaces, ns_cmp);
2591}
2592
bda4e0fb
KB		 2593static void nvme_set_irq_hints(struct nvme_dev *dev)
2594{
2595 struct nvme_queue *nvmeq;
2596 int i;
2597
2598 for (i = 0; i < dev->online_queues; i++) {
2599 nvmeq = dev->queues[i];
2600
2601 if (!nvmeq->tags || !(*nvmeq->tags))
2602 continue;
2603
2604 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2605 blk_mq_tags_cpumask(*nvmeq->tags));
2606 }
2607}
2608
a5768aa8
KB		 2609static void nvme_dev_scan(struct work_struct *work)
2610{
2611 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2612 struct nvme_id_ctrl *ctrl;
2613
2614 if (!dev->tagset.tags)
2615 return;
2616 if (nvme_identify_ctrl(dev, &ctrl))
2617 return;
2618 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2619 kfree(ctrl);
bda4e0fb 2620 nvme_set_irq_hints(dev);
a5768aa8
KB		 2621}
2622
422ef0c7
MW		 2623/*
2624 * Return: error value if an error occurred setting up the queues or calling
2625 * Identify Device. 0 if these succeeded, even if adding some of the
2626 * namespaces failed. At the moment, these failures are silent. TBD which
2627 * failures should be reported.
2628 */
8d85fce7 2629static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2630{
e75ec752 2631 struct pci_dev *pdev = to_pci_dev(dev->dev);
c3bfe717 2632 int res;
51814232 2633 struct nvme_id_ctrl *ctrl;
a310acd7 2634 int shift = NVME_CAP_MPSMIN(lo_hi_readq(&dev->bar->cap)) + 12;
b60503ba 2635
d29ec824 2636 res = nvme_identify_ctrl(dev, &ctrl);
b60503ba 2637 if (res) {
e75ec752 2638 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
e1e5e564 2639 return -EIO;
b60503ba
MW		 2640 }
2641
0e5e4f0e 2642 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2643 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2644 dev->vwc = ctrl->vwc;
51814232
MW		 2645 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2646 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2647 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2648 if (ctrl->mdts)
8fc23e03 2649 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
b12363d0
S		 2650 else
2651 dev->max_hw_sectors = UINT_MAX;
68608c26 2652 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2653 (pdev->device == 0x0953) && ctrl->vs[3]) {
2654 unsigned int max_hw_sectors;
2655
159b67d7 2656 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2657 max_hw_sectors = dev->stripe_size >> (shift - 9);
2658 if (dev->max_hw_sectors) {
2659 dev->max_hw_sectors = min(max_hw_sectors,
2660 dev->max_hw_sectors);
2661 } else
2662 dev->max_hw_sectors = max_hw_sectors;
2663 }
d29ec824 2664 kfree(ctrl);
a4aea562 2665
ffe7704d
KB		 2666 if (!dev->tagset.tags) {
2667 dev->tagset.ops = &nvme_mq_ops;
2668 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2669 dev->tagset.timeout = NVME_IO_TIMEOUT;
2670 dev->tagset.numa_node = dev_to_node(dev->dev);
2671 dev->tagset.queue_depth =
a4aea562 2672 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ffe7704d
KB		 2673 dev->tagset.cmd_size = nvme_cmd_size(dev);
2674 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2675 dev->tagset.driver_data = dev;
b60503ba 2676
ffe7704d
KB		 2677 if (blk_mq_alloc_tag_set(&dev->tagset))
2678 return 0;
2679 }
a5768aa8 2680 schedule_work(&dev->scan_work);
e1e5e564 2681 return 0;
b60503ba
MW		 2682}
2683
0877cb0d
KB		 2684static int nvme_dev_map(struct nvme_dev *dev)
2685{
42f61420 2686 u64 cap;
0877cb0d 2687 int bars, result = -ENOMEM;
e75ec752 2688 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2689
2690 if (pci_enable_device_mem(pdev))
2691 return result;
2692
2693 dev->entry[0].vector = pdev->irq;
2694 pci_set_master(pdev);
2695 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2696 if (!bars)
2697 goto disable_pci;
2698
0877cb0d
KB		 2699 if (pci_request_selected_regions(pdev, bars, "nvme"))
2700 goto disable_pci;
2701
e75ec752
CH		 2702 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2703 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2704 goto disable;
0877cb0d 2705
0877cb0d
KB		 2706 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2707 if (!dev->bar)
2708 goto disable;
e32efbfc 2709
0e53d180
KB		 2710 if (readl(&dev->bar->csts) == -1) {
2711 result = -ENODEV;
2712 goto unmap;
2713 }
e32efbfc
JA		 2714
2715 /*
2716 * Some devices don't advertse INTx interrupts, pre-enable a single
2717 * MSIX vec for setup. We'll adjust this later.
2718 */
2719 if (!pdev->irq) {
2720 result = pci_enable_msix(pdev, dev->entry, 1);
2721 if (result < 0)
2722 goto unmap;
2723 }
2724
a310acd7 2725 cap = lo_hi_readq(&dev->bar->cap);
42f61420
KB		 2726 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2727 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d 2728 dev->dbs = ((void __iomem *)dev->bar) + 4096;
8ffaadf7
JD		 2729 if (readl(&dev->bar->vs) >= NVME_VS(1, 2))
2730 dev->cmb = nvme_map_cmb(dev);
0877cb0d
KB		 2731
2732 return 0;
2733
0e53d180
KB		 2734 unmap:
2735 iounmap(dev->bar);
2736 dev->bar = NULL;
0877cb0d
KB		 2737 disable:
2738 pci_release_regions(pdev);
2739 disable_pci:
2740 pci_disable_device(pdev);
2741 return result;
2742}
2743
2744static void nvme_dev_unmap(struct nvme_dev *dev)
2745{
e75ec752
CH		 2746 struct pci_dev *pdev = to_pci_dev(dev->dev);
2747
2748 if (pdev->msi_enabled)
2749 pci_disable_msi(pdev);
2750 else if (pdev->msix_enabled)
2751 pci_disable_msix(pdev);
0877cb0d
KB		 2752
2753 if (dev->bar) {
2754 iounmap(dev->bar);
2755 dev->bar = NULL;
e75ec752 2756 pci_release_regions(pdev);
0877cb0d
KB		 2757 }
2758
e75ec752
CH		 2759 if (pci_is_enabled(pdev))
2760 pci_disable_device(pdev);
0877cb0d
KB		 2761}
2762
4d115420
KB		 2763struct nvme_delq_ctx {
2764 struct task_struct *waiter;
2765 struct kthread_worker *worker;
2766 atomic_t refcount;
2767};
2768
2769static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2770{
2771 dq->waiter = current;
2772 mb();
2773
2774 for (;;) {
2775 set_current_state(TASK_KILLABLE);
2776 if (!atomic_read(&dq->refcount))
2777 break;
2778 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2779 fatal_signal_pending(current)) {
0fb59cbc
KB		 2780 /*
2781 * Disable the controller first since we can't trust it
2782 * at this point, but leave the admin queue enabled
2783 * until all queue deletion requests are flushed.
2784 * FIXME: This may take a while if there are more h/w
2785 * queues than admin tags.
2786 */
4d115420 2787 set_current_state(TASK_RUNNING);
a310acd7 2788 nvme_disable_ctrl(dev, lo_hi_readq(&dev->bar->cap));
0fb59cbc 2789 nvme_clear_queue(dev->queues[0]);
4d115420 2790 flush_kthread_worker(dq->worker);
0fb59cbc 2791 nvme_disable_queue(dev, 0);
4d115420
KB		 2792 return;
2793 }
2794 }
2795 set_current_state(TASK_RUNNING);
2796}
2797
2798static void nvme_put_dq(struct nvme_delq_ctx *dq)
2799{
2800 atomic_dec(&dq->refcount);
2801 if (dq->waiter)
2802 wake_up_process(dq->waiter);
2803}
2804
2805static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2806{
2807 atomic_inc(&dq->refcount);
2808 return dq;
2809}
2810
2811static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2812{
2813 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
4d115420 2814 nvme_put_dq(dq);
604e8c8d
KB		 2815
2816 spin_lock_irq(&nvmeq->q_lock);
2817 nvme_process_cq(nvmeq);
2818 spin_unlock_irq(&nvmeq->q_lock);
4d115420
KB		 2819}
2820
2821static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2822 kthread_work_func_t fn)
2823{
2824 struct nvme_command c;
2825
2826 memset(&c, 0, sizeof(c));
2827 c.delete_queue.opcode = opcode;
2828 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2829
2830 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2831 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2832 ADMIN_TIMEOUT);
4d115420
KB		 2833}
2834
2835static void nvme_del_cq_work_handler(struct kthread_work *work)
2836{
2837 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2838 cmdinfo.work);
2839 nvme_del_queue_end(nvmeq);
2840}
2841
2842static int nvme_delete_cq(struct nvme_queue *nvmeq)
2843{
2844 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2845 nvme_del_cq_work_handler);
2846}
2847
2848static void nvme_del_sq_work_handler(struct kthread_work *work)
2849{
2850 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2851 cmdinfo.work);
2852 int status = nvmeq->cmdinfo.status;
2853
2854 if (!status)
2855 status = nvme_delete_cq(nvmeq);
2856 if (status)
2857 nvme_del_queue_end(nvmeq);
2858}
2859
2860static int nvme_delete_sq(struct nvme_queue *nvmeq)
2861{
2862 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2863 nvme_del_sq_work_handler);
2864}
2865
2866static void nvme_del_queue_start(struct kthread_work *work)
2867{
2868 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2869 cmdinfo.work);
4d115420
KB		 2870 if (nvme_delete_sq(nvmeq))
2871 nvme_del_queue_end(nvmeq);
2872}
2873
2874static void nvme_disable_io_queues(struct nvme_dev *dev)
2875{
2876 int i;
2877 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2878 struct nvme_delq_ctx dq;
2879 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2880 &worker, "nvme%d", dev->instance);
2881
2882 if (IS_ERR(kworker_task)) {
e75ec752 2883 dev_err(dev->dev,
4d115420
KB		 2884 "Failed to create queue del task\n");
2885 for (i = dev->queue_count - 1; i > 0; i--)
2886 nvme_disable_queue(dev, i);
2887 return;
2888 }
2889
2890 dq.waiter = NULL;
2891 atomic_set(&dq.refcount, 0);
2892 dq.worker = &worker;
2893 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2894 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2895
2896 if (nvme_suspend_queue(nvmeq))
2897 continue;
2898 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2899 nvmeq->cmdinfo.worker = dq.worker;
2900 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2901 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2902 }
2903 nvme_wait_dq(&dq, dev);
2904 kthread_stop(kworker_task);
2905}
2906
b9afca3e
DM		 2907/*
2908* Remove the node from the device list and check
2909* for whether or not we need to stop the nvme_thread.
2910*/
2911static void nvme_dev_list_remove(struct nvme_dev *dev)
2912{
2913 struct task_struct *tmp = NULL;
2914
2915 spin_lock(&dev_list_lock);
2916 list_del_init(&dev->node);
2917 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2918 tmp = nvme_thread;
2919 nvme_thread = NULL;
2920 }
2921 spin_unlock(&dev_list_lock);
2922
2923 if (tmp)
2924 kthread_stop(tmp);
2925}
2926
c9d3bf88
KB		 2927static void nvme_freeze_queues(struct nvme_dev *dev)
2928{
2929 struct nvme_ns *ns;
2930
2931 list_for_each_entry(ns, &dev->namespaces, list) {
2932 blk_mq_freeze_queue_start(ns->queue);
2933
cddcd72b 2934 spin_lock_irq(ns->queue->queue_lock);
c9d3bf88 2935 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
cddcd72b 2936 spin_unlock_irq(ns->queue->queue_lock);
c9d3bf88
KB		 2937
2938 blk_mq_cancel_requeue_work(ns->queue);
2939 blk_mq_stop_hw_queues(ns->queue);
2940 }
2941}
2942
2943static void nvme_unfreeze_queues(struct nvme_dev *dev)
2944{
2945 struct nvme_ns *ns;
2946
2947 list_for_each_entry(ns, &dev->namespaces, list) {
2948 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2949 blk_mq_unfreeze_queue(ns->queue);
2950 blk_mq_start_stopped_hw_queues(ns->queue, true);
2951 blk_mq_kick_requeue_list(ns->queue);
2952 }
2953}
2954
f0b50732 2955static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2956{
22404274 2957 int i;
7c1b2450 2958 u32 csts = -1;
22404274 2959
b9afca3e 2960 nvme_dev_list_remove(dev);
1fa6aead 2961
c9d3bf88
KB		 2962 if (dev->bar) {
2963 nvme_freeze_queues(dev);
7c1b2450 2964 csts = readl(&dev->bar->csts);
c9d3bf88 2965 }
7c1b2450 2966 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2967 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2968 struct nvme_queue *nvmeq = dev->queues[i];
4d115420 2969 nvme_suspend_queue(nvmeq);
4d115420
KB		 2970 }
2971 } else {
2972 nvme_disable_io_queues(dev);
1894d8f1 2973 nvme_shutdown_ctrl(dev);
4d115420
KB		 2974 nvme_disable_queue(dev, 0);
2975 }
f0b50732 2976 nvme_dev_unmap(dev);
07836e65
KB		 2977
2978 for (i = dev->queue_count - 1; i >= 0; i--)
2979 nvme_clear_queue(dev->queues[i]);
f0b50732
KB		 2980}
2981
2982static void nvme_dev_remove(struct nvme_dev *dev)
2983{
5105aa55 2984 struct nvme_ns *ns, *next;
f0b50732 2985
5105aa55 2986 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
a5768aa8 2987 nvme_ns_remove(ns);
b60503ba
MW		 2988}
2989
091b6092
MW		 2990static int nvme_setup_prp_pools(struct nvme_dev *dev)
2991{
e75ec752 2992 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2993 PAGE_SIZE, PAGE_SIZE, 0);
2994 if (!dev->prp_page_pool)
2995 return -ENOMEM;
2996
99802a7a 2997 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2998 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2999 256, 256, 0);
3000 if (!dev->prp_small_pool) {
3001 dma_pool_destroy(dev->prp_page_pool);
3002 return -ENOMEM;
3003 }
091b6092
MW		 3004 return 0;
3005}
3006
3007static void nvme_release_prp_pools(struct nvme_dev *dev)
3008{
3009 dma_pool_destroy(dev->prp_page_pool);
99802a7a 3010 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 3011}
3012
cd58ad7d
QSA		 3013static DEFINE_IDA(nvme_instance_ida);
3014
3015static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 3016{
cd58ad7d
QSA		 3017 int instance, error;
3018
3019 do {
3020 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
3021 return -ENODEV;
3022
3023 spin_lock(&dev_list_lock);
3024 error = ida_get_new(&nvme_instance_ida, &instance);
3025 spin_unlock(&dev_list_lock);
3026 } while (error == -EAGAIN);
3027
3028 if (error)
3029 return -ENODEV;
3030
3031 dev->instance = instance;
3032 return 0;
b60503ba
MW		 3033}
3034
3035static void nvme_release_instance(struct nvme_dev *dev)
3036{
cd58ad7d
QSA		 3037 spin_lock(&dev_list_lock);
3038 ida_remove(&nvme_instance_ida, dev->instance);
3039 spin_unlock(&dev_list_lock);
b60503ba
MW		 3040}
3041
5e82e952
KB		 3042static void nvme_free_dev(struct kref *kref)
3043{
3044 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 3045
e75ec752 3046 put_device(dev->dev);
b3fffdef 3047 put_device(dev->device);
285dffc9 3048 nvme_release_instance(dev);
4af0e21c
KB		 3049 if (dev->tagset.tags)
3050 blk_mq_free_tag_set(&dev->tagset);
3051 if (dev->admin_q)
3052 blk_put_queue(dev->admin_q);
5e82e952
KB		 3053 kfree(dev->queues);
3054 kfree(dev->entry);
3055 kfree(dev);
3056}
3057
3058static int nvme_dev_open(struct inode *inode, struct file *f)
3059{
b3fffdef
KB		 3060 struct nvme_dev *dev;
3061 int instance = iminor(inode);
3062 int ret = -ENODEV;
3063
3064 spin_lock(&dev_list_lock);
3065 list_for_each_entry(dev, &dev_list, node) {
3066 if (dev->instance == instance) {
2e1d8448
KB		 3067 if (!dev->admin_q) {
3068 ret = -EWOULDBLOCK;
3069 break;
3070 }
b3fffdef
KB		 3071 if (!kref_get_unless_zero(&dev->kref))
3072 break;
3073 f->private_data = dev;
3074 ret = 0;
3075 break;
3076 }
3077 }
3078 spin_unlock(&dev_list_lock);
3079
3080 return ret;
5e82e952
KB		 3081}
3082
3083static int nvme_dev_release(struct inode *inode, struct file *f)
3084{
3085 struct nvme_dev *dev = f->private_data;
3086 kref_put(&dev->kref, nvme_free_dev);
3087 return 0;
3088}
3089
3090static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
3091{
3092 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 3093 struct nvme_ns *ns;
3094
5e82e952
KB		 3095 switch (cmd) {
3096 case NVME_IOCTL_ADMIN_CMD:
a4aea562 3097 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 3098 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 3099 if (list_empty(&dev->namespaces))
3100 return -ENOTTY;
3101 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
3102 return nvme_user_cmd(dev, ns, (void __user *)arg);
4cc06521
KB		 3103 case NVME_IOCTL_RESET:
3104 dev_warn(dev->dev, "resetting controller\n");
3105 return nvme_reset(dev);
81f03fed
JD		 3106 case NVME_IOCTL_SUBSYS_RESET:
3107 return nvme_subsys_reset(dev);
5e82e952
KB		 3108 default:
3109 return -ENOTTY;
3110 }
3111}
3112
3113static const struct file_operations nvme_dev_fops = {
3114 .owner = THIS_MODULE,
3115 .open = nvme_dev_open,
3116 .release = nvme_dev_release,
3117 .unlocked_ioctl = nvme_dev_ioctl,
3118 .compat_ioctl = nvme_dev_ioctl,
3119};
3120
3cf519b5 3121static void nvme_probe_work(struct work_struct *work)
f0b50732 3122{
3cf519b5 3123 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
b9afca3e 3124 bool start_thread = false;
3cf519b5 3125 int result;
f0b50732
KB		 3126
3127 result = nvme_dev_map(dev);
3128 if (result)
3cf519b5 3129 goto out;
f0b50732
KB		 3130
3131 result = nvme_configure_admin_queue(dev);
3132 if (result)
3133 goto unmap;
3134
3135 spin_lock(&dev_list_lock);
b9afca3e
DM		 3136 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
3137 start_thread = true;
3138 nvme_thread = NULL;
3139 }
f0b50732
KB		 3140 list_add(&dev->node, &dev_list);
3141 spin_unlock(&dev_list_lock);
3142
b9afca3e
DM		 3143 if (start_thread) {
3144 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 3145 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 3146 } else
3147 wait_event_killable(nvme_kthread_wait, nvme_thread);
3148
3149 if (IS_ERR_OR_NULL(nvme_thread)) {
3150 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
3151 goto disable;
3152 }
a4aea562
MB		 3153
3154 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 3155 result = nvme_alloc_admin_tags(dev);
3156 if (result)
3157 goto disable;
b9afca3e 3158
f0b50732 3159 result = nvme_setup_io_queues(dev);
badc34d4 3160 if (result)
0fb59cbc 3161 goto free_tags;
f0b50732 3162
1efccc9d 3163 dev->event_limit = 1;
3cf519b5 3164
2659e57b
CH		 3165 /*
3166 * Keep the controller around but remove all namespaces if we don't have
3167 * any working I/O queue.
3168 */
3cf519b5
CH		 3169 if (dev->online_queues < 2) {
3170 dev_warn(dev->dev, "IO queues not created\n");
3cf519b5
CH		 3171 nvme_dev_remove(dev);
3172 } else {
3173 nvme_unfreeze_queues(dev);
3174 nvme_dev_add(dev);
3175 }
3176
3177 return;
f0b50732 3178
0fb59cbc
KB		 3179 free_tags:
3180 nvme_dev_remove_admin(dev);
4af0e21c
KB		 3181 blk_put_queue(dev->admin_q);
3182 dev->admin_q = NULL;
3183 dev->queues[0]->tags = NULL;
f0b50732 3184 disable:
a1a5ef99 3185 nvme_disable_queue(dev, 0);
b9afca3e 3186 nvme_dev_list_remove(dev);
f0b50732
KB		 3187 unmap:
3188 nvme_dev_unmap(dev);
3cf519b5
CH		 3189 out:
3190 if (!work_busy(&dev->reset_work))
3191 nvme_dead_ctrl(dev);
f0b50732
KB		 3192}
3193
9a6b9458
KB		 3194static int nvme_remove_dead_ctrl(void *arg)
3195{
3196 struct nvme_dev *dev = (struct nvme_dev *)arg;
e75ec752 3197 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 3198
3199 if (pci_get_drvdata(pdev))
c81f4975 3200 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 3201 kref_put(&dev->kref, nvme_free_dev);
3202 return 0;
3203}
3204
de3eff2b
KB		 3205static void nvme_dead_ctrl(struct nvme_dev *dev)
3206{
3207 dev_warn(dev->dev, "Device failed to resume\n");
3208 kref_get(&dev->kref);
3209 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
3210 dev->instance))) {
3211 dev_err(dev->dev,
3212 "Failed to start controller remove task\n");
3213 kref_put(&dev->kref, nvme_free_dev);
3214 }
3215}
3216
77b50d9e 3217static void nvme_reset_work(struct work_struct *ws)
9a6b9458 3218{
77b50d9e 3219 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
ffe7704d
KB		 3220 bool in_probe = work_busy(&dev->probe_work);
3221
9a6b9458 3222 nvme_dev_shutdown(dev);
ffe7704d
KB		 3223
3224 /* Synchronize with device probe so that work will see failure status
3225 * and exit gracefully without trying to schedule another reset */
3226 flush_work(&dev->probe_work);
3227
3228 /* Fail this device if reset occured during probe to avoid
3229 * infinite initialization loops. */
3230 if (in_probe) {
de3eff2b 3231 nvme_dead_ctrl(dev);
ffe7704d 3232 return;
9a6b9458 3233 }
ffe7704d
KB		 3234 /* Schedule device resume asynchronously so the reset work is available
3235 * to cleanup errors that may occur during reinitialization */
3236 schedule_work(&dev->probe_work);
9a6b9458
KB		 3237}
3238
90667892 3239static int __nvme_reset(struct nvme_dev *dev)
9ca97374 3240{
90667892
CH		 3241 if (work_pending(&dev->reset_work))
3242 return -EBUSY;
3243 list_del_init(&dev->node);
3244 queue_work(nvme_workq, &dev->reset_work);
3245 return 0;
9ca97374
TH		 3246}
3247
4cc06521
KB		 3248static int nvme_reset(struct nvme_dev *dev)
3249{
90667892 3250 int ret;
4cc06521
KB		 3251
3252 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
3253 return -ENODEV;
3254
3255 spin_lock(&dev_list_lock);
90667892 3256 ret = __nvme_reset(dev);
4cc06521
KB		 3257 spin_unlock(&dev_list_lock);
3258
3259 if (!ret) {
3260 flush_work(&dev->reset_work);
ffe7704d 3261 flush_work(&dev->probe_work);
4cc06521
KB		 3262 return 0;
3263 }
3264
3265 return ret;
3266}
3267
3268static ssize_t nvme_sysfs_reset(struct device *dev,
3269 struct device_attribute *attr, const char *buf,
3270 size_t count)
3271{
3272 struct nvme_dev *ndev = dev_get_drvdata(dev);
3273 int ret;
3274
3275 ret = nvme_reset(ndev);
3276 if (ret < 0)
3277 return ret;
3278
3279 return count;
3280}
3281static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3282
8d85fce7 3283static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 3284{
a4aea562 3285 int node, result = -ENOMEM;
b60503ba
MW		 3286 struct nvme_dev *dev;
3287
a4aea562
MB		 3288 node = dev_to_node(&pdev->dev);
3289 if (node == NUMA_NO_NODE)
3290 set_dev_node(&pdev->dev, 0);
3291
3292 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3293 if (!dev)
3294 return -ENOMEM;
a4aea562
MB		 3295 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3296 GFP_KERNEL, node);
b60503ba
MW		 3297 if (!dev->entry)
3298 goto free;
a4aea562
MB		 3299 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3300 GFP_KERNEL, node);
b60503ba
MW		 3301 if (!dev->queues)
3302 goto free;
3303
3304 INIT_LIST_HEAD(&dev->namespaces);
77b50d9e 3305 INIT_WORK(&dev->reset_work, nvme_reset_work);
e75ec752 3306 dev->dev = get_device(&pdev->dev);
9a6b9458 3307 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 3308 result = nvme_set_instance(dev);
3309 if (result)
a96d4f5c 3310 goto put_pci;
b60503ba 3311
091b6092
MW		 3312 result = nvme_setup_prp_pools(dev);
3313 if (result)
0877cb0d 3314 goto release;
091b6092 3315
fb35e914 3316 kref_init(&dev->kref);
b3fffdef
KB		 3317 dev->device = device_create(nvme_class, &pdev->dev,
3318 MKDEV(nvme_char_major, dev->instance),
3319 dev, "nvme%d", dev->instance);
3320 if (IS_ERR(dev->device)) {
3321 result = PTR_ERR(dev->device);
2e1d8448 3322 goto release_pools;
b3fffdef
KB		 3323 }
3324 get_device(dev->device);
4cc06521
KB		 3325 dev_set_drvdata(dev->device, dev);
3326
3327 result = device_create_file(dev->device, &dev_attr_reset_controller);
3328 if (result)
3329 goto put_dev;
740216fc 3330
e6e96d73 3331 INIT_LIST_HEAD(&dev->node);
a5768aa8 3332 INIT_WORK(&dev->scan_work, nvme_dev_scan);
3cf519b5 3333 INIT_WORK(&dev->probe_work, nvme_probe_work);
2e1d8448 3334 schedule_work(&dev->probe_work);
b60503ba
MW		 3335 return 0;
3336
4cc06521
KB		 3337 put_dev:
3338 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3339 put_device(dev->device);
0877cb0d 3340 release_pools:
091b6092 3341 nvme_release_prp_pools(dev);
0877cb0d
KB		 3342 release:
3343 nvme_release_instance(dev);
a96d4f5c 3344 put_pci:
e75ec752 3345 put_device(dev->dev);
b60503ba
MW		 3346 free:
3347 kfree(dev->queues);
3348 kfree(dev->entry);
3349 kfree(dev);
3350 return result;
3351}
3352
f0d54a54
KB		 3353static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3354{
a6739479 3355 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 3356
a6739479
KB		 3357 if (prepare)
3358 nvme_dev_shutdown(dev);
3359 else
0a7385ad 3360 schedule_work(&dev->probe_work);
f0d54a54
KB		 3361}
3362
09ece142
KB		 3363static void nvme_shutdown(struct pci_dev *pdev)
3364{
3365 struct nvme_dev *dev = pci_get_drvdata(pdev);
3366 nvme_dev_shutdown(dev);
3367}
3368
8d85fce7 3369static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3370{
3371 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 3372
3373 spin_lock(&dev_list_lock);
3374 list_del_init(&dev->node);
3375 spin_unlock(&dev_list_lock);
3376
3377 pci_set_drvdata(pdev, NULL);
2e1d8448 3378 flush_work(&dev->probe_work);
9a6b9458 3379 flush_work(&dev->reset_work);
a5768aa8 3380 flush_work(&dev->scan_work);
4cc06521 3381 device_remove_file(dev->device, &dev_attr_reset_controller);
c9d3bf88 3382 nvme_dev_remove(dev);
3399a3f7 3383 nvme_dev_shutdown(dev);
a4aea562 3384 nvme_dev_remove_admin(dev);
b3fffdef 3385 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
a1a5ef99 3386 nvme_free_queues(dev, 0);
8ffaadf7 3387 nvme_release_cmb(dev);
9a6b9458 3388 nvme_release_prp_pools(dev);
5e82e952 3389 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 3390}
3391
3392/* These functions are yet to be implemented */
3393#define nvme_error_detected NULL
3394#define nvme_dump_registers NULL
3395#define nvme_link_reset NULL
3396#define nvme_slot_reset NULL
3397#define nvme_error_resume NULL
cd638946 3398
671a6018 3399#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3400static int nvme_suspend(struct device *dev)
3401{
3402 struct pci_dev *pdev = to_pci_dev(dev);
3403 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3404
3405 nvme_dev_shutdown(ndev);
3406 return 0;
3407}
3408
3409static int nvme_resume(struct device *dev)
3410{
3411 struct pci_dev *pdev = to_pci_dev(dev);
3412 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3413
0a7385ad 3414 schedule_work(&ndev->probe_work);
9a6b9458 3415 return 0;
cd638946 3416}
671a6018 3417#endif
cd638946
KB		 3418
3419static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 3420
1d352035 3421static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 3422 .error_detected = nvme_error_detected,
3423 .mmio_enabled = nvme_dump_registers,
3424 .link_reset = nvme_link_reset,
3425 .slot_reset = nvme_slot_reset,
3426 .resume = nvme_error_resume,
f0d54a54 3427 .reset_notify = nvme_reset_notify,
b60503ba
MW		 3428};
3429
3430/* Move to pci_ids.h later */
3431#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3432
6eb0d698 3433static const struct pci_device_id nvme_id_table[] = {
b60503ba 3434 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 3435 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
b60503ba
MW		 3436 { 0, }
3437};
3438MODULE_DEVICE_TABLE(pci, nvme_id_table);
3439
3440static struct pci_driver nvme_driver = {
3441 .name = "nvme",
3442 .id_table = nvme_id_table,
3443 .probe = nvme_probe,
8d85fce7 3444 .remove = nvme_remove,
09ece142 3445 .shutdown = nvme_shutdown,
cd638946
KB		 3446 .driver = {
3447 .pm = &nvme_dev_pm_ops,
3448 },
b60503ba
MW		 3449 .err_handler = &nvme_err_handler,
3450};
3451
3452static int __init nvme_init(void)
3453{
0ac13140 3454 int result;
1fa6aead 3455
b9afca3e 3456 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3457
9a6b9458
KB		 3458 nvme_workq = create_singlethread_workqueue("nvme");
3459 if (!nvme_workq)
b9afca3e 3460 return -ENOMEM;
9a6b9458 3461
5c42ea16
KB		 3462 result = register_blkdev(nvme_major, "nvme");
3463 if (result < 0)
9a6b9458 3464 goto kill_workq;
5c42ea16 3465 else if (result > 0)
0ac13140 3466 nvme_major = result;
b60503ba 3467
b3fffdef
KB		 3468 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3469 &nvme_dev_fops);
3470 if (result < 0)
3471 goto unregister_blkdev;
3472 else if (result > 0)
3473 nvme_char_major = result;
3474
3475 nvme_class = class_create(THIS_MODULE, "nvme");
c727040b
AK		 3476 if (IS_ERR(nvme_class)) {
3477 result = PTR_ERR(nvme_class);
b3fffdef 3478 goto unregister_chrdev;
c727040b 3479 }
b3fffdef 3480
f3db22fe
KB		 3481 result = pci_register_driver(&nvme_driver);
3482 if (result)
b3fffdef 3483 goto destroy_class;
1fa6aead 3484 return 0;
b60503ba 3485
b3fffdef
KB		 3486 destroy_class:
3487 class_destroy(nvme_class);
3488 unregister_chrdev:
3489 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1fa6aead 3490 unregister_blkdev:
b60503ba 3491 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3492 kill_workq:
3493 destroy_workqueue(nvme_workq);
b60503ba
MW		 3494 return result;
3495}
3496
3497static void __exit nvme_exit(void)
3498{
3499 pci_unregister_driver(&nvme_driver);
3500 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3501 destroy_workqueue(nvme_workq);
b3fffdef
KB		 3502 class_destroy(nvme_class);
3503 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
b9afca3e 3504 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3505 _nvme_check_size();
b60503ba
MW		 3506}
3507
3508MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3509MODULE_LICENSE("GPL");
c78b4713 3510MODULE_VERSION("1.0");
b60503ba
MW		 3511module_init(nvme_init);
3512module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)