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lightnvm: add free and bad lun info to show luns
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
8de05535 15#include <linux/bitops.h>
b60503ba 16#include <linux/blkdev.h>
a4aea562 17#include <linux/blk-mq.h>
42f61420 18#include <linux/cpu.h>
fd63e9ce 19#include <linux/delay.h>
b60503ba
MW		 20#include <linux/errno.h>
21#include <linux/fs.h>
22#include <linux/genhd.h>
4cc09e2d 23#include <linux/hdreg.h>
5aff9382 24#include <linux/idr.h>
b60503ba
MW		 25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kdev_t.h>
1fa6aead 29#include <linux/kthread.h>
b60503ba 30#include <linux/kernel.h>
a5768aa8 31#include <linux/list_sort.h>
b60503ba
MW		 32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
e1e5e564 40#include <linux/t10-pi.h>
b60503ba 41#include <linux/types.h>
1d277a63 42#include <linux/pr.h>
5d0f6131 43#include <scsi/sg.h>
2f8e2c87 44#include <linux/io-64-nonatomic-lo-hi.h>
1d277a63 45#include <asm/unaligned.h>
797a796a 46
9d99a8dd 47#include <uapi/linux/nvme_ioctl.h>
f11bb3e2
CH		 48#include "nvme.h"
49
b3fffdef 50#define NVME_MINORS (1U << MINORBITS)
9d43cf64 51#define NVME_Q_DEPTH 1024
d31af0a3 52#define NVME_AQ_DEPTH 256
b60503ba
MW		 53#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
54#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 55#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 56#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 57
58static unsigned char admin_timeout = 60;
59module_param(admin_timeout, byte, 0644);
60MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 61
bd67608a
MW		 62unsigned char nvme_io_timeout = 30;
63module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 64MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 65
2484f407
DM		 66static unsigned char shutdown_timeout = 5;
67module_param(shutdown_timeout, byte, 0644);
68MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
69
b60503ba
MW		 70static int nvme_major;
71module_param(nvme_major, int, 0);
72
b3fffdef
KB		 73static int nvme_char_major;
74module_param(nvme_char_major, int, 0);
75
58ffacb5
MW		 76static int use_threaded_interrupts;
77module_param(use_threaded_interrupts, int, 0);
78
8ffaadf7
JD		 79static bool use_cmb_sqes = true;
80module_param(use_cmb_sqes, bool, 0644);
81MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
82
1fa6aead
MW		 83static DEFINE_SPINLOCK(dev_list_lock);
84static LIST_HEAD(dev_list);
85static struct task_struct *nvme_thread;
9a6b9458 86static struct workqueue_struct *nvme_workq;
b9afca3e 87static wait_queue_head_t nvme_kthread_wait;
1fa6aead 88
b3fffdef
KB		 89static struct class *nvme_class;
90
90667892 91static int __nvme_reset(struct nvme_dev *dev);
4cc06521 92static int nvme_reset(struct nvme_dev *dev);
a0fa9647 93static void nvme_process_cq(struct nvme_queue *nvmeq);
3cf519b5 94static void nvme_dead_ctrl(struct nvme_dev *dev);
d4b4ff8e 95
4d115420
KB		 96struct async_cmd_info {
97 struct kthread_work work;
98 struct kthread_worker *worker;
a4aea562 99 struct request *req;
4d115420
KB		 100 u32 result;
101 int status;
102 void *ctx;
103};
1fa6aead 104
b60503ba
MW		 105/*
106 * An NVM Express queue. Each device has at least two (one for admin
107 * commands and one for I/O commands).
108 */
109struct nvme_queue {
110 struct device *q_dmadev;
091b6092 111 struct nvme_dev *dev;
3193f07b 112 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 113 spinlock_t q_lock;
114 struct nvme_command *sq_cmds;
8ffaadf7 115 struct nvme_command __iomem *sq_cmds_io;
b60503ba 116 volatile struct nvme_completion *cqes;
42483228 117 struct blk_mq_tags **tags;
b60503ba
MW		 118 dma_addr_t sq_dma_addr;
119 dma_addr_t cq_dma_addr;
b60503ba
MW		 120 u32 __iomem *q_db;
121 u16 q_depth;
6222d172 122 s16 cq_vector;
b60503ba
MW		 123 u16 sq_head;
124 u16 sq_tail;
125 u16 cq_head;
c30341dc 126 u16 qid;
e9539f47
MW		 127 u8 cq_phase;
128 u8 cqe_seen;
4d115420 129 struct async_cmd_info cmdinfo;
b60503ba
MW		 130};
131
132/*
133 * Check we didin't inadvertently grow the command struct
134 */
135static inline void _nvme_check_size(void)
136{
137 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
138 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
139 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
140 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
141 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 142 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 143 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 144 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
145 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
146 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
147 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 148 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 149}
150
edd10d33 151typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 152 struct nvme_completion *);
153
e85248e5 154struct nvme_cmd_info {
c2f5b650
MW		 155 nvme_completion_fn fn;
156 void *ctx;
c30341dc 157 int aborted;
a4aea562 158 struct nvme_queue *nvmeq;
ac3dd5bd 159 struct nvme_iod iod[0];
e85248e5
MW		 160};
161
ac3dd5bd
JA		 162/*
163 * Max size of iod being embedded in the request payload
164 */
165#define NVME_INT_PAGES 2
166#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
fda631ff 167#define NVME_INT_MASK 0x01
ac3dd5bd
JA		 168
169/*
170 * Will slightly overestimate the number of pages needed. This is OK
171 * as it only leads to a small amount of wasted memory for the lifetime of
172 * the I/O.
173 */
174static int nvme_npages(unsigned size, struct nvme_dev *dev)
175{
176 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
177 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
178}
179
180static unsigned int nvme_cmd_size(struct nvme_dev *dev)
181{
182 unsigned int ret = sizeof(struct nvme_cmd_info);
183
184 ret += sizeof(struct nvme_iod);
185 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
186 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
187
188 return ret;
189}
190
a4aea562
MB		 191static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
192 unsigned int hctx_idx)
e85248e5 193{
a4aea562
MB		 194 struct nvme_dev *dev = data;
195 struct nvme_queue *nvmeq = dev->queues[0];
196
42483228
KB		 197 WARN_ON(hctx_idx != 0);
198 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
199 WARN_ON(nvmeq->tags);
200
a4aea562 201 hctx->driver_data = nvmeq;
42483228 202 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 203 return 0;
e85248e5
MW		 204}
205
4af0e21c
KB		 206static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
207{
208 struct nvme_queue *nvmeq = hctx->driver_data;
209
210 nvmeq->tags = NULL;
211}
212
a4aea562
MB		 213static int nvme_admin_init_request(void *data, struct request *req,
214 unsigned int hctx_idx, unsigned int rq_idx,
215 unsigned int numa_node)
22404274 216{
a4aea562
MB		 217 struct nvme_dev *dev = data;
218 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
219 struct nvme_queue *nvmeq = dev->queues[0];
220
221 BUG_ON(!nvmeq);
222 cmd->nvmeq = nvmeq;
223 return 0;
22404274
KB		 224}
225
a4aea562
MB		 226static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
227 unsigned int hctx_idx)
b60503ba 228{
a4aea562 229 struct nvme_dev *dev = data;
42483228 230 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
a4aea562 231
42483228
KB		 232 if (!nvmeq->tags)
233 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 234
42483228 235 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 236 hctx->driver_data = nvmeq;
237 return 0;
b60503ba
MW		 238}
239
a4aea562
MB		 240static int nvme_init_request(void *data, struct request *req,
241 unsigned int hctx_idx, unsigned int rq_idx,
242 unsigned int numa_node)
b60503ba 243{
a4aea562
MB		 244 struct nvme_dev *dev = data;
245 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
246 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
247
248 BUG_ON(!nvmeq);
249 cmd->nvmeq = nvmeq;
250 return 0;
251}
252
253static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
254 nvme_completion_fn handler)
255{
256 cmd->fn = handler;
257 cmd->ctx = ctx;
258 cmd->aborted = 0;
c917dfe5 259 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 260}
261
ac3dd5bd
JA		 262static void *iod_get_private(struct nvme_iod *iod)
263{
264 return (void *) (iod->private & ~0x1UL);
265}
266
267/*
268 * If bit 0 is set, the iod is embedded in the request payload.
269 */
270static bool iod_should_kfree(struct nvme_iod *iod)
271{
fda631ff 272 return (iod->private & NVME_INT_MASK) == 0;
ac3dd5bd
JA		 273}
274
c2f5b650
MW		 275/* Special values must be less than 0x1000 */
276#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 277#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
278#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
279#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 280
edd10d33 281static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 282 struct nvme_completion *cqe)
283{
284 if (ctx == CMD_CTX_CANCELLED)
285 return;
c2f5b650 286 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 287 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 288 "completed id %d twice on queue %d\n",
289 cqe->command_id, le16_to_cpup(&cqe->sq_id));
290 return;
291 }
292 if (ctx == CMD_CTX_INVALID) {
edd10d33 293 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 294 "invalid id %d completed on queue %d\n",
295 cqe->command_id, le16_to_cpup(&cqe->sq_id));
296 return;
297 }
edd10d33 298 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 299}
300
a4aea562 301static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 302{
c2f5b650 303 void *ctx;
b60503ba 304
859361a2 305 if (fn)
a4aea562
MB		 306 *fn = cmd->fn;
307 ctx = cmd->ctx;
308 cmd->fn = special_completion;
309 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 310 return ctx;
b60503ba
MW		 311}
312
a4aea562
MB		 313static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
314 struct nvme_completion *cqe)
3c0cf138 315{
a4aea562
MB		 316 u32 result = le32_to_cpup(&cqe->result);
317 u16 status = le16_to_cpup(&cqe->status) >> 1;
318
319 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
320 ++nvmeq->dev->event_limit;
a5768aa8
KB		 321 if (status != NVME_SC_SUCCESS)
322 return;
323
324 switch (result & 0xff07) {
325 case NVME_AER_NOTICE_NS_CHANGED:
326 dev_info(nvmeq->q_dmadev, "rescanning\n");
327 schedule_work(&nvmeq->dev->scan_work);
328 default:
329 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
330 }
b60503ba
MW		 331}
332
a4aea562
MB		 333static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
334 struct nvme_completion *cqe)
5a92e700 335{
a4aea562
MB		 336 struct request *req = ctx;
337
338 u16 status = le16_to_cpup(&cqe->status) >> 1;
339 u32 result = le32_to_cpup(&cqe->result);
a51afb54 340
42483228 341 blk_mq_free_request(req);
a51afb54 342
a4aea562
MB		 343 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
344 ++nvmeq->dev->abort_limit;
5a92e700
KB		 345}
346
a4aea562
MB		 347static void async_completion(struct nvme_queue *nvmeq, void *ctx,
348 struct nvme_completion *cqe)
b60503ba 349{
a4aea562
MB		 350 struct async_cmd_info *cmdinfo = ctx;
351 cmdinfo->result = le32_to_cpup(&cqe->result);
352 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
353 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
42483228 354 blk_mq_free_request(cmdinfo->req);
b60503ba
MW		 355}
356
a4aea562
MB		 357static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
358 unsigned int tag)
b60503ba 359{
42483228 360 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
a51afb54 361
a4aea562 362 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 363}
364
a4aea562
MB		 365/*
366 * Called with local interrupts disabled and the q_lock held. May not sleep.
367 */
368static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
369 nvme_completion_fn *fn)
4f5099af 370{
a4aea562
MB		 371 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
372 void *ctx;
373 if (tag >= nvmeq->q_depth) {
374 *fn = special_completion;
375 return CMD_CTX_INVALID;
376 }
377 if (fn)
378 *fn = cmd->fn;
379 ctx = cmd->ctx;
380 cmd->fn = special_completion;
381 cmd->ctx = CMD_CTX_COMPLETED;
382 return ctx;
b60503ba
MW		 383}
384
385/**
714a7a22 386 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 387 * @nvmeq: The queue to use
388 * @cmd: The command to send
389 *
390 * Safe to use from interrupt context
391 */
e3f879bf
SB		 392static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
393 struct nvme_command *cmd)
b60503ba 394{
a4aea562
MB		 395 u16 tail = nvmeq->sq_tail;
396
8ffaadf7
JD		 397 if (nvmeq->sq_cmds_io)
398 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
399 else
400 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
401
b60503ba
MW		 402 if (++tail == nvmeq->q_depth)
403 tail = 0;
7547881d 404 writel(tail, nvmeq->q_db);
b60503ba 405 nvmeq->sq_tail = tail;
b60503ba
MW		 406}
407
e3f879bf 408static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
a4aea562
MB		 409{
410 unsigned long flags;
a4aea562 411 spin_lock_irqsave(&nvmeq->q_lock, flags);
e3f879bf 412 __nvme_submit_cmd(nvmeq, cmd);
a4aea562 413 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
a4aea562
MB		 414}
415
eca18b23 416static __le64 **iod_list(struct nvme_iod *iod)
e025344c 417{
eca18b23 418 return ((void *)iod) + iod->offset;
e025344c
SMM		 419}
420
ac3dd5bd
JA		 421static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
422 unsigned nseg, unsigned long private)
eca18b23 423{
ac3dd5bd
JA		 424 iod->private = private;
425 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
426 iod->npages = -1;
427 iod->length = nbytes;
428 iod->nents = 0;
eca18b23 429}
b60503ba 430
eca18b23 431static struct nvme_iod *
ac3dd5bd
JA		 432__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
433 unsigned long priv, gfp_t gfp)
b60503ba 434{
eca18b23 435 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 436 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 437 sizeof(struct scatterlist) * nseg, gfp);
438
ac3dd5bd
JA		 439 if (iod)
440 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 441
442 return iod;
b60503ba
MW		 443}
444
ac3dd5bd
JA		 445static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
446 gfp_t gfp)
447{
448 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
449 sizeof(struct nvme_dsm_range);
ac3dd5bd
JA		 450 struct nvme_iod *iod;
451
452 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
453 size <= NVME_INT_BYTES(dev)) {
454 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
455
456 iod = cmd->iod;
ac3dd5bd 457 iod_init(iod, size, rq->nr_phys_segments,
fda631ff 458 (unsigned long) rq | NVME_INT_MASK);
ac3dd5bd
JA		 459 return iod;
460 }
461
462 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
463 (unsigned long) rq, gfp);
464}
465
d29ec824 466static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 467{
1d090624 468 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 469 int i;
470 __le64 **list = iod_list(iod);
471 dma_addr_t prp_dma = iod->first_dma;
472
473 if (iod->npages == 0)
474 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
475 for (i = 0; i < iod->npages; i++) {
476 __le64 *prp_list = list[i];
477 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
478 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
479 prp_dma = next_prp_dma;
480 }
ac3dd5bd
JA		 481
482 if (iod_should_kfree(iod))
483 kfree(iod);
b60503ba
MW		 484}
485
b4ff9c8d
KB		 486static int nvme_error_status(u16 status)
487{
488 switch (status & 0x7ff) {
489 case NVME_SC_SUCCESS:
490 return 0;
491 case NVME_SC_CAP_EXCEEDED:
492 return -ENOSPC;
493 default:
494 return -EIO;
495 }
496}
497
52b68d7e 498#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 499static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
500{
501 if (be32_to_cpu(pi->ref_tag) == v)
502 pi->ref_tag = cpu_to_be32(p);
503}
504
505static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
506{
507 if (be32_to_cpu(pi->ref_tag) == p)
508 pi->ref_tag = cpu_to_be32(v);
509}
510
511/**
512 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
513 *
514 * The virtual start sector is the one that was originally submitted by the
515 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
516 * start sector may be different. Remap protection information to match the
517 * physical LBA on writes, and back to the original seed on reads.
518 *
519 * Type 0 and 3 do not have a ref tag, so no remapping required.
520 */
521static void nvme_dif_remap(struct request *req,
522 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
523{
524 struct nvme_ns *ns = req->rq_disk->private_data;
525 struct bio_integrity_payload *bip;
526 struct t10_pi_tuple *pi;
527 void *p, *pmap;
528 u32 i, nlb, ts, phys, virt;
529
530 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
531 return;
532
533 bip = bio_integrity(req->bio);
534 if (!bip)
535 return;
536
537 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 538
539 p = pmap;
540 virt = bip_get_seed(bip);
541 phys = nvme_block_nr(ns, blk_rq_pos(req));
542 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
ac6fc48c 543 ts = ns->disk->queue->integrity.tuple_size;
e1e5e564
KB		 544
545 for (i = 0; i < nlb; i++, virt++, phys++) {
546 pi = (struct t10_pi_tuple *)p;
547 dif_swap(phys, virt, pi);
548 p += ts;
549 }
550 kunmap_atomic(pmap);
551}
552
52b68d7e
KB		 553static void nvme_init_integrity(struct nvme_ns *ns)
554{
555 struct blk_integrity integrity;
556
557 switch (ns->pi_type) {
558 case NVME_NS_DPS_PI_TYPE3:
0f8087ec 559 integrity.profile = &t10_pi_type3_crc;
52b68d7e
KB		 560 break;
561 case NVME_NS_DPS_PI_TYPE1:
562 case NVME_NS_DPS_PI_TYPE2:
0f8087ec 563 integrity.profile = &t10_pi_type1_crc;
52b68d7e
KB		 564 break;
565 default:
4125a09b 566 integrity.profile = NULL;
52b68d7e
KB		 567 break;
568 }
569 integrity.tuple_size = ns->ms;
570 blk_integrity_register(ns->disk, &integrity);
571 blk_queue_max_integrity_segments(ns->queue, 1);
572}
573#else /* CONFIG_BLK_DEV_INTEGRITY */
574static void nvme_dif_remap(struct request *req,
575 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
576{
577}
578static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
579{
580}
581static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
582{
583}
584static void nvme_init_integrity(struct nvme_ns *ns)
585{
586}
587#endif
588
a4aea562 589static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 590 struct nvme_completion *cqe)
591{
eca18b23 592 struct nvme_iod *iod = ctx;
ac3dd5bd 593 struct request *req = iod_get_private(iod);
a4aea562 594 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
b60503ba 595 u16 status = le16_to_cpup(&cqe->status) >> 1;
0dfc70c3 596 bool requeue = false;
81c04b94 597 int error = 0;
b60503ba 598
edd10d33 599 if (unlikely(status)) {
a4aea562
MB		 600 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
601 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 602 unsigned long flags;
603
0dfc70c3 604 requeue = true;
a4aea562 605 blk_mq_requeue_request(req);
c9d3bf88
KB		 606 spin_lock_irqsave(req->q->queue_lock, flags);
607 if (!blk_queue_stopped(req->q))
608 blk_mq_kick_requeue_list(req->q);
609 spin_unlock_irqrestore(req->q->queue_lock, flags);
0dfc70c3 610 goto release_iod;
edd10d33 611 }
f4829a9b 612
d29ec824 613 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
17188bb4 614 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
81c04b94
CH		 615 error = -EINTR;
616 else
617 error = status;
d29ec824 618 } else {
81c04b94 619 error = nvme_error_status(status);
d29ec824 620 }
f4829a9b
CH		 621 }
622
a0a931d6
KB		 623 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
624 u32 result = le32_to_cpup(&cqe->result);
625 req->special = (void *)(uintptr_t)result;
626 }
a4aea562
MB		 627
628 if (cmd_rq->aborted)
e75ec752 629 dev_warn(nvmeq->dev->dev,
a4aea562 630 "completing aborted command with status:%04x\n",
81c04b94 631 error);
a4aea562 632
0dfc70c3 633release_iod:
e1e5e564 634 if (iod->nents) {
e75ec752 635 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
a4aea562 636 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
e1e5e564
KB		 637 if (blk_integrity_rq(req)) {
638 if (!rq_data_dir(req))
639 nvme_dif_remap(req, nvme_dif_complete);
e75ec752 640 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
e1e5e564
KB		 641 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
642 }
643 }
edd10d33 644 nvme_free_iod(nvmeq->dev, iod);
3291fa57 645
0dfc70c3
KB		 646 if (likely(!requeue))
647 blk_mq_complete_request(req, error);
b60503ba
MW		 648}
649
184d2944 650/* length is in bytes. gfp flags indicates whether we may sleep. */
d29ec824
CH		 651static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
652 int total_len, gfp_t gfp)
ff22b54f 653{
99802a7a 654 struct dma_pool *pool;
eca18b23
MW		 655 int length = total_len;
656 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 657 int dma_len = sg_dma_len(sg);
658 u64 dma_addr = sg_dma_address(sg);
f137e0f1
MI		 659 u32 page_size = dev->page_size;
660 int offset = dma_addr & (page_size - 1);
e025344c 661 __le64 *prp_list;
eca18b23 662 __le64 **list = iod_list(iod);
e025344c 663 dma_addr_t prp_dma;
eca18b23 664 int nprps, i;
ff22b54f 665
1d090624 666 length -= (page_size - offset);
ff22b54f 667 if (length <= 0)
eca18b23 668 return total_len;
ff22b54f 669
1d090624 670 dma_len -= (page_size - offset);
ff22b54f 671 if (dma_len) {
1d090624 672 dma_addr += (page_size - offset);
ff22b54f
MW		 673 } else {
674 sg = sg_next(sg);
675 dma_addr = sg_dma_address(sg);
676 dma_len = sg_dma_len(sg);
677 }
678
1d090624 679 if (length <= page_size) {
edd10d33 680 iod->first_dma = dma_addr;
eca18b23 681 return total_len;
e025344c
SMM		 682 }
683
1d090624 684 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 685 if (nprps <= (256 / 8)) {
686 pool = dev->prp_small_pool;
eca18b23 687 iod->npages = 0;
99802a7a
MW		 688 } else {
689 pool = dev->prp_page_pool;
eca18b23 690 iod->npages = 1;
99802a7a
MW		 691 }
692
b77954cb
MW		 693 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
694 if (!prp_list) {
edd10d33 695 iod->first_dma = dma_addr;
eca18b23 696 iod->npages = -1;
1d090624 697 return (total_len - length) + page_size;
b77954cb 698 }
eca18b23
MW		 699 list[0] = prp_list;
700 iod->first_dma = prp_dma;
e025344c
SMM		 701 i = 0;
702 for (;;) {
1d090624 703 if (i == page_size >> 3) {
e025344c 704 __le64 *old_prp_list = prp_list;
b77954cb 705 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 706 if (!prp_list)
707 return total_len - length;
708 list[iod->npages++] = prp_list;
7523d834
MW		 709 prp_list[0] = old_prp_list[i - 1];
710 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
711 i = 1;
e025344c
SMM		 712 }
713 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 714 dma_len -= page_size;
715 dma_addr += page_size;
716 length -= page_size;
e025344c
SMM		 717 if (length <= 0)
718 break;
719 if (dma_len > 0)
720 continue;
721 BUG_ON(dma_len < 0);
722 sg = sg_next(sg);
723 dma_addr = sg_dma_address(sg);
724 dma_len = sg_dma_len(sg);
ff22b54f
MW		 725 }
726
eca18b23 727 return total_len;
ff22b54f
MW		 728}
729
d29ec824
CH		 730static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
731 struct nvme_iod *iod)
732{
498c4394 733 struct nvme_command cmnd;
d29ec824 734
498c4394
JD		 735 memcpy(&cmnd, req->cmd, sizeof(cmnd));
736 cmnd.rw.command_id = req->tag;
d29ec824 737 if (req->nr_phys_segments) {
498c4394
JD		 738 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
739 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
d29ec824
CH		 740 }
741
498c4394 742 __nvme_submit_cmd(nvmeq, &cmnd);
d29ec824
CH		 743}
744
a4aea562
MB		 745/*
746 * We reuse the small pool to allocate the 16-byte range here as it is not
747 * worth having a special pool for these or additional cases to handle freeing
748 * the iod.
749 */
750static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
751 struct request *req, struct nvme_iod *iod)
0e5e4f0e 752{
edd10d33
KB		 753 struct nvme_dsm_range *range =
754 (struct nvme_dsm_range *)iod_list(iod)[0];
498c4394 755 struct nvme_command cmnd;
0e5e4f0e 756
0e5e4f0e 757 range->cattr = cpu_to_le32(0);
a4aea562
MB		 758 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
759 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e 760
498c4394
JD		 761 memset(&cmnd, 0, sizeof(cmnd));
762 cmnd.dsm.opcode = nvme_cmd_dsm;
763 cmnd.dsm.command_id = req->tag;
764 cmnd.dsm.nsid = cpu_to_le32(ns->ns_id);
765 cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma);
766 cmnd.dsm.nr = 0;
767 cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
0e5e4f0e 768
498c4394 769 __nvme_submit_cmd(nvmeq, &cmnd);
0e5e4f0e
KB		 770}
771
a4aea562 772static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 773 int cmdid)
774{
498c4394 775 struct nvme_command cmnd;
00df5cb4 776
498c4394
JD		 777 memset(&cmnd, 0, sizeof(cmnd));
778 cmnd.common.opcode = nvme_cmd_flush;
779 cmnd.common.command_id = cmdid;
780 cmnd.common.nsid = cpu_to_le32(ns->ns_id);
00df5cb4 781
498c4394 782 __nvme_submit_cmd(nvmeq, &cmnd);
00df5cb4
MW		 783}
784
a4aea562
MB		 785static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
786 struct nvme_ns *ns)
b60503ba 787{
ac3dd5bd 788 struct request *req = iod_get_private(iod);
498c4394 789 struct nvme_command cmnd;
a4aea562
MB		 790 u16 control = 0;
791 u32 dsmgmt = 0;
00df5cb4 792
a4aea562 793 if (req->cmd_flags & REQ_FUA)
b60503ba 794 control |= NVME_RW_FUA;
a4aea562 795 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 796 control |= NVME_RW_LR;
797
a4aea562 798 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 799 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
800
498c4394
JD		 801 memset(&cmnd, 0, sizeof(cmnd));
802 cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
803 cmnd.rw.command_id = req->tag;
804 cmnd.rw.nsid = cpu_to_le32(ns->ns_id);
805 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
806 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
807 cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
808 cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
b60503ba 809
e19b127f 810 if (ns->ms) {
e1e5e564
KB		 811 switch (ns->pi_type) {
812 case NVME_NS_DPS_PI_TYPE3:
813 control |= NVME_RW_PRINFO_PRCHK_GUARD;
814 break;
815 case NVME_NS_DPS_PI_TYPE1:
816 case NVME_NS_DPS_PI_TYPE2:
817 control |= NVME_RW_PRINFO_PRCHK_GUARD |
818 NVME_RW_PRINFO_PRCHK_REF;
498c4394 819 cmnd.rw.reftag = cpu_to_le32(
e1e5e564
KB		 820 nvme_block_nr(ns, blk_rq_pos(req)));
821 break;
822 }
e19b127f
AP		 823 if (blk_integrity_rq(req))
824 cmnd.rw.metadata =
825 cpu_to_le64(sg_dma_address(iod->meta_sg));
826 else
827 control |= NVME_RW_PRINFO_PRACT;
828 }
e1e5e564 829
498c4394
JD		 830 cmnd.rw.control = cpu_to_le16(control);
831 cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 832
498c4394 833 __nvme_submit_cmd(nvmeq, &cmnd);
b60503ba 834
1974b1ae 835 return 0;
edd10d33
KB		 836}
837
d29ec824
CH		 838/*
839 * NOTE: ns is NULL when called on the admin queue.
840 */
a4aea562
MB		 841static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
842 const struct blk_mq_queue_data *bd)
edd10d33 843{
a4aea562
MB		 844 struct nvme_ns *ns = hctx->queue->queuedata;
845 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 846 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 847 struct request *req = bd->rq;
848 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 849 struct nvme_iod *iod;
a4aea562 850 enum dma_data_direction dma_dir;
edd10d33 851
e1e5e564
KB		 852 /*
853 * If formated with metadata, require the block layer provide a buffer
854 * unless this namespace is formated such that the metadata can be
855 * stripped/generated by the controller with PRACT=1.
856 */
d29ec824 857 if (ns && ns->ms && !blk_integrity_rq(req)) {
71feb364
KB		 858 if (!(ns->pi_type && ns->ms == 8) &&
859 req->cmd_type != REQ_TYPE_DRV_PRIV) {
f4829a9b 860 blk_mq_complete_request(req, -EFAULT);
e1e5e564
KB		 861 return BLK_MQ_RQ_QUEUE_OK;
862 }
863 }
864
d29ec824 865 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
edd10d33 866 if (!iod)
fe54303e 867 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 868
a4aea562 869 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 870 void *range;
871 /*
872 * We reuse the small pool to allocate the 16-byte range here
873 * as it is not worth having a special pool for these or
874 * additional cases to handle freeing the iod.
875 */
d29ec824 876 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
edd10d33 877 &iod->first_dma);
a4aea562 878 if (!range)
fe54303e 879 goto retry_cmd;
edd10d33
KB		 880 iod_list(iod)[0] = (__le64 *)range;
881 iod->npages = 0;
ac3dd5bd 882 } else if (req->nr_phys_segments) {
a4aea562
MB		 883 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
884
ac3dd5bd 885 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 886 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 887 if (!iod->nents)
888 goto error_cmd;
a4aea562
MB		 889
890 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 891 goto retry_cmd;
a4aea562 892
fe54303e 893 if (blk_rq_bytes(req) !=
d29ec824
CH		 894 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
895 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
fe54303e
JA		 896 goto retry_cmd;
897 }
e1e5e564
KB		 898 if (blk_integrity_rq(req)) {
899 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
900 goto error_cmd;
901
902 sg_init_table(iod->meta_sg, 1);
903 if (blk_rq_map_integrity_sg(
904 req->q, req->bio, iod->meta_sg) != 1)
905 goto error_cmd;
906
907 if (rq_data_dir(req))
908 nvme_dif_remap(req, nvme_dif_prep);
909
910 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
911 goto error_cmd;
912 }
edd10d33 913 }
1974b1ae 914
9af8785a 915 nvme_set_info(cmd, iod, req_completion);
a4aea562 916 spin_lock_irq(&nvmeq->q_lock);
d29ec824
CH		 917 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
918 nvme_submit_priv(nvmeq, req, iod);
919 else if (req->cmd_flags & REQ_DISCARD)
a4aea562
MB		 920 nvme_submit_discard(nvmeq, ns, req, iod);
921 else if (req->cmd_flags & REQ_FLUSH)
922 nvme_submit_flush(nvmeq, ns, req->tag);
923 else
924 nvme_submit_iod(nvmeq, iod, ns);
925
926 nvme_process_cq(nvmeq);
927 spin_unlock_irq(&nvmeq->q_lock);
928 return BLK_MQ_RQ_QUEUE_OK;
929
fe54303e 930 error_cmd:
d29ec824 931 nvme_free_iod(dev, iod);
fe54303e
JA		 932 return BLK_MQ_RQ_QUEUE_ERROR;
933 retry_cmd:
d29ec824 934 nvme_free_iod(dev, iod);
fe54303e 935 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 936}
937
a0fa9647 938static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
b60503ba 939{
82123460 940 u16 head, phase;
b60503ba 941
b60503ba 942 head = nvmeq->cq_head;
82123460 943 phase = nvmeq->cq_phase;
b60503ba
MW		 944
945 for (;;) {
c2f5b650
MW		 946 void *ctx;
947 nvme_completion_fn fn;
b60503ba 948 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 949 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 950 break;
951 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
952 if (++head == nvmeq->q_depth) {
953 head = 0;
82123460 954 phase = !phase;
b60503ba 955 }
a0fa9647
JA		 956 if (tag && *tag == cqe.command_id)
957 *tag = -1;
a4aea562 958 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 959 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 960 }
961
962 /* If the controller ignores the cq head doorbell and continuously
963 * writes to the queue, it is theoretically possible to wrap around
964 * the queue twice and mistakenly return IRQ_NONE. Linux only
965 * requires that 0.1% of your interrupts are handled, so this isn't
966 * a big problem.
967 */
82123460 968 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
a0fa9647 969 return;
b60503ba 970
b80d5ccc 971 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 972 nvmeq->cq_head = head;
82123460 973 nvmeq->cq_phase = phase;
b60503ba 974
e9539f47 975 nvmeq->cqe_seen = 1;
a0fa9647
JA		 976}
977
978static void nvme_process_cq(struct nvme_queue *nvmeq)
979{
980 __nvme_process_cq(nvmeq, NULL);
b60503ba
MW		 981}
982
983static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 984{
985 irqreturn_t result;
986 struct nvme_queue *nvmeq = data;
987 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 988 nvme_process_cq(nvmeq);
989 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
990 nvmeq->cqe_seen = 0;
58ffacb5
MW		 991 spin_unlock(&nvmeq->q_lock);
992 return result;
993}
994
995static irqreturn_t nvme_irq_check(int irq, void *data)
996{
997 struct nvme_queue *nvmeq = data;
998 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
999 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
1000 return IRQ_NONE;
1001 return IRQ_WAKE_THREAD;
1002}
1003
a0fa9647
JA		 1004static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1005{
1006 struct nvme_queue *nvmeq = hctx->driver_data;
1007
1008 if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
1009 nvmeq->cq_phase) {
1010 spin_lock_irq(&nvmeq->q_lock);
1011 __nvme_process_cq(nvmeq, &tag);
1012 spin_unlock_irq(&nvmeq->q_lock);
1013
1014 if (tag == -1)
1015 return 1;
1016 }
1017
1018 return 0;
1019}
1020
b60503ba
MW		 1021/*
1022 * Returns 0 on success. If the result is negative, it's a Linux error code;
1023 * if the result is positive, it's an NVM Express status code
1024 */
d29ec824
CH		 1025int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1026 void *buffer, void __user *ubuffer, unsigned bufflen,
1027 u32 *result, unsigned timeout)
b60503ba 1028{
d29ec824
CH		 1029 bool write = cmd->common.opcode & 1;
1030 struct bio *bio = NULL;
f705f837 1031 struct request *req;
d29ec824 1032 int ret;
b60503ba 1033
d29ec824 1034 req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
f705f837
CH		 1035 if (IS_ERR(req))
1036 return PTR_ERR(req);
b60503ba 1037
d29ec824 1038 req->cmd_type = REQ_TYPE_DRV_PRIV;
e112af0d 1039 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d29ec824
CH		 1040 req->__data_len = 0;
1041 req->__sector = (sector_t) -1;
1042 req->bio = req->biotail = NULL;
b60503ba 1043
f4ff414a 1044 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
a4aea562 1045
d29ec824
CH		 1046 req->cmd = (unsigned char *)cmd;
1047 req->cmd_len = sizeof(struct nvme_command);
a0a931d6 1048 req->special = (void *)0;
b60503ba 1049
d29ec824 1050 if (buffer && bufflen) {
71baba4b
MG		 1051 ret = blk_rq_map_kern(q, req, buffer, bufflen,
1052 __GFP_DIRECT_RECLAIM);
d29ec824
CH		 1053 if (ret)
1054 goto out;
1055 } else if (ubuffer && bufflen) {
71baba4b
MG		 1056 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
1057 __GFP_DIRECT_RECLAIM);
d29ec824
CH		 1058 if (ret)
1059 goto out;
1060 bio = req->bio;
1061 }
3c0cf138 1062
d29ec824
CH		 1063 blk_execute_rq(req->q, NULL, req, 0);
1064 if (bio)
1065 blk_rq_unmap_user(bio);
b60503ba 1066 if (result)
a0a931d6 1067 *result = (u32)(uintptr_t)req->special;
d29ec824
CH		 1068 ret = req->errors;
1069 out:
f705f837 1070 blk_mq_free_request(req);
d29ec824 1071 return ret;
f705f837
CH		 1072}
1073
d29ec824
CH		 1074int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1075 void *buffer, unsigned bufflen)
f705f837 1076{
d29ec824 1077 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
b60503ba
MW		 1078}
1079
a4aea562
MB		 1080static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1081{
1082 struct nvme_queue *nvmeq = dev->queues[0];
1083 struct nvme_command c;
1084 struct nvme_cmd_info *cmd_info;
1085 struct request *req;
1086
1efccc9d 1087 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
9f173b33
DC		 1088 if (IS_ERR(req))
1089 return PTR_ERR(req);
a4aea562 1090
c917dfe5 1091 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562 1092 cmd_info = blk_mq_rq_to_pdu(req);
1efccc9d 1093 nvme_set_info(cmd_info, NULL, async_req_completion);
a4aea562
MB		 1094
1095 memset(&c, 0, sizeof(c));
1096 c.common.opcode = nvme_admin_async_event;
1097 c.common.command_id = req->tag;
1098
42483228 1099 blk_mq_free_request(req);
e3f879bf
SB		 1100 __nvme_submit_cmd(nvmeq, &c);
1101 return 0;
a4aea562
MB		 1102}
1103
1104static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 1105 struct nvme_command *cmd,
1106 struct async_cmd_info *cmdinfo, unsigned timeout)
1107{
a4aea562
MB		 1108 struct nvme_queue *nvmeq = dev->queues[0];
1109 struct request *req;
1110 struct nvme_cmd_info *cmd_rq;
4d115420 1111
a4aea562 1112 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 1113 if (IS_ERR(req))
1114 return PTR_ERR(req);
a4aea562
MB		 1115
1116 req->timeout = timeout;
1117 cmd_rq = blk_mq_rq_to_pdu(req);
1118 cmdinfo->req = req;
1119 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 1120 cmdinfo->status = -EINTR;
a4aea562
MB		 1121
1122 cmd->common.command_id = req->tag;
1123
e3f879bf
SB		 1124 nvme_submit_cmd(nvmeq, cmd);
1125 return 0;
4d115420
KB		 1126}
1127
b60503ba
MW		 1128static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1129{
b60503ba
MW		 1130 struct nvme_command c;
1131
1132 memset(&c, 0, sizeof(c));
1133 c.delete_queue.opcode = opcode;
1134 c.delete_queue.qid = cpu_to_le16(id);
1135
d29ec824 1136 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1137}
1138
1139static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1140 struct nvme_queue *nvmeq)
1141{
b60503ba
MW		 1142 struct nvme_command c;
1143 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1144
d29ec824
CH		 1145 /*
1146 * Note: we (ab)use the fact the the prp fields survive if no data
1147 * is attached to the request.
1148 */
b60503ba
MW		 1149 memset(&c, 0, sizeof(c));
1150 c.create_cq.opcode = nvme_admin_create_cq;
1151 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1152 c.create_cq.cqid = cpu_to_le16(qid);
1153 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1154 c.create_cq.cq_flags = cpu_to_le16(flags);
1155 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1156
d29ec824 1157 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1158}
1159
1160static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1161 struct nvme_queue *nvmeq)
1162{
b60503ba
MW		 1163 struct nvme_command c;
1164 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1165
d29ec824
CH		 1166 /*
1167 * Note: we (ab)use the fact the the prp fields survive if no data
1168 * is attached to the request.
1169 */
b60503ba
MW		 1170 memset(&c, 0, sizeof(c));
1171 c.create_sq.opcode = nvme_admin_create_sq;
1172 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1173 c.create_sq.sqid = cpu_to_le16(qid);
1174 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1175 c.create_sq.sq_flags = cpu_to_le16(flags);
1176 c.create_sq.cqid = cpu_to_le16(qid);
1177
d29ec824 1178 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1179}
1180
1181static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1182{
1183 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1184}
1185
1186static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1187{
1188 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1189}
1190
d29ec824 1191int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
bc5fc7e4 1192{
e44ac588 1193 struct nvme_command c = { };
d29ec824 1194 int error;
bc5fc7e4 1195
e44ac588
AM		 1196 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1197 c.identify.opcode = nvme_admin_identify;
1198 c.identify.cns = cpu_to_le32(1);
1199
d29ec824
CH		 1200 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1201 if (!*id)
1202 return -ENOMEM;
bc5fc7e4 1203
d29ec824
CH		 1204 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1205 sizeof(struct nvme_id_ctrl));
1206 if (error)
1207 kfree(*id);
1208 return error;
1209}
1210
1211int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1212 struct nvme_id_ns **id)
1213{
e44ac588 1214 struct nvme_command c = { };
d29ec824 1215 int error;
bc5fc7e4 1216
e44ac588
AM		 1217 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1218 c.identify.opcode = nvme_admin_identify,
1219 c.identify.nsid = cpu_to_le32(nsid),
1220
d29ec824
CH		 1221 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1222 if (!*id)
1223 return -ENOMEM;
1224
1225 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1226 sizeof(struct nvme_id_ns));
1227 if (error)
1228 kfree(*id);
1229 return error;
bc5fc7e4
MW		 1230}
1231
5d0f6131 1232int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1233 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1234{
1235 struct nvme_command c;
1236
1237 memset(&c, 0, sizeof(c));
1238 c.features.opcode = nvme_admin_get_features;
a42cecce 1239 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1240 c.features.prp1 = cpu_to_le64(dma_addr);
1241 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1242
d29ec824
CH		 1243 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1244 result, 0);
df348139
MW		 1245}
1246
5d0f6131
VV		 1247int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1248 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1249{
1250 struct nvme_command c;
1251
1252 memset(&c, 0, sizeof(c));
1253 c.features.opcode = nvme_admin_set_features;
1254 c.features.prp1 = cpu_to_le64(dma_addr);
1255 c.features.fid = cpu_to_le32(fid);
1256 c.features.dword11 = cpu_to_le32(dword11);
1257
d29ec824
CH		 1258 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1259 result, 0);
1260}
1261
1262int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1263{
e44ac588
AM		 1264 struct nvme_command c = { };
1265 int error;
1266
1267 c.common.opcode = nvme_admin_get_log_page,
1268 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
1269 c.common.cdw10[0] = cpu_to_le32(
d29ec824
CH		 1270 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1271 NVME_LOG_SMART),
d29ec824
CH		 1272
1273 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1274 if (!*log)
1275 return -ENOMEM;
1276
1277 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1278 sizeof(struct nvme_smart_log));
1279 if (error)
1280 kfree(*log);
1281 return error;
bc5fc7e4
MW		 1282}
1283
c30341dc 1284/**
a4aea562 1285 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1286 *
1287 * Schedule controller reset if the command was already aborted once before and
1288 * still hasn't been returned to the driver, or if this is the admin queue.
1289 */
a4aea562 1290static void nvme_abort_req(struct request *req)
c30341dc 1291{
a4aea562
MB		 1292 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1293 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1294 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1295 struct request *abort_req;
1296 struct nvme_cmd_info *abort_cmd;
1297 struct nvme_command cmd;
c30341dc 1298
a4aea562 1299 if (!nvmeq->qid || cmd_rq->aborted) {
90667892
CH		 1300 spin_lock(&dev_list_lock);
1301 if (!__nvme_reset(dev)) {
1302 dev_warn(dev->dev,
1303 "I/O %d QID %d timeout, reset controller\n",
1304 req->tag, nvmeq->qid);
1305 }
1306 spin_unlock(&dev_list_lock);
c30341dc
KB		 1307 return;
1308 }
1309
1310 if (!dev->abort_limit)
1311 return;
1312
a4aea562
MB		 1313 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1314 false);
9f173b33 1315 if (IS_ERR(abort_req))
c30341dc
KB		 1316 return;
1317
a4aea562
MB		 1318 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1319 nvme_set_info(abort_cmd, abort_req, abort_completion);
1320
c30341dc
KB		 1321 memset(&cmd, 0, sizeof(cmd));
1322 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1323 cmd.abort.cid = req->tag;
c30341dc 1324 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1325 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1326
1327 --dev->abort_limit;
a4aea562 1328 cmd_rq->aborted = 1;
c30341dc 1329
a4aea562 1330 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1331 nvmeq->qid);
e3f879bf 1332 nvme_submit_cmd(dev->queues[0], &cmd);
c30341dc
KB		 1333}
1334
42483228 1335static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
a09115b2 1336{
a4aea562
MB		 1337 struct nvme_queue *nvmeq = data;
1338 void *ctx;
1339 nvme_completion_fn fn;
1340 struct nvme_cmd_info *cmd;
cef6a948
KB		 1341 struct nvme_completion cqe;
1342
1343 if (!blk_mq_request_started(req))
1344 return;
a09115b2 1345
a4aea562 1346 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1347
a4aea562
MB		 1348 if (cmd->ctx == CMD_CTX_CANCELLED)
1349 return;
1350
cef6a948
KB		 1351 if (blk_queue_dying(req->q))
1352 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1353 else
1354 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1355
1356
a4aea562
MB		 1357 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1358 req->tag, nvmeq->qid);
1359 ctx = cancel_cmd_info(cmd, &fn);
1360 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1361}
1362
a4aea562 1363static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1364{
a4aea562
MB		 1365 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1366 struct nvme_queue *nvmeq = cmd->nvmeq;
1367
1368 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1369 nvmeq->qid);
7a509a6b 1370 spin_lock_irq(&nvmeq->q_lock);
07836e65 1371 nvme_abort_req(req);
7a509a6b 1372 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1373
07836e65
KB		 1374 /*
1375 * The aborted req will be completed on receiving the abort req.
1376 * We enable the timer again. If hit twice, it'll cause a device reset,
1377 * as the device then is in a faulty state.
1378 */
1379 return BLK_EH_RESET_TIMER;
a4aea562 1380}
22404274 1381
a4aea562
MB		 1382static void nvme_free_queue(struct nvme_queue *nvmeq)
1383{
9e866774
MW		 1384 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1385 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD		 1386 if (nvmeq->sq_cmds)
1387 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774
MW		 1388 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1389 kfree(nvmeq);
1390}
1391
a1a5ef99 1392static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1393{
1394 int i;
1395
a1a5ef99 1396 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1397 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1398 dev->queue_count--;
a4aea562 1399 dev->queues[i] = NULL;
f435c282 1400 nvme_free_queue(nvmeq);
121c7ad4 1401 }
22404274
KB		 1402}
1403
4d115420
KB		 1404/**
1405 * nvme_suspend_queue - put queue into suspended state
1406 * @nvmeq - queue to suspend
4d115420
KB		 1407 */
1408static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1409{
2b25d981 1410 int vector;
b60503ba 1411
a09115b2 1412 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1413 if (nvmeq->cq_vector == -1) {
1414 spin_unlock_irq(&nvmeq->q_lock);
1415 return 1;
1416 }
1417 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1418 nvmeq->dev->online_queues--;
2b25d981 1419 nvmeq->cq_vector = -1;
a09115b2
MW		 1420 spin_unlock_irq(&nvmeq->q_lock);
1421
6df3dbc8
KB		 1422 if (!nvmeq->qid && nvmeq->dev->admin_q)
1423 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1424
aba2080f
MW		 1425 irq_set_affinity_hint(vector, NULL);
1426 free_irq(vector, nvmeq);
b60503ba 1427
4d115420
KB		 1428 return 0;
1429}
b60503ba 1430
4d115420
KB		 1431static void nvme_clear_queue(struct nvme_queue *nvmeq)
1432{
22404274 1433 spin_lock_irq(&nvmeq->q_lock);
42483228
KB		 1434 if (nvmeq->tags && *nvmeq->tags)
1435 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
22404274 1436 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1437}
1438
4d115420
KB		 1439static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1440{
a4aea562 1441 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1442
1443 if (!nvmeq)
1444 return;
1445 if (nvme_suspend_queue(nvmeq))
1446 return;
1447
0e53d180
KB		 1448 /* Don't tell the adapter to delete the admin queue.
1449 * Don't tell a removed adapter to delete IO queues. */
1450 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1451 adapter_delete_sq(dev, qid);
1452 adapter_delete_cq(dev, qid);
1453 }
07836e65
KB		 1454
1455 spin_lock_irq(&nvmeq->q_lock);
1456 nvme_process_cq(nvmeq);
1457 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1458}
1459
8ffaadf7
JD		 1460static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1461 int entry_size)
1462{
1463 int q_depth = dev->q_depth;
1464 unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size);
1465
1466 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99
JD		 1467 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1468 mem_per_q = round_down(mem_per_q, dev->page_size);
1469 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1470
1471 /*
1472 * Ensure the reduced q_depth is above some threshold where it
1473 * would be better to map queues in system memory with the
1474 * original depth
1475 */
1476 if (q_depth < 64)
1477 return -ENOMEM;
1478 }
1479
1480 return q_depth;
1481}
1482
1483static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1484 int qid, int depth)
1485{
1486 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1487 unsigned offset = (qid - 1) *
1488 roundup(SQ_SIZE(depth), dev->page_size);
1489 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1490 nvmeq->sq_cmds_io = dev->cmb + offset;
1491 } else {
1492 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1493 &nvmeq->sq_dma_addr, GFP_KERNEL);
1494 if (!nvmeq->sq_cmds)
1495 return -ENOMEM;
1496 }
1497
1498 return 0;
1499}
1500
b60503ba 1501static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1502 int depth)
b60503ba 1503{
a4aea562 1504 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1505 if (!nvmeq)
1506 return NULL;
1507
e75ec752 1508 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1509 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1510 if (!nvmeq->cqes)
1511 goto free_nvmeq;
b60503ba 1512
8ffaadf7 1513 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1514 goto free_cqdma;
1515
e75ec752 1516 nvmeq->q_dmadev = dev->dev;
091b6092 1517 nvmeq->dev = dev;
3193f07b
MW		 1518 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1519 dev->instance, qid);
b60503ba
MW		 1520 spin_lock_init(&nvmeq->q_lock);
1521 nvmeq->cq_head = 0;
82123460 1522 nvmeq->cq_phase = 1;
b80d5ccc 1523 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1524 nvmeq->q_depth = depth;
c30341dc 1525 nvmeq->qid = qid;
758dd7fd 1526 nvmeq->cq_vector = -1;
a4aea562 1527 dev->queues[qid] = nvmeq;
b60503ba 1528
36a7e993
JD		 1529 /* make sure queue descriptor is set before queue count, for kthread */
1530 mb();
1531 dev->queue_count++;
1532
b60503ba
MW		 1533 return nvmeq;
1534
1535 free_cqdma:
e75ec752 1536 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1537 nvmeq->cq_dma_addr);
1538 free_nvmeq:
1539 kfree(nvmeq);
1540 return NULL;
1541}
1542
3001082c
MW		 1543static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1544 const char *name)
1545{
58ffacb5
MW		 1546 if (use_threaded_interrupts)
1547 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1548 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1549 name, nvmeq);
3001082c 1550 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1551 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1552}
1553
22404274 1554static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1555{
22404274 1556 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1557
7be50e93 1558 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1559 nvmeq->sq_tail = 0;
1560 nvmeq->cq_head = 0;
1561 nvmeq->cq_phase = 1;
b80d5ccc 1562 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1563 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1564 dev->online_queues++;
7be50e93 1565 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1566}
1567
1568static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1569{
1570 struct nvme_dev *dev = nvmeq->dev;
1571 int result;
3f85d50b 1572
2b25d981 1573 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1574 result = adapter_alloc_cq(dev, qid, nvmeq);
1575 if (result < 0)
22404274 1576 return result;
b60503ba
MW		 1577
1578 result = adapter_alloc_sq(dev, qid, nvmeq);
1579 if (result < 0)
1580 goto release_cq;
1581
3193f07b 1582 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1583 if (result < 0)
1584 goto release_sq;
1585
22404274 1586 nvme_init_queue(nvmeq, qid);
22404274 1587 return result;
b60503ba
MW		 1588
1589 release_sq:
1590 adapter_delete_sq(dev, qid);
1591 release_cq:
1592 adapter_delete_cq(dev, qid);
22404274 1593 return result;
b60503ba
MW		 1594}
1595
ba47e386
MW		 1596static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1597{
1598 unsigned long timeout;
1599 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1600
1601 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1602
1603 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1604 msleep(100);
1605 if (fatal_signal_pending(current))
1606 return -EINTR;
1607 if (time_after(jiffies, timeout)) {
e75ec752 1608 dev_err(dev->dev,
27e8166c
MW		 1609 "Device not ready; aborting %s\n", enabled ?
1610 "initialisation" : "reset");
ba47e386
MW		 1611 return -ENODEV;
1612 }
1613 }
1614
1615 return 0;
1616}
1617
1618/*
1619 * If the device has been passed off to us in an enabled state, just clear
1620 * the enabled bit. The spec says we should set the 'shutdown notification
1621 * bits', but doing so may cause the device to complete commands to the
1622 * admin queue ... and we don't know what memory that might be pointing at!
1623 */
1624static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1625{
01079522
DM		 1626 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1627 dev->ctrl_config &= ~NVME_CC_ENABLE;
1628 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1629
ba47e386
MW		 1630 return nvme_wait_ready(dev, cap, false);
1631}
1632
1633static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1634{
01079522
DM		 1635 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1636 dev->ctrl_config |= NVME_CC_ENABLE;
1637 writel(dev->ctrl_config, &dev->bar->cc);
1638
ba47e386
MW		 1639 return nvme_wait_ready(dev, cap, true);
1640}
1641
1894d8f1
KB		 1642static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1643{
1644 unsigned long timeout;
1894d8f1 1645
01079522
DM		 1646 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1647 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1648
1649 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1650
2484f407 1651 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1652 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1653 NVME_CSTS_SHST_CMPLT) {
1654 msleep(100);
1655 if (fatal_signal_pending(current))
1656 return -EINTR;
1657 if (time_after(jiffies, timeout)) {
e75ec752 1658 dev_err(dev->dev,
1894d8f1
KB		 1659 "Device shutdown incomplete; abort shutdown\n");
1660 return -ENODEV;
1661 }
1662 }
1663
1664 return 0;
1665}
1666
a4aea562 1667static struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1668 .queue_rq = nvme_queue_rq,
a4aea562
MB		 1669 .map_queue = blk_mq_map_queue,
1670 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1671 .exit_hctx = nvme_admin_exit_hctx,
a4aea562
MB		 1672 .init_request = nvme_admin_init_request,
1673 .timeout = nvme_timeout,
1674};
1675
1676static struct blk_mq_ops nvme_mq_ops = {
1677 .queue_rq = nvme_queue_rq,
1678 .map_queue = blk_mq_map_queue,
1679 .init_hctx = nvme_init_hctx,
1680 .init_request = nvme_init_request,
1681 .timeout = nvme_timeout,
a0fa9647 1682 .poll = nvme_poll,
a4aea562
MB		 1683};
1684
ea191d2f
KB		 1685static void nvme_dev_remove_admin(struct nvme_dev *dev)
1686{
1687 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1688 blk_cleanup_queue(dev->admin_q);
1689 blk_mq_free_tag_set(&dev->admin_tagset);
1690 }
1691}
1692
a4aea562
MB		 1693static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1694{
1695 if (!dev->admin_q) {
1696 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1697 dev->admin_tagset.nr_hw_queues = 1;
1698 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1efccc9d 1699 dev->admin_tagset.reserved_tags = 1;
a4aea562 1700 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1701 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
ac3dd5bd 1702 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1703 dev->admin_tagset.driver_data = dev;
1704
1705 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1706 return -ENOMEM;
1707
1708 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1709 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1710 blk_mq_free_tag_set(&dev->admin_tagset);
1711 return -ENOMEM;
1712 }
ea191d2f
KB		 1713 if (!blk_get_queue(dev->admin_q)) {
1714 nvme_dev_remove_admin(dev);
4af0e21c 1715 dev->admin_q = NULL;
ea191d2f
KB		 1716 return -ENODEV;
1717 }
0fb59cbc
KB		 1718 } else
1719 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1720
1721 return 0;
1722}
1723
8d85fce7 1724static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1725{
ba47e386 1726 int result;
b60503ba 1727 u32 aqa;
a310acd7 1728 u64 cap = lo_hi_readq(&dev->bar->cap);
b60503ba 1729 struct nvme_queue *nvmeq;
1d090624
KB		 1730 unsigned page_shift = PAGE_SHIFT;
1731 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1732 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1733
1734 if (page_shift < dev_page_min) {
e75ec752 1735 dev_err(dev->dev,
1d090624
KB		 1736 "Minimum device page size (%u) too large for "
1737 "host (%u)\n", 1 << dev_page_min,
1738 1 << page_shift);
1739 return -ENODEV;
1740 }
1741 if (page_shift > dev_page_max) {
e75ec752 1742 dev_info(dev->dev,
1d090624
KB		 1743 "Device maximum page size (%u) smaller than "
1744 "host (%u); enabling work-around\n",
1745 1 << dev_page_max, 1 << page_shift);
1746 page_shift = dev_page_max;
1747 }
b60503ba 1748
dfbac8c7
KB		 1749 dev->subsystem = readl(&dev->bar->vs) >= NVME_VS(1, 1) ?
1750 NVME_CAP_NSSRC(cap) : 0;
1751
1752 if (dev->subsystem && (readl(&dev->bar->csts) & NVME_CSTS_NSSRO))
1753 writel(NVME_CSTS_NSSRO, &dev->bar->csts);
1754
ba47e386
MW		 1755 result = nvme_disable_ctrl(dev, cap);
1756 if (result < 0)
1757 return result;
b60503ba 1758
a4aea562 1759 nvmeq = dev->queues[0];
cd638946 1760 if (!nvmeq) {
2b25d981 1761 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1762 if (!nvmeq)
1763 return -ENOMEM;
cd638946 1764 }
b60503ba
MW		 1765
1766 aqa = nvmeq->q_depth - 1;
1767 aqa |= aqa << 16;
1768
1d090624
KB		 1769 dev->page_size = 1 << page_shift;
1770
01079522 1771 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1772 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1773 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1774 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1775
1776 writel(aqa, &dev->bar->aqa);
a310acd7
SG		 1777 lo_hi_writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1778 lo_hi_writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1779
ba47e386 1780 result = nvme_enable_ctrl(dev, cap);
025c557a 1781 if (result)
a4aea562
MB		 1782 goto free_nvmeq;
1783
2b25d981 1784 nvmeq->cq_vector = 0;
3193f07b 1785 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
758dd7fd
JD		 1786 if (result) {
1787 nvmeq->cq_vector = -1;
0fb59cbc 1788 goto free_nvmeq;
758dd7fd 1789 }
025c557a 1790
b60503ba 1791 return result;
a4aea562 1792
a4aea562
MB		 1793 free_nvmeq:
1794 nvme_free_queues(dev, 0);
1795 return result;
b60503ba
MW		 1796}
1797
a53295b6
MW		 1798static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1799{
1800 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1801 struct nvme_user_io io;
1802 struct nvme_command c;
d29ec824 1803 unsigned length, meta_len;
a67a9513 1804 int status, write;
a67a9513
KB		 1805 dma_addr_t meta_dma = 0;
1806 void *meta = NULL;
fec558b5 1807 void __user *metadata;
a53295b6
MW		 1808
1809 if (copy_from_user(&io, uio, sizeof(io)))
1810 return -EFAULT;
6c7d4945
MW		 1811
1812 switch (io.opcode) {
1813 case nvme_cmd_write:
1814 case nvme_cmd_read:
6bbf1acd 1815 case nvme_cmd_compare:
6413214c 1816 break;
6c7d4945 1817 default:
6bbf1acd 1818 return -EINVAL;
6c7d4945
MW		 1819 }
1820
d29ec824
CH		 1821 length = (io.nblocks + 1) << ns->lba_shift;
1822 meta_len = (io.nblocks + 1) * ns->ms;
835da3f9 1823 metadata = (void __user *)(uintptr_t)io.metadata;
d29ec824 1824 write = io.opcode & 1;
a53295b6 1825
71feb364
KB		 1826 if (ns->ext) {
1827 length += meta_len;
1828 meta_len = 0;
a67a9513
KB		 1829 }
1830 if (meta_len) {
d29ec824
CH		 1831 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1832 return -EINVAL;
1833
e75ec752 1834 meta = dma_alloc_coherent(dev->dev, meta_len,
a67a9513 1835 &meta_dma, GFP_KERNEL);
fec558b5 1836
a67a9513
KB		 1837 if (!meta) {
1838 status = -ENOMEM;
1839 goto unmap;
1840 }
1841 if (write) {
fec558b5 1842 if (copy_from_user(meta, metadata, meta_len)) {
a67a9513
KB		 1843 status = -EFAULT;
1844 goto unmap;
1845 }
1846 }
1847 }
1848
a53295b6
MW		 1849 memset(&c, 0, sizeof(c));
1850 c.rw.opcode = io.opcode;
1851 c.rw.flags = io.flags;
6c7d4945 1852 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1853 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1854 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1855 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1856 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1857 c.rw.reftag = cpu_to_le32(io.reftag);
1858 c.rw.apptag = cpu_to_le16(io.apptag);
1859 c.rw.appmask = cpu_to_le16(io.appmask);
a67a9513 1860 c.rw.metadata = cpu_to_le64(meta_dma);
d29ec824
CH		 1861
1862 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
835da3f9 1863 (void __user *)(uintptr_t)io.addr, length, NULL, 0);
f410c680 1864 unmap:
a67a9513
KB		 1865 if (meta) {
1866 if (status == NVME_SC_SUCCESS && !write) {
fec558b5 1867 if (copy_to_user(metadata, meta, meta_len))
a67a9513
KB		 1868 status = -EFAULT;
1869 }
e75ec752 1870 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
f410c680 1871 }
a53295b6
MW		 1872 return status;
1873}
1874
a4aea562
MB		 1875static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1876 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1877{
7963e521 1878 struct nvme_passthru_cmd cmd;
6ee44cdc 1879 struct nvme_command c;
d29ec824
CH		 1880 unsigned timeout = 0;
1881 int status;
6ee44cdc 1882
6bbf1acd
MW		 1883 if (!capable(CAP_SYS_ADMIN))
1884 return -EACCES;
1885 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1886 return -EFAULT;
6ee44cdc
MW		 1887
1888 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1889 c.common.opcode = cmd.opcode;
1890 c.common.flags = cmd.flags;
1891 c.common.nsid = cpu_to_le32(cmd.nsid);
1892 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1893 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1894 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1895 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1896 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1897 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1898 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1899 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1900
d29ec824
CH		 1901 if (cmd.timeout_ms)
1902 timeout = msecs_to_jiffies(cmd.timeout_ms);
eca18b23 1903
f705f837 1904 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
835da3f9 1905 NULL, (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
d29ec824
CH		 1906 &cmd.result, timeout);
1907 if (status >= 0) {
1908 if (put_user(cmd.result, &ucmd->result))
1909 return -EFAULT;
6bbf1acd 1910 }
f4f117f6 1911
6ee44cdc
MW		 1912 return status;
1913}
1914
81f03fed
JD		 1915static int nvme_subsys_reset(struct nvme_dev *dev)
1916{
1917 if (!dev->subsystem)
1918 return -ENOTTY;
1919
1920 writel(0x4E564D65, &dev->bar->nssr); /* "NVMe" */
1921 return 0;
1922}
1923
b60503ba
MW		 1924static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1925 unsigned long arg)
1926{
1927 struct nvme_ns *ns = bdev->bd_disk->private_data;
1928
1929 switch (cmd) {
6bbf1acd 1930 case NVME_IOCTL_ID:
c3bfe717 1931 force_successful_syscall_return();
6bbf1acd
MW		 1932 return ns->ns_id;
1933 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1934 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1935 case NVME_IOCTL_IO_CMD:
a4aea562 1936 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1937 case NVME_IOCTL_SUBMIT_IO:
1938 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1939 case SG_GET_VERSION_NUM:
1940 return nvme_sg_get_version_num((void __user *)arg);
1941 case SG_IO:
1942 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1943 default:
1944 return -ENOTTY;
1945 }
1946}
1947
320a3827
KB		 1948#ifdef CONFIG_COMPAT
1949static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1950 unsigned int cmd, unsigned long arg)
1951{
320a3827
KB		 1952 switch (cmd) {
1953 case SG_IO:
e179729a 1954 return -ENOIOCTLCMD;
320a3827
KB		 1955 }
1956 return nvme_ioctl(bdev, mode, cmd, arg);
1957}
1958#else
1959#define nvme_compat_ioctl NULL
1960#endif
1961
5105aa55 1962static void nvme_free_dev(struct kref *kref);
188c3568
KB		 1963static void nvme_free_ns(struct kref *kref)
1964{
1965 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
1966
ca064085
MB		 1967 if (ns->type == NVME_NS_LIGHTNVM)
1968 nvme_nvm_unregister(ns->queue, ns->disk->disk_name);
1969
188c3568
KB		 1970 spin_lock(&dev_list_lock);
1971 ns->disk->private_data = NULL;
1972 spin_unlock(&dev_list_lock);
1973
5105aa55 1974 kref_put(&ns->dev->kref, nvme_free_dev);
188c3568
KB		 1975 put_disk(ns->disk);
1976 kfree(ns);
1977}
1978
9ac27090
KB		 1979static int nvme_open(struct block_device *bdev, fmode_t mode)
1980{
9e60352c
KB		 1981 int ret = 0;
1982 struct nvme_ns *ns;
9ac27090 1983
9e60352c
KB		 1984 spin_lock(&dev_list_lock);
1985 ns = bdev->bd_disk->private_data;
1986 if (!ns)
1987 ret = -ENXIO;
188c3568 1988 else if (!kref_get_unless_zero(&ns->kref))
9e60352c
KB		 1989 ret = -ENXIO;
1990 spin_unlock(&dev_list_lock);
1991
1992 return ret;
9ac27090
KB		 1993}
1994
9ac27090
KB		 1995static void nvme_release(struct gendisk *disk, fmode_t mode)
1996{
1997 struct nvme_ns *ns = disk->private_data;
188c3568 1998 kref_put(&ns->kref, nvme_free_ns);
9ac27090
KB		 1999}
2000
4cc09e2d
KB		 2001static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
2002{
2003 /* some standard values */
2004 geo->heads = 1 << 6;
2005 geo->sectors = 1 << 5;
2006 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
2007 return 0;
2008}
2009
e1e5e564
KB		 2010static void nvme_config_discard(struct nvme_ns *ns)
2011{
2012 u32 logical_block_size = queue_logical_block_size(ns->queue);
2013 ns->queue->limits.discard_zeroes_data = 0;
2014 ns->queue->limits.discard_alignment = logical_block_size;
2015 ns->queue->limits.discard_granularity = logical_block_size;
2bb4cd5c 2016 blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
e1e5e564
KB		 2017 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
2018}
2019
1b9dbf7f
KB		 2020static int nvme_revalidate_disk(struct gendisk *disk)
2021{
2022 struct nvme_ns *ns = disk->private_data;
2023 struct nvme_dev *dev = ns->dev;
2024 struct nvme_id_ns *id;
a67a9513
KB		 2025 u8 lbaf, pi_type;
2026 u16 old_ms;
e1e5e564 2027 unsigned short bs;
1b9dbf7f 2028
d29ec824 2029 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
a5768aa8
KB		 2030 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
2031 dev->instance, ns->ns_id);
2032 return -ENODEV;
1b9dbf7f 2033 }
a5768aa8
KB		 2034 if (id->ncap == 0) {
2035 kfree(id);
2036 return -ENODEV;
e1e5e564 2037 }
1b9dbf7f 2038
ca064085
MB		 2039 if (nvme_nvm_ns_supported(ns, id) && ns->type != NVME_NS_LIGHTNVM) {
2040 if (nvme_nvm_register(ns->queue, disk->disk_name)) {
2041 dev_warn(dev->dev,
2042 "%s: LightNVM init failure\n", __func__);
2043 kfree(id);
2044 return -ENODEV;
2045 }
2046 ns->type = NVME_NS_LIGHTNVM;
2047 }
2048
e1e5e564
KB		 2049 old_ms = ns->ms;
2050 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1b9dbf7f 2051 ns->lba_shift = id->lbaf[lbaf].ds;
e1e5e564 2052 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
a67a9513 2053 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
e1e5e564
KB		 2054
2055 /*
2056 * If identify namespace failed, use default 512 byte block size so
2057 * block layer can use before failing read/write for 0 capacity.
2058 */
2059 if (ns->lba_shift == 0)
2060 ns->lba_shift = 9;
2061 bs = 1 << ns->lba_shift;
2062
2063 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2064 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2065 id->dps & NVME_NS_DPS_PI_MASK : 0;
2066
4cfc766e 2067 blk_mq_freeze_queue(disk->queue);
52b68d7e
KB		 2068 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2069 ns->ms != old_ms ||
e1e5e564 2070 bs != queue_logical_block_size(disk->queue) ||
a67a9513 2071 (ns->ms && ns->ext)))
e1e5e564
KB		 2072 blk_integrity_unregister(disk);
2073
2074 ns->pi_type = pi_type;
2075 blk_queue_logical_block_size(ns->queue, bs);
2076
25520d55 2077 if (ns->ms && !ns->ext)
e1e5e564
KB		 2078 nvme_init_integrity(ns);
2079
ca064085
MB		 2080 if ((ns->ms && !(ns->ms == 8 && ns->pi_type) &&
2081 !blk_get_integrity(disk)) ||
2082 ns->type == NVME_NS_LIGHTNVM)
e1e5e564
KB		 2083 set_capacity(disk, 0);
2084 else
2085 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2086
2087 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2088 nvme_config_discard(ns);
4cfc766e 2089 blk_mq_unfreeze_queue(disk->queue);
1b9dbf7f 2090
d29ec824 2091 kfree(id);
1b9dbf7f
KB		 2092 return 0;
2093}
2094
1d277a63
KB		 2095static char nvme_pr_type(enum pr_type type)
2096{
2097 switch (type) {
2098 case PR_WRITE_EXCLUSIVE:
2099 return 1;
2100 case PR_EXCLUSIVE_ACCESS:
2101 return 2;
2102 case PR_WRITE_EXCLUSIVE_REG_ONLY:
2103 return 3;
2104 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
2105 return 4;
2106 case PR_WRITE_EXCLUSIVE_ALL_REGS:
2107 return 5;
2108 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
2109 return 6;
2110 default:
2111 return 0;
2112 }
2113};
2114
2115static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
2116 u64 key, u64 sa_key, u8 op)
2117{
2118 struct nvme_ns *ns = bdev->bd_disk->private_data;
2119 struct nvme_command c;
2120 u8 data[16] = { 0, };
2121
2122 put_unaligned_le64(key, &data[0]);
2123 put_unaligned_le64(sa_key, &data[8]);
2124
2125 memset(&c, 0, sizeof(c));
2126 c.common.opcode = op;
a6dd1020
CH		 2127 c.common.nsid = cpu_to_le32(ns->ns_id);
2128 c.common.cdw10[0] = cpu_to_le32(cdw10);
1d277a63
KB		 2129
2130 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
2131}
2132
2133static int nvme_pr_register(struct block_device *bdev, u64 old,
2134 u64 new, unsigned flags)
2135{
2136 u32 cdw10;
2137
2138 if (flags & ~PR_FL_IGNORE_KEY)
2139 return -EOPNOTSUPP;
2140
2141 cdw10 = old ? 2 : 0;
2142 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
2143 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
2144 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
2145}
2146
2147static int nvme_pr_reserve(struct block_device *bdev, u64 key,
2148 enum pr_type type, unsigned flags)
2149{
2150 u32 cdw10;
2151
2152 if (flags & ~PR_FL_IGNORE_KEY)
2153 return -EOPNOTSUPP;
2154
2155 cdw10 = nvme_pr_type(type) << 8;
2156 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
2157 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
2158}
2159
2160static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
2161 enum pr_type type, bool abort)
2162{
2163 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
2164 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
2165}
2166
2167static int nvme_pr_clear(struct block_device *bdev, u64 key)
2168{
73fcf4e2 2169 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1d277a63
KB		 2170 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
2171}
2172
2173static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
2174{
2175 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
2176 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
2177}
2178
2179static const struct pr_ops nvme_pr_ops = {
2180 .pr_register = nvme_pr_register,
2181 .pr_reserve = nvme_pr_reserve,
2182 .pr_release = nvme_pr_release,
2183 .pr_preempt = nvme_pr_preempt,
2184 .pr_clear = nvme_pr_clear,
2185};
2186
b60503ba
MW		 2187static const struct block_device_operations nvme_fops = {
2188 .owner = THIS_MODULE,
2189 .ioctl = nvme_ioctl,
320a3827 2190 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 2191 .open = nvme_open,
2192 .release = nvme_release,
4cc09e2d 2193 .getgeo = nvme_getgeo,
1b9dbf7f 2194 .revalidate_disk= nvme_revalidate_disk,
1d277a63 2195 .pr_ops = &nvme_pr_ops,
b60503ba
MW		 2196};
2197
1fa6aead
MW		 2198static int nvme_kthread(void *data)
2199{
d4b4ff8e 2200 struct nvme_dev *dev, *next;
1fa6aead
MW		 2201
2202 while (!kthread_should_stop()) {
564a232c 2203 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 2204 spin_lock(&dev_list_lock);
d4b4ff8e 2205 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 2206 int i;
dfbac8c7
KB		 2207 u32 csts = readl(&dev->bar->csts);
2208
2209 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
2210 csts & NVME_CSTS_CFS) {
90667892
CH		 2211 if (!__nvme_reset(dev)) {
2212 dev_warn(dev->dev,
2213 "Failed status: %x, reset controller\n",
2214 readl(&dev->bar->csts));
2215 }
d4b4ff8e
KB		 2216 continue;
2217 }
1fa6aead 2218 for (i = 0; i < dev->queue_count; i++) {
a4aea562 2219 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 2220 if (!nvmeq)
2221 continue;
1fa6aead 2222 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 2223 nvme_process_cq(nvmeq);
6fccf938
KB		 2224
2225 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 2226 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 2227 break;
2228 dev->event_limit--;
2229 }
1fa6aead
MW		 2230 spin_unlock_irq(&nvmeq->q_lock);
2231 }
2232 }
2233 spin_unlock(&dev_list_lock);
acb7aa0d 2234 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 2235 }
2236 return 0;
2237}
2238
e1e5e564 2239static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
b60503ba
MW		 2240{
2241 struct nvme_ns *ns;
2242 struct gendisk *disk;
e75ec752 2243 int node = dev_to_node(dev->dev);
b60503ba 2244
a4aea562 2245 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba 2246 if (!ns)
e1e5e564
KB		 2247 return;
2248
a4aea562 2249 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 2250 if (IS_ERR(ns->queue))
b60503ba 2251 goto out_free_ns;
4eeb9215
MW		 2252 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2253 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 2254 ns->dev = dev;
2255 ns->queue->queuedata = ns;
2256
a4aea562 2257 disk = alloc_disk_node(0, node);
b60503ba
MW		 2258 if (!disk)
2259 goto out_free_queue;
a4aea562 2260
188c3568 2261 kref_init(&ns->kref);
5aff9382 2262 ns->ns_id = nsid;
b60503ba 2263 ns->disk = disk;
e1e5e564
KB		 2264 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2265 list_add_tail(&ns->list, &dev->namespaces);
2266
e9ef4636 2267 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
e824410f 2268 if (dev->max_hw_sectors) {
8fc23e03 2269 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
e824410f 2270 blk_queue_max_segments(ns->queue,
6824c5ef 2271 (dev->max_hw_sectors / (dev->page_size >> 9)) + 1);
e824410f 2272 }
a4aea562
MB		 2273 if (dev->stripe_size)
2274 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2275 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2276 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
03100aad 2277 blk_queue_virt_boundary(ns->queue, dev->page_size - 1);
b60503ba
MW		 2278
2279 disk->major = nvme_major;
469071a3 2280 disk->first_minor = 0;
b60503ba
MW		 2281 disk->fops = &nvme_fops;
2282 disk->private_data = ns;
2283 disk->queue = ns->queue;
b3fffdef 2284 disk->driverfs_dev = dev->device;
469071a3 2285 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2286 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba 2287
e1e5e564
KB		 2288 /*
2289 * Initialize capacity to 0 until we establish the namespace format and
2290 * setup integrity extentions if necessary. The revalidate_disk after
2291 * add_disk allows the driver to register with integrity if the format
2292 * requires it.
2293 */
2294 set_capacity(disk, 0);
a5768aa8
KB		 2295 if (nvme_revalidate_disk(ns->disk))
2296 goto out_free_disk;
2297
5105aa55 2298 kref_get(&dev->kref);
ca064085
MB		 2299 if (ns->type != NVME_NS_LIGHTNVM) {
2300 add_disk(ns->disk);
2301 if (ns->ms) {
2302 struct block_device *bd = bdget_disk(ns->disk, 0);
2303 if (!bd)
2304 return;
2305 if (blkdev_get(bd, FMODE_READ, NULL)) {
2306 bdput(bd);
2307 return;
2308 }
2309 blkdev_reread_part(bd);
2310 blkdev_put(bd, FMODE_READ);
7bee6074 2311 }
7bee6074 2312 }
e1e5e564 2313 return;
a5768aa8
KB		 2314 out_free_disk:
2315 kfree(disk);
2316 list_del(&ns->list);
b60503ba
MW		 2317 out_free_queue:
2318 blk_cleanup_queue(ns->queue);
2319 out_free_ns:
2320 kfree(ns);
b60503ba
MW		 2321}
2322
2659e57b
CH		 2323/*
2324 * Create I/O queues. Failing to create an I/O queue is not an issue,
2325 * we can continue with less than the desired amount of queues, and
2326 * even a controller without I/O queues an still be used to issue
2327 * admin commands. This might be useful to upgrade a buggy firmware
2328 * for example.
2329 */
42f61420
KB		 2330static void nvme_create_io_queues(struct nvme_dev *dev)
2331{
a4aea562 2332 unsigned i;
42f61420 2333
a4aea562 2334 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2335 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2336 break;
2337
a4aea562 2338 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2659e57b
CH		 2339 if (nvme_create_queue(dev->queues[i], i)) {
2340 nvme_free_queues(dev, i);
42f61420 2341 break;
2659e57b 2342 }
42f61420
KB		 2343}
2344
b3b06812 2345static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2346{
2347 int status;
2348 u32 result;
b3b06812 2349 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2350
df348139 2351 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2352 &result);
27e8166c
MW		 2353 if (status < 0)
2354 return status;
2355 if (status > 0) {
e75ec752 2356 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
badc34d4 2357 return 0;
27e8166c 2358 }
b60503ba
MW		 2359 return min(result & 0xffff, result >> 16) + 1;
2360}
2361
8ffaadf7
JD		 2362static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
2363{
2364 u64 szu, size, offset;
2365 u32 cmbloc;
2366 resource_size_t bar_size;
2367 struct pci_dev *pdev = to_pci_dev(dev->dev);
2368 void __iomem *cmb;
2369 dma_addr_t dma_addr;
2370
2371 if (!use_cmb_sqes)
2372 return NULL;
2373
2374 dev->cmbsz = readl(&dev->bar->cmbsz);
2375 if (!(NVME_CMB_SZ(dev->cmbsz)))
2376 return NULL;
2377
2378 cmbloc = readl(&dev->bar->cmbloc);
2379
2380 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
2381 size = szu * NVME_CMB_SZ(dev->cmbsz);
2382 offset = szu * NVME_CMB_OFST(cmbloc);
2383 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
2384
2385 if (offset > bar_size)
2386 return NULL;
2387
2388 /*
2389 * Controllers may support a CMB size larger than their BAR,
2390 * for example, due to being behind a bridge. Reduce the CMB to
2391 * the reported size of the BAR
2392 */
2393 if (size > bar_size - offset)
2394 size = bar_size - offset;
2395
2396 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
2397 cmb = ioremap_wc(dma_addr, size);
2398 if (!cmb)
2399 return NULL;
2400
2401 dev->cmb_dma_addr = dma_addr;
2402 dev->cmb_size = size;
2403 return cmb;
2404}
2405
2406static inline void nvme_release_cmb(struct nvme_dev *dev)
2407{
2408 if (dev->cmb) {
2409 iounmap(dev->cmb);
2410 dev->cmb = NULL;
2411 }
2412}
2413
9d713c2b
KB		 2414static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2415{
b80d5ccc 2416 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2417}
2418
8d85fce7 2419static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2420{
a4aea562 2421 struct nvme_queue *adminq = dev->queues[0];
e75ec752 2422 struct pci_dev *pdev = to_pci_dev(dev->dev);
42f61420 2423 int result, i, vecs, nr_io_queues, size;
b60503ba 2424
42f61420 2425 nr_io_queues = num_possible_cpus();
b348b7d5 2426 result = set_queue_count(dev, nr_io_queues);
badc34d4 2427 if (result <= 0)
1b23484b 2428 return result;
b348b7d5
MW		 2429 if (result < nr_io_queues)
2430 nr_io_queues = result;
b60503ba 2431
8ffaadf7
JD		 2432 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
2433 result = nvme_cmb_qdepth(dev, nr_io_queues,
2434 sizeof(struct nvme_command));
2435 if (result > 0)
2436 dev->q_depth = result;
2437 else
2438 nvme_release_cmb(dev);
2439 }
2440
9d713c2b
KB		 2441 size = db_bar_size(dev, nr_io_queues);
2442 if (size > 8192) {
f1938f6e 2443 iounmap(dev->bar);
9d713c2b
KB		 2444 do {
2445 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2446 if (dev->bar)
2447 break;
2448 if (!--nr_io_queues)
2449 return -ENOMEM;
2450 size = db_bar_size(dev, nr_io_queues);
2451 } while (1);
f1938f6e 2452 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2453 adminq->q_db = dev->dbs;
f1938f6e
MW		 2454 }
2455
9d713c2b 2456 /* Deregister the admin queue's interrupt */
3193f07b 2457 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2458
e32efbfc
JA		 2459 /*
2460 * If we enable msix early due to not intx, disable it again before
2461 * setting up the full range we need.
2462 */
2463 if (!pdev->irq)
2464 pci_disable_msix(pdev);
2465
be577fab 2466 for (i = 0; i < nr_io_queues; i++)
1b23484b 2467 dev->entry[i].entry = i;
be577fab
AG		 2468 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2469 if (vecs < 0) {
2470 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2471 if (vecs < 0) {
2472 vecs = 1;
2473 } else {
2474 for (i = 0; i < vecs; i++)
2475 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2476 }
2477 }
2478
063a8096
MW		 2479 /*
2480 * Should investigate if there's a performance win from allocating
2481 * more queues than interrupt vectors; it might allow the submission
2482 * path to scale better, even if the receive path is limited by the
2483 * number of interrupts.
2484 */
2485 nr_io_queues = vecs;
42f61420 2486 dev->max_qid = nr_io_queues;
063a8096 2487
3193f07b 2488 result = queue_request_irq(dev, adminq, adminq->irqname);
758dd7fd
JD		 2489 if (result) {
2490 adminq->cq_vector = -1;
22404274 2491 goto free_queues;
758dd7fd 2492 }
1b23484b 2493
cd638946 2494 /* Free previously allocated queues that are no longer usable */
42f61420 2495 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2496 nvme_create_io_queues(dev);
9ecdc946 2497
22404274 2498 return 0;
b60503ba 2499
22404274 2500 free_queues:
a1a5ef99 2501 nvme_free_queues(dev, 1);
22404274 2502 return result;
b60503ba
MW		 2503}
2504
a5768aa8
KB		 2505static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2506{
2507 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2508 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2509
2510 return nsa->ns_id - nsb->ns_id;
2511}
2512
2513static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2514{
2515 struct nvme_ns *ns;
2516
2517 list_for_each_entry(ns, &dev->namespaces, list) {
2518 if (ns->ns_id == nsid)
2519 return ns;
2520 if (ns->ns_id > nsid)
2521 break;
2522 }
2523 return NULL;
2524}
2525
2526static inline bool nvme_io_incapable(struct nvme_dev *dev)
2527{
2528 return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
2529 dev->online_queues < 2);
2530}
2531
2532static void nvme_ns_remove(struct nvme_ns *ns)
2533{
2534 bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2535
2536 if (kill)
2537 blk_set_queue_dying(ns->queue);
9609b994 2538 if (ns->disk->flags & GENHD_FL_UP)
a5768aa8 2539 del_gendisk(ns->disk);
a5768aa8
KB		 2540 if (kill || !blk_queue_dying(ns->queue)) {
2541 blk_mq_abort_requeue_list(ns->queue);
2542 blk_cleanup_queue(ns->queue);
5105aa55
KB		 2543 }
2544 list_del_init(&ns->list);
2545 kref_put(&ns->kref, nvme_free_ns);
a5768aa8
KB		 2546}
2547
2548static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2549{
2550 struct nvme_ns *ns, *next;
2551 unsigned i;
2552
2553 for (i = 1; i <= nn; i++) {
2554 ns = nvme_find_ns(dev, i);
2555 if (ns) {
5105aa55 2556 if (revalidate_disk(ns->disk))
a5768aa8 2557 nvme_ns_remove(ns);
a5768aa8
KB		 2558 } else
2559 nvme_alloc_ns(dev, i);
2560 }
2561 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
5105aa55 2562 if (ns->ns_id > nn)
a5768aa8 2563 nvme_ns_remove(ns);
a5768aa8
KB		 2564 }
2565 list_sort(NULL, &dev->namespaces, ns_cmp);
2566}
2567
bda4e0fb
KB		 2568static void nvme_set_irq_hints(struct nvme_dev *dev)
2569{
2570 struct nvme_queue *nvmeq;
2571 int i;
2572
2573 for (i = 0; i < dev->online_queues; i++) {
2574 nvmeq = dev->queues[i];
2575
2576 if (!nvmeq->tags || !(*nvmeq->tags))
2577 continue;
2578
2579 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2580 blk_mq_tags_cpumask(*nvmeq->tags));
2581 }
2582}
2583
a5768aa8
KB		 2584static void nvme_dev_scan(struct work_struct *work)
2585{
2586 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2587 struct nvme_id_ctrl *ctrl;
2588
2589 if (!dev->tagset.tags)
2590 return;
2591 if (nvme_identify_ctrl(dev, &ctrl))
2592 return;
2593 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2594 kfree(ctrl);
bda4e0fb 2595 nvme_set_irq_hints(dev);
a5768aa8
KB		 2596}
2597
422ef0c7
MW		 2598/*
2599 * Return: error value if an error occurred setting up the queues or calling
2600 * Identify Device. 0 if these succeeded, even if adding some of the
2601 * namespaces failed. At the moment, these failures are silent. TBD which
2602 * failures should be reported.
2603 */
8d85fce7 2604static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2605{
e75ec752 2606 struct pci_dev *pdev = to_pci_dev(dev->dev);
c3bfe717 2607 int res;
51814232 2608 struct nvme_id_ctrl *ctrl;
a310acd7 2609 int shift = NVME_CAP_MPSMIN(lo_hi_readq(&dev->bar->cap)) + 12;
b60503ba 2610
d29ec824 2611 res = nvme_identify_ctrl(dev, &ctrl);
b60503ba 2612 if (res) {
e75ec752 2613 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
e1e5e564 2614 return -EIO;
b60503ba
MW		 2615 }
2616
0e5e4f0e 2617 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2618 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2619 dev->vwc = ctrl->vwc;
51814232
MW		 2620 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2621 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2622 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2623 if (ctrl->mdts)
8fc23e03 2624 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
b12363d0
S		 2625 else
2626 dev->max_hw_sectors = UINT_MAX;
68608c26 2627 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2628 (pdev->device == 0x0953) && ctrl->vs[3]) {
2629 unsigned int max_hw_sectors;
2630
159b67d7 2631 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2632 max_hw_sectors = dev->stripe_size >> (shift - 9);
2633 if (dev->max_hw_sectors) {
2634 dev->max_hw_sectors = min(max_hw_sectors,
2635 dev->max_hw_sectors);
2636 } else
2637 dev->max_hw_sectors = max_hw_sectors;
2638 }
d29ec824 2639 kfree(ctrl);
a4aea562 2640
ffe7704d
KB		 2641 if (!dev->tagset.tags) {
2642 dev->tagset.ops = &nvme_mq_ops;
2643 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2644 dev->tagset.timeout = NVME_IO_TIMEOUT;
2645 dev->tagset.numa_node = dev_to_node(dev->dev);
2646 dev->tagset.queue_depth =
a4aea562 2647 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ffe7704d
KB		 2648 dev->tagset.cmd_size = nvme_cmd_size(dev);
2649 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2650 dev->tagset.driver_data = dev;
b60503ba 2651
ffe7704d
KB		 2652 if (blk_mq_alloc_tag_set(&dev->tagset))
2653 return 0;
2654 }
a5768aa8 2655 schedule_work(&dev->scan_work);
e1e5e564 2656 return 0;
b60503ba
MW		 2657}
2658
0877cb0d
KB		 2659static int nvme_dev_map(struct nvme_dev *dev)
2660{
42f61420 2661 u64 cap;
0877cb0d 2662 int bars, result = -ENOMEM;
e75ec752 2663 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2664
2665 if (pci_enable_device_mem(pdev))
2666 return result;
2667
2668 dev->entry[0].vector = pdev->irq;
2669 pci_set_master(pdev);
2670 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2671 if (!bars)
2672 goto disable_pci;
2673
0877cb0d
KB		 2674 if (pci_request_selected_regions(pdev, bars, "nvme"))
2675 goto disable_pci;
2676
e75ec752
CH		 2677 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2678 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2679 goto disable;
0877cb0d 2680
0877cb0d
KB		 2681 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2682 if (!dev->bar)
2683 goto disable;
e32efbfc 2684
0e53d180
KB		 2685 if (readl(&dev->bar->csts) == -1) {
2686 result = -ENODEV;
2687 goto unmap;
2688 }
e32efbfc
JA		 2689
2690 /*
2691 * Some devices don't advertse INTx interrupts, pre-enable a single
2692 * MSIX vec for setup. We'll adjust this later.
2693 */
2694 if (!pdev->irq) {
2695 result = pci_enable_msix(pdev, dev->entry, 1);
2696 if (result < 0)
2697 goto unmap;
2698 }
2699
a310acd7 2700 cap = lo_hi_readq(&dev->bar->cap);
42f61420
KB		 2701 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2702 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d 2703 dev->dbs = ((void __iomem *)dev->bar) + 4096;
8ffaadf7
JD		 2704 if (readl(&dev->bar->vs) >= NVME_VS(1, 2))
2705 dev->cmb = nvme_map_cmb(dev);
0877cb0d
KB		 2706
2707 return 0;
2708
0e53d180
KB		 2709 unmap:
2710 iounmap(dev->bar);
2711 dev->bar = NULL;
0877cb0d
KB		 2712 disable:
2713 pci_release_regions(pdev);
2714 disable_pci:
2715 pci_disable_device(pdev);
2716 return result;
2717}
2718
2719static void nvme_dev_unmap(struct nvme_dev *dev)
2720{
e75ec752
CH		 2721 struct pci_dev *pdev = to_pci_dev(dev->dev);
2722
2723 if (pdev->msi_enabled)
2724 pci_disable_msi(pdev);
2725 else if (pdev->msix_enabled)
2726 pci_disable_msix(pdev);
0877cb0d
KB		 2727
2728 if (dev->bar) {
2729 iounmap(dev->bar);
2730 dev->bar = NULL;
e75ec752 2731 pci_release_regions(pdev);
0877cb0d
KB		 2732 }
2733
e75ec752
CH		 2734 if (pci_is_enabled(pdev))
2735 pci_disable_device(pdev);
0877cb0d
KB		 2736}
2737
4d115420
KB		 2738struct nvme_delq_ctx {
2739 struct task_struct *waiter;
2740 struct kthread_worker *worker;
2741 atomic_t refcount;
2742};
2743
2744static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2745{
2746 dq->waiter = current;
2747 mb();
2748
2749 for (;;) {
2750 set_current_state(TASK_KILLABLE);
2751 if (!atomic_read(&dq->refcount))
2752 break;
2753 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2754 fatal_signal_pending(current)) {
0fb59cbc
KB		 2755 /*
2756 * Disable the controller first since we can't trust it
2757 * at this point, but leave the admin queue enabled
2758 * until all queue deletion requests are flushed.
2759 * FIXME: This may take a while if there are more h/w
2760 * queues than admin tags.
2761 */
4d115420 2762 set_current_state(TASK_RUNNING);
a310acd7 2763 nvme_disable_ctrl(dev, lo_hi_readq(&dev->bar->cap));
0fb59cbc 2764 nvme_clear_queue(dev->queues[0]);
4d115420 2765 flush_kthread_worker(dq->worker);
0fb59cbc 2766 nvme_disable_queue(dev, 0);
4d115420
KB		 2767 return;
2768 }
2769 }
2770 set_current_state(TASK_RUNNING);
2771}
2772
2773static void nvme_put_dq(struct nvme_delq_ctx *dq)
2774{
2775 atomic_dec(&dq->refcount);
2776 if (dq->waiter)
2777 wake_up_process(dq->waiter);
2778}
2779
2780static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2781{
2782 atomic_inc(&dq->refcount);
2783 return dq;
2784}
2785
2786static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2787{
2788 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
4d115420
KB		 2789 nvme_put_dq(dq);
2790}
2791
2792static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2793 kthread_work_func_t fn)
2794{
2795 struct nvme_command c;
2796
2797 memset(&c, 0, sizeof(c));
2798 c.delete_queue.opcode = opcode;
2799 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2800
2801 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2802 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2803 ADMIN_TIMEOUT);
4d115420
KB		 2804}
2805
2806static void nvme_del_cq_work_handler(struct kthread_work *work)
2807{
2808 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2809 cmdinfo.work);
2810 nvme_del_queue_end(nvmeq);
2811}
2812
2813static int nvme_delete_cq(struct nvme_queue *nvmeq)
2814{
2815 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2816 nvme_del_cq_work_handler);
2817}
2818
2819static void nvme_del_sq_work_handler(struct kthread_work *work)
2820{
2821 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2822 cmdinfo.work);
2823 int status = nvmeq->cmdinfo.status;
2824
2825 if (!status)
2826 status = nvme_delete_cq(nvmeq);
2827 if (status)
2828 nvme_del_queue_end(nvmeq);
2829}
2830
2831static int nvme_delete_sq(struct nvme_queue *nvmeq)
2832{
2833 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2834 nvme_del_sq_work_handler);
2835}
2836
2837static void nvme_del_queue_start(struct kthread_work *work)
2838{
2839 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2840 cmdinfo.work);
4d115420
KB		 2841 if (nvme_delete_sq(nvmeq))
2842 nvme_del_queue_end(nvmeq);
2843}
2844
2845static void nvme_disable_io_queues(struct nvme_dev *dev)
2846{
2847 int i;
2848 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2849 struct nvme_delq_ctx dq;
2850 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2851 &worker, "nvme%d", dev->instance);
2852
2853 if (IS_ERR(kworker_task)) {
e75ec752 2854 dev_err(dev->dev,
4d115420
KB		 2855 "Failed to create queue del task\n");
2856 for (i = dev->queue_count - 1; i > 0; i--)
2857 nvme_disable_queue(dev, i);
2858 return;
2859 }
2860
2861 dq.waiter = NULL;
2862 atomic_set(&dq.refcount, 0);
2863 dq.worker = &worker;
2864 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2865 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2866
2867 if (nvme_suspend_queue(nvmeq))
2868 continue;
2869 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2870 nvmeq->cmdinfo.worker = dq.worker;
2871 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2872 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2873 }
2874 nvme_wait_dq(&dq, dev);
2875 kthread_stop(kworker_task);
2876}
2877
b9afca3e
DM		 2878/*
2879* Remove the node from the device list and check
2880* for whether or not we need to stop the nvme_thread.
2881*/
2882static void nvme_dev_list_remove(struct nvme_dev *dev)
2883{
2884 struct task_struct *tmp = NULL;
2885
2886 spin_lock(&dev_list_lock);
2887 list_del_init(&dev->node);
2888 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2889 tmp = nvme_thread;
2890 nvme_thread = NULL;
2891 }
2892 spin_unlock(&dev_list_lock);
2893
2894 if (tmp)
2895 kthread_stop(tmp);
2896}
2897
c9d3bf88
KB		 2898static void nvme_freeze_queues(struct nvme_dev *dev)
2899{
2900 struct nvme_ns *ns;
2901
2902 list_for_each_entry(ns, &dev->namespaces, list) {
2903 blk_mq_freeze_queue_start(ns->queue);
2904
cddcd72b 2905 spin_lock_irq(ns->queue->queue_lock);
c9d3bf88 2906 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
cddcd72b 2907 spin_unlock_irq(ns->queue->queue_lock);
c9d3bf88
KB		 2908
2909 blk_mq_cancel_requeue_work(ns->queue);
2910 blk_mq_stop_hw_queues(ns->queue);
2911 }
2912}
2913
2914static void nvme_unfreeze_queues(struct nvme_dev *dev)
2915{
2916 struct nvme_ns *ns;
2917
2918 list_for_each_entry(ns, &dev->namespaces, list) {
2919 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2920 blk_mq_unfreeze_queue(ns->queue);
2921 blk_mq_start_stopped_hw_queues(ns->queue, true);
2922 blk_mq_kick_requeue_list(ns->queue);
2923 }
2924}
2925
f0b50732 2926static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2927{
22404274 2928 int i;
7c1b2450 2929 u32 csts = -1;
22404274 2930
b9afca3e 2931 nvme_dev_list_remove(dev);
1fa6aead 2932
c9d3bf88
KB		 2933 if (dev->bar) {
2934 nvme_freeze_queues(dev);
7c1b2450 2935 csts = readl(&dev->bar->csts);
c9d3bf88 2936 }
7c1b2450 2937 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2938 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2939 struct nvme_queue *nvmeq = dev->queues[i];
4d115420 2940 nvme_suspend_queue(nvmeq);
4d115420
KB		 2941 }
2942 } else {
2943 nvme_disable_io_queues(dev);
1894d8f1 2944 nvme_shutdown_ctrl(dev);
4d115420
KB		 2945 nvme_disable_queue(dev, 0);
2946 }
f0b50732 2947 nvme_dev_unmap(dev);
07836e65
KB		 2948
2949 for (i = dev->queue_count - 1; i >= 0; i--)
2950 nvme_clear_queue(dev->queues[i]);
f0b50732
KB		 2951}
2952
2953static void nvme_dev_remove(struct nvme_dev *dev)
2954{
5105aa55 2955 struct nvme_ns *ns, *next;
f0b50732 2956
5105aa55 2957 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
a5768aa8 2958 nvme_ns_remove(ns);
b60503ba
MW		 2959}
2960
091b6092
MW		 2961static int nvme_setup_prp_pools(struct nvme_dev *dev)
2962{
e75ec752 2963 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2964 PAGE_SIZE, PAGE_SIZE, 0);
2965 if (!dev->prp_page_pool)
2966 return -ENOMEM;
2967
99802a7a 2968 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2969 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2970 256, 256, 0);
2971 if (!dev->prp_small_pool) {
2972 dma_pool_destroy(dev->prp_page_pool);
2973 return -ENOMEM;
2974 }
091b6092
MW		 2975 return 0;
2976}
2977
2978static void nvme_release_prp_pools(struct nvme_dev *dev)
2979{
2980 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2981 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2982}
2983
cd58ad7d
QSA		 2984static DEFINE_IDA(nvme_instance_ida);
2985
2986static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2987{
cd58ad7d
QSA		 2988 int instance, error;
2989
2990 do {
2991 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2992 return -ENODEV;
2993
2994 spin_lock(&dev_list_lock);
2995 error = ida_get_new(&nvme_instance_ida, &instance);
2996 spin_unlock(&dev_list_lock);
2997 } while (error == -EAGAIN);
2998
2999 if (error)
3000 return -ENODEV;
3001
3002 dev->instance = instance;
3003 return 0;
b60503ba
MW		 3004}
3005
3006static void nvme_release_instance(struct nvme_dev *dev)
3007{
cd58ad7d
QSA		 3008 spin_lock(&dev_list_lock);
3009 ida_remove(&nvme_instance_ida, dev->instance);
3010 spin_unlock(&dev_list_lock);
b60503ba
MW		 3011}
3012
5e82e952
KB		 3013static void nvme_free_dev(struct kref *kref)
3014{
3015 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 3016
e75ec752 3017 put_device(dev->dev);
b3fffdef 3018 put_device(dev->device);
285dffc9 3019 nvme_release_instance(dev);
4af0e21c
KB		 3020 if (dev->tagset.tags)
3021 blk_mq_free_tag_set(&dev->tagset);
3022 if (dev->admin_q)
3023 blk_put_queue(dev->admin_q);
5e82e952
KB		 3024 kfree(dev->queues);
3025 kfree(dev->entry);
3026 kfree(dev);
3027}
3028
3029static int nvme_dev_open(struct inode *inode, struct file *f)
3030{
b3fffdef
KB		 3031 struct nvme_dev *dev;
3032 int instance = iminor(inode);
3033 int ret = -ENODEV;
3034
3035 spin_lock(&dev_list_lock);
3036 list_for_each_entry(dev, &dev_list, node) {
3037 if (dev->instance == instance) {
2e1d8448
KB		 3038 if (!dev->admin_q) {
3039 ret = -EWOULDBLOCK;
3040 break;
3041 }
b3fffdef
KB		 3042 if (!kref_get_unless_zero(&dev->kref))
3043 break;
3044 f->private_data = dev;
3045 ret = 0;
3046 break;
3047 }
3048 }
3049 spin_unlock(&dev_list_lock);
3050
3051 return ret;
5e82e952
KB		 3052}
3053
3054static int nvme_dev_release(struct inode *inode, struct file *f)
3055{
3056 struct nvme_dev *dev = f->private_data;
3057 kref_put(&dev->kref, nvme_free_dev);
3058 return 0;
3059}
3060
3061static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
3062{
3063 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 3064 struct nvme_ns *ns;
3065
5e82e952
KB		 3066 switch (cmd) {
3067 case NVME_IOCTL_ADMIN_CMD:
a4aea562 3068 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 3069 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 3070 if (list_empty(&dev->namespaces))
3071 return -ENOTTY;
3072 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
3073 return nvme_user_cmd(dev, ns, (void __user *)arg);
4cc06521
KB		 3074 case NVME_IOCTL_RESET:
3075 dev_warn(dev->dev, "resetting controller\n");
3076 return nvme_reset(dev);
81f03fed
JD		 3077 case NVME_IOCTL_SUBSYS_RESET:
3078 return nvme_subsys_reset(dev);
5e82e952
KB		 3079 default:
3080 return -ENOTTY;
3081 }
3082}
3083
3084static const struct file_operations nvme_dev_fops = {
3085 .owner = THIS_MODULE,
3086 .open = nvme_dev_open,
3087 .release = nvme_dev_release,
3088 .unlocked_ioctl = nvme_dev_ioctl,
3089 .compat_ioctl = nvme_dev_ioctl,
3090};
3091
3cf519b5 3092static void nvme_probe_work(struct work_struct *work)
f0b50732 3093{
3cf519b5 3094 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
b9afca3e 3095 bool start_thread = false;
3cf519b5 3096 int result;
f0b50732
KB		 3097
3098 result = nvme_dev_map(dev);
3099 if (result)
3cf519b5 3100 goto out;
f0b50732
KB		 3101
3102 result = nvme_configure_admin_queue(dev);
3103 if (result)
3104 goto unmap;
3105
3106 spin_lock(&dev_list_lock);
b9afca3e
DM		 3107 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
3108 start_thread = true;
3109 nvme_thread = NULL;
3110 }
f0b50732
KB		 3111 list_add(&dev->node, &dev_list);
3112 spin_unlock(&dev_list_lock);
3113
b9afca3e
DM		 3114 if (start_thread) {
3115 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 3116 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 3117 } else
3118 wait_event_killable(nvme_kthread_wait, nvme_thread);
3119
3120 if (IS_ERR_OR_NULL(nvme_thread)) {
3121 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
3122 goto disable;
3123 }
a4aea562
MB		 3124
3125 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 3126 result = nvme_alloc_admin_tags(dev);
3127 if (result)
3128 goto disable;
b9afca3e 3129
f0b50732 3130 result = nvme_setup_io_queues(dev);
badc34d4 3131 if (result)
0fb59cbc 3132 goto free_tags;
f0b50732 3133
1efccc9d 3134 dev->event_limit = 1;
3cf519b5 3135
2659e57b
CH		 3136 /*
3137 * Keep the controller around but remove all namespaces if we don't have
3138 * any working I/O queue.
3139 */
3cf519b5
CH		 3140 if (dev->online_queues < 2) {
3141 dev_warn(dev->dev, "IO queues not created\n");
3cf519b5
CH		 3142 nvme_dev_remove(dev);
3143 } else {
3144 nvme_unfreeze_queues(dev);
3145 nvme_dev_add(dev);
3146 }
3147
3148 return;
f0b50732 3149
0fb59cbc
KB		 3150 free_tags:
3151 nvme_dev_remove_admin(dev);
4af0e21c
KB		 3152 blk_put_queue(dev->admin_q);
3153 dev->admin_q = NULL;
3154 dev->queues[0]->tags = NULL;
f0b50732 3155 disable:
a1a5ef99 3156 nvme_disable_queue(dev, 0);
b9afca3e 3157 nvme_dev_list_remove(dev);
f0b50732
KB		 3158 unmap:
3159 nvme_dev_unmap(dev);
3cf519b5
CH		 3160 out:
3161 if (!work_busy(&dev->reset_work))
3162 nvme_dead_ctrl(dev);
f0b50732
KB		 3163}
3164
9a6b9458
KB		 3165static int nvme_remove_dead_ctrl(void *arg)
3166{
3167 struct nvme_dev *dev = (struct nvme_dev *)arg;
e75ec752 3168 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 3169
3170 if (pci_get_drvdata(pdev))
c81f4975 3171 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 3172 kref_put(&dev->kref, nvme_free_dev);
3173 return 0;
3174}
3175
de3eff2b
KB		 3176static void nvme_dead_ctrl(struct nvme_dev *dev)
3177{
3178 dev_warn(dev->dev, "Device failed to resume\n");
3179 kref_get(&dev->kref);
3180 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
3181 dev->instance))) {
3182 dev_err(dev->dev,
3183 "Failed to start controller remove task\n");
3184 kref_put(&dev->kref, nvme_free_dev);
3185 }
3186}
3187
77b50d9e 3188static void nvme_reset_work(struct work_struct *ws)
9a6b9458 3189{
77b50d9e 3190 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
ffe7704d
KB		 3191 bool in_probe = work_busy(&dev->probe_work);
3192
9a6b9458 3193 nvme_dev_shutdown(dev);
ffe7704d
KB		 3194
3195 /* Synchronize with device probe so that work will see failure status
3196 * and exit gracefully without trying to schedule another reset */
3197 flush_work(&dev->probe_work);
3198
3199 /* Fail this device if reset occured during probe to avoid
3200 * infinite initialization loops. */
3201 if (in_probe) {
de3eff2b 3202 nvme_dead_ctrl(dev);
ffe7704d 3203 return;
9a6b9458 3204 }
ffe7704d
KB		 3205 /* Schedule device resume asynchronously so the reset work is available
3206 * to cleanup errors that may occur during reinitialization */
3207 schedule_work(&dev->probe_work);
9a6b9458
KB		 3208}
3209
90667892 3210static int __nvme_reset(struct nvme_dev *dev)
9ca97374 3211{
90667892
CH		 3212 if (work_pending(&dev->reset_work))
3213 return -EBUSY;
3214 list_del_init(&dev->node);
3215 queue_work(nvme_workq, &dev->reset_work);
3216 return 0;
9ca97374
TH		 3217}
3218
4cc06521
KB		 3219static int nvme_reset(struct nvme_dev *dev)
3220{
90667892 3221 int ret;
4cc06521
KB		 3222
3223 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
3224 return -ENODEV;
3225
3226 spin_lock(&dev_list_lock);
90667892 3227 ret = __nvme_reset(dev);
4cc06521
KB		 3228 spin_unlock(&dev_list_lock);
3229
3230 if (!ret) {
3231 flush_work(&dev->reset_work);
ffe7704d 3232 flush_work(&dev->probe_work);
4cc06521
KB		 3233 return 0;
3234 }
3235
3236 return ret;
3237}
3238
3239static ssize_t nvme_sysfs_reset(struct device *dev,
3240 struct device_attribute *attr, const char *buf,
3241 size_t count)
3242{
3243 struct nvme_dev *ndev = dev_get_drvdata(dev);
3244 int ret;
3245
3246 ret = nvme_reset(ndev);
3247 if (ret < 0)
3248 return ret;
3249
3250 return count;
3251}
3252static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3253
8d85fce7 3254static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 3255{
a4aea562 3256 int node, result = -ENOMEM;
b60503ba
MW		 3257 struct nvme_dev *dev;
3258
a4aea562
MB		 3259 node = dev_to_node(&pdev->dev);
3260 if (node == NUMA_NO_NODE)
3261 set_dev_node(&pdev->dev, 0);
3262
3263 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3264 if (!dev)
3265 return -ENOMEM;
a4aea562
MB		 3266 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3267 GFP_KERNEL, node);
b60503ba
MW		 3268 if (!dev->entry)
3269 goto free;
a4aea562
MB		 3270 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3271 GFP_KERNEL, node);
b60503ba
MW		 3272 if (!dev->queues)
3273 goto free;
3274
3275 INIT_LIST_HEAD(&dev->namespaces);
77b50d9e 3276 INIT_WORK(&dev->reset_work, nvme_reset_work);
e75ec752 3277 dev->dev = get_device(&pdev->dev);
9a6b9458 3278 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 3279 result = nvme_set_instance(dev);
3280 if (result)
a96d4f5c 3281 goto put_pci;
b60503ba 3282
091b6092
MW		 3283 result = nvme_setup_prp_pools(dev);
3284 if (result)
0877cb0d 3285 goto release;
091b6092 3286
fb35e914 3287 kref_init(&dev->kref);
b3fffdef
KB		 3288 dev->device = device_create(nvme_class, &pdev->dev,
3289 MKDEV(nvme_char_major, dev->instance),
3290 dev, "nvme%d", dev->instance);
3291 if (IS_ERR(dev->device)) {
3292 result = PTR_ERR(dev->device);
2e1d8448 3293 goto release_pools;
b3fffdef
KB		 3294 }
3295 get_device(dev->device);
4cc06521
KB		 3296 dev_set_drvdata(dev->device, dev);
3297
3298 result = device_create_file(dev->device, &dev_attr_reset_controller);
3299 if (result)
3300 goto put_dev;
740216fc 3301
e6e96d73 3302 INIT_LIST_HEAD(&dev->node);
a5768aa8 3303 INIT_WORK(&dev->scan_work, nvme_dev_scan);
3cf519b5 3304 INIT_WORK(&dev->probe_work, nvme_probe_work);
2e1d8448 3305 schedule_work(&dev->probe_work);
b60503ba
MW		 3306 return 0;
3307
4cc06521
KB		 3308 put_dev:
3309 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3310 put_device(dev->device);
0877cb0d 3311 release_pools:
091b6092 3312 nvme_release_prp_pools(dev);
0877cb0d
KB		 3313 release:
3314 nvme_release_instance(dev);
a96d4f5c 3315 put_pci:
e75ec752 3316 put_device(dev->dev);
b60503ba
MW		 3317 free:
3318 kfree(dev->queues);
3319 kfree(dev->entry);
3320 kfree(dev);
3321 return result;
3322}
3323
f0d54a54
KB		 3324static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3325{
a6739479 3326 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 3327
a6739479
KB		 3328 if (prepare)
3329 nvme_dev_shutdown(dev);
3330 else
0a7385ad 3331 schedule_work(&dev->probe_work);
f0d54a54
KB		 3332}
3333
09ece142
KB		 3334static void nvme_shutdown(struct pci_dev *pdev)
3335{
3336 struct nvme_dev *dev = pci_get_drvdata(pdev);
3337 nvme_dev_shutdown(dev);
3338}
3339
8d85fce7 3340static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3341{
3342 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 3343
3344 spin_lock(&dev_list_lock);
3345 list_del_init(&dev->node);
3346 spin_unlock(&dev_list_lock);
3347
3348 pci_set_drvdata(pdev, NULL);
2e1d8448 3349 flush_work(&dev->probe_work);
9a6b9458 3350 flush_work(&dev->reset_work);
a5768aa8 3351 flush_work(&dev->scan_work);
4cc06521 3352 device_remove_file(dev->device, &dev_attr_reset_controller);
c9d3bf88 3353 nvme_dev_remove(dev);
3399a3f7 3354 nvme_dev_shutdown(dev);
a4aea562 3355 nvme_dev_remove_admin(dev);
b3fffdef 3356 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
a1a5ef99 3357 nvme_free_queues(dev, 0);
8ffaadf7 3358 nvme_release_cmb(dev);
9a6b9458 3359 nvme_release_prp_pools(dev);
5e82e952 3360 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 3361}
3362
3363/* These functions are yet to be implemented */
3364#define nvme_error_detected NULL
3365#define nvme_dump_registers NULL
3366#define nvme_link_reset NULL
3367#define nvme_slot_reset NULL
3368#define nvme_error_resume NULL
cd638946 3369
671a6018 3370#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3371static int nvme_suspend(struct device *dev)
3372{
3373 struct pci_dev *pdev = to_pci_dev(dev);
3374 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3375
3376 nvme_dev_shutdown(ndev);
3377 return 0;
3378}
3379
3380static int nvme_resume(struct device *dev)
3381{
3382 struct pci_dev *pdev = to_pci_dev(dev);
3383 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3384
0a7385ad 3385 schedule_work(&ndev->probe_work);
9a6b9458 3386 return 0;
cd638946 3387}
671a6018 3388#endif
cd638946
KB		 3389
3390static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 3391
1d352035 3392static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 3393 .error_detected = nvme_error_detected,
3394 .mmio_enabled = nvme_dump_registers,
3395 .link_reset = nvme_link_reset,
3396 .slot_reset = nvme_slot_reset,
3397 .resume = nvme_error_resume,
f0d54a54 3398 .reset_notify = nvme_reset_notify,
b60503ba
MW		 3399};
3400
3401/* Move to pci_ids.h later */
3402#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3403
6eb0d698 3404static const struct pci_device_id nvme_id_table[] = {
b60503ba 3405 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 3406 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
b60503ba
MW		 3407 { 0, }
3408};
3409MODULE_DEVICE_TABLE(pci, nvme_id_table);
3410
3411static struct pci_driver nvme_driver = {
3412 .name = "nvme",
3413 .id_table = nvme_id_table,
3414 .probe = nvme_probe,
8d85fce7 3415 .remove = nvme_remove,
09ece142 3416 .shutdown = nvme_shutdown,
cd638946
KB		 3417 .driver = {
3418 .pm = &nvme_dev_pm_ops,
3419 },
b60503ba
MW		 3420 .err_handler = &nvme_err_handler,
3421};
3422
3423static int __init nvme_init(void)
3424{
0ac13140 3425 int result;
1fa6aead 3426
b9afca3e 3427 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3428
9a6b9458
KB		 3429 nvme_workq = create_singlethread_workqueue("nvme");
3430 if (!nvme_workq)
b9afca3e 3431 return -ENOMEM;
9a6b9458 3432
5c42ea16
KB		 3433 result = register_blkdev(nvme_major, "nvme");
3434 if (result < 0)
9a6b9458 3435 goto kill_workq;
5c42ea16 3436 else if (result > 0)
0ac13140 3437 nvme_major = result;
b60503ba 3438
b3fffdef
KB		 3439 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3440 &nvme_dev_fops);
3441 if (result < 0)
3442 goto unregister_blkdev;
3443 else if (result > 0)
3444 nvme_char_major = result;
3445
3446 nvme_class = class_create(THIS_MODULE, "nvme");
c727040b
AK		 3447 if (IS_ERR(nvme_class)) {
3448 result = PTR_ERR(nvme_class);
b3fffdef 3449 goto unregister_chrdev;
c727040b 3450 }
b3fffdef 3451
f3db22fe
KB		 3452 result = pci_register_driver(&nvme_driver);
3453 if (result)
b3fffdef 3454 goto destroy_class;
1fa6aead 3455 return 0;
b60503ba 3456
b3fffdef
KB		 3457 destroy_class:
3458 class_destroy(nvme_class);
3459 unregister_chrdev:
3460 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1fa6aead 3461 unregister_blkdev:
b60503ba 3462 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3463 kill_workq:
3464 destroy_workqueue(nvme_workq);
b60503ba
MW		 3465 return result;
3466}
3467
3468static void __exit nvme_exit(void)
3469{
3470 pci_unregister_driver(&nvme_driver);
3471 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3472 destroy_workqueue(nvme_workq);
b3fffdef
KB		 3473 class_destroy(nvme_class);
3474 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
b9afca3e 3475 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3476 _nvme_check_size();
b60503ba
MW		 3477}
3478
3479MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3480MODULE_LICENSE("GPL");
c78b4713 3481MODULE_VERSION("1.0");
b60503ba
MW		 3482module_init(nvme_init);
3483module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)