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net/mlx4: Add reference counting to MAC registeration
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
4d531aa8 94 [12] = "Dual Port Different Protocol (DPDP) support",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
540b3a39 112 [53] = "Port ETS Scheduler support",
4d531aa8 113 [55] = "Port link type sensing support",
00f5ce99 114 [59] = "Port management change event support",
08ff3235
OG		 115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
225c7b1f
RD		 117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 122 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 123 mlx4_dbg(dev, " %s\n", fname[i]);
124}
125
b3416f44
SP		 126static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127{
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65 131 [2] = "RSS XOR Hash Function support",
955154fa 132 [3] = "Device manage flow steering support",
d998735f
EE		 133 [4] = "Automatic MAC reassignment support",
134 [5] = "Time stamping support"
b3416f44
SP		 135 };
136 int i;
137
138 for (i = 0; i < ARRAY_SIZE(fname); ++i)
139 if (fname[i] && (flags & (1LL << i)))
140 mlx4_dbg(dev, " %s\n", fname[i]);
141}
142
2d928651
VS		 143int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
144{
145 struct mlx4_cmd_mailbox *mailbox;
146 u32 *inbox;
147 int err = 0;
148
149#define MOD_STAT_CFG_IN_SIZE 0x100
150
151#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
152#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
153
154 mailbox = mlx4_alloc_cmd_mailbox(dev);
155 if (IS_ERR(mailbox))
156 return PTR_ERR(mailbox);
157 inbox = mailbox->buf;
158
159 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
160
161 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
162 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
163
164 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 165 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 166
167 mlx4_free_cmd_mailbox(dev, mailbox);
168 return err;
169}
170
5cc914f1
MA		 171int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
172 struct mlx4_vhcr *vhcr,
173 struct mlx4_cmd_mailbox *inbox,
174 struct mlx4_cmd_mailbox *outbox,
175 struct mlx4_cmd_info *cmd)
176{
177 u8 field;
178 u32 size;
179 int err = 0;
180
181#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
182#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 183#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 184#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
5cc914f1
MA		 185#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
186#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
187#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
188#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
189#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
190#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
191#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 192#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
5cc914f1 193
105c320f
JM		 194#define QUERY_FUNC_CAP_FMR_FLAG 0x80
195#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
196#define QUERY_FUNC_CAP_FLAG_ETH 0x80
197
198/* when opcode modifier = 1 */
5cc914f1 199#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
105c320f 200#define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8
5cc914f1
MA		 201#define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
202
47605df9
JM		 203#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
204#define QUERY_FUNC_CAP_QP0_PROXY 0x14
205#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
206#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
207
105c320f
JM		 208#define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40
209#define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80
210
211#define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80
212
5cc914f1 213 if (vhcr->op_modifier == 1) {
105c320f
JM		 214 field = 0;
215 /* ensure force vlan and force mac bits are not set */
5cc914f1 216 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
105c320f
JM		 217 /* ensure that phy_wqe_gid bit is not set */
218 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
219
47605df9
JM		 220 field = vhcr->in_modifier; /* phys-port = logical-port */
221 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
222
223 /* size is now the QP number */
224 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1;
225 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
226
227 size += 2;
228 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
229
230 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1;
231 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY);
232
233 size += 2;
234 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY);
235
5cc914f1 236 } else if (vhcr->op_modifier == 0) {
105c320f
JM		 237 /* enable rdma and ethernet interfaces */
238 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA);
5cc914f1
MA		 239 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
240
5cc914f1
MA		 241 field = dev->caps.num_ports;
242 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
243
08ff3235 244 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 245 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
246
105c320f
JM		 247 field = 0; /* protected FMR support not available as yet */
248 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
249
5cc914f1
MA		 250 size = dev->caps.num_qps;
251 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
252
253 size = dev->caps.num_srqs;
254 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
255
256 size = dev->caps.num_cqs;
257 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
258
259 size = dev->caps.num_eqs;
260 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
261
262 size = dev->caps.reserved_eqs;
263 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
264
265 size = dev->caps.num_mpts;
266 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
267
2b8fb286 268 size = dev->caps.num_mtts;
5cc914f1
MA		 269 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
270
271 size = dev->caps.num_mgms + dev->caps.num_amgms;
272 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
273
274 } else
275 err = -EINVAL;
276
277 return err;
278}
279
47605df9
JM		 280int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
281 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 282{
283 struct mlx4_cmd_mailbox *mailbox;
284 u32 *outbox;
47605df9 285 u8 field, op_modifier;
5cc914f1 286 u32 size;
5cc914f1
MA		 287 int err = 0;
288
47605df9 289 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
5cc914f1
MA		 290
291 mailbox = mlx4_alloc_cmd_mailbox(dev);
292 if (IS_ERR(mailbox))
293 return PTR_ERR(mailbox);
294
47605df9
JM		 295 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
296 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 297 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
298 if (err)
299 goto out;
300
301 outbox = mailbox->buf;
302
47605df9
JM		 303 if (!op_modifier) {
304 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
305 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
306 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
307 err = -EPROTONOSUPPORT;
308 goto out;
309 }
310 func_cap->flags = field;
5cc914f1 311
47605df9
JM		 312 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
313 func_cap->num_ports = field;
5cc914f1 314
47605df9
JM		 315 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
316 func_cap->pf_context_behaviour = size;
5cc914f1 317
47605df9
JM		 318 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
319 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 320
47605df9
JM		 321 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
322 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 323
47605df9
JM		 324 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
325 func_cap->cq_quota = size & 0xFFFFFF;
5cc914f1 326
47605df9
JM		 327 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
328 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 329
47605df9
JM		 330 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
331 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 332
47605df9
JM		 333 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
334 func_cap->mpt_quota = size & 0xFFFFFF;
5cc914f1 335
47605df9
JM		 336 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
337 func_cap->mtt_quota = size & 0xFFFFFF;
5cc914f1 338
47605df9
JM		 339 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
340 func_cap->mcg_quota = size & 0xFFFFFF;
341 goto out;
342 }
5cc914f1 343
47605df9
JM		 344 /* logical port query */
345 if (gen_or_port > dev->caps.num_ports) {
346 err = -EINVAL;
347 goto out;
348 }
5cc914f1 349
47605df9
JM		 350 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
351 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
352 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) {
353 mlx4_err(dev, "VLAN is enforced on this port\n");
354 err = -EPROTONOSUPPORT;
5cc914f1 355 goto out;
47605df9 356 }
5cc914f1 357
47605df9
JM		 358 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) {
359 mlx4_err(dev, "Force mac is enabled on this port\n");
360 err = -EPROTONOSUPPORT;
361 goto out;
5cc914f1 362 }
47605df9
JM		 363 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
364 MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
365 if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) {
366 mlx4_err(dev, "phy_wqe_gid is "
367 "enforced on this ib port\n");
368 err = -EPROTONOSUPPORT;
369 goto out;
370 }
371 }
5cc914f1 372
47605df9
JM		 373 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
374 func_cap->physical_port = field;
375 if (func_cap->physical_port != gen_or_port) {
376 err = -ENOSYS;
377 goto out;
5cc914f1
MA		 378 }
379
47605df9
JM		 380 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
381 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
382
383 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
384 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
385
386 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
387 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
388
389 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
390 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
391
5cc914f1
MA		 392 /* All other resources are allocated by the master, but we still report
393 * 'num' and 'reserved' capabilities as follows:
394 * - num remains the maximum resource index
395 * - 'num - reserved' is the total available objects of a resource, but
396 * resource indices may be less than 'reserved'
397 * TODO: set per-resource quotas */
398
399out:
400 mlx4_free_cmd_mailbox(dev, mailbox);
401
402 return err;
403}
404
225c7b1f
RD		 405int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
406{
407 struct mlx4_cmd_mailbox *mailbox;
408 u32 *outbox;
409 u8 field;
ccf86321 410 u32 field32, flags, ext_flags;
225c7b1f
RD		 411 u16 size;
412 u16 stat_rate;
413 int err;
5ae2a7a8 414 int i;
225c7b1f
RD		 415
416#define QUERY_DEV_CAP_OUT_SIZE 0x100
417#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
418#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
419#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
420#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
421#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
422#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
423#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
424#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
425#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
426#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
427#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
428#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
429#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
430#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
431#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
432#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
433#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
434#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
435#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
436#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
437#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 438#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 439#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 440#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
441#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
442#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
443#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
444#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 445#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 446#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
447#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
d998735f 448#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
225c7b1f 449#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 450#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 451#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
452#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
453#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
454#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
455#define QUERY_DEV_CAP_BF_OFFSET 0x4c
456#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
457#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
458#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
459#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
460#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
461#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
462#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
463#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
464#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
465#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
466#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
467#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 468#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
469#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 470#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
0ff1fb65
HHZ		 471#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
472#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
225c7b1f
RD		 473#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
474#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
475#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
476#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
477#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
478#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
479#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
480#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
481#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
482#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 483#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 484#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
485#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
955154fa 486#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
225c7b1f 487
b3416f44 488 dev_cap->flags2 = 0;
225c7b1f
RD		 489 mailbox = mlx4_alloc_cmd_mailbox(dev);
490 if (IS_ERR(mailbox))
491 return PTR_ERR(mailbox);
492 outbox = mailbox->buf;
493
494 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 495 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 496 if (err)
497 goto out;
498
499 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
500 dev_cap->reserved_qps = 1 << (field & 0xf);
501 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
502 dev_cap->max_qps = 1 << (field & 0x1f);
503 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
504 dev_cap->reserved_srqs = 1 << (field >> 4);
505 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
506 dev_cap->max_srqs = 1 << (field & 0x1f);
507 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
508 dev_cap->max_cq_sz = 1 << field;
509 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
510 dev_cap->reserved_cqs = 1 << (field & 0xf);
511 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
512 dev_cap->max_cqs = 1 << (field & 0x1f);
513 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
514 dev_cap->max_mpts = 1 << (field & 0x3f);
515 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 516 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 517 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 518 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 519 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
520 dev_cap->reserved_mtts = 1 << (field >> 4);
521 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
522 dev_cap->max_mrw_sz = 1 << field;
523 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
524 dev_cap->reserved_mrws = 1 << (field & 0xf);
525 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
526 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
527 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
528 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
529 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
530 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 531 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
532 field &= 0x1f;
533 if (!field)
534 dev_cap->max_gso_sz = 0;
535 else
536 dev_cap->max_gso_sz = 1 << field;
537
b3416f44
SP		 538 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
539 if (field & 0x20)
540 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
541 if (field & 0x10)
542 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
543 field &= 0xf;
544 if (field) {
545 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
546 dev_cap->max_rss_tbl_sz = 1 << field;
547 } else
548 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 549 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
550 dev_cap->max_rdma_global = 1 << (field & 0x3f);
551 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
552 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 553 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 554 dev_cap->num_ports = field & 0xf;
149983af
DB		 555 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
556 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 557 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
558 if (field & 0x80)
559 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
560 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
561 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
562 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 563 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
564 dev_cap->stat_rate_support = stat_rate;
d998735f
EE		 565 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
566 if (field & 0x80)
567 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
ccf86321 568 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 569 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 570 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 571 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
572 dev_cap->reserved_uars = field >> 4;
573 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
574 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
575 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
576 dev_cap->min_page_sz = 1 << field;
577
578 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
579 if (field & 0x80) {
580 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
581 dev_cap->bf_reg_size = 1 << (field & 0x1f);
582 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 583 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 584 field = 3;
225c7b1f
RD		 585 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
586 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
587 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
588 } else {
589 dev_cap->bf_reg_size = 0;
590 mlx4_dbg(dev, "BlueFlame not available\n");
591 }
592
593 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
594 dev_cap->max_sq_sg = field;
595 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
596 dev_cap->max_sq_desc_sz = size;
597
598 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
599 dev_cap->max_qp_per_mcg = 1 << field;
600 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
601 dev_cap->reserved_mgms = field & 0xf;
602 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
603 dev_cap->max_mcgs = 1 << field;
604 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
605 dev_cap->reserved_pds = field >> 4;
606 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
607 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 608 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
609 dev_cap->reserved_xrcds = field >> 4;
426dd00d 610 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 611 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 612
613 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
614 dev_cap->rdmarc_entry_sz = size;
615 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
616 dev_cap->qpc_entry_sz = size;
617 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
618 dev_cap->aux_entry_sz = size;
619 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
620 dev_cap->altc_entry_sz = size;
621 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
622 dev_cap->eqc_entry_sz = size;
623 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
624 dev_cap->cqc_entry_sz = size;
625 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
626 dev_cap->srq_entry_sz = size;
627 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
628 dev_cap->cmpt_entry_sz = size;
629 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
630 dev_cap->mtt_entry_sz = size;
631 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
632 dev_cap->dmpt_entry_sz = size;
633
634 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
635 dev_cap->max_srq_sz = 1 << field;
636 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
637 dev_cap->max_qp_sz = 1 << field;
638 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
639 dev_cap->resize_srq = field & 1;
640 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
641 dev_cap->max_rq_sg = field;
642 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
643 dev_cap->max_rq_desc_sz = size;
644
645 MLX4_GET(dev_cap->bmme_flags, outbox,
646 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
647 MLX4_GET(dev_cap->reserved_lkey, outbox,
648 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
955154fa
MB		 649 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
650 if (field & 1<<6)
651 dev_cap->flags2 |= MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN;
225c7b1f
RD		 652 MLX4_GET(dev_cap->max_icm_sz, outbox,
653 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 654 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
655 MLX4_GET(dev_cap->max_counters, outbox,
656 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 657
5ae2a7a8
RD		 658 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
659 for (i = 1; i <= dev_cap->num_ports; ++i) {
660 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
661 dev_cap->max_vl[i] = field >> 4;
662 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 663 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 664 dev_cap->max_port_width[i] = field & 0xf;
665 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
666 dev_cap->max_gids[i] = 1 << (field & 0xf);
667 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
668 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
669 }
670 } else {
7ff93f8b 671#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 672#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 673#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 674#define QUERY_PORT_WIDTH_OFFSET 0x06
675#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 676#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 677#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 678#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 679#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
680#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
681#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 682
683 for (i = 1; i <= dev_cap->num_ports; ++i) {
684 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
401453a3 685 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
5ae2a7a8
RD		 686 if (err)
687 goto out;
688
7ff93f8b
YP		 689 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
690 dev_cap->supported_port_types[i] = field & 3;
8d0fc7b6
YP		 691 dev_cap->suggested_type[i] = (field >> 3) & 1;
692 dev_cap->default_sense[i] = (field >> 4) & 1;
5ae2a7a8 693 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 694 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 695 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
696 dev_cap->max_port_width[i] = field & 0xf;
697 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
698 dev_cap->max_gids[i] = 1 << (field >> 4);
699 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
700 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
701 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 702 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
703 dev_cap->log_max_macs[i] = field & 0xf;
704 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 705 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
706 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 707 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
708 dev_cap->trans_type[i] = field32 >> 24;
709 dev_cap->vendor_oui[i] = field32 & 0xffffff;
710 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
711 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 712 }
713 }
714
95d04f07
RD		 715 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
716 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 717
718 /*
719 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
720 * we can't use any EQs whose doorbell falls on that page,
721 * even if the EQ itself isn't reserved.
722 */
723 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
724 dev_cap->reserved_eqs);
725
726 mlx4_dbg(dev, "Max ICM size %lld MB\n",
727 (unsigned long long) dev_cap->max_icm_sz >> 20);
728 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
729 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
730 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
731 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
732 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
733 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
734 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
735 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
736 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
737 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
738 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
739 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
740 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
741 dev_cap->max_pds, dev_cap->reserved_mgms);
742 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
743 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
744 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 745 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 746 dev_cap->max_port_width[1]);
225c7b1f
RD		 747 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
748 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
749 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
750 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 751 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 752 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 753 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
225c7b1f
RD		 754
755 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 756 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 757
758out:
759 mlx4_free_cmd_mailbox(dev, mailbox);
760 return err;
761}
762
b91cb3eb
JM		 763int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
764 struct mlx4_vhcr *vhcr,
765 struct mlx4_cmd_mailbox *inbox,
766 struct mlx4_cmd_mailbox *outbox,
767 struct mlx4_cmd_info *cmd)
768{
2a4fae14 769 u64 flags;
b91cb3eb
JM		 770 int err = 0;
771 u8 field;
cc1ade94 772 u32 bmme_flags;
b91cb3eb
JM		 773
774 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
775 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
776 if (err)
777 return err;
778
cc1ade94
SM		 779 /* add port mng change event capability and disable mw type 1
780 * unconditionally to slaves
781 */
2a4fae14
JM		 782 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
783 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
cc1ade94 784 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
2a4fae14
JM		 785 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
786
30b40c31
AV		 787 /* For guests, disable timestamp */
788 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
789 field &= 0x7f;
790 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
791
b91cb3eb
JM		 792 /* For guests, report Blueflame disabled */
793 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
794 field &= 0x7f;
795 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
796
cc1ade94
SM		 797 /* For guests, disable mw type 2 */
798 MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
799 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
800 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
801
0081c8f3
JM		 802 /* turn off device-managed steering capability if not enabled */
803 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
804 MLX4_GET(field, outbox->buf,
805 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
806 field &= 0x7f;
807 MLX4_PUT(outbox->buf, field,
808 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
809 }
b91cb3eb
JM		 810 return 0;
811}
812
5cc914f1
MA		 813int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
814 struct mlx4_vhcr *vhcr,
815 struct mlx4_cmd_mailbox *inbox,
816 struct mlx4_cmd_mailbox *outbox,
817 struct mlx4_cmd_info *cmd)
818{
819 u64 def_mac;
820 u8 port_type;
6634961c 821 u16 short_field;
5cc914f1
MA		 822 int err;
823
105c320f 824#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
6634961c
JM		 825#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
826#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 827
5cc914f1
MA		 828 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
829 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
830 MLX4_CMD_NATIVE);
831
832 if (!err && dev->caps.function != slave) {
833 /* set slave default_mac address */
834 MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
835 def_mac += slave << 8;
836 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
837
838 /* get port type - currently only eth is enabled */
839 MLX4_GET(port_type, outbox->buf,
840 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
841
105c320f
JM		 842 /* No link sensing allowed */
843 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
844 /* set port type to currently operating port type */
845 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1
MA		 846
847 MLX4_PUT(outbox->buf, port_type,
848 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c
JM		 849
850 short_field = 1; /* slave max gids */
851 MLX4_PUT(outbox->buf, short_field,
852 QUERY_PORT_CUR_MAX_GID_OFFSET);
853
854 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
855 MLX4_PUT(outbox->buf, short_field,
856 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1
MA		 857 }
858
859 return err;
860}
861
6634961c
JM		 862int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
863 int *gid_tbl_len, int *pkey_tbl_len)
864{
865 struct mlx4_cmd_mailbox *mailbox;
866 u32 *outbox;
867 u16 field;
868 int err;
869
870 mailbox = mlx4_alloc_cmd_mailbox(dev);
871 if (IS_ERR(mailbox))
872 return PTR_ERR(mailbox);
873
874 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
875 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
876 MLX4_CMD_WRAPPED);
877 if (err)
878 goto out;
879
880 outbox = mailbox->buf;
881
882 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
883 *gid_tbl_len = field;
884
885 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
886 *pkey_tbl_len = field;
887
888out:
889 mlx4_free_cmd_mailbox(dev, mailbox);
890 return err;
891}
892EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
893
225c7b1f
RD		 894int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
895{
896 struct mlx4_cmd_mailbox *mailbox;
897 struct mlx4_icm_iter iter;
898 __be64 *pages;
899 int lg;
900 int nent = 0;
901 int i;
902 int err = 0;
903 int ts = 0, tc = 0;
904
905 mailbox = mlx4_alloc_cmd_mailbox(dev);
906 if (IS_ERR(mailbox))
907 return PTR_ERR(mailbox);
908 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
909 pages = mailbox->buf;
910
911 for (mlx4_icm_first(icm, &iter);
912 !mlx4_icm_last(&iter);
913 mlx4_icm_next(&iter)) {
914 /*
915 * We have to pass pages that are aligned to their
916 * size, so find the least significant 1 in the
917 * address or size and use that as our log2 size.
918 */
919 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
920 if (lg < MLX4_ICM_PAGE_SHIFT) {
921 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
922 MLX4_ICM_PAGE_SIZE,
923 (unsigned long long) mlx4_icm_addr(&iter),
924 mlx4_icm_size(&iter));
925 err = -EINVAL;
926 goto out;
927 }
928
929 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
930 if (virt != -1) {
931 pages[nent * 2] = cpu_to_be64(virt);
932 virt += 1 << lg;
933 }
934
935 pages[nent * 2 + 1] =
936 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
937 (lg - MLX4_ICM_PAGE_SHIFT));
938 ts += 1 << (lg - 10);
939 ++tc;
940
941 if (++nent == MLX4_MAILBOX_SIZE / 16) {
942 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 943 MLX4_CMD_TIME_CLASS_B,
944 MLX4_CMD_NATIVE);
225c7b1f
RD		 945 if (err)
946 goto out;
947 nent = 0;
948 }
949 }
950 }
951
952 if (nent)
f9baff50
JM		 953 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
954 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 955 if (err)
956 goto out;
957
958 switch (op) {
959 case MLX4_CMD_MAP_FA:
960 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
961 break;
962 case MLX4_CMD_MAP_ICM_AUX:
963 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
964 break;
965 case MLX4_CMD_MAP_ICM:
966 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
967 tc, ts, (unsigned long long) virt - (ts << 10));
968 break;
969 }
970
971out:
972 mlx4_free_cmd_mailbox(dev, mailbox);
973 return err;
974}
975
976int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
977{
978 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
979}
980
981int mlx4_UNMAP_FA(struct mlx4_dev *dev)
982{
f9baff50
JM		 983 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
984 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 985}
986
987
988int mlx4_RUN_FW(struct mlx4_dev *dev)
989{
f9baff50
JM		 990 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
991 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 992}
993
994int mlx4_QUERY_FW(struct mlx4_dev *dev)
995{
996 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
997 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
998 struct mlx4_cmd_mailbox *mailbox;
999 u32 *outbox;
1000 int err = 0;
1001 u64 fw_ver;
fe40900f 1002 u16 cmd_if_rev;
225c7b1f
RD		 1003 u8 lg;
1004
1005#define QUERY_FW_OUT_SIZE 0x100
1006#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 1007#define QUERY_FW_PPF_ID 0x09
fe40900f 1008#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 1009#define QUERY_FW_MAX_CMD_OFFSET 0x0f
1010#define QUERY_FW_ERR_START_OFFSET 0x30
1011#define QUERY_FW_ERR_SIZE_OFFSET 0x38
1012#define QUERY_FW_ERR_BAR_OFFSET 0x3c
1013
1014#define QUERY_FW_SIZE_OFFSET 0x00
1015#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1016#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1017
5cc914f1
MA		 1018#define QUERY_FW_COMM_BASE_OFFSET 0x40
1019#define QUERY_FW_COMM_BAR_OFFSET 0x48
1020
ddd8a6c1
EE		 1021#define QUERY_FW_CLOCK_OFFSET 0x50
1022#define QUERY_FW_CLOCK_BAR 0x58
1023
225c7b1f
RD		 1024 mailbox = mlx4_alloc_cmd_mailbox(dev);
1025 if (IS_ERR(mailbox))
1026 return PTR_ERR(mailbox);
1027 outbox = mailbox->buf;
1028
1029 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 1030 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1031 if (err)
1032 goto out;
1033
1034 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1035 /*
3e1db334 1036 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1037 * version, so swap here.
1038 */
1039 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1040 ((fw_ver & 0xffff0000ull) >> 16) |
1041 ((fw_ver & 0x0000ffffull) << 16);
1042
752a50ca
JM		 1043 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1044 dev->caps.function = lg;
1045
b91cb3eb
JM		 1046 if (mlx4_is_slave(dev))
1047 goto out;
1048
5cc914f1 1049
fe40900f 1050 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1051 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1052 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 1053 mlx4_err(dev, "Installed FW has unsupported "
1054 "command interface revision %d.\n",
1055 cmd_if_rev);
1056 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1057 (int) (dev->caps.fw_ver >> 32),
1058 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1059 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 1060 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
1061 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1062 err = -ENODEV;
1063 goto out;
1064 }
1065
5ae2a7a8
RD		 1066 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1067 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1068
225c7b1f
RD		 1069 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1070 cmd->max_cmds = 1 << lg;
1071
fe40900f 1072 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1073 (int) (dev->caps.fw_ver >> 32),
1074 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1075 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1076 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1077
1078 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1079 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1080 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1081 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1082
1083 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1084 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1085
1086 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1087 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1088 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1089 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1090
5cc914f1
MA		 1091 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1092 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1093 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1094 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1095 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1096 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1097
ddd8a6c1
EE		 1098 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1099 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1100 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1101 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1102 fw->clock_bar, fw->clock_offset);
1103
225c7b1f
RD		 1104 /*
1105 * Round up number of system pages needed in case
1106 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1107 */
1108 fw->fw_pages =
1109 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1110 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1111
1112 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1113 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1114
1115out:
1116 mlx4_free_cmd_mailbox(dev, mailbox);
1117 return err;
1118}
1119
b91cb3eb
JM		 1120int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1121 struct mlx4_vhcr *vhcr,
1122 struct mlx4_cmd_mailbox *inbox,
1123 struct mlx4_cmd_mailbox *outbox,
1124 struct mlx4_cmd_info *cmd)
1125{
1126 u8 *outbuf;
1127 int err;
1128
1129 outbuf = outbox->buf;
1130 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1131 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1132 if (err)
1133 return err;
1134
752a50ca
JM		 1135 /* for slaves, set pci PPF ID to invalid and zero out everything
1136 * else except FW version */
b91cb3eb
JM		 1137 outbuf[0] = outbuf[1] = 0;
1138 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1139 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1140
b91cb3eb
JM		 1141 return 0;
1142}
1143
225c7b1f
RD		 1144static void get_board_id(void *vsd, char *board_id)
1145{
1146 int i;
1147
1148#define VSD_OFFSET_SIG1 0x00
1149#define VSD_OFFSET_SIG2 0xde
1150#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1151#define VSD_OFFSET_TS_BOARD_ID 0x20
1152
1153#define VSD_SIGNATURE_TOPSPIN 0x5ad
1154
1155 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1156
1157 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1158 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1159 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1160 } else {
1161 /*
1162 * The board ID is a string but the firmware byte
1163 * swaps each 4-byte word before passing it back to
1164 * us. Therefore we need to swab it before printing.
1165 */
1166 for (i = 0; i < 4; ++i)
1167 ((u32 *) board_id)[i] =
1168 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1169 }
1170}
1171
1172int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1173{
1174 struct mlx4_cmd_mailbox *mailbox;
1175 u32 *outbox;
1176 int err;
1177
1178#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1179#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1180#define QUERY_ADAPTER_VSD_OFFSET 0x20
1181
1182 mailbox = mlx4_alloc_cmd_mailbox(dev);
1183 if (IS_ERR(mailbox))
1184 return PTR_ERR(mailbox);
1185 outbox = mailbox->buf;
1186
1187 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1188 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1189 if (err)
1190 goto out;
1191
225c7b1f
RD		 1192 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1193
1194 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1195 adapter->board_id);
1196
1197out:
1198 mlx4_free_cmd_mailbox(dev, mailbox);
1199 return err;
1200}
1201
1202int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1203{
1204 struct mlx4_cmd_mailbox *mailbox;
1205 __be32 *inbox;
1206 int err;
1207
1208#define INIT_HCA_IN_SIZE 0x200
1209#define INIT_HCA_VERSION_OFFSET 0x000
1210#define INIT_HCA_VERSION 2
c57e20dc 1211#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 1212#define INIT_HCA_FLAGS_OFFSET 0x014
1213#define INIT_HCA_QPC_OFFSET 0x020
1214#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1215#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1216#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1217#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1218#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1219#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1220#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
225c7b1f
RD		 1221#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1222#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1223#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1224#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1225#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1226#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1227#define INIT_HCA_MCAST_OFFSET 0x0c0
1228#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1229#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1230#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1231#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1232#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1233#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1234#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1235#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1236#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1237#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1238#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1239#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1240#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1241#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1242#define INIT_HCA_TPT_OFFSET 0x0f0
1243#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
e448834e 1244#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
225c7b1f
RD		 1245#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1246#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1247#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1248#define INIT_HCA_UAR_OFFSET 0x120
1249#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1250#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1251
1252 mailbox = mlx4_alloc_cmd_mailbox(dev);
1253 if (IS_ERR(mailbox))
1254 return PTR_ERR(mailbox);
1255 inbox = mailbox->buf;
1256
1257 memset(inbox, 0, INIT_HCA_IN_SIZE);
1258
1259 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1260
c57e20dc
EC		 1261 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1262 (ilog2(cache_line_size()) - 4) << 5;
1263
225c7b1f
RD		 1264#if defined(__LITTLE_ENDIAN)
1265 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1266#elif defined(__BIG_ENDIAN)
1267 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1268#else
1269#error Host endianness not defined
1270#endif
1271 /* Check port for UD address vector: */
1272 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1273
8ff095ec
EC		 1274 /* Enable IPoIB checksumming if we can: */
1275 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1276 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1277
51f5f0ee
JM		 1278 /* Enable QoS support if module parameter set */
1279 if (enable_qos)
1280 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1281
f2a3f6a3
OG		 1282 /* enable counters */
1283 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1284 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1285
08ff3235
OG		 1286 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1287 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1288 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1289 dev->caps.eqe_size = 64;
1290 dev->caps.eqe_factor = 1;
1291 } else {
1292 dev->caps.eqe_size = 32;
1293 dev->caps.eqe_factor = 0;
1294 }
1295
1296 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1297 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1298 dev->caps.cqe_size = 64;
1299 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1300 } else {
1301 dev->caps.cqe_size = 32;
1302 }
1303
225c7b1f
RD		 1304 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1305
1306 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1307 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1308 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1309 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1310 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1311 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1312 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1313 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1314 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1315 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1316 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1317 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1318
0ff1fb65
HHZ		 1319 /* steering attributes */
1320 if (dev->caps.steering_mode ==
1321 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1322 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1323 cpu_to_be32(1 <<
1324 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1325
1326 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1327 MLX4_PUT(inbox, param->log_mc_entry_sz,
1328 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1329 MLX4_PUT(inbox, param->log_mc_table_sz,
1330 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1331 /* Enable Ethernet flow steering
1332 * with udp unicast and tcp unicast
1333 */
23537b73 1334 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1335 INIT_HCA_FS_ETH_BITS_OFFSET);
1336 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1337 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1338 /* Enable IPoIB flow steering
1339 * with udp unicast and tcp unicast
1340 */
23537b73 1341 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1342 INIT_HCA_FS_IB_BITS_OFFSET);
1343 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1344 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1345 } else {
1346 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1347 MLX4_PUT(inbox, param->log_mc_entry_sz,
1348 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1349 MLX4_PUT(inbox, param->log_mc_hash_sz,
1350 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1351 MLX4_PUT(inbox, param->log_mc_table_sz,
1352 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1353 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1354 MLX4_PUT(inbox, (u8) (1 << 3),
1355 INIT_HCA_UC_STEERING_OFFSET);
1356 }
225c7b1f
RD		 1357
1358 /* TPT attributes */
1359
1360 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1361 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
225c7b1f
RD		 1362 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1363 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1364 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1365
1366 /* UAR attributes */
1367
ab9c17a0 1368 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1369 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1370
f9baff50
JM		 1371 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1372 MLX4_CMD_NATIVE);
225c7b1f
RD		 1373
1374 if (err)
1375 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1376
1377 mlx4_free_cmd_mailbox(dev, mailbox);
1378 return err;
1379}
1380
ab9c17a0
JM		 1381int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1382 struct mlx4_init_hca_param *param)
1383{
1384 struct mlx4_cmd_mailbox *mailbox;
1385 __be32 *outbox;
7b8157be 1386 u32 dword_field;
ab9c17a0 1387 int err;
08ff3235 1388 u8 byte_field;
ab9c17a0
JM		 1389
1390#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
ddd8a6c1 1391#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
ab9c17a0
JM		 1392
1393 mailbox = mlx4_alloc_cmd_mailbox(dev);
1394 if (IS_ERR(mailbox))
1395 return PTR_ERR(mailbox);
1396 outbox = mailbox->buf;
1397
1398 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1399 MLX4_CMD_QUERY_HCA,
1400 MLX4_CMD_TIME_CLASS_B,
1401 !mlx4_is_slave(dev));
1402 if (err)
1403 goto out;
1404
1405 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
ddd8a6c1 1406 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
ab9c17a0
JM		 1407
1408 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1409
1410 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1411 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1412 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1413 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1414 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1415 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1416 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1417 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1418 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1419 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1420 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1421 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1422
7b8157be
JM		 1423 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1424 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1425 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1426 } else {
1427 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1428 if (byte_field & 0x8)
1429 param->steering_mode = MLX4_STEERING_MODE_B0;
1430 else
1431 param->steering_mode = MLX4_STEERING_MODE_A0;
1432 }
0ff1fb65 1433 /* steering attributes */
7b8157be 1434 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
0ff1fb65
HHZ		 1435 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1436 MLX4_GET(param->log_mc_entry_sz, outbox,
1437 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1438 MLX4_GET(param->log_mc_table_sz, outbox,
1439 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1440 } else {
1441 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1442 MLX4_GET(param->log_mc_entry_sz, outbox,
1443 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1444 MLX4_GET(param->log_mc_hash_sz, outbox,
1445 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1446 MLX4_GET(param->log_mc_table_sz, outbox,
1447 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1448 }
ab9c17a0 1449
08ff3235
OG		 1450 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1451 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1452 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1453 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1454 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1455 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1456
ab9c17a0
JM		 1457 /* TPT attributes */
1458
1459 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1460 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
ab9c17a0
JM		 1461 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1462 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1463 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1464
1465 /* UAR attributes */
1466
1467 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1468 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1469
1470out:
1471 mlx4_free_cmd_mailbox(dev, mailbox);
1472
1473 return err;
1474}
1475
980e9001
JM		 1476/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1477 * and real QP0 are active, so that the paravirtualized QP0 is ready
1478 * to operate */
1479static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1480{
1481 struct mlx4_priv *priv = mlx4_priv(dev);
1482 /* irrelevant if not infiniband */
1483 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1484 priv->mfunc.master.qp0_state[port].qp0_active)
1485 return 1;
1486 return 0;
1487}
1488
5cc914f1
MA		 1489int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1490 struct mlx4_vhcr *vhcr,
1491 struct mlx4_cmd_mailbox *inbox,
1492 struct mlx4_cmd_mailbox *outbox,
1493 struct mlx4_cmd_info *cmd)
1494{
1495 struct mlx4_priv *priv = mlx4_priv(dev);
1496 int port = vhcr->in_modifier;
1497 int err;
1498
1499 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1500 return 0;
1501
980e9001
JM		 1502 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1503 /* Enable port only if it was previously disabled */
1504 if (!priv->mfunc.master.init_port_ref[port]) {
1505 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1506 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1507 if (err)
1508 return err;
1509 }
1510 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1511 } else {
1512 if (slave == mlx4_master_func_num(dev)) {
1513 if (check_qp0_state(dev, slave, port) &&
1514 !priv->mfunc.master.qp0_state[port].port_active) {
1515 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1516 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1517 if (err)
1518 return err;
1519 priv->mfunc.master.qp0_state[port].port_active = 1;
1520 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1521 }
1522 } else
1523 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1524 }
1525 ++priv->mfunc.master.init_port_ref[port];
1526 return 0;
1527}
1528
5ae2a7a8 1529int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1530{
1531 struct mlx4_cmd_mailbox *mailbox;
1532 u32 *inbox;
1533 int err;
1534 u32 flags;
5ae2a7a8 1535 u16 field;
225c7b1f 1536
5ae2a7a8 1537 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1538#define INIT_PORT_IN_SIZE 256
1539#define INIT_PORT_FLAGS_OFFSET 0x00
1540#define INIT_PORT_FLAG_SIG (1 << 18)
1541#define INIT_PORT_FLAG_NG (1 << 17)
1542#define INIT_PORT_FLAG_G0 (1 << 16)
1543#define INIT_PORT_VL_SHIFT 4
1544#define INIT_PORT_PORT_WIDTH_SHIFT 8
1545#define INIT_PORT_MTU_OFFSET 0x04
1546#define INIT_PORT_MAX_GID_OFFSET 0x06
1547#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1548#define INIT_PORT_GUID0_OFFSET 0x10
1549#define INIT_PORT_NODE_GUID_OFFSET 0x18
1550#define INIT_PORT_SI_GUID_OFFSET 0x20
1551
5ae2a7a8
RD		 1552 mailbox = mlx4_alloc_cmd_mailbox(dev);
1553 if (IS_ERR(mailbox))
1554 return PTR_ERR(mailbox);
1555 inbox = mailbox->buf;
225c7b1f 1556
5ae2a7a8 1557 memset(inbox, 0, INIT_PORT_IN_SIZE);
225c7b1f 1558
5ae2a7a8
RD		 1559 flags = 0;
1560 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1561 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1562 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1563
b79acb49 1564 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1565 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1566 field = dev->caps.gid_table_len[port];
1567 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1568 field = dev->caps.pkey_table_len[port];
1569 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1570
5ae2a7a8 1571 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1572 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1573
5ae2a7a8
RD		 1574 mlx4_free_cmd_mailbox(dev, mailbox);
1575 } else
1576 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1577 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1578
1579 return err;
1580}
1581EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1582
5cc914f1
MA		 1583int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1584 struct mlx4_vhcr *vhcr,
1585 struct mlx4_cmd_mailbox *inbox,
1586 struct mlx4_cmd_mailbox *outbox,
1587 struct mlx4_cmd_info *cmd)
1588{
1589 struct mlx4_priv *priv = mlx4_priv(dev);
1590 int port = vhcr->in_modifier;
1591 int err;
1592
1593 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1594 (1 << port)))
1595 return 0;
1596
980e9001
JM		 1597 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1598 if (priv->mfunc.master.init_port_ref[port] == 1) {
1599 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1600 1000, MLX4_CMD_NATIVE);
1601 if (err)
1602 return err;
1603 }
1604 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1605 } else {
1606 /* infiniband port */
1607 if (slave == mlx4_master_func_num(dev)) {
1608 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1609 priv->mfunc.master.qp0_state[port].port_active) {
1610 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1611 1000, MLX4_CMD_NATIVE);
1612 if (err)
1613 return err;
1614 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1615 priv->mfunc.master.qp0_state[port].port_active = 0;
1616 }
1617 } else
1618 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 1619 }
5cc914f1
MA		 1620 --priv->mfunc.master.init_port_ref[port];
1621 return 0;
1622}
1623
225c7b1f
RD		 1624int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1625{
f9baff50
JM		 1626 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1627 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1628}
1629EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1630
1631int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1632{
f9baff50
JM		 1633 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1634 MLX4_CMD_NATIVE);
225c7b1f
RD		 1635}
1636
1637int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1638{
1639 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1640 MLX4_CMD_SET_ICM_SIZE,
f9baff50 1641 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1642 if (ret)
1643 return ret;
1644
1645 /*
1646 * Round up number of system pages needed in case
1647 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1648 */
1649 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1650 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1651
1652 return 0;
1653}
1654
1655int mlx4_NOP(struct mlx4_dev *dev)
1656{
1657 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 1658 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 1659}
14c07b13
YP		 1660
1661#define MLX4_WOL_SETUP_MODE (5 << 28)
1662int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1663{
1664 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1665
1666 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 1667 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1668 MLX4_CMD_NATIVE);
14c07b13
YP		 1669}
1670EXPORT_SYMBOL_GPL(mlx4_wol_read);
1671
1672int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1673{
1674 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1675
1676 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 1677 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 1678}
1679EXPORT_SYMBOL_GPL(mlx4_wol_write);
Linux 6.x block layer and io_uring tree(s)