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net/mlx4: Add set VF default vlan ID and priority support
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
4d531aa8 94 [12] = "Dual Port Different Protocol (DPDP) support",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
540b3a39 112 [53] = "Port ETS Scheduler support",
4d531aa8 113 [55] = "Port link type sensing support",
00f5ce99 114 [59] = "Port management change event support",
08ff3235
OG		 115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
225c7b1f
RD		 117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 122 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 123 mlx4_dbg(dev, " %s\n", fname[i]);
124}
125
b3416f44
SP		 126static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127{
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65 131 [2] = "RSS XOR Hash Function support",
955154fa 132 [3] = "Device manage flow steering support",
d998735f
EE		 133 [4] = "Automatic MAC reassignment support",
134 [5] = "Time stamping support"
b3416f44
SP		 135 };
136 int i;
137
138 for (i = 0; i < ARRAY_SIZE(fname); ++i)
139 if (fname[i] && (flags & (1LL << i)))
140 mlx4_dbg(dev, " %s\n", fname[i]);
141}
142
2d928651
VS		 143int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
144{
145 struct mlx4_cmd_mailbox *mailbox;
146 u32 *inbox;
147 int err = 0;
148
149#define MOD_STAT_CFG_IN_SIZE 0x100
150
151#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
152#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
153
154 mailbox = mlx4_alloc_cmd_mailbox(dev);
155 if (IS_ERR(mailbox))
156 return PTR_ERR(mailbox);
157 inbox = mailbox->buf;
158
159 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
160
161 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
162 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
163
164 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 165 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 166
167 mlx4_free_cmd_mailbox(dev, mailbox);
168 return err;
169}
170
5cc914f1
MA		 171int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
172 struct mlx4_vhcr *vhcr,
173 struct mlx4_cmd_mailbox *inbox,
174 struct mlx4_cmd_mailbox *outbox,
175 struct mlx4_cmd_info *cmd)
176{
177 u8 field;
178 u32 size;
179 int err = 0;
180
181#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
182#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 183#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 184#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
5cc914f1
MA		 185#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
186#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
187#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
188#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
189#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
190#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
191#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 192#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
5cc914f1 193
105c320f
JM		 194#define QUERY_FUNC_CAP_FMR_FLAG 0x80
195#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
196#define QUERY_FUNC_CAP_FLAG_ETH 0x80
197
198/* when opcode modifier = 1 */
5cc914f1 199#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
105c320f 200#define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8
5cc914f1
MA		 201#define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
202
47605df9
JM		 203#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
204#define QUERY_FUNC_CAP_QP0_PROXY 0x14
205#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
206#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
207
105c320f
JM		 208#define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40
209#define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80
210
211#define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80
212
5cc914f1 213 if (vhcr->op_modifier == 1) {
105c320f
JM		 214 field = 0;
215 /* ensure force vlan and force mac bits are not set */
5cc914f1 216 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
105c320f
JM		 217 /* ensure that phy_wqe_gid bit is not set */
218 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
219
47605df9
JM		 220 field = vhcr->in_modifier; /* phys-port = logical-port */
221 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
222
223 /* size is now the QP number */
224 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1;
225 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
226
227 size += 2;
228 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
229
230 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1;
231 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY);
232
233 size += 2;
234 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY);
235
5cc914f1 236 } else if (vhcr->op_modifier == 0) {
105c320f
JM		 237 /* enable rdma and ethernet interfaces */
238 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA);
5cc914f1
MA		 239 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
240
5cc914f1
MA		 241 field = dev->caps.num_ports;
242 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
243
08ff3235 244 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 245 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
246
105c320f
JM		 247 field = 0; /* protected FMR support not available as yet */
248 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
249
5cc914f1
MA		 250 size = dev->caps.num_qps;
251 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
252
253 size = dev->caps.num_srqs;
254 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
255
256 size = dev->caps.num_cqs;
257 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
258
259 size = dev->caps.num_eqs;
260 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
261
262 size = dev->caps.reserved_eqs;
263 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
264
265 size = dev->caps.num_mpts;
266 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
267
2b8fb286 268 size = dev->caps.num_mtts;
5cc914f1
MA		 269 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
270
271 size = dev->caps.num_mgms + dev->caps.num_amgms;
272 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
273
274 } else
275 err = -EINVAL;
276
277 return err;
278}
279
47605df9
JM		 280int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
281 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 282{
283 struct mlx4_cmd_mailbox *mailbox;
284 u32 *outbox;
47605df9 285 u8 field, op_modifier;
5cc914f1 286 u32 size;
5cc914f1
MA		 287 int err = 0;
288
47605df9 289 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
5cc914f1
MA		 290
291 mailbox = mlx4_alloc_cmd_mailbox(dev);
292 if (IS_ERR(mailbox))
293 return PTR_ERR(mailbox);
294
47605df9
JM		 295 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
296 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 297 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
298 if (err)
299 goto out;
300
301 outbox = mailbox->buf;
302
47605df9
JM		 303 if (!op_modifier) {
304 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
305 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
306 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
307 err = -EPROTONOSUPPORT;
308 goto out;
309 }
310 func_cap->flags = field;
5cc914f1 311
47605df9
JM		 312 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
313 func_cap->num_ports = field;
5cc914f1 314
47605df9
JM		 315 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
316 func_cap->pf_context_behaviour = size;
5cc914f1 317
47605df9
JM		 318 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
319 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 320
47605df9
JM		 321 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
322 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 323
47605df9
JM		 324 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
325 func_cap->cq_quota = size & 0xFFFFFF;
5cc914f1 326
47605df9
JM		 327 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
328 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 329
47605df9
JM		 330 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
331 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 332
47605df9
JM		 333 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
334 func_cap->mpt_quota = size & 0xFFFFFF;
5cc914f1 335
47605df9
JM		 336 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
337 func_cap->mtt_quota = size & 0xFFFFFF;
5cc914f1 338
47605df9
JM		 339 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
340 func_cap->mcg_quota = size & 0xFFFFFF;
341 goto out;
342 }
5cc914f1 343
47605df9
JM		 344 /* logical port query */
345 if (gen_or_port > dev->caps.num_ports) {
346 err = -EINVAL;
347 goto out;
348 }
5cc914f1 349
47605df9
JM		 350 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
351 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
352 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) {
353 mlx4_err(dev, "VLAN is enforced on this port\n");
354 err = -EPROTONOSUPPORT;
5cc914f1 355 goto out;
47605df9 356 }
5cc914f1 357
47605df9
JM		 358 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) {
359 mlx4_err(dev, "Force mac is enabled on this port\n");
360 err = -EPROTONOSUPPORT;
361 goto out;
5cc914f1 362 }
47605df9
JM		 363 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
364 MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
365 if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) {
366 mlx4_err(dev, "phy_wqe_gid is "
367 "enforced on this ib port\n");
368 err = -EPROTONOSUPPORT;
369 goto out;
370 }
371 }
5cc914f1 372
47605df9
JM		 373 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
374 func_cap->physical_port = field;
375 if (func_cap->physical_port != gen_or_port) {
376 err = -ENOSYS;
377 goto out;
5cc914f1
MA		 378 }
379
47605df9
JM		 380 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
381 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
382
383 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
384 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
385
386 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
387 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
388
389 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
390 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
391
5cc914f1
MA		 392 /* All other resources are allocated by the master, but we still report
393 * 'num' and 'reserved' capabilities as follows:
394 * - num remains the maximum resource index
395 * - 'num - reserved' is the total available objects of a resource, but
396 * resource indices may be less than 'reserved'
397 * TODO: set per-resource quotas */
398
399out:
400 mlx4_free_cmd_mailbox(dev, mailbox);
401
402 return err;
403}
404
225c7b1f
RD		 405int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
406{
407 struct mlx4_cmd_mailbox *mailbox;
408 u32 *outbox;
409 u8 field;
ccf86321 410 u32 field32, flags, ext_flags;
225c7b1f
RD		 411 u16 size;
412 u16 stat_rate;
413 int err;
5ae2a7a8 414 int i;
225c7b1f
RD		 415
416#define QUERY_DEV_CAP_OUT_SIZE 0x100
417#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
418#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
419#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
420#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
421#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
422#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
423#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
424#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
425#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
426#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
427#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
428#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
429#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
430#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
431#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
432#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
433#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
434#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
435#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
436#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
437#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 438#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 439#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 440#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
441#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
442#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
443#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
444#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 445#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 446#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
447#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
d998735f 448#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
225c7b1f 449#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 450#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 451#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
452#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
453#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
454#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
455#define QUERY_DEV_CAP_BF_OFFSET 0x4c
456#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
457#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
458#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
459#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
460#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
461#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
462#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
463#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
464#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
465#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
466#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
467#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 468#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
469#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 470#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
3f7fb021 471#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
0ff1fb65
HHZ		 472#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
473#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
225c7b1f
RD		 474#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
475#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
476#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
477#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
478#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
479#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
480#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
481#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
482#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
483#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 484#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 485#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
486#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
955154fa 487#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
225c7b1f 488
b3416f44 489 dev_cap->flags2 = 0;
225c7b1f
RD		 490 mailbox = mlx4_alloc_cmd_mailbox(dev);
491 if (IS_ERR(mailbox))
492 return PTR_ERR(mailbox);
493 outbox = mailbox->buf;
494
495 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 496 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 497 if (err)
498 goto out;
499
500 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
501 dev_cap->reserved_qps = 1 << (field & 0xf);
502 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
503 dev_cap->max_qps = 1 << (field & 0x1f);
504 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
505 dev_cap->reserved_srqs = 1 << (field >> 4);
506 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
507 dev_cap->max_srqs = 1 << (field & 0x1f);
508 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
509 dev_cap->max_cq_sz = 1 << field;
510 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
511 dev_cap->reserved_cqs = 1 << (field & 0xf);
512 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
513 dev_cap->max_cqs = 1 << (field & 0x1f);
514 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
515 dev_cap->max_mpts = 1 << (field & 0x3f);
516 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 517 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 518 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 519 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 520 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
521 dev_cap->reserved_mtts = 1 << (field >> 4);
522 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
523 dev_cap->max_mrw_sz = 1 << field;
524 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
525 dev_cap->reserved_mrws = 1 << (field & 0xf);
526 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
527 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
528 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
529 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
530 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
531 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 532 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
533 field &= 0x1f;
534 if (!field)
535 dev_cap->max_gso_sz = 0;
536 else
537 dev_cap->max_gso_sz = 1 << field;
538
b3416f44
SP		 539 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
540 if (field & 0x20)
541 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
542 if (field & 0x10)
543 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
544 field &= 0xf;
545 if (field) {
546 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
547 dev_cap->max_rss_tbl_sz = 1 << field;
548 } else
549 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 550 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
551 dev_cap->max_rdma_global = 1 << (field & 0x3f);
552 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
553 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 554 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 555 dev_cap->num_ports = field & 0xf;
149983af
DB		 556 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
557 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 558 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
559 if (field & 0x80)
560 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
561 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
562 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
563 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 564 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
565 dev_cap->stat_rate_support = stat_rate;
d998735f
EE		 566 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
567 if (field & 0x80)
568 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
ccf86321 569 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 570 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 571 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 572 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
573 dev_cap->reserved_uars = field >> 4;
574 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
575 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
576 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
577 dev_cap->min_page_sz = 1 << field;
578
579 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
580 if (field & 0x80) {
581 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
582 dev_cap->bf_reg_size = 1 << (field & 0x1f);
583 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 584 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 585 field = 3;
225c7b1f
RD		 586 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
587 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
588 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
589 } else {
590 dev_cap->bf_reg_size = 0;
591 mlx4_dbg(dev, "BlueFlame not available\n");
592 }
593
594 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
595 dev_cap->max_sq_sg = field;
596 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
597 dev_cap->max_sq_desc_sz = size;
598
599 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
600 dev_cap->max_qp_per_mcg = 1 << field;
601 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
602 dev_cap->reserved_mgms = field & 0xf;
603 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
604 dev_cap->max_mcgs = 1 << field;
605 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
606 dev_cap->reserved_pds = field >> 4;
607 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
608 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 609 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
610 dev_cap->reserved_xrcds = field >> 4;
426dd00d 611 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 612 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 613
614 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
615 dev_cap->rdmarc_entry_sz = size;
616 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
617 dev_cap->qpc_entry_sz = size;
618 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
619 dev_cap->aux_entry_sz = size;
620 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
621 dev_cap->altc_entry_sz = size;
622 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
623 dev_cap->eqc_entry_sz = size;
624 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
625 dev_cap->cqc_entry_sz = size;
626 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
627 dev_cap->srq_entry_sz = size;
628 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
629 dev_cap->cmpt_entry_sz = size;
630 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
631 dev_cap->mtt_entry_sz = size;
632 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
633 dev_cap->dmpt_entry_sz = size;
634
635 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
636 dev_cap->max_srq_sz = 1 << field;
637 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
638 dev_cap->max_qp_sz = 1 << field;
639 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
640 dev_cap->resize_srq = field & 1;
641 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
642 dev_cap->max_rq_sg = field;
643 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
644 dev_cap->max_rq_desc_sz = size;
645
646 MLX4_GET(dev_cap->bmme_flags, outbox,
647 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
648 MLX4_GET(dev_cap->reserved_lkey, outbox,
649 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
955154fa
MB		 650 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
651 if (field & 1<<6)
652 dev_cap->flags2 |= MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN;
225c7b1f
RD		 653 MLX4_GET(dev_cap->max_icm_sz, outbox,
654 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 655 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
656 MLX4_GET(dev_cap->max_counters, outbox,
657 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 658
3f7fb021
RE		 659 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
660 if (field32 & (1 << 26))
661 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
662
5ae2a7a8
RD		 663 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
664 for (i = 1; i <= dev_cap->num_ports; ++i) {
665 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
666 dev_cap->max_vl[i] = field >> 4;
667 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 668 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 669 dev_cap->max_port_width[i] = field & 0xf;
670 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
671 dev_cap->max_gids[i] = 1 << (field & 0xf);
672 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
673 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
674 }
675 } else {
7ff93f8b 676#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 677#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 678#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 679#define QUERY_PORT_WIDTH_OFFSET 0x06
680#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 681#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 682#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 683#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 684#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
685#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
686#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 687
688 for (i = 1; i <= dev_cap->num_ports; ++i) {
689 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
401453a3 690 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
5ae2a7a8
RD		 691 if (err)
692 goto out;
693
7ff93f8b
YP		 694 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
695 dev_cap->supported_port_types[i] = field & 3;
8d0fc7b6
YP		 696 dev_cap->suggested_type[i] = (field >> 3) & 1;
697 dev_cap->default_sense[i] = (field >> 4) & 1;
5ae2a7a8 698 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 699 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 700 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
701 dev_cap->max_port_width[i] = field & 0xf;
702 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
703 dev_cap->max_gids[i] = 1 << (field >> 4);
704 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
705 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
706 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 707 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
708 dev_cap->log_max_macs[i] = field & 0xf;
709 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 710 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
711 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 712 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
713 dev_cap->trans_type[i] = field32 >> 24;
714 dev_cap->vendor_oui[i] = field32 & 0xffffff;
715 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
716 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 717 }
718 }
719
95d04f07
RD		 720 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
721 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 722
723 /*
724 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
725 * we can't use any EQs whose doorbell falls on that page,
726 * even if the EQ itself isn't reserved.
727 */
728 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
729 dev_cap->reserved_eqs);
730
731 mlx4_dbg(dev, "Max ICM size %lld MB\n",
732 (unsigned long long) dev_cap->max_icm_sz >> 20);
733 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
734 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
735 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
736 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
737 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
738 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
739 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
740 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
741 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
742 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
743 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
744 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
745 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
746 dev_cap->max_pds, dev_cap->reserved_mgms);
747 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
748 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
749 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 750 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 751 dev_cap->max_port_width[1]);
225c7b1f
RD		 752 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
753 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
754 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
755 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 756 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 757 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 758 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
225c7b1f
RD		 759
760 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 761 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 762
763out:
764 mlx4_free_cmd_mailbox(dev, mailbox);
765 return err;
766}
767
b91cb3eb
JM		 768int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
769 struct mlx4_vhcr *vhcr,
770 struct mlx4_cmd_mailbox *inbox,
771 struct mlx4_cmd_mailbox *outbox,
772 struct mlx4_cmd_info *cmd)
773{
2a4fae14 774 u64 flags;
b91cb3eb
JM		 775 int err = 0;
776 u8 field;
cc1ade94 777 u32 bmme_flags;
b91cb3eb
JM		 778
779 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
780 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
781 if (err)
782 return err;
783
cc1ade94
SM		 784 /* add port mng change event capability and disable mw type 1
785 * unconditionally to slaves
786 */
2a4fae14
JM		 787 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
788 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
cc1ade94 789 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
2a4fae14
JM		 790 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
791
30b40c31
AV		 792 /* For guests, disable timestamp */
793 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
794 field &= 0x7f;
795 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
796
b91cb3eb
JM		 797 /* For guests, report Blueflame disabled */
798 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
799 field &= 0x7f;
800 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
801
cc1ade94
SM		 802 /* For guests, disable mw type 2 */
803 MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
804 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
805 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
806
0081c8f3
JM		 807 /* turn off device-managed steering capability if not enabled */
808 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
809 MLX4_GET(field, outbox->buf,
810 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
811 field &= 0x7f;
812 MLX4_PUT(outbox->buf, field,
813 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
814 }
b91cb3eb
JM		 815 return 0;
816}
817
5cc914f1
MA		 818int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
819 struct mlx4_vhcr *vhcr,
820 struct mlx4_cmd_mailbox *inbox,
821 struct mlx4_cmd_mailbox *outbox,
822 struct mlx4_cmd_info *cmd)
823{
0eb62b93 824 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 825 u64 def_mac;
826 u8 port_type;
6634961c 827 u16 short_field;
5cc914f1
MA		 828 int err;
829
105c320f 830#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
6634961c
JM		 831#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
832#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 833
5cc914f1
MA		 834 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
835 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
836 MLX4_CMD_NATIVE);
837
838 if (!err && dev->caps.function != slave) {
839 /* set slave default_mac address */
840 MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
841 def_mac += slave << 8;
0eb62b93
RE		 842 /* if config MAC in DB use it */
843 if (priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac)
844 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
5cc914f1
MA		 845 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
846
847 /* get port type - currently only eth is enabled */
848 MLX4_GET(port_type, outbox->buf,
849 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
850
105c320f
JM		 851 /* No link sensing allowed */
852 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
853 /* set port type to currently operating port type */
854 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1
MA		 855
856 MLX4_PUT(outbox->buf, port_type,
857 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c
JM		 858
859 short_field = 1; /* slave max gids */
860 MLX4_PUT(outbox->buf, short_field,
861 QUERY_PORT_CUR_MAX_GID_OFFSET);
862
863 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
864 MLX4_PUT(outbox->buf, short_field,
865 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1
MA		 866 }
867
868 return err;
869}
870
6634961c
JM		 871int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
872 int *gid_tbl_len, int *pkey_tbl_len)
873{
874 struct mlx4_cmd_mailbox *mailbox;
875 u32 *outbox;
876 u16 field;
877 int err;
878
879 mailbox = mlx4_alloc_cmd_mailbox(dev);
880 if (IS_ERR(mailbox))
881 return PTR_ERR(mailbox);
882
883 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
884 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
885 MLX4_CMD_WRAPPED);
886 if (err)
887 goto out;
888
889 outbox = mailbox->buf;
890
891 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
892 *gid_tbl_len = field;
893
894 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
895 *pkey_tbl_len = field;
896
897out:
898 mlx4_free_cmd_mailbox(dev, mailbox);
899 return err;
900}
901EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
902
225c7b1f
RD		 903int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
904{
905 struct mlx4_cmd_mailbox *mailbox;
906 struct mlx4_icm_iter iter;
907 __be64 *pages;
908 int lg;
909 int nent = 0;
910 int i;
911 int err = 0;
912 int ts = 0, tc = 0;
913
914 mailbox = mlx4_alloc_cmd_mailbox(dev);
915 if (IS_ERR(mailbox))
916 return PTR_ERR(mailbox);
917 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
918 pages = mailbox->buf;
919
920 for (mlx4_icm_first(icm, &iter);
921 !mlx4_icm_last(&iter);
922 mlx4_icm_next(&iter)) {
923 /*
924 * We have to pass pages that are aligned to their
925 * size, so find the least significant 1 in the
926 * address or size and use that as our log2 size.
927 */
928 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
929 if (lg < MLX4_ICM_PAGE_SHIFT) {
930 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
931 MLX4_ICM_PAGE_SIZE,
932 (unsigned long long) mlx4_icm_addr(&iter),
933 mlx4_icm_size(&iter));
934 err = -EINVAL;
935 goto out;
936 }
937
938 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
939 if (virt != -1) {
940 pages[nent * 2] = cpu_to_be64(virt);
941 virt += 1 << lg;
942 }
943
944 pages[nent * 2 + 1] =
945 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
946 (lg - MLX4_ICM_PAGE_SHIFT));
947 ts += 1 << (lg - 10);
948 ++tc;
949
950 if (++nent == MLX4_MAILBOX_SIZE / 16) {
951 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 952 MLX4_CMD_TIME_CLASS_B,
953 MLX4_CMD_NATIVE);
225c7b1f
RD		 954 if (err)
955 goto out;
956 nent = 0;
957 }
958 }
959 }
960
961 if (nent)
f9baff50
JM		 962 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
963 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 964 if (err)
965 goto out;
966
967 switch (op) {
968 case MLX4_CMD_MAP_FA:
969 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
970 break;
971 case MLX4_CMD_MAP_ICM_AUX:
972 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
973 break;
974 case MLX4_CMD_MAP_ICM:
975 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
976 tc, ts, (unsigned long long) virt - (ts << 10));
977 break;
978 }
979
980out:
981 mlx4_free_cmd_mailbox(dev, mailbox);
982 return err;
983}
984
985int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
986{
987 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
988}
989
990int mlx4_UNMAP_FA(struct mlx4_dev *dev)
991{
f9baff50
JM		 992 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
993 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 994}
995
996
997int mlx4_RUN_FW(struct mlx4_dev *dev)
998{
f9baff50
JM		 999 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1000 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1001}
1002
1003int mlx4_QUERY_FW(struct mlx4_dev *dev)
1004{
1005 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1006 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1007 struct mlx4_cmd_mailbox *mailbox;
1008 u32 *outbox;
1009 int err = 0;
1010 u64 fw_ver;
fe40900f 1011 u16 cmd_if_rev;
225c7b1f
RD		 1012 u8 lg;
1013
1014#define QUERY_FW_OUT_SIZE 0x100
1015#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 1016#define QUERY_FW_PPF_ID 0x09
fe40900f 1017#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 1018#define QUERY_FW_MAX_CMD_OFFSET 0x0f
1019#define QUERY_FW_ERR_START_OFFSET 0x30
1020#define QUERY_FW_ERR_SIZE_OFFSET 0x38
1021#define QUERY_FW_ERR_BAR_OFFSET 0x3c
1022
1023#define QUERY_FW_SIZE_OFFSET 0x00
1024#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1025#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1026
5cc914f1
MA		 1027#define QUERY_FW_COMM_BASE_OFFSET 0x40
1028#define QUERY_FW_COMM_BAR_OFFSET 0x48
1029
ddd8a6c1
EE		 1030#define QUERY_FW_CLOCK_OFFSET 0x50
1031#define QUERY_FW_CLOCK_BAR 0x58
1032
225c7b1f
RD		 1033 mailbox = mlx4_alloc_cmd_mailbox(dev);
1034 if (IS_ERR(mailbox))
1035 return PTR_ERR(mailbox);
1036 outbox = mailbox->buf;
1037
1038 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 1039 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1040 if (err)
1041 goto out;
1042
1043 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1044 /*
3e1db334 1045 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1046 * version, so swap here.
1047 */
1048 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1049 ((fw_ver & 0xffff0000ull) >> 16) |
1050 ((fw_ver & 0x0000ffffull) << 16);
1051
752a50ca
JM		 1052 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1053 dev->caps.function = lg;
1054
b91cb3eb
JM		 1055 if (mlx4_is_slave(dev))
1056 goto out;
1057
5cc914f1 1058
fe40900f 1059 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1060 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1061 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 1062 mlx4_err(dev, "Installed FW has unsupported "
1063 "command interface revision %d.\n",
1064 cmd_if_rev);
1065 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1066 (int) (dev->caps.fw_ver >> 32),
1067 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1068 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 1069 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
1070 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1071 err = -ENODEV;
1072 goto out;
1073 }
1074
5ae2a7a8
RD		 1075 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1076 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1077
225c7b1f
RD		 1078 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1079 cmd->max_cmds = 1 << lg;
1080
fe40900f 1081 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1082 (int) (dev->caps.fw_ver >> 32),
1083 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1084 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1085 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1086
1087 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1088 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1089 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1090 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1091
1092 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1093 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1094
1095 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1096 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1097 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1098 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1099
5cc914f1
MA		 1100 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1101 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1102 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1103 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1104 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1105 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1106
ddd8a6c1
EE		 1107 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1108 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1109 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1110 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1111 fw->clock_bar, fw->clock_offset);
1112
225c7b1f
RD		 1113 /*
1114 * Round up number of system pages needed in case
1115 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1116 */
1117 fw->fw_pages =
1118 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1119 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1120
1121 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1122 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1123
1124out:
1125 mlx4_free_cmd_mailbox(dev, mailbox);
1126 return err;
1127}
1128
b91cb3eb
JM		 1129int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1130 struct mlx4_vhcr *vhcr,
1131 struct mlx4_cmd_mailbox *inbox,
1132 struct mlx4_cmd_mailbox *outbox,
1133 struct mlx4_cmd_info *cmd)
1134{
1135 u8 *outbuf;
1136 int err;
1137
1138 outbuf = outbox->buf;
1139 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1140 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1141 if (err)
1142 return err;
1143
752a50ca
JM		 1144 /* for slaves, set pci PPF ID to invalid and zero out everything
1145 * else except FW version */
b91cb3eb
JM		 1146 outbuf[0] = outbuf[1] = 0;
1147 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1148 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1149
b91cb3eb
JM		 1150 return 0;
1151}
1152
225c7b1f
RD		 1153static void get_board_id(void *vsd, char *board_id)
1154{
1155 int i;
1156
1157#define VSD_OFFSET_SIG1 0x00
1158#define VSD_OFFSET_SIG2 0xde
1159#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1160#define VSD_OFFSET_TS_BOARD_ID 0x20
1161
1162#define VSD_SIGNATURE_TOPSPIN 0x5ad
1163
1164 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1165
1166 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1167 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1168 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1169 } else {
1170 /*
1171 * The board ID is a string but the firmware byte
1172 * swaps each 4-byte word before passing it back to
1173 * us. Therefore we need to swab it before printing.
1174 */
1175 for (i = 0; i < 4; ++i)
1176 ((u32 *) board_id)[i] =
1177 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1178 }
1179}
1180
1181int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1182{
1183 struct mlx4_cmd_mailbox *mailbox;
1184 u32 *outbox;
1185 int err;
1186
1187#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1188#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1189#define QUERY_ADAPTER_VSD_OFFSET 0x20
1190
1191 mailbox = mlx4_alloc_cmd_mailbox(dev);
1192 if (IS_ERR(mailbox))
1193 return PTR_ERR(mailbox);
1194 outbox = mailbox->buf;
1195
1196 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1197 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1198 if (err)
1199 goto out;
1200
225c7b1f
RD		 1201 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1202
1203 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1204 adapter->board_id);
1205
1206out:
1207 mlx4_free_cmd_mailbox(dev, mailbox);
1208 return err;
1209}
1210
1211int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1212{
1213 struct mlx4_cmd_mailbox *mailbox;
1214 __be32 *inbox;
1215 int err;
1216
1217#define INIT_HCA_IN_SIZE 0x200
1218#define INIT_HCA_VERSION_OFFSET 0x000
1219#define INIT_HCA_VERSION 2
c57e20dc 1220#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 1221#define INIT_HCA_FLAGS_OFFSET 0x014
1222#define INIT_HCA_QPC_OFFSET 0x020
1223#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1224#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1225#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1226#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1227#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1228#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1229#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
225c7b1f
RD		 1230#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1231#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1232#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1233#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1234#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1235#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1236#define INIT_HCA_MCAST_OFFSET 0x0c0
1237#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1238#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1239#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1240#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1241#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1242#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1243#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1244#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1245#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1246#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1247#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1248#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1249#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1250#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1251#define INIT_HCA_TPT_OFFSET 0x0f0
1252#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
e448834e 1253#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
225c7b1f
RD		 1254#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1255#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1256#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1257#define INIT_HCA_UAR_OFFSET 0x120
1258#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1259#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1260
1261 mailbox = mlx4_alloc_cmd_mailbox(dev);
1262 if (IS_ERR(mailbox))
1263 return PTR_ERR(mailbox);
1264 inbox = mailbox->buf;
1265
1266 memset(inbox, 0, INIT_HCA_IN_SIZE);
1267
1268 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1269
c57e20dc
EC		 1270 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1271 (ilog2(cache_line_size()) - 4) << 5;
1272
225c7b1f
RD		 1273#if defined(__LITTLE_ENDIAN)
1274 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1275#elif defined(__BIG_ENDIAN)
1276 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1277#else
1278#error Host endianness not defined
1279#endif
1280 /* Check port for UD address vector: */
1281 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1282
8ff095ec
EC		 1283 /* Enable IPoIB checksumming if we can: */
1284 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1285 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1286
51f5f0ee
JM		 1287 /* Enable QoS support if module parameter set */
1288 if (enable_qos)
1289 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1290
f2a3f6a3
OG		 1291 /* enable counters */
1292 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1293 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1294
08ff3235
OG		 1295 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1296 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1297 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1298 dev->caps.eqe_size = 64;
1299 dev->caps.eqe_factor = 1;
1300 } else {
1301 dev->caps.eqe_size = 32;
1302 dev->caps.eqe_factor = 0;
1303 }
1304
1305 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1306 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1307 dev->caps.cqe_size = 64;
1308 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1309 } else {
1310 dev->caps.cqe_size = 32;
1311 }
1312
225c7b1f
RD		 1313 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1314
1315 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1316 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1317 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1318 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1319 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1320 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1321 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1322 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1323 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1324 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1325 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1326 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1327
0ff1fb65
HHZ		 1328 /* steering attributes */
1329 if (dev->caps.steering_mode ==
1330 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1331 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1332 cpu_to_be32(1 <<
1333 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1334
1335 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1336 MLX4_PUT(inbox, param->log_mc_entry_sz,
1337 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1338 MLX4_PUT(inbox, param->log_mc_table_sz,
1339 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1340 /* Enable Ethernet flow steering
1341 * with udp unicast and tcp unicast
1342 */
23537b73 1343 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1344 INIT_HCA_FS_ETH_BITS_OFFSET);
1345 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1346 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1347 /* Enable IPoIB flow steering
1348 * with udp unicast and tcp unicast
1349 */
23537b73 1350 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1351 INIT_HCA_FS_IB_BITS_OFFSET);
1352 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1353 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1354 } else {
1355 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1356 MLX4_PUT(inbox, param->log_mc_entry_sz,
1357 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1358 MLX4_PUT(inbox, param->log_mc_hash_sz,
1359 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1360 MLX4_PUT(inbox, param->log_mc_table_sz,
1361 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1362 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1363 MLX4_PUT(inbox, (u8) (1 << 3),
1364 INIT_HCA_UC_STEERING_OFFSET);
1365 }
225c7b1f
RD		 1366
1367 /* TPT attributes */
1368
1369 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1370 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
225c7b1f
RD		 1371 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1372 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1373 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1374
1375 /* UAR attributes */
1376
ab9c17a0 1377 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1378 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1379
f9baff50
JM		 1380 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1381 MLX4_CMD_NATIVE);
225c7b1f
RD		 1382
1383 if (err)
1384 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1385
1386 mlx4_free_cmd_mailbox(dev, mailbox);
1387 return err;
1388}
1389
ab9c17a0
JM		 1390int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1391 struct mlx4_init_hca_param *param)
1392{
1393 struct mlx4_cmd_mailbox *mailbox;
1394 __be32 *outbox;
7b8157be 1395 u32 dword_field;
ab9c17a0 1396 int err;
08ff3235 1397 u8 byte_field;
ab9c17a0
JM		 1398
1399#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
ddd8a6c1 1400#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
ab9c17a0
JM		 1401
1402 mailbox = mlx4_alloc_cmd_mailbox(dev);
1403 if (IS_ERR(mailbox))
1404 return PTR_ERR(mailbox);
1405 outbox = mailbox->buf;
1406
1407 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1408 MLX4_CMD_QUERY_HCA,
1409 MLX4_CMD_TIME_CLASS_B,
1410 !mlx4_is_slave(dev));
1411 if (err)
1412 goto out;
1413
1414 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
ddd8a6c1 1415 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
ab9c17a0
JM		 1416
1417 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1418
1419 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1420 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1421 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1422 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1423 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1424 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1425 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1426 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1427 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1428 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1429 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1430 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1431
7b8157be
JM		 1432 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1433 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1434 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1435 } else {
1436 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1437 if (byte_field & 0x8)
1438 param->steering_mode = MLX4_STEERING_MODE_B0;
1439 else
1440 param->steering_mode = MLX4_STEERING_MODE_A0;
1441 }
0ff1fb65 1442 /* steering attributes */
7b8157be 1443 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
0ff1fb65
HHZ		 1444 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1445 MLX4_GET(param->log_mc_entry_sz, outbox,
1446 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1447 MLX4_GET(param->log_mc_table_sz, outbox,
1448 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1449 } else {
1450 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1451 MLX4_GET(param->log_mc_entry_sz, outbox,
1452 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1453 MLX4_GET(param->log_mc_hash_sz, outbox,
1454 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1455 MLX4_GET(param->log_mc_table_sz, outbox,
1456 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1457 }
ab9c17a0 1458
08ff3235
OG		 1459 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1460 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1461 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1462 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1463 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1464 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1465
ab9c17a0
JM		 1466 /* TPT attributes */
1467
1468 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1469 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
ab9c17a0
JM		 1470 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1471 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1472 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1473
1474 /* UAR attributes */
1475
1476 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1477 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1478
1479out:
1480 mlx4_free_cmd_mailbox(dev, mailbox);
1481
1482 return err;
1483}
1484
980e9001
JM		 1485/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1486 * and real QP0 are active, so that the paravirtualized QP0 is ready
1487 * to operate */
1488static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1489{
1490 struct mlx4_priv *priv = mlx4_priv(dev);
1491 /* irrelevant if not infiniband */
1492 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1493 priv->mfunc.master.qp0_state[port].qp0_active)
1494 return 1;
1495 return 0;
1496}
1497
5cc914f1
MA		 1498int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1499 struct mlx4_vhcr *vhcr,
1500 struct mlx4_cmd_mailbox *inbox,
1501 struct mlx4_cmd_mailbox *outbox,
1502 struct mlx4_cmd_info *cmd)
1503{
1504 struct mlx4_priv *priv = mlx4_priv(dev);
1505 int port = vhcr->in_modifier;
1506 int err;
1507
1508 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1509 return 0;
1510
980e9001
JM		 1511 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1512 /* Enable port only if it was previously disabled */
1513 if (!priv->mfunc.master.init_port_ref[port]) {
1514 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1515 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1516 if (err)
1517 return err;
1518 }
1519 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1520 } else {
1521 if (slave == mlx4_master_func_num(dev)) {
1522 if (check_qp0_state(dev, slave, port) &&
1523 !priv->mfunc.master.qp0_state[port].port_active) {
1524 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1525 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1526 if (err)
1527 return err;
1528 priv->mfunc.master.qp0_state[port].port_active = 1;
1529 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1530 }
1531 } else
1532 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1533 }
1534 ++priv->mfunc.master.init_port_ref[port];
1535 return 0;
1536}
1537
5ae2a7a8 1538int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1539{
1540 struct mlx4_cmd_mailbox *mailbox;
1541 u32 *inbox;
1542 int err;
1543 u32 flags;
5ae2a7a8 1544 u16 field;
225c7b1f 1545
5ae2a7a8 1546 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1547#define INIT_PORT_IN_SIZE 256
1548#define INIT_PORT_FLAGS_OFFSET 0x00
1549#define INIT_PORT_FLAG_SIG (1 << 18)
1550#define INIT_PORT_FLAG_NG (1 << 17)
1551#define INIT_PORT_FLAG_G0 (1 << 16)
1552#define INIT_PORT_VL_SHIFT 4
1553#define INIT_PORT_PORT_WIDTH_SHIFT 8
1554#define INIT_PORT_MTU_OFFSET 0x04
1555#define INIT_PORT_MAX_GID_OFFSET 0x06
1556#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1557#define INIT_PORT_GUID0_OFFSET 0x10
1558#define INIT_PORT_NODE_GUID_OFFSET 0x18
1559#define INIT_PORT_SI_GUID_OFFSET 0x20
1560
5ae2a7a8
RD		 1561 mailbox = mlx4_alloc_cmd_mailbox(dev);
1562 if (IS_ERR(mailbox))
1563 return PTR_ERR(mailbox);
1564 inbox = mailbox->buf;
225c7b1f 1565
5ae2a7a8 1566 memset(inbox, 0, INIT_PORT_IN_SIZE);
225c7b1f 1567
5ae2a7a8
RD		 1568 flags = 0;
1569 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1570 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1571 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1572
b79acb49 1573 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1574 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1575 field = dev->caps.gid_table_len[port];
1576 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1577 field = dev->caps.pkey_table_len[port];
1578 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1579
5ae2a7a8 1580 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1581 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1582
5ae2a7a8
RD		 1583 mlx4_free_cmd_mailbox(dev, mailbox);
1584 } else
1585 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1586 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1587
1588 return err;
1589}
1590EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1591
5cc914f1
MA		 1592int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1593 struct mlx4_vhcr *vhcr,
1594 struct mlx4_cmd_mailbox *inbox,
1595 struct mlx4_cmd_mailbox *outbox,
1596 struct mlx4_cmd_info *cmd)
1597{
1598 struct mlx4_priv *priv = mlx4_priv(dev);
1599 int port = vhcr->in_modifier;
1600 int err;
1601
1602 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1603 (1 << port)))
1604 return 0;
1605
980e9001
JM		 1606 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1607 if (priv->mfunc.master.init_port_ref[port] == 1) {
1608 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1609 1000, MLX4_CMD_NATIVE);
1610 if (err)
1611 return err;
1612 }
1613 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1614 } else {
1615 /* infiniband port */
1616 if (slave == mlx4_master_func_num(dev)) {
1617 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1618 priv->mfunc.master.qp0_state[port].port_active) {
1619 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1620 1000, MLX4_CMD_NATIVE);
1621 if (err)
1622 return err;
1623 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1624 priv->mfunc.master.qp0_state[port].port_active = 0;
1625 }
1626 } else
1627 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 1628 }
5cc914f1
MA		 1629 --priv->mfunc.master.init_port_ref[port];
1630 return 0;
1631}
1632
225c7b1f
RD		 1633int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1634{
f9baff50
JM		 1635 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1636 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1637}
1638EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1639
1640int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1641{
f9baff50
JM		 1642 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1643 MLX4_CMD_NATIVE);
225c7b1f
RD		 1644}
1645
1646int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1647{
1648 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1649 MLX4_CMD_SET_ICM_SIZE,
f9baff50 1650 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1651 if (ret)
1652 return ret;
1653
1654 /*
1655 * Round up number of system pages needed in case
1656 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1657 */
1658 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1659 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1660
1661 return 0;
1662}
1663
1664int mlx4_NOP(struct mlx4_dev *dev)
1665{
1666 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 1667 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 1668}
14c07b13
YP		 1669
1670#define MLX4_WOL_SETUP_MODE (5 << 28)
1671int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1672{
1673 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1674
1675 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 1676 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1677 MLX4_CMD_NATIVE);
14c07b13
YP		 1678}
1679EXPORT_SYMBOL_GPL(mlx4_wol_read);
1680
1681int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1682{
1683 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1684
1685 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 1686 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 1687}
1688EXPORT_SYMBOL_GPL(mlx4_wol_write);
Linux 6.x block layer and io_uring tree(s)