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NVMe: Use an IDA to allocate minor numbers
[linux-2.6-block.git] / drivers / block / nvme.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/nvme.h>
20#include <linux/bio.h>
8de05535 21#include <linux/bitops.h>
b60503ba 22#include <linux/blkdev.h>
fd63e9ce 23#include <linux/delay.h>
b60503ba
MW		 24#include <linux/errno.h>
25#include <linux/fs.h>
26#include <linux/genhd.h>
5aff9382 27#include <linux/idr.h>
b60503ba
MW		 28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/kdev_t.h>
1fa6aead 32#include <linux/kthread.h>
b60503ba
MW		 33#include <linux/kernel.h>
34#include <linux/mm.h>
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/pci.h>
be7b6275 38#include <linux/poison.h>
b60503ba
MW		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/version.h>
43
44#define NVME_Q_DEPTH 1024
45#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
46#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
47#define NVME_MINORS 64
e85248e5
MW		 48#define IO_TIMEOUT (5 * HZ)
49#define ADMIN_TIMEOUT (60 * HZ)
b60503ba
MW		 50
51static int nvme_major;
52module_param(nvme_major, int, 0);
53
58ffacb5
MW		 54static int use_threaded_interrupts;
55module_param(use_threaded_interrupts, int, 0);
56
1fa6aead
MW		 57static DEFINE_SPINLOCK(dev_list_lock);
58static LIST_HEAD(dev_list);
59static struct task_struct *nvme_thread;
60
b60503ba
MW		 61/*
62 * Represents an NVM Express device. Each nvme_dev is a PCI function.
63 */
64struct nvme_dev {
1fa6aead 65 struct list_head node;
b60503ba
MW		 66 struct nvme_queue **queues;
67 u32 __iomem *dbs;
68 struct pci_dev *pci_dev;
091b6092 69 struct dma_pool *prp_page_pool;
99802a7a 70 struct dma_pool *prp_small_pool;
b60503ba
MW		 71 int instance;
72 int queue_count;
73 u32 ctrl_config;
74 struct msix_entry *entry;
75 struct nvme_bar __iomem *bar;
76 struct list_head namespaces;
51814232
MW		 77 char serial[20];
78 char model[40];
79 char firmware_rev[8];
b60503ba
MW		 80};
81
82/*
83 * An NVM Express namespace is equivalent to a SCSI LUN
84 */
85struct nvme_ns {
86 struct list_head list;
87
88 struct nvme_dev *dev;
89 struct request_queue *queue;
90 struct gendisk *disk;
91
92 int ns_id;
93 int lba_shift;
94};
95
96/*
97 * An NVM Express queue. Each device has at least two (one for admin
98 * commands and one for I/O commands).
99 */
100struct nvme_queue {
101 struct device *q_dmadev;
091b6092 102 struct nvme_dev *dev;
b60503ba
MW		 103 spinlock_t q_lock;
104 struct nvme_command *sq_cmds;
105 volatile struct nvme_completion *cqes;
106 dma_addr_t sq_dma_addr;
107 dma_addr_t cq_dma_addr;
108 wait_queue_head_t sq_full;
1fa6aead 109 wait_queue_t sq_cong_wait;
b60503ba
MW		 110 struct bio_list sq_cong;
111 u32 __iomem *q_db;
112 u16 q_depth;
113 u16 cq_vector;
114 u16 sq_head;
115 u16 sq_tail;
116 u16 cq_head;
82123460 117 u16 cq_phase;
b60503ba
MW		 118 unsigned long cmdid_data[];
119};
120
121/*
122 * Check we didin't inadvertently grow the command struct
123 */
124static inline void _nvme_check_size(void)
125{
126 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
132 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
135}
136
e85248e5
MW		 137struct nvme_cmd_info {
138 unsigned long ctx;
139 unsigned long timeout;
140};
141
142static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
143{
144 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
145}
146
b60503ba 147/**
714a7a22
MW		 148 * alloc_cmdid() - Allocate a Command ID
149 * @nvmeq: The queue that will be used for this command
150 * @ctx: A pointer that will be passed to the handler
151 * @handler: The ID of the handler to call
b60503ba
MW		 152 *
153 * Allocate a Command ID for a queue. The data passed in will
154 * be passed to the completion handler. This is implemented by using
155 * the bottom two bits of the ctx pointer to store the handler ID.
156 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
157 * We can change this if it becomes a problem.
158 */
e85248e5
MW		 159static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
160 unsigned timeout)
b60503ba 161{
e6d15f79 162 int depth = nvmeq->q_depth - 1;
e85248e5 163 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba
MW		 164 int cmdid;
165
166 BUG_ON((unsigned long)ctx & 3);
167
168 do {
169 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
170 if (cmdid >= depth)
171 return -EBUSY;
172 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
173
e85248e5
MW		 174 info[cmdid].ctx = (unsigned long)ctx | handler;
175 info[cmdid].timeout = jiffies + timeout;
b60503ba
MW		 176 return cmdid;
177}
178
179static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
e85248e5 180 int handler, unsigned timeout)
b60503ba
MW		 181{
182 int cmdid;
183 wait_event_killable(nvmeq->sq_full,
e85248e5 184 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
b60503ba
MW		 185 return (cmdid < 0) ? -EINTR : cmdid;
186}
187
fa922821
MW		 188/*
189 * If you need more than four handlers, you'll need to change how
be7b6275
MW		 190 * alloc_cmdid and nvme_process_cq work. Consider using a special
191 * CMD_CTX value instead, if that works for your situation.
b60503ba
MW		 192 */
193enum {
194 sync_completion_id = 0,
195 bio_completion_id,
196};
197
00df5cb4 198/* Special values must be a multiple of 4, and less than 0x1000 */
be7b6275 199#define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id)
d2d87034
MW		 200#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
201#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
202#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
00df5cb4 203#define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
be7b6275 204
b60503ba
MW		 205static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
206{
207 unsigned long data;
e85248e5 208 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 209
e85248e5 210 if (cmdid >= nvmeq->q_depth)
48e3d398 211 return CMD_CTX_INVALID;
e85248e5
MW		 212 data = info[cmdid].ctx;
213 info[cmdid].ctx = CMD_CTX_COMPLETED;
b60503ba
MW		 214 clear_bit(cmdid, nvmeq->cmdid_data);
215 wake_up(&nvmeq->sq_full);
216 return data;
217}
218
21075bde 219static unsigned long cancel_cmdid(struct nvme_queue *nvmeq, int cmdid)
3c0cf138 220{
21075bde 221 unsigned long data;
e85248e5 222 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
21075bde 223 data = info[cmdid].ctx;
e85248e5 224 info[cmdid].ctx = CMD_CTX_CANCELLED;
21075bde 225 return data;
3c0cf138
MW		 226}
227
b60503ba
MW		 228static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
229{
9ecdc946 230 return ns->dev->queues[get_cpu() + 1];
b60503ba
MW		 231}
232
233static void put_nvmeq(struct nvme_queue *nvmeq)
234{
1b23484b 235 put_cpu();
b60503ba
MW		 236}
237
238/**
714a7a22 239 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 240 * @nvmeq: The queue to use
241 * @cmd: The command to send
242 *
243 * Safe to use from interrupt context
244 */
245static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
246{
247 unsigned long flags;
248 u16 tail;
b60503ba
MW		 249 spin_lock_irqsave(&nvmeq->q_lock, flags);
250 tail = nvmeq->sq_tail;
251 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 252 if (++tail == nvmeq->q_depth)
253 tail = 0;
7547881d 254 writel(tail, nvmeq->q_db);
b60503ba
MW		 255 nvmeq->sq_tail = tail;
256 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
257
258 return 0;
259}
260
e025344c
SMM		 261struct nvme_prps {
262 int npages;
263 dma_addr_t first_dma;
264 __le64 *list[0];
265};
266
d567760c 267static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
e025344c
SMM		 268{
269 const int last_prp = PAGE_SIZE / 8 - 1;
270 int i;
271 dma_addr_t prp_dma;
272
273 if (!prps)
274 return;
275
276 prp_dma = prps->first_dma;
99802a7a
MW		 277
278 if (prps->npages == 0)
279 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
e025344c
SMM		 280 for (i = 0; i < prps->npages; i++) {
281 __le64 *prp_list = prps->list[i];
282 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
091b6092 283 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
e025344c
SMM		 284 prp_dma = next_prp_dma;
285 }
286 kfree(prps);
287}
288
d534df3c 289struct nvme_bio {
b60503ba
MW		 290 struct bio *bio;
291 int nents;
e025344c 292 struct nvme_prps *prps;
b60503ba
MW		 293 struct scatterlist sg[0];
294};
295
296/* XXX: use a mempool */
d534df3c 297static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
b60503ba 298{
d534df3c 299 return kzalloc(sizeof(struct nvme_bio) +
b60503ba
MW		 300 sizeof(struct scatterlist) * nseg, gfp);
301}
302
d534df3c 303static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
b60503ba 304{
d567760c 305 nvme_free_prps(nvmeq->dev, nbio->prps);
d534df3c 306 kfree(nbio);
b60503ba
MW		 307}
308
309static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
310 struct nvme_completion *cqe)
311{
d534df3c
MW		 312 struct nvme_bio *nbio = ctx;
313 struct bio *bio = nbio->bio;
b60503ba
MW		 314 u16 status = le16_to_cpup(&cqe->status) >> 1;
315
d534df3c 316 dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
b60503ba 317 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
d534df3c 318 free_nbio(nvmeq, nbio);
09a58f53 319 if (status) {
1ad2f893 320 bio_endio(bio, -EIO);
09a58f53 321 } else if (bio->bi_vcnt > bio->bi_idx) {
1ad2f893
MW		 322 bio_list_add(&nvmeq->sq_cong, bio);
323 wake_up_process(nvme_thread);
324 } else {
325 bio_endio(bio, 0);
326 }
b60503ba
MW		 327}
328
ff22b54f 329/* length is in bytes */
d567760c 330static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
e025344c 331 struct nvme_common_command *cmd,
ff22b54f
MW		 332 struct scatterlist *sg, int length)
333{
99802a7a 334 struct dma_pool *pool;
ff22b54f
MW		 335 int dma_len = sg_dma_len(sg);
336 u64 dma_addr = sg_dma_address(sg);
337 int offset = offset_in_page(dma_addr);
e025344c
SMM		 338 __le64 *prp_list;
339 dma_addr_t prp_dma;
340 int nprps, npages, i, prp_page;
341 struct nvme_prps *prps = NULL;
ff22b54f
MW		 342
343 cmd->prp1 = cpu_to_le64(dma_addr);
344 length -= (PAGE_SIZE - offset);
345 if (length <= 0)
e025344c 346 return prps;
ff22b54f
MW		 347
348 dma_len -= (PAGE_SIZE - offset);
349 if (dma_len) {
350 dma_addr += (PAGE_SIZE - offset);
351 } else {
352 sg = sg_next(sg);
353 dma_addr = sg_dma_address(sg);
354 dma_len = sg_dma_len(sg);
355 }
356
357 if (length <= PAGE_SIZE) {
358 cmd->prp2 = cpu_to_le64(dma_addr);
e025344c
SMM		 359 return prps;
360 }
361
362 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
363 npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
364 prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
e025344c 365 prp_page = 0;
99802a7a
MW		 366 if (nprps <= (256 / 8)) {
367 pool = dev->prp_small_pool;
368 prps->npages = 0;
369 } else {
370 pool = dev->prp_page_pool;
371 prps->npages = npages;
372 }
373
374 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
e025344c
SMM		 375 prps->list[prp_page++] = prp_list;
376 prps->first_dma = prp_dma;
377 cmd->prp2 = cpu_to_le64(prp_dma);
378 i = 0;
379 for (;;) {
7523d834 380 if (i == PAGE_SIZE / 8) {
e025344c 381 __le64 *old_prp_list = prp_list;
99802a7a 382 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
e025344c 383 prps->list[prp_page++] = prp_list;
7523d834
MW		 384 prp_list[0] = old_prp_list[i - 1];
385 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
386 i = 1;
e025344c
SMM		 387 }
388 prp_list[i++] = cpu_to_le64(dma_addr);
389 dma_len -= PAGE_SIZE;
390 dma_addr += PAGE_SIZE;
391 length -= PAGE_SIZE;
392 if (length <= 0)
393 break;
394 if (dma_len > 0)
395 continue;
396 BUG_ON(dma_len < 0);
397 sg = sg_next(sg);
398 dma_addr = sg_dma_address(sg);
399 dma_len = sg_dma_len(sg);
ff22b54f
MW		 400 }
401
e025344c 402 return prps;
ff22b54f
MW		 403}
404
1ad2f893
MW		 405/* NVMe scatterlists require no holes in the virtual address */
406#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
407 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
408
d534df3c 409static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
b60503ba
MW		 410 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
411{
76830840
MW		 412 struct bio_vec *bvec, *bvprv = NULL;
413 struct scatterlist *sg = NULL;
1ad2f893 414 int i, old_idx, length = 0, nsegs = 0;
b60503ba 415
76830840 416 sg_init_table(nbio->sg, psegs);
1ad2f893 417 old_idx = bio->bi_idx;
b60503ba 418 bio_for_each_segment(bvec, bio, i) {
76830840
MW		 419 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
420 sg->length += bvec->bv_len;
421 } else {
1ad2f893
MW		 422 if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
423 break;
76830840
MW		 424 sg = sg ? sg + 1 : nbio->sg;
425 sg_set_page(sg, bvec->bv_page, bvec->bv_len,
426 bvec->bv_offset);
427 nsegs++;
428 }
1ad2f893 429 length += bvec->bv_len;
76830840 430 bvprv = bvec;
b60503ba 431 }
1ad2f893 432 bio->bi_idx = i;
d534df3c 433 nbio->nents = nsegs;
76830840 434 sg_mark_end(sg);
1ad2f893
MW		 435 if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
436 bio->bi_idx = old_idx;
437 return -ENOMEM;
438 }
439 return length;
b60503ba
MW		 440}
441
00df5cb4
MW		 442static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
443 int cmdid)
444{
445 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
446
447 memset(cmnd, 0, sizeof(*cmnd));
448 cmnd->common.opcode = nvme_cmd_flush;
449 cmnd->common.command_id = cmdid;
450 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
451
452 if (++nvmeq->sq_tail == nvmeq->q_depth)
453 nvmeq->sq_tail = 0;
454 writel(nvmeq->sq_tail, nvmeq->q_db);
455
456 return 0;
457}
458
459static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
460{
461 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
462 sync_completion_id, IO_TIMEOUT);
463 if (unlikely(cmdid < 0))
464 return cmdid;
465
466 return nvme_submit_flush(nvmeq, ns, cmdid);
467}
468
b60503ba
MW		 469static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
470 struct bio *bio)
471{
ff22b54f 472 struct nvme_command *cmnd;
d534df3c 473 struct nvme_bio *nbio;
b60503ba 474 enum dma_data_direction dma_dir;
1ad2f893 475 int cmdid, length, result = -ENOMEM;
b60503ba
MW		 476 u16 control;
477 u32 dsmgmt;
b60503ba
MW		 478 int psegs = bio_phys_segments(ns->queue, bio);
479
00df5cb4
MW		 480 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
481 result = nvme_submit_flush_data(nvmeq, ns);
482 if (result)
483 return result;
484 }
485
eeee3226 486 nbio = alloc_nbio(psegs, GFP_ATOMIC);
d534df3c 487 if (!nbio)
eeee3226 488 goto nomem;
d534df3c 489 nbio->bio = bio;
b60503ba 490
eeee3226 491 result = -EBUSY;
d534df3c 492 cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
b60503ba 493 if (unlikely(cmdid < 0))
d534df3c 494 goto free_nbio;
b60503ba 495
00df5cb4
MW		 496 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
497 return nvme_submit_flush(nvmeq, ns, cmdid);
498
b60503ba
MW		 499 control = 0;
500 if (bio->bi_rw & REQ_FUA)
501 control |= NVME_RW_FUA;
502 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
503 control |= NVME_RW_LR;
504
505 dsmgmt = 0;
506 if (bio->bi_rw & REQ_RAHEAD)
507 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
508
ff22b54f 509 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b60503ba 510
b8deb62c 511 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 512 if (bio_data_dir(bio)) {
ff22b54f 513 cmnd->rw.opcode = nvme_cmd_write;
b60503ba
MW		 514 dma_dir = DMA_TO_DEVICE;
515 } else {
ff22b54f 516 cmnd->rw.opcode = nvme_cmd_read;
b60503ba
MW		 517 dma_dir = DMA_FROM_DEVICE;
518 }
519
1ad2f893
MW		 520 result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
521 if (result < 0)
eeee3226 522 goto free_nbio;
1ad2f893 523 length = result;
b60503ba 524
ff22b54f
MW		 525 cmnd->rw.command_id = cmdid;
526 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
d567760c 527 nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
1ad2f893 528 length);
ff22b54f 529 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
1ad2f893 530 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
ff22b54f
MW		 531 cmnd->rw.control = cpu_to_le16(control);
532 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 533
d8ee9d69
MW		 534 bio->bi_sector += length >> 9;
535
b60503ba
MW		 536 if (++nvmeq->sq_tail == nvmeq->q_depth)
537 nvmeq->sq_tail = 0;
7547881d 538 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 539
1974b1ae
MW		 540 return 0;
541
d534df3c
MW		 542 free_nbio:
543 free_nbio(nvmeq, nbio);
eeee3226
MW		 544 nomem:
545 return result;
b60503ba
MW		 546}
547
548/*
549 * NB: return value of non-zero would mean that we were a stacking driver.
550 * make_request must always succeed.
551 */
552static int nvme_make_request(struct request_queue *q, struct bio *bio)
553{
554 struct nvme_ns *ns = q->queuedata;
555 struct nvme_queue *nvmeq = get_nvmeq(ns);
eeee3226
MW		 556 int result = -EBUSY;
557
558 spin_lock_irq(&nvmeq->q_lock);
559 if (bio_list_empty(&nvmeq->sq_cong))
560 result = nvme_submit_bio_queue(nvmeq, ns, bio);
561 if (unlikely(result)) {
562 if (bio_list_empty(&nvmeq->sq_cong))
563 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
b60503ba
MW		 564 bio_list_add(&nvmeq->sq_cong, bio);
565 }
eeee3226
MW		 566
567 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 568 put_nvmeq(nvmeq);
569
570 return 0;
571}
572
573struct sync_cmd_info {
574 struct task_struct *task;
575 u32 result;
576 int status;
577};
578
579static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
580 struct nvme_completion *cqe)
581{
582 struct sync_cmd_info *cmdinfo = ctx;
c4270559 583 if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
be7b6275 584 return;
00df5cb4
MW		 585 if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
586 return;
b36235df
MW		 587 if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
588 dev_warn(nvmeq->q_dmadev,
589 "completed id %d twice on queue %d\n",
590 cqe->command_id, le16_to_cpup(&cqe->sq_id));
591 return;
592 }
48e3d398
MW		 593 if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
594 dev_warn(nvmeq->q_dmadev,
595 "invalid id %d completed on queue %d\n",
596 cqe->command_id, le16_to_cpup(&cqe->sq_id));
597 return;
598 }
b60503ba
MW		 599 cmdinfo->result = le32_to_cpup(&cqe->result);
600 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
601 wake_up_process(cmdinfo->task);
602}
603
604typedef void (*completion_fn)(struct nvme_queue *, void *,
605 struct nvme_completion *);
606
8de05535
MW		 607static const completion_fn nvme_completions[4] = {
608 [sync_completion_id] = sync_completion,
609 [bio_completion_id] = bio_completion,
610};
611
b60503ba
MW		 612static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
613{
82123460 614 u16 head, phase;
b60503ba 615
b60503ba 616 head = nvmeq->cq_head;
82123460 617 phase = nvmeq->cq_phase;
b60503ba
MW		 618
619 for (;;) {
620 unsigned long data;
621 void *ptr;
622 unsigned char handler;
623 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 624 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 625 break;
626 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
627 if (++head == nvmeq->q_depth) {
628 head = 0;
82123460 629 phase = !phase;
b60503ba
MW		 630 }
631
632 data = free_cmdid(nvmeq, cqe.command_id);
633 handler = data & 3;
634 ptr = (void *)(data & ~3UL);
8de05535 635 nvme_completions[handler](nvmeq, ptr, &cqe);
b60503ba
MW		 636 }
637
638 /* If the controller ignores the cq head doorbell and continuously
639 * writes to the queue, it is theoretically possible to wrap around
640 * the queue twice and mistakenly return IRQ_NONE. Linux only
641 * requires that 0.1% of your interrupts are handled, so this isn't
642 * a big problem.
643 */
82123460 644 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
b60503ba
MW		 645 return IRQ_NONE;
646
647 writel(head, nvmeq->q_db + 1);
648 nvmeq->cq_head = head;
82123460 649 nvmeq->cq_phase = phase;
b60503ba
MW		 650
651 return IRQ_HANDLED;
652}
653
654static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 655{
656 irqreturn_t result;
657 struct nvme_queue *nvmeq = data;
658 spin_lock(&nvmeq->q_lock);
659 result = nvme_process_cq(nvmeq);
660 spin_unlock(&nvmeq->q_lock);
661 return result;
662}
663
664static irqreturn_t nvme_irq_check(int irq, void *data)
665{
666 struct nvme_queue *nvmeq = data;
667 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
668 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
669 return IRQ_NONE;
670 return IRQ_WAKE_THREAD;
671}
672
3c0cf138
MW		 673static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
674{
675 spin_lock_irq(&nvmeq->q_lock);
21075bde 676 cancel_cmdid(nvmeq, cmdid);
3c0cf138
MW		 677 spin_unlock_irq(&nvmeq->q_lock);
678}
679
b60503ba
MW		 680/*
681 * Returns 0 on success. If the result is negative, it's a Linux error code;
682 * if the result is positive, it's an NVM Express status code
683 */
3c0cf138 684static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
e85248e5 685 struct nvme_command *cmd, u32 *result, unsigned timeout)
b60503ba
MW		 686{
687 int cmdid;
688 struct sync_cmd_info cmdinfo;
689
690 cmdinfo.task = current;
691 cmdinfo.status = -EINTR;
692
e85248e5
MW		 693 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
694 timeout);
b60503ba
MW		 695 if (cmdid < 0)
696 return cmdid;
697 cmd->common.command_id = cmdid;
698
3c0cf138
MW		 699 set_current_state(TASK_KILLABLE);
700 nvme_submit_cmd(nvmeq, cmd);
b60503ba
MW		 701 schedule();
702
3c0cf138
MW		 703 if (cmdinfo.status == -EINTR) {
704 nvme_abort_command(nvmeq, cmdid);
705 return -EINTR;
706 }
707
b60503ba
MW		 708 if (result)
709 *result = cmdinfo.result;
710
711 return cmdinfo.status;
712}
713
714static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
715 u32 *result)
716{
e85248e5 717 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 718}
719
720static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
721{
722 int status;
723 struct nvme_command c;
724
725 memset(&c, 0, sizeof(c));
726 c.delete_queue.opcode = opcode;
727 c.delete_queue.qid = cpu_to_le16(id);
728
729 status = nvme_submit_admin_cmd(dev, &c, NULL);
730 if (status)
731 return -EIO;
732 return 0;
733}
734
735static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
736 struct nvme_queue *nvmeq)
737{
738 int status;
739 struct nvme_command c;
740 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
741
742 memset(&c, 0, sizeof(c));
743 c.create_cq.opcode = nvme_admin_create_cq;
744 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
745 c.create_cq.cqid = cpu_to_le16(qid);
746 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
747 c.create_cq.cq_flags = cpu_to_le16(flags);
748 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
749
750 status = nvme_submit_admin_cmd(dev, &c, NULL);
751 if (status)
752 return -EIO;
753 return 0;
754}
755
756static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
757 struct nvme_queue *nvmeq)
758{
759 int status;
760 struct nvme_command c;
761 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
762
763 memset(&c, 0, sizeof(c));
764 c.create_sq.opcode = nvme_admin_create_sq;
765 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
766 c.create_sq.sqid = cpu_to_le16(qid);
767 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
768 c.create_sq.sq_flags = cpu_to_le16(flags);
769 c.create_sq.cqid = cpu_to_le16(qid);
770
771 status = nvme_submit_admin_cmd(dev, &c, NULL);
772 if (status)
773 return -EIO;
774 return 0;
775}
776
777static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
778{
779 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
780}
781
782static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
783{
784 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
785}
786
787static void nvme_free_queue(struct nvme_dev *dev, int qid)
788{
789 struct nvme_queue *nvmeq = dev->queues[qid];
aba2080f 790 int vector = dev->entry[nvmeq->cq_vector].vector;
b60503ba 791
aba2080f
MW		 792 irq_set_affinity_hint(vector, NULL);
793 free_irq(vector, nvmeq);
b60503ba
MW		 794
795 /* Don't tell the adapter to delete the admin queue */
796 if (qid) {
797 adapter_delete_sq(dev, qid);
798 adapter_delete_cq(dev, qid);
799 }
800
801 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
802 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
803 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
804 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
805 kfree(nvmeq);
806}
807
808static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
809 int depth, int vector)
810{
811 struct device *dmadev = &dev->pci_dev->dev;
e85248e5 812 unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
b60503ba
MW		 813 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
814 if (!nvmeq)
815 return NULL;
816
817 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
818 &nvmeq->cq_dma_addr, GFP_KERNEL);
819 if (!nvmeq->cqes)
820 goto free_nvmeq;
821 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
822
823 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
824 &nvmeq->sq_dma_addr, GFP_KERNEL);
825 if (!nvmeq->sq_cmds)
826 goto free_cqdma;
827
828 nvmeq->q_dmadev = dmadev;
091b6092 829 nvmeq->dev = dev;
b60503ba
MW		 830 spin_lock_init(&nvmeq->q_lock);
831 nvmeq->cq_head = 0;
82123460 832 nvmeq->cq_phase = 1;
b60503ba 833 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 834 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba
MW		 835 bio_list_init(&nvmeq->sq_cong);
836 nvmeq->q_db = &dev->dbs[qid * 2];
837 nvmeq->q_depth = depth;
838 nvmeq->cq_vector = vector;
839
840 return nvmeq;
841
842 free_cqdma:
843 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
844 nvmeq->cq_dma_addr);
845 free_nvmeq:
846 kfree(nvmeq);
847 return NULL;
848}
849
3001082c
MW		 850static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
851 const char *name)
852{
58ffacb5
MW		 853 if (use_threaded_interrupts)
854 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
ec6ce618 855 nvme_irq_check, nvme_irq,
58ffacb5
MW		 856 IRQF_DISABLED | IRQF_SHARED,
857 name, nvmeq);
3001082c
MW		 858 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
859 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
860}
861
b60503ba
MW		 862static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
863 int qid, int cq_size, int vector)
864{
865 int result;
866 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
867
3f85d50b
MW		 868 if (!nvmeq)
869 return NULL;
870
b60503ba
MW		 871 result = adapter_alloc_cq(dev, qid, nvmeq);
872 if (result < 0)
873 goto free_nvmeq;
874
875 result = adapter_alloc_sq(dev, qid, nvmeq);
876 if (result < 0)
877 goto release_cq;
878
3001082c 879 result = queue_request_irq(dev, nvmeq, "nvme");
b60503ba
MW		 880 if (result < 0)
881 goto release_sq;
882
883 return nvmeq;
884
885 release_sq:
886 adapter_delete_sq(dev, qid);
887 release_cq:
888 adapter_delete_cq(dev, qid);
889 free_nvmeq:
890 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
891 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
892 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
893 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
894 kfree(nvmeq);
895 return NULL;
896}
897
898static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
899{
900 int result;
901 u32 aqa;
22605f96
MW		 902 u64 cap;
903 unsigned long timeout;
b60503ba
MW		 904 struct nvme_queue *nvmeq;
905
906 dev->dbs = ((void __iomem *)dev->bar) + 4096;
907
908 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
3f85d50b
MW		 909 if (!nvmeq)
910 return -ENOMEM;
b60503ba
MW		 911
912 aqa = nvmeq->q_depth - 1;
913 aqa |= aqa << 16;
914
915 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
916 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
917 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 918 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba 919
5911f200 920 writel(0, &dev->bar->cc);
b60503ba
MW		 921 writel(aqa, &dev->bar->aqa);
922 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
923 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
924 writel(dev->ctrl_config, &dev->bar->cc);
925
22605f96
MW		 926 cap = readq(&dev->bar->cap);
927 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
928
b60503ba
MW		 929 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
930 msleep(100);
931 if (fatal_signal_pending(current))
932 return -EINTR;
22605f96
MW		 933 if (time_after(jiffies, timeout)) {
934 dev_err(&dev->pci_dev->dev,
935 "Device not ready; aborting initialisation\n");
936 return -ENODEV;
937 }
b60503ba
MW		 938 }
939
3001082c 940 result = queue_request_irq(dev, nvmeq, "nvme admin");
b60503ba
MW		 941 dev->queues[0] = nvmeq;
942 return result;
943}
944
7fc3cdab
MW		 945static int nvme_map_user_pages(struct nvme_dev *dev, int write,
946 unsigned long addr, unsigned length,
947 struct scatterlist **sgp)
b60503ba 948{
36c14ed9 949 int i, err, count, nents, offset;
7fc3cdab
MW		 950 struct scatterlist *sg;
951 struct page **pages;
36c14ed9
MW		 952
953 if (addr & 3)
954 return -EINVAL;
7fc3cdab
MW		 955 if (!length)
956 return -EINVAL;
957
36c14ed9 958 offset = offset_in_page(addr);
7fc3cdab
MW		 959 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
960 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
36c14ed9
MW		 961
962 err = get_user_pages_fast(addr, count, 1, pages);
963 if (err < count) {
964 count = err;
965 err = -EFAULT;
966 goto put_pages;
967 }
7fc3cdab
MW		 968
969 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
36c14ed9 970 sg_init_table(sg, count);
ff22b54f 971 sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
7fc3cdab
MW		 972 length -= (PAGE_SIZE - offset);
973 for (i = 1; i < count; i++) {
974 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
975 length -= PAGE_SIZE;
976 }
977
978 err = -ENOMEM;
979 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
980 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9
MW		 981 if (!nents)
982 goto put_pages;
b60503ba 983
7fc3cdab
MW		 984 kfree(pages);
985 *sgp = sg;
986 return nents;
b60503ba 987
7fc3cdab
MW		 988 put_pages:
989 for (i = 0; i < count; i++)
990 put_page(pages[i]);
991 kfree(pages);
992 return err;
993}
b60503ba 994
7fc3cdab
MW		 995static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
996 unsigned long addr, int length,
997 struct scatterlist *sg, int nents)
998{
999 int i, count;
b60503ba 1000
7fc3cdab 1001 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
36c14ed9 1002 dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
7fc3cdab 1003
36c14ed9 1004 for (i = 0; i < count; i++)
7fc3cdab
MW		 1005 put_page(sg_page(&sg[i]));
1006}
b60503ba 1007
7fc3cdab
MW		 1008static int nvme_submit_user_admin_command(struct nvme_dev *dev,
1009 unsigned long addr, unsigned length,
1010 struct nvme_command *cmd)
1011{
1012 int err, nents;
1013 struct scatterlist *sg;
e025344c 1014 struct nvme_prps *prps;
7fc3cdab
MW		 1015
1016 nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
1017 if (nents < 0)
1018 return nents;
d567760c 1019 prps = nvme_setup_prps(dev, &cmd->common, sg, length);
7fc3cdab
MW		 1020 err = nvme_submit_admin_cmd(dev, cmd, NULL);
1021 nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
d567760c 1022 nvme_free_prps(dev, prps);
7fc3cdab 1023 return err ? -EIO : 0;
b60503ba
MW		 1024}
1025
bd38c555 1026static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
b60503ba 1027{
b60503ba 1028 struct nvme_command c;
b60503ba 1029
bd38c555
MW		 1030 memset(&c, 0, sizeof(c));
1031 c.identify.opcode = nvme_admin_identify;
1032 c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
1033 c.identify.cns = cpu_to_le32(cns);
1034
1035 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1036}
1037
1038static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
1039{
1040 struct nvme_command c;
b60503ba
MW		 1041
1042 memset(&c, 0, sizeof(c));
1043 c.features.opcode = nvme_admin_get_features;
1044 c.features.nsid = cpu_to_le32(ns->ns_id);
b60503ba
MW		 1045 c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1046
bd38c555 1047 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
b60503ba
MW		 1048}
1049
a53295b6
MW		 1050static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1051{
1052 struct nvme_dev *dev = ns->dev;
1053 struct nvme_queue *nvmeq;
1054 struct nvme_user_io io;
1055 struct nvme_command c;
1056 unsigned length;
a53295b6
MW		 1057 int nents, status;
1058 struct scatterlist *sg;
e025344c 1059 struct nvme_prps *prps;
a53295b6
MW		 1060
1061 if (copy_from_user(&io, uio, sizeof(io)))
1062 return -EFAULT;
6c7d4945
MW		 1063 length = (io.nblocks + 1) << ns->lba_shift;
1064
1065 switch (io.opcode) {
1066 case nvme_cmd_write:
1067 case nvme_cmd_read:
1068 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr,
1069 length, &sg);
1070 default:
1071 return -EFAULT;
1072 }
1073
a53295b6
MW		 1074 if (nents < 0)
1075 return nents;
1076
1077 memset(&c, 0, sizeof(c));
1078 c.rw.opcode = io.opcode;
1079 c.rw.flags = io.flags;
6c7d4945 1080 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1081 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1082 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6
MW		 1083 c.rw.control = cpu_to_le16(io.control);
1084 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
6c7d4945
MW		 1085 c.rw.reftag = io.reftag;
1086 c.rw.apptag = io.apptag;
1087 c.rw.appmask = io.appmask;
a53295b6 1088 /* XXX: metadata */
d567760c 1089 prps = nvme_setup_prps(dev, &c.common, sg, length);
a53295b6 1090
d567760c 1091 nvmeq = get_nvmeq(ns);
fa922821
MW		 1092 /*
1093 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
b1ad37ef
MW		 1094 * disabled. We may be preempted at any point, and be rescheduled
1095 * to a different CPU. That will cause cacheline bouncing, but no
1096 * additional races since q_lock already protects against other CPUs.
1097 */
a53295b6 1098 put_nvmeq(nvmeq);
6c7d4945 1099 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, IO_TIMEOUT);
a53295b6
MW		 1100
1101 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
d567760c 1102 nvme_free_prps(dev, prps);
a53295b6
MW		 1103 return status;
1104}
1105
6ee44cdc
MW		 1106static int nvme_download_firmware(struct nvme_ns *ns,
1107 struct nvme_dlfw __user *udlfw)
1108{
1109 struct nvme_dev *dev = ns->dev;
1110 struct nvme_dlfw dlfw;
1111 struct nvme_command c;
1112 int nents, status;
1113 struct scatterlist *sg;
e025344c 1114 struct nvme_prps *prps;
6ee44cdc
MW		 1115
1116 if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1117 return -EFAULT;
1118 if (dlfw.length >= (1 << 30))
1119 return -EINVAL;
1120
1121 nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1122 if (nents < 0)
1123 return nents;
1124
1125 memset(&c, 0, sizeof(c));
1126 c.dlfw.opcode = nvme_admin_download_fw;
1127 c.dlfw.numd = cpu_to_le32(dlfw.length);
1128 c.dlfw.offset = cpu_to_le32(dlfw.offset);
d567760c 1129 prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
6ee44cdc
MW		 1130
1131 status = nvme_submit_admin_cmd(dev, &c, NULL);
1132 nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
d567760c 1133 nvme_free_prps(dev, prps);
6ee44cdc
MW		 1134 return status;
1135}
1136
1137static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1138{
1139 struct nvme_dev *dev = ns->dev;
1140 struct nvme_command c;
1141
1142 memset(&c, 0, sizeof(c));
1143 c.common.opcode = nvme_admin_activate_fw;
1144 c.common.rsvd10[0] = cpu_to_le32(arg);
1145
1146 return nvme_submit_admin_cmd(dev, &c, NULL);
1147}
1148
b60503ba
MW		 1149static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1150 unsigned long arg)
1151{
1152 struct nvme_ns *ns = bdev->bd_disk->private_data;
1153
1154 switch (cmd) {
1155 case NVME_IOCTL_IDENTIFY_NS:
36c14ed9 1156 return nvme_identify(ns, arg, 0);
b60503ba 1157 case NVME_IOCTL_IDENTIFY_CTRL:
36c14ed9 1158 return nvme_identify(ns, arg, 1);
b60503ba 1159 case NVME_IOCTL_GET_RANGE_TYPE:
bd38c555 1160 return nvme_get_range_type(ns, arg);
a53295b6
MW		 1161 case NVME_IOCTL_SUBMIT_IO:
1162 return nvme_submit_io(ns, (void __user *)arg);
6ee44cdc
MW		 1163 case NVME_IOCTL_DOWNLOAD_FW:
1164 return nvme_download_firmware(ns, (void __user *)arg);
1165 case NVME_IOCTL_ACTIVATE_FW:
1166 return nvme_activate_firmware(ns, arg);
b60503ba
MW		 1167 default:
1168 return -ENOTTY;
1169 }
1170}
1171
1172static const struct block_device_operations nvme_fops = {
1173 .owner = THIS_MODULE,
1174 .ioctl = nvme_ioctl,
49481682 1175 .compat_ioctl = nvme_ioctl,
b60503ba
MW		 1176};
1177
8de05535
MW		 1178static void nvme_timeout_ios(struct nvme_queue *nvmeq)
1179{
1180 int depth = nvmeq->q_depth - 1;
1181 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1182 unsigned long now = jiffies;
1183 int cmdid;
1184
1185 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1186 unsigned long data;
1187 void *ptr;
1188 unsigned char handler;
1189 static struct nvme_completion cqe = { .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, };
1190
1191 if (!time_after(now, info[cmdid].timeout))
1192 continue;
1193 dev_warn(nvmeq->q_dmadev, "Timing out I/O %d\n", cmdid);
1194 data = cancel_cmdid(nvmeq, cmdid);
1195 handler = data & 3;
1196 ptr = (void *)(data & ~3UL);
1197 nvme_completions[handler](nvmeq, ptr, &cqe);
1198 }
1199}
1200
1fa6aead
MW		 1201static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1202{
1203 while (bio_list_peek(&nvmeq->sq_cong)) {
1204 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1205 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1206 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1207 bio_list_add_head(&nvmeq->sq_cong, bio);
1208 break;
1209 }
3cb967c0
MW		 1210 if (bio_list_empty(&nvmeq->sq_cong))
1211 remove_wait_queue(&nvmeq->sq_full,
1212 &nvmeq->sq_cong_wait);
1fa6aead
MW		 1213 }
1214}
1215
1216static int nvme_kthread(void *data)
1217{
1218 struct nvme_dev *dev;
1219
1220 while (!kthread_should_stop()) {
1221 __set_current_state(TASK_RUNNING);
1222 spin_lock(&dev_list_lock);
1223 list_for_each_entry(dev, &dev_list, node) {
1224 int i;
1225 for (i = 0; i < dev->queue_count; i++) {
1226 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 1227 if (!nvmeq)
1228 continue;
1fa6aead
MW		 1229 spin_lock_irq(&nvmeq->q_lock);
1230 if (nvme_process_cq(nvmeq))
1231 printk("process_cq did something\n");
8de05535 1232 nvme_timeout_ios(nvmeq);
1fa6aead
MW		 1233 nvme_resubmit_bios(nvmeq);
1234 spin_unlock_irq(&nvmeq->q_lock);
1235 }
1236 }
1237 spin_unlock(&dev_list_lock);
1238 set_current_state(TASK_INTERRUPTIBLE);
1239 schedule_timeout(HZ);
1240 }
1241 return 0;
1242}
1243
5aff9382
MW		 1244static DEFINE_IDA(nvme_index_ida);
1245
1246static int nvme_get_ns_idx(void)
1247{
1248 int index, error;
1249
1250 do {
1251 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1252 return -1;
1253
1254 spin_lock(&dev_list_lock);
1255 error = ida_get_new(&nvme_index_ida, &index);
1256 spin_unlock(&dev_list_lock);
1257 } while (error == -EAGAIN);
1258
1259 if (error)
1260 index = -1;
1261 return index;
1262}
1263
1264static void nvme_put_ns_idx(int index)
1265{
1266 spin_lock(&dev_list_lock);
1267 ida_remove(&nvme_index_ida, index);
1268 spin_unlock(&dev_list_lock);
1269}
1270
1271static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid,
b60503ba
MW		 1272 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1273{
1274 struct nvme_ns *ns;
1275 struct gendisk *disk;
1276 int lbaf;
1277
1278 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1279 return NULL;
1280
1281 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1282 if (!ns)
1283 return NULL;
1284 ns->queue = blk_alloc_queue(GFP_KERNEL);
1285 if (!ns->queue)
1286 goto out_free_ns;
1287 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1288 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1289 blk_queue_make_request(ns->queue, nvme_make_request);
1290 ns->dev = dev;
1291 ns->queue->queuedata = ns;
1292
1293 disk = alloc_disk(NVME_MINORS);
1294 if (!disk)
1295 goto out_free_queue;
5aff9382 1296 ns->ns_id = nsid;
b60503ba
MW		 1297 ns->disk = disk;
1298 lbaf = id->flbas & 0xf;
1299 ns->lba_shift = id->lbaf[lbaf].ds;
1300
1301 disk->major = nvme_major;
1302 disk->minors = NVME_MINORS;
5aff9382 1303 disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
b60503ba
MW		 1304 disk->fops = &nvme_fops;
1305 disk->private_data = ns;
1306 disk->queue = ns->queue;
388f037f 1307 disk->driverfs_dev = &dev->pci_dev->dev;
5aff9382 1308 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1309 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1310
1311 return ns;
1312
1313 out_free_queue:
1314 blk_cleanup_queue(ns->queue);
1315 out_free_ns:
1316 kfree(ns);
1317 return NULL;
1318}
1319
1320static void nvme_ns_free(struct nvme_ns *ns)
1321{
5aff9382 1322 int index = ns->disk->first_minor / NVME_MINORS;
b60503ba 1323 put_disk(ns->disk);
5aff9382 1324 nvme_put_ns_idx(index);
b60503ba
MW		 1325 blk_cleanup_queue(ns->queue);
1326 kfree(ns);
1327}
1328
b3b06812 1329static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 1330{
1331 int status;
1332 u32 result;
1333 struct nvme_command c;
b3b06812 1334 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba
MW		 1335
1336 memset(&c, 0, sizeof(c));
1337 c.features.opcode = nvme_admin_get_features;
1338 c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1339 c.features.dword11 = cpu_to_le32(q_count);
1340
1341 status = nvme_submit_admin_cmd(dev, &c, &result);
1342 if (status)
1343 return -EIO;
1344 return min(result & 0xffff, result >> 16) + 1;
1345}
1346
b60503ba
MW		 1347static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1348{
b348b7d5 1349 int result, cpu, i, nr_io_queues;
b60503ba 1350
b348b7d5
MW		 1351 nr_io_queues = num_online_cpus();
1352 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW		 1353 if (result < 0)
1354 return result;
b348b7d5
MW		 1355 if (result < nr_io_queues)
1356 nr_io_queues = result;
b60503ba 1357
1b23484b
MW		 1358 /* Deregister the admin queue's interrupt */
1359 free_irq(dev->entry[0].vector, dev->queues[0]);
1360
b348b7d5 1361 for (i = 0; i < nr_io_queues; i++)
1b23484b
MW		 1362 dev->entry[i].entry = i;
1363 for (;;) {
b348b7d5
MW		 1364 result = pci_enable_msix(dev->pci_dev, dev->entry,
1365 nr_io_queues);
1b23484b
MW		 1366 if (result == 0) {
1367 break;
1368 } else if (result > 0) {
b348b7d5 1369 nr_io_queues = result;
1b23484b
MW		 1370 continue;
1371 } else {
b348b7d5 1372 nr_io_queues = 1;
1b23484b
MW		 1373 break;
1374 }
1375 }
1376
1377 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1378 /* XXX: handle failure here */
1379
1380 cpu = cpumask_first(cpu_online_mask);
b348b7d5 1381 for (i = 0; i < nr_io_queues; i++) {
1b23484b
MW		 1382 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1383 cpu = cpumask_next(cpu, cpu_online_mask);
1384 }
1385
b348b7d5 1386 for (i = 0; i < nr_io_queues; i++) {
1b23484b
MW		 1387 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1388 NVME_Q_DEPTH, i);
1389 if (!dev->queues[i + 1])
1390 return -ENOMEM;
1391 dev->queue_count++;
1392 }
b60503ba 1393
9ecdc946
MW		 1394 for (; i < num_possible_cpus(); i++) {
1395 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1396 dev->queues[i + 1] = dev->queues[target + 1];
1397 }
1398
b60503ba
MW		 1399 return 0;
1400}
1401
1402static void nvme_free_queues(struct nvme_dev *dev)
1403{
1404 int i;
1405
1406 for (i = dev->queue_count - 1; i >= 0; i--)
1407 nvme_free_queue(dev, i);
1408}
1409
1410static int __devinit nvme_dev_add(struct nvme_dev *dev)
1411{
1412 int res, nn, i;
1413 struct nvme_ns *ns, *next;
51814232 1414 struct nvme_id_ctrl *ctrl;
b60503ba
MW		 1415 void *id;
1416 dma_addr_t dma_addr;
1417 struct nvme_command cid, crt;
1418
1419 res = nvme_setup_io_queues(dev);
1420 if (res)
1421 return res;
1422
1423 /* XXX: Switch to a SG list once prp2 works */
1424 id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1425 GFP_KERNEL);
1426
1427 memset(&cid, 0, sizeof(cid));
1428 cid.identify.opcode = nvme_admin_identify;
1429 cid.identify.nsid = 0;
1430 cid.identify.prp1 = cpu_to_le64(dma_addr);
1431 cid.identify.cns = cpu_to_le32(1);
1432
1433 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1434 if (res) {
1435 res = -EIO;
1436 goto out_free;
1437 }
1438
51814232
MW		 1439 ctrl = id;
1440 nn = le32_to_cpup(&ctrl->nn);
1441 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1442 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1443 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
b60503ba
MW		 1444
1445 cid.identify.cns = 0;
1446 memset(&crt, 0, sizeof(crt));
1447 crt.features.opcode = nvme_admin_get_features;
1448 crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1449 crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1450
ac88c36a 1451 for (i = 0; i <= nn; i++) {
b60503ba
MW		 1452 cid.identify.nsid = cpu_to_le32(i);
1453 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1454 if (res)
1455 continue;
1456
1457 if (((struct nvme_id_ns *)id)->ncap == 0)
1458 continue;
1459
1460 crt.features.nsid = cpu_to_le32(i);
1461 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1462 if (res)
1463 continue;
1464
1465 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1466 if (ns)
1467 list_add_tail(&ns->list, &dev->namespaces);
1468 }
1469 list_for_each_entry(ns, &dev->namespaces, list)
1470 add_disk(ns->disk);
1471
1472 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1473 return 0;
1474
1475 out_free:
1476 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1477 list_del(&ns->list);
1478 nvme_ns_free(ns);
1479 }
1480
1481 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1482 return res;
1483}
1484
1485static int nvme_dev_remove(struct nvme_dev *dev)
1486{
1487 struct nvme_ns *ns, *next;
1488
1fa6aead
MW		 1489 spin_lock(&dev_list_lock);
1490 list_del(&dev->node);
1491 spin_unlock(&dev_list_lock);
1492
b60503ba
MW		 1493 /* TODO: wait all I/O finished or cancel them */
1494
1495 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1496 list_del(&ns->list);
1497 del_gendisk(ns->disk);
1498 nvme_ns_free(ns);
1499 }
1500
1501 nvme_free_queues(dev);
1502
1503 return 0;
1504}
1505
091b6092
MW		 1506static int nvme_setup_prp_pools(struct nvme_dev *dev)
1507{
1508 struct device *dmadev = &dev->pci_dev->dev;
1509 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1510 PAGE_SIZE, PAGE_SIZE, 0);
1511 if (!dev->prp_page_pool)
1512 return -ENOMEM;
1513
99802a7a
MW		 1514 /* Optimisation for I/Os between 4k and 128k */
1515 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1516 256, 256, 0);
1517 if (!dev->prp_small_pool) {
1518 dma_pool_destroy(dev->prp_page_pool);
1519 return -ENOMEM;
1520 }
091b6092
MW		 1521 return 0;
1522}
1523
1524static void nvme_release_prp_pools(struct nvme_dev *dev)
1525{
1526 dma_pool_destroy(dev->prp_page_pool);
99802a7a 1527 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 1528}
1529
b60503ba
MW		 1530/* XXX: Use an ida or something to let remove / add work correctly */
1531static void nvme_set_instance(struct nvme_dev *dev)
1532{
1533 static int instance;
1534 dev->instance = instance++;
1535}
1536
1537static void nvme_release_instance(struct nvme_dev *dev)
1538{
1539}
1540
1541static int __devinit nvme_probe(struct pci_dev *pdev,
1542 const struct pci_device_id *id)
1543{
574e8b95 1544 int bars, result = -ENOMEM;
b60503ba
MW		 1545 struct nvme_dev *dev;
1546
1547 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1548 if (!dev)
1549 return -ENOMEM;
1550 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1551 GFP_KERNEL);
1552 if (!dev->entry)
1553 goto free;
1b23484b
MW		 1554 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1555 GFP_KERNEL);
b60503ba
MW		 1556 if (!dev->queues)
1557 goto free;
1558
0ee5a7d7
SMM		 1559 if (pci_enable_device_mem(pdev))
1560 goto free;
f64d3365 1561 pci_set_master(pdev);
574e8b95
MW		 1562 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1563 if (pci_request_selected_regions(pdev, bars, "nvme"))
1564 goto disable;
0ee5a7d7 1565
b60503ba
MW		 1566 INIT_LIST_HEAD(&dev->namespaces);
1567 dev->pci_dev = pdev;
1568 pci_set_drvdata(pdev, dev);
2930353f
MW		 1569 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1570 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
b60503ba 1571 nvme_set_instance(dev);
53c9577e 1572 dev->entry[0].vector = pdev->irq;
b60503ba 1573
091b6092
MW		 1574 result = nvme_setup_prp_pools(dev);
1575 if (result)
1576 goto disable_msix;
1577
b60503ba
MW		 1578 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1579 if (!dev->bar) {
1580 result = -ENOMEM;
574e8b95 1581 goto disable_msix;
b60503ba
MW		 1582 }
1583
1584 result = nvme_configure_admin_queue(dev);
1585 if (result)
1586 goto unmap;
1587 dev->queue_count++;
1588
1fa6aead
MW		 1589 spin_lock(&dev_list_lock);
1590 list_add(&dev->node, &dev_list);
1591 spin_unlock(&dev_list_lock);
1592
740216fc
MW		 1593 result = nvme_dev_add(dev);
1594 if (result)
1595 goto delete;
1596
b60503ba
MW		 1597 return 0;
1598
1599 delete:
740216fc
MW		 1600 spin_lock(&dev_list_lock);
1601 list_del(&dev->node);
1602 spin_unlock(&dev_list_lock);
1603
b60503ba
MW		 1604 nvme_free_queues(dev);
1605 unmap:
1606 iounmap(dev->bar);
574e8b95 1607 disable_msix:
b60503ba
MW		 1608 pci_disable_msix(pdev);
1609 nvme_release_instance(dev);
091b6092 1610 nvme_release_prp_pools(dev);
574e8b95 1611 disable:
0ee5a7d7 1612 pci_disable_device(pdev);
574e8b95 1613 pci_release_regions(pdev);
b60503ba
MW		 1614 free:
1615 kfree(dev->queues);
1616 kfree(dev->entry);
1617 kfree(dev);
1618 return result;
1619}
1620
1621static void __devexit nvme_remove(struct pci_dev *pdev)
1622{
1623 struct nvme_dev *dev = pci_get_drvdata(pdev);
1624 nvme_dev_remove(dev);
1625 pci_disable_msix(pdev);
1626 iounmap(dev->bar);
1627 nvme_release_instance(dev);
091b6092 1628 nvme_release_prp_pools(dev);
0ee5a7d7 1629 pci_disable_device(pdev);
574e8b95 1630 pci_release_regions(pdev);
b60503ba
MW		 1631 kfree(dev->queues);
1632 kfree(dev->entry);
1633 kfree(dev);
1634}
1635
1636/* These functions are yet to be implemented */
1637#define nvme_error_detected NULL
1638#define nvme_dump_registers NULL
1639#define nvme_link_reset NULL
1640#define nvme_slot_reset NULL
1641#define nvme_error_resume NULL
1642#define nvme_suspend NULL
1643#define nvme_resume NULL
1644
1645static struct pci_error_handlers nvme_err_handler = {
1646 .error_detected = nvme_error_detected,
1647 .mmio_enabled = nvme_dump_registers,
1648 .link_reset = nvme_link_reset,
1649 .slot_reset = nvme_slot_reset,
1650 .resume = nvme_error_resume,
1651};
1652
1653/* Move to pci_ids.h later */
1654#define PCI_CLASS_STORAGE_EXPRESS 0x010802
1655
1656static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1657 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1658 { 0, }
1659};
1660MODULE_DEVICE_TABLE(pci, nvme_id_table);
1661
1662static struct pci_driver nvme_driver = {
1663 .name = "nvme",
1664 .id_table = nvme_id_table,
1665 .probe = nvme_probe,
1666 .remove = __devexit_p(nvme_remove),
1667 .suspend = nvme_suspend,
1668 .resume = nvme_resume,
1669 .err_handler = &nvme_err_handler,
1670};
1671
1672static int __init nvme_init(void)
1673{
1fa6aead
MW		 1674 int result = -EBUSY;
1675
1676 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1677 if (IS_ERR(nvme_thread))
1678 return PTR_ERR(nvme_thread);
b60503ba
MW		 1679
1680 nvme_major = register_blkdev(nvme_major, "nvme");
1681 if (nvme_major <= 0)
1fa6aead 1682 goto kill_kthread;
b60503ba
MW		 1683
1684 result = pci_register_driver(&nvme_driver);
1fa6aead
MW		 1685 if (result)
1686 goto unregister_blkdev;
1687 return 0;
b60503ba 1688
1fa6aead 1689 unregister_blkdev:
b60503ba 1690 unregister_blkdev(nvme_major, "nvme");
1fa6aead
MW		 1691 kill_kthread:
1692 kthread_stop(nvme_thread);
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MW		 1693 return result;
1694}
1695
1696static void __exit nvme_exit(void)
1697{
1698 pci_unregister_driver(&nvme_driver);
1699 unregister_blkdev(nvme_major, "nvme");
1fa6aead 1700 kthread_stop(nvme_thread);
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MW		 1701}
1702
1703MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1704MODULE_LICENSE("GPL");
8ef70067 1705MODULE_VERSION("0.5");
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MW		 1706module_init(nvme_init);
1707module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)