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NVMe: Unify controller probe and resume
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba 31#include <linux/kernel.h>
a5768aa8 32#include <linux/list_sort.h>
b60503ba
MW		 33#include <linux/mm.h>
34#include <linux/module.h>
35#include <linux/moduleparam.h>
36#include <linux/pci.h>
be7b6275 37#include <linux/poison.h>
c3bfe717 38#include <linux/ptrace.h>
b60503ba
MW		 39#include <linux/sched.h>
40#include <linux/slab.h>
e1e5e564 41#include <linux/t10-pi.h>
b60503ba 42#include <linux/types.h>
5d0f6131 43#include <scsi/sg.h>
797a796a
HM		 44#include <asm-generic/io-64-nonatomic-lo-hi.h>
45
b3fffdef 46#define NVME_MINORS (1U << MINORBITS)
9d43cf64 47#define NVME_Q_DEPTH 1024
d31af0a3 48#define NVME_AQ_DEPTH 256
b60503ba
MW		 49#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
50#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 51#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 52#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 53
54static unsigned char admin_timeout = 60;
55module_param(admin_timeout, byte, 0644);
56MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 57
bd67608a
MW		 58unsigned char nvme_io_timeout = 30;
59module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 60MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 61
2484f407
DM		 62static unsigned char shutdown_timeout = 5;
63module_param(shutdown_timeout, byte, 0644);
64MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
65
b60503ba
MW		 66static int nvme_major;
67module_param(nvme_major, int, 0);
68
b3fffdef
KB		 69static int nvme_char_major;
70module_param(nvme_char_major, int, 0);
71
58ffacb5
MW		 72static int use_threaded_interrupts;
73module_param(use_threaded_interrupts, int, 0);
74
1fa6aead
MW		 75static DEFINE_SPINLOCK(dev_list_lock);
76static LIST_HEAD(dev_list);
77static struct task_struct *nvme_thread;
9a6b9458 78static struct workqueue_struct *nvme_workq;
b9afca3e 79static wait_queue_head_t nvme_kthread_wait;
1fa6aead 80
b3fffdef
KB		 81static struct class *nvme_class;
82
d4b4ff8e 83static void nvme_reset_failed_dev(struct work_struct *ws);
4cc06521 84static int nvme_reset(struct nvme_dev *dev);
a4aea562 85static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 86
4d115420
KB		 87struct async_cmd_info {
88 struct kthread_work work;
89 struct kthread_worker *worker;
a4aea562 90 struct request *req;
4d115420
KB		 91 u32 result;
92 int status;
93 void *ctx;
94};
1fa6aead 95
b60503ba
MW		 96/*
97 * An NVM Express queue. Each device has at least two (one for admin
98 * commands and one for I/O commands).
99 */
100struct nvme_queue {
101 struct device *q_dmadev;
091b6092 102 struct nvme_dev *dev;
3193f07b 103 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 104 spinlock_t q_lock;
105 struct nvme_command *sq_cmds;
106 volatile struct nvme_completion *cqes;
42483228 107 struct blk_mq_tags **tags;
b60503ba
MW		 108 dma_addr_t sq_dma_addr;
109 dma_addr_t cq_dma_addr;
b60503ba
MW		 110 u32 __iomem *q_db;
111 u16 q_depth;
6222d172 112 s16 cq_vector;
b60503ba
MW		 113 u16 sq_head;
114 u16 sq_tail;
115 u16 cq_head;
c30341dc 116 u16 qid;
e9539f47
MW		 117 u8 cq_phase;
118 u8 cqe_seen;
4d115420 119 struct async_cmd_info cmdinfo;
b60503ba
MW		 120};
121
122/*
123 * Check we didin't inadvertently grow the command struct
124 */
125static inline void _nvme_check_size(void)
126{
127 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 132 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 133 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 134 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
135 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
136 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
137 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 138 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 139}
140
edd10d33 141typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 142 struct nvme_completion *);
143
e85248e5 144struct nvme_cmd_info {
c2f5b650
MW		 145 nvme_completion_fn fn;
146 void *ctx;
c30341dc 147 int aborted;
a4aea562 148 struct nvme_queue *nvmeq;
ac3dd5bd 149 struct nvme_iod iod[0];
e85248e5
MW		 150};
151
ac3dd5bd
JA		 152/*
153 * Max size of iod being embedded in the request payload
154 */
155#define NVME_INT_PAGES 2
156#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
fda631ff 157#define NVME_INT_MASK 0x01
ac3dd5bd
JA		 158
159/*
160 * Will slightly overestimate the number of pages needed. This is OK
161 * as it only leads to a small amount of wasted memory for the lifetime of
162 * the I/O.
163 */
164static int nvme_npages(unsigned size, struct nvme_dev *dev)
165{
166 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
167 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
168}
169
170static unsigned int nvme_cmd_size(struct nvme_dev *dev)
171{
172 unsigned int ret = sizeof(struct nvme_cmd_info);
173
174 ret += sizeof(struct nvme_iod);
175 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
176 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
177
178 return ret;
179}
180
a4aea562
MB		 181static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
182 unsigned int hctx_idx)
e85248e5 183{
a4aea562
MB		 184 struct nvme_dev *dev = data;
185 struct nvme_queue *nvmeq = dev->queues[0];
186
42483228
KB		 187 WARN_ON(hctx_idx != 0);
188 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
189 WARN_ON(nvmeq->tags);
190
a4aea562 191 hctx->driver_data = nvmeq;
42483228 192 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 193 return 0;
e85248e5
MW		 194}
195
4af0e21c
KB		 196static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
197{
198 struct nvme_queue *nvmeq = hctx->driver_data;
199
200 nvmeq->tags = NULL;
201}
202
a4aea562
MB		 203static int nvme_admin_init_request(void *data, struct request *req,
204 unsigned int hctx_idx, unsigned int rq_idx,
205 unsigned int numa_node)
22404274 206{
a4aea562
MB		 207 struct nvme_dev *dev = data;
208 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
209 struct nvme_queue *nvmeq = dev->queues[0];
210
211 BUG_ON(!nvmeq);
212 cmd->nvmeq = nvmeq;
213 return 0;
22404274
KB		 214}
215
a4aea562
MB		 216static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
217 unsigned int hctx_idx)
b60503ba 218{
a4aea562 219 struct nvme_dev *dev = data;
42483228 220 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
a4aea562 221
42483228
KB		 222 if (!nvmeq->tags)
223 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 224
42483228 225 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 226 hctx->driver_data = nvmeq;
227 return 0;
b60503ba
MW		 228}
229
a4aea562
MB		 230static int nvme_init_request(void *data, struct request *req,
231 unsigned int hctx_idx, unsigned int rq_idx,
232 unsigned int numa_node)
b60503ba 233{
a4aea562
MB		 234 struct nvme_dev *dev = data;
235 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
236 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
237
238 BUG_ON(!nvmeq);
239 cmd->nvmeq = nvmeq;
240 return 0;
241}
242
243static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
244 nvme_completion_fn handler)
245{
246 cmd->fn = handler;
247 cmd->ctx = ctx;
248 cmd->aborted = 0;
c917dfe5 249 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 250}
251
ac3dd5bd
JA		 252static void *iod_get_private(struct nvme_iod *iod)
253{
254 return (void *) (iod->private & ~0x1UL);
255}
256
257/*
258 * If bit 0 is set, the iod is embedded in the request payload.
259 */
260static bool iod_should_kfree(struct nvme_iod *iod)
261{
fda631ff 262 return (iod->private & NVME_INT_MASK) == 0;
ac3dd5bd
JA		 263}
264
c2f5b650
MW		 265/* Special values must be less than 0x1000 */
266#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 267#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
268#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
269#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 270
edd10d33 271static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 272 struct nvme_completion *cqe)
273{
274 if (ctx == CMD_CTX_CANCELLED)
275 return;
c2f5b650 276 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 277 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 278 "completed id %d twice on queue %d\n",
279 cqe->command_id, le16_to_cpup(&cqe->sq_id));
280 return;
281 }
282 if (ctx == CMD_CTX_INVALID) {
edd10d33 283 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 284 "invalid id %d completed on queue %d\n",
285 cqe->command_id, le16_to_cpup(&cqe->sq_id));
286 return;
287 }
edd10d33 288 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 289}
290
a4aea562 291static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 292{
c2f5b650 293 void *ctx;
b60503ba 294
859361a2 295 if (fn)
a4aea562
MB		 296 *fn = cmd->fn;
297 ctx = cmd->ctx;
298 cmd->fn = special_completion;
299 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 300 return ctx;
b60503ba
MW		 301}
302
a4aea562
MB		 303static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
304 struct nvme_completion *cqe)
3c0cf138 305{
a4aea562
MB		 306 u32 result = le32_to_cpup(&cqe->result);
307 u16 status = le16_to_cpup(&cqe->status) >> 1;
308
309 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
310 ++nvmeq->dev->event_limit;
a5768aa8
KB		 311 if (status != NVME_SC_SUCCESS)
312 return;
313
314 switch (result & 0xff07) {
315 case NVME_AER_NOTICE_NS_CHANGED:
316 dev_info(nvmeq->q_dmadev, "rescanning\n");
317 schedule_work(&nvmeq->dev->scan_work);
318 default:
319 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
320 }
b60503ba
MW		 321}
322
a4aea562
MB		 323static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
324 struct nvme_completion *cqe)
5a92e700 325{
a4aea562
MB		 326 struct request *req = ctx;
327
328 u16 status = le16_to_cpup(&cqe->status) >> 1;
329 u32 result = le32_to_cpup(&cqe->result);
a51afb54 330
42483228 331 blk_mq_free_request(req);
a51afb54 332
a4aea562
MB		 333 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
334 ++nvmeq->dev->abort_limit;
5a92e700
KB		 335}
336
a4aea562
MB		 337static void async_completion(struct nvme_queue *nvmeq, void *ctx,
338 struct nvme_completion *cqe)
b60503ba 339{
a4aea562
MB		 340 struct async_cmd_info *cmdinfo = ctx;
341 cmdinfo->result = le32_to_cpup(&cqe->result);
342 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
343 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
42483228 344 blk_mq_free_request(cmdinfo->req);
b60503ba
MW		 345}
346
a4aea562
MB		 347static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
348 unsigned int tag)
b60503ba 349{
42483228 350 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
a51afb54 351
a4aea562 352 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 353}
354
a4aea562
MB		 355/*
356 * Called with local interrupts disabled and the q_lock held. May not sleep.
357 */
358static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
359 nvme_completion_fn *fn)
4f5099af 360{
a4aea562
MB		 361 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
362 void *ctx;
363 if (tag >= nvmeq->q_depth) {
364 *fn = special_completion;
365 return CMD_CTX_INVALID;
366 }
367 if (fn)
368 *fn = cmd->fn;
369 ctx = cmd->ctx;
370 cmd->fn = special_completion;
371 cmd->ctx = CMD_CTX_COMPLETED;
372 return ctx;
b60503ba
MW		 373}
374
375/**
714a7a22 376 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 377 * @nvmeq: The queue to use
378 * @cmd: The command to send
379 *
380 * Safe to use from interrupt context
381 */
a4aea562 382static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 383{
a4aea562
MB		 384 u16 tail = nvmeq->sq_tail;
385
b60503ba 386 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 387 if (++tail == nvmeq->q_depth)
388 tail = 0;
7547881d 389 writel(tail, nvmeq->q_db);
b60503ba 390 nvmeq->sq_tail = tail;
b60503ba
MW		 391
392 return 0;
393}
394
a4aea562
MB		 395static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
396{
397 unsigned long flags;
398 int ret;
399 spin_lock_irqsave(&nvmeq->q_lock, flags);
400 ret = __nvme_submit_cmd(nvmeq, cmd);
401 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
402 return ret;
403}
404
eca18b23 405static __le64 **iod_list(struct nvme_iod *iod)
e025344c 406{
eca18b23 407 return ((void *)iod) + iod->offset;
e025344c
SMM		 408}
409
ac3dd5bd
JA		 410static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
411 unsigned nseg, unsigned long private)
eca18b23 412{
ac3dd5bd
JA		 413 iod->private = private;
414 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
415 iod->npages = -1;
416 iod->length = nbytes;
417 iod->nents = 0;
eca18b23 418}
b60503ba 419
eca18b23 420static struct nvme_iod *
ac3dd5bd
JA		 421__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
422 unsigned long priv, gfp_t gfp)
b60503ba 423{
eca18b23 424 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 425 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 426 sizeof(struct scatterlist) * nseg, gfp);
427
ac3dd5bd
JA		 428 if (iod)
429 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 430
431 return iod;
b60503ba
MW		 432}
433
ac3dd5bd
JA		 434static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
435 gfp_t gfp)
436{
437 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
438 sizeof(struct nvme_dsm_range);
ac3dd5bd
JA		 439 struct nvme_iod *iod;
440
441 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
442 size <= NVME_INT_BYTES(dev)) {
443 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
444
445 iod = cmd->iod;
ac3dd5bd 446 iod_init(iod, size, rq->nr_phys_segments,
fda631ff 447 (unsigned long) rq | NVME_INT_MASK);
ac3dd5bd
JA		 448 return iod;
449 }
450
451 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
452 (unsigned long) rq, gfp);
453}
454
d29ec824 455static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 456{
1d090624 457 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 458 int i;
459 __le64 **list = iod_list(iod);
460 dma_addr_t prp_dma = iod->first_dma;
461
462 if (iod->npages == 0)
463 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
464 for (i = 0; i < iod->npages; i++) {
465 __le64 *prp_list = list[i];
466 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
467 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
468 prp_dma = next_prp_dma;
469 }
ac3dd5bd
JA		 470
471 if (iod_should_kfree(iod))
472 kfree(iod);
b60503ba
MW		 473}
474
b4ff9c8d
KB		 475static int nvme_error_status(u16 status)
476{
477 switch (status & 0x7ff) {
478 case NVME_SC_SUCCESS:
479 return 0;
480 case NVME_SC_CAP_EXCEEDED:
481 return -ENOSPC;
482 default:
483 return -EIO;
484 }
485}
486
52b68d7e 487#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 488static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
489{
490 if (be32_to_cpu(pi->ref_tag) == v)
491 pi->ref_tag = cpu_to_be32(p);
492}
493
494static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
495{
496 if (be32_to_cpu(pi->ref_tag) == p)
497 pi->ref_tag = cpu_to_be32(v);
498}
499
500/**
501 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
502 *
503 * The virtual start sector is the one that was originally submitted by the
504 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
505 * start sector may be different. Remap protection information to match the
506 * physical LBA on writes, and back to the original seed on reads.
507 *
508 * Type 0 and 3 do not have a ref tag, so no remapping required.
509 */
510static void nvme_dif_remap(struct request *req,
511 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
512{
513 struct nvme_ns *ns = req->rq_disk->private_data;
514 struct bio_integrity_payload *bip;
515 struct t10_pi_tuple *pi;
516 void *p, *pmap;
517 u32 i, nlb, ts, phys, virt;
518
519 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
520 return;
521
522 bip = bio_integrity(req->bio);
523 if (!bip)
524 return;
525
526 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 527
528 p = pmap;
529 virt = bip_get_seed(bip);
530 phys = nvme_block_nr(ns, blk_rq_pos(req));
531 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
532 ts = ns->disk->integrity->tuple_size;
533
534 for (i = 0; i < nlb; i++, virt++, phys++) {
535 pi = (struct t10_pi_tuple *)p;
536 dif_swap(phys, virt, pi);
537 p += ts;
538 }
539 kunmap_atomic(pmap);
540}
541
52b68d7e
KB		 542static int nvme_noop_verify(struct blk_integrity_iter *iter)
543{
544 return 0;
545}
546
547static int nvme_noop_generate(struct blk_integrity_iter *iter)
548{
549 return 0;
550}
551
552struct blk_integrity nvme_meta_noop = {
553 .name = "NVME_META_NOOP",
554 .generate_fn = nvme_noop_generate,
555 .verify_fn = nvme_noop_verify,
556};
557
558static void nvme_init_integrity(struct nvme_ns *ns)
559{
560 struct blk_integrity integrity;
561
562 switch (ns->pi_type) {
563 case NVME_NS_DPS_PI_TYPE3:
564 integrity = t10_pi_type3_crc;
565 break;
566 case NVME_NS_DPS_PI_TYPE1:
567 case NVME_NS_DPS_PI_TYPE2:
568 integrity = t10_pi_type1_crc;
569 break;
570 default:
571 integrity = nvme_meta_noop;
572 break;
573 }
574 integrity.tuple_size = ns->ms;
575 blk_integrity_register(ns->disk, &integrity);
576 blk_queue_max_integrity_segments(ns->queue, 1);
577}
578#else /* CONFIG_BLK_DEV_INTEGRITY */
579static void nvme_dif_remap(struct request *req,
580 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
581{
582}
583static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
584{
585}
586static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
587{
588}
589static void nvme_init_integrity(struct nvme_ns *ns)
590{
591}
592#endif
593
a4aea562 594static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 595 struct nvme_completion *cqe)
596{
eca18b23 597 struct nvme_iod *iod = ctx;
ac3dd5bd 598 struct request *req = iod_get_private(iod);
a4aea562
MB		 599 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
600
b60503ba
MW		 601 u16 status = le16_to_cpup(&cqe->status) >> 1;
602
edd10d33 603 if (unlikely(status)) {
a4aea562
MB		 604 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
605 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 606 unsigned long flags;
607
a4aea562 608 blk_mq_requeue_request(req);
c9d3bf88
KB		 609 spin_lock_irqsave(req->q->queue_lock, flags);
610 if (!blk_queue_stopped(req->q))
611 blk_mq_kick_requeue_list(req->q);
612 spin_unlock_irqrestore(req->q->queue_lock, flags);
edd10d33
KB		 613 return;
614 }
d29ec824 615 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
17188bb4
KB		 616 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
617 req->errors = -EINTR;
618 else
619 req->errors = status;
d29ec824
CH		 620 } else {
621 req->errors = nvme_error_status(status);
622 }
a4aea562
MB		 623 } else
624 req->errors = 0;
a0a931d6
KB		 625 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
626 u32 result = le32_to_cpup(&cqe->result);
627 req->special = (void *)(uintptr_t)result;
628 }
a4aea562
MB		 629
630 if (cmd_rq->aborted)
e75ec752 631 dev_warn(nvmeq->dev->dev,
a4aea562
MB		 632 "completing aborted command with status:%04x\n",
633 status);
634
e1e5e564 635 if (iod->nents) {
e75ec752 636 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
a4aea562 637 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
e1e5e564
KB		 638 if (blk_integrity_rq(req)) {
639 if (!rq_data_dir(req))
640 nvme_dif_remap(req, nvme_dif_complete);
e75ec752 641 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
e1e5e564
KB		 642 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
643 }
644 }
edd10d33 645 nvme_free_iod(nvmeq->dev, iod);
3291fa57 646
a4aea562 647 blk_mq_complete_request(req);
b60503ba
MW		 648}
649
184d2944 650/* length is in bytes. gfp flags indicates whether we may sleep. */
d29ec824
CH		 651static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
652 int total_len, gfp_t gfp)
ff22b54f 653{
99802a7a 654 struct dma_pool *pool;
eca18b23
MW		 655 int length = total_len;
656 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 657 int dma_len = sg_dma_len(sg);
658 u64 dma_addr = sg_dma_address(sg);
f137e0f1
MI		 659 u32 page_size = dev->page_size;
660 int offset = dma_addr & (page_size - 1);
e025344c 661 __le64 *prp_list;
eca18b23 662 __le64 **list = iod_list(iod);
e025344c 663 dma_addr_t prp_dma;
eca18b23 664 int nprps, i;
ff22b54f 665
1d090624 666 length -= (page_size - offset);
ff22b54f 667 if (length <= 0)
eca18b23 668 return total_len;
ff22b54f 669
1d090624 670 dma_len -= (page_size - offset);
ff22b54f 671 if (dma_len) {
1d090624 672 dma_addr += (page_size - offset);
ff22b54f
MW		 673 } else {
674 sg = sg_next(sg);
675 dma_addr = sg_dma_address(sg);
676 dma_len = sg_dma_len(sg);
677 }
678
1d090624 679 if (length <= page_size) {
edd10d33 680 iod->first_dma = dma_addr;
eca18b23 681 return total_len;
e025344c
SMM		 682 }
683
1d090624 684 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 685 if (nprps <= (256 / 8)) {
686 pool = dev->prp_small_pool;
eca18b23 687 iod->npages = 0;
99802a7a
MW		 688 } else {
689 pool = dev->prp_page_pool;
eca18b23 690 iod->npages = 1;
99802a7a
MW		 691 }
692
b77954cb
MW		 693 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
694 if (!prp_list) {
edd10d33 695 iod->first_dma = dma_addr;
eca18b23 696 iod->npages = -1;
1d090624 697 return (total_len - length) + page_size;
b77954cb 698 }
eca18b23
MW		 699 list[0] = prp_list;
700 iod->first_dma = prp_dma;
e025344c
SMM		 701 i = 0;
702 for (;;) {
1d090624 703 if (i == page_size >> 3) {
e025344c 704 __le64 *old_prp_list = prp_list;
b77954cb 705 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 706 if (!prp_list)
707 return total_len - length;
708 list[iod->npages++] = prp_list;
7523d834
MW		 709 prp_list[0] = old_prp_list[i - 1];
710 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
711 i = 1;
e025344c
SMM		 712 }
713 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 714 dma_len -= page_size;
715 dma_addr += page_size;
716 length -= page_size;
e025344c
SMM		 717 if (length <= 0)
718 break;
719 if (dma_len > 0)
720 continue;
721 BUG_ON(dma_len < 0);
722 sg = sg_next(sg);
723 dma_addr = sg_dma_address(sg);
724 dma_len = sg_dma_len(sg);
ff22b54f
MW		 725 }
726
eca18b23 727 return total_len;
ff22b54f
MW		 728}
729
d29ec824
CH		 730static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
731 struct nvme_iod *iod)
732{
733 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
734
735 memcpy(cmnd, req->cmd, sizeof(struct nvme_command));
736 cmnd->rw.command_id = req->tag;
737 if (req->nr_phys_segments) {
738 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
739 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
740 }
741
742 if (++nvmeq->sq_tail == nvmeq->q_depth)
743 nvmeq->sq_tail = 0;
744 writel(nvmeq->sq_tail, nvmeq->q_db);
745}
746
a4aea562
MB		 747/*
748 * We reuse the small pool to allocate the 16-byte range here as it is not
749 * worth having a special pool for these or additional cases to handle freeing
750 * the iod.
751 */
752static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
753 struct request *req, struct nvme_iod *iod)
0e5e4f0e 754{
edd10d33
KB		 755 struct nvme_dsm_range *range =
756 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 757 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
758
0e5e4f0e 759 range->cattr = cpu_to_le32(0);
a4aea562
MB		 760 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
761 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e
KB		 762
763 memset(cmnd, 0, sizeof(*cmnd));
764 cmnd->dsm.opcode = nvme_cmd_dsm;
a4aea562 765 cmnd->dsm.command_id = req->tag;
0e5e4f0e
KB		 766 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
767 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
768 cmnd->dsm.nr = 0;
769 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
770
771 if (++nvmeq->sq_tail == nvmeq->q_depth)
772 nvmeq->sq_tail = 0;
773 writel(nvmeq->sq_tail, nvmeq->q_db);
0e5e4f0e
KB		 774}
775
a4aea562 776static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 777 int cmdid)
778{
779 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
780
781 memset(cmnd, 0, sizeof(*cmnd));
782 cmnd->common.opcode = nvme_cmd_flush;
783 cmnd->common.command_id = cmdid;
784 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
785
786 if (++nvmeq->sq_tail == nvmeq->q_depth)
787 nvmeq->sq_tail = 0;
788 writel(nvmeq->sq_tail, nvmeq->q_db);
00df5cb4
MW		 789}
790
a4aea562
MB		 791static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
792 struct nvme_ns *ns)
b60503ba 793{
ac3dd5bd 794 struct request *req = iod_get_private(iod);
ff22b54f 795 struct nvme_command *cmnd;
a4aea562
MB		 796 u16 control = 0;
797 u32 dsmgmt = 0;
00df5cb4 798
a4aea562 799 if (req->cmd_flags & REQ_FUA)
b60503ba 800 control |= NVME_RW_FUA;
a4aea562 801 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 802 control |= NVME_RW_LR;
803
a4aea562 804 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 805 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
806
ff22b54f 807 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 808 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 809
a4aea562
MB		 810 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
811 cmnd->rw.command_id = req->tag;
ff22b54f 812 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 813 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
814 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
a4aea562
MB		 815 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
816 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
e1e5e564
KB		 817
818 if (blk_integrity_rq(req)) {
819 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
820 switch (ns->pi_type) {
821 case NVME_NS_DPS_PI_TYPE3:
822 control |= NVME_RW_PRINFO_PRCHK_GUARD;
823 break;
824 case NVME_NS_DPS_PI_TYPE1:
825 case NVME_NS_DPS_PI_TYPE2:
826 control |= NVME_RW_PRINFO_PRCHK_GUARD |
827 NVME_RW_PRINFO_PRCHK_REF;
828 cmnd->rw.reftag = cpu_to_le32(
829 nvme_block_nr(ns, blk_rq_pos(req)));
830 break;
831 }
832 } else if (ns->ms)
833 control |= NVME_RW_PRINFO_PRACT;
834
ff22b54f
MW		 835 cmnd->rw.control = cpu_to_le16(control);
836 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 837
b60503ba
MW		 838 if (++nvmeq->sq_tail == nvmeq->q_depth)
839 nvmeq->sq_tail = 0;
7547881d 840 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 841
1974b1ae 842 return 0;
edd10d33
KB		 843}
844
d29ec824
CH		 845/*
846 * NOTE: ns is NULL when called on the admin queue.
847 */
a4aea562
MB		 848static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
849 const struct blk_mq_queue_data *bd)
edd10d33 850{
a4aea562
MB		 851 struct nvme_ns *ns = hctx->queue->queuedata;
852 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 853 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 854 struct request *req = bd->rq;
855 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 856 struct nvme_iod *iod;
a4aea562 857 enum dma_data_direction dma_dir;
edd10d33 858
e1e5e564
KB		 859 /*
860 * If formated with metadata, require the block layer provide a buffer
861 * unless this namespace is formated such that the metadata can be
862 * stripped/generated by the controller with PRACT=1.
863 */
d29ec824 864 if (ns && ns->ms && !blk_integrity_rq(req)) {
71feb364
KB		 865 if (!(ns->pi_type && ns->ms == 8) &&
866 req->cmd_type != REQ_TYPE_DRV_PRIV) {
e1e5e564
KB		 867 req->errors = -EFAULT;
868 blk_mq_complete_request(req);
869 return BLK_MQ_RQ_QUEUE_OK;
870 }
871 }
872
d29ec824 873 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
edd10d33 874 if (!iod)
fe54303e 875 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 876
a4aea562 877 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 878 void *range;
879 /*
880 * We reuse the small pool to allocate the 16-byte range here
881 * as it is not worth having a special pool for these or
882 * additional cases to handle freeing the iod.
883 */
d29ec824 884 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
edd10d33 885 &iod->first_dma);
a4aea562 886 if (!range)
fe54303e 887 goto retry_cmd;
edd10d33
KB		 888 iod_list(iod)[0] = (__le64 *)range;
889 iod->npages = 0;
ac3dd5bd 890 } else if (req->nr_phys_segments) {
a4aea562
MB		 891 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
892
ac3dd5bd 893 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 894 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 895 if (!iod->nents)
896 goto error_cmd;
a4aea562
MB		 897
898 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 899 goto retry_cmd;
a4aea562 900
fe54303e 901 if (blk_rq_bytes(req) !=
d29ec824
CH		 902 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
903 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
fe54303e
JA		 904 goto retry_cmd;
905 }
e1e5e564
KB		 906 if (blk_integrity_rq(req)) {
907 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
908 goto error_cmd;
909
910 sg_init_table(iod->meta_sg, 1);
911 if (blk_rq_map_integrity_sg(
912 req->q, req->bio, iod->meta_sg) != 1)
913 goto error_cmd;
914
915 if (rq_data_dir(req))
916 nvme_dif_remap(req, nvme_dif_prep);
917
918 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
919 goto error_cmd;
920 }
edd10d33 921 }
1974b1ae 922
9af8785a 923 nvme_set_info(cmd, iod, req_completion);
a4aea562 924 spin_lock_irq(&nvmeq->q_lock);
d29ec824
CH		 925 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
926 nvme_submit_priv(nvmeq, req, iod);
927 else if (req->cmd_flags & REQ_DISCARD)
a4aea562
MB		 928 nvme_submit_discard(nvmeq, ns, req, iod);
929 else if (req->cmd_flags & REQ_FLUSH)
930 nvme_submit_flush(nvmeq, ns, req->tag);
931 else
932 nvme_submit_iod(nvmeq, iod, ns);
933
934 nvme_process_cq(nvmeq);
935 spin_unlock_irq(&nvmeq->q_lock);
936 return BLK_MQ_RQ_QUEUE_OK;
937
fe54303e 938 error_cmd:
d29ec824 939 nvme_free_iod(dev, iod);
fe54303e
JA		 940 return BLK_MQ_RQ_QUEUE_ERROR;
941 retry_cmd:
d29ec824 942 nvme_free_iod(dev, iod);
fe54303e 943 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 944}
945
e9539f47 946static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 947{
82123460 948 u16 head, phase;
b60503ba 949
b60503ba 950 head = nvmeq->cq_head;
82123460 951 phase = nvmeq->cq_phase;
b60503ba
MW		 952
953 for (;;) {
c2f5b650
MW		 954 void *ctx;
955 nvme_completion_fn fn;
b60503ba 956 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 957 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 958 break;
959 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
960 if (++head == nvmeq->q_depth) {
961 head = 0;
82123460 962 phase = !phase;
b60503ba 963 }
a4aea562 964 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 965 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 966 }
967
968 /* If the controller ignores the cq head doorbell and continuously
969 * writes to the queue, it is theoretically possible to wrap around
970 * the queue twice and mistakenly return IRQ_NONE. Linux only
971 * requires that 0.1% of your interrupts are handled, so this isn't
972 * a big problem.
973 */
82123460 974 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 975 return 0;
b60503ba 976
b80d5ccc 977 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 978 nvmeq->cq_head = head;
82123460 979 nvmeq->cq_phase = phase;
b60503ba 980
e9539f47
MW		 981 nvmeq->cqe_seen = 1;
982 return 1;
b60503ba
MW		 983}
984
985static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 986{
987 irqreturn_t result;
988 struct nvme_queue *nvmeq = data;
989 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 990 nvme_process_cq(nvmeq);
991 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
992 nvmeq->cqe_seen = 0;
58ffacb5
MW		 993 spin_unlock(&nvmeq->q_lock);
994 return result;
995}
996
997static irqreturn_t nvme_irq_check(int irq, void *data)
998{
999 struct nvme_queue *nvmeq = data;
1000 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
1001 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
1002 return IRQ_NONE;
1003 return IRQ_WAKE_THREAD;
1004}
1005
b60503ba
MW		 1006/*
1007 * Returns 0 on success. If the result is negative, it's a Linux error code;
1008 * if the result is positive, it's an NVM Express status code
1009 */
d29ec824
CH		 1010int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1011 void *buffer, void __user *ubuffer, unsigned bufflen,
1012 u32 *result, unsigned timeout)
b60503ba 1013{
d29ec824
CH		 1014 bool write = cmd->common.opcode & 1;
1015 struct bio *bio = NULL;
f705f837 1016 struct request *req;
d29ec824 1017 int ret;
b60503ba 1018
d29ec824 1019 req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
f705f837
CH		 1020 if (IS_ERR(req))
1021 return PTR_ERR(req);
b60503ba 1022
d29ec824 1023 req->cmd_type = REQ_TYPE_DRV_PRIV;
e112af0d 1024 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d29ec824
CH		 1025 req->__data_len = 0;
1026 req->__sector = (sector_t) -1;
1027 req->bio = req->biotail = NULL;
b60503ba 1028
f4ff414a 1029 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
a4aea562 1030
d29ec824
CH		 1031 req->cmd = (unsigned char *)cmd;
1032 req->cmd_len = sizeof(struct nvme_command);
a0a931d6 1033 req->special = (void *)0;
b60503ba 1034
d29ec824
CH		 1035 if (buffer && bufflen) {
1036 ret = blk_rq_map_kern(q, req, buffer, bufflen, __GFP_WAIT);
1037 if (ret)
1038 goto out;
1039 } else if (ubuffer && bufflen) {
1040 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen, __GFP_WAIT);
1041 if (ret)
1042 goto out;
1043 bio = req->bio;
1044 }
3c0cf138 1045
d29ec824
CH		 1046 blk_execute_rq(req->q, NULL, req, 0);
1047 if (bio)
1048 blk_rq_unmap_user(bio);
b60503ba 1049 if (result)
a0a931d6 1050 *result = (u32)(uintptr_t)req->special;
d29ec824
CH		 1051 ret = req->errors;
1052 out:
f705f837 1053 blk_mq_free_request(req);
d29ec824 1054 return ret;
f705f837
CH		 1055}
1056
d29ec824
CH		 1057int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1058 void *buffer, unsigned bufflen)
f705f837 1059{
d29ec824 1060 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
b60503ba
MW		 1061}
1062
a4aea562
MB		 1063static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1064{
1065 struct nvme_queue *nvmeq = dev->queues[0];
1066 struct nvme_command c;
1067 struct nvme_cmd_info *cmd_info;
1068 struct request *req;
1069
1efccc9d 1070 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
9f173b33
DC		 1071 if (IS_ERR(req))
1072 return PTR_ERR(req);
a4aea562 1073
c917dfe5 1074 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562 1075 cmd_info = blk_mq_rq_to_pdu(req);
1efccc9d 1076 nvme_set_info(cmd_info, NULL, async_req_completion);
a4aea562
MB		 1077
1078 memset(&c, 0, sizeof(c));
1079 c.common.opcode = nvme_admin_async_event;
1080 c.common.command_id = req->tag;
1081
42483228 1082 blk_mq_free_request(req);
a4aea562
MB		 1083 return __nvme_submit_cmd(nvmeq, &c);
1084}
1085
1086static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 1087 struct nvme_command *cmd,
1088 struct async_cmd_info *cmdinfo, unsigned timeout)
1089{
a4aea562
MB		 1090 struct nvme_queue *nvmeq = dev->queues[0];
1091 struct request *req;
1092 struct nvme_cmd_info *cmd_rq;
4d115420 1093
a4aea562 1094 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 1095 if (IS_ERR(req))
1096 return PTR_ERR(req);
a4aea562
MB		 1097
1098 req->timeout = timeout;
1099 cmd_rq = blk_mq_rq_to_pdu(req);
1100 cmdinfo->req = req;
1101 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 1102 cmdinfo->status = -EINTR;
a4aea562
MB		 1103
1104 cmd->common.command_id = req->tag;
1105
4f5099af 1106 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 1107}
1108
b60503ba
MW		 1109static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1110{
b60503ba
MW		 1111 struct nvme_command c;
1112
1113 memset(&c, 0, sizeof(c));
1114 c.delete_queue.opcode = opcode;
1115 c.delete_queue.qid = cpu_to_le16(id);
1116
d29ec824 1117 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1118}
1119
1120static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1121 struct nvme_queue *nvmeq)
1122{
b60503ba
MW		 1123 struct nvme_command c;
1124 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1125
d29ec824
CH		 1126 /*
1127 * Note: we (ab)use the fact the the prp fields survive if no data
1128 * is attached to the request.
1129 */
b60503ba
MW		 1130 memset(&c, 0, sizeof(c));
1131 c.create_cq.opcode = nvme_admin_create_cq;
1132 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1133 c.create_cq.cqid = cpu_to_le16(qid);
1134 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1135 c.create_cq.cq_flags = cpu_to_le16(flags);
1136 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1137
d29ec824 1138 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1139}
1140
1141static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1142 struct nvme_queue *nvmeq)
1143{
b60503ba
MW		 1144 struct nvme_command c;
1145 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1146
d29ec824
CH		 1147 /*
1148 * Note: we (ab)use the fact the the prp fields survive if no data
1149 * is attached to the request.
1150 */
b60503ba
MW		 1151 memset(&c, 0, sizeof(c));
1152 c.create_sq.opcode = nvme_admin_create_sq;
1153 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1154 c.create_sq.sqid = cpu_to_le16(qid);
1155 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1156 c.create_sq.sq_flags = cpu_to_le16(flags);
1157 c.create_sq.cqid = cpu_to_le16(qid);
1158
d29ec824 1159 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1160}
1161
1162static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1163{
1164 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1165}
1166
1167static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1168{
1169 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1170}
1171
d29ec824 1172int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
bc5fc7e4 1173{
d29ec824
CH		 1174 struct nvme_command c = {
1175 .identify.opcode = nvme_admin_identify,
1176 .identify.cns = cpu_to_le32(1),
1177 };
1178 int error;
bc5fc7e4 1179
d29ec824
CH		 1180 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1181 if (!*id)
1182 return -ENOMEM;
bc5fc7e4 1183
d29ec824
CH		 1184 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1185 sizeof(struct nvme_id_ctrl));
1186 if (error)
1187 kfree(*id);
1188 return error;
1189}
1190
1191int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1192 struct nvme_id_ns **id)
1193{
1194 struct nvme_command c = {
1195 .identify.opcode = nvme_admin_identify,
1196 .identify.nsid = cpu_to_le32(nsid),
1197 };
1198 int error;
bc5fc7e4 1199
d29ec824
CH		 1200 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1201 if (!*id)
1202 return -ENOMEM;
1203
1204 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1205 sizeof(struct nvme_id_ns));
1206 if (error)
1207 kfree(*id);
1208 return error;
bc5fc7e4
MW		 1209}
1210
5d0f6131 1211int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1212 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1213{
1214 struct nvme_command c;
1215
1216 memset(&c, 0, sizeof(c));
1217 c.features.opcode = nvme_admin_get_features;
a42cecce 1218 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1219 c.features.prp1 = cpu_to_le64(dma_addr);
1220 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1221
d29ec824
CH		 1222 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1223 result, 0);
df348139
MW		 1224}
1225
5d0f6131
VV		 1226int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1227 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1228{
1229 struct nvme_command c;
1230
1231 memset(&c, 0, sizeof(c));
1232 c.features.opcode = nvme_admin_set_features;
1233 c.features.prp1 = cpu_to_le64(dma_addr);
1234 c.features.fid = cpu_to_le32(fid);
1235 c.features.dword11 = cpu_to_le32(dword11);
1236
d29ec824
CH		 1237 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1238 result, 0);
1239}
1240
1241int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1242{
1243 struct nvme_command c = {
1244 .common.opcode = nvme_admin_get_log_page,
1245 .common.nsid = cpu_to_le32(0xFFFFFFFF),
1246 .common.cdw10[0] = cpu_to_le32(
1247 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1248 NVME_LOG_SMART),
1249 };
1250 int error;
1251
1252 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1253 if (!*log)
1254 return -ENOMEM;
1255
1256 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1257 sizeof(struct nvme_smart_log));
1258 if (error)
1259 kfree(*log);
1260 return error;
bc5fc7e4
MW		 1261}
1262
c30341dc 1263/**
a4aea562 1264 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1265 *
1266 * Schedule controller reset if the command was already aborted once before and
1267 * still hasn't been returned to the driver, or if this is the admin queue.
1268 */
a4aea562 1269static void nvme_abort_req(struct request *req)
c30341dc 1270{
a4aea562
MB		 1271 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1272 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1273 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1274 struct request *abort_req;
1275 struct nvme_cmd_info *abort_cmd;
1276 struct nvme_command cmd;
c30341dc 1277
a4aea562 1278 if (!nvmeq->qid || cmd_rq->aborted) {
7a509a6b
KB		 1279 unsigned long flags;
1280
1281 spin_lock_irqsave(&dev_list_lock, flags);
c30341dc 1282 if (work_busy(&dev->reset_work))
7a509a6b 1283 goto out;
c30341dc 1284 list_del_init(&dev->node);
e75ec752 1285 dev_warn(dev->dev, "I/O %d QID %d timeout, reset controller\n",
a4aea562 1286 req->tag, nvmeq->qid);
9ca97374 1287 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc 1288 queue_work(nvme_workq, &dev->reset_work);
7a509a6b
KB		 1289 out:
1290 spin_unlock_irqrestore(&dev_list_lock, flags);
c30341dc
KB		 1291 return;
1292 }
1293
1294 if (!dev->abort_limit)
1295 return;
1296
a4aea562
MB		 1297 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1298 false);
9f173b33 1299 if (IS_ERR(abort_req))
c30341dc
KB		 1300 return;
1301
a4aea562
MB		 1302 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1303 nvme_set_info(abort_cmd, abort_req, abort_completion);
1304
c30341dc
KB		 1305 memset(&cmd, 0, sizeof(cmd));
1306 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1307 cmd.abort.cid = req->tag;
c30341dc 1308 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1309 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1310
1311 --dev->abort_limit;
a4aea562 1312 cmd_rq->aborted = 1;
c30341dc 1313
a4aea562 1314 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1315 nvmeq->qid);
a4aea562
MB		 1316 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1317 dev_warn(nvmeq->q_dmadev,
1318 "Could not abort I/O %d QID %d",
1319 req->tag, nvmeq->qid);
c87fd540 1320 blk_mq_free_request(abort_req);
a4aea562 1321 }
c30341dc
KB		 1322}
1323
42483228 1324static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
a09115b2 1325{
a4aea562
MB		 1326 struct nvme_queue *nvmeq = data;
1327 void *ctx;
1328 nvme_completion_fn fn;
1329 struct nvme_cmd_info *cmd;
cef6a948
KB		 1330 struct nvme_completion cqe;
1331
1332 if (!blk_mq_request_started(req))
1333 return;
a09115b2 1334
a4aea562 1335 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1336
a4aea562
MB		 1337 if (cmd->ctx == CMD_CTX_CANCELLED)
1338 return;
1339
cef6a948
KB		 1340 if (blk_queue_dying(req->q))
1341 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1342 else
1343 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1344
1345
a4aea562
MB		 1346 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1347 req->tag, nvmeq->qid);
1348 ctx = cancel_cmd_info(cmd, &fn);
1349 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1350}
1351
a4aea562 1352static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1353{
a4aea562
MB		 1354 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1355 struct nvme_queue *nvmeq = cmd->nvmeq;
1356
1357 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1358 nvmeq->qid);
7a509a6b 1359 spin_lock_irq(&nvmeq->q_lock);
07836e65 1360 nvme_abort_req(req);
7a509a6b 1361 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1362
07836e65
KB		 1363 /*
1364 * The aborted req will be completed on receiving the abort req.
1365 * We enable the timer again. If hit twice, it'll cause a device reset,
1366 * as the device then is in a faulty state.
1367 */
1368 return BLK_EH_RESET_TIMER;
a4aea562 1369}
22404274 1370
a4aea562
MB		 1371static void nvme_free_queue(struct nvme_queue *nvmeq)
1372{
9e866774
MW		 1373 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1374 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1375 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1376 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1377 kfree(nvmeq);
1378}
1379
a1a5ef99 1380static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1381{
1382 int i;
1383
a1a5ef99 1384 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1385 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1386 dev->queue_count--;
a4aea562 1387 dev->queues[i] = NULL;
f435c282 1388 nvme_free_queue(nvmeq);
121c7ad4 1389 }
22404274
KB		 1390}
1391
4d115420
KB		 1392/**
1393 * nvme_suspend_queue - put queue into suspended state
1394 * @nvmeq - queue to suspend
4d115420
KB		 1395 */
1396static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1397{
2b25d981 1398 int vector;
b60503ba 1399
a09115b2 1400 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1401 if (nvmeq->cq_vector == -1) {
1402 spin_unlock_irq(&nvmeq->q_lock);
1403 return 1;
1404 }
1405 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1406 nvmeq->dev->online_queues--;
2b25d981 1407 nvmeq->cq_vector = -1;
a09115b2
MW		 1408 spin_unlock_irq(&nvmeq->q_lock);
1409
6df3dbc8
KB		 1410 if (!nvmeq->qid && nvmeq->dev->admin_q)
1411 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1412
aba2080f
MW		 1413 irq_set_affinity_hint(vector, NULL);
1414 free_irq(vector, nvmeq);
b60503ba 1415
4d115420
KB		 1416 return 0;
1417}
b60503ba 1418
4d115420
KB		 1419static void nvme_clear_queue(struct nvme_queue *nvmeq)
1420{
22404274 1421 spin_lock_irq(&nvmeq->q_lock);
42483228
KB		 1422 if (nvmeq->tags && *nvmeq->tags)
1423 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
22404274 1424 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1425}
1426
4d115420
KB		 1427static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1428{
a4aea562 1429 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1430
1431 if (!nvmeq)
1432 return;
1433 if (nvme_suspend_queue(nvmeq))
1434 return;
1435
0e53d180
KB		 1436 /* Don't tell the adapter to delete the admin queue.
1437 * Don't tell a removed adapter to delete IO queues. */
1438 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1439 adapter_delete_sq(dev, qid);
1440 adapter_delete_cq(dev, qid);
1441 }
07836e65
KB		 1442
1443 spin_lock_irq(&nvmeq->q_lock);
1444 nvme_process_cq(nvmeq);
1445 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1446}
1447
1448static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1449 int depth)
b60503ba 1450{
a4aea562 1451 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1452 if (!nvmeq)
1453 return NULL;
1454
e75ec752 1455 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1456 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1457 if (!nvmeq->cqes)
1458 goto free_nvmeq;
b60503ba 1459
e75ec752 1460 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
b60503ba
MW		 1461 &nvmeq->sq_dma_addr, GFP_KERNEL);
1462 if (!nvmeq->sq_cmds)
1463 goto free_cqdma;
1464
e75ec752 1465 nvmeq->q_dmadev = dev->dev;
091b6092 1466 nvmeq->dev = dev;
3193f07b
MW		 1467 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1468 dev->instance, qid);
b60503ba
MW		 1469 spin_lock_init(&nvmeq->q_lock);
1470 nvmeq->cq_head = 0;
82123460 1471 nvmeq->cq_phase = 1;
b80d5ccc 1472 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1473 nvmeq->q_depth = depth;
c30341dc 1474 nvmeq->qid = qid;
a4aea562 1475 dev->queues[qid] = nvmeq;
b60503ba 1476
36a7e993
JD		 1477 /* make sure queue descriptor is set before queue count, for kthread */
1478 mb();
1479 dev->queue_count++;
1480
b60503ba
MW		 1481 return nvmeq;
1482
1483 free_cqdma:
e75ec752 1484 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1485 nvmeq->cq_dma_addr);
1486 free_nvmeq:
1487 kfree(nvmeq);
1488 return NULL;
1489}
1490
3001082c
MW		 1491static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1492 const char *name)
1493{
58ffacb5
MW		 1494 if (use_threaded_interrupts)
1495 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1496 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1497 name, nvmeq);
3001082c 1498 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1499 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1500}
1501
22404274 1502static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1503{
22404274 1504 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1505
7be50e93 1506 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1507 nvmeq->sq_tail = 0;
1508 nvmeq->cq_head = 0;
1509 nvmeq->cq_phase = 1;
b80d5ccc 1510 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1511 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1512 dev->online_queues++;
7be50e93 1513 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1514}
1515
1516static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1517{
1518 struct nvme_dev *dev = nvmeq->dev;
1519 int result;
3f85d50b 1520
2b25d981 1521 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1522 result = adapter_alloc_cq(dev, qid, nvmeq);
1523 if (result < 0)
22404274 1524 return result;
b60503ba
MW		 1525
1526 result = adapter_alloc_sq(dev, qid, nvmeq);
1527 if (result < 0)
1528 goto release_cq;
1529
3193f07b 1530 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1531 if (result < 0)
1532 goto release_sq;
1533
22404274 1534 nvme_init_queue(nvmeq, qid);
22404274 1535 return result;
b60503ba
MW		 1536
1537 release_sq:
1538 adapter_delete_sq(dev, qid);
1539 release_cq:
1540 adapter_delete_cq(dev, qid);
22404274 1541 return result;
b60503ba
MW		 1542}
1543
ba47e386
MW		 1544static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1545{
1546 unsigned long timeout;
1547 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1548
1549 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1550
1551 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1552 msleep(100);
1553 if (fatal_signal_pending(current))
1554 return -EINTR;
1555 if (time_after(jiffies, timeout)) {
e75ec752 1556 dev_err(dev->dev,
27e8166c
MW		 1557 "Device not ready; aborting %s\n", enabled ?
1558 "initialisation" : "reset");
ba47e386
MW		 1559 return -ENODEV;
1560 }
1561 }
1562
1563 return 0;
1564}
1565
1566/*
1567 * If the device has been passed off to us in an enabled state, just clear
1568 * the enabled bit. The spec says we should set the 'shutdown notification
1569 * bits', but doing so may cause the device to complete commands to the
1570 * admin queue ... and we don't know what memory that might be pointing at!
1571 */
1572static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1573{
01079522
DM		 1574 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1575 dev->ctrl_config &= ~NVME_CC_ENABLE;
1576 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1577
ba47e386
MW		 1578 return nvme_wait_ready(dev, cap, false);
1579}
1580
1581static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1582{
01079522
DM		 1583 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1584 dev->ctrl_config |= NVME_CC_ENABLE;
1585 writel(dev->ctrl_config, &dev->bar->cc);
1586
ba47e386
MW		 1587 return nvme_wait_ready(dev, cap, true);
1588}
1589
1894d8f1
KB		 1590static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1591{
1592 unsigned long timeout;
1894d8f1 1593
01079522
DM		 1594 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1595 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1596
1597 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1598
2484f407 1599 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1600 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1601 NVME_CSTS_SHST_CMPLT) {
1602 msleep(100);
1603 if (fatal_signal_pending(current))
1604 return -EINTR;
1605 if (time_after(jiffies, timeout)) {
e75ec752 1606 dev_err(dev->dev,
1894d8f1
KB		 1607 "Device shutdown incomplete; abort shutdown\n");
1608 return -ENODEV;
1609 }
1610 }
1611
1612 return 0;
1613}
1614
a4aea562 1615static struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1616 .queue_rq = nvme_queue_rq,
a4aea562
MB		 1617 .map_queue = blk_mq_map_queue,
1618 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1619 .exit_hctx = nvme_admin_exit_hctx,
a4aea562
MB		 1620 .init_request = nvme_admin_init_request,
1621 .timeout = nvme_timeout,
1622};
1623
1624static struct blk_mq_ops nvme_mq_ops = {
1625 .queue_rq = nvme_queue_rq,
1626 .map_queue = blk_mq_map_queue,
1627 .init_hctx = nvme_init_hctx,
1628 .init_request = nvme_init_request,
1629 .timeout = nvme_timeout,
1630};
1631
ea191d2f
KB		 1632static void nvme_dev_remove_admin(struct nvme_dev *dev)
1633{
1634 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1635 blk_cleanup_queue(dev->admin_q);
1636 blk_mq_free_tag_set(&dev->admin_tagset);
1637 }
1638}
1639
a4aea562
MB		 1640static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1641{
1642 if (!dev->admin_q) {
1643 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1644 dev->admin_tagset.nr_hw_queues = 1;
1645 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1efccc9d 1646 dev->admin_tagset.reserved_tags = 1;
a4aea562 1647 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1648 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
ac3dd5bd 1649 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1650 dev->admin_tagset.driver_data = dev;
1651
1652 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1653 return -ENOMEM;
1654
1655 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1656 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1657 blk_mq_free_tag_set(&dev->admin_tagset);
1658 return -ENOMEM;
1659 }
ea191d2f
KB		 1660 if (!blk_get_queue(dev->admin_q)) {
1661 nvme_dev_remove_admin(dev);
4af0e21c 1662 dev->admin_q = NULL;
ea191d2f
KB		 1663 return -ENODEV;
1664 }
0fb59cbc
KB		 1665 } else
1666 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1667
1668 return 0;
1669}
1670
8d85fce7 1671static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1672{
ba47e386 1673 int result;
b60503ba 1674 u32 aqa;
ba47e386 1675 u64 cap = readq(&dev->bar->cap);
b60503ba 1676 struct nvme_queue *nvmeq;
1d090624
KB		 1677 unsigned page_shift = PAGE_SHIFT;
1678 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1679 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1680
1681 if (page_shift < dev_page_min) {
e75ec752 1682 dev_err(dev->dev,
1d090624
KB		 1683 "Minimum device page size (%u) too large for "
1684 "host (%u)\n", 1 << dev_page_min,
1685 1 << page_shift);
1686 return -ENODEV;
1687 }
1688 if (page_shift > dev_page_max) {
e75ec752 1689 dev_info(dev->dev,
1d090624
KB		 1690 "Device maximum page size (%u) smaller than "
1691 "host (%u); enabling work-around\n",
1692 1 << dev_page_max, 1 << page_shift);
1693 page_shift = dev_page_max;
1694 }
b60503ba 1695
ba47e386
MW		 1696 result = nvme_disable_ctrl(dev, cap);
1697 if (result < 0)
1698 return result;
b60503ba 1699
a4aea562 1700 nvmeq = dev->queues[0];
cd638946 1701 if (!nvmeq) {
2b25d981 1702 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1703 if (!nvmeq)
1704 return -ENOMEM;
cd638946 1705 }
b60503ba
MW		 1706
1707 aqa = nvmeq->q_depth - 1;
1708 aqa |= aqa << 16;
1709
1d090624
KB		 1710 dev->page_size = 1 << page_shift;
1711
01079522 1712 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1713 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1714 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1715 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1716
1717 writel(aqa, &dev->bar->aqa);
1718 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1719 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1720
ba47e386 1721 result = nvme_enable_ctrl(dev, cap);
025c557a 1722 if (result)
a4aea562
MB		 1723 goto free_nvmeq;
1724
2b25d981 1725 nvmeq->cq_vector = 0;
3193f07b 1726 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1727 if (result)
0fb59cbc 1728 goto free_nvmeq;
025c557a 1729
b60503ba 1730 return result;
a4aea562 1731
a4aea562
MB		 1732 free_nvmeq:
1733 nvme_free_queues(dev, 0);
1734 return result;
b60503ba
MW		 1735}
1736
a53295b6
MW		 1737static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1738{
1739 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1740 struct nvme_user_io io;
1741 struct nvme_command c;
d29ec824 1742 unsigned length, meta_len;
a67a9513 1743 int status, write;
a67a9513
KB		 1744 dma_addr_t meta_dma = 0;
1745 void *meta = NULL;
fec558b5 1746 void __user *metadata;
a53295b6
MW		 1747
1748 if (copy_from_user(&io, uio, sizeof(io)))
1749 return -EFAULT;
6c7d4945
MW		 1750
1751 switch (io.opcode) {
1752 case nvme_cmd_write:
1753 case nvme_cmd_read:
6bbf1acd 1754 case nvme_cmd_compare:
6413214c 1755 break;
6c7d4945 1756 default:
6bbf1acd 1757 return -EINVAL;
6c7d4945
MW		 1758 }
1759
d29ec824
CH		 1760 length = (io.nblocks + 1) << ns->lba_shift;
1761 meta_len = (io.nblocks + 1) * ns->ms;
6a398a3e 1762 metadata = (void __user *)(unsigned long)io.metadata;
d29ec824 1763 write = io.opcode & 1;
a53295b6 1764
71feb364
KB		 1765 if (ns->ext) {
1766 length += meta_len;
1767 meta_len = 0;
a67a9513
KB		 1768 }
1769 if (meta_len) {
d29ec824
CH		 1770 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1771 return -EINVAL;
1772
e75ec752 1773 meta = dma_alloc_coherent(dev->dev, meta_len,
a67a9513 1774 &meta_dma, GFP_KERNEL);
fec558b5 1775
a67a9513
KB		 1776 if (!meta) {
1777 status = -ENOMEM;
1778 goto unmap;
1779 }
1780 if (write) {
fec558b5 1781 if (copy_from_user(meta, metadata, meta_len)) {
a67a9513
KB		 1782 status = -EFAULT;
1783 goto unmap;
1784 }
1785 }
1786 }
1787
a53295b6
MW		 1788 memset(&c, 0, sizeof(c));
1789 c.rw.opcode = io.opcode;
1790 c.rw.flags = io.flags;
6c7d4945 1791 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1792 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1793 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1794 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1795 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1796 c.rw.reftag = cpu_to_le32(io.reftag);
1797 c.rw.apptag = cpu_to_le16(io.apptag);
1798 c.rw.appmask = cpu_to_le16(io.appmask);
a67a9513 1799 c.rw.metadata = cpu_to_le64(meta_dma);
d29ec824
CH		 1800
1801 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
1802 (void __user *)io.addr, length, NULL, 0);
f410c680 1803 unmap:
a67a9513
KB		 1804 if (meta) {
1805 if (status == NVME_SC_SUCCESS && !write) {
fec558b5 1806 if (copy_to_user(metadata, meta, meta_len))
a67a9513
KB		 1807 status = -EFAULT;
1808 }
e75ec752 1809 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
f410c680 1810 }
a53295b6
MW		 1811 return status;
1812}
1813
a4aea562
MB		 1814static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1815 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1816{
7963e521 1817 struct nvme_passthru_cmd cmd;
6ee44cdc 1818 struct nvme_command c;
d29ec824
CH		 1819 unsigned timeout = 0;
1820 int status;
6ee44cdc 1821
6bbf1acd
MW		 1822 if (!capable(CAP_SYS_ADMIN))
1823 return -EACCES;
1824 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1825 return -EFAULT;
6ee44cdc
MW		 1826
1827 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1828 c.common.opcode = cmd.opcode;
1829 c.common.flags = cmd.flags;
1830 c.common.nsid = cpu_to_le32(cmd.nsid);
1831 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1832 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1833 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1834 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1835 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1836 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1837 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1838 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1839
d29ec824
CH		 1840 if (cmd.timeout_ms)
1841 timeout = msecs_to_jiffies(cmd.timeout_ms);
eca18b23 1842
f705f837 1843 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
d29ec824
CH		 1844 NULL, (void __user *)cmd.addr, cmd.data_len,
1845 &cmd.result, timeout);
1846 if (status >= 0) {
1847 if (put_user(cmd.result, &ucmd->result))
1848 return -EFAULT;
6bbf1acd 1849 }
f4f117f6 1850
6ee44cdc
MW		 1851 return status;
1852}
1853
b60503ba
MW		 1854static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1855 unsigned long arg)
1856{
1857 struct nvme_ns *ns = bdev->bd_disk->private_data;
1858
1859 switch (cmd) {
6bbf1acd 1860 case NVME_IOCTL_ID:
c3bfe717 1861 force_successful_syscall_return();
6bbf1acd
MW		 1862 return ns->ns_id;
1863 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1864 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1865 case NVME_IOCTL_IO_CMD:
a4aea562 1866 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1867 case NVME_IOCTL_SUBMIT_IO:
1868 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1869 case SG_GET_VERSION_NUM:
1870 return nvme_sg_get_version_num((void __user *)arg);
1871 case SG_IO:
1872 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1873 default:
1874 return -ENOTTY;
1875 }
1876}
1877
320a3827
KB		 1878#ifdef CONFIG_COMPAT
1879static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1880 unsigned int cmd, unsigned long arg)
1881{
320a3827
KB		 1882 switch (cmd) {
1883 case SG_IO:
e179729a 1884 return -ENOIOCTLCMD;
320a3827
KB		 1885 }
1886 return nvme_ioctl(bdev, mode, cmd, arg);
1887}
1888#else
1889#define nvme_compat_ioctl NULL
1890#endif
1891
9ac27090
KB		 1892static int nvme_open(struct block_device *bdev, fmode_t mode)
1893{
9e60352c
KB		 1894 int ret = 0;
1895 struct nvme_ns *ns;
9ac27090 1896
9e60352c
KB		 1897 spin_lock(&dev_list_lock);
1898 ns = bdev->bd_disk->private_data;
1899 if (!ns)
1900 ret = -ENXIO;
1901 else if (!kref_get_unless_zero(&ns->dev->kref))
1902 ret = -ENXIO;
1903 spin_unlock(&dev_list_lock);
1904
1905 return ret;
9ac27090
KB		 1906}
1907
1908static void nvme_free_dev(struct kref *kref);
1909
1910static void nvme_release(struct gendisk *disk, fmode_t mode)
1911{
1912 struct nvme_ns *ns = disk->private_data;
1913 struct nvme_dev *dev = ns->dev;
1914
1915 kref_put(&dev->kref, nvme_free_dev);
1916}
1917
4cc09e2d
KB		 1918static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1919{
1920 /* some standard values */
1921 geo->heads = 1 << 6;
1922 geo->sectors = 1 << 5;
1923 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1924 return 0;
1925}
1926
e1e5e564
KB		 1927static void nvme_config_discard(struct nvme_ns *ns)
1928{
1929 u32 logical_block_size = queue_logical_block_size(ns->queue);
1930 ns->queue->limits.discard_zeroes_data = 0;
1931 ns->queue->limits.discard_alignment = logical_block_size;
1932 ns->queue->limits.discard_granularity = logical_block_size;
1933 ns->queue->limits.max_discard_sectors = 0xffffffff;
1934 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1935}
1936
1b9dbf7f
KB		 1937static int nvme_revalidate_disk(struct gendisk *disk)
1938{
1939 struct nvme_ns *ns = disk->private_data;
1940 struct nvme_dev *dev = ns->dev;
1941 struct nvme_id_ns *id;
a67a9513
KB		 1942 u8 lbaf, pi_type;
1943 u16 old_ms;
e1e5e564 1944 unsigned short bs;
1b9dbf7f 1945
d29ec824 1946 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
a5768aa8
KB		 1947 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
1948 dev->instance, ns->ns_id);
1949 return -ENODEV;
1b9dbf7f 1950 }
a5768aa8
KB		 1951 if (id->ncap == 0) {
1952 kfree(id);
1953 return -ENODEV;
e1e5e564 1954 }
1b9dbf7f 1955
e1e5e564
KB		 1956 old_ms = ns->ms;
1957 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1b9dbf7f 1958 ns->lba_shift = id->lbaf[lbaf].ds;
e1e5e564 1959 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
a67a9513 1960 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
e1e5e564
KB		 1961
1962 /*
1963 * If identify namespace failed, use default 512 byte block size so
1964 * block layer can use before failing read/write for 0 capacity.
1965 */
1966 if (ns->lba_shift == 0)
1967 ns->lba_shift = 9;
1968 bs = 1 << ns->lba_shift;
1969
1970 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
1971 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
1972 id->dps & NVME_NS_DPS_PI_MASK : 0;
1973
52b68d7e
KB		 1974 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
1975 ns->ms != old_ms ||
e1e5e564 1976 bs != queue_logical_block_size(disk->queue) ||
a67a9513 1977 (ns->ms && ns->ext)))
e1e5e564
KB		 1978 blk_integrity_unregister(disk);
1979
1980 ns->pi_type = pi_type;
1981 blk_queue_logical_block_size(ns->queue, bs);
1982
52b68d7e 1983 if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
a67a9513 1984 !ns->ext)
e1e5e564
KB		 1985 nvme_init_integrity(ns);
1986
a5768aa8 1987 if (ns->ms && !blk_get_integrity(disk))
e1e5e564
KB		 1988 set_capacity(disk, 0);
1989 else
1990 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1991
1992 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1993 nvme_config_discard(ns);
1b9dbf7f 1994
d29ec824 1995 kfree(id);
1b9dbf7f
KB		 1996 return 0;
1997}
1998
b60503ba
MW		 1999static const struct block_device_operations nvme_fops = {
2000 .owner = THIS_MODULE,
2001 .ioctl = nvme_ioctl,
320a3827 2002 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 2003 .open = nvme_open,
2004 .release = nvme_release,
4cc09e2d 2005 .getgeo = nvme_getgeo,
1b9dbf7f 2006 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 2007};
2008
1fa6aead
MW		 2009static int nvme_kthread(void *data)
2010{
d4b4ff8e 2011 struct nvme_dev *dev, *next;
1fa6aead
MW		 2012
2013 while (!kthread_should_stop()) {
564a232c 2014 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 2015 spin_lock(&dev_list_lock);
d4b4ff8e 2016 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 2017 int i;
07836e65 2018 if (readl(&dev->bar->csts) & NVME_CSTS_CFS) {
d4b4ff8e
KB		 2019 if (work_busy(&dev->reset_work))
2020 continue;
2021 list_del_init(&dev->node);
e75ec752 2022 dev_warn(dev->dev,
a4aea562
MB		 2023 "Failed status: %x, reset controller\n",
2024 readl(&dev->bar->csts));
9ca97374 2025 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 2026 queue_work(nvme_workq, &dev->reset_work);
2027 continue;
2028 }
1fa6aead 2029 for (i = 0; i < dev->queue_count; i++) {
a4aea562 2030 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 2031 if (!nvmeq)
2032 continue;
1fa6aead 2033 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 2034 nvme_process_cq(nvmeq);
6fccf938
KB		 2035
2036 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 2037 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 2038 break;
2039 dev->event_limit--;
2040 }
1fa6aead
MW		 2041 spin_unlock_irq(&nvmeq->q_lock);
2042 }
2043 }
2044 spin_unlock(&dev_list_lock);
acb7aa0d 2045 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 2046 }
2047 return 0;
2048}
2049
e1e5e564 2050static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
b60503ba
MW		 2051{
2052 struct nvme_ns *ns;
2053 struct gendisk *disk;
e75ec752 2054 int node = dev_to_node(dev->dev);
b60503ba 2055
a4aea562 2056 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba 2057 if (!ns)
e1e5e564
KB		 2058 return;
2059
a4aea562 2060 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 2061 if (IS_ERR(ns->queue))
b60503ba 2062 goto out_free_ns;
4eeb9215
MW		 2063 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2064 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 2065 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 2066 ns->dev = dev;
2067 ns->queue->queuedata = ns;
2068
a4aea562 2069 disk = alloc_disk_node(0, node);
b60503ba
MW		 2070 if (!disk)
2071 goto out_free_queue;
a4aea562 2072
5aff9382 2073 ns->ns_id = nsid;
b60503ba 2074 ns->disk = disk;
e1e5e564
KB		 2075 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2076 list_add_tail(&ns->list, &dev->namespaces);
2077
e9ef4636 2078 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 2079 if (dev->max_hw_sectors)
2080 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 2081 if (dev->stripe_size)
2082 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2083 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2084 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 2085
2086 disk->major = nvme_major;
469071a3 2087 disk->first_minor = 0;
b60503ba
MW		 2088 disk->fops = &nvme_fops;
2089 disk->private_data = ns;
2090 disk->queue = ns->queue;
b3fffdef 2091 disk->driverfs_dev = dev->device;
469071a3 2092 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2093 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba 2094
e1e5e564
KB		 2095 /*
2096 * Initialize capacity to 0 until we establish the namespace format and
2097 * setup integrity extentions if necessary. The revalidate_disk after
2098 * add_disk allows the driver to register with integrity if the format
2099 * requires it.
2100 */
2101 set_capacity(disk, 0);
a5768aa8
KB		 2102 if (nvme_revalidate_disk(ns->disk))
2103 goto out_free_disk;
2104
e1e5e564
KB		 2105 add_disk(ns->disk);
2106 if (ns->ms)
2107 revalidate_disk(ns->disk);
2108 return;
a5768aa8
KB		 2109 out_free_disk:
2110 kfree(disk);
2111 list_del(&ns->list);
b60503ba
MW		 2112 out_free_queue:
2113 blk_cleanup_queue(ns->queue);
2114 out_free_ns:
2115 kfree(ns);
b60503ba
MW		 2116}
2117
42f61420
KB		 2118static void nvme_create_io_queues(struct nvme_dev *dev)
2119{
a4aea562 2120 unsigned i;
42f61420 2121
a4aea562 2122 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2123 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2124 break;
2125
a4aea562
MB		 2126 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2127 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 2128 break;
2129}
2130
b3b06812 2131static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2132{
2133 int status;
2134 u32 result;
b3b06812 2135 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2136
df348139 2137 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2138 &result);
27e8166c
MW		 2139 if (status < 0)
2140 return status;
2141 if (status > 0) {
e75ec752 2142 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
badc34d4 2143 return 0;
27e8166c 2144 }
b60503ba
MW		 2145 return min(result & 0xffff, result >> 16) + 1;
2146}
2147
9d713c2b
KB		 2148static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2149{
b80d5ccc 2150 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2151}
2152
8d85fce7 2153static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2154{
a4aea562 2155 struct nvme_queue *adminq = dev->queues[0];
e75ec752 2156 struct pci_dev *pdev = to_pci_dev(dev->dev);
42f61420 2157 int result, i, vecs, nr_io_queues, size;
b60503ba 2158
42f61420 2159 nr_io_queues = num_possible_cpus();
b348b7d5 2160 result = set_queue_count(dev, nr_io_queues);
badc34d4 2161 if (result <= 0)
1b23484b 2162 return result;
b348b7d5
MW		 2163 if (result < nr_io_queues)
2164 nr_io_queues = result;
b60503ba 2165
9d713c2b
KB		 2166 size = db_bar_size(dev, nr_io_queues);
2167 if (size > 8192) {
f1938f6e 2168 iounmap(dev->bar);
9d713c2b
KB		 2169 do {
2170 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2171 if (dev->bar)
2172 break;
2173 if (!--nr_io_queues)
2174 return -ENOMEM;
2175 size = db_bar_size(dev, nr_io_queues);
2176 } while (1);
f1938f6e 2177 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2178 adminq->q_db = dev->dbs;
f1938f6e
MW		 2179 }
2180
9d713c2b 2181 /* Deregister the admin queue's interrupt */
3193f07b 2182 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2183
e32efbfc
JA		 2184 /*
2185 * If we enable msix early due to not intx, disable it again before
2186 * setting up the full range we need.
2187 */
2188 if (!pdev->irq)
2189 pci_disable_msix(pdev);
2190
be577fab 2191 for (i = 0; i < nr_io_queues; i++)
1b23484b 2192 dev->entry[i].entry = i;
be577fab
AG		 2193 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2194 if (vecs < 0) {
2195 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2196 if (vecs < 0) {
2197 vecs = 1;
2198 } else {
2199 for (i = 0; i < vecs; i++)
2200 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2201 }
2202 }
2203
063a8096
MW		 2204 /*
2205 * Should investigate if there's a performance win from allocating
2206 * more queues than interrupt vectors; it might allow the submission
2207 * path to scale better, even if the receive path is limited by the
2208 * number of interrupts.
2209 */
2210 nr_io_queues = vecs;
42f61420 2211 dev->max_qid = nr_io_queues;
063a8096 2212
3193f07b 2213 result = queue_request_irq(dev, adminq, adminq->irqname);
a4aea562 2214 if (result)
22404274 2215 goto free_queues;
1b23484b 2216
cd638946 2217 /* Free previously allocated queues that are no longer usable */
42f61420 2218 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2219 nvme_create_io_queues(dev);
9ecdc946 2220
22404274 2221 return 0;
b60503ba 2222
22404274 2223 free_queues:
a1a5ef99 2224 nvme_free_queues(dev, 1);
22404274 2225 return result;
b60503ba
MW		 2226}
2227
a5768aa8
KB		 2228static void nvme_free_namespace(struct nvme_ns *ns)
2229{
2230 list_del(&ns->list);
2231
2232 spin_lock(&dev_list_lock);
2233 ns->disk->private_data = NULL;
2234 spin_unlock(&dev_list_lock);
2235
2236 put_disk(ns->disk);
2237 kfree(ns);
2238}
2239
2240static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2241{
2242 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2243 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2244
2245 return nsa->ns_id - nsb->ns_id;
2246}
2247
2248static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2249{
2250 struct nvme_ns *ns;
2251
2252 list_for_each_entry(ns, &dev->namespaces, list) {
2253 if (ns->ns_id == nsid)
2254 return ns;
2255 if (ns->ns_id > nsid)
2256 break;
2257 }
2258 return NULL;
2259}
2260
2261static inline bool nvme_io_incapable(struct nvme_dev *dev)
2262{
2263 return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
2264 dev->online_queues < 2);
2265}
2266
2267static void nvme_ns_remove(struct nvme_ns *ns)
2268{
2269 bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2270
2271 if (kill)
2272 blk_set_queue_dying(ns->queue);
2273 if (ns->disk->flags & GENHD_FL_UP) {
2274 if (blk_get_integrity(ns->disk))
2275 blk_integrity_unregister(ns->disk);
2276 del_gendisk(ns->disk);
2277 }
2278 if (kill || !blk_queue_dying(ns->queue)) {
2279 blk_mq_abort_requeue_list(ns->queue);
2280 blk_cleanup_queue(ns->queue);
2281 }
2282}
2283
2284static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2285{
2286 struct nvme_ns *ns, *next;
2287 unsigned i;
2288
2289 for (i = 1; i <= nn; i++) {
2290 ns = nvme_find_ns(dev, i);
2291 if (ns) {
2292 if (revalidate_disk(ns->disk)) {
2293 nvme_ns_remove(ns);
2294 nvme_free_namespace(ns);
2295 }
2296 } else
2297 nvme_alloc_ns(dev, i);
2298 }
2299 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2300 if (ns->ns_id > nn) {
2301 nvme_ns_remove(ns);
2302 nvme_free_namespace(ns);
2303 }
2304 }
2305 list_sort(NULL, &dev->namespaces, ns_cmp);
2306}
2307
2308static void nvme_dev_scan(struct work_struct *work)
2309{
2310 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2311 struct nvme_id_ctrl *ctrl;
2312
2313 if (!dev->tagset.tags)
2314 return;
2315 if (nvme_identify_ctrl(dev, &ctrl))
2316 return;
2317 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2318 kfree(ctrl);
2319}
2320
422ef0c7
MW		 2321/*
2322 * Return: error value if an error occurred setting up the queues or calling
2323 * Identify Device. 0 if these succeeded, even if adding some of the
2324 * namespaces failed. At the moment, these failures are silent. TBD which
2325 * failures should be reported.
2326 */
8d85fce7 2327static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2328{
e75ec752 2329 struct pci_dev *pdev = to_pci_dev(dev->dev);
c3bfe717 2330 int res;
a5768aa8 2331 unsigned nn;
51814232 2332 struct nvme_id_ctrl *ctrl;
159b67d7 2333 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2334
d29ec824 2335 res = nvme_identify_ctrl(dev, &ctrl);
b60503ba 2336 if (res) {
e75ec752 2337 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
e1e5e564 2338 return -EIO;
b60503ba
MW		 2339 }
2340
51814232 2341 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2342 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2343 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2344 dev->vwc = ctrl->vwc;
51814232
MW		 2345 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2346 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2347 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2348 if (ctrl->mdts)
8fc23e03 2349 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2350 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2351 (pdev->device == 0x0953) && ctrl->vs[3]) {
2352 unsigned int max_hw_sectors;
2353
159b67d7 2354 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2355 max_hw_sectors = dev->stripe_size >> (shift - 9);
2356 if (dev->max_hw_sectors) {
2357 dev->max_hw_sectors = min(max_hw_sectors,
2358 dev->max_hw_sectors);
2359 } else
2360 dev->max_hw_sectors = max_hw_sectors;
2361 }
d29ec824 2362 kfree(ctrl);
a4aea562 2363
ffe7704d
KB		 2364 if (!dev->tagset.tags) {
2365 dev->tagset.ops = &nvme_mq_ops;
2366 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2367 dev->tagset.timeout = NVME_IO_TIMEOUT;
2368 dev->tagset.numa_node = dev_to_node(dev->dev);
2369 dev->tagset.queue_depth =
a4aea562 2370 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ffe7704d
KB		 2371 dev->tagset.cmd_size = nvme_cmd_size(dev);
2372 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2373 dev->tagset.driver_data = dev;
b60503ba 2374
ffe7704d
KB		 2375 if (blk_mq_alloc_tag_set(&dev->tagset))
2376 return 0;
2377 }
a5768aa8 2378 schedule_work(&dev->scan_work);
e1e5e564 2379 return 0;
b60503ba
MW		 2380}
2381
0877cb0d
KB		 2382static int nvme_dev_map(struct nvme_dev *dev)
2383{
42f61420 2384 u64 cap;
0877cb0d 2385 int bars, result = -ENOMEM;
e75ec752 2386 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2387
2388 if (pci_enable_device_mem(pdev))
2389 return result;
2390
2391 dev->entry[0].vector = pdev->irq;
2392 pci_set_master(pdev);
2393 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2394 if (!bars)
2395 goto disable_pci;
2396
0877cb0d
KB		 2397 if (pci_request_selected_regions(pdev, bars, "nvme"))
2398 goto disable_pci;
2399
e75ec752
CH		 2400 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2401 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2402 goto disable;
0877cb0d 2403
0877cb0d
KB		 2404 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2405 if (!dev->bar)
2406 goto disable;
e32efbfc 2407
0e53d180
KB		 2408 if (readl(&dev->bar->csts) == -1) {
2409 result = -ENODEV;
2410 goto unmap;
2411 }
e32efbfc
JA		 2412
2413 /*
2414 * Some devices don't advertse INTx interrupts, pre-enable a single
2415 * MSIX vec for setup. We'll adjust this later.
2416 */
2417 if (!pdev->irq) {
2418 result = pci_enable_msix(pdev, dev->entry, 1);
2419 if (result < 0)
2420 goto unmap;
2421 }
2422
42f61420
KB		 2423 cap = readq(&dev->bar->cap);
2424 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2425 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2426 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2427
2428 return 0;
2429
0e53d180
KB		 2430 unmap:
2431 iounmap(dev->bar);
2432 dev->bar = NULL;
0877cb0d
KB		 2433 disable:
2434 pci_release_regions(pdev);
2435 disable_pci:
2436 pci_disable_device(pdev);
2437 return result;
2438}
2439
2440static void nvme_dev_unmap(struct nvme_dev *dev)
2441{
e75ec752
CH		 2442 struct pci_dev *pdev = to_pci_dev(dev->dev);
2443
2444 if (pdev->msi_enabled)
2445 pci_disable_msi(pdev);
2446 else if (pdev->msix_enabled)
2447 pci_disable_msix(pdev);
0877cb0d
KB		 2448
2449 if (dev->bar) {
2450 iounmap(dev->bar);
2451 dev->bar = NULL;
e75ec752 2452 pci_release_regions(pdev);
0877cb0d
KB		 2453 }
2454
e75ec752
CH		 2455 if (pci_is_enabled(pdev))
2456 pci_disable_device(pdev);
0877cb0d
KB		 2457}
2458
4d115420
KB		 2459struct nvme_delq_ctx {
2460 struct task_struct *waiter;
2461 struct kthread_worker *worker;
2462 atomic_t refcount;
2463};
2464
2465static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2466{
2467 dq->waiter = current;
2468 mb();
2469
2470 for (;;) {
2471 set_current_state(TASK_KILLABLE);
2472 if (!atomic_read(&dq->refcount))
2473 break;
2474 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2475 fatal_signal_pending(current)) {
0fb59cbc
KB		 2476 /*
2477 * Disable the controller first since we can't trust it
2478 * at this point, but leave the admin queue enabled
2479 * until all queue deletion requests are flushed.
2480 * FIXME: This may take a while if there are more h/w
2481 * queues than admin tags.
2482 */
4d115420 2483 set_current_state(TASK_RUNNING);
4d115420 2484 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2485 nvme_clear_queue(dev->queues[0]);
4d115420 2486 flush_kthread_worker(dq->worker);
0fb59cbc 2487 nvme_disable_queue(dev, 0);
4d115420
KB		 2488 return;
2489 }
2490 }
2491 set_current_state(TASK_RUNNING);
2492}
2493
2494static void nvme_put_dq(struct nvme_delq_ctx *dq)
2495{
2496 atomic_dec(&dq->refcount);
2497 if (dq->waiter)
2498 wake_up_process(dq->waiter);
2499}
2500
2501static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2502{
2503 atomic_inc(&dq->refcount);
2504 return dq;
2505}
2506
2507static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2508{
2509 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
4d115420
KB		 2510 nvme_put_dq(dq);
2511}
2512
2513static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2514 kthread_work_func_t fn)
2515{
2516 struct nvme_command c;
2517
2518 memset(&c, 0, sizeof(c));
2519 c.delete_queue.opcode = opcode;
2520 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2521
2522 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2523 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2524 ADMIN_TIMEOUT);
4d115420
KB		 2525}
2526
2527static void nvme_del_cq_work_handler(struct kthread_work *work)
2528{
2529 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2530 cmdinfo.work);
2531 nvme_del_queue_end(nvmeq);
2532}
2533
2534static int nvme_delete_cq(struct nvme_queue *nvmeq)
2535{
2536 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2537 nvme_del_cq_work_handler);
2538}
2539
2540static void nvme_del_sq_work_handler(struct kthread_work *work)
2541{
2542 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2543 cmdinfo.work);
2544 int status = nvmeq->cmdinfo.status;
2545
2546 if (!status)
2547 status = nvme_delete_cq(nvmeq);
2548 if (status)
2549 nvme_del_queue_end(nvmeq);
2550}
2551
2552static int nvme_delete_sq(struct nvme_queue *nvmeq)
2553{
2554 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2555 nvme_del_sq_work_handler);
2556}
2557
2558static void nvme_del_queue_start(struct kthread_work *work)
2559{
2560 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2561 cmdinfo.work);
4d115420
KB		 2562 if (nvme_delete_sq(nvmeq))
2563 nvme_del_queue_end(nvmeq);
2564}
2565
2566static void nvme_disable_io_queues(struct nvme_dev *dev)
2567{
2568 int i;
2569 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2570 struct nvme_delq_ctx dq;
2571 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2572 &worker, "nvme%d", dev->instance);
2573
2574 if (IS_ERR(kworker_task)) {
e75ec752 2575 dev_err(dev->dev,
4d115420
KB		 2576 "Failed to create queue del task\n");
2577 for (i = dev->queue_count - 1; i > 0; i--)
2578 nvme_disable_queue(dev, i);
2579 return;
2580 }
2581
2582 dq.waiter = NULL;
2583 atomic_set(&dq.refcount, 0);
2584 dq.worker = &worker;
2585 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2586 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2587
2588 if (nvme_suspend_queue(nvmeq))
2589 continue;
2590 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2591 nvmeq->cmdinfo.worker = dq.worker;
2592 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2593 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2594 }
2595 nvme_wait_dq(&dq, dev);
2596 kthread_stop(kworker_task);
2597}
2598
b9afca3e
DM		 2599/*
2600* Remove the node from the device list and check
2601* for whether or not we need to stop the nvme_thread.
2602*/
2603static void nvme_dev_list_remove(struct nvme_dev *dev)
2604{
2605 struct task_struct *tmp = NULL;
2606
2607 spin_lock(&dev_list_lock);
2608 list_del_init(&dev->node);
2609 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2610 tmp = nvme_thread;
2611 nvme_thread = NULL;
2612 }
2613 spin_unlock(&dev_list_lock);
2614
2615 if (tmp)
2616 kthread_stop(tmp);
2617}
2618
c9d3bf88
KB		 2619static void nvme_freeze_queues(struct nvme_dev *dev)
2620{
2621 struct nvme_ns *ns;
2622
2623 list_for_each_entry(ns, &dev->namespaces, list) {
2624 blk_mq_freeze_queue_start(ns->queue);
2625
cddcd72b 2626 spin_lock_irq(ns->queue->queue_lock);
c9d3bf88 2627 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
cddcd72b 2628 spin_unlock_irq(ns->queue->queue_lock);
c9d3bf88
KB		 2629
2630 blk_mq_cancel_requeue_work(ns->queue);
2631 blk_mq_stop_hw_queues(ns->queue);
2632 }
2633}
2634
2635static void nvme_unfreeze_queues(struct nvme_dev *dev)
2636{
2637 struct nvme_ns *ns;
2638
2639 list_for_each_entry(ns, &dev->namespaces, list) {
2640 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2641 blk_mq_unfreeze_queue(ns->queue);
2642 blk_mq_start_stopped_hw_queues(ns->queue, true);
2643 blk_mq_kick_requeue_list(ns->queue);
2644 }
2645}
2646
f0b50732 2647static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2648{
22404274 2649 int i;
7c1b2450 2650 u32 csts = -1;
22404274 2651
b9afca3e 2652 nvme_dev_list_remove(dev);
1fa6aead 2653
c9d3bf88
KB		 2654 if (dev->bar) {
2655 nvme_freeze_queues(dev);
7c1b2450 2656 csts = readl(&dev->bar->csts);
c9d3bf88 2657 }
7c1b2450 2658 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2659 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2660 struct nvme_queue *nvmeq = dev->queues[i];
4d115420 2661 nvme_suspend_queue(nvmeq);
4d115420
KB		 2662 }
2663 } else {
2664 nvme_disable_io_queues(dev);
1894d8f1 2665 nvme_shutdown_ctrl(dev);
4d115420
KB		 2666 nvme_disable_queue(dev, 0);
2667 }
f0b50732 2668 nvme_dev_unmap(dev);
07836e65
KB		 2669
2670 for (i = dev->queue_count - 1; i >= 0; i--)
2671 nvme_clear_queue(dev->queues[i]);
f0b50732
KB		 2672}
2673
2674static void nvme_dev_remove(struct nvme_dev *dev)
2675{
9ac27090 2676 struct nvme_ns *ns;
f0b50732 2677
a5768aa8
KB		 2678 list_for_each_entry(ns, &dev->namespaces, list)
2679 nvme_ns_remove(ns);
b60503ba
MW		 2680}
2681
091b6092
MW		 2682static int nvme_setup_prp_pools(struct nvme_dev *dev)
2683{
e75ec752 2684 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2685 PAGE_SIZE, PAGE_SIZE, 0);
2686 if (!dev->prp_page_pool)
2687 return -ENOMEM;
2688
99802a7a 2689 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2690 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2691 256, 256, 0);
2692 if (!dev->prp_small_pool) {
2693 dma_pool_destroy(dev->prp_page_pool);
2694 return -ENOMEM;
2695 }
091b6092
MW		 2696 return 0;
2697}
2698
2699static void nvme_release_prp_pools(struct nvme_dev *dev)
2700{
2701 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2702 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2703}
2704
cd58ad7d
QSA		 2705static DEFINE_IDA(nvme_instance_ida);
2706
2707static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2708{
cd58ad7d
QSA		 2709 int instance, error;
2710
2711 do {
2712 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2713 return -ENODEV;
2714
2715 spin_lock(&dev_list_lock);
2716 error = ida_get_new(&nvme_instance_ida, &instance);
2717 spin_unlock(&dev_list_lock);
2718 } while (error == -EAGAIN);
2719
2720 if (error)
2721 return -ENODEV;
2722
2723 dev->instance = instance;
2724 return 0;
b60503ba
MW		 2725}
2726
2727static void nvme_release_instance(struct nvme_dev *dev)
2728{
cd58ad7d
QSA		 2729 spin_lock(&dev_list_lock);
2730 ida_remove(&nvme_instance_ida, dev->instance);
2731 spin_unlock(&dev_list_lock);
b60503ba
MW		 2732}
2733
9ac27090
KB		 2734static void nvme_free_namespaces(struct nvme_dev *dev)
2735{
2736 struct nvme_ns *ns, *next;
2737
a5768aa8
KB		 2738 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
2739 nvme_free_namespace(ns);
9ac27090
KB		 2740}
2741
5e82e952
KB		 2742static void nvme_free_dev(struct kref *kref)
2743{
2744 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2745
e75ec752 2746 put_device(dev->dev);
b3fffdef 2747 put_device(dev->device);
9ac27090 2748 nvme_free_namespaces(dev);
285dffc9 2749 nvme_release_instance(dev);
4af0e21c
KB		 2750 if (dev->tagset.tags)
2751 blk_mq_free_tag_set(&dev->tagset);
2752 if (dev->admin_q)
2753 blk_put_queue(dev->admin_q);
5e82e952
KB		 2754 kfree(dev->queues);
2755 kfree(dev->entry);
2756 kfree(dev);
2757}
2758
2759static int nvme_dev_open(struct inode *inode, struct file *f)
2760{
b3fffdef
KB		 2761 struct nvme_dev *dev;
2762 int instance = iminor(inode);
2763 int ret = -ENODEV;
2764
2765 spin_lock(&dev_list_lock);
2766 list_for_each_entry(dev, &dev_list, node) {
2767 if (dev->instance == instance) {
2e1d8448
KB		 2768 if (!dev->admin_q) {
2769 ret = -EWOULDBLOCK;
2770 break;
2771 }
b3fffdef
KB		 2772 if (!kref_get_unless_zero(&dev->kref))
2773 break;
2774 f->private_data = dev;
2775 ret = 0;
2776 break;
2777 }
2778 }
2779 spin_unlock(&dev_list_lock);
2780
2781 return ret;
5e82e952
KB		 2782}
2783
2784static int nvme_dev_release(struct inode *inode, struct file *f)
2785{
2786 struct nvme_dev *dev = f->private_data;
2787 kref_put(&dev->kref, nvme_free_dev);
2788 return 0;
2789}
2790
2791static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2792{
2793 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2794 struct nvme_ns *ns;
2795
5e82e952
KB		 2796 switch (cmd) {
2797 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2798 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2799 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2800 if (list_empty(&dev->namespaces))
2801 return -ENOTTY;
2802 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2803 return nvme_user_cmd(dev, ns, (void __user *)arg);
4cc06521
KB		 2804 case NVME_IOCTL_RESET:
2805 dev_warn(dev->dev, "resetting controller\n");
2806 return nvme_reset(dev);
5e82e952
KB		 2807 default:
2808 return -ENOTTY;
2809 }
2810}
2811
2812static const struct file_operations nvme_dev_fops = {
2813 .owner = THIS_MODULE,
2814 .open = nvme_dev_open,
2815 .release = nvme_dev_release,
2816 .unlocked_ioctl = nvme_dev_ioctl,
2817 .compat_ioctl = nvme_dev_ioctl,
2818};
2819
a4aea562
MB		 2820static void nvme_set_irq_hints(struct nvme_dev *dev)
2821{
2822 struct nvme_queue *nvmeq;
2823 int i;
2824
2825 for (i = 0; i < dev->online_queues; i++) {
2826 nvmeq = dev->queues[i];
2827
42483228 2828 if (!nvmeq->tags || !(*nvmeq->tags))
a4aea562
MB		 2829 continue;
2830
2831 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
42483228 2832 blk_mq_tags_cpumask(*nvmeq->tags));
a4aea562
MB		 2833 }
2834}
2835
f0b50732
KB		 2836static int nvme_dev_start(struct nvme_dev *dev)
2837{
2838 int result;
b9afca3e 2839 bool start_thread = false;
f0b50732
KB		 2840
2841 result = nvme_dev_map(dev);
2842 if (result)
2843 return result;
2844
2845 result = nvme_configure_admin_queue(dev);
2846 if (result)
2847 goto unmap;
2848
2849 spin_lock(&dev_list_lock);
b9afca3e
DM		 2850 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2851 start_thread = true;
2852 nvme_thread = NULL;
2853 }
f0b50732
KB		 2854 list_add(&dev->node, &dev_list);
2855 spin_unlock(&dev_list_lock);
2856
b9afca3e
DM		 2857 if (start_thread) {
2858 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2859 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2860 } else
2861 wait_event_killable(nvme_kthread_wait, nvme_thread);
2862
2863 if (IS_ERR_OR_NULL(nvme_thread)) {
2864 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2865 goto disable;
2866 }
a4aea562
MB		 2867
2868 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 2869 result = nvme_alloc_admin_tags(dev);
2870 if (result)
2871 goto disable;
b9afca3e 2872
f0b50732 2873 result = nvme_setup_io_queues(dev);
badc34d4 2874 if (result)
0fb59cbc 2875 goto free_tags;
f0b50732 2876
a4aea562
MB		 2877 nvme_set_irq_hints(dev);
2878
1efccc9d 2879 dev->event_limit = 1;
d82e8bfd 2880 return result;
f0b50732 2881
0fb59cbc
KB		 2882 free_tags:
2883 nvme_dev_remove_admin(dev);
4af0e21c
KB		 2884 blk_put_queue(dev->admin_q);
2885 dev->admin_q = NULL;
2886 dev->queues[0]->tags = NULL;
f0b50732 2887 disable:
a1a5ef99 2888 nvme_disable_queue(dev, 0);
b9afca3e 2889 nvme_dev_list_remove(dev);
f0b50732
KB		 2890 unmap:
2891 nvme_dev_unmap(dev);
2892 return result;
2893}
2894
9a6b9458
KB		 2895static int nvme_remove_dead_ctrl(void *arg)
2896{
2897 struct nvme_dev *dev = (struct nvme_dev *)arg;
e75ec752 2898 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2899
2900 if (pci_get_drvdata(pdev))
c81f4975 2901 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2902 kref_put(&dev->kref, nvme_free_dev);
2903 return 0;
2904}
2905
2906static void nvme_remove_disks(struct work_struct *ws)
2907{
9a6b9458
KB		 2908 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2909
5a92e700 2910 nvme_free_queues(dev, 1);
302c6727 2911 nvme_dev_remove(dev);
9a6b9458
KB		 2912}
2913
2914static int nvme_dev_resume(struct nvme_dev *dev)
2915{
2916 int ret;
2917
2918 ret = nvme_dev_start(dev);
badc34d4 2919 if (ret)
9a6b9458 2920 return ret;
badc34d4 2921 if (dev->online_queues < 2) {
9a6b9458 2922 spin_lock(&dev_list_lock);
9ca97374 2923 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2924 queue_work(nvme_workq, &dev->reset_work);
2925 spin_unlock(&dev_list_lock);
c9d3bf88
KB		 2926 } else {
2927 nvme_unfreeze_queues(dev);
ffe7704d 2928 nvme_dev_add(dev);
c9d3bf88 2929 nvme_set_irq_hints(dev);
9a6b9458
KB		 2930 }
2931 return 0;
2932}
2933
2934static void nvme_dev_reset(struct nvme_dev *dev)
2935{
ffe7704d
KB		 2936 bool in_probe = work_busy(&dev->probe_work);
2937
9a6b9458 2938 nvme_dev_shutdown(dev);
ffe7704d
KB		 2939
2940 /* Synchronize with device probe so that work will see failure status
2941 * and exit gracefully without trying to schedule another reset */
2942 flush_work(&dev->probe_work);
2943
2944 /* Fail this device if reset occured during probe to avoid
2945 * infinite initialization loops. */
2946 if (in_probe) {
e75ec752 2947 dev_warn(dev->dev, "Device failed to resume\n");
9a6b9458
KB		 2948 kref_get(&dev->kref);
2949 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2950 dev->instance))) {
e75ec752 2951 dev_err(dev->dev,
9a6b9458
KB		 2952 "Failed to start controller remove task\n");
2953 kref_put(&dev->kref, nvme_free_dev);
2954 }
ffe7704d 2955 return;
9a6b9458 2956 }
ffe7704d
KB		 2957 /* Schedule device resume asynchronously so the reset work is available
2958 * to cleanup errors that may occur during reinitialization */
2959 schedule_work(&dev->probe_work);
9a6b9458
KB		 2960}
2961
2962static void nvme_reset_failed_dev(struct work_struct *ws)
2963{
2964 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2965 nvme_dev_reset(dev);
2966}
2967
9ca97374
TH		 2968static void nvme_reset_workfn(struct work_struct *work)
2969{
2970 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2971 dev->reset_workfn(work);
2972}
2973
4cc06521
KB		 2974static int nvme_reset(struct nvme_dev *dev)
2975{
2976 int ret = -EBUSY;
2977
2978 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
2979 return -ENODEV;
2980
2981 spin_lock(&dev_list_lock);
2982 if (!work_pending(&dev->reset_work)) {
2983 dev->reset_workfn = nvme_reset_failed_dev;
2984 queue_work(nvme_workq, &dev->reset_work);
2985 ret = 0;
2986 }
2987 spin_unlock(&dev_list_lock);
2988
2989 if (!ret) {
2990 flush_work(&dev->reset_work);
ffe7704d 2991 flush_work(&dev->probe_work);
4cc06521
KB		 2992 return 0;
2993 }
2994
2995 return ret;
2996}
2997
2998static ssize_t nvme_sysfs_reset(struct device *dev,
2999 struct device_attribute *attr, const char *buf,
3000 size_t count)
3001{
3002 struct nvme_dev *ndev = dev_get_drvdata(dev);
3003 int ret;
3004
3005 ret = nvme_reset(ndev);
3006 if (ret < 0)
3007 return ret;
3008
3009 return count;
3010}
3011static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3012
2e1d8448 3013static void nvme_async_probe(struct work_struct *work);
8d85fce7 3014static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 3015{
a4aea562 3016 int node, result = -ENOMEM;
b60503ba
MW		 3017 struct nvme_dev *dev;
3018
a4aea562
MB		 3019 node = dev_to_node(&pdev->dev);
3020 if (node == NUMA_NO_NODE)
3021 set_dev_node(&pdev->dev, 0);
3022
3023 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3024 if (!dev)
3025 return -ENOMEM;
a4aea562
MB		 3026 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3027 GFP_KERNEL, node);
b60503ba
MW		 3028 if (!dev->entry)
3029 goto free;
a4aea562
MB		 3030 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3031 GFP_KERNEL, node);
b60503ba
MW		 3032 if (!dev->queues)
3033 goto free;
3034
3035 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 3036 dev->reset_workfn = nvme_reset_failed_dev;
3037 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
e75ec752 3038 dev->dev = get_device(&pdev->dev);
9a6b9458 3039 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 3040 result = nvme_set_instance(dev);
3041 if (result)
a96d4f5c 3042 goto put_pci;
b60503ba 3043
091b6092
MW		 3044 result = nvme_setup_prp_pools(dev);
3045 if (result)
0877cb0d 3046 goto release;
091b6092 3047
fb35e914 3048 kref_init(&dev->kref);
b3fffdef
KB		 3049 dev->device = device_create(nvme_class, &pdev->dev,
3050 MKDEV(nvme_char_major, dev->instance),
3051 dev, "nvme%d", dev->instance);
3052 if (IS_ERR(dev->device)) {
3053 result = PTR_ERR(dev->device);
2e1d8448 3054 goto release_pools;
b3fffdef
KB		 3055 }
3056 get_device(dev->device);
4cc06521
KB		 3057 dev_set_drvdata(dev->device, dev);
3058
3059 result = device_create_file(dev->device, &dev_attr_reset_controller);
3060 if (result)
3061 goto put_dev;
740216fc 3062
e6e96d73 3063 INIT_LIST_HEAD(&dev->node);
a5768aa8 3064 INIT_WORK(&dev->scan_work, nvme_dev_scan);
2e1d8448
KB		 3065 INIT_WORK(&dev->probe_work, nvme_async_probe);
3066 schedule_work(&dev->probe_work);
b60503ba
MW		 3067 return 0;
3068
4cc06521
KB		 3069 put_dev:
3070 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3071 put_device(dev->device);
0877cb0d 3072 release_pools:
091b6092 3073 nvme_release_prp_pools(dev);
0877cb0d
KB		 3074 release:
3075 nvme_release_instance(dev);
a96d4f5c 3076 put_pci:
e75ec752 3077 put_device(dev->dev);
b60503ba
MW		 3078 free:
3079 kfree(dev->queues);
3080 kfree(dev->entry);
3081 kfree(dev);
3082 return result;
3083}
3084
2e1d8448
KB		 3085static void nvme_async_probe(struct work_struct *work)
3086{
3087 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
2e1d8448 3088
ffe7704d 3089 if (nvme_dev_resume(dev))
2e1d8448 3090 goto reset;
2e1d8448
KB		 3091 return;
3092 reset:
4cc06521 3093 spin_lock(&dev_list_lock);
07836e65
KB		 3094 if (!work_busy(&dev->reset_work)) {
3095 dev->reset_workfn = nvme_reset_failed_dev;
3096 queue_work(nvme_workq, &dev->reset_work);
3097 }
4cc06521 3098 spin_unlock(&dev_list_lock);
2e1d8448
KB		 3099}
3100
f0d54a54
KB		 3101static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3102{
a6739479 3103 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 3104
a6739479
KB		 3105 if (prepare)
3106 nvme_dev_shutdown(dev);
3107 else
3108 nvme_dev_resume(dev);
f0d54a54
KB		 3109}
3110
09ece142
KB		 3111static void nvme_shutdown(struct pci_dev *pdev)
3112{
3113 struct nvme_dev *dev = pci_get_drvdata(pdev);
3114 nvme_dev_shutdown(dev);
3115}
3116
8d85fce7 3117static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3118{
3119 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 3120
3121 spin_lock(&dev_list_lock);
3122 list_del_init(&dev->node);
3123 spin_unlock(&dev_list_lock);
3124
3125 pci_set_drvdata(pdev, NULL);
2e1d8448 3126 flush_work(&dev->probe_work);
9a6b9458 3127 flush_work(&dev->reset_work);
a5768aa8 3128 flush_work(&dev->scan_work);
4cc06521 3129 device_remove_file(dev->device, &dev_attr_reset_controller);
9a6b9458 3130 nvme_dev_shutdown(dev);
c9d3bf88 3131 nvme_dev_remove(dev);
a4aea562 3132 nvme_dev_remove_admin(dev);
b3fffdef 3133 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
a1a5ef99 3134 nvme_free_queues(dev, 0);
9a6b9458 3135 nvme_release_prp_pools(dev);
5e82e952 3136 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 3137}
3138
3139/* These functions are yet to be implemented */
3140#define nvme_error_detected NULL
3141#define nvme_dump_registers NULL
3142#define nvme_link_reset NULL
3143#define nvme_slot_reset NULL
3144#define nvme_error_resume NULL
cd638946 3145
671a6018 3146#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3147static int nvme_suspend(struct device *dev)
3148{
3149 struct pci_dev *pdev = to_pci_dev(dev);
3150 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3151
3152 nvme_dev_shutdown(ndev);
3153 return 0;
3154}
3155
3156static int nvme_resume(struct device *dev)
3157{
3158 struct pci_dev *pdev = to_pci_dev(dev);
3159 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3160
9a6b9458 3161 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 3162 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 3163 queue_work(nvme_workq, &ndev->reset_work);
3164 }
3165 return 0;
cd638946 3166}
671a6018 3167#endif
cd638946
KB		 3168
3169static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 3170
1d352035 3171static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 3172 .error_detected = nvme_error_detected,
3173 .mmio_enabled = nvme_dump_registers,
3174 .link_reset = nvme_link_reset,
3175 .slot_reset = nvme_slot_reset,
3176 .resume = nvme_error_resume,
f0d54a54 3177 .reset_notify = nvme_reset_notify,
b60503ba
MW		 3178};
3179
3180/* Move to pci_ids.h later */
3181#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3182
6eb0d698 3183static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 3184 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3185 { 0, }
3186};
3187MODULE_DEVICE_TABLE(pci, nvme_id_table);
3188
3189static struct pci_driver nvme_driver = {
3190 .name = "nvme",
3191 .id_table = nvme_id_table,
3192 .probe = nvme_probe,
8d85fce7 3193 .remove = nvme_remove,
09ece142 3194 .shutdown = nvme_shutdown,
cd638946
KB		 3195 .driver = {
3196 .pm = &nvme_dev_pm_ops,
3197 },
b60503ba
MW		 3198 .err_handler = &nvme_err_handler,
3199};
3200
3201static int __init nvme_init(void)
3202{
0ac13140 3203 int result;
1fa6aead 3204
b9afca3e 3205 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3206
9a6b9458
KB		 3207 nvme_workq = create_singlethread_workqueue("nvme");
3208 if (!nvme_workq)
b9afca3e 3209 return -ENOMEM;
9a6b9458 3210
5c42ea16
KB		 3211 result = register_blkdev(nvme_major, "nvme");
3212 if (result < 0)
9a6b9458 3213 goto kill_workq;
5c42ea16 3214 else if (result > 0)
0ac13140 3215 nvme_major = result;
b60503ba 3216
b3fffdef
KB		 3217 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3218 &nvme_dev_fops);
3219 if (result < 0)
3220 goto unregister_blkdev;
3221 else if (result > 0)
3222 nvme_char_major = result;
3223
3224 nvme_class = class_create(THIS_MODULE, "nvme");
c727040b
AK		 3225 if (IS_ERR(nvme_class)) {
3226 result = PTR_ERR(nvme_class);
b3fffdef 3227 goto unregister_chrdev;
c727040b 3228 }
b3fffdef 3229
f3db22fe
KB		 3230 result = pci_register_driver(&nvme_driver);
3231 if (result)
b3fffdef 3232 goto destroy_class;
1fa6aead 3233 return 0;
b60503ba 3234
b3fffdef
KB		 3235 destroy_class:
3236 class_destroy(nvme_class);
3237 unregister_chrdev:
3238 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1fa6aead 3239 unregister_blkdev:
b60503ba 3240 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3241 kill_workq:
3242 destroy_workqueue(nvme_workq);
b60503ba
MW		 3243 return result;
3244}
3245
3246static void __exit nvme_exit(void)
3247{
3248 pci_unregister_driver(&nvme_driver);
3249 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3250 destroy_workqueue(nvme_workq);
b3fffdef
KB		 3251 class_destroy(nvme_class);
3252 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
b9afca3e 3253 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3254 _nvme_check_size();
b60503ba
MW		 3255}
3256
3257MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3258MODULE_LICENSE("GPL");
c78b4713 3259MODULE_VERSION("1.0");
b60503ba
MW		 3260module_init(nvme_init);
3261module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)