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Merge branch 'thermal-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang...
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
40#include <linux/types.h>
5d0f6131 41#include <scsi/sg.h>
797a796a
HM		 42#include <asm-generic/io-64-nonatomic-lo-hi.h>
43
9d43cf64 44#define NVME_Q_DEPTH 1024
a4aea562 45#define NVME_AQ_DEPTH 64
b60503ba
MW		 46#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 48#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 49#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 50#define IOD_TIMEOUT (retry_time * HZ)
51
52static unsigned char admin_timeout = 60;
53module_param(admin_timeout, byte, 0644);
54MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 55
bd67608a
MW		 56unsigned char nvme_io_timeout = 30;
57module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 58MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 59
61e4ce08
KB		 60static unsigned char retry_time = 30;
61module_param(retry_time, byte, 0644);
62MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
63
2484f407
DM		 64static unsigned char shutdown_timeout = 5;
65module_param(shutdown_timeout, byte, 0644);
66MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
67
b60503ba
MW		 68static int nvme_major;
69module_param(nvme_major, int, 0);
70
58ffacb5
MW		 71static int use_threaded_interrupts;
72module_param(use_threaded_interrupts, int, 0);
73
1fa6aead
MW		 74static DEFINE_SPINLOCK(dev_list_lock);
75static LIST_HEAD(dev_list);
76static struct task_struct *nvme_thread;
9a6b9458 77static struct workqueue_struct *nvme_workq;
b9afca3e 78static wait_queue_head_t nvme_kthread_wait;
f3db22fe 79static struct notifier_block nvme_nb;
1fa6aead 80
d4b4ff8e 81static void nvme_reset_failed_dev(struct work_struct *ws);
a4aea562 82static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 83
4d115420
KB		 84struct async_cmd_info {
85 struct kthread_work work;
86 struct kthread_worker *worker;
a4aea562 87 struct request *req;
4d115420
KB		 88 u32 result;
89 int status;
90 void *ctx;
91};
1fa6aead 92
b60503ba
MW		 93/*
94 * An NVM Express queue. Each device has at least two (one for admin
95 * commands and one for I/O commands).
96 */
97struct nvme_queue {
f435c282 98 struct llist_node node;
b60503ba 99 struct device *q_dmadev;
091b6092 100 struct nvme_dev *dev;
3193f07b 101 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 102 spinlock_t q_lock;
103 struct nvme_command *sq_cmds;
104 volatile struct nvme_completion *cqes;
105 dma_addr_t sq_dma_addr;
106 dma_addr_t cq_dma_addr;
b60503ba
MW		 107 u32 __iomem *q_db;
108 u16 q_depth;
109 u16 cq_vector;
110 u16 sq_head;
111 u16 sq_tail;
112 u16 cq_head;
c30341dc 113 u16 qid;
e9539f47
MW		 114 u8 cq_phase;
115 u8 cqe_seen;
4d115420 116 struct async_cmd_info cmdinfo;
a4aea562 117 struct blk_mq_hw_ctx *hctx;
b60503ba
MW		 118};
119
120/*
121 * Check we didin't inadvertently grow the command struct
122 */
123static inline void _nvme_check_size(void)
124{
125 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 130 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 131 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 136 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 137}
138
edd10d33 139typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 140 struct nvme_completion *);
141
e85248e5 142struct nvme_cmd_info {
c2f5b650
MW		 143 nvme_completion_fn fn;
144 void *ctx;
c30341dc 145 int aborted;
a4aea562 146 struct nvme_queue *nvmeq;
e85248e5
MW		 147};
148
a4aea562
MB		 149static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
150 unsigned int hctx_idx)
e85248e5 151{
a4aea562
MB		 152 struct nvme_dev *dev = data;
153 struct nvme_queue *nvmeq = dev->queues[0];
154
155 WARN_ON(nvmeq->hctx);
156 nvmeq->hctx = hctx;
157 hctx->driver_data = nvmeq;
158 return 0;
e85248e5
MW		 159}
160
a4aea562
MB		 161static int nvme_admin_init_request(void *data, struct request *req,
162 unsigned int hctx_idx, unsigned int rq_idx,
163 unsigned int numa_node)
22404274 164{
a4aea562
MB		 165 struct nvme_dev *dev = data;
166 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
167 struct nvme_queue *nvmeq = dev->queues[0];
168
169 BUG_ON(!nvmeq);
170 cmd->nvmeq = nvmeq;
171 return 0;
22404274
KB		 172}
173
2c30540b
JA		 174static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
175{
176 struct nvme_queue *nvmeq = hctx->driver_data;
177
178 nvmeq->hctx = NULL;
179}
180
a4aea562
MB		 181static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
182 unsigned int hctx_idx)
b60503ba 183{
a4aea562
MB		 184 struct nvme_dev *dev = data;
185 struct nvme_queue *nvmeq = dev->queues[
186 (hctx_idx % dev->queue_count) + 1];
b60503ba 187
a4aea562
MB		 188 if (!nvmeq->hctx)
189 nvmeq->hctx = hctx;
190
191 /* nvmeq queues are shared between namespaces. We assume here that
192 * blk-mq map the tags so they match up with the nvme queue tags. */
193 WARN_ON(nvmeq->hctx->tags != hctx->tags);
b60503ba 194
a4aea562
MB		 195 hctx->driver_data = nvmeq;
196 return 0;
b60503ba
MW		 197}
198
a4aea562
MB		 199static int nvme_init_request(void *data, struct request *req,
200 unsigned int hctx_idx, unsigned int rq_idx,
201 unsigned int numa_node)
b60503ba 202{
a4aea562
MB		 203 struct nvme_dev *dev = data;
204 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
205 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
206
207 BUG_ON(!nvmeq);
208 cmd->nvmeq = nvmeq;
209 return 0;
210}
211
212static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
213 nvme_completion_fn handler)
214{
215 cmd->fn = handler;
216 cmd->ctx = ctx;
217 cmd->aborted = 0;
c917dfe5 218 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 219}
220
c2f5b650
MW		 221/* Special values must be less than 0x1000 */
222#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 223#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
224#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
225#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 226
edd10d33 227static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 228 struct nvme_completion *cqe)
229{
230 if (ctx == CMD_CTX_CANCELLED)
231 return;
c2f5b650 232 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 233 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 234 "completed id %d twice on queue %d\n",
235 cqe->command_id, le16_to_cpup(&cqe->sq_id));
236 return;
237 }
238 if (ctx == CMD_CTX_INVALID) {
edd10d33 239 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 240 "invalid id %d completed on queue %d\n",
241 cqe->command_id, le16_to_cpup(&cqe->sq_id));
242 return;
243 }
edd10d33 244 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 245}
246
a4aea562 247static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 248{
c2f5b650 249 void *ctx;
b60503ba 250
859361a2 251 if (fn)
a4aea562
MB		 252 *fn = cmd->fn;
253 ctx = cmd->ctx;
254 cmd->fn = special_completion;
255 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 256 return ctx;
b60503ba
MW		 257}
258
a4aea562
MB		 259static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
260 struct nvme_completion *cqe)
3c0cf138 261{
a4aea562 262 struct request *req = ctx;
3c0cf138 263
a4aea562
MB		 264 u32 result = le32_to_cpup(&cqe->result);
265 u16 status = le16_to_cpup(&cqe->status) >> 1;
266
267 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
268 ++nvmeq->dev->event_limit;
269 if (status == NVME_SC_SUCCESS)
270 dev_warn(nvmeq->q_dmadev,
271 "async event result %08x\n", result);
272
9d135bb8 273 blk_mq_free_hctx_request(nvmeq->hctx, req);
b60503ba
MW		 274}
275
a4aea562
MB		 276static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
277 struct nvme_completion *cqe)
5a92e700 278{
a4aea562
MB		 279 struct request *req = ctx;
280
281 u16 status = le16_to_cpup(&cqe->status) >> 1;
282 u32 result = le32_to_cpup(&cqe->result);
a51afb54 283
9d135bb8 284 blk_mq_free_hctx_request(nvmeq->hctx, req);
a51afb54 285
a4aea562
MB		 286 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
287 ++nvmeq->dev->abort_limit;
5a92e700
KB		 288}
289
a4aea562
MB		 290static void async_completion(struct nvme_queue *nvmeq, void *ctx,
291 struct nvme_completion *cqe)
b60503ba 292{
a4aea562
MB		 293 struct async_cmd_info *cmdinfo = ctx;
294 cmdinfo->result = le32_to_cpup(&cqe->result);
295 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
296 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
9d135bb8 297 blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
b60503ba
MW		 298}
299
a4aea562
MB		 300static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
301 unsigned int tag)
b60503ba 302{
a4aea562
MB		 303 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
304 struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
a51afb54 305
a4aea562 306 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 307}
308
a4aea562
MB		 309/*
310 * Called with local interrupts disabled and the q_lock held. May not sleep.
311 */
312static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
313 nvme_completion_fn *fn)
4f5099af 314{
a4aea562
MB		 315 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
316 void *ctx;
317 if (tag >= nvmeq->q_depth) {
318 *fn = special_completion;
319 return CMD_CTX_INVALID;
320 }
321 if (fn)
322 *fn = cmd->fn;
323 ctx = cmd->ctx;
324 cmd->fn = special_completion;
325 cmd->ctx = CMD_CTX_COMPLETED;
326 return ctx;
b60503ba
MW		 327}
328
329/**
714a7a22 330 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 331 * @nvmeq: The queue to use
332 * @cmd: The command to send
333 *
334 * Safe to use from interrupt context
335 */
a4aea562 336static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 337{
a4aea562
MB		 338 u16 tail = nvmeq->sq_tail;
339
b60503ba 340 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 341 if (++tail == nvmeq->q_depth)
342 tail = 0;
7547881d 343 writel(tail, nvmeq->q_db);
b60503ba 344 nvmeq->sq_tail = tail;
b60503ba
MW		 345
346 return 0;
347}
348
a4aea562
MB		 349static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
350{
351 unsigned long flags;
352 int ret;
353 spin_lock_irqsave(&nvmeq->q_lock, flags);
354 ret = __nvme_submit_cmd(nvmeq, cmd);
355 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
356 return ret;
357}
358
eca18b23 359static __le64 **iod_list(struct nvme_iod *iod)
e025344c 360{
eca18b23 361 return ((void *)iod) + iod->offset;
e025344c
SMM		 362}
363
eca18b23
MW		 364/*
365 * Will slightly overestimate the number of pages needed. This is OK
366 * as it only leads to a small amount of wasted memory for the lifetime of
367 * the I/O.
368 */
1d090624 369static int nvme_npages(unsigned size, struct nvme_dev *dev)
eca18b23 370{
1d090624
KB		 371 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
372 return DIV_ROUND_UP(8 * nprps, dev->page_size - 8);
eca18b23 373}
b60503ba 374
eca18b23 375static struct nvme_iod *
1d090624 376nvme_alloc_iod(unsigned nseg, unsigned nbytes, struct nvme_dev *dev, gfp_t gfp)
b60503ba 377{
eca18b23 378 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
1d090624 379 sizeof(__le64 *) * nvme_npages(nbytes, dev) +
eca18b23
MW		 380 sizeof(struct scatterlist) * nseg, gfp);
381
382 if (iod) {
383 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
384 iod->npages = -1;
385 iod->length = nbytes;
2b196034 386 iod->nents = 0;
edd10d33 387 iod->first_dma = 0ULL;
eca18b23
MW		 388 }
389
390 return iod;
b60503ba
MW		 391}
392
5d0f6131 393void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 394{
1d090624 395 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 396 int i;
397 __le64 **list = iod_list(iod);
398 dma_addr_t prp_dma = iod->first_dma;
399
400 if (iod->npages == 0)
401 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
402 for (i = 0; i < iod->npages; i++) {
403 __le64 *prp_list = list[i];
404 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
405 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
406 prp_dma = next_prp_dma;
407 }
408 kfree(iod);
b60503ba
MW		 409}
410
b4ff9c8d
KB		 411static int nvme_error_status(u16 status)
412{
413 switch (status & 0x7ff) {
414 case NVME_SC_SUCCESS:
415 return 0;
416 case NVME_SC_CAP_EXCEEDED:
417 return -ENOSPC;
418 default:
419 return -EIO;
420 }
421}
422
a4aea562 423static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 424 struct nvme_completion *cqe)
425{
eca18b23 426 struct nvme_iod *iod = ctx;
a4aea562
MB		 427 struct request *req = iod->private;
428 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
429
b60503ba
MW		 430 u16 status = le16_to_cpup(&cqe->status) >> 1;
431
edd10d33 432 if (unlikely(status)) {
a4aea562
MB		 433 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
434 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 435 unsigned long flags;
436
a4aea562 437 blk_mq_requeue_request(req);
c9d3bf88
KB		 438 spin_lock_irqsave(req->q->queue_lock, flags);
439 if (!blk_queue_stopped(req->q))
440 blk_mq_kick_requeue_list(req->q);
441 spin_unlock_irqrestore(req->q->queue_lock, flags);
edd10d33
KB		 442 return;
443 }
a4aea562
MB		 444 req->errors = nvme_error_status(status);
445 } else
446 req->errors = 0;
447
448 if (cmd_rq->aborted)
449 dev_warn(&nvmeq->dev->pci_dev->dev,
450 "completing aborted command with status:%04x\n",
451 status);
452
453 if (iod->nents)
454 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
455 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
edd10d33 456 nvme_free_iod(nvmeq->dev, iod);
3291fa57 457
a4aea562 458 blk_mq_complete_request(req);
b60503ba
MW		 459}
460
184d2944 461/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 462int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
463 gfp_t gfp)
ff22b54f 464{
99802a7a 465 struct dma_pool *pool;
eca18b23
MW		 466 int length = total_len;
467 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 468 int dma_len = sg_dma_len(sg);
469 u64 dma_addr = sg_dma_address(sg);
470 int offset = offset_in_page(dma_addr);
e025344c 471 __le64 *prp_list;
eca18b23 472 __le64 **list = iod_list(iod);
e025344c 473 dma_addr_t prp_dma;
eca18b23 474 int nprps, i;
1d090624 475 u32 page_size = dev->page_size;
ff22b54f 476
1d090624 477 length -= (page_size - offset);
ff22b54f 478 if (length <= 0)
eca18b23 479 return total_len;
ff22b54f 480
1d090624 481 dma_len -= (page_size - offset);
ff22b54f 482 if (dma_len) {
1d090624 483 dma_addr += (page_size - offset);
ff22b54f
MW		 484 } else {
485 sg = sg_next(sg);
486 dma_addr = sg_dma_address(sg);
487 dma_len = sg_dma_len(sg);
488 }
489
1d090624 490 if (length <= page_size) {
edd10d33 491 iod->first_dma = dma_addr;
eca18b23 492 return total_len;
e025344c
SMM		 493 }
494
1d090624 495 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 496 if (nprps <= (256 / 8)) {
497 pool = dev->prp_small_pool;
eca18b23 498 iod->npages = 0;
99802a7a
MW		 499 } else {
500 pool = dev->prp_page_pool;
eca18b23 501 iod->npages = 1;
99802a7a
MW		 502 }
503
b77954cb
MW		 504 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
505 if (!prp_list) {
edd10d33 506 iod->first_dma = dma_addr;
eca18b23 507 iod->npages = -1;
1d090624 508 return (total_len - length) + page_size;
b77954cb 509 }
eca18b23
MW		 510 list[0] = prp_list;
511 iod->first_dma = prp_dma;
e025344c
SMM		 512 i = 0;
513 for (;;) {
1d090624 514 if (i == page_size >> 3) {
e025344c 515 __le64 *old_prp_list = prp_list;
b77954cb 516 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 517 if (!prp_list)
518 return total_len - length;
519 list[iod->npages++] = prp_list;
7523d834
MW		 520 prp_list[0] = old_prp_list[i - 1];
521 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
522 i = 1;
e025344c
SMM		 523 }
524 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 525 dma_len -= page_size;
526 dma_addr += page_size;
527 length -= page_size;
e025344c
SMM		 528 if (length <= 0)
529 break;
530 if (dma_len > 0)
531 continue;
532 BUG_ON(dma_len < 0);
533 sg = sg_next(sg);
534 dma_addr = sg_dma_address(sg);
535 dma_len = sg_dma_len(sg);
ff22b54f
MW		 536 }
537
eca18b23 538 return total_len;
ff22b54f
MW		 539}
540
a4aea562
MB		 541/*
542 * We reuse the small pool to allocate the 16-byte range here as it is not
543 * worth having a special pool for these or additional cases to handle freeing
544 * the iod.
545 */
546static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
547 struct request *req, struct nvme_iod *iod)
0e5e4f0e 548{
edd10d33
KB		 549 struct nvme_dsm_range *range =
550 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 551 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
552
0e5e4f0e 553 range->cattr = cpu_to_le32(0);
a4aea562
MB		 554 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
555 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e
KB		 556
557 memset(cmnd, 0, sizeof(*cmnd));
558 cmnd->dsm.opcode = nvme_cmd_dsm;
a4aea562 559 cmnd->dsm.command_id = req->tag;
0e5e4f0e
KB		 560 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
561 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
562 cmnd->dsm.nr = 0;
563 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
564
565 if (++nvmeq->sq_tail == nvmeq->q_depth)
566 nvmeq->sq_tail = 0;
567 writel(nvmeq->sq_tail, nvmeq->q_db);
0e5e4f0e
KB		 568}
569
a4aea562 570static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 571 int cmdid)
572{
573 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
574
575 memset(cmnd, 0, sizeof(*cmnd));
576 cmnd->common.opcode = nvme_cmd_flush;
577 cmnd->common.command_id = cmdid;
578 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
579
580 if (++nvmeq->sq_tail == nvmeq->q_depth)
581 nvmeq->sq_tail = 0;
582 writel(nvmeq->sq_tail, nvmeq->q_db);
00df5cb4
MW		 583}
584
a4aea562
MB		 585static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
586 struct nvme_ns *ns)
b60503ba 587{
a4aea562 588 struct request *req = iod->private;
ff22b54f 589 struct nvme_command *cmnd;
a4aea562
MB		 590 u16 control = 0;
591 u32 dsmgmt = 0;
00df5cb4 592
a4aea562 593 if (req->cmd_flags & REQ_FUA)
b60503ba 594 control |= NVME_RW_FUA;
a4aea562 595 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 596 control |= NVME_RW_LR;
597
a4aea562 598 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 599 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
600
ff22b54f 601 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 602 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 603
a4aea562
MB		 604 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
605 cmnd->rw.command_id = req->tag;
ff22b54f 606 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 607 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
608 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
a4aea562
MB		 609 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
610 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
ff22b54f
MW		 611 cmnd->rw.control = cpu_to_le16(control);
612 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 613
b60503ba
MW		 614 if (++nvmeq->sq_tail == nvmeq->q_depth)
615 nvmeq->sq_tail = 0;
7547881d 616 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 617
1974b1ae 618 return 0;
edd10d33
KB		 619}
620
a4aea562
MB		 621static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
622 const struct blk_mq_queue_data *bd)
edd10d33 623{
a4aea562
MB		 624 struct nvme_ns *ns = hctx->queue->queuedata;
625 struct nvme_queue *nvmeq = hctx->driver_data;
626 struct request *req = bd->rq;
627 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 628 struct nvme_iod *iod;
a4aea562 629 int psegs = req->nr_phys_segments;
a4aea562
MB		 630 enum dma_data_direction dma_dir;
631 unsigned size = !(req->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(req) :
9dbbfab7 632 sizeof(struct nvme_dsm_range);
edd10d33 633
9dbbfab7 634 iod = nvme_alloc_iod(psegs, size, ns->dev, GFP_ATOMIC);
edd10d33 635 if (!iod)
fe54303e 636 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562
MB		 637
638 iod->private = req;
edd10d33 639
a4aea562 640 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 641 void *range;
642 /*
643 * We reuse the small pool to allocate the 16-byte range here
644 * as it is not worth having a special pool for these or
645 * additional cases to handle freeing the iod.
646 */
647 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
648 GFP_ATOMIC,
649 &iod->first_dma);
a4aea562 650 if (!range)
fe54303e 651 goto retry_cmd;
edd10d33
KB		 652 iod_list(iod)[0] = (__le64 *)range;
653 iod->npages = 0;
654 } else if (psegs) {
a4aea562
MB		 655 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
656
657 sg_init_table(iod->sg, psegs);
658 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 659 if (!iod->nents)
660 goto error_cmd;
a4aea562
MB		 661
662 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 663 goto retry_cmd;
a4aea562 664
fe54303e
JA		 665 if (blk_rq_bytes(req) !=
666 nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
667 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg,
668 iod->nents, dma_dir);
669 goto retry_cmd;
670 }
edd10d33 671 }
1974b1ae 672
9af8785a 673 nvme_set_info(cmd, iod, req_completion);
a4aea562
MB		 674 spin_lock_irq(&nvmeq->q_lock);
675 if (req->cmd_flags & REQ_DISCARD)
676 nvme_submit_discard(nvmeq, ns, req, iod);
677 else if (req->cmd_flags & REQ_FLUSH)
678 nvme_submit_flush(nvmeq, ns, req->tag);
679 else
680 nvme_submit_iod(nvmeq, iod, ns);
681
682 nvme_process_cq(nvmeq);
683 spin_unlock_irq(&nvmeq->q_lock);
684 return BLK_MQ_RQ_QUEUE_OK;
685
fe54303e
JA		 686 error_cmd:
687 nvme_free_iod(nvmeq->dev, iod);
688 return BLK_MQ_RQ_QUEUE_ERROR;
689 retry_cmd:
eca18b23 690 nvme_free_iod(nvmeq->dev, iod);
fe54303e 691 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 692}
693
e9539f47 694static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 695{
82123460 696 u16 head, phase;
b60503ba 697
b60503ba 698 head = nvmeq->cq_head;
82123460 699 phase = nvmeq->cq_phase;
b60503ba
MW		 700
701 for (;;) {
c2f5b650
MW		 702 void *ctx;
703 nvme_completion_fn fn;
b60503ba 704 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 705 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 706 break;
707 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
708 if (++head == nvmeq->q_depth) {
709 head = 0;
82123460 710 phase = !phase;
b60503ba 711 }
a4aea562 712 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 713 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 714 }
715
716 /* If the controller ignores the cq head doorbell and continuously
717 * writes to the queue, it is theoretically possible to wrap around
718 * the queue twice and mistakenly return IRQ_NONE. Linux only
719 * requires that 0.1% of your interrupts are handled, so this isn't
720 * a big problem.
721 */
82123460 722 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 723 return 0;
b60503ba 724
b80d5ccc 725 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 726 nvmeq->cq_head = head;
82123460 727 nvmeq->cq_phase = phase;
b60503ba 728
e9539f47
MW		 729 nvmeq->cqe_seen = 1;
730 return 1;
b60503ba
MW		 731}
732
a4aea562
MB		 733/* Admin queue isn't initialized as a request queue. If at some point this
734 * happens anyway, make sure to notify the user */
735static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
736 const struct blk_mq_queue_data *bd)
7d822457 737{
a4aea562
MB		 738 WARN_ON_ONCE(1);
739 return BLK_MQ_RQ_QUEUE_ERROR;
7d822457
MW		 740}
741
b60503ba 742static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 743{
744 irqreturn_t result;
745 struct nvme_queue *nvmeq = data;
746 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 747 nvme_process_cq(nvmeq);
748 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
749 nvmeq->cqe_seen = 0;
58ffacb5
MW		 750 spin_unlock(&nvmeq->q_lock);
751 return result;
752}
753
754static irqreturn_t nvme_irq_check(int irq, void *data)
755{
756 struct nvme_queue *nvmeq = data;
757 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
758 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
759 return IRQ_NONE;
760 return IRQ_WAKE_THREAD;
761}
762
a4aea562
MB		 763static void nvme_abort_cmd_info(struct nvme_queue *nvmeq, struct nvme_cmd_info *
764 cmd_info)
3c0cf138
MW		 765{
766 spin_lock_irq(&nvmeq->q_lock);
a4aea562 767 cancel_cmd_info(cmd_info, NULL);
3c0cf138
MW		 768 spin_unlock_irq(&nvmeq->q_lock);
769}
770
c2f5b650
MW		 771struct sync_cmd_info {
772 struct task_struct *task;
773 u32 result;
774 int status;
775};
776
edd10d33 777static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 778 struct nvme_completion *cqe)
779{
780 struct sync_cmd_info *cmdinfo = ctx;
781 cmdinfo->result = le32_to_cpup(&cqe->result);
782 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
783 wake_up_process(cmdinfo->task);
784}
785
b60503ba
MW		 786/*
787 * Returns 0 on success. If the result is negative, it's a Linux error code;
788 * if the result is positive, it's an NVM Express status code
789 */
a4aea562 790static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
5d0f6131 791 u32 *result, unsigned timeout)
b60503ba 792{
a4aea562 793 int ret;
b60503ba 794 struct sync_cmd_info cmdinfo;
a4aea562
MB		 795 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
796 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
b60503ba
MW		 797
798 cmdinfo.task = current;
799 cmdinfo.status = -EINTR;
800
a4aea562
MB		 801 cmd->common.command_id = req->tag;
802
803 nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
b60503ba 804
3c0cf138 805 set_current_state(TASK_KILLABLE);
4f5099af
KB		 806 ret = nvme_submit_cmd(nvmeq, cmd);
807 if (ret) {
a4aea562 808 nvme_finish_cmd(nvmeq, req->tag, NULL);
4f5099af 809 set_current_state(TASK_RUNNING);
4f5099af 810 }
849c6e77 811 ret = schedule_timeout(timeout);
b60503ba 812
849c6e77
JA		 813 /*
814 * Ensure that sync_completion has either run, or that it will
815 * never run.
816 */
817 nvme_abort_cmd_info(nvmeq, blk_mq_rq_to_pdu(req));
818
819 /*
820 * We never got the completion
821 */
822 if (cmdinfo.status == -EINTR)
3c0cf138 823 return -EINTR;
3c0cf138 824
b60503ba
MW		 825 if (result)
826 *result = cmdinfo.result;
827
828 return cmdinfo.status;
829}
830
a4aea562
MB		 831static int nvme_submit_async_admin_req(struct nvme_dev *dev)
832{
833 struct nvme_queue *nvmeq = dev->queues[0];
834 struct nvme_command c;
835 struct nvme_cmd_info *cmd_info;
836 struct request *req;
837
6dcc0cf6 838 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false);
9f173b33
DC		 839 if (IS_ERR(req))
840 return PTR_ERR(req);
a4aea562 841
c917dfe5 842 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562
MB		 843 cmd_info = blk_mq_rq_to_pdu(req);
844 nvme_set_info(cmd_info, req, async_req_completion);
845
846 memset(&c, 0, sizeof(c));
847 c.common.opcode = nvme_admin_async_event;
848 c.common.command_id = req->tag;
849
850 return __nvme_submit_cmd(nvmeq, &c);
851}
852
853static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 854 struct nvme_command *cmd,
855 struct async_cmd_info *cmdinfo, unsigned timeout)
856{
a4aea562
MB		 857 struct nvme_queue *nvmeq = dev->queues[0];
858 struct request *req;
859 struct nvme_cmd_info *cmd_rq;
4d115420 860
a4aea562 861 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 862 if (IS_ERR(req))
863 return PTR_ERR(req);
a4aea562
MB		 864
865 req->timeout = timeout;
866 cmd_rq = blk_mq_rq_to_pdu(req);
867 cmdinfo->req = req;
868 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 869 cmdinfo->status = -EINTR;
a4aea562
MB		 870
871 cmd->common.command_id = req->tag;
872
4f5099af 873 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 874}
875
a64e6bb4 876static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
a4aea562 877 u32 *result, unsigned timeout)
b60503ba 878{
a4aea562
MB		 879 int res;
880 struct request *req;
881
882 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
97fe3832
JA		 883 if (IS_ERR(req))
884 return PTR_ERR(req);
a4aea562 885 res = nvme_submit_sync_cmd(req, cmd, result, timeout);
9d135bb8 886 blk_mq_free_request(req);
a4aea562 887 return res;
4f5099af
KB		 888}
889
a4aea562 890int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
4f5099af
KB		 891 u32 *result)
892{
a4aea562 893 return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 894}
895
a4aea562
MB		 896int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
897 struct nvme_command *cmd, u32 *result)
4d115420 898{
a4aea562
MB		 899 int res;
900 struct request *req;
901
902 req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
903 false);
97fe3832
JA		 904 if (IS_ERR(req))
905 return PTR_ERR(req);
a4aea562 906 res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
9d135bb8 907 blk_mq_free_request(req);
a4aea562 908 return res;
4d115420
KB		 909}
910
b60503ba
MW		 911static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
912{
b60503ba
MW		 913 struct nvme_command c;
914
915 memset(&c, 0, sizeof(c));
916 c.delete_queue.opcode = opcode;
917 c.delete_queue.qid = cpu_to_le16(id);
918
a4aea562 919 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 920}
921
922static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
923 struct nvme_queue *nvmeq)
924{
b60503ba
MW		 925 struct nvme_command c;
926 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
927
928 memset(&c, 0, sizeof(c));
929 c.create_cq.opcode = nvme_admin_create_cq;
930 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
931 c.create_cq.cqid = cpu_to_le16(qid);
932 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
933 c.create_cq.cq_flags = cpu_to_le16(flags);
934 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
935
a4aea562 936 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 937}
938
939static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
940 struct nvme_queue *nvmeq)
941{
b60503ba
MW		 942 struct nvme_command c;
943 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
944
945 memset(&c, 0, sizeof(c));
946 c.create_sq.opcode = nvme_admin_create_sq;
947 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
948 c.create_sq.sqid = cpu_to_le16(qid);
949 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
950 c.create_sq.sq_flags = cpu_to_le16(flags);
951 c.create_sq.cqid = cpu_to_le16(qid);
952
a4aea562 953 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 954}
955
956static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
957{
958 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
959}
960
961static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
962{
963 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
964}
965
5d0f6131 966int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 967 dma_addr_t dma_addr)
968{
969 struct nvme_command c;
970
971 memset(&c, 0, sizeof(c));
972 c.identify.opcode = nvme_admin_identify;
973 c.identify.nsid = cpu_to_le32(nsid);
974 c.identify.prp1 = cpu_to_le64(dma_addr);
975 c.identify.cns = cpu_to_le32(cns);
976
977 return nvme_submit_admin_cmd(dev, &c, NULL);
978}
979
5d0f6131 980int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 981 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 982{
983 struct nvme_command c;
984
985 memset(&c, 0, sizeof(c));
986 c.features.opcode = nvme_admin_get_features;
a42cecce 987 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 988 c.features.prp1 = cpu_to_le64(dma_addr);
989 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 990
08df1e05 991 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 992}
993
5d0f6131
VV		 994int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
995 dma_addr_t dma_addr, u32 *result)
df348139
MW		 996{
997 struct nvme_command c;
998
999 memset(&c, 0, sizeof(c));
1000 c.features.opcode = nvme_admin_set_features;
1001 c.features.prp1 = cpu_to_le64(dma_addr);
1002 c.features.fid = cpu_to_le32(fid);
1003 c.features.dword11 = cpu_to_le32(dword11);
1004
bc5fc7e4
MW		 1005 return nvme_submit_admin_cmd(dev, &c, result);
1006}
1007
c30341dc 1008/**
a4aea562 1009 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1010 *
1011 * Schedule controller reset if the command was already aborted once before and
1012 * still hasn't been returned to the driver, or if this is the admin queue.
1013 */
a4aea562 1014static void nvme_abort_req(struct request *req)
c30341dc 1015{
a4aea562
MB		 1016 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1017 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1018 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1019 struct request *abort_req;
1020 struct nvme_cmd_info *abort_cmd;
1021 struct nvme_command cmd;
c30341dc 1022
a4aea562 1023 if (!nvmeq->qid || cmd_rq->aborted) {
7a509a6b
KB		 1024 unsigned long flags;
1025
1026 spin_lock_irqsave(&dev_list_lock, flags);
c30341dc 1027 if (work_busy(&dev->reset_work))
7a509a6b 1028 goto out;
c30341dc
KB		 1029 list_del_init(&dev->node);
1030 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1031 "I/O %d QID %d timeout, reset controller\n",
1032 req->tag, nvmeq->qid);
9ca97374 1033 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc 1034 queue_work(nvme_workq, &dev->reset_work);
7a509a6b
KB		 1035 out:
1036 spin_unlock_irqrestore(&dev_list_lock, flags);
c30341dc
KB		 1037 return;
1038 }
1039
1040 if (!dev->abort_limit)
1041 return;
1042
a4aea562
MB		 1043 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1044 false);
9f173b33 1045 if (IS_ERR(abort_req))
c30341dc
KB		 1046 return;
1047
a4aea562
MB		 1048 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1049 nvme_set_info(abort_cmd, abort_req, abort_completion);
1050
c30341dc
KB		 1051 memset(&cmd, 0, sizeof(cmd));
1052 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1053 cmd.abort.cid = req->tag;
c30341dc 1054 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1055 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1056
1057 --dev->abort_limit;
a4aea562 1058 cmd_rq->aborted = 1;
c30341dc 1059
a4aea562 1060 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1061 nvmeq->qid);
a4aea562
MB		 1062 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1063 dev_warn(nvmeq->q_dmadev,
1064 "Could not abort I/O %d QID %d",
1065 req->tag, nvmeq->qid);
c87fd540 1066 blk_mq_free_request(abort_req);
a4aea562 1067 }
c30341dc
KB		 1068}
1069
a4aea562
MB		 1070static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1071 struct request *req, void *data, bool reserved)
a09115b2 1072{
a4aea562
MB		 1073 struct nvme_queue *nvmeq = data;
1074 void *ctx;
1075 nvme_completion_fn fn;
1076 struct nvme_cmd_info *cmd;
cef6a948
KB		 1077 struct nvme_completion cqe;
1078
1079 if (!blk_mq_request_started(req))
1080 return;
a09115b2 1081
a4aea562 1082 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1083
a4aea562
MB		 1084 if (cmd->ctx == CMD_CTX_CANCELLED)
1085 return;
1086
cef6a948
KB		 1087 if (blk_queue_dying(req->q))
1088 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1089 else
1090 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1091
1092
a4aea562
MB		 1093 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1094 req->tag, nvmeq->qid);
1095 ctx = cancel_cmd_info(cmd, &fn);
1096 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1097}
1098
a4aea562 1099static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1100{
a4aea562
MB		 1101 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1102 struct nvme_queue *nvmeq = cmd->nvmeq;
1103
7a509a6b
KB		 1104 /*
1105 * The aborted req will be completed on receiving the abort req.
1106 * We enable the timer again. If hit twice, it'll cause a device reset,
1107 * as the device then is in a faulty state.
1108 */
1109 int ret = BLK_EH_RESET_TIMER;
1110
a4aea562
MB		 1111 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1112 nvmeq->qid);
c917dfe5 1113
7a509a6b 1114 spin_lock_irq(&nvmeq->q_lock);
c917dfe5
KB		 1115 if (!nvmeq->dev->initialized) {
1116 /*
1117 * Force cancelled command frees the request, which requires we
1118 * return BLK_EH_NOT_HANDLED.
1119 */
1120 nvme_cancel_queue_ios(nvmeq->hctx, req, nvmeq, reserved);
7a509a6b
KB		 1121 ret = BLK_EH_NOT_HANDLED;
1122 } else
1123 nvme_abort_req(req);
1124 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1125
7a509a6b 1126 return ret;
a4aea562 1127}
22404274 1128
a4aea562
MB		 1129static void nvme_free_queue(struct nvme_queue *nvmeq)
1130{
9e866774
MW		 1131 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1132 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1133 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1134 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1135 kfree(nvmeq);
1136}
1137
a1a5ef99 1138static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274 1139{
f435c282
KB		 1140 LLIST_HEAD(q_list);
1141 struct nvme_queue *nvmeq, *next;
1142 struct llist_node *entry;
22404274
KB		 1143 int i;
1144
a1a5ef99 1145 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1146 struct nvme_queue *nvmeq = dev->queues[i];
f435c282 1147 llist_add(&nvmeq->node, &q_list);
22404274 1148 dev->queue_count--;
a4aea562 1149 dev->queues[i] = NULL;
22404274 1150 }
f435c282
KB		 1151 synchronize_rcu();
1152 entry = llist_del_all(&q_list);
1153 llist_for_each_entry_safe(nvmeq, next, entry, node)
1154 nvme_free_queue(nvmeq);
22404274
KB		 1155}
1156
4d115420
KB		 1157/**
1158 * nvme_suspend_queue - put queue into suspended state
1159 * @nvmeq - queue to suspend
4d115420
KB		 1160 */
1161static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1162{
2b25d981 1163 int vector;
b60503ba 1164
a09115b2 1165 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1166 if (nvmeq->cq_vector == -1) {
1167 spin_unlock_irq(&nvmeq->q_lock);
1168 return 1;
1169 }
1170 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1171 nvmeq->dev->online_queues--;
2b25d981 1172 nvmeq->cq_vector = -1;
a09115b2
MW		 1173 spin_unlock_irq(&nvmeq->q_lock);
1174
aba2080f
MW		 1175 irq_set_affinity_hint(vector, NULL);
1176 free_irq(vector, nvmeq);
b60503ba 1177
4d115420
KB		 1178 return 0;
1179}
b60503ba 1180
4d115420
KB		 1181static void nvme_clear_queue(struct nvme_queue *nvmeq)
1182{
a4aea562
MB		 1183 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1184
22404274
KB		 1185 spin_lock_irq(&nvmeq->q_lock);
1186 nvme_process_cq(nvmeq);
a4aea562
MB		 1187 if (hctx && hctx->tags)
1188 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
22404274 1189 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1190}
1191
4d115420
KB		 1192static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1193{
a4aea562 1194 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1195
1196 if (!nvmeq)
1197 return;
1198 if (nvme_suspend_queue(nvmeq))
1199 return;
1200
0e53d180
KB		 1201 /* Don't tell the adapter to delete the admin queue.
1202 * Don't tell a removed adapter to delete IO queues. */
1203 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1204 adapter_delete_sq(dev, qid);
1205 adapter_delete_cq(dev, qid);
1206 }
0fb59cbc
KB		 1207 if (!qid && dev->admin_q)
1208 blk_mq_freeze_queue_start(dev->admin_q);
4d115420 1209 nvme_clear_queue(nvmeq);
b60503ba
MW		 1210}
1211
1212static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1213 int depth)
b60503ba
MW		 1214{
1215 struct device *dmadev = &dev->pci_dev->dev;
a4aea562 1216 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1217 if (!nvmeq)
1218 return NULL;
1219
4d51abf9
JP		 1220 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1221 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1222 if (!nvmeq->cqes)
1223 goto free_nvmeq;
b60503ba
MW		 1224
1225 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1226 &nvmeq->sq_dma_addr, GFP_KERNEL);
1227 if (!nvmeq->sq_cmds)
1228 goto free_cqdma;
1229
1230 nvmeq->q_dmadev = dmadev;
091b6092 1231 nvmeq->dev = dev;
3193f07b
MW		 1232 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1233 dev->instance, qid);
b60503ba
MW		 1234 spin_lock_init(&nvmeq->q_lock);
1235 nvmeq->cq_head = 0;
82123460 1236 nvmeq->cq_phase = 1;
b80d5ccc 1237 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1238 nvmeq->q_depth = depth;
c30341dc 1239 nvmeq->qid = qid;
22404274 1240 dev->queue_count++;
a4aea562 1241 dev->queues[qid] = nvmeq;
b60503ba
MW		 1242
1243 return nvmeq;
1244
1245 free_cqdma:
68b8eca5 1246 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1247 nvmeq->cq_dma_addr);
1248 free_nvmeq:
1249 kfree(nvmeq);
1250 return NULL;
1251}
1252
3001082c
MW		 1253static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1254 const char *name)
1255{
58ffacb5
MW		 1256 if (use_threaded_interrupts)
1257 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1258 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1259 name, nvmeq);
3001082c 1260 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1261 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1262}
1263
22404274 1264static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1265{
22404274 1266 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1267
7be50e93 1268 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1269 nvmeq->sq_tail = 0;
1270 nvmeq->cq_head = 0;
1271 nvmeq->cq_phase = 1;
b80d5ccc 1272 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1273 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1274 dev->online_queues++;
7be50e93 1275 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1276}
1277
1278static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1279{
1280 struct nvme_dev *dev = nvmeq->dev;
1281 int result;
3f85d50b 1282
2b25d981 1283 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1284 result = adapter_alloc_cq(dev, qid, nvmeq);
1285 if (result < 0)
22404274 1286 return result;
b60503ba
MW		 1287
1288 result = adapter_alloc_sq(dev, qid, nvmeq);
1289 if (result < 0)
1290 goto release_cq;
1291
3193f07b 1292 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1293 if (result < 0)
1294 goto release_sq;
1295
22404274 1296 nvme_init_queue(nvmeq, qid);
22404274 1297 return result;
b60503ba
MW		 1298
1299 release_sq:
1300 adapter_delete_sq(dev, qid);
1301 release_cq:
1302 adapter_delete_cq(dev, qid);
22404274 1303 return result;
b60503ba
MW		 1304}
1305
ba47e386
MW		 1306static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1307{
1308 unsigned long timeout;
1309 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1310
1311 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1312
1313 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1314 msleep(100);
1315 if (fatal_signal_pending(current))
1316 return -EINTR;
1317 if (time_after(jiffies, timeout)) {
1318 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1319 "Device not ready; aborting %s\n", enabled ?
1320 "initialisation" : "reset");
ba47e386
MW		 1321 return -ENODEV;
1322 }
1323 }
1324
1325 return 0;
1326}
1327
1328/*
1329 * If the device has been passed off to us in an enabled state, just clear
1330 * the enabled bit. The spec says we should set the 'shutdown notification
1331 * bits', but doing so may cause the device to complete commands to the
1332 * admin queue ... and we don't know what memory that might be pointing at!
1333 */
1334static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1335{
01079522
DM		 1336 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1337 dev->ctrl_config &= ~NVME_CC_ENABLE;
1338 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1339
ba47e386
MW		 1340 return nvme_wait_ready(dev, cap, false);
1341}
1342
1343static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1344{
01079522
DM		 1345 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1346 dev->ctrl_config |= NVME_CC_ENABLE;
1347 writel(dev->ctrl_config, &dev->bar->cc);
1348
ba47e386
MW		 1349 return nvme_wait_ready(dev, cap, true);
1350}
1351
1894d8f1
KB		 1352static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1353{
1354 unsigned long timeout;
1894d8f1 1355
01079522
DM		 1356 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1357 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1358
1359 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1360
2484f407 1361 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1362 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1363 NVME_CSTS_SHST_CMPLT) {
1364 msleep(100);
1365 if (fatal_signal_pending(current))
1366 return -EINTR;
1367 if (time_after(jiffies, timeout)) {
1368 dev_err(&dev->pci_dev->dev,
1369 "Device shutdown incomplete; abort shutdown\n");
1370 return -ENODEV;
1371 }
1372 }
1373
1374 return 0;
1375}
1376
a4aea562
MB		 1377static struct blk_mq_ops nvme_mq_admin_ops = {
1378 .queue_rq = nvme_admin_queue_rq,
1379 .map_queue = blk_mq_map_queue,
1380 .init_hctx = nvme_admin_init_hctx,
2c30540b 1381 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1382 .init_request = nvme_admin_init_request,
1383 .timeout = nvme_timeout,
1384};
1385
1386static struct blk_mq_ops nvme_mq_ops = {
1387 .queue_rq = nvme_queue_rq,
1388 .map_queue = blk_mq_map_queue,
1389 .init_hctx = nvme_init_hctx,
2c30540b 1390 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1391 .init_request = nvme_init_request,
1392 .timeout = nvme_timeout,
1393};
1394
ea191d2f
KB		 1395static void nvme_dev_remove_admin(struct nvme_dev *dev)
1396{
1397 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1398 blk_cleanup_queue(dev->admin_q);
1399 blk_mq_free_tag_set(&dev->admin_tagset);
1400 }
1401}
1402
a4aea562
MB		 1403static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1404{
1405 if (!dev->admin_q) {
1406 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1407 dev->admin_tagset.nr_hw_queues = 1;
1408 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1409 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1410 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
1411 dev->admin_tagset.cmd_size = sizeof(struct nvme_cmd_info);
1412 dev->admin_tagset.driver_data = dev;
1413
1414 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1415 return -ENOMEM;
1416
1417 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1418 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1419 blk_mq_free_tag_set(&dev->admin_tagset);
1420 return -ENOMEM;
1421 }
ea191d2f
KB		 1422 if (!blk_get_queue(dev->admin_q)) {
1423 nvme_dev_remove_admin(dev);
1424 return -ENODEV;
1425 }
0fb59cbc
KB		 1426 } else
1427 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1428
1429 return 0;
1430}
1431
8d85fce7 1432static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1433{
ba47e386 1434 int result;
b60503ba 1435 u32 aqa;
ba47e386 1436 u64 cap = readq(&dev->bar->cap);
b60503ba 1437 struct nvme_queue *nvmeq;
1d090624
KB		 1438 unsigned page_shift = PAGE_SHIFT;
1439 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1440 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1441
1442 if (page_shift < dev_page_min) {
1443 dev_err(&dev->pci_dev->dev,
1444 "Minimum device page size (%u) too large for "
1445 "host (%u)\n", 1 << dev_page_min,
1446 1 << page_shift);
1447 return -ENODEV;
1448 }
1449 if (page_shift > dev_page_max) {
1450 dev_info(&dev->pci_dev->dev,
1451 "Device maximum page size (%u) smaller than "
1452 "host (%u); enabling work-around\n",
1453 1 << dev_page_max, 1 << page_shift);
1454 page_shift = dev_page_max;
1455 }
b60503ba 1456
ba47e386
MW		 1457 result = nvme_disable_ctrl(dev, cap);
1458 if (result < 0)
1459 return result;
b60503ba 1460
a4aea562 1461 nvmeq = dev->queues[0];
cd638946 1462 if (!nvmeq) {
2b25d981 1463 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1464 if (!nvmeq)
1465 return -ENOMEM;
cd638946 1466 }
b60503ba
MW		 1467
1468 aqa = nvmeq->q_depth - 1;
1469 aqa |= aqa << 16;
1470
1d090624
KB		 1471 dev->page_size = 1 << page_shift;
1472
01079522 1473 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1474 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1475 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1476 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1477
1478 writel(aqa, &dev->bar->aqa);
1479 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1480 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1481
ba47e386 1482 result = nvme_enable_ctrl(dev, cap);
025c557a 1483 if (result)
a4aea562
MB		 1484 goto free_nvmeq;
1485
2b25d981 1486 nvmeq->cq_vector = 0;
3193f07b 1487 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1488 if (result)
0fb59cbc 1489 goto free_nvmeq;
025c557a 1490
b60503ba 1491 return result;
a4aea562 1492
a4aea562
MB		 1493 free_nvmeq:
1494 nvme_free_queues(dev, 0);
1495 return result;
b60503ba
MW		 1496}
1497
5d0f6131 1498struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1499 unsigned long addr, unsigned length)
b60503ba 1500{
36c14ed9 1501 int i, err, count, nents, offset;
7fc3cdab
MW		 1502 struct scatterlist *sg;
1503 struct page **pages;
eca18b23 1504 struct nvme_iod *iod;
36c14ed9
MW		 1505
1506 if (addr & 3)
eca18b23 1507 return ERR_PTR(-EINVAL);
5460fc03 1508 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1509 return ERR_PTR(-EINVAL);
7fc3cdab 1510
36c14ed9 1511 offset = offset_in_page(addr);
7fc3cdab
MW		 1512 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1513 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1514 if (!pages)
1515 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1516
1517 err = get_user_pages_fast(addr, count, 1, pages);
1518 if (err < count) {
1519 count = err;
1520 err = -EFAULT;
1521 goto put_pages;
1522 }
7fc3cdab 1523
6808c5fb 1524 err = -ENOMEM;
1d090624 1525 iod = nvme_alloc_iod(count, length, dev, GFP_KERNEL);
6808c5fb
S		 1526 if (!iod)
1527 goto put_pages;
1528
eca18b23 1529 sg = iod->sg;
36c14ed9 1530 sg_init_table(sg, count);
d0ba1e49
MW		 1531 for (i = 0; i < count; i++) {
1532 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1533 min_t(unsigned, length, PAGE_SIZE - offset),
1534 offset);
d0ba1e49
MW		 1535 length -= (PAGE_SIZE - offset);
1536 offset = 0;
7fc3cdab 1537 }
fe304c43 1538 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1539 iod->nents = count;
7fc3cdab 1540
7fc3cdab
MW		 1541 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1542 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1543 if (!nents)
eca18b23 1544 goto free_iod;
b60503ba 1545
7fc3cdab 1546 kfree(pages);
eca18b23 1547 return iod;
b60503ba 1548
eca18b23
MW		 1549 free_iod:
1550 kfree(iod);
7fc3cdab
MW		 1551 put_pages:
1552 for (i = 0; i < count; i++)
1553 put_page(pages[i]);
1554 kfree(pages);
eca18b23 1555 return ERR_PTR(err);
7fc3cdab 1556}
b60503ba 1557
5d0f6131 1558void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1559 struct nvme_iod *iod)
7fc3cdab 1560{
1c2ad9fa 1561 int i;
b60503ba 1562
1c2ad9fa
MW		 1563 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1564 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1565
1c2ad9fa
MW		 1566 for (i = 0; i < iod->nents; i++)
1567 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1568}
b60503ba 1569
a53295b6
MW		 1570static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1571{
1572 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1573 struct nvme_user_io io;
1574 struct nvme_command c;
f410c680
KB		 1575 unsigned length, meta_len;
1576 int status, i;
1577 struct nvme_iod *iod, *meta_iod = NULL;
1578 dma_addr_t meta_dma_addr;
1579 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1580
1581 if (copy_from_user(&io, uio, sizeof(io)))
1582 return -EFAULT;
6c7d4945 1583 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1584 meta_len = (io.nblocks + 1) * ns->ms;
1585
1586 if (meta_len && ((io.metadata & 3) || !io.metadata))
1587 return -EINVAL;
6c7d4945
MW		 1588
1589 switch (io.opcode) {
1590 case nvme_cmd_write:
1591 case nvme_cmd_read:
6bbf1acd 1592 case nvme_cmd_compare:
eca18b23 1593 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1594 break;
6c7d4945 1595 default:
6bbf1acd 1596 return -EINVAL;
6c7d4945
MW		 1597 }
1598
eca18b23
MW		 1599 if (IS_ERR(iod))
1600 return PTR_ERR(iod);
a53295b6
MW		 1601
1602 memset(&c, 0, sizeof(c));
1603 c.rw.opcode = io.opcode;
1604 c.rw.flags = io.flags;
6c7d4945 1605 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1606 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1607 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1608 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1609 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1610 c.rw.reftag = cpu_to_le32(io.reftag);
1611 c.rw.apptag = cpu_to_le16(io.apptag);
1612 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1613
1614 if (meta_len) {
1b56749e
KB		 1615 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1616 meta_len);
f410c680
KB		 1617 if (IS_ERR(meta_iod)) {
1618 status = PTR_ERR(meta_iod);
1619 meta_iod = NULL;
1620 goto unmap;
1621 }
1622
1623 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1624 &meta_dma_addr, GFP_KERNEL);
1625 if (!meta_mem) {
1626 status = -ENOMEM;
1627 goto unmap;
1628 }
1629
1630 if (io.opcode & 1) {
1631 int meta_offset = 0;
1632
1633 for (i = 0; i < meta_iod->nents; i++) {
1634 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1635 meta_iod->sg[i].offset;
1636 memcpy(meta_mem + meta_offset, meta,
1637 meta_iod->sg[i].length);
1638 kunmap_atomic(meta);
1639 meta_offset += meta_iod->sg[i].length;
1640 }
1641 }
1642
1643 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1644 }
1645
edd10d33
KB		 1646 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1647 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1648 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1649
b77954cb
MW		 1650 if (length != (io.nblocks + 1) << ns->lba_shift)
1651 status = -ENOMEM;
1652 else
a4aea562 1653 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
a53295b6 1654
f410c680
KB		 1655 if (meta_len) {
1656 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1657 int meta_offset = 0;
1658
1659 for (i = 0; i < meta_iod->nents; i++) {
1660 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1661 meta_iod->sg[i].offset;
1662 memcpy(meta, meta_mem + meta_offset,
1663 meta_iod->sg[i].length);
1664 kunmap_atomic(meta);
1665 meta_offset += meta_iod->sg[i].length;
1666 }
1667 }
1668
1669 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1670 meta_dma_addr);
1671 }
1672
1673 unmap:
1c2ad9fa 1674 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1675 nvme_free_iod(dev, iod);
f410c680
KB		 1676
1677 if (meta_iod) {
1678 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1679 nvme_free_iod(dev, meta_iod);
1680 }
1681
a53295b6
MW		 1682 return status;
1683}
1684
a4aea562
MB		 1685static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1686 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1687{
7963e521 1688 struct nvme_passthru_cmd cmd;
6ee44cdc 1689 struct nvme_command c;
eca18b23 1690 int status, length;
c7d36ab8 1691 struct nvme_iod *uninitialized_var(iod);
94f370ca 1692 unsigned timeout;
6ee44cdc 1693
6bbf1acd
MW		 1694 if (!capable(CAP_SYS_ADMIN))
1695 return -EACCES;
1696 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1697 return -EFAULT;
6ee44cdc
MW		 1698
1699 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1700 c.common.opcode = cmd.opcode;
1701 c.common.flags = cmd.flags;
1702 c.common.nsid = cpu_to_le32(cmd.nsid);
1703 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1704 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1705 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1706 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1707 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1708 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1709 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1710 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1711
1712 length = cmd.data_len;
1713 if (cmd.data_len) {
49742188
MW		 1714 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1715 length);
eca18b23
MW		 1716 if (IS_ERR(iod))
1717 return PTR_ERR(iod);
edd10d33
KB		 1718 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1719 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1720 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1721 }
1722
94f370ca
KB		 1723 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1724 ADMIN_TIMEOUT;
a4aea562 1725
6bbf1acd 1726 if (length != cmd.data_len)
b77954cb 1727 status = -ENOMEM;
a4aea562
MB		 1728 else if (ns) {
1729 struct request *req;
1730
1731 req = blk_mq_alloc_request(ns->queue, WRITE,
1732 (GFP_KERNEL|__GFP_WAIT), false);
97fe3832
JA		 1733 if (IS_ERR(req))
1734 status = PTR_ERR(req);
a4aea562
MB		 1735 else {
1736 status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1737 timeout);
9d135bb8 1738 blk_mq_free_request(req);
a4aea562
MB		 1739 }
1740 } else
1741 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
eca18b23 1742
6bbf1acd 1743 if (cmd.data_len) {
1c2ad9fa 1744 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1745 nvme_free_iod(dev, iod);
6bbf1acd 1746 }
f4f117f6 1747
cf90bc48 1748 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1749 sizeof(cmd.result)))
1750 status = -EFAULT;
1751
6ee44cdc
MW		 1752 return status;
1753}
1754
b60503ba
MW		 1755static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1756 unsigned long arg)
1757{
1758 struct nvme_ns *ns = bdev->bd_disk->private_data;
1759
1760 switch (cmd) {
6bbf1acd 1761 case NVME_IOCTL_ID:
c3bfe717 1762 force_successful_syscall_return();
6bbf1acd
MW		 1763 return ns->ns_id;
1764 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1765 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1766 case NVME_IOCTL_IO_CMD:
a4aea562 1767 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1768 case NVME_IOCTL_SUBMIT_IO:
1769 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1770 case SG_GET_VERSION_NUM:
1771 return nvme_sg_get_version_num((void __user *)arg);
1772 case SG_IO:
1773 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1774 default:
1775 return -ENOTTY;
1776 }
1777}
1778
320a3827
KB		 1779#ifdef CONFIG_COMPAT
1780static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1781 unsigned int cmd, unsigned long arg)
1782{
320a3827
KB		 1783 switch (cmd) {
1784 case SG_IO:
e179729a 1785 return -ENOIOCTLCMD;
320a3827
KB		 1786 }
1787 return nvme_ioctl(bdev, mode, cmd, arg);
1788}
1789#else
1790#define nvme_compat_ioctl NULL
1791#endif
1792
9ac27090
KB		 1793static int nvme_open(struct block_device *bdev, fmode_t mode)
1794{
9e60352c
KB		 1795 int ret = 0;
1796 struct nvme_ns *ns;
9ac27090 1797
9e60352c
KB		 1798 spin_lock(&dev_list_lock);
1799 ns = bdev->bd_disk->private_data;
1800 if (!ns)
1801 ret = -ENXIO;
1802 else if (!kref_get_unless_zero(&ns->dev->kref))
1803 ret = -ENXIO;
1804 spin_unlock(&dev_list_lock);
1805
1806 return ret;
9ac27090
KB		 1807}
1808
1809static void nvme_free_dev(struct kref *kref);
1810
1811static void nvme_release(struct gendisk *disk, fmode_t mode)
1812{
1813 struct nvme_ns *ns = disk->private_data;
1814 struct nvme_dev *dev = ns->dev;
1815
1816 kref_put(&dev->kref, nvme_free_dev);
1817}
1818
4cc09e2d
KB		 1819static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1820{
1821 /* some standard values */
1822 geo->heads = 1 << 6;
1823 geo->sectors = 1 << 5;
1824 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1825 return 0;
1826}
1827
1b9dbf7f
KB		 1828static int nvme_revalidate_disk(struct gendisk *disk)
1829{
1830 struct nvme_ns *ns = disk->private_data;
1831 struct nvme_dev *dev = ns->dev;
1832 struct nvme_id_ns *id;
1833 dma_addr_t dma_addr;
1834 int lbaf;
1835
1836 id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
1837 GFP_KERNEL);
1838 if (!id) {
1839 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
1840 __func__);
1841 return 0;
1842 }
1843
1844 if (nvme_identify(dev, ns->ns_id, 0, dma_addr))
1845 goto free;
1846
1847 lbaf = id->flbas & 0xf;
1848 ns->lba_shift = id->lbaf[lbaf].ds;
1849
1850 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1851 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1852 free:
1853 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1854 return 0;
1855}
1856
b60503ba
MW		 1857static const struct block_device_operations nvme_fops = {
1858 .owner = THIS_MODULE,
1859 .ioctl = nvme_ioctl,
320a3827 1860 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1861 .open = nvme_open,
1862 .release = nvme_release,
4cc09e2d 1863 .getgeo = nvme_getgeo,
1b9dbf7f 1864 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 1865};
1866
1fa6aead
MW		 1867static int nvme_kthread(void *data)
1868{
d4b4ff8e 1869 struct nvme_dev *dev, *next;
1fa6aead
MW		 1870
1871 while (!kthread_should_stop()) {
564a232c 1872 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1873 spin_lock(&dev_list_lock);
d4b4ff8e 1874 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1875 int i;
d4b4ff8e
KB		 1876 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1877 dev->initialized) {
1878 if (work_busy(&dev->reset_work))
1879 continue;
1880 list_del_init(&dev->node);
1881 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1882 "Failed status: %x, reset controller\n",
1883 readl(&dev->bar->csts));
9ca97374 1884 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 1885 queue_work(nvme_workq, &dev->reset_work);
1886 continue;
1887 }
1fa6aead 1888 for (i = 0; i < dev->queue_count; i++) {
a4aea562 1889 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 1890 if (!nvmeq)
1891 continue;
1fa6aead 1892 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 1893 nvme_process_cq(nvmeq);
6fccf938
KB		 1894
1895 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 1896 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 1897 break;
1898 dev->event_limit--;
1899 }
1fa6aead
MW		 1900 spin_unlock_irq(&nvmeq->q_lock);
1901 }
1902 }
1903 spin_unlock(&dev_list_lock);
acb7aa0d 1904 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1905 }
1906 return 0;
1907}
1908
0e5e4f0e
KB		 1909static void nvme_config_discard(struct nvme_ns *ns)
1910{
1911 u32 logical_block_size = queue_logical_block_size(ns->queue);
1912 ns->queue->limits.discard_zeroes_data = 0;
1913 ns->queue->limits.discard_alignment = logical_block_size;
1914 ns->queue->limits.discard_granularity = logical_block_size;
1915 ns->queue->limits.max_discard_sectors = 0xffffffff;
1916 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1917}
1918
c3bfe717 1919static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1920 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1921{
1922 struct nvme_ns *ns;
1923 struct gendisk *disk;
a4aea562 1924 int node = dev_to_node(&dev->pci_dev->dev);
b60503ba
MW		 1925 int lbaf;
1926
1927 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1928 return NULL;
1929
a4aea562 1930 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba
MW		 1931 if (!ns)
1932 return NULL;
a4aea562 1933 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 1934 if (IS_ERR(ns->queue))
b60503ba 1935 goto out_free_ns;
4eeb9215
MW		 1936 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1937 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 1938 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 1939 ns->dev = dev;
1940 ns->queue->queuedata = ns;
1941
a4aea562 1942 disk = alloc_disk_node(0, node);
b60503ba
MW		 1943 if (!disk)
1944 goto out_free_queue;
a4aea562 1945
5aff9382 1946 ns->ns_id = nsid;
b60503ba
MW		 1947 ns->disk = disk;
1948 lbaf = id->flbas & 0xf;
1949 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1950 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1951 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1952 if (dev->max_hw_sectors)
1953 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 1954 if (dev->stripe_size)
1955 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 1956 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
1957 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 1958
1959 disk->major = nvme_major;
469071a3 1960 disk->first_minor = 0;
b60503ba
MW		 1961 disk->fops = &nvme_fops;
1962 disk->private_data = ns;
1963 disk->queue = ns->queue;
388f037f 1964 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1965 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1966 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1967 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1968
0e5e4f0e
KB		 1969 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1970 nvme_config_discard(ns);
1971
b60503ba
MW		 1972 return ns;
1973
1974 out_free_queue:
1975 blk_cleanup_queue(ns->queue);
1976 out_free_ns:
1977 kfree(ns);
1978 return NULL;
1979}
1980
42f61420
KB		 1981static void nvme_create_io_queues(struct nvme_dev *dev)
1982{
a4aea562 1983 unsigned i;
42f61420 1984
a4aea562 1985 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 1986 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 1987 break;
1988
a4aea562
MB		 1989 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
1990 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 1991 break;
1992}
1993
b3b06812 1994static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 1995{
1996 int status;
1997 u32 result;
b3b06812 1998 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 1999
df348139 2000 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2001 &result);
27e8166c
MW		 2002 if (status < 0)
2003 return status;
2004 if (status > 0) {
2005 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2006 status);
badc34d4 2007 return 0;
27e8166c 2008 }
b60503ba
MW		 2009 return min(result & 0xffff, result >> 16) + 1;
2010}
2011
9d713c2b
KB		 2012static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2013{
b80d5ccc 2014 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2015}
2016
8d85fce7 2017static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2018{
a4aea562 2019 struct nvme_queue *adminq = dev->queues[0];
fa08a396 2020 struct pci_dev *pdev = dev->pci_dev;
42f61420 2021 int result, i, vecs, nr_io_queues, size;
b60503ba 2022
42f61420 2023 nr_io_queues = num_possible_cpus();
b348b7d5 2024 result = set_queue_count(dev, nr_io_queues);
badc34d4 2025 if (result <= 0)
1b23484b 2026 return result;
b348b7d5
MW		 2027 if (result < nr_io_queues)
2028 nr_io_queues = result;
b60503ba 2029
9d713c2b
KB		 2030 size = db_bar_size(dev, nr_io_queues);
2031 if (size > 8192) {
f1938f6e 2032 iounmap(dev->bar);
9d713c2b
KB		 2033 do {
2034 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2035 if (dev->bar)
2036 break;
2037 if (!--nr_io_queues)
2038 return -ENOMEM;
2039 size = db_bar_size(dev, nr_io_queues);
2040 } while (1);
f1938f6e 2041 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2042 adminq->q_db = dev->dbs;
f1938f6e
MW		 2043 }
2044
9d713c2b 2045 /* Deregister the admin queue's interrupt */
3193f07b 2046 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2047
e32efbfc
JA		 2048 /*
2049 * If we enable msix early due to not intx, disable it again before
2050 * setting up the full range we need.
2051 */
2052 if (!pdev->irq)
2053 pci_disable_msix(pdev);
2054
be577fab 2055 for (i = 0; i < nr_io_queues; i++)
1b23484b 2056 dev->entry[i].entry = i;
be577fab
AG		 2057 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2058 if (vecs < 0) {
2059 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2060 if (vecs < 0) {
2061 vecs = 1;
2062 } else {
2063 for (i = 0; i < vecs; i++)
2064 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2065 }
2066 }
2067
063a8096
MW		 2068 /*
2069 * Should investigate if there's a performance win from allocating
2070 * more queues than interrupt vectors; it might allow the submission
2071 * path to scale better, even if the receive path is limited by the
2072 * number of interrupts.
2073 */
2074 nr_io_queues = vecs;
42f61420 2075 dev->max_qid = nr_io_queues;
063a8096 2076
3193f07b 2077 result = queue_request_irq(dev, adminq, adminq->irqname);
a4aea562 2078 if (result)
22404274 2079 goto free_queues;
1b23484b 2080
cd638946 2081 /* Free previously allocated queues that are no longer usable */
42f61420 2082 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2083 nvme_create_io_queues(dev);
9ecdc946 2084
22404274 2085 return 0;
b60503ba 2086
22404274 2087 free_queues:
a1a5ef99 2088 nvme_free_queues(dev, 1);
22404274 2089 return result;
b60503ba
MW		 2090}
2091
422ef0c7
MW		 2092/*
2093 * Return: error value if an error occurred setting up the queues or calling
2094 * Identify Device. 0 if these succeeded, even if adding some of the
2095 * namespaces failed. At the moment, these failures are silent. TBD which
2096 * failures should be reported.
2097 */
8d85fce7 2098static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2099{
68608c26 2100 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2101 int res;
2102 unsigned nn, i;
cbb6218f 2103 struct nvme_ns *ns;
51814232 2104 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2105 struct nvme_id_ns *id_ns;
2106 void *mem;
b60503ba 2107 dma_addr_t dma_addr;
159b67d7 2108 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2109
68608c26 2110 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2111 if (!mem)
2112 return -ENOMEM;
b60503ba 2113
bc5fc7e4 2114 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2115 if (res) {
27e8166c 2116 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
b60503ba 2117 res = -EIO;
cbb6218f 2118 goto out;
b60503ba
MW		 2119 }
2120
bc5fc7e4 2121 ctrl = mem;
51814232 2122 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2123 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2124 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2125 dev->vwc = ctrl->vwc;
6fccf938 2126 dev->event_limit = min(ctrl->aerl + 1, 8);
51814232
MW		 2127 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2128 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2129 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2130 if (ctrl->mdts)
8fc23e03 2131 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2132 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2133 (pdev->device == 0x0953) && ctrl->vs[3]) {
2134 unsigned int max_hw_sectors;
2135
159b67d7 2136 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2137 max_hw_sectors = dev->stripe_size >> (shift - 9);
2138 if (dev->max_hw_sectors) {
2139 dev->max_hw_sectors = min(max_hw_sectors,
2140 dev->max_hw_sectors);
2141 } else
2142 dev->max_hw_sectors = max_hw_sectors;
2143 }
2144
2145 dev->tagset.ops = &nvme_mq_ops;
2146 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2147 dev->tagset.timeout = NVME_IO_TIMEOUT;
2148 dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2149 dev->tagset.queue_depth =
2150 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2151 dev->tagset.cmd_size = sizeof(struct nvme_cmd_info);
2152 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2153 dev->tagset.driver_data = dev;
2154
2155 if (blk_mq_alloc_tag_set(&dev->tagset))
2156 goto out;
b60503ba 2157
bc5fc7e4 2158 id_ns = mem;
2b2c1896 2159 for (i = 1; i <= nn; i++) {
bc5fc7e4 2160 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2161 if (res)
2162 continue;
2163
bc5fc7e4 2164 if (id_ns->ncap == 0)
b60503ba
MW		 2165 continue;
2166
bc5fc7e4 2167 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2168 dma_addr + 4096, NULL);
b60503ba 2169 if (res)
12209036 2170 memset(mem + 4096, 0, 4096);
b60503ba 2171
bc5fc7e4 2172 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2173 if (ns)
2174 list_add_tail(&ns->list, &dev->namespaces);
2175 }
2176 list_for_each_entry(ns, &dev->namespaces, list)
2177 add_disk(ns->disk);
422ef0c7 2178 res = 0;
b60503ba 2179
bc5fc7e4 2180 out:
684f5c20 2181 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2182 return res;
2183}
2184
0877cb0d
KB		 2185static int nvme_dev_map(struct nvme_dev *dev)
2186{
42f61420 2187 u64 cap;
0877cb0d
KB		 2188 int bars, result = -ENOMEM;
2189 struct pci_dev *pdev = dev->pci_dev;
2190
2191 if (pci_enable_device_mem(pdev))
2192 return result;
2193
2194 dev->entry[0].vector = pdev->irq;
2195 pci_set_master(pdev);
2196 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2197 if (!bars)
2198 goto disable_pci;
2199
0877cb0d
KB		 2200 if (pci_request_selected_regions(pdev, bars, "nvme"))
2201 goto disable_pci;
2202
052d0efa
RK		 2203 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2204 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2205 goto disable;
0877cb0d 2206
0877cb0d
KB		 2207 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2208 if (!dev->bar)
2209 goto disable;
e32efbfc 2210
0e53d180
KB		 2211 if (readl(&dev->bar->csts) == -1) {
2212 result = -ENODEV;
2213 goto unmap;
2214 }
e32efbfc
JA		 2215
2216 /*
2217 * Some devices don't advertse INTx interrupts, pre-enable a single
2218 * MSIX vec for setup. We'll adjust this later.
2219 */
2220 if (!pdev->irq) {
2221 result = pci_enable_msix(pdev, dev->entry, 1);
2222 if (result < 0)
2223 goto unmap;
2224 }
2225
42f61420
KB		 2226 cap = readq(&dev->bar->cap);
2227 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2228 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2229 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2230
2231 return 0;
2232
0e53d180
KB		 2233 unmap:
2234 iounmap(dev->bar);
2235 dev->bar = NULL;
0877cb0d
KB		 2236 disable:
2237 pci_release_regions(pdev);
2238 disable_pci:
2239 pci_disable_device(pdev);
2240 return result;
2241}
2242
2243static void nvme_dev_unmap(struct nvme_dev *dev)
2244{
2245 if (dev->pci_dev->msi_enabled)
2246 pci_disable_msi(dev->pci_dev);
2247 else if (dev->pci_dev->msix_enabled)
2248 pci_disable_msix(dev->pci_dev);
2249
2250 if (dev->bar) {
2251 iounmap(dev->bar);
2252 dev->bar = NULL;
9a6b9458 2253 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2254 }
2255
0877cb0d
KB		 2256 if (pci_is_enabled(dev->pci_dev))
2257 pci_disable_device(dev->pci_dev);
2258}
2259
4d115420
KB		 2260struct nvme_delq_ctx {
2261 struct task_struct *waiter;
2262 struct kthread_worker *worker;
2263 atomic_t refcount;
2264};
2265
2266static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2267{
2268 dq->waiter = current;
2269 mb();
2270
2271 for (;;) {
2272 set_current_state(TASK_KILLABLE);
2273 if (!atomic_read(&dq->refcount))
2274 break;
2275 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2276 fatal_signal_pending(current)) {
0fb59cbc
KB		 2277 /*
2278 * Disable the controller first since we can't trust it
2279 * at this point, but leave the admin queue enabled
2280 * until all queue deletion requests are flushed.
2281 * FIXME: This may take a while if there are more h/w
2282 * queues than admin tags.
2283 */
4d115420 2284 set_current_state(TASK_RUNNING);
4d115420 2285 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2286 nvme_clear_queue(dev->queues[0]);
4d115420 2287 flush_kthread_worker(dq->worker);
0fb59cbc 2288 nvme_disable_queue(dev, 0);
4d115420
KB		 2289 return;
2290 }
2291 }
2292 set_current_state(TASK_RUNNING);
2293}
2294
2295static void nvme_put_dq(struct nvme_delq_ctx *dq)
2296{
2297 atomic_dec(&dq->refcount);
2298 if (dq->waiter)
2299 wake_up_process(dq->waiter);
2300}
2301
2302static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2303{
2304 atomic_inc(&dq->refcount);
2305 return dq;
2306}
2307
2308static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2309{
2310 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2311
2312 nvme_clear_queue(nvmeq);
2313 nvme_put_dq(dq);
2314}
2315
2316static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2317 kthread_work_func_t fn)
2318{
2319 struct nvme_command c;
2320
2321 memset(&c, 0, sizeof(c));
2322 c.delete_queue.opcode = opcode;
2323 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2324
2325 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2326 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2327 ADMIN_TIMEOUT);
4d115420
KB		 2328}
2329
2330static void nvme_del_cq_work_handler(struct kthread_work *work)
2331{
2332 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2333 cmdinfo.work);
2334 nvme_del_queue_end(nvmeq);
2335}
2336
2337static int nvme_delete_cq(struct nvme_queue *nvmeq)
2338{
2339 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2340 nvme_del_cq_work_handler);
2341}
2342
2343static void nvme_del_sq_work_handler(struct kthread_work *work)
2344{
2345 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2346 cmdinfo.work);
2347 int status = nvmeq->cmdinfo.status;
2348
2349 if (!status)
2350 status = nvme_delete_cq(nvmeq);
2351 if (status)
2352 nvme_del_queue_end(nvmeq);
2353}
2354
2355static int nvme_delete_sq(struct nvme_queue *nvmeq)
2356{
2357 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2358 nvme_del_sq_work_handler);
2359}
2360
2361static void nvme_del_queue_start(struct kthread_work *work)
2362{
2363 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2364 cmdinfo.work);
4d115420
KB		 2365 if (nvme_delete_sq(nvmeq))
2366 nvme_del_queue_end(nvmeq);
2367}
2368
2369static void nvme_disable_io_queues(struct nvme_dev *dev)
2370{
2371 int i;
2372 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2373 struct nvme_delq_ctx dq;
2374 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2375 &worker, "nvme%d", dev->instance);
2376
2377 if (IS_ERR(kworker_task)) {
2378 dev_err(&dev->pci_dev->dev,
2379 "Failed to create queue del task\n");
2380 for (i = dev->queue_count - 1; i > 0; i--)
2381 nvme_disable_queue(dev, i);
2382 return;
2383 }
2384
2385 dq.waiter = NULL;
2386 atomic_set(&dq.refcount, 0);
2387 dq.worker = &worker;
2388 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2389 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2390
2391 if (nvme_suspend_queue(nvmeq))
2392 continue;
2393 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2394 nvmeq->cmdinfo.worker = dq.worker;
2395 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2396 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2397 }
2398 nvme_wait_dq(&dq, dev);
2399 kthread_stop(kworker_task);
2400}
2401
b9afca3e
DM		 2402/*
2403* Remove the node from the device list and check
2404* for whether or not we need to stop the nvme_thread.
2405*/
2406static void nvme_dev_list_remove(struct nvme_dev *dev)
2407{
2408 struct task_struct *tmp = NULL;
2409
2410 spin_lock(&dev_list_lock);
2411 list_del_init(&dev->node);
2412 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2413 tmp = nvme_thread;
2414 nvme_thread = NULL;
2415 }
2416 spin_unlock(&dev_list_lock);
2417
2418 if (tmp)
2419 kthread_stop(tmp);
2420}
2421
c9d3bf88
KB		 2422static void nvme_freeze_queues(struct nvme_dev *dev)
2423{
2424 struct nvme_ns *ns;
2425
2426 list_for_each_entry(ns, &dev->namespaces, list) {
2427 blk_mq_freeze_queue_start(ns->queue);
2428
2429 spin_lock(ns->queue->queue_lock);
2430 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2431 spin_unlock(ns->queue->queue_lock);
2432
2433 blk_mq_cancel_requeue_work(ns->queue);
2434 blk_mq_stop_hw_queues(ns->queue);
2435 }
2436}
2437
2438static void nvme_unfreeze_queues(struct nvme_dev *dev)
2439{
2440 struct nvme_ns *ns;
2441
2442 list_for_each_entry(ns, &dev->namespaces, list) {
2443 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2444 blk_mq_unfreeze_queue(ns->queue);
2445 blk_mq_start_stopped_hw_queues(ns->queue, true);
2446 blk_mq_kick_requeue_list(ns->queue);
2447 }
2448}
2449
f0b50732 2450static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2451{
22404274 2452 int i;
7c1b2450 2453 u32 csts = -1;
22404274 2454
d4b4ff8e 2455 dev->initialized = 0;
b9afca3e 2456 nvme_dev_list_remove(dev);
1fa6aead 2457
c9d3bf88
KB		 2458 if (dev->bar) {
2459 nvme_freeze_queues(dev);
7c1b2450 2460 csts = readl(&dev->bar->csts);
c9d3bf88 2461 }
7c1b2450 2462 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2463 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2464 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2465 nvme_suspend_queue(nvmeq);
2466 nvme_clear_queue(nvmeq);
2467 }
2468 } else {
2469 nvme_disable_io_queues(dev);
1894d8f1 2470 nvme_shutdown_ctrl(dev);
4d115420
KB		 2471 nvme_disable_queue(dev, 0);
2472 }
f0b50732
KB		 2473 nvme_dev_unmap(dev);
2474}
2475
2476static void nvme_dev_remove(struct nvme_dev *dev)
2477{
9ac27090 2478 struct nvme_ns *ns;
f0b50732 2479
9ac27090
KB		 2480 list_for_each_entry(ns, &dev->namespaces, list) {
2481 if (ns->disk->flags & GENHD_FL_UP)
2482 del_gendisk(ns->disk);
cef6a948
KB		 2483 if (!blk_queue_dying(ns->queue)) {
2484 blk_mq_abort_requeue_list(ns->queue);
9ac27090 2485 blk_cleanup_queue(ns->queue);
cef6a948 2486 }
b60503ba 2487 }
b60503ba
MW		 2488}
2489
091b6092
MW		 2490static int nvme_setup_prp_pools(struct nvme_dev *dev)
2491{
2492 struct device *dmadev = &dev->pci_dev->dev;
2493 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2494 PAGE_SIZE, PAGE_SIZE, 0);
2495 if (!dev->prp_page_pool)
2496 return -ENOMEM;
2497
99802a7a
MW		 2498 /* Optimisation for I/Os between 4k and 128k */
2499 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2500 256, 256, 0);
2501 if (!dev->prp_small_pool) {
2502 dma_pool_destroy(dev->prp_page_pool);
2503 return -ENOMEM;
2504 }
091b6092
MW		 2505 return 0;
2506}
2507
2508static void nvme_release_prp_pools(struct nvme_dev *dev)
2509{
2510 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2511 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2512}
2513
cd58ad7d
QSA		 2514static DEFINE_IDA(nvme_instance_ida);
2515
2516static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2517{
cd58ad7d
QSA		 2518 int instance, error;
2519
2520 do {
2521 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2522 return -ENODEV;
2523
2524 spin_lock(&dev_list_lock);
2525 error = ida_get_new(&nvme_instance_ida, &instance);
2526 spin_unlock(&dev_list_lock);
2527 } while (error == -EAGAIN);
2528
2529 if (error)
2530 return -ENODEV;
2531
2532 dev->instance = instance;
2533 return 0;
b60503ba
MW		 2534}
2535
2536static void nvme_release_instance(struct nvme_dev *dev)
2537{
cd58ad7d
QSA		 2538 spin_lock(&dev_list_lock);
2539 ida_remove(&nvme_instance_ida, dev->instance);
2540 spin_unlock(&dev_list_lock);
b60503ba
MW		 2541}
2542
9ac27090
KB		 2543static void nvme_free_namespaces(struct nvme_dev *dev)
2544{
2545 struct nvme_ns *ns, *next;
2546
2547 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2548 list_del(&ns->list);
9e60352c
KB		 2549
2550 spin_lock(&dev_list_lock);
2551 ns->disk->private_data = NULL;
2552 spin_unlock(&dev_list_lock);
2553
9ac27090
KB		 2554 put_disk(ns->disk);
2555 kfree(ns);
2556 }
2557}
2558
5e82e952
KB		 2559static void nvme_free_dev(struct kref *kref)
2560{
2561 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2562
a96d4f5c 2563 pci_dev_put(dev->pci_dev);
9ac27090 2564 nvme_free_namespaces(dev);
285dffc9 2565 nvme_release_instance(dev);
a4aea562 2566 blk_mq_free_tag_set(&dev->tagset);
ea191d2f 2567 blk_put_queue(dev->admin_q);
5e82e952
KB		 2568 kfree(dev->queues);
2569 kfree(dev->entry);
2570 kfree(dev);
2571}
2572
2573static int nvme_dev_open(struct inode *inode, struct file *f)
2574{
2575 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2576 miscdev);
2577 kref_get(&dev->kref);
2578 f->private_data = dev;
2579 return 0;
2580}
2581
2582static int nvme_dev_release(struct inode *inode, struct file *f)
2583{
2584 struct nvme_dev *dev = f->private_data;
2585 kref_put(&dev->kref, nvme_free_dev);
2586 return 0;
2587}
2588
2589static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2590{
2591 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2592 struct nvme_ns *ns;
2593
5e82e952
KB		 2594 switch (cmd) {
2595 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2596 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2597 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2598 if (list_empty(&dev->namespaces))
2599 return -ENOTTY;
2600 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2601 return nvme_user_cmd(dev, ns, (void __user *)arg);
5e82e952
KB		 2602 default:
2603 return -ENOTTY;
2604 }
2605}
2606
2607static const struct file_operations nvme_dev_fops = {
2608 .owner = THIS_MODULE,
2609 .open = nvme_dev_open,
2610 .release = nvme_dev_release,
2611 .unlocked_ioctl = nvme_dev_ioctl,
2612 .compat_ioctl = nvme_dev_ioctl,
2613};
2614
a4aea562
MB		 2615static void nvme_set_irq_hints(struct nvme_dev *dev)
2616{
2617 struct nvme_queue *nvmeq;
2618 int i;
2619
2620 for (i = 0; i < dev->online_queues; i++) {
2621 nvmeq = dev->queues[i];
2622
2623 if (!nvmeq->hctx)
2624 continue;
2625
2626 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2627 nvmeq->hctx->cpumask);
2628 }
2629}
2630
f0b50732
KB		 2631static int nvme_dev_start(struct nvme_dev *dev)
2632{
2633 int result;
b9afca3e 2634 bool start_thread = false;
f0b50732
KB		 2635
2636 result = nvme_dev_map(dev);
2637 if (result)
2638 return result;
2639
2640 result = nvme_configure_admin_queue(dev);
2641 if (result)
2642 goto unmap;
2643
2644 spin_lock(&dev_list_lock);
b9afca3e
DM		 2645 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2646 start_thread = true;
2647 nvme_thread = NULL;
2648 }
f0b50732
KB		 2649 list_add(&dev->node, &dev_list);
2650 spin_unlock(&dev_list_lock);
2651
b9afca3e
DM		 2652 if (start_thread) {
2653 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2654 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2655 } else
2656 wait_event_killable(nvme_kthread_wait, nvme_thread);
2657
2658 if (IS_ERR_OR_NULL(nvme_thread)) {
2659 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2660 goto disable;
2661 }
a4aea562
MB		 2662
2663 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 2664 result = nvme_alloc_admin_tags(dev);
2665 if (result)
2666 goto disable;
b9afca3e 2667
f0b50732 2668 result = nvme_setup_io_queues(dev);
badc34d4 2669 if (result)
0fb59cbc 2670 goto free_tags;
f0b50732 2671
a4aea562
MB		 2672 nvme_set_irq_hints(dev);
2673
d82e8bfd 2674 return result;
f0b50732 2675
0fb59cbc
KB		 2676 free_tags:
2677 nvme_dev_remove_admin(dev);
f0b50732 2678 disable:
a1a5ef99 2679 nvme_disable_queue(dev, 0);
b9afca3e 2680 nvme_dev_list_remove(dev);
f0b50732
KB		 2681 unmap:
2682 nvme_dev_unmap(dev);
2683 return result;
2684}
2685
9a6b9458
KB		 2686static int nvme_remove_dead_ctrl(void *arg)
2687{
2688 struct nvme_dev *dev = (struct nvme_dev *)arg;
2689 struct pci_dev *pdev = dev->pci_dev;
2690
2691 if (pci_get_drvdata(pdev))
c81f4975 2692 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2693 kref_put(&dev->kref, nvme_free_dev);
2694 return 0;
2695}
2696
2697static void nvme_remove_disks(struct work_struct *ws)
2698{
9a6b9458
KB		 2699 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2700
5a92e700 2701 nvme_free_queues(dev, 1);
302c6727 2702 nvme_dev_remove(dev);
9a6b9458
KB		 2703}
2704
2705static int nvme_dev_resume(struct nvme_dev *dev)
2706{
2707 int ret;
2708
2709 ret = nvme_dev_start(dev);
badc34d4 2710 if (ret)
9a6b9458 2711 return ret;
badc34d4 2712 if (dev->online_queues < 2) {
9a6b9458 2713 spin_lock(&dev_list_lock);
9ca97374 2714 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2715 queue_work(nvme_workq, &dev->reset_work);
2716 spin_unlock(&dev_list_lock);
c9d3bf88
KB		 2717 } else {
2718 nvme_unfreeze_queues(dev);
2719 nvme_set_irq_hints(dev);
9a6b9458 2720 }
d4b4ff8e 2721 dev->initialized = 1;
9a6b9458
KB		 2722 return 0;
2723}
2724
2725static void nvme_dev_reset(struct nvme_dev *dev)
2726{
2727 nvme_dev_shutdown(dev);
2728 if (nvme_dev_resume(dev)) {
a4aea562 2729 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
9a6b9458
KB		 2730 kref_get(&dev->kref);
2731 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2732 dev->instance))) {
2733 dev_err(&dev->pci_dev->dev,
2734 "Failed to start controller remove task\n");
2735 kref_put(&dev->kref, nvme_free_dev);
2736 }
2737 }
2738}
2739
2740static void nvme_reset_failed_dev(struct work_struct *ws)
2741{
2742 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2743 nvme_dev_reset(dev);
2744}
2745
9ca97374
TH		 2746static void nvme_reset_workfn(struct work_struct *work)
2747{
2748 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2749 dev->reset_workfn(work);
2750}
2751
8d85fce7 2752static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2753{
a4aea562 2754 int node, result = -ENOMEM;
b60503ba
MW		 2755 struct nvme_dev *dev;
2756
a4aea562
MB		 2757 node = dev_to_node(&pdev->dev);
2758 if (node == NUMA_NO_NODE)
2759 set_dev_node(&pdev->dev, 0);
2760
2761 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2762 if (!dev)
2763 return -ENOMEM;
a4aea562
MB		 2764 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2765 GFP_KERNEL, node);
b60503ba
MW		 2766 if (!dev->entry)
2767 goto free;
a4aea562
MB		 2768 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2769 GFP_KERNEL, node);
b60503ba
MW		 2770 if (!dev->queues)
2771 goto free;
2772
2773 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2774 dev->reset_workfn = nvme_reset_failed_dev;
2775 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
a96d4f5c 2776 dev->pci_dev = pci_dev_get(pdev);
9a6b9458 2777 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2778 result = nvme_set_instance(dev);
2779 if (result)
a96d4f5c 2780 goto put_pci;
b60503ba 2781
091b6092
MW		 2782 result = nvme_setup_prp_pools(dev);
2783 if (result)
0877cb0d 2784 goto release;
091b6092 2785
fb35e914 2786 kref_init(&dev->kref);
f0b50732 2787 result = nvme_dev_start(dev);
badc34d4 2788 if (result)
0877cb0d 2789 goto release_pools;
b60503ba 2790
badc34d4
KB		 2791 if (dev->online_queues > 1)
2792 result = nvme_dev_add(dev);
d82e8bfd 2793 if (result)
f0b50732 2794 goto shutdown;
740216fc 2795
5e82e952
KB		 2796 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2797 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2798 dev->miscdev.parent = &pdev->dev;
2799 dev->miscdev.name = dev->name;
2800 dev->miscdev.fops = &nvme_dev_fops;
2801 result = misc_register(&dev->miscdev);
2802 if (result)
2803 goto remove;
2804
a4aea562
MB		 2805 nvme_set_irq_hints(dev);
2806
d4b4ff8e 2807 dev->initialized = 1;
b60503ba
MW		 2808 return 0;
2809
5e82e952
KB		 2810 remove:
2811 nvme_dev_remove(dev);
a4aea562 2812 nvme_dev_remove_admin(dev);
9ac27090 2813 nvme_free_namespaces(dev);
f0b50732
KB		 2814 shutdown:
2815 nvme_dev_shutdown(dev);
0877cb0d 2816 release_pools:
a1a5ef99 2817 nvme_free_queues(dev, 0);
091b6092 2818 nvme_release_prp_pools(dev);
0877cb0d
KB		 2819 release:
2820 nvme_release_instance(dev);
a96d4f5c
KB		 2821 put_pci:
2822 pci_dev_put(dev->pci_dev);
b60503ba
MW		 2823 free:
2824 kfree(dev->queues);
2825 kfree(dev->entry);
2826 kfree(dev);
2827 return result;
2828}
2829
f0d54a54
KB		 2830static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2831{
a6739479 2832 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 2833
a6739479
KB		 2834 if (prepare)
2835 nvme_dev_shutdown(dev);
2836 else
2837 nvme_dev_resume(dev);
f0d54a54
KB		 2838}
2839
09ece142
KB		 2840static void nvme_shutdown(struct pci_dev *pdev)
2841{
2842 struct nvme_dev *dev = pci_get_drvdata(pdev);
2843 nvme_dev_shutdown(dev);
2844}
2845
8d85fce7 2846static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2847{
2848 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2849
2850 spin_lock(&dev_list_lock);
2851 list_del_init(&dev->node);
2852 spin_unlock(&dev_list_lock);
2853
2854 pci_set_drvdata(pdev, NULL);
2855 flush_work(&dev->reset_work);
5e82e952 2856 misc_deregister(&dev->miscdev);
9a6b9458 2857 nvme_dev_shutdown(dev);
c9d3bf88 2858 nvme_dev_remove(dev);
a4aea562 2859 nvme_dev_remove_admin(dev);
a1a5ef99 2860 nvme_free_queues(dev, 0);
9a6b9458 2861 nvme_release_prp_pools(dev);
5e82e952 2862 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2863}
2864
2865/* These functions are yet to be implemented */
2866#define nvme_error_detected NULL
2867#define nvme_dump_registers NULL
2868#define nvme_link_reset NULL
2869#define nvme_slot_reset NULL
2870#define nvme_error_resume NULL
cd638946 2871
671a6018 2872#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2873static int nvme_suspend(struct device *dev)
2874{
2875 struct pci_dev *pdev = to_pci_dev(dev);
2876 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2877
2878 nvme_dev_shutdown(ndev);
2879 return 0;
2880}
2881
2882static int nvme_resume(struct device *dev)
2883{
2884 struct pci_dev *pdev = to_pci_dev(dev);
2885 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2886
9a6b9458 2887 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2888 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 2889 queue_work(nvme_workq, &ndev->reset_work);
2890 }
2891 return 0;
cd638946 2892}
671a6018 2893#endif
cd638946
KB		 2894
2895static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2896
1d352035 2897static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2898 .error_detected = nvme_error_detected,
2899 .mmio_enabled = nvme_dump_registers,
2900 .link_reset = nvme_link_reset,
2901 .slot_reset = nvme_slot_reset,
2902 .resume = nvme_error_resume,
f0d54a54 2903 .reset_notify = nvme_reset_notify,
b60503ba
MW		 2904};
2905
2906/* Move to pci_ids.h later */
2907#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2908
6eb0d698 2909static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2910 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2911 { 0, }
2912};
2913MODULE_DEVICE_TABLE(pci, nvme_id_table);
2914
2915static struct pci_driver nvme_driver = {
2916 .name = "nvme",
2917 .id_table = nvme_id_table,
2918 .probe = nvme_probe,
8d85fce7 2919 .remove = nvme_remove,
09ece142 2920 .shutdown = nvme_shutdown,
cd638946
KB		 2921 .driver = {
2922 .pm = &nvme_dev_pm_ops,
2923 },
b60503ba
MW		 2924 .err_handler = &nvme_err_handler,
2925};
2926
2927static int __init nvme_init(void)
2928{
0ac13140 2929 int result;
1fa6aead 2930
b9afca3e 2931 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2932
9a6b9458
KB		 2933 nvme_workq = create_singlethread_workqueue("nvme");
2934 if (!nvme_workq)
b9afca3e 2935 return -ENOMEM;
9a6b9458 2936
5c42ea16
KB		 2937 result = register_blkdev(nvme_major, "nvme");
2938 if (result < 0)
9a6b9458 2939 goto kill_workq;
5c42ea16 2940 else if (result > 0)
0ac13140 2941 nvme_major = result;
b60503ba 2942
f3db22fe
KB		 2943 result = pci_register_driver(&nvme_driver);
2944 if (result)
a4aea562 2945 goto unregister_blkdev;
1fa6aead 2946 return 0;
b60503ba 2947
1fa6aead 2948 unregister_blkdev:
b60503ba 2949 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2950 kill_workq:
2951 destroy_workqueue(nvme_workq);
b60503ba
MW		 2952 return result;
2953}
2954
2955static void __exit nvme_exit(void)
2956{
2957 pci_unregister_driver(&nvme_driver);
f3db22fe 2958 unregister_hotcpu_notifier(&nvme_nb);
b60503ba 2959 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2960 destroy_workqueue(nvme_workq);
b9afca3e 2961 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 2962 _nvme_check_size();
b60503ba
MW		 2963}
2964
2965MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2966MODULE_LICENSE("GPL");
c78b4713 2967MODULE_VERSION("1.0");
b60503ba
MW		 2968module_init(nvme_init);
2969module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)