projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
nvme: Fix PRP list calculation for non-4k system page size
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
e1e5e564 40#include <linux/t10-pi.h>
b60503ba 41#include <linux/types.h>
5d0f6131 42#include <scsi/sg.h>
797a796a
HM		 43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
b3fffdef 45#define NVME_MINORS (1U << MINORBITS)
9d43cf64 46#define NVME_Q_DEPTH 1024
a4aea562 47#define NVME_AQ_DEPTH 64
b60503ba
MW		 48#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
49#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 50#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 51#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 52
53static unsigned char admin_timeout = 60;
54module_param(admin_timeout, byte, 0644);
55MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 56
bd67608a
MW		 57unsigned char nvme_io_timeout = 30;
58module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 59MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 60
2484f407
DM		 61static unsigned char shutdown_timeout = 5;
62module_param(shutdown_timeout, byte, 0644);
63MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
64
b60503ba
MW		 65static int nvme_major;
66module_param(nvme_major, int, 0);
67
b3fffdef
KB		 68static int nvme_char_major;
69module_param(nvme_char_major, int, 0);
70
58ffacb5
MW		 71static int use_threaded_interrupts;
72module_param(use_threaded_interrupts, int, 0);
73
1fa6aead
MW		 74static DEFINE_SPINLOCK(dev_list_lock);
75static LIST_HEAD(dev_list);
76static struct task_struct *nvme_thread;
9a6b9458 77static struct workqueue_struct *nvme_workq;
b9afca3e 78static wait_queue_head_t nvme_kthread_wait;
1fa6aead 79
b3fffdef
KB		 80static struct class *nvme_class;
81
d4b4ff8e 82static void nvme_reset_failed_dev(struct work_struct *ws);
a4aea562 83static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 84
4d115420
KB		 85struct async_cmd_info {
86 struct kthread_work work;
87 struct kthread_worker *worker;
a4aea562 88 struct request *req;
4d115420
KB		 89 u32 result;
90 int status;
91 void *ctx;
92};
1fa6aead 93
b60503ba
MW		 94/*
95 * An NVM Express queue. Each device has at least two (one for admin
96 * commands and one for I/O commands).
97 */
98struct nvme_queue {
99 struct device *q_dmadev;
091b6092 100 struct nvme_dev *dev;
3193f07b 101 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 102 spinlock_t q_lock;
103 struct nvme_command *sq_cmds;
104 volatile struct nvme_completion *cqes;
105 dma_addr_t sq_dma_addr;
106 dma_addr_t cq_dma_addr;
b60503ba
MW		 107 u32 __iomem *q_db;
108 u16 q_depth;
6222d172 109 s16 cq_vector;
b60503ba
MW		 110 u16 sq_head;
111 u16 sq_tail;
112 u16 cq_head;
c30341dc 113 u16 qid;
e9539f47
MW		 114 u8 cq_phase;
115 u8 cqe_seen;
4d115420 116 struct async_cmd_info cmdinfo;
a4aea562 117 struct blk_mq_hw_ctx *hctx;
b60503ba
MW		 118};
119
120/*
121 * Check we didin't inadvertently grow the command struct
122 */
123static inline void _nvme_check_size(void)
124{
125 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 130 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 131 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 136 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 137}
138
edd10d33 139typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 140 struct nvme_completion *);
141
e85248e5 142struct nvme_cmd_info {
c2f5b650
MW		 143 nvme_completion_fn fn;
144 void *ctx;
c30341dc 145 int aborted;
a4aea562 146 struct nvme_queue *nvmeq;
ac3dd5bd 147 struct nvme_iod iod[0];
e85248e5
MW		 148};
149
ac3dd5bd
JA		 150/*
151 * Max size of iod being embedded in the request payload
152 */
153#define NVME_INT_PAGES 2
154#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
fda631ff 155#define NVME_INT_MASK 0x01
ac3dd5bd
JA		 156
157/*
158 * Will slightly overestimate the number of pages needed. This is OK
159 * as it only leads to a small amount of wasted memory for the lifetime of
160 * the I/O.
161 */
162static int nvme_npages(unsigned size, struct nvme_dev *dev)
163{
164 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
165 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
166}
167
168static unsigned int nvme_cmd_size(struct nvme_dev *dev)
169{
170 unsigned int ret = sizeof(struct nvme_cmd_info);
171
172 ret += sizeof(struct nvme_iod);
173 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
174 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
175
176 return ret;
177}
178
a4aea562
MB		 179static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
180 unsigned int hctx_idx)
e85248e5 181{
a4aea562
MB		 182 struct nvme_dev *dev = data;
183 struct nvme_queue *nvmeq = dev->queues[0];
184
185 WARN_ON(nvmeq->hctx);
186 nvmeq->hctx = hctx;
187 hctx->driver_data = nvmeq;
188 return 0;
e85248e5
MW		 189}
190
a4aea562
MB		 191static int nvme_admin_init_request(void *data, struct request *req,
192 unsigned int hctx_idx, unsigned int rq_idx,
193 unsigned int numa_node)
22404274 194{
a4aea562
MB		 195 struct nvme_dev *dev = data;
196 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
197 struct nvme_queue *nvmeq = dev->queues[0];
198
199 BUG_ON(!nvmeq);
200 cmd->nvmeq = nvmeq;
201 return 0;
22404274
KB		 202}
203
2c30540b
JA		 204static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
205{
206 struct nvme_queue *nvmeq = hctx->driver_data;
207
208 nvmeq->hctx = NULL;
209}
210
a4aea562
MB		 211static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
212 unsigned int hctx_idx)
b60503ba 213{
a4aea562
MB		 214 struct nvme_dev *dev = data;
215 struct nvme_queue *nvmeq = dev->queues[
216 (hctx_idx % dev->queue_count) + 1];
b60503ba 217
a4aea562
MB		 218 if (!nvmeq->hctx)
219 nvmeq->hctx = hctx;
220
221 /* nvmeq queues are shared between namespaces. We assume here that
222 * blk-mq map the tags so they match up with the nvme queue tags. */
223 WARN_ON(nvmeq->hctx->tags != hctx->tags);
b60503ba 224
a4aea562
MB		 225 hctx->driver_data = nvmeq;
226 return 0;
b60503ba
MW		 227}
228
a4aea562
MB		 229static int nvme_init_request(void *data, struct request *req,
230 unsigned int hctx_idx, unsigned int rq_idx,
231 unsigned int numa_node)
b60503ba 232{
a4aea562
MB		 233 struct nvme_dev *dev = data;
234 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
235 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
236
237 BUG_ON(!nvmeq);
238 cmd->nvmeq = nvmeq;
239 return 0;
240}
241
242static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
243 nvme_completion_fn handler)
244{
245 cmd->fn = handler;
246 cmd->ctx = ctx;
247 cmd->aborted = 0;
c917dfe5 248 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 249}
250
ac3dd5bd
JA		 251static void *iod_get_private(struct nvme_iod *iod)
252{
253 return (void *) (iod->private & ~0x1UL);
254}
255
256/*
257 * If bit 0 is set, the iod is embedded in the request payload.
258 */
259static bool iod_should_kfree(struct nvme_iod *iod)
260{
fda631ff 261 return (iod->private & NVME_INT_MASK) == 0;
ac3dd5bd
JA		 262}
263
c2f5b650
MW		 264/* Special values must be less than 0x1000 */
265#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 266#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
267#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
268#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 269
edd10d33 270static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 271 struct nvme_completion *cqe)
272{
273 if (ctx == CMD_CTX_CANCELLED)
274 return;
c2f5b650 275 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 276 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 277 "completed id %d twice on queue %d\n",
278 cqe->command_id, le16_to_cpup(&cqe->sq_id));
279 return;
280 }
281 if (ctx == CMD_CTX_INVALID) {
edd10d33 282 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 283 "invalid id %d completed on queue %d\n",
284 cqe->command_id, le16_to_cpup(&cqe->sq_id));
285 return;
286 }
edd10d33 287 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 288}
289
a4aea562 290static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 291{
c2f5b650 292 void *ctx;
b60503ba 293
859361a2 294 if (fn)
a4aea562
MB		 295 *fn = cmd->fn;
296 ctx = cmd->ctx;
297 cmd->fn = special_completion;
298 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 299 return ctx;
b60503ba
MW		 300}
301
a4aea562
MB		 302static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
303 struct nvme_completion *cqe)
3c0cf138 304{
a4aea562
MB		 305 u32 result = le32_to_cpup(&cqe->result);
306 u16 status = le16_to_cpup(&cqe->status) >> 1;
307
308 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
309 ++nvmeq->dev->event_limit;
310 if (status == NVME_SC_SUCCESS)
311 dev_warn(nvmeq->q_dmadev,
312 "async event result %08x\n", result);
b60503ba
MW		 313}
314
a4aea562
MB		 315static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
316 struct nvme_completion *cqe)
5a92e700 317{
a4aea562
MB		 318 struct request *req = ctx;
319
320 u16 status = le16_to_cpup(&cqe->status) >> 1;
321 u32 result = le32_to_cpup(&cqe->result);
a51afb54 322
9d135bb8 323 blk_mq_free_hctx_request(nvmeq->hctx, req);
a51afb54 324
a4aea562
MB		 325 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
326 ++nvmeq->dev->abort_limit;
5a92e700
KB		 327}
328
a4aea562
MB		 329static void async_completion(struct nvme_queue *nvmeq, void *ctx,
330 struct nvme_completion *cqe)
b60503ba 331{
a4aea562
MB		 332 struct async_cmd_info *cmdinfo = ctx;
333 cmdinfo->result = le32_to_cpup(&cqe->result);
334 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
335 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
9d135bb8 336 blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
b60503ba
MW		 337}
338
a4aea562
MB		 339static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
340 unsigned int tag)
b60503ba 341{
a4aea562
MB		 342 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
343 struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
a51afb54 344
a4aea562 345 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 346}
347
a4aea562
MB		 348/*
349 * Called with local interrupts disabled and the q_lock held. May not sleep.
350 */
351static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
352 nvme_completion_fn *fn)
4f5099af 353{
a4aea562
MB		 354 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
355 void *ctx;
356 if (tag >= nvmeq->q_depth) {
357 *fn = special_completion;
358 return CMD_CTX_INVALID;
359 }
360 if (fn)
361 *fn = cmd->fn;
362 ctx = cmd->ctx;
363 cmd->fn = special_completion;
364 cmd->ctx = CMD_CTX_COMPLETED;
365 return ctx;
b60503ba
MW		 366}
367
368/**
714a7a22 369 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 370 * @nvmeq: The queue to use
371 * @cmd: The command to send
372 *
373 * Safe to use from interrupt context
374 */
a4aea562 375static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 376{
a4aea562
MB		 377 u16 tail = nvmeq->sq_tail;
378
b60503ba 379 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 380 if (++tail == nvmeq->q_depth)
381 tail = 0;
7547881d 382 writel(tail, nvmeq->q_db);
b60503ba 383 nvmeq->sq_tail = tail;
b60503ba
MW		 384
385 return 0;
386}
387
a4aea562
MB		 388static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
389{
390 unsigned long flags;
391 int ret;
392 spin_lock_irqsave(&nvmeq->q_lock, flags);
393 ret = __nvme_submit_cmd(nvmeq, cmd);
394 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
395 return ret;
396}
397
eca18b23 398static __le64 **iod_list(struct nvme_iod *iod)
e025344c 399{
eca18b23 400 return ((void *)iod) + iod->offset;
e025344c
SMM		 401}
402
ac3dd5bd
JA		 403static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
404 unsigned nseg, unsigned long private)
eca18b23 405{
ac3dd5bd
JA		 406 iod->private = private;
407 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
408 iod->npages = -1;
409 iod->length = nbytes;
410 iod->nents = 0;
eca18b23 411}
b60503ba 412
eca18b23 413static struct nvme_iod *
ac3dd5bd
JA		 414__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
415 unsigned long priv, gfp_t gfp)
b60503ba 416{
eca18b23 417 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 418 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 419 sizeof(struct scatterlist) * nseg, gfp);
420
ac3dd5bd
JA		 421 if (iod)
422 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 423
424 return iod;
b60503ba
MW		 425}
426
ac3dd5bd
JA		 427static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
428 gfp_t gfp)
429{
430 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
431 sizeof(struct nvme_dsm_range);
ac3dd5bd
JA		 432 struct nvme_iod *iod;
433
434 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
435 size <= NVME_INT_BYTES(dev)) {
436 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
437
438 iod = cmd->iod;
ac3dd5bd 439 iod_init(iod, size, rq->nr_phys_segments,
fda631ff 440 (unsigned long) rq | NVME_INT_MASK);
ac3dd5bd
JA		 441 return iod;
442 }
443
444 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
445 (unsigned long) rq, gfp);
446}
447
5d0f6131 448void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 449{
1d090624 450 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 451 int i;
452 __le64 **list = iod_list(iod);
453 dma_addr_t prp_dma = iod->first_dma;
454
455 if (iod->npages == 0)
456 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
457 for (i = 0; i < iod->npages; i++) {
458 __le64 *prp_list = list[i];
459 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
460 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
461 prp_dma = next_prp_dma;
462 }
ac3dd5bd
JA		 463
464 if (iod_should_kfree(iod))
465 kfree(iod);
b60503ba
MW		 466}
467
b4ff9c8d
KB		 468static int nvme_error_status(u16 status)
469{
470 switch (status & 0x7ff) {
471 case NVME_SC_SUCCESS:
472 return 0;
473 case NVME_SC_CAP_EXCEEDED:
474 return -ENOSPC;
475 default:
476 return -EIO;
477 }
478}
479
52b68d7e 480#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 481static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
482{
483 if (be32_to_cpu(pi->ref_tag) == v)
484 pi->ref_tag = cpu_to_be32(p);
485}
486
487static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
488{
489 if (be32_to_cpu(pi->ref_tag) == p)
490 pi->ref_tag = cpu_to_be32(v);
491}
492
493/**
494 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
495 *
496 * The virtual start sector is the one that was originally submitted by the
497 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
498 * start sector may be different. Remap protection information to match the
499 * physical LBA on writes, and back to the original seed on reads.
500 *
501 * Type 0 and 3 do not have a ref tag, so no remapping required.
502 */
503static void nvme_dif_remap(struct request *req,
504 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
505{
506 struct nvme_ns *ns = req->rq_disk->private_data;
507 struct bio_integrity_payload *bip;
508 struct t10_pi_tuple *pi;
509 void *p, *pmap;
510 u32 i, nlb, ts, phys, virt;
511
512 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
513 return;
514
515 bip = bio_integrity(req->bio);
516 if (!bip)
517 return;
518
519 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
520 if (!pmap)
521 return;
522
523 p = pmap;
524 virt = bip_get_seed(bip);
525 phys = nvme_block_nr(ns, blk_rq_pos(req));
526 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
527 ts = ns->disk->integrity->tuple_size;
528
529 for (i = 0; i < nlb; i++, virt++, phys++) {
530 pi = (struct t10_pi_tuple *)p;
531 dif_swap(phys, virt, pi);
532 p += ts;
533 }
534 kunmap_atomic(pmap);
535}
536
52b68d7e
KB		 537static int nvme_noop_verify(struct blk_integrity_iter *iter)
538{
539 return 0;
540}
541
542static int nvme_noop_generate(struct blk_integrity_iter *iter)
543{
544 return 0;
545}
546
547struct blk_integrity nvme_meta_noop = {
548 .name = "NVME_META_NOOP",
549 .generate_fn = nvme_noop_generate,
550 .verify_fn = nvme_noop_verify,
551};
552
553static void nvme_init_integrity(struct nvme_ns *ns)
554{
555 struct blk_integrity integrity;
556
557 switch (ns->pi_type) {
558 case NVME_NS_DPS_PI_TYPE3:
559 integrity = t10_pi_type3_crc;
560 break;
561 case NVME_NS_DPS_PI_TYPE1:
562 case NVME_NS_DPS_PI_TYPE2:
563 integrity = t10_pi_type1_crc;
564 break;
565 default:
566 integrity = nvme_meta_noop;
567 break;
568 }
569 integrity.tuple_size = ns->ms;
570 blk_integrity_register(ns->disk, &integrity);
571 blk_queue_max_integrity_segments(ns->queue, 1);
572}
573#else /* CONFIG_BLK_DEV_INTEGRITY */
574static void nvme_dif_remap(struct request *req,
575 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
576{
577}
578static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
579{
580}
581static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
582{
583}
584static void nvme_init_integrity(struct nvme_ns *ns)
585{
586}
587#endif
588
a4aea562 589static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 590 struct nvme_completion *cqe)
591{
eca18b23 592 struct nvme_iod *iod = ctx;
ac3dd5bd 593 struct request *req = iod_get_private(iod);
a4aea562
MB		 594 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
595
b60503ba
MW		 596 u16 status = le16_to_cpup(&cqe->status) >> 1;
597
edd10d33 598 if (unlikely(status)) {
a4aea562
MB		 599 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
600 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 601 unsigned long flags;
602
a4aea562 603 blk_mq_requeue_request(req);
c9d3bf88
KB		 604 spin_lock_irqsave(req->q->queue_lock, flags);
605 if (!blk_queue_stopped(req->q))
606 blk_mq_kick_requeue_list(req->q);
607 spin_unlock_irqrestore(req->q->queue_lock, flags);
edd10d33
KB		 608 return;
609 }
a4aea562
MB		 610 req->errors = nvme_error_status(status);
611 } else
612 req->errors = 0;
613
614 if (cmd_rq->aborted)
615 dev_warn(&nvmeq->dev->pci_dev->dev,
616 "completing aborted command with status:%04x\n",
617 status);
618
e1e5e564 619 if (iod->nents) {
a4aea562
MB		 620 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
621 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
e1e5e564
KB		 622 if (blk_integrity_rq(req)) {
623 if (!rq_data_dir(req))
624 nvme_dif_remap(req, nvme_dif_complete);
625 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->meta_sg, 1,
626 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
627 }
628 }
edd10d33 629 nvme_free_iod(nvmeq->dev, iod);
3291fa57 630
a4aea562 631 blk_mq_complete_request(req);
b60503ba
MW		 632}
633
184d2944 634/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 635int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
636 gfp_t gfp)
ff22b54f 637{
99802a7a 638 struct dma_pool *pool;
eca18b23
MW		 639 int length = total_len;
640 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 641 int dma_len = sg_dma_len(sg);
642 u64 dma_addr = sg_dma_address(sg);
f137e0f1
MI		 643 u32 page_size = dev->page_size;
644 int offset = dma_addr & (page_size - 1);
e025344c 645 __le64 *prp_list;
eca18b23 646 __le64 **list = iod_list(iod);
e025344c 647 dma_addr_t prp_dma;
eca18b23 648 int nprps, i;
ff22b54f 649
1d090624 650 length -= (page_size - offset);
ff22b54f 651 if (length <= 0)
eca18b23 652 return total_len;
ff22b54f 653
1d090624 654 dma_len -= (page_size - offset);
ff22b54f 655 if (dma_len) {
1d090624 656 dma_addr += (page_size - offset);
ff22b54f
MW		 657 } else {
658 sg = sg_next(sg);
659 dma_addr = sg_dma_address(sg);
660 dma_len = sg_dma_len(sg);
661 }
662
1d090624 663 if (length <= page_size) {
edd10d33 664 iod->first_dma = dma_addr;
eca18b23 665 return total_len;
e025344c
SMM		 666 }
667
1d090624 668 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 669 if (nprps <= (256 / 8)) {
670 pool = dev->prp_small_pool;
eca18b23 671 iod->npages = 0;
99802a7a
MW		 672 } else {
673 pool = dev->prp_page_pool;
eca18b23 674 iod->npages = 1;
99802a7a
MW		 675 }
676
b77954cb
MW		 677 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
678 if (!prp_list) {
edd10d33 679 iod->first_dma = dma_addr;
eca18b23 680 iod->npages = -1;
1d090624 681 return (total_len - length) + page_size;
b77954cb 682 }
eca18b23
MW		 683 list[0] = prp_list;
684 iod->first_dma = prp_dma;
e025344c
SMM		 685 i = 0;
686 for (;;) {
1d090624 687 if (i == page_size >> 3) {
e025344c 688 __le64 *old_prp_list = prp_list;
b77954cb 689 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 690 if (!prp_list)
691 return total_len - length;
692 list[iod->npages++] = prp_list;
7523d834
MW		 693 prp_list[0] = old_prp_list[i - 1];
694 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
695 i = 1;
e025344c
SMM		 696 }
697 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 698 dma_len -= page_size;
699 dma_addr += page_size;
700 length -= page_size;
e025344c
SMM		 701 if (length <= 0)
702 break;
703 if (dma_len > 0)
704 continue;
705 BUG_ON(dma_len < 0);
706 sg = sg_next(sg);
707 dma_addr = sg_dma_address(sg);
708 dma_len = sg_dma_len(sg);
ff22b54f
MW		 709 }
710
eca18b23 711 return total_len;
ff22b54f
MW		 712}
713
a4aea562
MB		 714/*
715 * We reuse the small pool to allocate the 16-byte range here as it is not
716 * worth having a special pool for these or additional cases to handle freeing
717 * the iod.
718 */
719static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
720 struct request *req, struct nvme_iod *iod)
0e5e4f0e 721{
edd10d33
KB		 722 struct nvme_dsm_range *range =
723 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 724 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
725
0e5e4f0e 726 range->cattr = cpu_to_le32(0);
a4aea562
MB		 727 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
728 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e
KB		 729
730 memset(cmnd, 0, sizeof(*cmnd));
731 cmnd->dsm.opcode = nvme_cmd_dsm;
a4aea562 732 cmnd->dsm.command_id = req->tag;
0e5e4f0e
KB		 733 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
734 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
735 cmnd->dsm.nr = 0;
736 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
737
738 if (++nvmeq->sq_tail == nvmeq->q_depth)
739 nvmeq->sq_tail = 0;
740 writel(nvmeq->sq_tail, nvmeq->q_db);
0e5e4f0e
KB		 741}
742
a4aea562 743static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 744 int cmdid)
745{
746 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
747
748 memset(cmnd, 0, sizeof(*cmnd));
749 cmnd->common.opcode = nvme_cmd_flush;
750 cmnd->common.command_id = cmdid;
751 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
752
753 if (++nvmeq->sq_tail == nvmeq->q_depth)
754 nvmeq->sq_tail = 0;
755 writel(nvmeq->sq_tail, nvmeq->q_db);
00df5cb4
MW		 756}
757
a4aea562
MB		 758static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
759 struct nvme_ns *ns)
b60503ba 760{
ac3dd5bd 761 struct request *req = iod_get_private(iod);
ff22b54f 762 struct nvme_command *cmnd;
a4aea562
MB		 763 u16 control = 0;
764 u32 dsmgmt = 0;
00df5cb4 765
a4aea562 766 if (req->cmd_flags & REQ_FUA)
b60503ba 767 control |= NVME_RW_FUA;
a4aea562 768 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 769 control |= NVME_RW_LR;
770
a4aea562 771 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 772 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
773
ff22b54f 774 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 775 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 776
a4aea562
MB		 777 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
778 cmnd->rw.command_id = req->tag;
ff22b54f 779 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 780 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
781 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
a4aea562
MB		 782 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
783 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
e1e5e564
KB		 784
785 if (blk_integrity_rq(req)) {
786 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
787 switch (ns->pi_type) {
788 case NVME_NS_DPS_PI_TYPE3:
789 control |= NVME_RW_PRINFO_PRCHK_GUARD;
790 break;
791 case NVME_NS_DPS_PI_TYPE1:
792 case NVME_NS_DPS_PI_TYPE2:
793 control |= NVME_RW_PRINFO_PRCHK_GUARD |
794 NVME_RW_PRINFO_PRCHK_REF;
795 cmnd->rw.reftag = cpu_to_le32(
796 nvme_block_nr(ns, blk_rq_pos(req)));
797 break;
798 }
799 } else if (ns->ms)
800 control |= NVME_RW_PRINFO_PRACT;
801
ff22b54f
MW		 802 cmnd->rw.control = cpu_to_le16(control);
803 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 804
b60503ba
MW		 805 if (++nvmeq->sq_tail == nvmeq->q_depth)
806 nvmeq->sq_tail = 0;
7547881d 807 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 808
1974b1ae 809 return 0;
edd10d33
KB		 810}
811
a4aea562
MB		 812static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
813 const struct blk_mq_queue_data *bd)
edd10d33 814{
a4aea562
MB		 815 struct nvme_ns *ns = hctx->queue->queuedata;
816 struct nvme_queue *nvmeq = hctx->driver_data;
817 struct request *req = bd->rq;
818 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 819 struct nvme_iod *iod;
a4aea562 820 enum dma_data_direction dma_dir;
edd10d33 821
e1e5e564
KB		 822 /*
823 * If formated with metadata, require the block layer provide a buffer
824 * unless this namespace is formated such that the metadata can be
825 * stripped/generated by the controller with PRACT=1.
826 */
827 if (ns->ms && !blk_integrity_rq(req)) {
828 if (!(ns->pi_type && ns->ms == 8)) {
829 req->errors = -EFAULT;
830 blk_mq_complete_request(req);
831 return BLK_MQ_RQ_QUEUE_OK;
832 }
833 }
834
ac3dd5bd 835 iod = nvme_alloc_iod(req, ns->dev, GFP_ATOMIC);
edd10d33 836 if (!iod)
fe54303e 837 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 838
a4aea562 839 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 840 void *range;
841 /*
842 * We reuse the small pool to allocate the 16-byte range here
843 * as it is not worth having a special pool for these or
844 * additional cases to handle freeing the iod.
845 */
846 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
847 GFP_ATOMIC,
848 &iod->first_dma);
a4aea562 849 if (!range)
fe54303e 850 goto retry_cmd;
edd10d33
KB		 851 iod_list(iod)[0] = (__le64 *)range;
852 iod->npages = 0;
ac3dd5bd 853 } else if (req->nr_phys_segments) {
a4aea562
MB		 854 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
855
ac3dd5bd 856 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 857 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 858 if (!iod->nents)
859 goto error_cmd;
a4aea562
MB		 860
861 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 862 goto retry_cmd;
a4aea562 863
fe54303e
JA		 864 if (blk_rq_bytes(req) !=
865 nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
866 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg,
867 iod->nents, dma_dir);
868 goto retry_cmd;
869 }
e1e5e564
KB		 870 if (blk_integrity_rq(req)) {
871 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
872 goto error_cmd;
873
874 sg_init_table(iod->meta_sg, 1);
875 if (blk_rq_map_integrity_sg(
876 req->q, req->bio, iod->meta_sg) != 1)
877 goto error_cmd;
878
879 if (rq_data_dir(req))
880 nvme_dif_remap(req, nvme_dif_prep);
881
882 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
883 goto error_cmd;
884 }
edd10d33 885 }
1974b1ae 886
9af8785a 887 nvme_set_info(cmd, iod, req_completion);
a4aea562
MB		 888 spin_lock_irq(&nvmeq->q_lock);
889 if (req->cmd_flags & REQ_DISCARD)
890 nvme_submit_discard(nvmeq, ns, req, iod);
891 else if (req->cmd_flags & REQ_FLUSH)
892 nvme_submit_flush(nvmeq, ns, req->tag);
893 else
894 nvme_submit_iod(nvmeq, iod, ns);
895
896 nvme_process_cq(nvmeq);
897 spin_unlock_irq(&nvmeq->q_lock);
898 return BLK_MQ_RQ_QUEUE_OK;
899
fe54303e
JA		 900 error_cmd:
901 nvme_free_iod(nvmeq->dev, iod);
902 return BLK_MQ_RQ_QUEUE_ERROR;
903 retry_cmd:
eca18b23 904 nvme_free_iod(nvmeq->dev, iod);
fe54303e 905 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 906}
907
e9539f47 908static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 909{
82123460 910 u16 head, phase;
b60503ba 911
b60503ba 912 head = nvmeq->cq_head;
82123460 913 phase = nvmeq->cq_phase;
b60503ba
MW		 914
915 for (;;) {
c2f5b650
MW		 916 void *ctx;
917 nvme_completion_fn fn;
b60503ba 918 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 919 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 920 break;
921 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
922 if (++head == nvmeq->q_depth) {
923 head = 0;
82123460 924 phase = !phase;
b60503ba 925 }
a4aea562 926 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 927 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 928 }
929
930 /* If the controller ignores the cq head doorbell and continuously
931 * writes to the queue, it is theoretically possible to wrap around
932 * the queue twice and mistakenly return IRQ_NONE. Linux only
933 * requires that 0.1% of your interrupts are handled, so this isn't
934 * a big problem.
935 */
82123460 936 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 937 return 0;
b60503ba 938
b80d5ccc 939 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 940 nvmeq->cq_head = head;
82123460 941 nvmeq->cq_phase = phase;
b60503ba 942
e9539f47
MW		 943 nvmeq->cqe_seen = 1;
944 return 1;
b60503ba
MW		 945}
946
a4aea562
MB		 947/* Admin queue isn't initialized as a request queue. If at some point this
948 * happens anyway, make sure to notify the user */
949static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
950 const struct blk_mq_queue_data *bd)
7d822457 951{
a4aea562
MB		 952 WARN_ON_ONCE(1);
953 return BLK_MQ_RQ_QUEUE_ERROR;
7d822457
MW		 954}
955
b60503ba 956static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 957{
958 irqreturn_t result;
959 struct nvme_queue *nvmeq = data;
960 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 961 nvme_process_cq(nvmeq);
962 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
963 nvmeq->cqe_seen = 0;
58ffacb5
MW		 964 spin_unlock(&nvmeq->q_lock);
965 return result;
966}
967
968static irqreturn_t nvme_irq_check(int irq, void *data)
969{
970 struct nvme_queue *nvmeq = data;
971 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
972 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
973 return IRQ_NONE;
974 return IRQ_WAKE_THREAD;
975}
976
c2f5b650
MW		 977struct sync_cmd_info {
978 struct task_struct *task;
979 u32 result;
980 int status;
981};
982
edd10d33 983static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 984 struct nvme_completion *cqe)
985{
986 struct sync_cmd_info *cmdinfo = ctx;
987 cmdinfo->result = le32_to_cpup(&cqe->result);
988 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
989 wake_up_process(cmdinfo->task);
990}
991
b60503ba
MW		 992/*
993 * Returns 0 on success. If the result is negative, it's a Linux error code;
994 * if the result is positive, it's an NVM Express status code
995 */
a4aea562 996static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
5d0f6131 997 u32 *result, unsigned timeout)
b60503ba 998{
b60503ba 999 struct sync_cmd_info cmdinfo;
a4aea562
MB		 1000 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1001 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
b60503ba
MW		 1002
1003 cmdinfo.task = current;
1004 cmdinfo.status = -EINTR;
1005
a4aea562
MB		 1006 cmd->common.command_id = req->tag;
1007
1008 nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
b60503ba 1009
0c0f9b95
KB		 1010 set_current_state(TASK_UNINTERRUPTIBLE);
1011 nvme_submit_cmd(nvmeq, cmd);
1012 schedule();
3c0cf138 1013
b60503ba
MW		 1014 if (result)
1015 *result = cmdinfo.result;
b60503ba
MW		 1016 return cmdinfo.status;
1017}
1018
a4aea562
MB		 1019static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1020{
1021 struct nvme_queue *nvmeq = dev->queues[0];
1022 struct nvme_command c;
1023 struct nvme_cmd_info *cmd_info;
1024 struct request *req;
1025
1efccc9d 1026 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
9f173b33
DC		 1027 if (IS_ERR(req))
1028 return PTR_ERR(req);
a4aea562 1029
c917dfe5 1030 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562 1031 cmd_info = blk_mq_rq_to_pdu(req);
1efccc9d 1032 nvme_set_info(cmd_info, NULL, async_req_completion);
a4aea562
MB		 1033
1034 memset(&c, 0, sizeof(c));
1035 c.common.opcode = nvme_admin_async_event;
1036 c.common.command_id = req->tag;
1037
1efccc9d 1038 blk_mq_free_hctx_request(nvmeq->hctx, req);
a4aea562
MB		 1039 return __nvme_submit_cmd(nvmeq, &c);
1040}
1041
1042static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 1043 struct nvme_command *cmd,
1044 struct async_cmd_info *cmdinfo, unsigned timeout)
1045{
a4aea562
MB		 1046 struct nvme_queue *nvmeq = dev->queues[0];
1047 struct request *req;
1048 struct nvme_cmd_info *cmd_rq;
4d115420 1049
a4aea562 1050 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 1051 if (IS_ERR(req))
1052 return PTR_ERR(req);
a4aea562
MB		 1053
1054 req->timeout = timeout;
1055 cmd_rq = blk_mq_rq_to_pdu(req);
1056 cmdinfo->req = req;
1057 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 1058 cmdinfo->status = -EINTR;
a4aea562
MB		 1059
1060 cmd->common.command_id = req->tag;
1061
4f5099af 1062 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 1063}
1064
a64e6bb4 1065static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
a4aea562 1066 u32 *result, unsigned timeout)
b60503ba 1067{
a4aea562
MB		 1068 int res;
1069 struct request *req;
1070
1071 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
97fe3832
JA		 1072 if (IS_ERR(req))
1073 return PTR_ERR(req);
a4aea562 1074 res = nvme_submit_sync_cmd(req, cmd, result, timeout);
9d135bb8 1075 blk_mq_free_request(req);
a4aea562 1076 return res;
4f5099af
KB		 1077}
1078
a4aea562 1079int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
4f5099af
KB		 1080 u32 *result)
1081{
a4aea562 1082 return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 1083}
1084
a4aea562
MB		 1085int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1086 struct nvme_command *cmd, u32 *result)
4d115420 1087{
a4aea562
MB		 1088 int res;
1089 struct request *req;
1090
1091 req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
1092 false);
97fe3832
JA		 1093 if (IS_ERR(req))
1094 return PTR_ERR(req);
a4aea562 1095 res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
9d135bb8 1096 blk_mq_free_request(req);
a4aea562 1097 return res;
4d115420
KB		 1098}
1099
b60503ba
MW		 1100static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1101{
b60503ba
MW		 1102 struct nvme_command c;
1103
1104 memset(&c, 0, sizeof(c));
1105 c.delete_queue.opcode = opcode;
1106 c.delete_queue.qid = cpu_to_le16(id);
1107
a4aea562 1108 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 1109}
1110
1111static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1112 struct nvme_queue *nvmeq)
1113{
b60503ba
MW		 1114 struct nvme_command c;
1115 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1116
1117 memset(&c, 0, sizeof(c));
1118 c.create_cq.opcode = nvme_admin_create_cq;
1119 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1120 c.create_cq.cqid = cpu_to_le16(qid);
1121 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1122 c.create_cq.cq_flags = cpu_to_le16(flags);
1123 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1124
a4aea562 1125 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 1126}
1127
1128static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1129 struct nvme_queue *nvmeq)
1130{
b60503ba
MW		 1131 struct nvme_command c;
1132 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1133
1134 memset(&c, 0, sizeof(c));
1135 c.create_sq.opcode = nvme_admin_create_sq;
1136 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1137 c.create_sq.sqid = cpu_to_le16(qid);
1138 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1139 c.create_sq.sq_flags = cpu_to_le16(flags);
1140 c.create_sq.cqid = cpu_to_le16(qid);
1141
a4aea562 1142 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 1143}
1144
1145static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1146{
1147 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1148}
1149
1150static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1151{
1152 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1153}
1154
5d0f6131 1155int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 1156 dma_addr_t dma_addr)
1157{
1158 struct nvme_command c;
1159
1160 memset(&c, 0, sizeof(c));
1161 c.identify.opcode = nvme_admin_identify;
1162 c.identify.nsid = cpu_to_le32(nsid);
1163 c.identify.prp1 = cpu_to_le64(dma_addr);
1164 c.identify.cns = cpu_to_le32(cns);
1165
1166 return nvme_submit_admin_cmd(dev, &c, NULL);
1167}
1168
5d0f6131 1169int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1170 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1171{
1172 struct nvme_command c;
1173
1174 memset(&c, 0, sizeof(c));
1175 c.features.opcode = nvme_admin_get_features;
a42cecce 1176 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1177 c.features.prp1 = cpu_to_le64(dma_addr);
1178 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1179
08df1e05 1180 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 1181}
1182
5d0f6131
VV		 1183int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1184 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1185{
1186 struct nvme_command c;
1187
1188 memset(&c, 0, sizeof(c));
1189 c.features.opcode = nvme_admin_set_features;
1190 c.features.prp1 = cpu_to_le64(dma_addr);
1191 c.features.fid = cpu_to_le32(fid);
1192 c.features.dword11 = cpu_to_le32(dword11);
1193
bc5fc7e4
MW		 1194 return nvme_submit_admin_cmd(dev, &c, result);
1195}
1196
c30341dc 1197/**
a4aea562 1198 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1199 *
1200 * Schedule controller reset if the command was already aborted once before and
1201 * still hasn't been returned to the driver, or if this is the admin queue.
1202 */
a4aea562 1203static void nvme_abort_req(struct request *req)
c30341dc 1204{
a4aea562
MB		 1205 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1206 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1207 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1208 struct request *abort_req;
1209 struct nvme_cmd_info *abort_cmd;
1210 struct nvme_command cmd;
c30341dc 1211
a4aea562 1212 if (!nvmeq->qid || cmd_rq->aborted) {
7a509a6b
KB		 1213 unsigned long flags;
1214
1215 spin_lock_irqsave(&dev_list_lock, flags);
c30341dc 1216 if (work_busy(&dev->reset_work))
7a509a6b 1217 goto out;
c30341dc
KB		 1218 list_del_init(&dev->node);
1219 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1220 "I/O %d QID %d timeout, reset controller\n",
1221 req->tag, nvmeq->qid);
9ca97374 1222 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc 1223 queue_work(nvme_workq, &dev->reset_work);
7a509a6b
KB		 1224 out:
1225 spin_unlock_irqrestore(&dev_list_lock, flags);
c30341dc
KB		 1226 return;
1227 }
1228
1229 if (!dev->abort_limit)
1230 return;
1231
a4aea562
MB		 1232 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1233 false);
9f173b33 1234 if (IS_ERR(abort_req))
c30341dc
KB		 1235 return;
1236
a4aea562
MB		 1237 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1238 nvme_set_info(abort_cmd, abort_req, abort_completion);
1239
c30341dc
KB		 1240 memset(&cmd, 0, sizeof(cmd));
1241 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1242 cmd.abort.cid = req->tag;
c30341dc 1243 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1244 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1245
1246 --dev->abort_limit;
a4aea562 1247 cmd_rq->aborted = 1;
c30341dc 1248
a4aea562 1249 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1250 nvmeq->qid);
a4aea562
MB		 1251 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1252 dev_warn(nvmeq->q_dmadev,
1253 "Could not abort I/O %d QID %d",
1254 req->tag, nvmeq->qid);
c87fd540 1255 blk_mq_free_request(abort_req);
a4aea562 1256 }
c30341dc
KB		 1257}
1258
a4aea562
MB		 1259static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1260 struct request *req, void *data, bool reserved)
a09115b2 1261{
a4aea562
MB		 1262 struct nvme_queue *nvmeq = data;
1263 void *ctx;
1264 nvme_completion_fn fn;
1265 struct nvme_cmd_info *cmd;
cef6a948
KB		 1266 struct nvme_completion cqe;
1267
1268 if (!blk_mq_request_started(req))
1269 return;
a09115b2 1270
a4aea562 1271 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1272
a4aea562
MB		 1273 if (cmd->ctx == CMD_CTX_CANCELLED)
1274 return;
1275
cef6a948
KB		 1276 if (blk_queue_dying(req->q))
1277 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1278 else
1279 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1280
1281
a4aea562
MB		 1282 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1283 req->tag, nvmeq->qid);
1284 ctx = cancel_cmd_info(cmd, &fn);
1285 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1286}
1287
a4aea562 1288static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1289{
a4aea562
MB		 1290 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1291 struct nvme_queue *nvmeq = cmd->nvmeq;
1292
1293 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1294 nvmeq->qid);
7a509a6b 1295 spin_lock_irq(&nvmeq->q_lock);
07836e65 1296 nvme_abort_req(req);
7a509a6b 1297 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1298
07836e65
KB		 1299 /*
1300 * The aborted req will be completed on receiving the abort req.
1301 * We enable the timer again. If hit twice, it'll cause a device reset,
1302 * as the device then is in a faulty state.
1303 */
1304 return BLK_EH_RESET_TIMER;
a4aea562 1305}
22404274 1306
a4aea562
MB		 1307static void nvme_free_queue(struct nvme_queue *nvmeq)
1308{
9e866774
MW		 1309 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1310 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1311 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1312 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1313 kfree(nvmeq);
1314}
1315
a1a5ef99 1316static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1317{
1318 int i;
1319
a1a5ef99 1320 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1321 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1322 dev->queue_count--;
a4aea562 1323 dev->queues[i] = NULL;
f435c282 1324 nvme_free_queue(nvmeq);
121c7ad4 1325 }
22404274
KB		 1326}
1327
4d115420
KB		 1328/**
1329 * nvme_suspend_queue - put queue into suspended state
1330 * @nvmeq - queue to suspend
4d115420
KB		 1331 */
1332static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1333{
2b25d981 1334 int vector;
b60503ba 1335
a09115b2 1336 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1337 if (nvmeq->cq_vector == -1) {
1338 spin_unlock_irq(&nvmeq->q_lock);
1339 return 1;
1340 }
1341 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1342 nvmeq->dev->online_queues--;
2b25d981 1343 nvmeq->cq_vector = -1;
a09115b2
MW		 1344 spin_unlock_irq(&nvmeq->q_lock);
1345
6df3dbc8
KB		 1346 if (!nvmeq->qid && nvmeq->dev->admin_q)
1347 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1348
aba2080f
MW		 1349 irq_set_affinity_hint(vector, NULL);
1350 free_irq(vector, nvmeq);
b60503ba 1351
4d115420
KB		 1352 return 0;
1353}
b60503ba 1354
4d115420
KB		 1355static void nvme_clear_queue(struct nvme_queue *nvmeq)
1356{
a4aea562
MB		 1357 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1358
22404274 1359 spin_lock_irq(&nvmeq->q_lock);
a4aea562
MB		 1360 if (hctx && hctx->tags)
1361 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
22404274 1362 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1363}
1364
4d115420
KB		 1365static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1366{
a4aea562 1367 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1368
1369 if (!nvmeq)
1370 return;
1371 if (nvme_suspend_queue(nvmeq))
1372 return;
1373
0e53d180
KB		 1374 /* Don't tell the adapter to delete the admin queue.
1375 * Don't tell a removed adapter to delete IO queues. */
1376 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1377 adapter_delete_sq(dev, qid);
1378 adapter_delete_cq(dev, qid);
1379 }
07836e65
KB		 1380
1381 spin_lock_irq(&nvmeq->q_lock);
1382 nvme_process_cq(nvmeq);
1383 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1384}
1385
1386static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1387 int depth)
b60503ba
MW		 1388{
1389 struct device *dmadev = &dev->pci_dev->dev;
a4aea562 1390 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1391 if (!nvmeq)
1392 return NULL;
1393
4d51abf9
JP		 1394 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1395 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1396 if (!nvmeq->cqes)
1397 goto free_nvmeq;
b60503ba
MW		 1398
1399 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1400 &nvmeq->sq_dma_addr, GFP_KERNEL);
1401 if (!nvmeq->sq_cmds)
1402 goto free_cqdma;
1403
1404 nvmeq->q_dmadev = dmadev;
091b6092 1405 nvmeq->dev = dev;
3193f07b
MW		 1406 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1407 dev->instance, qid);
b60503ba
MW		 1408 spin_lock_init(&nvmeq->q_lock);
1409 nvmeq->cq_head = 0;
82123460 1410 nvmeq->cq_phase = 1;
b80d5ccc 1411 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1412 nvmeq->q_depth = depth;
c30341dc 1413 nvmeq->qid = qid;
22404274 1414 dev->queue_count++;
a4aea562 1415 dev->queues[qid] = nvmeq;
b60503ba
MW		 1416
1417 return nvmeq;
1418
1419 free_cqdma:
68b8eca5 1420 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1421 nvmeq->cq_dma_addr);
1422 free_nvmeq:
1423 kfree(nvmeq);
1424 return NULL;
1425}
1426
3001082c
MW		 1427static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1428 const char *name)
1429{
58ffacb5
MW		 1430 if (use_threaded_interrupts)
1431 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1432 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1433 name, nvmeq);
3001082c 1434 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1435 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1436}
1437
22404274 1438static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1439{
22404274 1440 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1441
7be50e93 1442 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1443 nvmeq->sq_tail = 0;
1444 nvmeq->cq_head = 0;
1445 nvmeq->cq_phase = 1;
b80d5ccc 1446 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1447 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1448 dev->online_queues++;
7be50e93 1449 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1450}
1451
1452static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1453{
1454 struct nvme_dev *dev = nvmeq->dev;
1455 int result;
3f85d50b 1456
2b25d981 1457 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1458 result = adapter_alloc_cq(dev, qid, nvmeq);
1459 if (result < 0)
22404274 1460 return result;
b60503ba
MW		 1461
1462 result = adapter_alloc_sq(dev, qid, nvmeq);
1463 if (result < 0)
1464 goto release_cq;
1465
3193f07b 1466 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1467 if (result < 0)
1468 goto release_sq;
1469
22404274 1470 nvme_init_queue(nvmeq, qid);
22404274 1471 return result;
b60503ba
MW		 1472
1473 release_sq:
1474 adapter_delete_sq(dev, qid);
1475 release_cq:
1476 adapter_delete_cq(dev, qid);
22404274 1477 return result;
b60503ba
MW		 1478}
1479
ba47e386
MW		 1480static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1481{
1482 unsigned long timeout;
1483 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1484
1485 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1486
1487 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1488 msleep(100);
1489 if (fatal_signal_pending(current))
1490 return -EINTR;
1491 if (time_after(jiffies, timeout)) {
1492 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1493 "Device not ready; aborting %s\n", enabled ?
1494 "initialisation" : "reset");
ba47e386
MW		 1495 return -ENODEV;
1496 }
1497 }
1498
1499 return 0;
1500}
1501
1502/*
1503 * If the device has been passed off to us in an enabled state, just clear
1504 * the enabled bit. The spec says we should set the 'shutdown notification
1505 * bits', but doing so may cause the device to complete commands to the
1506 * admin queue ... and we don't know what memory that might be pointing at!
1507 */
1508static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1509{
01079522
DM		 1510 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1511 dev->ctrl_config &= ~NVME_CC_ENABLE;
1512 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1513
ba47e386
MW		 1514 return nvme_wait_ready(dev, cap, false);
1515}
1516
1517static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1518{
01079522
DM		 1519 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1520 dev->ctrl_config |= NVME_CC_ENABLE;
1521 writel(dev->ctrl_config, &dev->bar->cc);
1522
ba47e386
MW		 1523 return nvme_wait_ready(dev, cap, true);
1524}
1525
1894d8f1
KB		 1526static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1527{
1528 unsigned long timeout;
1894d8f1 1529
01079522
DM		 1530 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1531 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1532
1533 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1534
2484f407 1535 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1536 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1537 NVME_CSTS_SHST_CMPLT) {
1538 msleep(100);
1539 if (fatal_signal_pending(current))
1540 return -EINTR;
1541 if (time_after(jiffies, timeout)) {
1542 dev_err(&dev->pci_dev->dev,
1543 "Device shutdown incomplete; abort shutdown\n");
1544 return -ENODEV;
1545 }
1546 }
1547
1548 return 0;
1549}
1550
a4aea562
MB		 1551static struct blk_mq_ops nvme_mq_admin_ops = {
1552 .queue_rq = nvme_admin_queue_rq,
1553 .map_queue = blk_mq_map_queue,
1554 .init_hctx = nvme_admin_init_hctx,
2c30540b 1555 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1556 .init_request = nvme_admin_init_request,
1557 .timeout = nvme_timeout,
1558};
1559
1560static struct blk_mq_ops nvme_mq_ops = {
1561 .queue_rq = nvme_queue_rq,
1562 .map_queue = blk_mq_map_queue,
1563 .init_hctx = nvme_init_hctx,
2c30540b 1564 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1565 .init_request = nvme_init_request,
1566 .timeout = nvme_timeout,
1567};
1568
ea191d2f
KB		 1569static void nvme_dev_remove_admin(struct nvme_dev *dev)
1570{
1571 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1572 blk_cleanup_queue(dev->admin_q);
1573 blk_mq_free_tag_set(&dev->admin_tagset);
1574 }
1575}
1576
a4aea562
MB		 1577static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1578{
1579 if (!dev->admin_q) {
1580 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1581 dev->admin_tagset.nr_hw_queues = 1;
1582 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1efccc9d 1583 dev->admin_tagset.reserved_tags = 1;
a4aea562
MB		 1584 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1585 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
ac3dd5bd 1586 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1587 dev->admin_tagset.driver_data = dev;
1588
1589 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1590 return -ENOMEM;
1591
1592 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1593 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1594 blk_mq_free_tag_set(&dev->admin_tagset);
1595 return -ENOMEM;
1596 }
ea191d2f
KB		 1597 if (!blk_get_queue(dev->admin_q)) {
1598 nvme_dev_remove_admin(dev);
1599 return -ENODEV;
1600 }
0fb59cbc
KB		 1601 } else
1602 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1603
1604 return 0;
1605}
1606
8d85fce7 1607static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1608{
ba47e386 1609 int result;
b60503ba 1610 u32 aqa;
ba47e386 1611 u64 cap = readq(&dev->bar->cap);
b60503ba 1612 struct nvme_queue *nvmeq;
1d090624
KB		 1613 unsigned page_shift = PAGE_SHIFT;
1614 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1615 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1616
1617 if (page_shift < dev_page_min) {
1618 dev_err(&dev->pci_dev->dev,
1619 "Minimum device page size (%u) too large for "
1620 "host (%u)\n", 1 << dev_page_min,
1621 1 << page_shift);
1622 return -ENODEV;
1623 }
1624 if (page_shift > dev_page_max) {
1625 dev_info(&dev->pci_dev->dev,
1626 "Device maximum page size (%u) smaller than "
1627 "host (%u); enabling work-around\n",
1628 1 << dev_page_max, 1 << page_shift);
1629 page_shift = dev_page_max;
1630 }
b60503ba 1631
ba47e386
MW		 1632 result = nvme_disable_ctrl(dev, cap);
1633 if (result < 0)
1634 return result;
b60503ba 1635
a4aea562 1636 nvmeq = dev->queues[0];
cd638946 1637 if (!nvmeq) {
2b25d981 1638 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1639 if (!nvmeq)
1640 return -ENOMEM;
cd638946 1641 }
b60503ba
MW		 1642
1643 aqa = nvmeq->q_depth - 1;
1644 aqa |= aqa << 16;
1645
1d090624
KB		 1646 dev->page_size = 1 << page_shift;
1647
01079522 1648 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1649 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1650 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1651 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1652
1653 writel(aqa, &dev->bar->aqa);
1654 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1655 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1656
ba47e386 1657 result = nvme_enable_ctrl(dev, cap);
025c557a 1658 if (result)
a4aea562
MB		 1659 goto free_nvmeq;
1660
2b25d981 1661 nvmeq->cq_vector = 0;
3193f07b 1662 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1663 if (result)
0fb59cbc 1664 goto free_nvmeq;
025c557a 1665
b60503ba 1666 return result;
a4aea562 1667
a4aea562
MB		 1668 free_nvmeq:
1669 nvme_free_queues(dev, 0);
1670 return result;
b60503ba
MW		 1671}
1672
5d0f6131 1673struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1674 unsigned long addr, unsigned length)
b60503ba 1675{
36c14ed9 1676 int i, err, count, nents, offset;
7fc3cdab
MW		 1677 struct scatterlist *sg;
1678 struct page **pages;
eca18b23 1679 struct nvme_iod *iod;
36c14ed9
MW		 1680
1681 if (addr & 3)
eca18b23 1682 return ERR_PTR(-EINVAL);
5460fc03 1683 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1684 return ERR_PTR(-EINVAL);
7fc3cdab 1685
36c14ed9 1686 offset = offset_in_page(addr);
7fc3cdab
MW		 1687 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1688 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1689 if (!pages)
1690 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1691
1692 err = get_user_pages_fast(addr, count, 1, pages);
1693 if (err < count) {
1694 count = err;
1695 err = -EFAULT;
1696 goto put_pages;
1697 }
7fc3cdab 1698
6808c5fb 1699 err = -ENOMEM;
ac3dd5bd 1700 iod = __nvme_alloc_iod(count, length, dev, 0, GFP_KERNEL);
6808c5fb
S		 1701 if (!iod)
1702 goto put_pages;
1703
eca18b23 1704 sg = iod->sg;
36c14ed9 1705 sg_init_table(sg, count);
d0ba1e49
MW		 1706 for (i = 0; i < count; i++) {
1707 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1708 min_t(unsigned, length, PAGE_SIZE - offset),
1709 offset);
d0ba1e49
MW		 1710 length -= (PAGE_SIZE - offset);
1711 offset = 0;
7fc3cdab 1712 }
fe304c43 1713 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1714 iod->nents = count;
7fc3cdab 1715
7fc3cdab
MW		 1716 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1717 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1718 if (!nents)
eca18b23 1719 goto free_iod;
b60503ba 1720
7fc3cdab 1721 kfree(pages);
eca18b23 1722 return iod;
b60503ba 1723
eca18b23
MW		 1724 free_iod:
1725 kfree(iod);
7fc3cdab
MW		 1726 put_pages:
1727 for (i = 0; i < count; i++)
1728 put_page(pages[i]);
1729 kfree(pages);
eca18b23 1730 return ERR_PTR(err);
7fc3cdab 1731}
b60503ba 1732
5d0f6131 1733void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1734 struct nvme_iod *iod)
7fc3cdab 1735{
1c2ad9fa 1736 int i;
b60503ba 1737
1c2ad9fa
MW		 1738 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1739 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1740
1c2ad9fa
MW		 1741 for (i = 0; i < iod->nents; i++)
1742 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1743}
b60503ba 1744
a53295b6
MW		 1745static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1746{
1747 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1748 struct nvme_user_io io;
1749 struct nvme_command c;
f410c680
KB		 1750 unsigned length, meta_len;
1751 int status, i;
1752 struct nvme_iod *iod, *meta_iod = NULL;
1753 dma_addr_t meta_dma_addr;
1754 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1755
1756 if (copy_from_user(&io, uio, sizeof(io)))
1757 return -EFAULT;
6c7d4945 1758 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1759 meta_len = (io.nblocks + 1) * ns->ms;
1760
1761 if (meta_len && ((io.metadata & 3) || !io.metadata))
1762 return -EINVAL;
6c7d4945
MW		 1763
1764 switch (io.opcode) {
1765 case nvme_cmd_write:
1766 case nvme_cmd_read:
6bbf1acd 1767 case nvme_cmd_compare:
eca18b23 1768 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1769 break;
6c7d4945 1770 default:
6bbf1acd 1771 return -EINVAL;
6c7d4945
MW		 1772 }
1773
eca18b23
MW		 1774 if (IS_ERR(iod))
1775 return PTR_ERR(iod);
a53295b6
MW		 1776
1777 memset(&c, 0, sizeof(c));
1778 c.rw.opcode = io.opcode;
1779 c.rw.flags = io.flags;
6c7d4945 1780 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1781 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1782 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1783 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1784 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1785 c.rw.reftag = cpu_to_le32(io.reftag);
1786 c.rw.apptag = cpu_to_le16(io.apptag);
1787 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1788
1789 if (meta_len) {
1b56749e
KB		 1790 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1791 meta_len);
f410c680
KB		 1792 if (IS_ERR(meta_iod)) {
1793 status = PTR_ERR(meta_iod);
1794 meta_iod = NULL;
1795 goto unmap;
1796 }
1797
1798 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1799 &meta_dma_addr, GFP_KERNEL);
1800 if (!meta_mem) {
1801 status = -ENOMEM;
1802 goto unmap;
1803 }
1804
1805 if (io.opcode & 1) {
1806 int meta_offset = 0;
1807
1808 for (i = 0; i < meta_iod->nents; i++) {
1809 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1810 meta_iod->sg[i].offset;
1811 memcpy(meta_mem + meta_offset, meta,
1812 meta_iod->sg[i].length);
1813 kunmap_atomic(meta);
1814 meta_offset += meta_iod->sg[i].length;
1815 }
1816 }
1817
1818 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1819 }
1820
edd10d33
KB		 1821 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1822 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1823 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1824
b77954cb
MW		 1825 if (length != (io.nblocks + 1) << ns->lba_shift)
1826 status = -ENOMEM;
1827 else
a4aea562 1828 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
a53295b6 1829
f410c680
KB		 1830 if (meta_len) {
1831 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1832 int meta_offset = 0;
1833
1834 for (i = 0; i < meta_iod->nents; i++) {
1835 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1836 meta_iod->sg[i].offset;
1837 memcpy(meta, meta_mem + meta_offset,
1838 meta_iod->sg[i].length);
1839 kunmap_atomic(meta);
1840 meta_offset += meta_iod->sg[i].length;
1841 }
1842 }
1843
1844 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1845 meta_dma_addr);
1846 }
1847
1848 unmap:
1c2ad9fa 1849 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1850 nvme_free_iod(dev, iod);
f410c680
KB		 1851
1852 if (meta_iod) {
1853 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1854 nvme_free_iod(dev, meta_iod);
1855 }
1856
a53295b6
MW		 1857 return status;
1858}
1859
a4aea562
MB		 1860static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1861 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1862{
7963e521 1863 struct nvme_passthru_cmd cmd;
6ee44cdc 1864 struct nvme_command c;
eca18b23 1865 int status, length;
c7d36ab8 1866 struct nvme_iod *uninitialized_var(iod);
94f370ca 1867 unsigned timeout;
6ee44cdc 1868
6bbf1acd
MW		 1869 if (!capable(CAP_SYS_ADMIN))
1870 return -EACCES;
1871 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1872 return -EFAULT;
6ee44cdc
MW		 1873
1874 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1875 c.common.opcode = cmd.opcode;
1876 c.common.flags = cmd.flags;
1877 c.common.nsid = cpu_to_le32(cmd.nsid);
1878 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1879 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1880 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1881 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1882 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1883 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1884 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1885 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1886
1887 length = cmd.data_len;
1888 if (cmd.data_len) {
49742188
MW		 1889 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1890 length);
eca18b23
MW		 1891 if (IS_ERR(iod))
1892 return PTR_ERR(iod);
edd10d33
KB		 1893 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1894 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1895 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1896 }
1897
94f370ca
KB		 1898 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1899 ADMIN_TIMEOUT;
a4aea562 1900
6bbf1acd 1901 if (length != cmd.data_len)
b77954cb 1902 status = -ENOMEM;
a4aea562
MB		 1903 else if (ns) {
1904 struct request *req;
1905
1906 req = blk_mq_alloc_request(ns->queue, WRITE,
1907 (GFP_KERNEL|__GFP_WAIT), false);
97fe3832
JA		 1908 if (IS_ERR(req))
1909 status = PTR_ERR(req);
a4aea562
MB		 1910 else {
1911 status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1912 timeout);
9d135bb8 1913 blk_mq_free_request(req);
a4aea562
MB		 1914 }
1915 } else
1916 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
eca18b23 1917
6bbf1acd 1918 if (cmd.data_len) {
1c2ad9fa 1919 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1920 nvme_free_iod(dev, iod);
6bbf1acd 1921 }
f4f117f6 1922
cf90bc48 1923 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1924 sizeof(cmd.result)))
1925 status = -EFAULT;
1926
6ee44cdc
MW		 1927 return status;
1928}
1929
b60503ba
MW		 1930static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1931 unsigned long arg)
1932{
1933 struct nvme_ns *ns = bdev->bd_disk->private_data;
1934
1935 switch (cmd) {
6bbf1acd 1936 case NVME_IOCTL_ID:
c3bfe717 1937 force_successful_syscall_return();
6bbf1acd
MW		 1938 return ns->ns_id;
1939 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1940 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1941 case NVME_IOCTL_IO_CMD:
a4aea562 1942 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1943 case NVME_IOCTL_SUBMIT_IO:
1944 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1945 case SG_GET_VERSION_NUM:
1946 return nvme_sg_get_version_num((void __user *)arg);
1947 case SG_IO:
1948 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1949 default:
1950 return -ENOTTY;
1951 }
1952}
1953
320a3827
KB		 1954#ifdef CONFIG_COMPAT
1955static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1956 unsigned int cmd, unsigned long arg)
1957{
320a3827
KB		 1958 switch (cmd) {
1959 case SG_IO:
e179729a 1960 return -ENOIOCTLCMD;
320a3827
KB		 1961 }
1962 return nvme_ioctl(bdev, mode, cmd, arg);
1963}
1964#else
1965#define nvme_compat_ioctl NULL
1966#endif
1967
9ac27090
KB		 1968static int nvme_open(struct block_device *bdev, fmode_t mode)
1969{
9e60352c
KB		 1970 int ret = 0;
1971 struct nvme_ns *ns;
9ac27090 1972
9e60352c
KB		 1973 spin_lock(&dev_list_lock);
1974 ns = bdev->bd_disk->private_data;
1975 if (!ns)
1976 ret = -ENXIO;
1977 else if (!kref_get_unless_zero(&ns->dev->kref))
1978 ret = -ENXIO;
1979 spin_unlock(&dev_list_lock);
1980
1981 return ret;
9ac27090
KB		 1982}
1983
1984static void nvme_free_dev(struct kref *kref);
1985
1986static void nvme_release(struct gendisk *disk, fmode_t mode)
1987{
1988 struct nvme_ns *ns = disk->private_data;
1989 struct nvme_dev *dev = ns->dev;
1990
1991 kref_put(&dev->kref, nvme_free_dev);
1992}
1993
4cc09e2d
KB		 1994static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1995{
1996 /* some standard values */
1997 geo->heads = 1 << 6;
1998 geo->sectors = 1 << 5;
1999 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
2000 return 0;
2001}
2002
e1e5e564
KB		 2003static void nvme_config_discard(struct nvme_ns *ns)
2004{
2005 u32 logical_block_size = queue_logical_block_size(ns->queue);
2006 ns->queue->limits.discard_zeroes_data = 0;
2007 ns->queue->limits.discard_alignment = logical_block_size;
2008 ns->queue->limits.discard_granularity = logical_block_size;
2009 ns->queue->limits.max_discard_sectors = 0xffffffff;
2010 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
2011}
2012
1b9dbf7f
KB		 2013static int nvme_revalidate_disk(struct gendisk *disk)
2014{
2015 struct nvme_ns *ns = disk->private_data;
2016 struct nvme_dev *dev = ns->dev;
2017 struct nvme_id_ns *id;
2018 dma_addr_t dma_addr;
e1e5e564
KB		 2019 int lbaf, pi_type, old_ms;
2020 unsigned short bs;
1b9dbf7f
KB		 2021
2022 id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
2023 GFP_KERNEL);
2024 if (!id) {
2025 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
2026 __func__);
2027 return 0;
2028 }
e1e5e564
KB		 2029 if (nvme_identify(dev, ns->ns_id, 0, dma_addr)) {
2030 dev_warn(&dev->pci_dev->dev,
2031 "identify failed ns:%d, setting capacity to 0\n",
2032 ns->ns_id);
2033 memset(id, 0, sizeof(*id));
2034 }
1b9dbf7f 2035
e1e5e564
KB		 2036 old_ms = ns->ms;
2037 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1b9dbf7f 2038 ns->lba_shift = id->lbaf[lbaf].ds;
e1e5e564
KB		 2039 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
2040
2041 /*
2042 * If identify namespace failed, use default 512 byte block size so
2043 * block layer can use before failing read/write for 0 capacity.
2044 */
2045 if (ns->lba_shift == 0)
2046 ns->lba_shift = 9;
2047 bs = 1 << ns->lba_shift;
2048
2049 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2050 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2051 id->dps & NVME_NS_DPS_PI_MASK : 0;
2052
52b68d7e
KB		 2053 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2054 ns->ms != old_ms ||
e1e5e564
KB		 2055 bs != queue_logical_block_size(disk->queue) ||
2056 (ns->ms && id->flbas & NVME_NS_FLBAS_META_EXT)))
2057 blk_integrity_unregister(disk);
2058
2059 ns->pi_type = pi_type;
2060 blk_queue_logical_block_size(ns->queue, bs);
2061
52b68d7e 2062 if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
e1e5e564
KB		 2063 !(id->flbas & NVME_NS_FLBAS_META_EXT))
2064 nvme_init_integrity(ns);
2065
52b68d7e 2066 if (id->ncap == 0 || (ns->ms && !blk_get_integrity(disk)))
e1e5e564
KB		 2067 set_capacity(disk, 0);
2068 else
2069 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2070
2071 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2072 nvme_config_discard(ns);
1b9dbf7f 2073
1b9dbf7f
KB		 2074 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
2075 return 0;
2076}
2077
b60503ba
MW		 2078static const struct block_device_operations nvme_fops = {
2079 .owner = THIS_MODULE,
2080 .ioctl = nvme_ioctl,
320a3827 2081 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 2082 .open = nvme_open,
2083 .release = nvme_release,
4cc09e2d 2084 .getgeo = nvme_getgeo,
1b9dbf7f 2085 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 2086};
2087
1fa6aead
MW		 2088static int nvme_kthread(void *data)
2089{
d4b4ff8e 2090 struct nvme_dev *dev, *next;
1fa6aead
MW		 2091
2092 while (!kthread_should_stop()) {
564a232c 2093 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 2094 spin_lock(&dev_list_lock);
d4b4ff8e 2095 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 2096 int i;
07836e65 2097 if (readl(&dev->bar->csts) & NVME_CSTS_CFS) {
d4b4ff8e
KB		 2098 if (work_busy(&dev->reset_work))
2099 continue;
2100 list_del_init(&dev->node);
2101 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 2102 "Failed status: %x, reset controller\n",
2103 readl(&dev->bar->csts));
9ca97374 2104 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 2105 queue_work(nvme_workq, &dev->reset_work);
2106 continue;
2107 }
1fa6aead 2108 for (i = 0; i < dev->queue_count; i++) {
a4aea562 2109 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 2110 if (!nvmeq)
2111 continue;
1fa6aead 2112 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 2113 nvme_process_cq(nvmeq);
6fccf938
KB		 2114
2115 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 2116 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 2117 break;
2118 dev->event_limit--;
2119 }
1fa6aead
MW		 2120 spin_unlock_irq(&nvmeq->q_lock);
2121 }
2122 }
2123 spin_unlock(&dev_list_lock);
acb7aa0d 2124 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 2125 }
2126 return 0;
2127}
2128
e1e5e564 2129static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
b60503ba
MW		 2130{
2131 struct nvme_ns *ns;
2132 struct gendisk *disk;
a4aea562 2133 int node = dev_to_node(&dev->pci_dev->dev);
b60503ba 2134
a4aea562 2135 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba 2136 if (!ns)
e1e5e564
KB		 2137 return;
2138
a4aea562 2139 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 2140 if (IS_ERR(ns->queue))
b60503ba 2141 goto out_free_ns;
4eeb9215
MW		 2142 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2143 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 2144 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 2145 ns->dev = dev;
2146 ns->queue->queuedata = ns;
2147
a4aea562 2148 disk = alloc_disk_node(0, node);
b60503ba
MW		 2149 if (!disk)
2150 goto out_free_queue;
a4aea562 2151
5aff9382 2152 ns->ns_id = nsid;
b60503ba 2153 ns->disk = disk;
e1e5e564
KB		 2154 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2155 list_add_tail(&ns->list, &dev->namespaces);
2156
e9ef4636 2157 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 2158 if (dev->max_hw_sectors)
2159 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 2160 if (dev->stripe_size)
2161 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2162 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2163 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 2164
2165 disk->major = nvme_major;
469071a3 2166 disk->first_minor = 0;
b60503ba
MW		 2167 disk->fops = &nvme_fops;
2168 disk->private_data = ns;
2169 disk->queue = ns->queue;
b3fffdef 2170 disk->driverfs_dev = dev->device;
469071a3 2171 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2172 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba 2173
e1e5e564
KB		 2174 /*
2175 * Initialize capacity to 0 until we establish the namespace format and
2176 * setup integrity extentions if necessary. The revalidate_disk after
2177 * add_disk allows the driver to register with integrity if the format
2178 * requires it.
2179 */
2180 set_capacity(disk, 0);
2181 nvme_revalidate_disk(ns->disk);
2182 add_disk(ns->disk);
2183 if (ns->ms)
2184 revalidate_disk(ns->disk);
2185 return;
b60503ba
MW		 2186 out_free_queue:
2187 blk_cleanup_queue(ns->queue);
2188 out_free_ns:
2189 kfree(ns);
b60503ba
MW		 2190}
2191
42f61420
KB		 2192static void nvme_create_io_queues(struct nvme_dev *dev)
2193{
a4aea562 2194 unsigned i;
42f61420 2195
a4aea562 2196 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2197 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2198 break;
2199
a4aea562
MB		 2200 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2201 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 2202 break;
2203}
2204
b3b06812 2205static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2206{
2207 int status;
2208 u32 result;
b3b06812 2209 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2210
df348139 2211 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2212 &result);
27e8166c
MW		 2213 if (status < 0)
2214 return status;
2215 if (status > 0) {
2216 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2217 status);
badc34d4 2218 return 0;
27e8166c 2219 }
b60503ba
MW		 2220 return min(result & 0xffff, result >> 16) + 1;
2221}
2222
9d713c2b
KB		 2223static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2224{
b80d5ccc 2225 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2226}
2227
8d85fce7 2228static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2229{
a4aea562 2230 struct nvme_queue *adminq = dev->queues[0];
fa08a396 2231 struct pci_dev *pdev = dev->pci_dev;
42f61420 2232 int result, i, vecs, nr_io_queues, size;
b60503ba 2233
42f61420 2234 nr_io_queues = num_possible_cpus();
b348b7d5 2235 result = set_queue_count(dev, nr_io_queues);
badc34d4 2236 if (result <= 0)
1b23484b 2237 return result;
b348b7d5
MW		 2238 if (result < nr_io_queues)
2239 nr_io_queues = result;
b60503ba 2240
9d713c2b
KB		 2241 size = db_bar_size(dev, nr_io_queues);
2242 if (size > 8192) {
f1938f6e 2243 iounmap(dev->bar);
9d713c2b
KB		 2244 do {
2245 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2246 if (dev->bar)
2247 break;
2248 if (!--nr_io_queues)
2249 return -ENOMEM;
2250 size = db_bar_size(dev, nr_io_queues);
2251 } while (1);
f1938f6e 2252 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2253 adminq->q_db = dev->dbs;
f1938f6e
MW		 2254 }
2255
9d713c2b 2256 /* Deregister the admin queue's interrupt */
3193f07b 2257 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2258
e32efbfc
JA		 2259 /*
2260 * If we enable msix early due to not intx, disable it again before
2261 * setting up the full range we need.
2262 */
2263 if (!pdev->irq)
2264 pci_disable_msix(pdev);
2265
be577fab 2266 for (i = 0; i < nr_io_queues; i++)
1b23484b 2267 dev->entry[i].entry = i;
be577fab
AG		 2268 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2269 if (vecs < 0) {
2270 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2271 if (vecs < 0) {
2272 vecs = 1;
2273 } else {
2274 for (i = 0; i < vecs; i++)
2275 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2276 }
2277 }
2278
063a8096
MW		 2279 /*
2280 * Should investigate if there's a performance win from allocating
2281 * more queues than interrupt vectors; it might allow the submission
2282 * path to scale better, even if the receive path is limited by the
2283 * number of interrupts.
2284 */
2285 nr_io_queues = vecs;
42f61420 2286 dev->max_qid = nr_io_queues;
063a8096 2287
3193f07b 2288 result = queue_request_irq(dev, adminq, adminq->irqname);
a4aea562 2289 if (result)
22404274 2290 goto free_queues;
1b23484b 2291
cd638946 2292 /* Free previously allocated queues that are no longer usable */
42f61420 2293 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2294 nvme_create_io_queues(dev);
9ecdc946 2295
22404274 2296 return 0;
b60503ba 2297
22404274 2298 free_queues:
a1a5ef99 2299 nvme_free_queues(dev, 1);
22404274 2300 return result;
b60503ba
MW		 2301}
2302
422ef0c7
MW		 2303/*
2304 * Return: error value if an error occurred setting up the queues or calling
2305 * Identify Device. 0 if these succeeded, even if adding some of the
2306 * namespaces failed. At the moment, these failures are silent. TBD which
2307 * failures should be reported.
2308 */
8d85fce7 2309static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2310{
68608c26 2311 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2312 int res;
2313 unsigned nn, i;
51814232 2314 struct nvme_id_ctrl *ctrl;
bc5fc7e4 2315 void *mem;
b60503ba 2316 dma_addr_t dma_addr;
159b67d7 2317 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2318
e1e5e564 2319 mem = dma_alloc_coherent(&pdev->dev, 4096, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2320 if (!mem)
2321 return -ENOMEM;
b60503ba 2322
bc5fc7e4 2323 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2324 if (res) {
27e8166c 2325 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
e1e5e564
KB		 2326 dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr);
2327 return -EIO;
b60503ba
MW		 2328 }
2329
bc5fc7e4 2330 ctrl = mem;
51814232 2331 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2332 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2333 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2334 dev->vwc = ctrl->vwc;
51814232
MW		 2335 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2336 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2337 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2338 if (ctrl->mdts)
8fc23e03 2339 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2340 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2341 (pdev->device == 0x0953) && ctrl->vs[3]) {
2342 unsigned int max_hw_sectors;
2343
159b67d7 2344 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2345 max_hw_sectors = dev->stripe_size >> (shift - 9);
2346 if (dev->max_hw_sectors) {
2347 dev->max_hw_sectors = min(max_hw_sectors,
2348 dev->max_hw_sectors);
2349 } else
2350 dev->max_hw_sectors = max_hw_sectors;
2351 }
e1e5e564 2352 dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr);
a4aea562
MB		 2353
2354 dev->tagset.ops = &nvme_mq_ops;
2355 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2356 dev->tagset.timeout = NVME_IO_TIMEOUT;
2357 dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2358 dev->tagset.queue_depth =
2359 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ac3dd5bd 2360 dev->tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 2361 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2362 dev->tagset.driver_data = dev;
2363
2364 if (blk_mq_alloc_tag_set(&dev->tagset))
e1e5e564 2365 return 0;
b60503ba 2366
e1e5e564
KB		 2367 for (i = 1; i <= nn; i++)
2368 nvme_alloc_ns(dev, i);
b60503ba 2369
e1e5e564 2370 return 0;
b60503ba
MW		 2371}
2372
0877cb0d
KB		 2373static int nvme_dev_map(struct nvme_dev *dev)
2374{
42f61420 2375 u64 cap;
0877cb0d
KB		 2376 int bars, result = -ENOMEM;
2377 struct pci_dev *pdev = dev->pci_dev;
2378
2379 if (pci_enable_device_mem(pdev))
2380 return result;
2381
2382 dev->entry[0].vector = pdev->irq;
2383 pci_set_master(pdev);
2384 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2385 if (!bars)
2386 goto disable_pci;
2387
0877cb0d
KB		 2388 if (pci_request_selected_regions(pdev, bars, "nvme"))
2389 goto disable_pci;
2390
052d0efa
RK		 2391 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2392 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2393 goto disable;
0877cb0d 2394
0877cb0d
KB		 2395 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2396 if (!dev->bar)
2397 goto disable;
e32efbfc 2398
0e53d180
KB		 2399 if (readl(&dev->bar->csts) == -1) {
2400 result = -ENODEV;
2401 goto unmap;
2402 }
e32efbfc
JA		 2403
2404 /*
2405 * Some devices don't advertse INTx interrupts, pre-enable a single
2406 * MSIX vec for setup. We'll adjust this later.
2407 */
2408 if (!pdev->irq) {
2409 result = pci_enable_msix(pdev, dev->entry, 1);
2410 if (result < 0)
2411 goto unmap;
2412 }
2413
42f61420
KB		 2414 cap = readq(&dev->bar->cap);
2415 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2416 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2417 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2418
2419 return 0;
2420
0e53d180
KB		 2421 unmap:
2422 iounmap(dev->bar);
2423 dev->bar = NULL;
0877cb0d
KB		 2424 disable:
2425 pci_release_regions(pdev);
2426 disable_pci:
2427 pci_disable_device(pdev);
2428 return result;
2429}
2430
2431static void nvme_dev_unmap(struct nvme_dev *dev)
2432{
2433 if (dev->pci_dev->msi_enabled)
2434 pci_disable_msi(dev->pci_dev);
2435 else if (dev->pci_dev->msix_enabled)
2436 pci_disable_msix(dev->pci_dev);
2437
2438 if (dev->bar) {
2439 iounmap(dev->bar);
2440 dev->bar = NULL;
9a6b9458 2441 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2442 }
2443
0877cb0d
KB		 2444 if (pci_is_enabled(dev->pci_dev))
2445 pci_disable_device(dev->pci_dev);
2446}
2447
4d115420
KB		 2448struct nvme_delq_ctx {
2449 struct task_struct *waiter;
2450 struct kthread_worker *worker;
2451 atomic_t refcount;
2452};
2453
2454static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2455{
2456 dq->waiter = current;
2457 mb();
2458
2459 for (;;) {
2460 set_current_state(TASK_KILLABLE);
2461 if (!atomic_read(&dq->refcount))
2462 break;
2463 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2464 fatal_signal_pending(current)) {
0fb59cbc
KB		 2465 /*
2466 * Disable the controller first since we can't trust it
2467 * at this point, but leave the admin queue enabled
2468 * until all queue deletion requests are flushed.
2469 * FIXME: This may take a while if there are more h/w
2470 * queues than admin tags.
2471 */
4d115420 2472 set_current_state(TASK_RUNNING);
4d115420 2473 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2474 nvme_clear_queue(dev->queues[0]);
4d115420 2475 flush_kthread_worker(dq->worker);
0fb59cbc 2476 nvme_disable_queue(dev, 0);
4d115420
KB		 2477 return;
2478 }
2479 }
2480 set_current_state(TASK_RUNNING);
2481}
2482
2483static void nvme_put_dq(struct nvme_delq_ctx *dq)
2484{
2485 atomic_dec(&dq->refcount);
2486 if (dq->waiter)
2487 wake_up_process(dq->waiter);
2488}
2489
2490static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2491{
2492 atomic_inc(&dq->refcount);
2493 return dq;
2494}
2495
2496static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2497{
2498 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
4d115420
KB		 2499 nvme_put_dq(dq);
2500}
2501
2502static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2503 kthread_work_func_t fn)
2504{
2505 struct nvme_command c;
2506
2507 memset(&c, 0, sizeof(c));
2508 c.delete_queue.opcode = opcode;
2509 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2510
2511 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2512 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2513 ADMIN_TIMEOUT);
4d115420
KB		 2514}
2515
2516static void nvme_del_cq_work_handler(struct kthread_work *work)
2517{
2518 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2519 cmdinfo.work);
2520 nvme_del_queue_end(nvmeq);
2521}
2522
2523static int nvme_delete_cq(struct nvme_queue *nvmeq)
2524{
2525 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2526 nvme_del_cq_work_handler);
2527}
2528
2529static void nvme_del_sq_work_handler(struct kthread_work *work)
2530{
2531 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2532 cmdinfo.work);
2533 int status = nvmeq->cmdinfo.status;
2534
2535 if (!status)
2536 status = nvme_delete_cq(nvmeq);
2537 if (status)
2538 nvme_del_queue_end(nvmeq);
2539}
2540
2541static int nvme_delete_sq(struct nvme_queue *nvmeq)
2542{
2543 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2544 nvme_del_sq_work_handler);
2545}
2546
2547static void nvme_del_queue_start(struct kthread_work *work)
2548{
2549 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2550 cmdinfo.work);
4d115420
KB		 2551 if (nvme_delete_sq(nvmeq))
2552 nvme_del_queue_end(nvmeq);
2553}
2554
2555static void nvme_disable_io_queues(struct nvme_dev *dev)
2556{
2557 int i;
2558 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2559 struct nvme_delq_ctx dq;
2560 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2561 &worker, "nvme%d", dev->instance);
2562
2563 if (IS_ERR(kworker_task)) {
2564 dev_err(&dev->pci_dev->dev,
2565 "Failed to create queue del task\n");
2566 for (i = dev->queue_count - 1; i > 0; i--)
2567 nvme_disable_queue(dev, i);
2568 return;
2569 }
2570
2571 dq.waiter = NULL;
2572 atomic_set(&dq.refcount, 0);
2573 dq.worker = &worker;
2574 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2575 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2576
2577 if (nvme_suspend_queue(nvmeq))
2578 continue;
2579 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2580 nvmeq->cmdinfo.worker = dq.worker;
2581 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2582 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2583 }
2584 nvme_wait_dq(&dq, dev);
2585 kthread_stop(kworker_task);
2586}
2587
b9afca3e
DM		 2588/*
2589* Remove the node from the device list and check
2590* for whether or not we need to stop the nvme_thread.
2591*/
2592static void nvme_dev_list_remove(struct nvme_dev *dev)
2593{
2594 struct task_struct *tmp = NULL;
2595
2596 spin_lock(&dev_list_lock);
2597 list_del_init(&dev->node);
2598 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2599 tmp = nvme_thread;
2600 nvme_thread = NULL;
2601 }
2602 spin_unlock(&dev_list_lock);
2603
2604 if (tmp)
2605 kthread_stop(tmp);
2606}
2607
c9d3bf88
KB		 2608static void nvme_freeze_queues(struct nvme_dev *dev)
2609{
2610 struct nvme_ns *ns;
2611
2612 list_for_each_entry(ns, &dev->namespaces, list) {
2613 blk_mq_freeze_queue_start(ns->queue);
2614
2615 spin_lock(ns->queue->queue_lock);
2616 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2617 spin_unlock(ns->queue->queue_lock);
2618
2619 blk_mq_cancel_requeue_work(ns->queue);
2620 blk_mq_stop_hw_queues(ns->queue);
2621 }
2622}
2623
2624static void nvme_unfreeze_queues(struct nvme_dev *dev)
2625{
2626 struct nvme_ns *ns;
2627
2628 list_for_each_entry(ns, &dev->namespaces, list) {
2629 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2630 blk_mq_unfreeze_queue(ns->queue);
2631 blk_mq_start_stopped_hw_queues(ns->queue, true);
2632 blk_mq_kick_requeue_list(ns->queue);
2633 }
2634}
2635
f0b50732 2636static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2637{
22404274 2638 int i;
7c1b2450 2639 u32 csts = -1;
22404274 2640
b9afca3e 2641 nvme_dev_list_remove(dev);
1fa6aead 2642
c9d3bf88
KB		 2643 if (dev->bar) {
2644 nvme_freeze_queues(dev);
7c1b2450 2645 csts = readl(&dev->bar->csts);
c9d3bf88 2646 }
7c1b2450 2647 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2648 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2649 struct nvme_queue *nvmeq = dev->queues[i];
4d115420 2650 nvme_suspend_queue(nvmeq);
4d115420
KB		 2651 }
2652 } else {
2653 nvme_disable_io_queues(dev);
1894d8f1 2654 nvme_shutdown_ctrl(dev);
4d115420
KB		 2655 nvme_disable_queue(dev, 0);
2656 }
f0b50732 2657 nvme_dev_unmap(dev);
07836e65
KB		 2658
2659 for (i = dev->queue_count - 1; i >= 0; i--)
2660 nvme_clear_queue(dev->queues[i]);
f0b50732
KB		 2661}
2662
2663static void nvme_dev_remove(struct nvme_dev *dev)
2664{
9ac27090 2665 struct nvme_ns *ns;
f0b50732 2666
9ac27090 2667 list_for_each_entry(ns, &dev->namespaces, list) {
e1e5e564 2668 if (ns->disk->flags & GENHD_FL_UP) {
52b68d7e 2669 if (blk_get_integrity(ns->disk))
e1e5e564 2670 blk_integrity_unregister(ns->disk);
9ac27090 2671 del_gendisk(ns->disk);
e1e5e564 2672 }
cef6a948
KB		 2673 if (!blk_queue_dying(ns->queue)) {
2674 blk_mq_abort_requeue_list(ns->queue);
9ac27090 2675 blk_cleanup_queue(ns->queue);
cef6a948 2676 }
b60503ba 2677 }
b60503ba
MW		 2678}
2679
091b6092
MW		 2680static int nvme_setup_prp_pools(struct nvme_dev *dev)
2681{
2682 struct device *dmadev = &dev->pci_dev->dev;
2683 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2684 PAGE_SIZE, PAGE_SIZE, 0);
2685 if (!dev->prp_page_pool)
2686 return -ENOMEM;
2687
99802a7a
MW		 2688 /* Optimisation for I/Os between 4k and 128k */
2689 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2690 256, 256, 0);
2691 if (!dev->prp_small_pool) {
2692 dma_pool_destroy(dev->prp_page_pool);
2693 return -ENOMEM;
2694 }
091b6092
MW		 2695 return 0;
2696}
2697
2698static void nvme_release_prp_pools(struct nvme_dev *dev)
2699{
2700 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2701 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2702}
2703
cd58ad7d
QSA		 2704static DEFINE_IDA(nvme_instance_ida);
2705
2706static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2707{
cd58ad7d
QSA		 2708 int instance, error;
2709
2710 do {
2711 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2712 return -ENODEV;
2713
2714 spin_lock(&dev_list_lock);
2715 error = ida_get_new(&nvme_instance_ida, &instance);
2716 spin_unlock(&dev_list_lock);
2717 } while (error == -EAGAIN);
2718
2719 if (error)
2720 return -ENODEV;
2721
2722 dev->instance = instance;
2723 return 0;
b60503ba
MW		 2724}
2725
2726static void nvme_release_instance(struct nvme_dev *dev)
2727{
cd58ad7d
QSA		 2728 spin_lock(&dev_list_lock);
2729 ida_remove(&nvme_instance_ida, dev->instance);
2730 spin_unlock(&dev_list_lock);
b60503ba
MW		 2731}
2732
9ac27090
KB		 2733static void nvme_free_namespaces(struct nvme_dev *dev)
2734{
2735 struct nvme_ns *ns, *next;
2736
2737 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2738 list_del(&ns->list);
9e60352c
KB		 2739
2740 spin_lock(&dev_list_lock);
2741 ns->disk->private_data = NULL;
2742 spin_unlock(&dev_list_lock);
2743
9ac27090
KB		 2744 put_disk(ns->disk);
2745 kfree(ns);
2746 }
2747}
2748
5e82e952
KB		 2749static void nvme_free_dev(struct kref *kref)
2750{
2751 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2752
a96d4f5c 2753 pci_dev_put(dev->pci_dev);
b3fffdef 2754 put_device(dev->device);
9ac27090 2755 nvme_free_namespaces(dev);
285dffc9 2756 nvme_release_instance(dev);
a4aea562 2757 blk_mq_free_tag_set(&dev->tagset);
ea191d2f 2758 blk_put_queue(dev->admin_q);
5e82e952
KB		 2759 kfree(dev->queues);
2760 kfree(dev->entry);
2761 kfree(dev);
2762}
2763
2764static int nvme_dev_open(struct inode *inode, struct file *f)
2765{
b3fffdef
KB		 2766 struct nvme_dev *dev;
2767 int instance = iminor(inode);
2768 int ret = -ENODEV;
2769
2770 spin_lock(&dev_list_lock);
2771 list_for_each_entry(dev, &dev_list, node) {
2772 if (dev->instance == instance) {
2e1d8448
KB		 2773 if (!dev->admin_q) {
2774 ret = -EWOULDBLOCK;
2775 break;
2776 }
b3fffdef
KB		 2777 if (!kref_get_unless_zero(&dev->kref))
2778 break;
2779 f->private_data = dev;
2780 ret = 0;
2781 break;
2782 }
2783 }
2784 spin_unlock(&dev_list_lock);
2785
2786 return ret;
5e82e952
KB		 2787}
2788
2789static int nvme_dev_release(struct inode *inode, struct file *f)
2790{
2791 struct nvme_dev *dev = f->private_data;
2792 kref_put(&dev->kref, nvme_free_dev);
2793 return 0;
2794}
2795
2796static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2797{
2798 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2799 struct nvme_ns *ns;
2800
5e82e952
KB		 2801 switch (cmd) {
2802 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2803 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2804 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2805 if (list_empty(&dev->namespaces))
2806 return -ENOTTY;
2807 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2808 return nvme_user_cmd(dev, ns, (void __user *)arg);
5e82e952
KB		 2809 default:
2810 return -ENOTTY;
2811 }
2812}
2813
2814static const struct file_operations nvme_dev_fops = {
2815 .owner = THIS_MODULE,
2816 .open = nvme_dev_open,
2817 .release = nvme_dev_release,
2818 .unlocked_ioctl = nvme_dev_ioctl,
2819 .compat_ioctl = nvme_dev_ioctl,
2820};
2821
a4aea562
MB		 2822static void nvme_set_irq_hints(struct nvme_dev *dev)
2823{
2824 struct nvme_queue *nvmeq;
2825 int i;
2826
2827 for (i = 0; i < dev->online_queues; i++) {
2828 nvmeq = dev->queues[i];
2829
2830 if (!nvmeq->hctx)
2831 continue;
2832
2833 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2834 nvmeq->hctx->cpumask);
2835 }
2836}
2837
f0b50732
KB		 2838static int nvme_dev_start(struct nvme_dev *dev)
2839{
2840 int result;
b9afca3e 2841 bool start_thread = false;
f0b50732
KB		 2842
2843 result = nvme_dev_map(dev);
2844 if (result)
2845 return result;
2846
2847 result = nvme_configure_admin_queue(dev);
2848 if (result)
2849 goto unmap;
2850
2851 spin_lock(&dev_list_lock);
b9afca3e
DM		 2852 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2853 start_thread = true;
2854 nvme_thread = NULL;
2855 }
f0b50732
KB		 2856 list_add(&dev->node, &dev_list);
2857 spin_unlock(&dev_list_lock);
2858
b9afca3e
DM		 2859 if (start_thread) {
2860 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2861 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2862 } else
2863 wait_event_killable(nvme_kthread_wait, nvme_thread);
2864
2865 if (IS_ERR_OR_NULL(nvme_thread)) {
2866 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2867 goto disable;
2868 }
a4aea562
MB		 2869
2870 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 2871 result = nvme_alloc_admin_tags(dev);
2872 if (result)
2873 goto disable;
b9afca3e 2874
f0b50732 2875 result = nvme_setup_io_queues(dev);
badc34d4 2876 if (result)
0fb59cbc 2877 goto free_tags;
f0b50732 2878
a4aea562
MB		 2879 nvme_set_irq_hints(dev);
2880
1efccc9d 2881 dev->event_limit = 1;
d82e8bfd 2882 return result;
f0b50732 2883
0fb59cbc
KB		 2884 free_tags:
2885 nvme_dev_remove_admin(dev);
f0b50732 2886 disable:
a1a5ef99 2887 nvme_disable_queue(dev, 0);
b9afca3e 2888 nvme_dev_list_remove(dev);
f0b50732
KB		 2889 unmap:
2890 nvme_dev_unmap(dev);
2891 return result;
2892}
2893
9a6b9458
KB		 2894static int nvme_remove_dead_ctrl(void *arg)
2895{
2896 struct nvme_dev *dev = (struct nvme_dev *)arg;
2897 struct pci_dev *pdev = dev->pci_dev;
2898
2899 if (pci_get_drvdata(pdev))
c81f4975 2900 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2901 kref_put(&dev->kref, nvme_free_dev);
2902 return 0;
2903}
2904
2905static void nvme_remove_disks(struct work_struct *ws)
2906{
9a6b9458
KB		 2907 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2908
5a92e700 2909 nvme_free_queues(dev, 1);
302c6727 2910 nvme_dev_remove(dev);
9a6b9458
KB		 2911}
2912
2913static int nvme_dev_resume(struct nvme_dev *dev)
2914{
2915 int ret;
2916
2917 ret = nvme_dev_start(dev);
badc34d4 2918 if (ret)
9a6b9458 2919 return ret;
badc34d4 2920 if (dev->online_queues < 2) {
9a6b9458 2921 spin_lock(&dev_list_lock);
9ca97374 2922 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2923 queue_work(nvme_workq, &dev->reset_work);
2924 spin_unlock(&dev_list_lock);
c9d3bf88
KB		 2925 } else {
2926 nvme_unfreeze_queues(dev);
2927 nvme_set_irq_hints(dev);
9a6b9458
KB		 2928 }
2929 return 0;
2930}
2931
2932static void nvme_dev_reset(struct nvme_dev *dev)
2933{
2934 nvme_dev_shutdown(dev);
2935 if (nvme_dev_resume(dev)) {
a4aea562 2936 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
9a6b9458
KB		 2937 kref_get(&dev->kref);
2938 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2939 dev->instance))) {
2940 dev_err(&dev->pci_dev->dev,
2941 "Failed to start controller remove task\n");
2942 kref_put(&dev->kref, nvme_free_dev);
2943 }
2944 }
2945}
2946
2947static void nvme_reset_failed_dev(struct work_struct *ws)
2948{
2949 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2950 nvme_dev_reset(dev);
2951}
2952
9ca97374
TH		 2953static void nvme_reset_workfn(struct work_struct *work)
2954{
2955 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2956 dev->reset_workfn(work);
2957}
2958
2e1d8448 2959static void nvme_async_probe(struct work_struct *work);
8d85fce7 2960static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2961{
a4aea562 2962 int node, result = -ENOMEM;
b60503ba
MW		 2963 struct nvme_dev *dev;
2964
a4aea562
MB		 2965 node = dev_to_node(&pdev->dev);
2966 if (node == NUMA_NO_NODE)
2967 set_dev_node(&pdev->dev, 0);
2968
2969 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2970 if (!dev)
2971 return -ENOMEM;
a4aea562
MB		 2972 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2973 GFP_KERNEL, node);
b60503ba
MW		 2974 if (!dev->entry)
2975 goto free;
a4aea562
MB		 2976 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2977 GFP_KERNEL, node);
b60503ba
MW		 2978 if (!dev->queues)
2979 goto free;
2980
2981 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2982 dev->reset_workfn = nvme_reset_failed_dev;
2983 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
a96d4f5c 2984 dev->pci_dev = pci_dev_get(pdev);
9a6b9458 2985 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2986 result = nvme_set_instance(dev);
2987 if (result)
a96d4f5c 2988 goto put_pci;
b60503ba 2989
091b6092
MW		 2990 result = nvme_setup_prp_pools(dev);
2991 if (result)
0877cb0d 2992 goto release;
091b6092 2993
fb35e914 2994 kref_init(&dev->kref);
b3fffdef
KB		 2995 dev->device = device_create(nvme_class, &pdev->dev,
2996 MKDEV(nvme_char_major, dev->instance),
2997 dev, "nvme%d", dev->instance);
2998 if (IS_ERR(dev->device)) {
2999 result = PTR_ERR(dev->device);
2e1d8448 3000 goto release_pools;
b3fffdef
KB		 3001 }
3002 get_device(dev->device);
740216fc 3003
2e1d8448
KB		 3004 INIT_WORK(&dev->probe_work, nvme_async_probe);
3005 schedule_work(&dev->probe_work);
b60503ba
MW		 3006 return 0;
3007
0877cb0d 3008 release_pools:
091b6092 3009 nvme_release_prp_pools(dev);
0877cb0d
KB		 3010 release:
3011 nvme_release_instance(dev);
a96d4f5c
KB		 3012 put_pci:
3013 pci_dev_put(dev->pci_dev);
b60503ba
MW		 3014 free:
3015 kfree(dev->queues);
3016 kfree(dev->entry);
3017 kfree(dev);
3018 return result;
3019}
3020
2e1d8448
KB		 3021static void nvme_async_probe(struct work_struct *work)
3022{
3023 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
3024 int result;
3025
3026 result = nvme_dev_start(dev);
3027 if (result)
3028 goto reset;
3029
3030 if (dev->online_queues > 1)
3031 result = nvme_dev_add(dev);
3032 if (result)
3033 goto reset;
3034
3035 nvme_set_irq_hints(dev);
2e1d8448
KB		 3036 return;
3037 reset:
07836e65
KB		 3038 if (!work_busy(&dev->reset_work)) {
3039 dev->reset_workfn = nvme_reset_failed_dev;
3040 queue_work(nvme_workq, &dev->reset_work);
3041 }
2e1d8448
KB		 3042}
3043
f0d54a54
KB		 3044static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3045{
a6739479 3046 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 3047
a6739479
KB		 3048 if (prepare)
3049 nvme_dev_shutdown(dev);
3050 else
3051 nvme_dev_resume(dev);
f0d54a54
KB		 3052}
3053
09ece142
KB		 3054static void nvme_shutdown(struct pci_dev *pdev)
3055{
3056 struct nvme_dev *dev = pci_get_drvdata(pdev);
3057 nvme_dev_shutdown(dev);
3058}
3059
8d85fce7 3060static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3061{
3062 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 3063
3064 spin_lock(&dev_list_lock);
3065 list_del_init(&dev->node);
3066 spin_unlock(&dev_list_lock);
3067
3068 pci_set_drvdata(pdev, NULL);
2e1d8448 3069 flush_work(&dev->probe_work);
9a6b9458 3070 flush_work(&dev->reset_work);
9a6b9458 3071 nvme_dev_shutdown(dev);
c9d3bf88 3072 nvme_dev_remove(dev);
a4aea562 3073 nvme_dev_remove_admin(dev);
b3fffdef 3074 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
a1a5ef99 3075 nvme_free_queues(dev, 0);
9a6b9458 3076 nvme_release_prp_pools(dev);
5e82e952 3077 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 3078}
3079
3080/* These functions are yet to be implemented */
3081#define nvme_error_detected NULL
3082#define nvme_dump_registers NULL
3083#define nvme_link_reset NULL
3084#define nvme_slot_reset NULL
3085#define nvme_error_resume NULL
cd638946 3086
671a6018 3087#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3088static int nvme_suspend(struct device *dev)
3089{
3090 struct pci_dev *pdev = to_pci_dev(dev);
3091 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3092
3093 nvme_dev_shutdown(ndev);
3094 return 0;
3095}
3096
3097static int nvme_resume(struct device *dev)
3098{
3099 struct pci_dev *pdev = to_pci_dev(dev);
3100 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3101
9a6b9458 3102 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 3103 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 3104 queue_work(nvme_workq, &ndev->reset_work);
3105 }
3106 return 0;
cd638946 3107}
671a6018 3108#endif
cd638946
KB		 3109
3110static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 3111
1d352035 3112static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 3113 .error_detected = nvme_error_detected,
3114 .mmio_enabled = nvme_dump_registers,
3115 .link_reset = nvme_link_reset,
3116 .slot_reset = nvme_slot_reset,
3117 .resume = nvme_error_resume,
f0d54a54 3118 .reset_notify = nvme_reset_notify,
b60503ba
MW		 3119};
3120
3121/* Move to pci_ids.h later */
3122#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3123
6eb0d698 3124static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 3125 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3126 { 0, }
3127};
3128MODULE_DEVICE_TABLE(pci, nvme_id_table);
3129
3130static struct pci_driver nvme_driver = {
3131 .name = "nvme",
3132 .id_table = nvme_id_table,
3133 .probe = nvme_probe,
8d85fce7 3134 .remove = nvme_remove,
09ece142 3135 .shutdown = nvme_shutdown,
cd638946
KB		 3136 .driver = {
3137 .pm = &nvme_dev_pm_ops,
3138 },
b60503ba
MW		 3139 .err_handler = &nvme_err_handler,
3140};
3141
3142static int __init nvme_init(void)
3143{
0ac13140 3144 int result;
1fa6aead 3145
b9afca3e 3146 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3147
9a6b9458
KB		 3148 nvme_workq = create_singlethread_workqueue("nvme");
3149 if (!nvme_workq)
b9afca3e 3150 return -ENOMEM;
9a6b9458 3151
5c42ea16
KB		 3152 result = register_blkdev(nvme_major, "nvme");
3153 if (result < 0)
9a6b9458 3154 goto kill_workq;
5c42ea16 3155 else if (result > 0)
0ac13140 3156 nvme_major = result;
b60503ba 3157
b3fffdef
KB		 3158 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3159 &nvme_dev_fops);
3160 if (result < 0)
3161 goto unregister_blkdev;
3162 else if (result > 0)
3163 nvme_char_major = result;
3164
3165 nvme_class = class_create(THIS_MODULE, "nvme");
3166 if (!nvme_class)
3167 goto unregister_chrdev;
3168
f3db22fe
KB		 3169 result = pci_register_driver(&nvme_driver);
3170 if (result)
b3fffdef 3171 goto destroy_class;
1fa6aead 3172 return 0;
b60503ba 3173
b3fffdef
KB		 3174 destroy_class:
3175 class_destroy(nvme_class);
3176 unregister_chrdev:
3177 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1fa6aead 3178 unregister_blkdev:
b60503ba 3179 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3180 kill_workq:
3181 destroy_workqueue(nvme_workq);
b60503ba
MW		 3182 return result;
3183}
3184
3185static void __exit nvme_exit(void)
3186{
3187 pci_unregister_driver(&nvme_driver);
3188 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3189 destroy_workqueue(nvme_workq);
b3fffdef
KB		 3190 class_destroy(nvme_class);
3191 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
b9afca3e 3192 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3193 _nvme_check_size();
b60503ba
MW		 3194}
3195
3196MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3197MODULE_LICENSE("GPL");
c78b4713 3198MODULE_VERSION("1.0");
b60503ba
MW		 3199module_init(nvme_init);
3200module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)