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blk-mq: add BLK_MQ_F_DEFER_ISSUE support flag
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
16#include <linux/bio.h>
8de05535 17#include <linux/bitops.h>
b60503ba 18#include <linux/blkdev.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
42f61420 36#include <linux/percpu.h>
be7b6275 37#include <linux/poison.h>
c3bfe717 38#include <linux/ptrace.h>
b60503ba
MW		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
5d0f6131 42#include <scsi/sg.h>
797a796a
HM		 43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
3291fa57
KB		 45#include <trace/events/block.h>
46
9d43cf64 47#define NVME_Q_DEPTH 1024
b60503ba
MW		 48#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
49#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64
KB		 50#define ADMIN_TIMEOUT (admin_timeout * HZ)
51#define IOD_TIMEOUT (retry_time * HZ)
52
53static unsigned char admin_timeout = 60;
54module_param(admin_timeout, byte, 0644);
55MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 56
bd67608a
MW		 57unsigned char nvme_io_timeout = 30;
58module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 59MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 60
61e4ce08
KB		 61static unsigned char retry_time = 30;
62module_param(retry_time, byte, 0644);
63MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
64
b60503ba
MW		 65static int nvme_major;
66module_param(nvme_major, int, 0);
67
58ffacb5
MW		 68static int use_threaded_interrupts;
69module_param(use_threaded_interrupts, int, 0);
70
1fa6aead
MW		 71static DEFINE_SPINLOCK(dev_list_lock);
72static LIST_HEAD(dev_list);
73static struct task_struct *nvme_thread;
9a6b9458 74static struct workqueue_struct *nvme_workq;
b9afca3e 75static wait_queue_head_t nvme_kthread_wait;
f3db22fe 76static struct notifier_block nvme_nb;
1fa6aead 77
d4b4ff8e
KB		 78static void nvme_reset_failed_dev(struct work_struct *ws);
79
4d115420
KB		 80struct async_cmd_info {
81 struct kthread_work work;
82 struct kthread_worker *worker;
83 u32 result;
84 int status;
85 void *ctx;
86};
1fa6aead 87
b60503ba
MW		 88/*
89 * An NVM Express queue. Each device has at least two (one for admin
90 * commands and one for I/O commands).
91 */
92struct nvme_queue {
5a92e700 93 struct rcu_head r_head;
b60503ba 94 struct device *q_dmadev;
091b6092 95 struct nvme_dev *dev;
3193f07b 96 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 97 spinlock_t q_lock;
98 struct nvme_command *sq_cmds;
99 volatile struct nvme_completion *cqes;
100 dma_addr_t sq_dma_addr;
101 dma_addr_t cq_dma_addr;
102 wait_queue_head_t sq_full;
1fa6aead 103 wait_queue_t sq_cong_wait;
b60503ba 104 struct bio_list sq_cong;
edd10d33 105 struct list_head iod_bio;
b60503ba
MW		 106 u32 __iomem *q_db;
107 u16 q_depth;
108 u16 cq_vector;
109 u16 sq_head;
110 u16 sq_tail;
111 u16 cq_head;
c30341dc 112 u16 qid;
e9539f47
MW		 113 u8 cq_phase;
114 u8 cqe_seen;
22404274 115 u8 q_suspended;
42f61420 116 cpumask_var_t cpu_mask;
4d115420 117 struct async_cmd_info cmdinfo;
b60503ba
MW		 118 unsigned long cmdid_data[];
119};
120
121/*
122 * Check we didin't inadvertently grow the command struct
123 */
124static inline void _nvme_check_size(void)
125{
126 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 131 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 132 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 133 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
136 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 137 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 138}
139
edd10d33 140typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 141 struct nvme_completion *);
142
e85248e5 143struct nvme_cmd_info {
c2f5b650
MW		 144 nvme_completion_fn fn;
145 void *ctx;
e85248e5 146 unsigned long timeout;
c30341dc 147 int aborted;
e85248e5
MW		 148};
149
150static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
151{
152 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
153}
154
22404274
KB		 155static unsigned nvme_queue_extra(int depth)
156{
157 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
158}
159
b60503ba 160/**
714a7a22
MW		 161 * alloc_cmdid() - Allocate a Command ID
162 * @nvmeq: The queue that will be used for this command
163 * @ctx: A pointer that will be passed to the handler
c2f5b650 164 * @handler: The function to call on completion
b60503ba
MW		 165 *
166 * Allocate a Command ID for a queue. The data passed in will
167 * be passed to the completion handler. This is implemented by using
168 * the bottom two bits of the ctx pointer to store the handler ID.
169 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
170 * We can change this if it becomes a problem.
184d2944
MW		 171 *
172 * May be called with local interrupts disabled and the q_lock held,
173 * or with interrupts enabled and no locks held.
b60503ba 174 */
c2f5b650
MW		 175static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
176 nvme_completion_fn handler, unsigned timeout)
b60503ba 177{
e6d15f79 178 int depth = nvmeq->q_depth - 1;
e85248e5 179 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba
MW		 180 int cmdid;
181
b60503ba
MW		 182 do {
183 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
184 if (cmdid >= depth)
185 return -EBUSY;
186 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
187
c2f5b650
MW		 188 info[cmdid].fn = handler;
189 info[cmdid].ctx = ctx;
e85248e5 190 info[cmdid].timeout = jiffies + timeout;
c30341dc 191 info[cmdid].aborted = 0;
b60503ba
MW		 192 return cmdid;
193}
194
195static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 196 nvme_completion_fn handler, unsigned timeout)
b60503ba
MW		 197{
198 int cmdid;
199 wait_event_killable(nvmeq->sq_full,
e85248e5 200 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
b60503ba
MW		 201 return (cmdid < 0) ? -EINTR : cmdid;
202}
203
c2f5b650
MW		 204/* Special values must be less than 0x1000 */
205#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 206#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
207#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
208#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
53562be7 209#define CMD_CTX_ABORT (0x318 + CMD_CTX_BASE)
be7b6275 210
edd10d33 211static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 212 struct nvme_completion *cqe)
213{
214 if (ctx == CMD_CTX_CANCELLED)
215 return;
c30341dc 216 if (ctx == CMD_CTX_ABORT) {
edd10d33 217 ++nvmeq->dev->abort_limit;
c30341dc
KB		 218 return;
219 }
c2f5b650 220 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 221 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 222 "completed id %d twice on queue %d\n",
223 cqe->command_id, le16_to_cpup(&cqe->sq_id));
224 return;
225 }
226 if (ctx == CMD_CTX_INVALID) {
edd10d33 227 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 228 "invalid id %d completed on queue %d\n",
229 cqe->command_id, le16_to_cpup(&cqe->sq_id));
230 return;
231 }
232
edd10d33 233 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 234}
235
edd10d33 236static void async_completion(struct nvme_queue *nvmeq, void *ctx,
4d115420
KB		 237 struct nvme_completion *cqe)
238{
239 struct async_cmd_info *cmdinfo = ctx;
240 cmdinfo->result = le32_to_cpup(&cqe->result);
241 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
242 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
243}
244
184d2944
MW		 245/*
246 * Called with local interrupts disabled and the q_lock held. May not sleep.
247 */
c2f5b650
MW		 248static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
249 nvme_completion_fn *fn)
b60503ba 250{
c2f5b650 251 void *ctx;
e85248e5 252 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 253
94bbac40
KB		 254 if (cmdid >= nvmeq->q_depth || !info[cmdid].fn) {
255 if (fn)
256 *fn = special_completion;
48e3d398 257 return CMD_CTX_INVALID;
c2f5b650 258 }
859361a2
KB		 259 if (fn)
260 *fn = info[cmdid].fn;
c2f5b650
MW		 261 ctx = info[cmdid].ctx;
262 info[cmdid].fn = special_completion;
e85248e5 263 info[cmdid].ctx = CMD_CTX_COMPLETED;
b60503ba
MW		 264 clear_bit(cmdid, nvmeq->cmdid_data);
265 wake_up(&nvmeq->sq_full);
c2f5b650 266 return ctx;
b60503ba
MW		 267}
268
c2f5b650
MW		 269static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
270 nvme_completion_fn *fn)
3c0cf138 271{
c2f5b650 272 void *ctx;
e85248e5 273 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
c2f5b650
MW		 274 if (fn)
275 *fn = info[cmdid].fn;
276 ctx = info[cmdid].ctx;
277 info[cmdid].fn = special_completion;
e85248e5 278 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 279 return ctx;
3c0cf138
MW		 280}
281
5a92e700 282static struct nvme_queue *raw_nvmeq(struct nvme_dev *dev, int qid)
b60503ba 283{
5a92e700 284 return rcu_dereference_raw(dev->queues[qid]);
b60503ba
MW		 285}
286
4f5099af 287static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) __acquires(RCU)
5a92e700 288{
a51afb54 289 struct nvme_queue *nvmeq;
42f61420 290 unsigned queue_id = get_cpu_var(*dev->io_queue);
a51afb54 291
5a92e700 292 rcu_read_lock();
a51afb54
KB		 293 nvmeq = rcu_dereference(dev->queues[queue_id]);
294 if (nvmeq)
295 return nvmeq;
296
297 rcu_read_unlock();
298 put_cpu_var(*dev->io_queue);
299 return NULL;
5a92e700
KB		 300}
301
4f5099af 302static void put_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
b60503ba 303{
5a92e700 304 rcu_read_unlock();
42f61420 305 put_cpu_var(nvmeq->dev->io_queue);
b60503ba
MW		 306}
307
4f5099af
KB		 308static struct nvme_queue *lock_nvmeq(struct nvme_dev *dev, int q_idx)
309 __acquires(RCU)
b60503ba 310{
a51afb54
KB		 311 struct nvme_queue *nvmeq;
312
4f5099af 313 rcu_read_lock();
a51afb54
KB		 314 nvmeq = rcu_dereference(dev->queues[q_idx]);
315 if (nvmeq)
316 return nvmeq;
317
318 rcu_read_unlock();
319 return NULL;
4f5099af
KB		 320}
321
322static void unlock_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
323{
324 rcu_read_unlock();
b60503ba
MW		 325}
326
327/**
714a7a22 328 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 329 * @nvmeq: The queue to use
330 * @cmd: The command to send
331 *
332 * Safe to use from interrupt context
333 */
334static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
335{
336 unsigned long flags;
337 u16 tail;
b60503ba 338 spin_lock_irqsave(&nvmeq->q_lock, flags);
4f5099af
KB		 339 if (nvmeq->q_suspended) {
340 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
341 return -EBUSY;
342 }
b60503ba
MW		 343 tail = nvmeq->sq_tail;
344 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 345 if (++tail == nvmeq->q_depth)
346 tail = 0;
7547881d 347 writel(tail, nvmeq->q_db);
b60503ba
MW		 348 nvmeq->sq_tail = tail;
349 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
350
351 return 0;
352}
353
eca18b23 354static __le64 **iod_list(struct nvme_iod *iod)
e025344c 355{
eca18b23 356 return ((void *)iod) + iod->offset;
e025344c
SMM		 357}
358
eca18b23
MW		 359/*
360 * Will slightly overestimate the number of pages needed. This is OK
361 * as it only leads to a small amount of wasted memory for the lifetime of
362 * the I/O.
363 */
364static int nvme_npages(unsigned size)
365{
366 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
367 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
368}
b60503ba 369
eca18b23
MW		 370static struct nvme_iod *
371nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
b60503ba 372{
eca18b23
MW		 373 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
374 sizeof(__le64 *) * nvme_npages(nbytes) +
375 sizeof(struct scatterlist) * nseg, gfp);
376
377 if (iod) {
378 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
379 iod->npages = -1;
380 iod->length = nbytes;
2b196034 381 iod->nents = 0;
edd10d33 382 iod->first_dma = 0ULL;
6198221f 383 iod->start_time = jiffies;
eca18b23
MW		 384 }
385
386 return iod;
b60503ba
MW		 387}
388
5d0f6131 389void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 390{
eca18b23
MW		 391 const int last_prp = PAGE_SIZE / 8 - 1;
392 int i;
393 __le64 **list = iod_list(iod);
394 dma_addr_t prp_dma = iod->first_dma;
395
396 if (iod->npages == 0)
397 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
398 for (i = 0; i < iod->npages; i++) {
399 __le64 *prp_list = list[i];
400 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
401 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
402 prp_dma = next_prp_dma;
403 }
404 kfree(iod);
b60503ba
MW		 405}
406
6198221f
KB		 407static void nvme_start_io_acct(struct bio *bio)
408{
409 struct gendisk *disk = bio->bi_bdev->bd_disk;
b4e75cbf
SB		 410 if (blk_queue_io_stat(disk->queue)) {
411 const int rw = bio_data_dir(bio);
412 int cpu = part_stat_lock();
413 part_round_stats(cpu, &disk->part0);
414 part_stat_inc(cpu, &disk->part0, ios[rw]);
415 part_stat_add(cpu, &disk->part0, sectors[rw],
416 bio_sectors(bio));
417 part_inc_in_flight(&disk->part0, rw);
418 part_stat_unlock();
419 }
6198221f
KB		 420}
421
422static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
423{
424 struct gendisk *disk = bio->bi_bdev->bd_disk;
b4e75cbf
SB		 425 if (blk_queue_io_stat(disk->queue)) {
426 const int rw = bio_data_dir(bio);
427 unsigned long duration = jiffies - start_time;
428 int cpu = part_stat_lock();
429 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
430 part_round_stats(cpu, &disk->part0);
431 part_dec_in_flight(&disk->part0, rw);
432 part_stat_unlock();
433 }
6198221f
KB		 434}
435
edd10d33 436static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 437 struct nvme_completion *cqe)
438{
eca18b23
MW		 439 struct nvme_iod *iod = ctx;
440 struct bio *bio = iod->private;
b60503ba 441 u16 status = le16_to_cpup(&cqe->status) >> 1;
3291fa57 442 int error = 0;
b60503ba 443
edd10d33
KB		 444 if (unlikely(status)) {
445 if (!(status & NVME_SC_DNR ||
446 bio->bi_rw & REQ_FAILFAST_MASK) &&
447 (jiffies - iod->start_time) < IOD_TIMEOUT) {
448 if (!waitqueue_active(&nvmeq->sq_full))
449 add_wait_queue(&nvmeq->sq_full,
450 &nvmeq->sq_cong_wait);
451 list_add_tail(&iod->node, &nvmeq->iod_bio);
452 wake_up(&nvmeq->sq_full);
453 return;
454 }
3291fa57 455 error = -EIO;
edd10d33 456 }
9e59d091 457 if (iod->nents) {
edd10d33 458 dma_unmap_sg(nvmeq->q_dmadev, iod->sg, iod->nents,
b60503ba 459 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9e59d091
KB		 460 nvme_end_io_acct(bio, iod->start_time);
461 }
edd10d33 462 nvme_free_iod(nvmeq->dev, iod);
3291fa57
KB		 463
464 trace_block_bio_complete(bdev_get_queue(bio->bi_bdev), bio, error);
465 bio_endio(bio, error);
b60503ba
MW		 466}
467
184d2944 468/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 469int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
470 gfp_t gfp)
ff22b54f 471{
99802a7a 472 struct dma_pool *pool;
eca18b23
MW		 473 int length = total_len;
474 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 475 int dma_len = sg_dma_len(sg);
476 u64 dma_addr = sg_dma_address(sg);
477 int offset = offset_in_page(dma_addr);
e025344c 478 __le64 *prp_list;
eca18b23 479 __le64 **list = iod_list(iod);
e025344c 480 dma_addr_t prp_dma;
eca18b23 481 int nprps, i;
ff22b54f 482
ff22b54f
MW		 483 length -= (PAGE_SIZE - offset);
484 if (length <= 0)
eca18b23 485 return total_len;
ff22b54f
MW		 486
487 dma_len -= (PAGE_SIZE - offset);
488 if (dma_len) {
489 dma_addr += (PAGE_SIZE - offset);
490 } else {
491 sg = sg_next(sg);
492 dma_addr = sg_dma_address(sg);
493 dma_len = sg_dma_len(sg);
494 }
495
496 if (length <= PAGE_SIZE) {
edd10d33 497 iod->first_dma = dma_addr;
eca18b23 498 return total_len;
e025344c
SMM		 499 }
500
501 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
99802a7a
MW		 502 if (nprps <= (256 / 8)) {
503 pool = dev->prp_small_pool;
eca18b23 504 iod->npages = 0;
99802a7a
MW		 505 } else {
506 pool = dev->prp_page_pool;
eca18b23 507 iod->npages = 1;
99802a7a
MW		 508 }
509
b77954cb
MW		 510 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
511 if (!prp_list) {
edd10d33 512 iod->first_dma = dma_addr;
eca18b23
MW		 513 iod->npages = -1;
514 return (total_len - length) + PAGE_SIZE;
b77954cb 515 }
eca18b23
MW		 516 list[0] = prp_list;
517 iod->first_dma = prp_dma;
e025344c
SMM		 518 i = 0;
519 for (;;) {
7523d834 520 if (i == PAGE_SIZE / 8) {
e025344c 521 __le64 *old_prp_list = prp_list;
b77954cb 522 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 523 if (!prp_list)
524 return total_len - length;
525 list[iod->npages++] = prp_list;
7523d834
MW		 526 prp_list[0] = old_prp_list[i - 1];
527 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
528 i = 1;
e025344c
SMM		 529 }
530 prp_list[i++] = cpu_to_le64(dma_addr);
531 dma_len -= PAGE_SIZE;
532 dma_addr += PAGE_SIZE;
533 length -= PAGE_SIZE;
534 if (length <= 0)
535 break;
536 if (dma_len > 0)
537 continue;
538 BUG_ON(dma_len < 0);
539 sg = sg_next(sg);
540 dma_addr = sg_dma_address(sg);
541 dma_len = sg_dma_len(sg);
ff22b54f
MW		 542 }
543
eca18b23 544 return total_len;
ff22b54f
MW		 545}
546
427e9708 547static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
20d0189b 548 int len)
427e9708 549{
20d0189b
KO		 550 struct bio *split = bio_split(bio, len >> 9, GFP_ATOMIC, NULL);
551 if (!split)
427e9708
KB		 552 return -ENOMEM;
553
3291fa57
KB		 554 trace_block_split(bdev_get_queue(bio->bi_bdev), bio,
555 split->bi_iter.bi_sector);
20d0189b
KO		 556 bio_chain(split, bio);
557
edd10d33 558 if (!waitqueue_active(&nvmeq->sq_full))
427e9708 559 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
20d0189b
KO		 560 bio_list_add(&nvmeq->sq_cong, split);
561 bio_list_add(&nvmeq->sq_cong, bio);
edd10d33 562 wake_up(&nvmeq->sq_full);
427e9708
KB		 563
564 return 0;
565}
566
1ad2f893
MW		 567/* NVMe scatterlists require no holes in the virtual address */
568#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
569 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
570
427e9708 571static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
b60503ba
MW		 572 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
573{
7988613b
KO		 574 struct bio_vec bvec, bvprv;
575 struct bvec_iter iter;
76830840 576 struct scatterlist *sg = NULL;
7988613b
KO		 577 int length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size;
578 int first = 1;
159b67d7
KB		 579
580 if (nvmeq->dev->stripe_size)
581 split_len = nvmeq->dev->stripe_size -
4f024f37
KO		 582 ((bio->bi_iter.bi_sector << 9) &
583 (nvmeq->dev->stripe_size - 1));
b60503ba 584
eca18b23 585 sg_init_table(iod->sg, psegs);
7988613b
KO		 586 bio_for_each_segment(bvec, bio, iter) {
587 if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) {
588 sg->length += bvec.bv_len;
76830840 589 } else {
7988613b
KO		 590 if (!first && BIOVEC_NOT_VIRT_MERGEABLE(&bvprv, &bvec))
591 return nvme_split_and_submit(bio, nvmeq,
20d0189b 592 length);
427e9708 593
eca18b23 594 sg = sg ? sg + 1 : iod->sg;
7988613b
KO		 595 sg_set_page(sg, bvec.bv_page,
596 bvec.bv_len, bvec.bv_offset);
76830840
MW		 597 nsegs++;
598 }
159b67d7 599
7988613b 600 if (split_len - length < bvec.bv_len)
20d0189b 601 return nvme_split_and_submit(bio, nvmeq, split_len);
7988613b 602 length += bvec.bv_len;
76830840 603 bvprv = bvec;
7988613b 604 first = 0;
b60503ba 605 }
eca18b23 606 iod->nents = nsegs;
76830840 607 sg_mark_end(sg);
427e9708 608 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
1ad2f893 609 return -ENOMEM;
427e9708 610
4f024f37 611 BUG_ON(length != bio->bi_iter.bi_size);
1ad2f893 612 return length;
b60503ba
MW		 613}
614
0e5e4f0e
KB		 615static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
616 struct bio *bio, struct nvme_iod *iod, int cmdid)
617{
edd10d33
KB		 618 struct nvme_dsm_range *range =
619 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 620 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
621
0e5e4f0e 622 range->cattr = cpu_to_le32(0);
4f024f37
KO		 623 range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift);
624 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
0e5e4f0e
KB		 625
626 memset(cmnd, 0, sizeof(*cmnd));
627 cmnd->dsm.opcode = nvme_cmd_dsm;
628 cmnd->dsm.command_id = cmdid;
629 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
630 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
631 cmnd->dsm.nr = 0;
632 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
633
634 if (++nvmeq->sq_tail == nvmeq->q_depth)
635 nvmeq->sq_tail = 0;
636 writel(nvmeq->sq_tail, nvmeq->q_db);
637
638 return 0;
639}
640
00df5cb4
MW		 641static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
642 int cmdid)
643{
644 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
645
646 memset(cmnd, 0, sizeof(*cmnd));
647 cmnd->common.opcode = nvme_cmd_flush;
648 cmnd->common.command_id = cmdid;
649 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
650
651 if (++nvmeq->sq_tail == nvmeq->q_depth)
652 nvmeq->sq_tail = 0;
653 writel(nvmeq->sq_tail, nvmeq->q_db);
654
655 return 0;
656}
657
edd10d33 658static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod)
b60503ba 659{
edd10d33
KB		 660 struct bio *bio = iod->private;
661 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
ff22b54f 662 struct nvme_command *cmnd;
edd10d33 663 int cmdid;
b60503ba
MW		 664 u16 control;
665 u32 dsmgmt;
00df5cb4 666
ff976d72 667 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 668 if (unlikely(cmdid < 0))
edd10d33 669 return cmdid;
b60503ba 670
edd10d33
KB		 671 if (bio->bi_rw & REQ_DISCARD)
672 return nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
53562be7 673 if (bio->bi_rw & REQ_FLUSH)
00df5cb4
MW		 674 return nvme_submit_flush(nvmeq, ns, cmdid);
675
b60503ba
MW		 676 control = 0;
677 if (bio->bi_rw & REQ_FUA)
678 control |= NVME_RW_FUA;
679 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
680 control |= NVME_RW_LR;
681
682 dsmgmt = 0;
683 if (bio->bi_rw & REQ_RAHEAD)
684 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
685
ff22b54f 686 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 687 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 688
edd10d33 689 cmnd->rw.opcode = bio_data_dir(bio) ? nvme_cmd_write : nvme_cmd_read;
ff22b54f
MW		 690 cmnd->rw.command_id = cmdid;
691 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 692 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
693 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
4f024f37 694 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
edd10d33
KB		 695 cmnd->rw.length =
696 cpu_to_le16((bio->bi_iter.bi_size >> ns->lba_shift) - 1);
ff22b54f
MW		 697 cmnd->rw.control = cpu_to_le16(control);
698 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 699
b60503ba
MW		 700 if (++nvmeq->sq_tail == nvmeq->q_depth)
701 nvmeq->sq_tail = 0;
7547881d 702 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 703
1974b1ae 704 return 0;
edd10d33
KB		 705}
706
53562be7
KB		 707static int nvme_split_flush_data(struct nvme_queue *nvmeq, struct bio *bio)
708{
709 struct bio *split = bio_clone(bio, GFP_ATOMIC);
710 if (!split)
711 return -ENOMEM;
712
713 split->bi_iter.bi_size = 0;
714 split->bi_phys_segments = 0;
715 bio->bi_rw &= ~REQ_FLUSH;
716 bio_chain(split, bio);
717
718 if (!waitqueue_active(&nvmeq->sq_full))
719 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
720 bio_list_add(&nvmeq->sq_cong, split);
721 bio_list_add(&nvmeq->sq_cong, bio);
722 wake_up_process(nvme_thread);
723
724 return 0;
725}
726
edd10d33
KB		 727/*
728 * Called with local interrupts disabled and the q_lock held. May not sleep.
729 */
730static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
731 struct bio *bio)
732{
733 struct nvme_iod *iod;
734 int psegs = bio_phys_segments(ns->queue, bio);
735 int result;
736
53562be7
KB		 737 if ((bio->bi_rw & REQ_FLUSH) && psegs)
738 return nvme_split_flush_data(nvmeq, bio);
edd10d33
KB		 739
740 iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, GFP_ATOMIC);
741 if (!iod)
742 return -ENOMEM;
743
744 iod->private = bio;
745 if (bio->bi_rw & REQ_DISCARD) {
746 void *range;
747 /*
748 * We reuse the small pool to allocate the 16-byte range here
749 * as it is not worth having a special pool for these or
750 * additional cases to handle freeing the iod.
751 */
752 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
753 GFP_ATOMIC,
754 &iod->first_dma);
755 if (!range) {
756 result = -ENOMEM;
757 goto free_iod;
758 }
759 iod_list(iod)[0] = (__le64 *)range;
760 iod->npages = 0;
761 } else if (psegs) {
762 result = nvme_map_bio(nvmeq, iod, bio,
763 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
764 psegs);
765 if (result <= 0)
766 goto free_iod;
767 if (nvme_setup_prps(nvmeq->dev, iod, result, GFP_ATOMIC) !=
768 result) {
769 result = -ENOMEM;
770 goto free_iod;
771 }
772 nvme_start_io_acct(bio);
773 }
774 if (unlikely(nvme_submit_iod(nvmeq, iod))) {
775 if (!waitqueue_active(&nvmeq->sq_full))
776 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
777 list_add_tail(&iod->node, &nvmeq->iod_bio);
778 }
779 return 0;
1974b1ae 780
eca18b23
MW		 781 free_iod:
782 nvme_free_iod(nvmeq->dev, iod);
eeee3226 783 return result;
b60503ba
MW		 784}
785
e9539f47 786static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 787{
82123460 788 u16 head, phase;
b60503ba 789
b60503ba 790 head = nvmeq->cq_head;
82123460 791 phase = nvmeq->cq_phase;
b60503ba
MW		 792
793 for (;;) {
c2f5b650
MW		 794 void *ctx;
795 nvme_completion_fn fn;
b60503ba 796 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 797 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 798 break;
799 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
800 if (++head == nvmeq->q_depth) {
801 head = 0;
82123460 802 phase = !phase;
b60503ba
MW		 803 }
804
c2f5b650 805 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
edd10d33 806 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 807 }
808
809 /* If the controller ignores the cq head doorbell and continuously
810 * writes to the queue, it is theoretically possible to wrap around
811 * the queue twice and mistakenly return IRQ_NONE. Linux only
812 * requires that 0.1% of your interrupts are handled, so this isn't
813 * a big problem.
814 */
82123460 815 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 816 return 0;
b60503ba 817
b80d5ccc 818 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 819 nvmeq->cq_head = head;
82123460 820 nvmeq->cq_phase = phase;
b60503ba 821
e9539f47
MW		 822 nvmeq->cqe_seen = 1;
823 return 1;
b60503ba
MW		 824}
825
7d822457
MW		 826static void nvme_make_request(struct request_queue *q, struct bio *bio)
827{
828 struct nvme_ns *ns = q->queuedata;
829 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
830 int result = -EBUSY;
831
cd638946 832 if (!nvmeq) {
cd638946
KB		 833 bio_endio(bio, -EIO);
834 return;
835 }
836
7d822457 837 spin_lock_irq(&nvmeq->q_lock);
22404274 838 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
7d822457
MW		 839 result = nvme_submit_bio_queue(nvmeq, ns, bio);
840 if (unlikely(result)) {
edd10d33 841 if (!waitqueue_active(&nvmeq->sq_full))
7d822457
MW		 842 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
843 bio_list_add(&nvmeq->sq_cong, bio);
844 }
845
846 nvme_process_cq(nvmeq);
847 spin_unlock_irq(&nvmeq->q_lock);
848 put_nvmeq(nvmeq);
849}
850
b60503ba 851static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 852{
853 irqreturn_t result;
854 struct nvme_queue *nvmeq = data;
855 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 856 nvme_process_cq(nvmeq);
857 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
858 nvmeq->cqe_seen = 0;
58ffacb5
MW		 859 spin_unlock(&nvmeq->q_lock);
860 return result;
861}
862
863static irqreturn_t nvme_irq_check(int irq, void *data)
864{
865 struct nvme_queue *nvmeq = data;
866 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
867 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
868 return IRQ_NONE;
869 return IRQ_WAKE_THREAD;
870}
871
3c0cf138
MW		 872static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
873{
874 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 875 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW		 876 spin_unlock_irq(&nvmeq->q_lock);
877}
878
c2f5b650
MW		 879struct sync_cmd_info {
880 struct task_struct *task;
881 u32 result;
882 int status;
883};
884
edd10d33 885static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 886 struct nvme_completion *cqe)
887{
888 struct sync_cmd_info *cmdinfo = ctx;
889 cmdinfo->result = le32_to_cpup(&cqe->result);
890 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
891 wake_up_process(cmdinfo->task);
892}
893
b60503ba
MW		 894/*
895 * Returns 0 on success. If the result is negative, it's a Linux error code;
896 * if the result is positive, it's an NVM Express status code
897 */
4f5099af
KB		 898static int nvme_submit_sync_cmd(struct nvme_dev *dev, int q_idx,
899 struct nvme_command *cmd,
5d0f6131 900 u32 *result, unsigned timeout)
b60503ba 901{
4f5099af 902 int cmdid, ret;
b60503ba 903 struct sync_cmd_info cmdinfo;
4f5099af
KB		 904 struct nvme_queue *nvmeq;
905
906 nvmeq = lock_nvmeq(dev, q_idx);
a51afb54 907 if (!nvmeq)
4f5099af 908 return -ENODEV;
b60503ba
MW		 909
910 cmdinfo.task = current;
911 cmdinfo.status = -EINTR;
912
4f5099af
KB		 913 cmdid = alloc_cmdid(nvmeq, &cmdinfo, sync_completion, timeout);
914 if (cmdid < 0) {
915 unlock_nvmeq(nvmeq);
b60503ba 916 return cmdid;
4f5099af 917 }
b60503ba
MW		 918 cmd->common.command_id = cmdid;
919
3c0cf138 920 set_current_state(TASK_KILLABLE);
4f5099af
KB		 921 ret = nvme_submit_cmd(nvmeq, cmd);
922 if (ret) {
923 free_cmdid(nvmeq, cmdid, NULL);
924 unlock_nvmeq(nvmeq);
925 set_current_state(TASK_RUNNING);
926 return ret;
927 }
928 unlock_nvmeq(nvmeq);
78f8d257 929 schedule_timeout(timeout);
b60503ba 930
3c0cf138 931 if (cmdinfo.status == -EINTR) {
4f5099af 932 nvmeq = lock_nvmeq(dev, q_idx);
a51afb54 933 if (nvmeq) {
4f5099af 934 nvme_abort_command(nvmeq, cmdid);
a51afb54
KB		 935 unlock_nvmeq(nvmeq);
936 }
3c0cf138
MW		 937 return -EINTR;
938 }
939
b60503ba
MW		 940 if (result)
941 *result = cmdinfo.result;
942
943 return cmdinfo.status;
944}
945
4d115420
KB		 946static int nvme_submit_async_cmd(struct nvme_queue *nvmeq,
947 struct nvme_command *cmd,
948 struct async_cmd_info *cmdinfo, unsigned timeout)
949{
950 int cmdid;
951
952 cmdid = alloc_cmdid_killable(nvmeq, cmdinfo, async_completion, timeout);
953 if (cmdid < 0)
954 return cmdid;
955 cmdinfo->status = -EINTR;
956 cmd->common.command_id = cmdid;
4f5099af 957 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 958}
959
5d0f6131 960int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
b60503ba
MW		 961 u32 *result)
962{
4f5099af
KB		 963 return nvme_submit_sync_cmd(dev, 0, cmd, result, ADMIN_TIMEOUT);
964}
965
966int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
967 u32 *result)
968{
969 return nvme_submit_sync_cmd(dev, smp_processor_id() + 1, cmd, result,
970 NVME_IO_TIMEOUT);
b60503ba
MW		 971}
972
4d115420
KB		 973static int nvme_submit_admin_cmd_async(struct nvme_dev *dev,
974 struct nvme_command *cmd, struct async_cmd_info *cmdinfo)
975{
5a92e700 976 return nvme_submit_async_cmd(raw_nvmeq(dev, 0), cmd, cmdinfo,
4d115420
KB		 977 ADMIN_TIMEOUT);
978}
979
b60503ba
MW		 980static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
981{
982 int status;
983 struct nvme_command c;
984
985 memset(&c, 0, sizeof(c));
986 c.delete_queue.opcode = opcode;
987 c.delete_queue.qid = cpu_to_le16(id);
988
989 status = nvme_submit_admin_cmd(dev, &c, NULL);
990 if (status)
991 return -EIO;
992 return 0;
993}
994
995static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
996 struct nvme_queue *nvmeq)
997{
998 int status;
999 struct nvme_command c;
1000 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1001
1002 memset(&c, 0, sizeof(c));
1003 c.create_cq.opcode = nvme_admin_create_cq;
1004 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1005 c.create_cq.cqid = cpu_to_le16(qid);
1006 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1007 c.create_cq.cq_flags = cpu_to_le16(flags);
1008 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1009
1010 status = nvme_submit_admin_cmd(dev, &c, NULL);
1011 if (status)
1012 return -EIO;
1013 return 0;
1014}
1015
1016static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1017 struct nvme_queue *nvmeq)
1018{
1019 int status;
1020 struct nvme_command c;
1021 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1022
1023 memset(&c, 0, sizeof(c));
1024 c.create_sq.opcode = nvme_admin_create_sq;
1025 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1026 c.create_sq.sqid = cpu_to_le16(qid);
1027 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1028 c.create_sq.sq_flags = cpu_to_le16(flags);
1029 c.create_sq.cqid = cpu_to_le16(qid);
1030
1031 status = nvme_submit_admin_cmd(dev, &c, NULL);
1032 if (status)
1033 return -EIO;
1034 return 0;
1035}
1036
1037static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1038{
1039 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1040}
1041
1042static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1043{
1044 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1045}
1046
5d0f6131 1047int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 1048 dma_addr_t dma_addr)
1049{
1050 struct nvme_command c;
1051
1052 memset(&c, 0, sizeof(c));
1053 c.identify.opcode = nvme_admin_identify;
1054 c.identify.nsid = cpu_to_le32(nsid);
1055 c.identify.prp1 = cpu_to_le64(dma_addr);
1056 c.identify.cns = cpu_to_le32(cns);
1057
1058 return nvme_submit_admin_cmd(dev, &c, NULL);
1059}
1060
5d0f6131 1061int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1062 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1063{
1064 struct nvme_command c;
1065
1066 memset(&c, 0, sizeof(c));
1067 c.features.opcode = nvme_admin_get_features;
a42cecce 1068 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1069 c.features.prp1 = cpu_to_le64(dma_addr);
1070 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1071
08df1e05 1072 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 1073}
1074
5d0f6131
VV		 1075int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1076 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1077{
1078 struct nvme_command c;
1079
1080 memset(&c, 0, sizeof(c));
1081 c.features.opcode = nvme_admin_set_features;
1082 c.features.prp1 = cpu_to_le64(dma_addr);
1083 c.features.fid = cpu_to_le32(fid);
1084 c.features.dword11 = cpu_to_le32(dword11);
1085
bc5fc7e4
MW		 1086 return nvme_submit_admin_cmd(dev, &c, result);
1087}
1088
c30341dc
KB		 1089/**
1090 * nvme_abort_cmd - Attempt aborting a command
1091 * @cmdid: Command id of a timed out IO
1092 * @queue: The queue with timed out IO
1093 *
1094 * Schedule controller reset if the command was already aborted once before and
1095 * still hasn't been returned to the driver, or if this is the admin queue.
1096 */
1097static void nvme_abort_cmd(int cmdid, struct nvme_queue *nvmeq)
1098{
1099 int a_cmdid;
1100 struct nvme_command cmd;
1101 struct nvme_dev *dev = nvmeq->dev;
1102 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
5a92e700 1103 struct nvme_queue *adminq;
c30341dc
KB		 1104
1105 if (!nvmeq->qid || info[cmdid].aborted) {
1106 if (work_busy(&dev->reset_work))
1107 return;
1108 list_del_init(&dev->node);
1109 dev_warn(&dev->pci_dev->dev,
1110 "I/O %d QID %d timeout, reset controller\n", cmdid,
1111 nvmeq->qid);
9ca97374 1112 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc
KB		 1113 queue_work(nvme_workq, &dev->reset_work);
1114 return;
1115 }
1116
1117 if (!dev->abort_limit)
1118 return;
1119
5a92e700
KB		 1120 adminq = rcu_dereference(dev->queues[0]);
1121 a_cmdid = alloc_cmdid(adminq, CMD_CTX_ABORT, special_completion,
c30341dc
KB		 1122 ADMIN_TIMEOUT);
1123 if (a_cmdid < 0)
1124 return;
1125
1126 memset(&cmd, 0, sizeof(cmd));
1127 cmd.abort.opcode = nvme_admin_abort_cmd;
1128 cmd.abort.cid = cmdid;
1129 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1130 cmd.abort.command_id = a_cmdid;
1131
1132 --dev->abort_limit;
1133 info[cmdid].aborted = 1;
1134 info[cmdid].timeout = jiffies + ADMIN_TIMEOUT;
1135
1136 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", cmdid,
1137 nvmeq->qid);
5a92e700 1138 nvme_submit_cmd(adminq, &cmd);
c30341dc
KB		 1139}
1140
a09115b2
MW		 1141/**
1142 * nvme_cancel_ios - Cancel outstanding I/Os
1143 * @queue: The queue to cancel I/Os on
1144 * @timeout: True to only cancel I/Os which have timed out
1145 */
1146static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1147{
1148 int depth = nvmeq->q_depth - 1;
1149 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1150 unsigned long now = jiffies;
1151 int cmdid;
1152
1153 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1154 void *ctx;
1155 nvme_completion_fn fn;
1156 static struct nvme_completion cqe = {
af2d9ca7 1157 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
a09115b2
MW		 1158 };
1159
1160 if (timeout && !time_after(now, info[cmdid].timeout))
1161 continue;
053ab702
KB		 1162 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1163 continue;
c30341dc
KB		 1164 if (timeout && nvmeq->dev->initialized) {
1165 nvme_abort_cmd(cmdid, nvmeq);
1166 continue;
1167 }
1168 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", cmdid,
1169 nvmeq->qid);
a09115b2 1170 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
edd10d33 1171 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1172 }
1173}
1174
5a92e700 1175static void nvme_free_queue(struct rcu_head *r)
9e866774 1176{
5a92e700
KB		 1177 struct nvme_queue *nvmeq = container_of(r, struct nvme_queue, r_head);
1178
22404274
KB		 1179 spin_lock_irq(&nvmeq->q_lock);
1180 while (bio_list_peek(&nvmeq->sq_cong)) {
1181 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1182 bio_endio(bio, -EIO);
1183 }
edd10d33
KB		 1184 while (!list_empty(&nvmeq->iod_bio)) {
1185 static struct nvme_completion cqe = {
1186 .status = cpu_to_le16(
1187 (NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1),
1188 };
1189 struct nvme_iod *iod = list_first_entry(&nvmeq->iod_bio,
1190 struct nvme_iod,
1191 node);
1192 list_del(&iod->node);
1193 bio_completion(nvmeq, iod, &cqe);
1194 }
22404274
KB		 1195 spin_unlock_irq(&nvmeq->q_lock);
1196
9e866774
MW		 1197 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1198 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1199 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1200 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
42f61420
KB		 1201 if (nvmeq->qid)
1202 free_cpumask_var(nvmeq->cpu_mask);
9e866774
MW		 1203 kfree(nvmeq);
1204}
1205
a1a5ef99 1206static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1207{
1208 int i;
1209
a1a5ef99 1210 for (i = dev->queue_count - 1; i >= lowest; i--) {
5a92e700
KB		 1211 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
1212 rcu_assign_pointer(dev->queues[i], NULL);
1213 call_rcu(&nvmeq->r_head, nvme_free_queue);
22404274 1214 dev->queue_count--;
22404274
KB		 1215 }
1216}
1217
4d115420
KB		 1218/**
1219 * nvme_suspend_queue - put queue into suspended state
1220 * @nvmeq - queue to suspend
1221 *
1222 * Returns 1 if already suspended, 0 otherwise.
1223 */
1224static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1225{
4d115420 1226 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1227
a09115b2 1228 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1229 if (nvmeq->q_suspended) {
1230 spin_unlock_irq(&nvmeq->q_lock);
4d115420 1231 return 1;
3295874b 1232 }
22404274 1233 nvmeq->q_suspended = 1;
42f61420 1234 nvmeq->dev->online_queues--;
a09115b2
MW		 1235 spin_unlock_irq(&nvmeq->q_lock);
1236
aba2080f
MW		 1237 irq_set_affinity_hint(vector, NULL);
1238 free_irq(vector, nvmeq);
b60503ba 1239
4d115420
KB		 1240 return 0;
1241}
b60503ba 1242
4d115420
KB		 1243static void nvme_clear_queue(struct nvme_queue *nvmeq)
1244{
22404274
KB		 1245 spin_lock_irq(&nvmeq->q_lock);
1246 nvme_process_cq(nvmeq);
1247 nvme_cancel_ios(nvmeq, false);
1248 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1249}
1250
4d115420
KB		 1251static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1252{
5a92e700 1253 struct nvme_queue *nvmeq = raw_nvmeq(dev, qid);
4d115420
KB		 1254
1255 if (!nvmeq)
1256 return;
1257 if (nvme_suspend_queue(nvmeq))
1258 return;
1259
0e53d180
KB		 1260 /* Don't tell the adapter to delete the admin queue.
1261 * Don't tell a removed adapter to delete IO queues. */
1262 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1263 adapter_delete_sq(dev, qid);
1264 adapter_delete_cq(dev, qid);
1265 }
4d115420 1266 nvme_clear_queue(nvmeq);
b60503ba
MW		 1267}
1268
1269static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1270 int depth, int vector)
1271{
1272 struct device *dmadev = &dev->pci_dev->dev;
22404274 1273 unsigned extra = nvme_queue_extra(depth);
b60503ba
MW		 1274 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1275 if (!nvmeq)
1276 return NULL;
1277
1278 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1279 &nvmeq->cq_dma_addr, GFP_KERNEL);
1280 if (!nvmeq->cqes)
1281 goto free_nvmeq;
1282 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1283
1284 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1285 &nvmeq->sq_dma_addr, GFP_KERNEL);
1286 if (!nvmeq->sq_cmds)
1287 goto free_cqdma;
1288
42f61420
KB		 1289 if (qid && !zalloc_cpumask_var(&nvmeq->cpu_mask, GFP_KERNEL))
1290 goto free_sqdma;
1291
b60503ba 1292 nvmeq->q_dmadev = dmadev;
091b6092 1293 nvmeq->dev = dev;
3193f07b
MW		 1294 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1295 dev->instance, qid);
b60503ba
MW		 1296 spin_lock_init(&nvmeq->q_lock);
1297 nvmeq->cq_head = 0;
82123460 1298 nvmeq->cq_phase = 1;
b60503ba 1299 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1300 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1301 bio_list_init(&nvmeq->sq_cong);
edd10d33 1302 INIT_LIST_HEAD(&nvmeq->iod_bio);
b80d5ccc 1303 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW		 1304 nvmeq->q_depth = depth;
1305 nvmeq->cq_vector = vector;
c30341dc 1306 nvmeq->qid = qid;
22404274
KB		 1307 nvmeq->q_suspended = 1;
1308 dev->queue_count++;
5a92e700 1309 rcu_assign_pointer(dev->queues[qid], nvmeq);
b60503ba
MW		 1310
1311 return nvmeq;
1312
42f61420
KB		 1313 free_sqdma:
1314 dma_free_coherent(dmadev, SQ_SIZE(depth), (void *)nvmeq->sq_cmds,
1315 nvmeq->sq_dma_addr);
b60503ba 1316 free_cqdma:
68b8eca5 1317 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1318 nvmeq->cq_dma_addr);
1319 free_nvmeq:
1320 kfree(nvmeq);
1321 return NULL;
1322}
1323
3001082c
MW		 1324static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1325 const char *name)
1326{
58ffacb5
MW		 1327 if (use_threaded_interrupts)
1328 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1329 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1330 name, nvmeq);
3001082c 1331 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1332 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1333}
1334
22404274 1335static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1336{
22404274
KB		 1337 struct nvme_dev *dev = nvmeq->dev;
1338 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
b60503ba 1339
22404274
KB		 1340 nvmeq->sq_tail = 0;
1341 nvmeq->cq_head = 0;
1342 nvmeq->cq_phase = 1;
b80d5ccc 1343 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274
KB		 1344 memset(nvmeq->cmdid_data, 0, extra);
1345 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1346 nvme_cancel_ios(nvmeq, false);
1347 nvmeq->q_suspended = 0;
42f61420 1348 dev->online_queues++;
22404274
KB		 1349}
1350
1351static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1352{
1353 struct nvme_dev *dev = nvmeq->dev;
1354 int result;
3f85d50b 1355
b60503ba
MW		 1356 result = adapter_alloc_cq(dev, qid, nvmeq);
1357 if (result < 0)
22404274 1358 return result;
b60503ba
MW		 1359
1360 result = adapter_alloc_sq(dev, qid, nvmeq);
1361 if (result < 0)
1362 goto release_cq;
1363
3193f07b 1364 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1365 if (result < 0)
1366 goto release_sq;
1367
0a8d44cb 1368 spin_lock_irq(&nvmeq->q_lock);
22404274 1369 nvme_init_queue(nvmeq, qid);
0a8d44cb 1370 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1371
1372 return result;
b60503ba
MW		 1373
1374 release_sq:
1375 adapter_delete_sq(dev, qid);
1376 release_cq:
1377 adapter_delete_cq(dev, qid);
22404274 1378 return result;
b60503ba
MW		 1379}
1380
ba47e386
MW		 1381static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1382{
1383 unsigned long timeout;
1384 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1385
1386 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1387
1388 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1389 msleep(100);
1390 if (fatal_signal_pending(current))
1391 return -EINTR;
1392 if (time_after(jiffies, timeout)) {
1393 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1394 "Device not ready; aborting %s\n", enabled ?
1395 "initialisation" : "reset");
ba47e386
MW		 1396 return -ENODEV;
1397 }
1398 }
1399
1400 return 0;
1401}
1402
1403/*
1404 * If the device has been passed off to us in an enabled state, just clear
1405 * the enabled bit. The spec says we should set the 'shutdown notification
1406 * bits', but doing so may cause the device to complete commands to the
1407 * admin queue ... and we don't know what memory that might be pointing at!
1408 */
1409static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1410{
44af146a
MW		 1411 u32 cc = readl(&dev->bar->cc);
1412
1413 if (cc & NVME_CC_ENABLE)
1414 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
ba47e386
MW		 1415 return nvme_wait_ready(dev, cap, false);
1416}
1417
1418static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1419{
1420 return nvme_wait_ready(dev, cap, true);
1421}
1422
1894d8f1
KB		 1423static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1424{
1425 unsigned long timeout;
1426 u32 cc;
1427
1428 cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
1429 writel(cc, &dev->bar->cc);
1430
1431 timeout = 2 * HZ + jiffies;
1432 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1433 NVME_CSTS_SHST_CMPLT) {
1434 msleep(100);
1435 if (fatal_signal_pending(current))
1436 return -EINTR;
1437 if (time_after(jiffies, timeout)) {
1438 dev_err(&dev->pci_dev->dev,
1439 "Device shutdown incomplete; abort shutdown\n");
1440 return -ENODEV;
1441 }
1442 }
1443
1444 return 0;
1445}
1446
8d85fce7 1447static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1448{
ba47e386 1449 int result;
b60503ba 1450 u32 aqa;
ba47e386 1451 u64 cap = readq(&dev->bar->cap);
b60503ba
MW		 1452 struct nvme_queue *nvmeq;
1453
ba47e386
MW		 1454 result = nvme_disable_ctrl(dev, cap);
1455 if (result < 0)
1456 return result;
b60503ba 1457
5a92e700 1458 nvmeq = raw_nvmeq(dev, 0);
cd638946
KB		 1459 if (!nvmeq) {
1460 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1461 if (!nvmeq)
1462 return -ENOMEM;
cd638946 1463 }
b60503ba
MW		 1464
1465 aqa = nvmeq->q_depth - 1;
1466 aqa |= aqa << 16;
1467
1468 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1469 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1470 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1471 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1472
1473 writel(aqa, &dev->bar->aqa);
1474 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1475 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1476 writel(dev->ctrl_config, &dev->bar->cc);
1477
ba47e386 1478 result = nvme_enable_ctrl(dev, cap);
025c557a 1479 if (result)
cd638946 1480 return result;
9e866774 1481
3193f07b 1482 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1483 if (result)
cd638946 1484 return result;
025c557a 1485
0a8d44cb 1486 spin_lock_irq(&nvmeq->q_lock);
22404274 1487 nvme_init_queue(nvmeq, 0);
0a8d44cb 1488 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1489 return result;
1490}
1491
5d0f6131 1492struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1493 unsigned long addr, unsigned length)
b60503ba 1494{
36c14ed9 1495 int i, err, count, nents, offset;
7fc3cdab
MW		 1496 struct scatterlist *sg;
1497 struct page **pages;
eca18b23 1498 struct nvme_iod *iod;
36c14ed9
MW		 1499
1500 if (addr & 3)
eca18b23 1501 return ERR_PTR(-EINVAL);
5460fc03 1502 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1503 return ERR_PTR(-EINVAL);
7fc3cdab 1504
36c14ed9 1505 offset = offset_in_page(addr);
7fc3cdab
MW		 1506 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1507 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1508 if (!pages)
1509 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1510
1511 err = get_user_pages_fast(addr, count, 1, pages);
1512 if (err < count) {
1513 count = err;
1514 err = -EFAULT;
1515 goto put_pages;
1516 }
7fc3cdab 1517
6808c5fb 1518 err = -ENOMEM;
eca18b23 1519 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
6808c5fb
S		 1520 if (!iod)
1521 goto put_pages;
1522
eca18b23 1523 sg = iod->sg;
36c14ed9 1524 sg_init_table(sg, count);
d0ba1e49
MW		 1525 for (i = 0; i < count; i++) {
1526 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1527 min_t(unsigned, length, PAGE_SIZE - offset),
1528 offset);
d0ba1e49
MW		 1529 length -= (PAGE_SIZE - offset);
1530 offset = 0;
7fc3cdab 1531 }
fe304c43 1532 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1533 iod->nents = count;
7fc3cdab 1534
7fc3cdab
MW		 1535 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1536 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1537 if (!nents)
eca18b23 1538 goto free_iod;
b60503ba 1539
7fc3cdab 1540 kfree(pages);
eca18b23 1541 return iod;
b60503ba 1542
eca18b23
MW		 1543 free_iod:
1544 kfree(iod);
7fc3cdab
MW		 1545 put_pages:
1546 for (i = 0; i < count; i++)
1547 put_page(pages[i]);
1548 kfree(pages);
eca18b23 1549 return ERR_PTR(err);
7fc3cdab 1550}
b60503ba 1551
5d0f6131 1552void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1553 struct nvme_iod *iod)
7fc3cdab 1554{
1c2ad9fa 1555 int i;
b60503ba 1556
1c2ad9fa
MW		 1557 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1558 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1559
1c2ad9fa
MW		 1560 for (i = 0; i < iod->nents; i++)
1561 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1562}
b60503ba 1563
a53295b6
MW		 1564static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1565{
1566 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1567 struct nvme_user_io io;
1568 struct nvme_command c;
f410c680
KB		 1569 unsigned length, meta_len;
1570 int status, i;
1571 struct nvme_iod *iod, *meta_iod = NULL;
1572 dma_addr_t meta_dma_addr;
1573 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1574
1575 if (copy_from_user(&io, uio, sizeof(io)))
1576 return -EFAULT;
6c7d4945 1577 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1578 meta_len = (io.nblocks + 1) * ns->ms;
1579
1580 if (meta_len && ((io.metadata & 3) || !io.metadata))
1581 return -EINVAL;
6c7d4945
MW		 1582
1583 switch (io.opcode) {
1584 case nvme_cmd_write:
1585 case nvme_cmd_read:
6bbf1acd 1586 case nvme_cmd_compare:
eca18b23 1587 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1588 break;
6c7d4945 1589 default:
6bbf1acd 1590 return -EINVAL;
6c7d4945
MW		 1591 }
1592
eca18b23
MW		 1593 if (IS_ERR(iod))
1594 return PTR_ERR(iod);
a53295b6
MW		 1595
1596 memset(&c, 0, sizeof(c));
1597 c.rw.opcode = io.opcode;
1598 c.rw.flags = io.flags;
6c7d4945 1599 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1600 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1601 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1602 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1603 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1604 c.rw.reftag = cpu_to_le32(io.reftag);
1605 c.rw.apptag = cpu_to_le16(io.apptag);
1606 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1607
1608 if (meta_len) {
1b56749e
KB		 1609 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1610 meta_len);
f410c680
KB		 1611 if (IS_ERR(meta_iod)) {
1612 status = PTR_ERR(meta_iod);
1613 meta_iod = NULL;
1614 goto unmap;
1615 }
1616
1617 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1618 &meta_dma_addr, GFP_KERNEL);
1619 if (!meta_mem) {
1620 status = -ENOMEM;
1621 goto unmap;
1622 }
1623
1624 if (io.opcode & 1) {
1625 int meta_offset = 0;
1626
1627 for (i = 0; i < meta_iod->nents; i++) {
1628 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1629 meta_iod->sg[i].offset;
1630 memcpy(meta_mem + meta_offset, meta,
1631 meta_iod->sg[i].length);
1632 kunmap_atomic(meta);
1633 meta_offset += meta_iod->sg[i].length;
1634 }
1635 }
1636
1637 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1638 }
1639
edd10d33
KB		 1640 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1641 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1642 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1643
b77954cb
MW		 1644 if (length != (io.nblocks + 1) << ns->lba_shift)
1645 status = -ENOMEM;
1646 else
4f5099af 1647 status = nvme_submit_io_cmd(dev, &c, NULL);
a53295b6 1648
f410c680
KB		 1649 if (meta_len) {
1650 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1651 int meta_offset = 0;
1652
1653 for (i = 0; i < meta_iod->nents; i++) {
1654 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1655 meta_iod->sg[i].offset;
1656 memcpy(meta, meta_mem + meta_offset,
1657 meta_iod->sg[i].length);
1658 kunmap_atomic(meta);
1659 meta_offset += meta_iod->sg[i].length;
1660 }
1661 }
1662
1663 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1664 meta_dma_addr);
1665 }
1666
1667 unmap:
1c2ad9fa 1668 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1669 nvme_free_iod(dev, iod);
f410c680
KB		 1670
1671 if (meta_iod) {
1672 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1673 nvme_free_iod(dev, meta_iod);
1674 }
1675
a53295b6
MW		 1676 return status;
1677}
1678
50af8bae 1679static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1680 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1681{
6bbf1acd 1682 struct nvme_admin_cmd cmd;
6ee44cdc 1683 struct nvme_command c;
eca18b23 1684 int status, length;
c7d36ab8 1685 struct nvme_iod *uninitialized_var(iod);
94f370ca 1686 unsigned timeout;
6ee44cdc 1687
6bbf1acd
MW		 1688 if (!capable(CAP_SYS_ADMIN))
1689 return -EACCES;
1690 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1691 return -EFAULT;
6ee44cdc
MW		 1692
1693 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1694 c.common.opcode = cmd.opcode;
1695 c.common.flags = cmd.flags;
1696 c.common.nsid = cpu_to_le32(cmd.nsid);
1697 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1698 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1699 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1700 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1701 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1702 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1703 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1704 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1705
1706 length = cmd.data_len;
1707 if (cmd.data_len) {
49742188
MW		 1708 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1709 length);
eca18b23
MW		 1710 if (IS_ERR(iod))
1711 return PTR_ERR(iod);
edd10d33
KB		 1712 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1713 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1714 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1715 }
1716
94f370ca
KB		 1717 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1718 ADMIN_TIMEOUT;
6bbf1acd 1719 if (length != cmd.data_len)
b77954cb
MW		 1720 status = -ENOMEM;
1721 else
4f5099af 1722 status = nvme_submit_sync_cmd(dev, 0, &c, &cmd.result, timeout);
eca18b23 1723
6bbf1acd 1724 if (cmd.data_len) {
1c2ad9fa 1725 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1726 nvme_free_iod(dev, iod);
6bbf1acd 1727 }
f4f117f6 1728
cf90bc48 1729 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1730 sizeof(cmd.result)))
1731 status = -EFAULT;
1732
6ee44cdc
MW		 1733 return status;
1734}
1735
b60503ba
MW		 1736static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1737 unsigned long arg)
1738{
1739 struct nvme_ns *ns = bdev->bd_disk->private_data;
1740
1741 switch (cmd) {
6bbf1acd 1742 case NVME_IOCTL_ID:
c3bfe717 1743 force_successful_syscall_return();
6bbf1acd
MW		 1744 return ns->ns_id;
1745 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1746 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW		 1747 case NVME_IOCTL_SUBMIT_IO:
1748 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1749 case SG_GET_VERSION_NUM:
1750 return nvme_sg_get_version_num((void __user *)arg);
1751 case SG_IO:
1752 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1753 default:
1754 return -ENOTTY;
1755 }
1756}
1757
320a3827
KB		 1758#ifdef CONFIG_COMPAT
1759static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1760 unsigned int cmd, unsigned long arg)
1761{
1762 struct nvme_ns *ns = bdev->bd_disk->private_data;
1763
1764 switch (cmd) {
1765 case SG_IO:
1766 return nvme_sg_io32(ns, arg);
1767 }
1768 return nvme_ioctl(bdev, mode, cmd, arg);
1769}
1770#else
1771#define nvme_compat_ioctl NULL
1772#endif
1773
9ac27090
KB		 1774static int nvme_open(struct block_device *bdev, fmode_t mode)
1775{
1776 struct nvme_ns *ns = bdev->bd_disk->private_data;
1777 struct nvme_dev *dev = ns->dev;
1778
1779 kref_get(&dev->kref);
1780 return 0;
1781}
1782
1783static void nvme_free_dev(struct kref *kref);
1784
1785static void nvme_release(struct gendisk *disk, fmode_t mode)
1786{
1787 struct nvme_ns *ns = disk->private_data;
1788 struct nvme_dev *dev = ns->dev;
1789
1790 kref_put(&dev->kref, nvme_free_dev);
1791}
1792
4cc09e2d
KB		 1793static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1794{
1795 /* some standard values */
1796 geo->heads = 1 << 6;
1797 geo->sectors = 1 << 5;
1798 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1799 return 0;
1800}
1801
b60503ba
MW		 1802static const struct block_device_operations nvme_fops = {
1803 .owner = THIS_MODULE,
1804 .ioctl = nvme_ioctl,
320a3827 1805 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1806 .open = nvme_open,
1807 .release = nvme_release,
4cc09e2d 1808 .getgeo = nvme_getgeo,
b60503ba
MW		 1809};
1810
edd10d33
KB		 1811static void nvme_resubmit_iods(struct nvme_queue *nvmeq)
1812{
1813 struct nvme_iod *iod, *next;
1814
1815 list_for_each_entry_safe(iod, next, &nvmeq->iod_bio, node) {
1816 if (unlikely(nvme_submit_iod(nvmeq, iod)))
1817 break;
1818 list_del(&iod->node);
1819 if (bio_list_empty(&nvmeq->sq_cong) &&
1820 list_empty(&nvmeq->iod_bio))
1821 remove_wait_queue(&nvmeq->sq_full,
1822 &nvmeq->sq_cong_wait);
1823 }
1824}
1825
1fa6aead
MW		 1826static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1827{
1828 while (bio_list_peek(&nvmeq->sq_cong)) {
1829 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1830 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
427e9708 1831
edd10d33
KB		 1832 if (bio_list_empty(&nvmeq->sq_cong) &&
1833 list_empty(&nvmeq->iod_bio))
427e9708
KB		 1834 remove_wait_queue(&nvmeq->sq_full,
1835 &nvmeq->sq_cong_wait);
1fa6aead 1836 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
edd10d33 1837 if (!waitqueue_active(&nvmeq->sq_full))
427e9708
KB		 1838 add_wait_queue(&nvmeq->sq_full,
1839 &nvmeq->sq_cong_wait);
1fa6aead
MW		 1840 bio_list_add_head(&nvmeq->sq_cong, bio);
1841 break;
1842 }
1843 }
1844}
1845
1846static int nvme_kthread(void *data)
1847{
d4b4ff8e 1848 struct nvme_dev *dev, *next;
1fa6aead
MW		 1849
1850 while (!kthread_should_stop()) {
564a232c 1851 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1852 spin_lock(&dev_list_lock);
d4b4ff8e 1853 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1854 int i;
d4b4ff8e
KB		 1855 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1856 dev->initialized) {
1857 if (work_busy(&dev->reset_work))
1858 continue;
1859 list_del_init(&dev->node);
1860 dev_warn(&dev->pci_dev->dev,
1861 "Failed status, reset controller\n");
9ca97374 1862 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 1863 queue_work(nvme_workq, &dev->reset_work);
1864 continue;
1865 }
5a92e700 1866 rcu_read_lock();
1fa6aead 1867 for (i = 0; i < dev->queue_count; i++) {
5a92e700
KB		 1868 struct nvme_queue *nvmeq =
1869 rcu_dereference(dev->queues[i]);
740216fc
MW		 1870 if (!nvmeq)
1871 continue;
1fa6aead 1872 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1873 if (nvmeq->q_suspended)
1874 goto unlock;
bc57a0f7 1875 nvme_process_cq(nvmeq);
a09115b2 1876 nvme_cancel_ios(nvmeq, true);
1fa6aead 1877 nvme_resubmit_bios(nvmeq);
edd10d33 1878 nvme_resubmit_iods(nvmeq);
22404274 1879 unlock:
1fa6aead
MW		 1880 spin_unlock_irq(&nvmeq->q_lock);
1881 }
5a92e700 1882 rcu_read_unlock();
1fa6aead
MW		 1883 }
1884 spin_unlock(&dev_list_lock);
acb7aa0d 1885 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1886 }
1887 return 0;
1888}
1889
0e5e4f0e
KB		 1890static void nvme_config_discard(struct nvme_ns *ns)
1891{
1892 u32 logical_block_size = queue_logical_block_size(ns->queue);
1893 ns->queue->limits.discard_zeroes_data = 0;
1894 ns->queue->limits.discard_alignment = logical_block_size;
1895 ns->queue->limits.discard_granularity = logical_block_size;
1896 ns->queue->limits.max_discard_sectors = 0xffffffff;
1897 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1898}
1899
c3bfe717 1900static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1901 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1902{
1903 struct nvme_ns *ns;
1904 struct gendisk *disk;
1905 int lbaf;
1906
1907 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1908 return NULL;
1909
1910 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1911 if (!ns)
1912 return NULL;
1913 ns->queue = blk_alloc_queue(GFP_KERNEL);
1914 if (!ns->queue)
1915 goto out_free_ns;
4eeb9215
MW		 1916 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1917 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1918 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b277da0a 1919 queue_flag_clear_unlocked(QUEUE_FLAG_ADD_RANDOM, ns->queue);
b60503ba
MW		 1920 blk_queue_make_request(ns->queue, nvme_make_request);
1921 ns->dev = dev;
1922 ns->queue->queuedata = ns;
1923
469071a3 1924 disk = alloc_disk(0);
b60503ba
MW		 1925 if (!disk)
1926 goto out_free_queue;
5aff9382 1927 ns->ns_id = nsid;
b60503ba
MW		 1928 ns->disk = disk;
1929 lbaf = id->flbas & 0xf;
1930 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1931 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1932 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1933 if (dev->max_hw_sectors)
1934 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a7d2ce28
KB		 1935 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
1936 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 1937
1938 disk->major = nvme_major;
469071a3 1939 disk->first_minor = 0;
b60503ba
MW		 1940 disk->fops = &nvme_fops;
1941 disk->private_data = ns;
1942 disk->queue = ns->queue;
388f037f 1943 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1944 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1945 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1946 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1947
0e5e4f0e
KB		 1948 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1949 nvme_config_discard(ns);
1950
b60503ba
MW		 1951 return ns;
1952
1953 out_free_queue:
1954 blk_cleanup_queue(ns->queue);
1955 out_free_ns:
1956 kfree(ns);
1957 return NULL;
1958}
1959
42f61420
KB		 1960static int nvme_find_closest_node(int node)
1961{
1962 int n, val, min_val = INT_MAX, best_node = node;
1963
1964 for_each_online_node(n) {
1965 if (n == node)
1966 continue;
1967 val = node_distance(node, n);
1968 if (val < min_val) {
1969 min_val = val;
1970 best_node = n;
1971 }
1972 }
1973 return best_node;
1974}
1975
1976static void nvme_set_queue_cpus(cpumask_t *qmask, struct nvme_queue *nvmeq,
1977 int count)
1978{
1979 int cpu;
1980 for_each_cpu(cpu, qmask) {
1981 if (cpumask_weight(nvmeq->cpu_mask) >= count)
1982 break;
1983 if (!cpumask_test_and_set_cpu(cpu, nvmeq->cpu_mask))
1984 *per_cpu_ptr(nvmeq->dev->io_queue, cpu) = nvmeq->qid;
1985 }
1986}
1987
1988static void nvme_add_cpus(cpumask_t *mask, const cpumask_t *unassigned_cpus,
1989 const cpumask_t *new_mask, struct nvme_queue *nvmeq, int cpus_per_queue)
1990{
1991 int next_cpu;
1992 for_each_cpu(next_cpu, new_mask) {
1993 cpumask_or(mask, mask, get_cpu_mask(next_cpu));
1994 cpumask_or(mask, mask, topology_thread_cpumask(next_cpu));
1995 cpumask_and(mask, mask, unassigned_cpus);
1996 nvme_set_queue_cpus(mask, nvmeq, cpus_per_queue);
1997 }
1998}
1999
2000static void nvme_create_io_queues(struct nvme_dev *dev)
2001{
2002 unsigned i, max;
2003
2004 max = min(dev->max_qid, num_online_cpus());
2005 for (i = dev->queue_count; i <= max; i++)
2006 if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1))
2007 break;
2008
2009 max = min(dev->queue_count - 1, num_online_cpus());
2010 for (i = dev->online_queues; i <= max; i++)
2011 if (nvme_create_queue(raw_nvmeq(dev, i), i))
2012 break;
2013}
2014
2015/*
2016 * If there are fewer queues than online cpus, this will try to optimally
2017 * assign a queue to multiple cpus by grouping cpus that are "close" together:
2018 * thread siblings, core, socket, closest node, then whatever else is
2019 * available.
2020 */
2021static void nvme_assign_io_queues(struct nvme_dev *dev)
2022{
2023 unsigned cpu, cpus_per_queue, queues, remainder, i;
2024 cpumask_var_t unassigned_cpus;
2025
2026 nvme_create_io_queues(dev);
2027
2028 queues = min(dev->online_queues - 1, num_online_cpus());
2029 if (!queues)
2030 return;
2031
2032 cpus_per_queue = num_online_cpus() / queues;
2033 remainder = queues - (num_online_cpus() - queues * cpus_per_queue);
2034
2035 if (!alloc_cpumask_var(&unassigned_cpus, GFP_KERNEL))
2036 return;
2037
2038 cpumask_copy(unassigned_cpus, cpu_online_mask);
2039 cpu = cpumask_first(unassigned_cpus);
2040 for (i = 1; i <= queues; i++) {
2041 struct nvme_queue *nvmeq = lock_nvmeq(dev, i);
2042 cpumask_t mask;
2043
2044 cpumask_clear(nvmeq->cpu_mask);
2045 if (!cpumask_weight(unassigned_cpus)) {
2046 unlock_nvmeq(nvmeq);
2047 break;
2048 }
2049
2050 mask = *get_cpu_mask(cpu);
2051 nvme_set_queue_cpus(&mask, nvmeq, cpus_per_queue);
2052 if (cpus_weight(mask) < cpus_per_queue)
2053 nvme_add_cpus(&mask, unassigned_cpus,
2054 topology_thread_cpumask(cpu),
2055 nvmeq, cpus_per_queue);
2056 if (cpus_weight(mask) < cpus_per_queue)
2057 nvme_add_cpus(&mask, unassigned_cpus,
2058 topology_core_cpumask(cpu),
2059 nvmeq, cpus_per_queue);
2060 if (cpus_weight(mask) < cpus_per_queue)
2061 nvme_add_cpus(&mask, unassigned_cpus,
2062 cpumask_of_node(cpu_to_node(cpu)),
2063 nvmeq, cpus_per_queue);
2064 if (cpus_weight(mask) < cpus_per_queue)
2065 nvme_add_cpus(&mask, unassigned_cpus,
2066 cpumask_of_node(
2067 nvme_find_closest_node(
2068 cpu_to_node(cpu))),
2069 nvmeq, cpus_per_queue);
2070 if (cpus_weight(mask) < cpus_per_queue)
2071 nvme_add_cpus(&mask, unassigned_cpus,
2072 unassigned_cpus,
2073 nvmeq, cpus_per_queue);
2074
2075 WARN(cpumask_weight(nvmeq->cpu_mask) != cpus_per_queue,
2076 "nvme%d qid:%d mis-matched queue-to-cpu assignment\n",
2077 dev->instance, i);
2078
2079 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2080 nvmeq->cpu_mask);
2081 cpumask_andnot(unassigned_cpus, unassigned_cpus,
2082 nvmeq->cpu_mask);
2083 cpu = cpumask_next(cpu, unassigned_cpus);
2084 if (remainder && !--remainder)
2085 cpus_per_queue++;
2086 unlock_nvmeq(nvmeq);
2087 }
2088 WARN(cpumask_weight(unassigned_cpus), "nvme%d unassigned online cpus\n",
2089 dev->instance);
2090 i = 0;
2091 cpumask_andnot(unassigned_cpus, cpu_possible_mask, cpu_online_mask);
2092 for_each_cpu(cpu, unassigned_cpus)
2093 *per_cpu_ptr(dev->io_queue, cpu) = (i++ % queues) + 1;
2094 free_cpumask_var(unassigned_cpus);
2095}
2096
b3b06812 2097static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2098{
2099 int status;
2100 u32 result;
b3b06812 2101 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2102
df348139 2103 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2104 &result);
27e8166c
MW		 2105 if (status < 0)
2106 return status;
2107 if (status > 0) {
2108 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2109 status);
2110 return -EBUSY;
2111 }
b60503ba
MW		 2112 return min(result & 0xffff, result >> 16) + 1;
2113}
2114
9d713c2b
KB		 2115static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2116{
b80d5ccc 2117 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2118}
2119
f3db22fe
KB		 2120static void nvme_cpu_workfn(struct work_struct *work)
2121{
2122 struct nvme_dev *dev = container_of(work, struct nvme_dev, cpu_work);
2123 if (dev->initialized)
2124 nvme_assign_io_queues(dev);
2125}
2126
33b1e95c
KB		 2127static int nvme_cpu_notify(struct notifier_block *self,
2128 unsigned long action, void *hcpu)
2129{
f3db22fe
KB		 2130 struct nvme_dev *dev;
2131
33b1e95c
KB		 2132 switch (action) {
2133 case CPU_ONLINE:
2134 case CPU_DEAD:
f3db22fe
KB		 2135 spin_lock(&dev_list_lock);
2136 list_for_each_entry(dev, &dev_list, node)
2137 schedule_work(&dev->cpu_work);
2138 spin_unlock(&dev_list_lock);
33b1e95c
KB		 2139 break;
2140 }
2141 return NOTIFY_OK;
2142}
2143
8d85fce7 2144static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2145{
5a92e700 2146 struct nvme_queue *adminq = raw_nvmeq(dev, 0);
fa08a396 2147 struct pci_dev *pdev = dev->pci_dev;
42f61420 2148 int result, i, vecs, nr_io_queues, size;
b60503ba 2149
42f61420 2150 nr_io_queues = num_possible_cpus();
b348b7d5 2151 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW		 2152 if (result < 0)
2153 return result;
b348b7d5
MW		 2154 if (result < nr_io_queues)
2155 nr_io_queues = result;
b60503ba 2156
9d713c2b
KB		 2157 size = db_bar_size(dev, nr_io_queues);
2158 if (size > 8192) {
f1938f6e 2159 iounmap(dev->bar);
9d713c2b
KB		 2160 do {
2161 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2162 if (dev->bar)
2163 break;
2164 if (!--nr_io_queues)
2165 return -ENOMEM;
2166 size = db_bar_size(dev, nr_io_queues);
2167 } while (1);
f1938f6e 2168 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2169 adminq->q_db = dev->dbs;
f1938f6e
MW		 2170 }
2171
9d713c2b 2172 /* Deregister the admin queue's interrupt */
3193f07b 2173 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2174
be577fab 2175 for (i = 0; i < nr_io_queues; i++)
1b23484b 2176 dev->entry[i].entry = i;
be577fab
AG		 2177 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2178 if (vecs < 0) {
2179 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2180 if (vecs < 0) {
2181 vecs = 1;
2182 } else {
2183 for (i = 0; i < vecs; i++)
2184 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2185 }
2186 }
2187
063a8096
MW		 2188 /*
2189 * Should investigate if there's a performance win from allocating
2190 * more queues than interrupt vectors; it might allow the submission
2191 * path to scale better, even if the receive path is limited by the
2192 * number of interrupts.
2193 */
2194 nr_io_queues = vecs;
42f61420 2195 dev->max_qid = nr_io_queues;
063a8096 2196
3193f07b 2197 result = queue_request_irq(dev, adminq, adminq->irqname);
9d713c2b 2198 if (result) {
3193f07b 2199 adminq->q_suspended = 1;
22404274 2200 goto free_queues;
9d713c2b 2201 }
1b23484b 2202
cd638946 2203 /* Free previously allocated queues that are no longer usable */
42f61420
KB		 2204 nvme_free_queues(dev, nr_io_queues + 1);
2205 nvme_assign_io_queues(dev);
9ecdc946 2206
22404274 2207 return 0;
b60503ba 2208
22404274 2209 free_queues:
a1a5ef99 2210 nvme_free_queues(dev, 1);
22404274 2211 return result;
b60503ba
MW		 2212}
2213
422ef0c7
MW		 2214/*
2215 * Return: error value if an error occurred setting up the queues or calling
2216 * Identify Device. 0 if these succeeded, even if adding some of the
2217 * namespaces failed. At the moment, these failures are silent. TBD which
2218 * failures should be reported.
2219 */
8d85fce7 2220static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2221{
68608c26 2222 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2223 int res;
2224 unsigned nn, i;
cbb6218f 2225 struct nvme_ns *ns;
51814232 2226 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2227 struct nvme_id_ns *id_ns;
2228 void *mem;
b60503ba 2229 dma_addr_t dma_addr;
159b67d7 2230 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2231
68608c26 2232 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2233 if (!mem)
2234 return -ENOMEM;
b60503ba 2235
bc5fc7e4 2236 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2237 if (res) {
27e8166c 2238 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
b60503ba 2239 res = -EIO;
cbb6218f 2240 goto out;
b60503ba
MW		 2241 }
2242
bc5fc7e4 2243 ctrl = mem;
51814232 2244 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2245 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2246 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2247 dev->vwc = ctrl->vwc;
51814232
MW		 2248 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2249 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2250 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2251 if (ctrl->mdts)
8fc23e03 2252 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26
MW		 2253 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2254 (pdev->device == 0x0953) && ctrl->vs[3])
159b67d7 2255 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
b60503ba 2256
bc5fc7e4 2257 id_ns = mem;
2b2c1896 2258 for (i = 1; i <= nn; i++) {
bc5fc7e4 2259 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2260 if (res)
2261 continue;
2262
bc5fc7e4 2263 if (id_ns->ncap == 0)
b60503ba
MW		 2264 continue;
2265
bc5fc7e4 2266 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2267 dma_addr + 4096, NULL);
b60503ba 2268 if (res)
12209036 2269 memset(mem + 4096, 0, 4096);
b60503ba 2270
bc5fc7e4 2271 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2272 if (ns)
2273 list_add_tail(&ns->list, &dev->namespaces);
2274 }
2275 list_for_each_entry(ns, &dev->namespaces, list)
2276 add_disk(ns->disk);
422ef0c7 2277 res = 0;
b60503ba 2278
bc5fc7e4 2279 out:
684f5c20 2280 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2281 return res;
2282}
2283
0877cb0d
KB		 2284static int nvme_dev_map(struct nvme_dev *dev)
2285{
42f61420 2286 u64 cap;
0877cb0d
KB		 2287 int bars, result = -ENOMEM;
2288 struct pci_dev *pdev = dev->pci_dev;
2289
2290 if (pci_enable_device_mem(pdev))
2291 return result;
2292
2293 dev->entry[0].vector = pdev->irq;
2294 pci_set_master(pdev);
2295 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2296 if (pci_request_selected_regions(pdev, bars, "nvme"))
2297 goto disable_pci;
2298
052d0efa
RK		 2299 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2300 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2301 goto disable;
0877cb0d 2302
0877cb0d
KB		 2303 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2304 if (!dev->bar)
2305 goto disable;
0e53d180
KB		 2306 if (readl(&dev->bar->csts) == -1) {
2307 result = -ENODEV;
2308 goto unmap;
2309 }
42f61420
KB		 2310 cap = readq(&dev->bar->cap);
2311 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2312 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2313 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2314
2315 return 0;
2316
0e53d180
KB		 2317 unmap:
2318 iounmap(dev->bar);
2319 dev->bar = NULL;
0877cb0d
KB		 2320 disable:
2321 pci_release_regions(pdev);
2322 disable_pci:
2323 pci_disable_device(pdev);
2324 return result;
2325}
2326
2327static void nvme_dev_unmap(struct nvme_dev *dev)
2328{
2329 if (dev->pci_dev->msi_enabled)
2330 pci_disable_msi(dev->pci_dev);
2331 else if (dev->pci_dev->msix_enabled)
2332 pci_disable_msix(dev->pci_dev);
2333
2334 if (dev->bar) {
2335 iounmap(dev->bar);
2336 dev->bar = NULL;
9a6b9458 2337 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2338 }
2339
0877cb0d
KB		 2340 if (pci_is_enabled(dev->pci_dev))
2341 pci_disable_device(dev->pci_dev);
2342}
2343
4d115420
KB		 2344struct nvme_delq_ctx {
2345 struct task_struct *waiter;
2346 struct kthread_worker *worker;
2347 atomic_t refcount;
2348};
2349
2350static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2351{
2352 dq->waiter = current;
2353 mb();
2354
2355 for (;;) {
2356 set_current_state(TASK_KILLABLE);
2357 if (!atomic_read(&dq->refcount))
2358 break;
2359 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2360 fatal_signal_pending(current)) {
2361 set_current_state(TASK_RUNNING);
2362
2363 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2364 nvme_disable_queue(dev, 0);
2365
2366 send_sig(SIGKILL, dq->worker->task, 1);
2367 flush_kthread_worker(dq->worker);
2368 return;
2369 }
2370 }
2371 set_current_state(TASK_RUNNING);
2372}
2373
2374static void nvme_put_dq(struct nvme_delq_ctx *dq)
2375{
2376 atomic_dec(&dq->refcount);
2377 if (dq->waiter)
2378 wake_up_process(dq->waiter);
2379}
2380
2381static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2382{
2383 atomic_inc(&dq->refcount);
2384 return dq;
2385}
2386
2387static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2388{
2389 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2390
2391 nvme_clear_queue(nvmeq);
2392 nvme_put_dq(dq);
2393}
2394
2395static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2396 kthread_work_func_t fn)
2397{
2398 struct nvme_command c;
2399
2400 memset(&c, 0, sizeof(c));
2401 c.delete_queue.opcode = opcode;
2402 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2403
2404 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2405 return nvme_submit_admin_cmd_async(nvmeq->dev, &c, &nvmeq->cmdinfo);
2406}
2407
2408static void nvme_del_cq_work_handler(struct kthread_work *work)
2409{
2410 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2411 cmdinfo.work);
2412 nvme_del_queue_end(nvmeq);
2413}
2414
2415static int nvme_delete_cq(struct nvme_queue *nvmeq)
2416{
2417 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2418 nvme_del_cq_work_handler);
2419}
2420
2421static void nvme_del_sq_work_handler(struct kthread_work *work)
2422{
2423 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2424 cmdinfo.work);
2425 int status = nvmeq->cmdinfo.status;
2426
2427 if (!status)
2428 status = nvme_delete_cq(nvmeq);
2429 if (status)
2430 nvme_del_queue_end(nvmeq);
2431}
2432
2433static int nvme_delete_sq(struct nvme_queue *nvmeq)
2434{
2435 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2436 nvme_del_sq_work_handler);
2437}
2438
2439static void nvme_del_queue_start(struct kthread_work *work)
2440{
2441 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2442 cmdinfo.work);
2443 allow_signal(SIGKILL);
2444 if (nvme_delete_sq(nvmeq))
2445 nvme_del_queue_end(nvmeq);
2446}
2447
2448static void nvme_disable_io_queues(struct nvme_dev *dev)
2449{
2450 int i;
2451 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2452 struct nvme_delq_ctx dq;
2453 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2454 &worker, "nvme%d", dev->instance);
2455
2456 if (IS_ERR(kworker_task)) {
2457 dev_err(&dev->pci_dev->dev,
2458 "Failed to create queue del task\n");
2459 for (i = dev->queue_count - 1; i > 0; i--)
2460 nvme_disable_queue(dev, i);
2461 return;
2462 }
2463
2464 dq.waiter = NULL;
2465 atomic_set(&dq.refcount, 0);
2466 dq.worker = &worker;
2467 for (i = dev->queue_count - 1; i > 0; i--) {
5a92e700 2468 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2469
2470 if (nvme_suspend_queue(nvmeq))
2471 continue;
2472 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2473 nvmeq->cmdinfo.worker = dq.worker;
2474 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2475 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2476 }
2477 nvme_wait_dq(&dq, dev);
2478 kthread_stop(kworker_task);
2479}
2480
b9afca3e
DM		 2481/*
2482* Remove the node from the device list and check
2483* for whether or not we need to stop the nvme_thread.
2484*/
2485static void nvme_dev_list_remove(struct nvme_dev *dev)
2486{
2487 struct task_struct *tmp = NULL;
2488
2489 spin_lock(&dev_list_lock);
2490 list_del_init(&dev->node);
2491 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2492 tmp = nvme_thread;
2493 nvme_thread = NULL;
2494 }
2495 spin_unlock(&dev_list_lock);
2496
2497 if (tmp)
2498 kthread_stop(tmp);
2499}
2500
f0b50732 2501static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2502{
22404274
KB		 2503 int i;
2504
d4b4ff8e 2505 dev->initialized = 0;
b9afca3e 2506 nvme_dev_list_remove(dev);
1fa6aead 2507
4d115420
KB		 2508 if (!dev->bar || (dev->bar && readl(&dev->bar->csts) == -1)) {
2509 for (i = dev->queue_count - 1; i >= 0; i--) {
5a92e700 2510 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2511 nvme_suspend_queue(nvmeq);
2512 nvme_clear_queue(nvmeq);
2513 }
2514 } else {
2515 nvme_disable_io_queues(dev);
1894d8f1 2516 nvme_shutdown_ctrl(dev);
4d115420
KB		 2517 nvme_disable_queue(dev, 0);
2518 }
f0b50732
KB		 2519 nvme_dev_unmap(dev);
2520}
2521
2522static void nvme_dev_remove(struct nvme_dev *dev)
2523{
9ac27090 2524 struct nvme_ns *ns;
f0b50732 2525
9ac27090
KB		 2526 list_for_each_entry(ns, &dev->namespaces, list) {
2527 if (ns->disk->flags & GENHD_FL_UP)
2528 del_gendisk(ns->disk);
2529 if (!blk_queue_dying(ns->queue))
2530 blk_cleanup_queue(ns->queue);
b60503ba 2531 }
b60503ba
MW		 2532}
2533
091b6092
MW		 2534static int nvme_setup_prp_pools(struct nvme_dev *dev)
2535{
2536 struct device *dmadev = &dev->pci_dev->dev;
2537 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2538 PAGE_SIZE, PAGE_SIZE, 0);
2539 if (!dev->prp_page_pool)
2540 return -ENOMEM;
2541
99802a7a
MW		 2542 /* Optimisation for I/Os between 4k and 128k */
2543 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2544 256, 256, 0);
2545 if (!dev->prp_small_pool) {
2546 dma_pool_destroy(dev->prp_page_pool);
2547 return -ENOMEM;
2548 }
091b6092
MW		 2549 return 0;
2550}
2551
2552static void nvme_release_prp_pools(struct nvme_dev *dev)
2553{
2554 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2555 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2556}
2557
cd58ad7d
QSA		 2558static DEFINE_IDA(nvme_instance_ida);
2559
2560static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2561{
cd58ad7d
QSA		 2562 int instance, error;
2563
2564 do {
2565 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2566 return -ENODEV;
2567
2568 spin_lock(&dev_list_lock);
2569 error = ida_get_new(&nvme_instance_ida, &instance);
2570 spin_unlock(&dev_list_lock);
2571 } while (error == -EAGAIN);
2572
2573 if (error)
2574 return -ENODEV;
2575
2576 dev->instance = instance;
2577 return 0;
b60503ba
MW		 2578}
2579
2580static void nvme_release_instance(struct nvme_dev *dev)
2581{
cd58ad7d
QSA		 2582 spin_lock(&dev_list_lock);
2583 ida_remove(&nvme_instance_ida, dev->instance);
2584 spin_unlock(&dev_list_lock);
b60503ba
MW		 2585}
2586
9ac27090
KB		 2587static void nvme_free_namespaces(struct nvme_dev *dev)
2588{
2589 struct nvme_ns *ns, *next;
2590
2591 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2592 list_del(&ns->list);
2593 put_disk(ns->disk);
2594 kfree(ns);
2595 }
2596}
2597
5e82e952
KB		 2598static void nvme_free_dev(struct kref *kref)
2599{
2600 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090
KB		 2601
2602 nvme_free_namespaces(dev);
42f61420 2603 free_percpu(dev->io_queue);
5e82e952
KB		 2604 kfree(dev->queues);
2605 kfree(dev->entry);
2606 kfree(dev);
2607}
2608
2609static int nvme_dev_open(struct inode *inode, struct file *f)
2610{
2611 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2612 miscdev);
2613 kref_get(&dev->kref);
2614 f->private_data = dev;
2615 return 0;
2616}
2617
2618static int nvme_dev_release(struct inode *inode, struct file *f)
2619{
2620 struct nvme_dev *dev = f->private_data;
2621 kref_put(&dev->kref, nvme_free_dev);
2622 return 0;
2623}
2624
2625static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2626{
2627 struct nvme_dev *dev = f->private_data;
2628 switch (cmd) {
2629 case NVME_IOCTL_ADMIN_CMD:
2630 return nvme_user_admin_cmd(dev, (void __user *)arg);
2631 default:
2632 return -ENOTTY;
2633 }
2634}
2635
2636static const struct file_operations nvme_dev_fops = {
2637 .owner = THIS_MODULE,
2638 .open = nvme_dev_open,
2639 .release = nvme_dev_release,
2640 .unlocked_ioctl = nvme_dev_ioctl,
2641 .compat_ioctl = nvme_dev_ioctl,
2642};
2643
f0b50732
KB		 2644static int nvme_dev_start(struct nvme_dev *dev)
2645{
2646 int result;
b9afca3e 2647 bool start_thread = false;
f0b50732
KB		 2648
2649 result = nvme_dev_map(dev);
2650 if (result)
2651 return result;
2652
2653 result = nvme_configure_admin_queue(dev);
2654 if (result)
2655 goto unmap;
2656
2657 spin_lock(&dev_list_lock);
b9afca3e
DM		 2658 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2659 start_thread = true;
2660 nvme_thread = NULL;
2661 }
f0b50732
KB		 2662 list_add(&dev->node, &dev_list);
2663 spin_unlock(&dev_list_lock);
2664
b9afca3e
DM		 2665 if (start_thread) {
2666 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2667 wake_up(&nvme_kthread_wait);
2668 } else
2669 wait_event_killable(nvme_kthread_wait, nvme_thread);
2670
2671 if (IS_ERR_OR_NULL(nvme_thread)) {
2672 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2673 goto disable;
2674 }
2675
f0b50732 2676 result = nvme_setup_io_queues(dev);
d82e8bfd 2677 if (result && result != -EBUSY)
f0b50732
KB		 2678 goto disable;
2679
d82e8bfd 2680 return result;
f0b50732
KB		 2681
2682 disable:
a1a5ef99 2683 nvme_disable_queue(dev, 0);
b9afca3e 2684 nvme_dev_list_remove(dev);
f0b50732
KB		 2685 unmap:
2686 nvme_dev_unmap(dev);
2687 return result;
2688}
2689
9a6b9458
KB		 2690static int nvme_remove_dead_ctrl(void *arg)
2691{
2692 struct nvme_dev *dev = (struct nvme_dev *)arg;
2693 struct pci_dev *pdev = dev->pci_dev;
2694
2695 if (pci_get_drvdata(pdev))
2696 pci_stop_and_remove_bus_device(pdev);
2697 kref_put(&dev->kref, nvme_free_dev);
2698 return 0;
2699}
2700
2701static void nvme_remove_disks(struct work_struct *ws)
2702{
9a6b9458
KB		 2703 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2704
2705 nvme_dev_remove(dev);
5a92e700 2706 nvme_free_queues(dev, 1);
9a6b9458
KB		 2707}
2708
2709static int nvme_dev_resume(struct nvme_dev *dev)
2710{
2711 int ret;
2712
2713 ret = nvme_dev_start(dev);
2714 if (ret && ret != -EBUSY)
2715 return ret;
2716 if (ret == -EBUSY) {
2717 spin_lock(&dev_list_lock);
9ca97374 2718 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2719 queue_work(nvme_workq, &dev->reset_work);
2720 spin_unlock(&dev_list_lock);
2721 }
d4b4ff8e 2722 dev->initialized = 1;
9a6b9458
KB		 2723 return 0;
2724}
2725
2726static void nvme_dev_reset(struct nvme_dev *dev)
2727{
2728 nvme_dev_shutdown(dev);
2729 if (nvme_dev_resume(dev)) {
2730 dev_err(&dev->pci_dev->dev, "Device failed to resume\n");
2731 kref_get(&dev->kref);
2732 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2733 dev->instance))) {
2734 dev_err(&dev->pci_dev->dev,
2735 "Failed to start controller remove task\n");
2736 kref_put(&dev->kref, nvme_free_dev);
2737 }
2738 }
2739}
2740
2741static void nvme_reset_failed_dev(struct work_struct *ws)
2742{
2743 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2744 nvme_dev_reset(dev);
2745}
2746
9ca97374
TH		 2747static void nvme_reset_workfn(struct work_struct *work)
2748{
2749 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2750 dev->reset_workfn(work);
2751}
2752
8d85fce7 2753static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2754{
0877cb0d 2755 int result = -ENOMEM;
b60503ba
MW		 2756 struct nvme_dev *dev;
2757
2758 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2759 if (!dev)
2760 return -ENOMEM;
2761 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2762 GFP_KERNEL);
2763 if (!dev->entry)
2764 goto free;
1b23484b
MW		 2765 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2766 GFP_KERNEL);
b60503ba
MW		 2767 if (!dev->queues)
2768 goto free;
42f61420
KB		 2769 dev->io_queue = alloc_percpu(unsigned short);
2770 if (!dev->io_queue)
2771 goto free;
b60503ba
MW		 2772
2773 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2774 dev->reset_workfn = nvme_reset_failed_dev;
2775 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
f3db22fe 2776 INIT_WORK(&dev->cpu_work, nvme_cpu_workfn);
b60503ba 2777 dev->pci_dev = pdev;
9a6b9458 2778 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2779 result = nvme_set_instance(dev);
2780 if (result)
0877cb0d 2781 goto free;
b60503ba 2782
091b6092
MW		 2783 result = nvme_setup_prp_pools(dev);
2784 if (result)
0877cb0d 2785 goto release;
091b6092 2786
fb35e914 2787 kref_init(&dev->kref);
f0b50732 2788 result = nvme_dev_start(dev);
d82e8bfd
KB		 2789 if (result) {
2790 if (result == -EBUSY)
2791 goto create_cdev;
0877cb0d 2792 goto release_pools;
d82e8bfd 2793 }
b60503ba 2794
740216fc 2795 result = nvme_dev_add(dev);
d82e8bfd 2796 if (result)
f0b50732 2797 goto shutdown;
740216fc 2798
d82e8bfd 2799 create_cdev:
5e82e952
KB		 2800 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2801 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2802 dev->miscdev.parent = &pdev->dev;
2803 dev->miscdev.name = dev->name;
2804 dev->miscdev.fops = &nvme_dev_fops;
2805 result = misc_register(&dev->miscdev);
2806 if (result)
2807 goto remove;
2808
d4b4ff8e 2809 dev->initialized = 1;
b60503ba
MW		 2810 return 0;
2811
5e82e952
KB		 2812 remove:
2813 nvme_dev_remove(dev);
9ac27090 2814 nvme_free_namespaces(dev);
f0b50732
KB		 2815 shutdown:
2816 nvme_dev_shutdown(dev);
0877cb0d 2817 release_pools:
a1a5ef99 2818 nvme_free_queues(dev, 0);
091b6092 2819 nvme_release_prp_pools(dev);
0877cb0d
KB		 2820 release:
2821 nvme_release_instance(dev);
b60503ba 2822 free:
42f61420 2823 free_percpu(dev->io_queue);
b60503ba
MW		 2824 kfree(dev->queues);
2825 kfree(dev->entry);
2826 kfree(dev);
2827 return result;
2828}
2829
f0d54a54
KB		 2830static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2831{
2832 struct nvme_dev *dev = pci_get_drvdata(pdev);
2833
2834 if (prepare)
2835 nvme_dev_shutdown(dev);
2836 else
2837 nvme_dev_resume(dev);
2838}
2839
09ece142
KB		 2840static void nvme_shutdown(struct pci_dev *pdev)
2841{
2842 struct nvme_dev *dev = pci_get_drvdata(pdev);
2843 nvme_dev_shutdown(dev);
2844}
2845
8d85fce7 2846static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2847{
2848 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2849
2850 spin_lock(&dev_list_lock);
2851 list_del_init(&dev->node);
2852 spin_unlock(&dev_list_lock);
2853
2854 pci_set_drvdata(pdev, NULL);
2855 flush_work(&dev->reset_work);
f3db22fe 2856 flush_work(&dev->cpu_work);
5e82e952 2857 misc_deregister(&dev->miscdev);
9a6b9458
KB		 2858 nvme_dev_remove(dev);
2859 nvme_dev_shutdown(dev);
a1a5ef99 2860 nvme_free_queues(dev, 0);
5a92e700 2861 rcu_barrier();
9a6b9458
KB		 2862 nvme_release_instance(dev);
2863 nvme_release_prp_pools(dev);
5e82e952 2864 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2865}
2866
2867/* These functions are yet to be implemented */
2868#define nvme_error_detected NULL
2869#define nvme_dump_registers NULL
2870#define nvme_link_reset NULL
2871#define nvme_slot_reset NULL
2872#define nvme_error_resume NULL
cd638946 2873
671a6018 2874#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2875static int nvme_suspend(struct device *dev)
2876{
2877 struct pci_dev *pdev = to_pci_dev(dev);
2878 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2879
2880 nvme_dev_shutdown(ndev);
2881 return 0;
2882}
2883
2884static int nvme_resume(struct device *dev)
2885{
2886 struct pci_dev *pdev = to_pci_dev(dev);
2887 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2888
9a6b9458 2889 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2890 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 2891 queue_work(nvme_workq, &ndev->reset_work);
2892 }
2893 return 0;
cd638946 2894}
671a6018 2895#endif
cd638946
KB		 2896
2897static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2898
1d352035 2899static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2900 .error_detected = nvme_error_detected,
2901 .mmio_enabled = nvme_dump_registers,
2902 .link_reset = nvme_link_reset,
2903 .slot_reset = nvme_slot_reset,
2904 .resume = nvme_error_resume,
f0d54a54 2905 .reset_notify = nvme_reset_notify,
b60503ba
MW		 2906};
2907
2908/* Move to pci_ids.h later */
2909#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2910
6eb0d698 2911static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2912 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2913 { 0, }
2914};
2915MODULE_DEVICE_TABLE(pci, nvme_id_table);
2916
2917static struct pci_driver nvme_driver = {
2918 .name = "nvme",
2919 .id_table = nvme_id_table,
2920 .probe = nvme_probe,
8d85fce7 2921 .remove = nvme_remove,
09ece142 2922 .shutdown = nvme_shutdown,
cd638946
KB		 2923 .driver = {
2924 .pm = &nvme_dev_pm_ops,
2925 },
b60503ba
MW		 2926 .err_handler = &nvme_err_handler,
2927};
2928
2929static int __init nvme_init(void)
2930{
0ac13140 2931 int result;
1fa6aead 2932
b9afca3e 2933 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2934
9a6b9458
KB		 2935 nvme_workq = create_singlethread_workqueue("nvme");
2936 if (!nvme_workq)
b9afca3e 2937 return -ENOMEM;
9a6b9458 2938
5c42ea16
KB		 2939 result = register_blkdev(nvme_major, "nvme");
2940 if (result < 0)
9a6b9458 2941 goto kill_workq;
5c42ea16 2942 else if (result > 0)
0ac13140 2943 nvme_major = result;
b60503ba 2944
f3db22fe
KB		 2945 nvme_nb.notifier_call = &nvme_cpu_notify;
2946 result = register_hotcpu_notifier(&nvme_nb);
1fa6aead
MW		 2947 if (result)
2948 goto unregister_blkdev;
f3db22fe
KB		 2949
2950 result = pci_register_driver(&nvme_driver);
2951 if (result)
2952 goto unregister_hotcpu;
1fa6aead 2953 return 0;
b60503ba 2954
f3db22fe
KB		 2955 unregister_hotcpu:
2956 unregister_hotcpu_notifier(&nvme_nb);
1fa6aead 2957 unregister_blkdev:
b60503ba 2958 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2959 kill_workq:
2960 destroy_workqueue(nvme_workq);
b60503ba
MW		 2961 return result;
2962}
2963
2964static void __exit nvme_exit(void)
2965{
2966 pci_unregister_driver(&nvme_driver);
f3db22fe 2967 unregister_hotcpu_notifier(&nvme_nb);
b60503ba 2968 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2969 destroy_workqueue(nvme_workq);
b9afca3e 2970 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 2971 _nvme_check_size();
b60503ba
MW		 2972}
2973
2974MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2975MODULE_LICENSE("GPL");
6eb0d698 2976MODULE_VERSION("0.9");
b60503ba
MW		 2977module_init(nvme_init);
2978module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)