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nvme: don't overwrite req->cmd_flags on sync cmd
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba 31#include <linux/kernel.h>
a5768aa8 32#include <linux/list_sort.h>
b60503ba
MW		 33#include <linux/mm.h>
34#include <linux/module.h>
35#include <linux/moduleparam.h>
36#include <linux/pci.h>
be7b6275 37#include <linux/poison.h>
c3bfe717 38#include <linux/ptrace.h>
b60503ba
MW		 39#include <linux/sched.h>
40#include <linux/slab.h>
e1e5e564 41#include <linux/t10-pi.h>
b60503ba 42#include <linux/types.h>
5d0f6131 43#include <scsi/sg.h>
797a796a
HM		 44#include <asm-generic/io-64-nonatomic-lo-hi.h>
45
b3fffdef 46#define NVME_MINORS (1U << MINORBITS)
9d43cf64 47#define NVME_Q_DEPTH 1024
d31af0a3 48#define NVME_AQ_DEPTH 256
b60503ba
MW		 49#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
50#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 51#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 52#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 53
54static unsigned char admin_timeout = 60;
55module_param(admin_timeout, byte, 0644);
56MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 57
bd67608a
MW		 58unsigned char nvme_io_timeout = 30;
59module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 60MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 61
2484f407
DM		 62static unsigned char shutdown_timeout = 5;
63module_param(shutdown_timeout, byte, 0644);
64MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
65
b60503ba
MW		 66static int nvme_major;
67module_param(nvme_major, int, 0);
68
b3fffdef
KB		 69static int nvme_char_major;
70module_param(nvme_char_major, int, 0);
71
58ffacb5
MW		 72static int use_threaded_interrupts;
73module_param(use_threaded_interrupts, int, 0);
74
1fa6aead
MW		 75static DEFINE_SPINLOCK(dev_list_lock);
76static LIST_HEAD(dev_list);
77static struct task_struct *nvme_thread;
9a6b9458 78static struct workqueue_struct *nvme_workq;
b9afca3e 79static wait_queue_head_t nvme_kthread_wait;
1fa6aead 80
b3fffdef
KB		 81static struct class *nvme_class;
82
d4b4ff8e 83static void nvme_reset_failed_dev(struct work_struct *ws);
4cc06521 84static int nvme_reset(struct nvme_dev *dev);
a4aea562 85static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 86
4d115420
KB		 87struct async_cmd_info {
88 struct kthread_work work;
89 struct kthread_worker *worker;
a4aea562 90 struct request *req;
4d115420
KB		 91 u32 result;
92 int status;
93 void *ctx;
94};
1fa6aead 95
b60503ba
MW		 96/*
97 * An NVM Express queue. Each device has at least two (one for admin
98 * commands and one for I/O commands).
99 */
100struct nvme_queue {
101 struct device *q_dmadev;
091b6092 102 struct nvme_dev *dev;
3193f07b 103 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 104 spinlock_t q_lock;
105 struct nvme_command *sq_cmds;
106 volatile struct nvme_completion *cqes;
42483228 107 struct blk_mq_tags **tags;
b60503ba
MW		 108 dma_addr_t sq_dma_addr;
109 dma_addr_t cq_dma_addr;
b60503ba
MW		 110 u32 __iomem *q_db;
111 u16 q_depth;
6222d172 112 s16 cq_vector;
b60503ba
MW		 113 u16 sq_head;
114 u16 sq_tail;
115 u16 cq_head;
c30341dc 116 u16 qid;
e9539f47
MW		 117 u8 cq_phase;
118 u8 cqe_seen;
4d115420 119 struct async_cmd_info cmdinfo;
b60503ba
MW		 120};
121
122/*
123 * Check we didin't inadvertently grow the command struct
124 */
125static inline void _nvme_check_size(void)
126{
127 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 132 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 133 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 134 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
135 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
136 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
137 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 138 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 139}
140
edd10d33 141typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 142 struct nvme_completion *);
143
e85248e5 144struct nvme_cmd_info {
c2f5b650
MW		 145 nvme_completion_fn fn;
146 void *ctx;
c30341dc 147 int aborted;
a4aea562 148 struct nvme_queue *nvmeq;
ac3dd5bd 149 struct nvme_iod iod[0];
e85248e5
MW		 150};
151
ac3dd5bd
JA		 152/*
153 * Max size of iod being embedded in the request payload
154 */
155#define NVME_INT_PAGES 2
156#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
fda631ff 157#define NVME_INT_MASK 0x01
ac3dd5bd
JA		 158
159/*
160 * Will slightly overestimate the number of pages needed. This is OK
161 * as it only leads to a small amount of wasted memory for the lifetime of
162 * the I/O.
163 */
164static int nvme_npages(unsigned size, struct nvme_dev *dev)
165{
166 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
167 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
168}
169
170static unsigned int nvme_cmd_size(struct nvme_dev *dev)
171{
172 unsigned int ret = sizeof(struct nvme_cmd_info);
173
174 ret += sizeof(struct nvme_iod);
175 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
176 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
177
178 return ret;
179}
180
a4aea562
MB		 181static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
182 unsigned int hctx_idx)
e85248e5 183{
a4aea562
MB		 184 struct nvme_dev *dev = data;
185 struct nvme_queue *nvmeq = dev->queues[0];
186
42483228
KB		 187 WARN_ON(hctx_idx != 0);
188 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
189 WARN_ON(nvmeq->tags);
190
a4aea562 191 hctx->driver_data = nvmeq;
42483228 192 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 193 return 0;
e85248e5
MW		 194}
195
a4aea562
MB		 196static int nvme_admin_init_request(void *data, struct request *req,
197 unsigned int hctx_idx, unsigned int rq_idx,
198 unsigned int numa_node)
22404274 199{
a4aea562
MB		 200 struct nvme_dev *dev = data;
201 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
202 struct nvme_queue *nvmeq = dev->queues[0];
203
204 BUG_ON(!nvmeq);
205 cmd->nvmeq = nvmeq;
206 return 0;
22404274
KB		 207}
208
a4aea562
MB		 209static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
210 unsigned int hctx_idx)
b60503ba 211{
a4aea562 212 struct nvme_dev *dev = data;
42483228 213 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
a4aea562 214
42483228
KB		 215 if (!nvmeq->tags)
216 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 217
42483228 218 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 219 hctx->driver_data = nvmeq;
220 return 0;
b60503ba
MW		 221}
222
a4aea562
MB		 223static int nvme_init_request(void *data, struct request *req,
224 unsigned int hctx_idx, unsigned int rq_idx,
225 unsigned int numa_node)
b60503ba 226{
a4aea562
MB		 227 struct nvme_dev *dev = data;
228 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
229 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
230
231 BUG_ON(!nvmeq);
232 cmd->nvmeq = nvmeq;
233 return 0;
234}
235
236static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
237 nvme_completion_fn handler)
238{
239 cmd->fn = handler;
240 cmd->ctx = ctx;
241 cmd->aborted = 0;
c917dfe5 242 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 243}
244
ac3dd5bd
JA		 245static void *iod_get_private(struct nvme_iod *iod)
246{
247 return (void *) (iod->private & ~0x1UL);
248}
249
250/*
251 * If bit 0 is set, the iod is embedded in the request payload.
252 */
253static bool iod_should_kfree(struct nvme_iod *iod)
254{
fda631ff 255 return (iod->private & NVME_INT_MASK) == 0;
ac3dd5bd
JA		 256}
257
c2f5b650
MW		 258/* Special values must be less than 0x1000 */
259#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 260#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
261#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
262#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 263
edd10d33 264static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 265 struct nvme_completion *cqe)
266{
267 if (ctx == CMD_CTX_CANCELLED)
268 return;
c2f5b650 269 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 270 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 271 "completed id %d twice on queue %d\n",
272 cqe->command_id, le16_to_cpup(&cqe->sq_id));
273 return;
274 }
275 if (ctx == CMD_CTX_INVALID) {
edd10d33 276 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 277 "invalid id %d completed on queue %d\n",
278 cqe->command_id, le16_to_cpup(&cqe->sq_id));
279 return;
280 }
edd10d33 281 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 282}
283
a4aea562 284static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 285{
c2f5b650 286 void *ctx;
b60503ba 287
859361a2 288 if (fn)
a4aea562
MB		 289 *fn = cmd->fn;
290 ctx = cmd->ctx;
291 cmd->fn = special_completion;
292 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 293 return ctx;
b60503ba
MW		 294}
295
a4aea562
MB		 296static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
297 struct nvme_completion *cqe)
3c0cf138 298{
a4aea562
MB		 299 u32 result = le32_to_cpup(&cqe->result);
300 u16 status = le16_to_cpup(&cqe->status) >> 1;
301
302 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
303 ++nvmeq->dev->event_limit;
a5768aa8
KB		 304 if (status != NVME_SC_SUCCESS)
305 return;
306
307 switch (result & 0xff07) {
308 case NVME_AER_NOTICE_NS_CHANGED:
309 dev_info(nvmeq->q_dmadev, "rescanning\n");
310 schedule_work(&nvmeq->dev->scan_work);
311 default:
312 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
313 }
b60503ba
MW		 314}
315
a4aea562
MB		 316static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
317 struct nvme_completion *cqe)
5a92e700 318{
a4aea562
MB		 319 struct request *req = ctx;
320
321 u16 status = le16_to_cpup(&cqe->status) >> 1;
322 u32 result = le32_to_cpup(&cqe->result);
a51afb54 323
42483228 324 blk_mq_free_request(req);
a51afb54 325
a4aea562
MB		 326 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
327 ++nvmeq->dev->abort_limit;
5a92e700
KB		 328}
329
a4aea562
MB		 330static void async_completion(struct nvme_queue *nvmeq, void *ctx,
331 struct nvme_completion *cqe)
b60503ba 332{
a4aea562
MB		 333 struct async_cmd_info *cmdinfo = ctx;
334 cmdinfo->result = le32_to_cpup(&cqe->result);
335 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
336 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
42483228 337 blk_mq_free_request(cmdinfo->req);
b60503ba
MW		 338}
339
a4aea562
MB		 340static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
341 unsigned int tag)
b60503ba 342{
42483228 343 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
a51afb54 344
a4aea562 345 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 346}
347
a4aea562
MB		 348/*
349 * Called with local interrupts disabled and the q_lock held. May not sleep.
350 */
351static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
352 nvme_completion_fn *fn)
4f5099af 353{
a4aea562
MB		 354 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
355 void *ctx;
356 if (tag >= nvmeq->q_depth) {
357 *fn = special_completion;
358 return CMD_CTX_INVALID;
359 }
360 if (fn)
361 *fn = cmd->fn;
362 ctx = cmd->ctx;
363 cmd->fn = special_completion;
364 cmd->ctx = CMD_CTX_COMPLETED;
365 return ctx;
b60503ba
MW		 366}
367
368/**
714a7a22 369 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 370 * @nvmeq: The queue to use
371 * @cmd: The command to send
372 *
373 * Safe to use from interrupt context
374 */
a4aea562 375static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 376{
a4aea562
MB		 377 u16 tail = nvmeq->sq_tail;
378
b60503ba 379 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 380 if (++tail == nvmeq->q_depth)
381 tail = 0;
7547881d 382 writel(tail, nvmeq->q_db);
b60503ba 383 nvmeq->sq_tail = tail;
b60503ba
MW		 384
385 return 0;
386}
387
a4aea562
MB		 388static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
389{
390 unsigned long flags;
391 int ret;
392 spin_lock_irqsave(&nvmeq->q_lock, flags);
393 ret = __nvme_submit_cmd(nvmeq, cmd);
394 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
395 return ret;
396}
397
eca18b23 398static __le64 **iod_list(struct nvme_iod *iod)
e025344c 399{
eca18b23 400 return ((void *)iod) + iod->offset;
e025344c
SMM		 401}
402
ac3dd5bd
JA		 403static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
404 unsigned nseg, unsigned long private)
eca18b23 405{
ac3dd5bd
JA		 406 iod->private = private;
407 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
408 iod->npages = -1;
409 iod->length = nbytes;
410 iod->nents = 0;
eca18b23 411}
b60503ba 412
eca18b23 413static struct nvme_iod *
ac3dd5bd
JA		 414__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
415 unsigned long priv, gfp_t gfp)
b60503ba 416{
eca18b23 417 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 418 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 419 sizeof(struct scatterlist) * nseg, gfp);
420
ac3dd5bd
JA		 421 if (iod)
422 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 423
424 return iod;
b60503ba
MW		 425}
426
ac3dd5bd
JA		 427static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
428 gfp_t gfp)
429{
430 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
431 sizeof(struct nvme_dsm_range);
ac3dd5bd
JA		 432 struct nvme_iod *iod;
433
434 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
435 size <= NVME_INT_BYTES(dev)) {
436 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
437
438 iod = cmd->iod;
ac3dd5bd 439 iod_init(iod, size, rq->nr_phys_segments,
fda631ff 440 (unsigned long) rq | NVME_INT_MASK);
ac3dd5bd
JA		 441 return iod;
442 }
443
444 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
445 (unsigned long) rq, gfp);
446}
447
d29ec824 448static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 449{
1d090624 450 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 451 int i;
452 __le64 **list = iod_list(iod);
453 dma_addr_t prp_dma = iod->first_dma;
454
455 if (iod->npages == 0)
456 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
457 for (i = 0; i < iod->npages; i++) {
458 __le64 *prp_list = list[i];
459 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
460 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
461 prp_dma = next_prp_dma;
462 }
ac3dd5bd
JA		 463
464 if (iod_should_kfree(iod))
465 kfree(iod);
b60503ba
MW		 466}
467
b4ff9c8d
KB		 468static int nvme_error_status(u16 status)
469{
470 switch (status & 0x7ff) {
471 case NVME_SC_SUCCESS:
472 return 0;
473 case NVME_SC_CAP_EXCEEDED:
474 return -ENOSPC;
475 default:
476 return -EIO;
477 }
478}
479
52b68d7e 480#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 481static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
482{
483 if (be32_to_cpu(pi->ref_tag) == v)
484 pi->ref_tag = cpu_to_be32(p);
485}
486
487static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
488{
489 if (be32_to_cpu(pi->ref_tag) == p)
490 pi->ref_tag = cpu_to_be32(v);
491}
492
493/**
494 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
495 *
496 * The virtual start sector is the one that was originally submitted by the
497 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
498 * start sector may be different. Remap protection information to match the
499 * physical LBA on writes, and back to the original seed on reads.
500 *
501 * Type 0 and 3 do not have a ref tag, so no remapping required.
502 */
503static void nvme_dif_remap(struct request *req,
504 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
505{
506 struct nvme_ns *ns = req->rq_disk->private_data;
507 struct bio_integrity_payload *bip;
508 struct t10_pi_tuple *pi;
509 void *p, *pmap;
510 u32 i, nlb, ts, phys, virt;
511
512 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
513 return;
514
515 bip = bio_integrity(req->bio);
516 if (!bip)
517 return;
518
519 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 520
521 p = pmap;
522 virt = bip_get_seed(bip);
523 phys = nvme_block_nr(ns, blk_rq_pos(req));
524 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
525 ts = ns->disk->integrity->tuple_size;
526
527 for (i = 0; i < nlb; i++, virt++, phys++) {
528 pi = (struct t10_pi_tuple *)p;
529 dif_swap(phys, virt, pi);
530 p += ts;
531 }
532 kunmap_atomic(pmap);
533}
534
52b68d7e
KB		 535static int nvme_noop_verify(struct blk_integrity_iter *iter)
536{
537 return 0;
538}
539
540static int nvme_noop_generate(struct blk_integrity_iter *iter)
541{
542 return 0;
543}
544
545struct blk_integrity nvme_meta_noop = {
546 .name = "NVME_META_NOOP",
547 .generate_fn = nvme_noop_generate,
548 .verify_fn = nvme_noop_verify,
549};
550
551static void nvme_init_integrity(struct nvme_ns *ns)
552{
553 struct blk_integrity integrity;
554
555 switch (ns->pi_type) {
556 case NVME_NS_DPS_PI_TYPE3:
557 integrity = t10_pi_type3_crc;
558 break;
559 case NVME_NS_DPS_PI_TYPE1:
560 case NVME_NS_DPS_PI_TYPE2:
561 integrity = t10_pi_type1_crc;
562 break;
563 default:
564 integrity = nvme_meta_noop;
565 break;
566 }
567 integrity.tuple_size = ns->ms;
568 blk_integrity_register(ns->disk, &integrity);
569 blk_queue_max_integrity_segments(ns->queue, 1);
570}
571#else /* CONFIG_BLK_DEV_INTEGRITY */
572static void nvme_dif_remap(struct request *req,
573 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
574{
575}
576static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
577{
578}
579static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
580{
581}
582static void nvme_init_integrity(struct nvme_ns *ns)
583{
584}
585#endif
586
a4aea562 587static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 588 struct nvme_completion *cqe)
589{
eca18b23 590 struct nvme_iod *iod = ctx;
ac3dd5bd 591 struct request *req = iod_get_private(iod);
a4aea562
MB		 592 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
593
b60503ba
MW		 594 u16 status = le16_to_cpup(&cqe->status) >> 1;
595
edd10d33 596 if (unlikely(status)) {
a4aea562
MB		 597 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
598 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 599 unsigned long flags;
600
a4aea562 601 blk_mq_requeue_request(req);
c9d3bf88
KB		 602 spin_lock_irqsave(req->q->queue_lock, flags);
603 if (!blk_queue_stopped(req->q))
604 blk_mq_kick_requeue_list(req->q);
605 spin_unlock_irqrestore(req->q->queue_lock, flags);
edd10d33
KB		 606 return;
607 }
d29ec824 608 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
d29ec824
CH		 609 req->errors = status;
610 } else {
611 req->errors = nvme_error_status(status);
612 }
a4aea562
MB		 613 } else
614 req->errors = 0;
a0a931d6
KB		 615 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
616 u32 result = le32_to_cpup(&cqe->result);
617 req->special = (void *)(uintptr_t)result;
618 }
a4aea562
MB		 619
620 if (cmd_rq->aborted)
e75ec752 621 dev_warn(nvmeq->dev->dev,
a4aea562
MB		 622 "completing aborted command with status:%04x\n",
623 status);
624
e1e5e564 625 if (iod->nents) {
e75ec752 626 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
a4aea562 627 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
e1e5e564
KB		 628 if (blk_integrity_rq(req)) {
629 if (!rq_data_dir(req))
630 nvme_dif_remap(req, nvme_dif_complete);
e75ec752 631 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
e1e5e564
KB		 632 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
633 }
634 }
edd10d33 635 nvme_free_iod(nvmeq->dev, iod);
3291fa57 636
a4aea562 637 blk_mq_complete_request(req);
b60503ba
MW		 638}
639
184d2944 640/* length is in bytes. gfp flags indicates whether we may sleep. */
d29ec824
CH		 641static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
642 int total_len, gfp_t gfp)
ff22b54f 643{
99802a7a 644 struct dma_pool *pool;
eca18b23
MW		 645 int length = total_len;
646 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 647 int dma_len = sg_dma_len(sg);
648 u64 dma_addr = sg_dma_address(sg);
f137e0f1
MI		 649 u32 page_size = dev->page_size;
650 int offset = dma_addr & (page_size - 1);
e025344c 651 __le64 *prp_list;
eca18b23 652 __le64 **list = iod_list(iod);
e025344c 653 dma_addr_t prp_dma;
eca18b23 654 int nprps, i;
ff22b54f 655
1d090624 656 length -= (page_size - offset);
ff22b54f 657 if (length <= 0)
eca18b23 658 return total_len;
ff22b54f 659
1d090624 660 dma_len -= (page_size - offset);
ff22b54f 661 if (dma_len) {
1d090624 662 dma_addr += (page_size - offset);
ff22b54f
MW		 663 } else {
664 sg = sg_next(sg);
665 dma_addr = sg_dma_address(sg);
666 dma_len = sg_dma_len(sg);
667 }
668
1d090624 669 if (length <= page_size) {
edd10d33 670 iod->first_dma = dma_addr;
eca18b23 671 return total_len;
e025344c
SMM		 672 }
673
1d090624 674 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 675 if (nprps <= (256 / 8)) {
676 pool = dev->prp_small_pool;
eca18b23 677 iod->npages = 0;
99802a7a
MW		 678 } else {
679 pool = dev->prp_page_pool;
eca18b23 680 iod->npages = 1;
99802a7a
MW		 681 }
682
b77954cb
MW		 683 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
684 if (!prp_list) {
edd10d33 685 iod->first_dma = dma_addr;
eca18b23 686 iod->npages = -1;
1d090624 687 return (total_len - length) + page_size;
b77954cb 688 }
eca18b23
MW		 689 list[0] = prp_list;
690 iod->first_dma = prp_dma;
e025344c
SMM		 691 i = 0;
692 for (;;) {
1d090624 693 if (i == page_size >> 3) {
e025344c 694 __le64 *old_prp_list = prp_list;
b77954cb 695 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 696 if (!prp_list)
697 return total_len - length;
698 list[iod->npages++] = prp_list;
7523d834
MW		 699 prp_list[0] = old_prp_list[i - 1];
700 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
701 i = 1;
e025344c
SMM		 702 }
703 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 704 dma_len -= page_size;
705 dma_addr += page_size;
706 length -= page_size;
e025344c
SMM		 707 if (length <= 0)
708 break;
709 if (dma_len > 0)
710 continue;
711 BUG_ON(dma_len < 0);
712 sg = sg_next(sg);
713 dma_addr = sg_dma_address(sg);
714 dma_len = sg_dma_len(sg);
ff22b54f
MW		 715 }
716
eca18b23 717 return total_len;
ff22b54f
MW		 718}
719
d29ec824
CH		 720static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
721 struct nvme_iod *iod)
722{
723 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
724
725 memcpy(cmnd, req->cmd, sizeof(struct nvme_command));
726 cmnd->rw.command_id = req->tag;
727 if (req->nr_phys_segments) {
728 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
729 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
730 }
731
732 if (++nvmeq->sq_tail == nvmeq->q_depth)
733 nvmeq->sq_tail = 0;
734 writel(nvmeq->sq_tail, nvmeq->q_db);
735}
736
a4aea562
MB		 737/*
738 * We reuse the small pool to allocate the 16-byte range here as it is not
739 * worth having a special pool for these or additional cases to handle freeing
740 * the iod.
741 */
742static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
743 struct request *req, struct nvme_iod *iod)
0e5e4f0e 744{
edd10d33
KB		 745 struct nvme_dsm_range *range =
746 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 747 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
748
0e5e4f0e 749 range->cattr = cpu_to_le32(0);
a4aea562
MB		 750 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
751 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e
KB		 752
753 memset(cmnd, 0, sizeof(*cmnd));
754 cmnd->dsm.opcode = nvme_cmd_dsm;
a4aea562 755 cmnd->dsm.command_id = req->tag;
0e5e4f0e
KB		 756 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
757 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
758 cmnd->dsm.nr = 0;
759 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
760
761 if (++nvmeq->sq_tail == nvmeq->q_depth)
762 nvmeq->sq_tail = 0;
763 writel(nvmeq->sq_tail, nvmeq->q_db);
0e5e4f0e
KB		 764}
765
a4aea562 766static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 767 int cmdid)
768{
769 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
770
771 memset(cmnd, 0, sizeof(*cmnd));
772 cmnd->common.opcode = nvme_cmd_flush;
773 cmnd->common.command_id = cmdid;
774 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
775
776 if (++nvmeq->sq_tail == nvmeq->q_depth)
777 nvmeq->sq_tail = 0;
778 writel(nvmeq->sq_tail, nvmeq->q_db);
00df5cb4
MW		 779}
780
a4aea562
MB		 781static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
782 struct nvme_ns *ns)
b60503ba 783{
ac3dd5bd 784 struct request *req = iod_get_private(iod);
ff22b54f 785 struct nvme_command *cmnd;
a4aea562
MB		 786 u16 control = 0;
787 u32 dsmgmt = 0;
00df5cb4 788
a4aea562 789 if (req->cmd_flags & REQ_FUA)
b60503ba 790 control |= NVME_RW_FUA;
a4aea562 791 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 792 control |= NVME_RW_LR;
793
a4aea562 794 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 795 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
796
ff22b54f 797 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 798 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 799
a4aea562
MB		 800 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
801 cmnd->rw.command_id = req->tag;
ff22b54f 802 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 803 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
804 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
a4aea562
MB		 805 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
806 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
e1e5e564
KB		 807
808 if (blk_integrity_rq(req)) {
809 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
810 switch (ns->pi_type) {
811 case NVME_NS_DPS_PI_TYPE3:
812 control |= NVME_RW_PRINFO_PRCHK_GUARD;
813 break;
814 case NVME_NS_DPS_PI_TYPE1:
815 case NVME_NS_DPS_PI_TYPE2:
816 control |= NVME_RW_PRINFO_PRCHK_GUARD |
817 NVME_RW_PRINFO_PRCHK_REF;
818 cmnd->rw.reftag = cpu_to_le32(
819 nvme_block_nr(ns, blk_rq_pos(req)));
820 break;
821 }
822 } else if (ns->ms)
823 control |= NVME_RW_PRINFO_PRACT;
824
ff22b54f
MW		 825 cmnd->rw.control = cpu_to_le16(control);
826 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 827
b60503ba
MW		 828 if (++nvmeq->sq_tail == nvmeq->q_depth)
829 nvmeq->sq_tail = 0;
7547881d 830 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 831
1974b1ae 832 return 0;
edd10d33
KB		 833}
834
d29ec824
CH		 835/*
836 * NOTE: ns is NULL when called on the admin queue.
837 */
a4aea562
MB		 838static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
839 const struct blk_mq_queue_data *bd)
edd10d33 840{
a4aea562
MB		 841 struct nvme_ns *ns = hctx->queue->queuedata;
842 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 843 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 844 struct request *req = bd->rq;
845 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 846 struct nvme_iod *iod;
a4aea562 847 enum dma_data_direction dma_dir;
edd10d33 848
e1e5e564
KB		 849 /*
850 * If formated with metadata, require the block layer provide a buffer
851 * unless this namespace is formated such that the metadata can be
852 * stripped/generated by the controller with PRACT=1.
853 */
d29ec824 854 if (ns && ns->ms && !blk_integrity_rq(req)) {
e1e5e564
KB		 855 if (!(ns->pi_type && ns->ms == 8)) {
856 req->errors = -EFAULT;
857 blk_mq_complete_request(req);
858 return BLK_MQ_RQ_QUEUE_OK;
859 }
860 }
861
d29ec824 862 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
edd10d33 863 if (!iod)
fe54303e 864 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 865
a4aea562 866 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 867 void *range;
868 /*
869 * We reuse the small pool to allocate the 16-byte range here
870 * as it is not worth having a special pool for these or
871 * additional cases to handle freeing the iod.
872 */
d29ec824 873 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
edd10d33 874 &iod->first_dma);
a4aea562 875 if (!range)
fe54303e 876 goto retry_cmd;
edd10d33
KB		 877 iod_list(iod)[0] = (__le64 *)range;
878 iod->npages = 0;
ac3dd5bd 879 } else if (req->nr_phys_segments) {
a4aea562
MB		 880 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
881
ac3dd5bd 882 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 883 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 884 if (!iod->nents)
885 goto error_cmd;
a4aea562
MB		 886
887 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 888 goto retry_cmd;
a4aea562 889
fe54303e 890 if (blk_rq_bytes(req) !=
d29ec824
CH		 891 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
892 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
fe54303e
JA		 893 goto retry_cmd;
894 }
e1e5e564
KB		 895 if (blk_integrity_rq(req)) {
896 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
897 goto error_cmd;
898
899 sg_init_table(iod->meta_sg, 1);
900 if (blk_rq_map_integrity_sg(
901 req->q, req->bio, iod->meta_sg) != 1)
902 goto error_cmd;
903
904 if (rq_data_dir(req))
905 nvme_dif_remap(req, nvme_dif_prep);
906
907 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
908 goto error_cmd;
909 }
edd10d33 910 }
1974b1ae 911
9af8785a 912 nvme_set_info(cmd, iod, req_completion);
a4aea562 913 spin_lock_irq(&nvmeq->q_lock);
d29ec824
CH		 914 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
915 nvme_submit_priv(nvmeq, req, iod);
916 else if (req->cmd_flags & REQ_DISCARD)
a4aea562
MB		 917 nvme_submit_discard(nvmeq, ns, req, iod);
918 else if (req->cmd_flags & REQ_FLUSH)
919 nvme_submit_flush(nvmeq, ns, req->tag);
920 else
921 nvme_submit_iod(nvmeq, iod, ns);
922
923 nvme_process_cq(nvmeq);
924 spin_unlock_irq(&nvmeq->q_lock);
925 return BLK_MQ_RQ_QUEUE_OK;
926
fe54303e 927 error_cmd:
d29ec824 928 nvme_free_iod(dev, iod);
fe54303e
JA		 929 return BLK_MQ_RQ_QUEUE_ERROR;
930 retry_cmd:
d29ec824 931 nvme_free_iod(dev, iod);
fe54303e 932 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 933}
934
e9539f47 935static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 936{
82123460 937 u16 head, phase;
b60503ba 938
b60503ba 939 head = nvmeq->cq_head;
82123460 940 phase = nvmeq->cq_phase;
b60503ba
MW		 941
942 for (;;) {
c2f5b650
MW		 943 void *ctx;
944 nvme_completion_fn fn;
b60503ba 945 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 946 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 947 break;
948 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
949 if (++head == nvmeq->q_depth) {
950 head = 0;
82123460 951 phase = !phase;
b60503ba 952 }
a4aea562 953 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 954 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 955 }
956
957 /* If the controller ignores the cq head doorbell and continuously
958 * writes to the queue, it is theoretically possible to wrap around
959 * the queue twice and mistakenly return IRQ_NONE. Linux only
960 * requires that 0.1% of your interrupts are handled, so this isn't
961 * a big problem.
962 */
82123460 963 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 964 return 0;
b60503ba 965
b80d5ccc 966 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 967 nvmeq->cq_head = head;
82123460 968 nvmeq->cq_phase = phase;
b60503ba 969
e9539f47
MW		 970 nvmeq->cqe_seen = 1;
971 return 1;
b60503ba
MW		 972}
973
974static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 975{
976 irqreturn_t result;
977 struct nvme_queue *nvmeq = data;
978 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 979 nvme_process_cq(nvmeq);
980 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
981 nvmeq->cqe_seen = 0;
58ffacb5
MW		 982 spin_unlock(&nvmeq->q_lock);
983 return result;
984}
985
986static irqreturn_t nvme_irq_check(int irq, void *data)
987{
988 struct nvme_queue *nvmeq = data;
989 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
990 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
991 return IRQ_NONE;
992 return IRQ_WAKE_THREAD;
993}
994
b60503ba
MW		 995/*
996 * Returns 0 on success. If the result is negative, it's a Linux error code;
997 * if the result is positive, it's an NVM Express status code
998 */
d29ec824
CH		 999int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1000 void *buffer, void __user *ubuffer, unsigned bufflen,
1001 u32 *result, unsigned timeout)
b60503ba 1002{
d29ec824
CH		 1003 bool write = cmd->common.opcode & 1;
1004 struct bio *bio = NULL;
f705f837 1005 struct request *req;
d29ec824 1006 int ret;
f705f837 1007
d29ec824 1008 req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
f705f837
CH		 1009 if (IS_ERR(req))
1010 return PTR_ERR(req);
b60503ba 1011
d29ec824 1012 req->cmd_type = REQ_TYPE_DRV_PRIV;
e112af0d 1013 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d29ec824
CH		 1014 req->__data_len = 0;
1015 req->__sector = (sector_t) -1;
1016 req->bio = req->biotail = NULL;
b60503ba 1017
f4ff414a 1018 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
a4aea562 1019
d29ec824
CH		 1020 req->cmd = (unsigned char *)cmd;
1021 req->cmd_len = sizeof(struct nvme_command);
a0a931d6 1022 req->special = (void *)0;
b60503ba 1023
d29ec824
CH		 1024 if (buffer && bufflen) {
1025 ret = blk_rq_map_kern(q, req, buffer, bufflen, __GFP_WAIT);
1026 if (ret)
1027 goto out;
1028 } else if (ubuffer && bufflen) {
1029 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen, __GFP_WAIT);
1030 if (ret)
1031 goto out;
1032 bio = req->bio;
1033 }
3c0cf138 1034
d29ec824
CH		 1035 blk_execute_rq(req->q, NULL, req, 0);
1036 if (bio)
1037 blk_rq_unmap_user(bio);
b60503ba 1038 if (result)
a0a931d6 1039 *result = (u32)(uintptr_t)req->special;
d29ec824
CH		 1040 ret = req->errors;
1041 out:
f705f837 1042 blk_mq_free_request(req);
d29ec824 1043 return ret;
f705f837
CH		 1044}
1045
d29ec824
CH		 1046int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1047 void *buffer, unsigned bufflen)
f705f837 1048{
d29ec824 1049 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
b60503ba
MW		 1050}
1051
a4aea562
MB		 1052static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1053{
1054 struct nvme_queue *nvmeq = dev->queues[0];
1055 struct nvme_command c;
1056 struct nvme_cmd_info *cmd_info;
1057 struct request *req;
1058
1efccc9d 1059 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
9f173b33
DC		 1060 if (IS_ERR(req))
1061 return PTR_ERR(req);
a4aea562 1062
c917dfe5 1063 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562 1064 cmd_info = blk_mq_rq_to_pdu(req);
1efccc9d 1065 nvme_set_info(cmd_info, NULL, async_req_completion);
a4aea562
MB		 1066
1067 memset(&c, 0, sizeof(c));
1068 c.common.opcode = nvme_admin_async_event;
1069 c.common.command_id = req->tag;
1070
42483228 1071 blk_mq_free_request(req);
a4aea562
MB		 1072 return __nvme_submit_cmd(nvmeq, &c);
1073}
1074
1075static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 1076 struct nvme_command *cmd,
1077 struct async_cmd_info *cmdinfo, unsigned timeout)
1078{
a4aea562
MB		 1079 struct nvme_queue *nvmeq = dev->queues[0];
1080 struct request *req;
1081 struct nvme_cmd_info *cmd_rq;
4d115420 1082
a4aea562 1083 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 1084 if (IS_ERR(req))
1085 return PTR_ERR(req);
a4aea562
MB		 1086
1087 req->timeout = timeout;
1088 cmd_rq = blk_mq_rq_to_pdu(req);
1089 cmdinfo->req = req;
1090 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 1091 cmdinfo->status = -EINTR;
a4aea562
MB		 1092
1093 cmd->common.command_id = req->tag;
1094
4f5099af 1095 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 1096}
1097
b60503ba
MW		 1098static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1099{
b60503ba
MW		 1100 struct nvme_command c;
1101
1102 memset(&c, 0, sizeof(c));
1103 c.delete_queue.opcode = opcode;
1104 c.delete_queue.qid = cpu_to_le16(id);
1105
d29ec824 1106 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1107}
1108
1109static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1110 struct nvme_queue *nvmeq)
1111{
b60503ba
MW		 1112 struct nvme_command c;
1113 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1114
d29ec824
CH		 1115 /*
1116 * Note: we (ab)use the fact the the prp fields survive if no data
1117 * is attached to the request.
1118 */
b60503ba
MW		 1119 memset(&c, 0, sizeof(c));
1120 c.create_cq.opcode = nvme_admin_create_cq;
1121 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1122 c.create_cq.cqid = cpu_to_le16(qid);
1123 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1124 c.create_cq.cq_flags = cpu_to_le16(flags);
1125 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1126
d29ec824 1127 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1128}
1129
1130static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1131 struct nvme_queue *nvmeq)
1132{
b60503ba
MW		 1133 struct nvme_command c;
1134 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1135
d29ec824
CH		 1136 /*
1137 * Note: we (ab)use the fact the the prp fields survive if no data
1138 * is attached to the request.
1139 */
b60503ba
MW		 1140 memset(&c, 0, sizeof(c));
1141 c.create_sq.opcode = nvme_admin_create_sq;
1142 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1143 c.create_sq.sqid = cpu_to_le16(qid);
1144 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1145 c.create_sq.sq_flags = cpu_to_le16(flags);
1146 c.create_sq.cqid = cpu_to_le16(qid);
1147
d29ec824 1148 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1149}
1150
1151static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1152{
1153 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1154}
1155
1156static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1157{
1158 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1159}
1160
d29ec824 1161int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
bc5fc7e4 1162{
d29ec824
CH		 1163 struct nvme_command c = {
1164 .identify.opcode = nvme_admin_identify,
1165 .identify.cns = cpu_to_le32(1),
1166 };
1167 int error;
bc5fc7e4 1168
d29ec824
CH		 1169 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1170 if (!*id)
1171 return -ENOMEM;
1172
1173 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1174 sizeof(struct nvme_id_ctrl));
1175 if (error)
1176 kfree(*id);
1177 return error;
1178}
1179
1180int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1181 struct nvme_id_ns **id)
1182{
1183 struct nvme_command c = {
1184 .identify.opcode = nvme_admin_identify,
1185 .identify.nsid = cpu_to_le32(nsid),
1186 };
1187 int error;
bc5fc7e4 1188
d29ec824
CH		 1189 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1190 if (!*id)
1191 return -ENOMEM;
1192
1193 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1194 sizeof(struct nvme_id_ns));
1195 if (error)
1196 kfree(*id);
1197 return error;
bc5fc7e4
MW		 1198}
1199
5d0f6131 1200int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1201 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1202{
1203 struct nvme_command c;
1204
1205 memset(&c, 0, sizeof(c));
1206 c.features.opcode = nvme_admin_get_features;
a42cecce 1207 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1208 c.features.prp1 = cpu_to_le64(dma_addr);
1209 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1210
d29ec824
CH		 1211 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1212 result, 0);
df348139
MW		 1213}
1214
5d0f6131
VV		 1215int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1216 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1217{
1218 struct nvme_command c;
1219
1220 memset(&c, 0, sizeof(c));
1221 c.features.opcode = nvme_admin_set_features;
1222 c.features.prp1 = cpu_to_le64(dma_addr);
1223 c.features.fid = cpu_to_le32(fid);
1224 c.features.dword11 = cpu_to_le32(dword11);
1225
d29ec824
CH		 1226 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1227 result, 0);
1228}
1229
1230int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1231{
1232 struct nvme_command c = {
1233 .common.opcode = nvme_admin_get_log_page,
1234 .common.nsid = cpu_to_le32(0xFFFFFFFF),
1235 .common.cdw10[0] = cpu_to_le32(
1236 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1237 NVME_LOG_SMART),
1238 };
1239 int error;
1240
1241 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1242 if (!*log)
1243 return -ENOMEM;
1244
1245 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1246 sizeof(struct nvme_smart_log));
1247 if (error)
1248 kfree(*log);
1249 return error;
bc5fc7e4
MW		 1250}
1251
c30341dc 1252/**
a4aea562 1253 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1254 *
1255 * Schedule controller reset if the command was already aborted once before and
1256 * still hasn't been returned to the driver, or if this is the admin queue.
1257 */
a4aea562 1258static void nvme_abort_req(struct request *req)
c30341dc 1259{
a4aea562
MB		 1260 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1261 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1262 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1263 struct request *abort_req;
1264 struct nvme_cmd_info *abort_cmd;
1265 struct nvme_command cmd;
c30341dc 1266
a4aea562 1267 if (!nvmeq->qid || cmd_rq->aborted) {
7a509a6b
KB		 1268 unsigned long flags;
1269
1270 spin_lock_irqsave(&dev_list_lock, flags);
c30341dc 1271 if (work_busy(&dev->reset_work))
7a509a6b 1272 goto out;
c30341dc 1273 list_del_init(&dev->node);
e75ec752 1274 dev_warn(dev->dev, "I/O %d QID %d timeout, reset controller\n",
a4aea562 1275 req->tag, nvmeq->qid);
9ca97374 1276 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc 1277 queue_work(nvme_workq, &dev->reset_work);
7a509a6b
KB		 1278 out:
1279 spin_unlock_irqrestore(&dev_list_lock, flags);
c30341dc
KB		 1280 return;
1281 }
1282
1283 if (!dev->abort_limit)
1284 return;
1285
a4aea562
MB		 1286 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1287 false);
9f173b33 1288 if (IS_ERR(abort_req))
c30341dc
KB		 1289 return;
1290
a4aea562
MB		 1291 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1292 nvme_set_info(abort_cmd, abort_req, abort_completion);
1293
c30341dc
KB		 1294 memset(&cmd, 0, sizeof(cmd));
1295 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1296 cmd.abort.cid = req->tag;
c30341dc 1297 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1298 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1299
1300 --dev->abort_limit;
a4aea562 1301 cmd_rq->aborted = 1;
c30341dc 1302
a4aea562 1303 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1304 nvmeq->qid);
a4aea562
MB		 1305 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1306 dev_warn(nvmeq->q_dmadev,
1307 "Could not abort I/O %d QID %d",
1308 req->tag, nvmeq->qid);
c87fd540 1309 blk_mq_free_request(abort_req);
a4aea562 1310 }
c30341dc
KB		 1311}
1312
42483228 1313static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
a09115b2 1314{
a4aea562
MB		 1315 struct nvme_queue *nvmeq = data;
1316 void *ctx;
1317 nvme_completion_fn fn;
1318 struct nvme_cmd_info *cmd;
cef6a948
KB		 1319 struct nvme_completion cqe;
1320
1321 if (!blk_mq_request_started(req))
1322 return;
a09115b2 1323
a4aea562 1324 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1325
a4aea562
MB		 1326 if (cmd->ctx == CMD_CTX_CANCELLED)
1327 return;
1328
cef6a948
KB		 1329 if (blk_queue_dying(req->q))
1330 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1331 else
1332 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1333
1334
a4aea562
MB		 1335 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1336 req->tag, nvmeq->qid);
1337 ctx = cancel_cmd_info(cmd, &fn);
1338 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1339}
1340
a4aea562 1341static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1342{
a4aea562
MB		 1343 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1344 struct nvme_queue *nvmeq = cmd->nvmeq;
1345
1346 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1347 nvmeq->qid);
7a509a6b 1348 spin_lock_irq(&nvmeq->q_lock);
07836e65 1349 nvme_abort_req(req);
7a509a6b 1350 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1351
07836e65
KB		 1352 /*
1353 * The aborted req will be completed on receiving the abort req.
1354 * We enable the timer again. If hit twice, it'll cause a device reset,
1355 * as the device then is in a faulty state.
1356 */
1357 return BLK_EH_RESET_TIMER;
a4aea562 1358}
22404274 1359
a4aea562
MB		 1360static void nvme_free_queue(struct nvme_queue *nvmeq)
1361{
9e866774
MW		 1362 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1363 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1364 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1365 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1366 kfree(nvmeq);
1367}
1368
a1a5ef99 1369static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1370{
1371 int i;
1372
a1a5ef99 1373 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1374 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1375 dev->queue_count--;
a4aea562 1376 dev->queues[i] = NULL;
f435c282 1377 nvme_free_queue(nvmeq);
121c7ad4 1378 }
22404274
KB		 1379}
1380
4d115420
KB		 1381/**
1382 * nvme_suspend_queue - put queue into suspended state
1383 * @nvmeq - queue to suspend
4d115420
KB		 1384 */
1385static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1386{
2b25d981 1387 int vector;
b60503ba 1388
a09115b2 1389 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1390 if (nvmeq->cq_vector == -1) {
1391 spin_unlock_irq(&nvmeq->q_lock);
1392 return 1;
1393 }
1394 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1395 nvmeq->dev->online_queues--;
2b25d981 1396 nvmeq->cq_vector = -1;
a09115b2
MW		 1397 spin_unlock_irq(&nvmeq->q_lock);
1398
6df3dbc8
KB		 1399 if (!nvmeq->qid && nvmeq->dev->admin_q)
1400 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1401
aba2080f
MW		 1402 irq_set_affinity_hint(vector, NULL);
1403 free_irq(vector, nvmeq);
b60503ba 1404
4d115420
KB		 1405 return 0;
1406}
b60503ba 1407
4d115420
KB		 1408static void nvme_clear_queue(struct nvme_queue *nvmeq)
1409{
22404274 1410 spin_lock_irq(&nvmeq->q_lock);
42483228
KB		 1411 if (nvmeq->tags && *nvmeq->tags)
1412 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
22404274 1413 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1414}
1415
4d115420
KB		 1416static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1417{
a4aea562 1418 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1419
1420 if (!nvmeq)
1421 return;
1422 if (nvme_suspend_queue(nvmeq))
1423 return;
1424
0e53d180
KB		 1425 /* Don't tell the adapter to delete the admin queue.
1426 * Don't tell a removed adapter to delete IO queues. */
1427 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1428 adapter_delete_sq(dev, qid);
1429 adapter_delete_cq(dev, qid);
1430 }
07836e65
KB		 1431
1432 spin_lock_irq(&nvmeq->q_lock);
1433 nvme_process_cq(nvmeq);
1434 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1435}
1436
1437static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1438 int depth)
b60503ba 1439{
a4aea562 1440 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1441 if (!nvmeq)
1442 return NULL;
1443
e75ec752 1444 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1445 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1446 if (!nvmeq->cqes)
1447 goto free_nvmeq;
b60503ba 1448
e75ec752 1449 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
b60503ba
MW		 1450 &nvmeq->sq_dma_addr, GFP_KERNEL);
1451 if (!nvmeq->sq_cmds)
1452 goto free_cqdma;
1453
e75ec752 1454 nvmeq->q_dmadev = dev->dev;
091b6092 1455 nvmeq->dev = dev;
3193f07b
MW		 1456 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1457 dev->instance, qid);
b60503ba
MW		 1458 spin_lock_init(&nvmeq->q_lock);
1459 nvmeq->cq_head = 0;
82123460 1460 nvmeq->cq_phase = 1;
b80d5ccc 1461 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1462 nvmeq->q_depth = depth;
c30341dc 1463 nvmeq->qid = qid;
a4aea562 1464 dev->queues[qid] = nvmeq;
b60503ba 1465
36a7e993
JD		 1466 /* make sure queue descriptor is set before queue count, for kthread */
1467 mb();
1468 dev->queue_count++;
1469
b60503ba
MW		 1470 return nvmeq;
1471
1472 free_cqdma:
e75ec752 1473 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1474 nvmeq->cq_dma_addr);
1475 free_nvmeq:
1476 kfree(nvmeq);
1477 return NULL;
1478}
1479
3001082c
MW		 1480static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1481 const char *name)
1482{
58ffacb5
MW		 1483 if (use_threaded_interrupts)
1484 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1485 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1486 name, nvmeq);
3001082c 1487 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1488 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1489}
1490
22404274 1491static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1492{
22404274 1493 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1494
7be50e93 1495 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1496 nvmeq->sq_tail = 0;
1497 nvmeq->cq_head = 0;
1498 nvmeq->cq_phase = 1;
b80d5ccc 1499 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1500 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1501 dev->online_queues++;
7be50e93 1502 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1503}
1504
1505static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1506{
1507 struct nvme_dev *dev = nvmeq->dev;
1508 int result;
3f85d50b 1509
2b25d981 1510 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1511 result = adapter_alloc_cq(dev, qid, nvmeq);
1512 if (result < 0)
22404274 1513 return result;
b60503ba
MW		 1514
1515 result = adapter_alloc_sq(dev, qid, nvmeq);
1516 if (result < 0)
1517 goto release_cq;
1518
3193f07b 1519 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1520 if (result < 0)
1521 goto release_sq;
1522
22404274 1523 nvme_init_queue(nvmeq, qid);
22404274 1524 return result;
b60503ba
MW		 1525
1526 release_sq:
1527 adapter_delete_sq(dev, qid);
1528 release_cq:
1529 adapter_delete_cq(dev, qid);
22404274 1530 return result;
b60503ba
MW		 1531}
1532
ba47e386
MW		 1533static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1534{
1535 unsigned long timeout;
1536 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1537
1538 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1539
1540 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1541 msleep(100);
1542 if (fatal_signal_pending(current))
1543 return -EINTR;
1544 if (time_after(jiffies, timeout)) {
e75ec752 1545 dev_err(dev->dev,
27e8166c
MW		 1546 "Device not ready; aborting %s\n", enabled ?
1547 "initialisation" : "reset");
ba47e386
MW		 1548 return -ENODEV;
1549 }
1550 }
1551
1552 return 0;
1553}
1554
1555/*
1556 * If the device has been passed off to us in an enabled state, just clear
1557 * the enabled bit. The spec says we should set the 'shutdown notification
1558 * bits', but doing so may cause the device to complete commands to the
1559 * admin queue ... and we don't know what memory that might be pointing at!
1560 */
1561static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1562{
01079522
DM		 1563 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1564 dev->ctrl_config &= ~NVME_CC_ENABLE;
1565 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1566
ba47e386
MW		 1567 return nvme_wait_ready(dev, cap, false);
1568}
1569
1570static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1571{
01079522
DM		 1572 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1573 dev->ctrl_config |= NVME_CC_ENABLE;
1574 writel(dev->ctrl_config, &dev->bar->cc);
1575
ba47e386
MW		 1576 return nvme_wait_ready(dev, cap, true);
1577}
1578
1894d8f1
KB		 1579static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1580{
1581 unsigned long timeout;
1894d8f1 1582
01079522
DM		 1583 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1584 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1585
1586 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1587
2484f407 1588 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1589 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1590 NVME_CSTS_SHST_CMPLT) {
1591 msleep(100);
1592 if (fatal_signal_pending(current))
1593 return -EINTR;
1594 if (time_after(jiffies, timeout)) {
e75ec752 1595 dev_err(dev->dev,
1894d8f1
KB		 1596 "Device shutdown incomplete; abort shutdown\n");
1597 return -ENODEV;
1598 }
1599 }
1600
1601 return 0;
1602}
1603
a4aea562 1604static struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1605 .queue_rq = nvme_queue_rq,
a4aea562
MB		 1606 .map_queue = blk_mq_map_queue,
1607 .init_hctx = nvme_admin_init_hctx,
1608 .init_request = nvme_admin_init_request,
1609 .timeout = nvme_timeout,
1610};
1611
1612static struct blk_mq_ops nvme_mq_ops = {
1613 .queue_rq = nvme_queue_rq,
1614 .map_queue = blk_mq_map_queue,
1615 .init_hctx = nvme_init_hctx,
1616 .init_request = nvme_init_request,
1617 .timeout = nvme_timeout,
1618};
1619
ea191d2f
KB		 1620static void nvme_dev_remove_admin(struct nvme_dev *dev)
1621{
1622 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1623 blk_cleanup_queue(dev->admin_q);
1624 blk_mq_free_tag_set(&dev->admin_tagset);
1625 }
1626}
1627
a4aea562
MB		 1628static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1629{
1630 if (!dev->admin_q) {
1631 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1632 dev->admin_tagset.nr_hw_queues = 1;
1633 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1efccc9d 1634 dev->admin_tagset.reserved_tags = 1;
a4aea562 1635 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1636 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
ac3dd5bd 1637 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1638 dev->admin_tagset.driver_data = dev;
1639
1640 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1641 return -ENOMEM;
1642
1643 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1644 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1645 blk_mq_free_tag_set(&dev->admin_tagset);
1646 return -ENOMEM;
1647 }
ea191d2f
KB		 1648 if (!blk_get_queue(dev->admin_q)) {
1649 nvme_dev_remove_admin(dev);
1650 return -ENODEV;
1651 }
0fb59cbc
KB		 1652 } else
1653 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1654
1655 return 0;
1656}
1657
8d85fce7 1658static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1659{
ba47e386 1660 int result;
b60503ba 1661 u32 aqa;
ba47e386 1662 u64 cap = readq(&dev->bar->cap);
b60503ba 1663 struct nvme_queue *nvmeq;
1d090624
KB		 1664 unsigned page_shift = PAGE_SHIFT;
1665 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1666 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1667
1668 if (page_shift < dev_page_min) {
e75ec752 1669 dev_err(dev->dev,
1d090624
KB		 1670 "Minimum device page size (%u) too large for "
1671 "host (%u)\n", 1 << dev_page_min,
1672 1 << page_shift);
1673 return -ENODEV;
1674 }
1675 if (page_shift > dev_page_max) {
e75ec752 1676 dev_info(dev->dev,
1d090624
KB		 1677 "Device maximum page size (%u) smaller than "
1678 "host (%u); enabling work-around\n",
1679 1 << dev_page_max, 1 << page_shift);
1680 page_shift = dev_page_max;
1681 }
b60503ba 1682
ba47e386
MW		 1683 result = nvme_disable_ctrl(dev, cap);
1684 if (result < 0)
1685 return result;
b60503ba 1686
a4aea562 1687 nvmeq = dev->queues[0];
cd638946 1688 if (!nvmeq) {
2b25d981 1689 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1690 if (!nvmeq)
1691 return -ENOMEM;
cd638946 1692 }
b60503ba
MW		 1693
1694 aqa = nvmeq->q_depth - 1;
1695 aqa |= aqa << 16;
1696
1d090624
KB		 1697 dev->page_size = 1 << page_shift;
1698
01079522 1699 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1700 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1701 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1702 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1703
1704 writel(aqa, &dev->bar->aqa);
1705 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1706 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1707
ba47e386 1708 result = nvme_enable_ctrl(dev, cap);
025c557a 1709 if (result)
a4aea562
MB		 1710 goto free_nvmeq;
1711
2b25d981 1712 nvmeq->cq_vector = 0;
3193f07b 1713 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1714 if (result)
0fb59cbc 1715 goto free_nvmeq;
025c557a 1716
b60503ba 1717 return result;
a4aea562 1718
a4aea562
MB		 1719 free_nvmeq:
1720 nvme_free_queues(dev, 0);
1721 return result;
b60503ba
MW		 1722}
1723
a53295b6
MW		 1724static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1725{
1726 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1727 struct nvme_user_io io;
1728 struct nvme_command c;
d29ec824 1729 unsigned length, meta_len;
a67a9513 1730 int status, write;
a67a9513
KB		 1731 dma_addr_t meta_dma = 0;
1732 void *meta = NULL;
a53295b6
MW		 1733
1734 if (copy_from_user(&io, uio, sizeof(io)))
1735 return -EFAULT;
6c7d4945
MW		 1736
1737 switch (io.opcode) {
1738 case nvme_cmd_write:
1739 case nvme_cmd_read:
6bbf1acd 1740 case nvme_cmd_compare:
6413214c 1741 break;
6c7d4945 1742 default:
6bbf1acd 1743 return -EINVAL;
6c7d4945
MW		 1744 }
1745
d29ec824
CH		 1746 length = (io.nblocks + 1) << ns->lba_shift;
1747 meta_len = (io.nblocks + 1) * ns->ms;
1748 write = io.opcode & 1;
a53295b6 1749
a67a9513 1750 if (meta_len) {
d29ec824
CH		 1751 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1752 return -EINVAL;
1753
1754 if (ns->ext) {
1755 length += meta_len;
1756 meta_len = 0;
1757 }
1758
e75ec752 1759 meta = dma_alloc_coherent(dev->dev, meta_len,
a67a9513
KB		 1760 &meta_dma, GFP_KERNEL);
1761 if (!meta) {
1762 status = -ENOMEM;
1763 goto unmap;
1764 }
1765 if (write) {
1766 if (copy_from_user(meta, (void __user *)io.metadata,
1767 meta_len)) {
1768 status = -EFAULT;
1769 goto unmap;
1770 }
1771 }
1772 }
1773
a53295b6
MW		 1774 memset(&c, 0, sizeof(c));
1775 c.rw.opcode = io.opcode;
1776 c.rw.flags = io.flags;
6c7d4945 1777 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1778 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1779 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1780 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1781 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1782 c.rw.reftag = cpu_to_le32(io.reftag);
1783 c.rw.apptag = cpu_to_le16(io.apptag);
1784 c.rw.appmask = cpu_to_le16(io.appmask);
a67a9513 1785 c.rw.metadata = cpu_to_le64(meta_dma);
d29ec824
CH		 1786
1787 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
1788 (void __user *)io.addr, length, NULL, 0);
f410c680 1789 unmap:
a67a9513
KB		 1790 if (meta) {
1791 if (status == NVME_SC_SUCCESS && !write) {
1792 if (copy_to_user((void __user *)io.metadata, meta,
1793 meta_len))
1794 status = -EFAULT;
1795 }
e75ec752 1796 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
f410c680 1797 }
a53295b6
MW		 1798 return status;
1799}
1800
a4aea562
MB		 1801static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1802 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1803{
7963e521 1804 struct nvme_passthru_cmd cmd;
6ee44cdc 1805 struct nvme_command c;
d29ec824
CH		 1806 unsigned timeout = 0;
1807 int status;
6ee44cdc 1808
6bbf1acd
MW		 1809 if (!capable(CAP_SYS_ADMIN))
1810 return -EACCES;
1811 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1812 return -EFAULT;
6ee44cdc
MW		 1813
1814 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1815 c.common.opcode = cmd.opcode;
1816 c.common.flags = cmd.flags;
1817 c.common.nsid = cpu_to_le32(cmd.nsid);
1818 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1819 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1820 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1821 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1822 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1823 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1824 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1825 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1826
d29ec824
CH		 1827 if (cmd.timeout_ms)
1828 timeout = msecs_to_jiffies(cmd.timeout_ms);
f705f837
CH		 1829
1830 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
d29ec824
CH		 1831 NULL, (void __user *)cmd.addr, cmd.data_len,
1832 &cmd.result, timeout);
1833 if (status >= 0) {
1834 if (put_user(cmd.result, &ucmd->result))
1835 return -EFAULT;
6bbf1acd 1836 }
f4f117f6 1837
6ee44cdc
MW		 1838 return status;
1839}
1840
b60503ba
MW		 1841static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1842 unsigned long arg)
1843{
1844 struct nvme_ns *ns = bdev->bd_disk->private_data;
1845
1846 switch (cmd) {
6bbf1acd 1847 case NVME_IOCTL_ID:
c3bfe717 1848 force_successful_syscall_return();
6bbf1acd
MW		 1849 return ns->ns_id;
1850 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1851 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1852 case NVME_IOCTL_IO_CMD:
a4aea562 1853 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1854 case NVME_IOCTL_SUBMIT_IO:
1855 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1856 case SG_GET_VERSION_NUM:
1857 return nvme_sg_get_version_num((void __user *)arg);
1858 case SG_IO:
1859 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1860 default:
1861 return -ENOTTY;
1862 }
1863}
1864
320a3827
KB		 1865#ifdef CONFIG_COMPAT
1866static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1867 unsigned int cmd, unsigned long arg)
1868{
320a3827
KB		 1869 switch (cmd) {
1870 case SG_IO:
e179729a 1871 return -ENOIOCTLCMD;
320a3827
KB		 1872 }
1873 return nvme_ioctl(bdev, mode, cmd, arg);
1874}
1875#else
1876#define nvme_compat_ioctl NULL
1877#endif
1878
9ac27090
KB		 1879static int nvme_open(struct block_device *bdev, fmode_t mode)
1880{
9e60352c
KB		 1881 int ret = 0;
1882 struct nvme_ns *ns;
9ac27090 1883
9e60352c
KB		 1884 spin_lock(&dev_list_lock);
1885 ns = bdev->bd_disk->private_data;
1886 if (!ns)
1887 ret = -ENXIO;
1888 else if (!kref_get_unless_zero(&ns->dev->kref))
1889 ret = -ENXIO;
1890 spin_unlock(&dev_list_lock);
1891
1892 return ret;
9ac27090
KB		 1893}
1894
1895static void nvme_free_dev(struct kref *kref);
1896
1897static void nvme_release(struct gendisk *disk, fmode_t mode)
1898{
1899 struct nvme_ns *ns = disk->private_data;
1900 struct nvme_dev *dev = ns->dev;
1901
1902 kref_put(&dev->kref, nvme_free_dev);
1903}
1904
4cc09e2d
KB		 1905static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1906{
1907 /* some standard values */
1908 geo->heads = 1 << 6;
1909 geo->sectors = 1 << 5;
1910 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1911 return 0;
1912}
1913
e1e5e564
KB		 1914static void nvme_config_discard(struct nvme_ns *ns)
1915{
1916 u32 logical_block_size = queue_logical_block_size(ns->queue);
1917 ns->queue->limits.discard_zeroes_data = 0;
1918 ns->queue->limits.discard_alignment = logical_block_size;
1919 ns->queue->limits.discard_granularity = logical_block_size;
1920 ns->queue->limits.max_discard_sectors = 0xffffffff;
1921 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1922}
1923
1b9dbf7f
KB		 1924static int nvme_revalidate_disk(struct gendisk *disk)
1925{
1926 struct nvme_ns *ns = disk->private_data;
1927 struct nvme_dev *dev = ns->dev;
1928 struct nvme_id_ns *id;
a67a9513
KB		 1929 u8 lbaf, pi_type;
1930 u16 old_ms;
e1e5e564 1931 unsigned short bs;
1b9dbf7f 1932
d29ec824 1933 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
a5768aa8
KB		 1934 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
1935 dev->instance, ns->ns_id);
1936 return -ENODEV;
1937 }
1938 if (id->ncap == 0) {
1939 kfree(id);
1940 return -ENODEV;
1b9dbf7f
KB		 1941 }
1942
e1e5e564
KB		 1943 old_ms = ns->ms;
1944 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1b9dbf7f 1945 ns->lba_shift = id->lbaf[lbaf].ds;
e1e5e564 1946 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
a67a9513 1947 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
e1e5e564
KB		 1948
1949 /*
1950 * If identify namespace failed, use default 512 byte block size so
1951 * block layer can use before failing read/write for 0 capacity.
1952 */
1953 if (ns->lba_shift == 0)
1954 ns->lba_shift = 9;
1955 bs = 1 << ns->lba_shift;
1956
1957 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
1958 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
1959 id->dps & NVME_NS_DPS_PI_MASK : 0;
1960
52b68d7e
KB		 1961 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
1962 ns->ms != old_ms ||
e1e5e564 1963 bs != queue_logical_block_size(disk->queue) ||
a67a9513 1964 (ns->ms && ns->ext)))
e1e5e564
KB		 1965 blk_integrity_unregister(disk);
1966
1967 ns->pi_type = pi_type;
1968 blk_queue_logical_block_size(ns->queue, bs);
1969
52b68d7e 1970 if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
a67a9513 1971 !ns->ext)
e1e5e564
KB		 1972 nvme_init_integrity(ns);
1973
a5768aa8 1974 if (ns->ms && !blk_get_integrity(disk))
e1e5e564
KB		 1975 set_capacity(disk, 0);
1976 else
1977 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1978
1979 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1980 nvme_config_discard(ns);
1b9dbf7f 1981
d29ec824 1982 kfree(id);
1b9dbf7f
KB		 1983 return 0;
1984}
1985
b60503ba
MW		 1986static const struct block_device_operations nvme_fops = {
1987 .owner = THIS_MODULE,
1988 .ioctl = nvme_ioctl,
320a3827 1989 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1990 .open = nvme_open,
1991 .release = nvme_release,
4cc09e2d 1992 .getgeo = nvme_getgeo,
1b9dbf7f 1993 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 1994};
1995
1fa6aead
MW		 1996static int nvme_kthread(void *data)
1997{
d4b4ff8e 1998 struct nvme_dev *dev, *next;
1fa6aead
MW		 1999
2000 while (!kthread_should_stop()) {
564a232c 2001 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 2002 spin_lock(&dev_list_lock);
d4b4ff8e 2003 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 2004 int i;
07836e65 2005 if (readl(&dev->bar->csts) & NVME_CSTS_CFS) {
d4b4ff8e
KB		 2006 if (work_busy(&dev->reset_work))
2007 continue;
2008 list_del_init(&dev->node);
e75ec752 2009 dev_warn(dev->dev,
a4aea562
MB		 2010 "Failed status: %x, reset controller\n",
2011 readl(&dev->bar->csts));
9ca97374 2012 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 2013 queue_work(nvme_workq, &dev->reset_work);
2014 continue;
2015 }
1fa6aead 2016 for (i = 0; i < dev->queue_count; i++) {
a4aea562 2017 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 2018 if (!nvmeq)
2019 continue;
1fa6aead 2020 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 2021 nvme_process_cq(nvmeq);
6fccf938
KB		 2022
2023 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 2024 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 2025 break;
2026 dev->event_limit--;
2027 }
1fa6aead
MW		 2028 spin_unlock_irq(&nvmeq->q_lock);
2029 }
2030 }
2031 spin_unlock(&dev_list_lock);
acb7aa0d 2032 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 2033 }
2034 return 0;
2035}
2036
e1e5e564 2037static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
b60503ba
MW		 2038{
2039 struct nvme_ns *ns;
2040 struct gendisk *disk;
e75ec752 2041 int node = dev_to_node(dev->dev);
b60503ba 2042
a4aea562 2043 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba 2044 if (!ns)
e1e5e564
KB		 2045 return;
2046
a4aea562 2047 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 2048 if (IS_ERR(ns->queue))
b60503ba 2049 goto out_free_ns;
4eeb9215
MW		 2050 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2051 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 2052 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 2053 ns->dev = dev;
2054 ns->queue->queuedata = ns;
2055
a4aea562 2056 disk = alloc_disk_node(0, node);
b60503ba
MW		 2057 if (!disk)
2058 goto out_free_queue;
a4aea562 2059
5aff9382 2060 ns->ns_id = nsid;
b60503ba 2061 ns->disk = disk;
e1e5e564
KB		 2062 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2063 list_add_tail(&ns->list, &dev->namespaces);
2064
e9ef4636 2065 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 2066 if (dev->max_hw_sectors)
2067 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 2068 if (dev->stripe_size)
2069 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2070 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2071 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 2072
2073 disk->major = nvme_major;
469071a3 2074 disk->first_minor = 0;
b60503ba
MW		 2075 disk->fops = &nvme_fops;
2076 disk->private_data = ns;
2077 disk->queue = ns->queue;
b3fffdef 2078 disk->driverfs_dev = dev->device;
469071a3 2079 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2080 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba 2081
e1e5e564
KB		 2082 /*
2083 * Initialize capacity to 0 until we establish the namespace format and
2084 * setup integrity extentions if necessary. The revalidate_disk after
2085 * add_disk allows the driver to register with integrity if the format
2086 * requires it.
2087 */
2088 set_capacity(disk, 0);
a5768aa8
KB		 2089 if (nvme_revalidate_disk(ns->disk))
2090 goto out_free_disk;
2091
e1e5e564
KB		 2092 add_disk(ns->disk);
2093 if (ns->ms)
2094 revalidate_disk(ns->disk);
2095 return;
a5768aa8
KB		 2096 out_free_disk:
2097 kfree(disk);
2098 list_del(&ns->list);
b60503ba
MW		 2099 out_free_queue:
2100 blk_cleanup_queue(ns->queue);
2101 out_free_ns:
2102 kfree(ns);
b60503ba
MW		 2103}
2104
42f61420
KB		 2105static void nvme_create_io_queues(struct nvme_dev *dev)
2106{
a4aea562 2107 unsigned i;
42f61420 2108
a4aea562 2109 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2110 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2111 break;
2112
a4aea562
MB		 2113 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2114 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 2115 break;
2116}
2117
b3b06812 2118static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2119{
2120 int status;
2121 u32 result;
b3b06812 2122 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2123
df348139 2124 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2125 &result);
27e8166c
MW		 2126 if (status < 0)
2127 return status;
2128 if (status > 0) {
e75ec752 2129 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
badc34d4 2130 return 0;
27e8166c 2131 }
b60503ba
MW		 2132 return min(result & 0xffff, result >> 16) + 1;
2133}
2134
9d713c2b
KB		 2135static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2136{
b80d5ccc 2137 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2138}
2139
8d85fce7 2140static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2141{
a4aea562 2142 struct nvme_queue *adminq = dev->queues[0];
e75ec752 2143 struct pci_dev *pdev = to_pci_dev(dev->dev);
42f61420 2144 int result, i, vecs, nr_io_queues, size;
b60503ba 2145
42f61420 2146 nr_io_queues = num_possible_cpus();
b348b7d5 2147 result = set_queue_count(dev, nr_io_queues);
badc34d4 2148 if (result <= 0)
1b23484b 2149 return result;
b348b7d5
MW		 2150 if (result < nr_io_queues)
2151 nr_io_queues = result;
b60503ba 2152
9d713c2b
KB		 2153 size = db_bar_size(dev, nr_io_queues);
2154 if (size > 8192) {
f1938f6e 2155 iounmap(dev->bar);
9d713c2b
KB		 2156 do {
2157 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2158 if (dev->bar)
2159 break;
2160 if (!--nr_io_queues)
2161 return -ENOMEM;
2162 size = db_bar_size(dev, nr_io_queues);
2163 } while (1);
f1938f6e 2164 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2165 adminq->q_db = dev->dbs;
f1938f6e
MW		 2166 }
2167
9d713c2b 2168 /* Deregister the admin queue's interrupt */
3193f07b 2169 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2170
e32efbfc
JA		 2171 /*
2172 * If we enable msix early due to not intx, disable it again before
2173 * setting up the full range we need.
2174 */
2175 if (!pdev->irq)
2176 pci_disable_msix(pdev);
2177
be577fab 2178 for (i = 0; i < nr_io_queues; i++)
1b23484b 2179 dev->entry[i].entry = i;
be577fab
AG		 2180 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2181 if (vecs < 0) {
2182 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2183 if (vecs < 0) {
2184 vecs = 1;
2185 } else {
2186 for (i = 0; i < vecs; i++)
2187 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2188 }
2189 }
2190
063a8096
MW		 2191 /*
2192 * Should investigate if there's a performance win from allocating
2193 * more queues than interrupt vectors; it might allow the submission
2194 * path to scale better, even if the receive path is limited by the
2195 * number of interrupts.
2196 */
2197 nr_io_queues = vecs;
42f61420 2198 dev->max_qid = nr_io_queues;
063a8096 2199
3193f07b 2200 result = queue_request_irq(dev, adminq, adminq->irqname);
a4aea562 2201 if (result)
22404274 2202 goto free_queues;
1b23484b 2203
cd638946 2204 /* Free previously allocated queues that are no longer usable */
42f61420 2205 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2206 nvme_create_io_queues(dev);
9ecdc946 2207
22404274 2208 return 0;
b60503ba 2209
22404274 2210 free_queues:
a1a5ef99 2211 nvme_free_queues(dev, 1);
22404274 2212 return result;
b60503ba
MW		 2213}
2214
a5768aa8
KB		 2215static void nvme_free_namespace(struct nvme_ns *ns)
2216{
2217 list_del(&ns->list);
2218
2219 spin_lock(&dev_list_lock);
2220 ns->disk->private_data = NULL;
2221 spin_unlock(&dev_list_lock);
2222
2223 put_disk(ns->disk);
2224 kfree(ns);
2225}
2226
2227static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2228{
2229 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2230 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2231
2232 return nsa->ns_id - nsb->ns_id;
2233}
2234
2235static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2236{
2237 struct nvme_ns *ns;
2238
2239 list_for_each_entry(ns, &dev->namespaces, list) {
2240 if (ns->ns_id == nsid)
2241 return ns;
2242 if (ns->ns_id > nsid)
2243 break;
2244 }
2245 return NULL;
2246}
2247
2248static inline bool nvme_io_incapable(struct nvme_dev *dev)
2249{
2250 return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
2251 dev->online_queues < 2);
2252}
2253
2254static void nvme_ns_remove(struct nvme_ns *ns)
2255{
2256 bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2257
2258 if (kill)
2259 blk_set_queue_dying(ns->queue);
2260 if (ns->disk->flags & GENHD_FL_UP) {
2261 if (blk_get_integrity(ns->disk))
2262 blk_integrity_unregister(ns->disk);
2263 del_gendisk(ns->disk);
2264 }
2265 if (kill || !blk_queue_dying(ns->queue)) {
2266 blk_mq_abort_requeue_list(ns->queue);
2267 blk_cleanup_queue(ns->queue);
2268 }
2269}
2270
2271static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2272{
2273 struct nvme_ns *ns, *next;
2274 unsigned i;
2275
2276 for (i = 1; i <= nn; i++) {
2277 ns = nvme_find_ns(dev, i);
2278 if (ns) {
2279 if (revalidate_disk(ns->disk)) {
2280 nvme_ns_remove(ns);
2281 nvme_free_namespace(ns);
2282 }
2283 } else
2284 nvme_alloc_ns(dev, i);
2285 }
2286 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2287 if (ns->ns_id > nn) {
2288 nvme_ns_remove(ns);
2289 nvme_free_namespace(ns);
2290 }
2291 }
2292 list_sort(NULL, &dev->namespaces, ns_cmp);
2293}
2294
2295static void nvme_dev_scan(struct work_struct *work)
2296{
2297 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2298 struct nvme_id_ctrl *ctrl;
2299
2300 if (!dev->tagset.tags)
2301 return;
2302 if (nvme_identify_ctrl(dev, &ctrl))
2303 return;
2304 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2305 kfree(ctrl);
2306}
2307
422ef0c7
MW		 2308/*
2309 * Return: error value if an error occurred setting up the queues or calling
2310 * Identify Device. 0 if these succeeded, even if adding some of the
2311 * namespaces failed. At the moment, these failures are silent. TBD which
2312 * failures should be reported.
2313 */
8d85fce7 2314static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2315{
e75ec752 2316 struct pci_dev *pdev = to_pci_dev(dev->dev);
c3bfe717 2317 int res;
a5768aa8 2318 unsigned nn;
51814232 2319 struct nvme_id_ctrl *ctrl;
159b67d7 2320 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2321
d29ec824 2322 res = nvme_identify_ctrl(dev, &ctrl);
b60503ba 2323 if (res) {
e75ec752 2324 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
e1e5e564 2325 return -EIO;
b60503ba
MW		 2326 }
2327
51814232 2328 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2329 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2330 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2331 dev->vwc = ctrl->vwc;
51814232
MW		 2332 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2333 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2334 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2335 if (ctrl->mdts)
8fc23e03 2336 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2337 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2338 (pdev->device == 0x0953) && ctrl->vs[3]) {
2339 unsigned int max_hw_sectors;
2340
159b67d7 2341 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2342 max_hw_sectors = dev->stripe_size >> (shift - 9);
2343 if (dev->max_hw_sectors) {
2344 dev->max_hw_sectors = min(max_hw_sectors,
2345 dev->max_hw_sectors);
2346 } else
2347 dev->max_hw_sectors = max_hw_sectors;
2348 }
d29ec824 2349 kfree(ctrl);
a4aea562
MB		 2350
2351 dev->tagset.ops = &nvme_mq_ops;
2352 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2353 dev->tagset.timeout = NVME_IO_TIMEOUT;
e75ec752 2354 dev->tagset.numa_node = dev_to_node(dev->dev);
a4aea562
MB		 2355 dev->tagset.queue_depth =
2356 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ac3dd5bd 2357 dev->tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 2358 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2359 dev->tagset.driver_data = dev;
2360
2361 if (blk_mq_alloc_tag_set(&dev->tagset))
e1e5e564 2362 return 0;
b60503ba 2363
a5768aa8 2364 schedule_work(&dev->scan_work);
e1e5e564 2365 return 0;
b60503ba
MW		 2366}
2367
0877cb0d
KB		 2368static int nvme_dev_map(struct nvme_dev *dev)
2369{
42f61420 2370 u64 cap;
0877cb0d 2371 int bars, result = -ENOMEM;
e75ec752 2372 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2373
2374 if (pci_enable_device_mem(pdev))
2375 return result;
2376
2377 dev->entry[0].vector = pdev->irq;
2378 pci_set_master(pdev);
2379 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2380 if (!bars)
2381 goto disable_pci;
2382
0877cb0d
KB		 2383 if (pci_request_selected_regions(pdev, bars, "nvme"))
2384 goto disable_pci;
2385
e75ec752
CH		 2386 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2387 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2388 goto disable;
0877cb0d 2389
0877cb0d
KB		 2390 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2391 if (!dev->bar)
2392 goto disable;
e32efbfc 2393
0e53d180
KB		 2394 if (readl(&dev->bar->csts) == -1) {
2395 result = -ENODEV;
2396 goto unmap;
2397 }
e32efbfc
JA		 2398
2399 /*
2400 * Some devices don't advertse INTx interrupts, pre-enable a single
2401 * MSIX vec for setup. We'll adjust this later.
2402 */
2403 if (!pdev->irq) {
2404 result = pci_enable_msix(pdev, dev->entry, 1);
2405 if (result < 0)
2406 goto unmap;
2407 }
2408
42f61420
KB		 2409 cap = readq(&dev->bar->cap);
2410 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2411 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2412 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2413
2414 return 0;
2415
0e53d180
KB		 2416 unmap:
2417 iounmap(dev->bar);
2418 dev->bar = NULL;
0877cb0d
KB		 2419 disable:
2420 pci_release_regions(pdev);
2421 disable_pci:
2422 pci_disable_device(pdev);
2423 return result;
2424}
2425
2426static void nvme_dev_unmap(struct nvme_dev *dev)
2427{
e75ec752
CH		 2428 struct pci_dev *pdev = to_pci_dev(dev->dev);
2429
2430 if (pdev->msi_enabled)
2431 pci_disable_msi(pdev);
2432 else if (pdev->msix_enabled)
2433 pci_disable_msix(pdev);
0877cb0d
KB		 2434
2435 if (dev->bar) {
2436 iounmap(dev->bar);
2437 dev->bar = NULL;
e75ec752 2438 pci_release_regions(pdev);
0877cb0d
KB		 2439 }
2440
e75ec752
CH		 2441 if (pci_is_enabled(pdev))
2442 pci_disable_device(pdev);
0877cb0d
KB		 2443}
2444
4d115420
KB		 2445struct nvme_delq_ctx {
2446 struct task_struct *waiter;
2447 struct kthread_worker *worker;
2448 atomic_t refcount;
2449};
2450
2451static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2452{
2453 dq->waiter = current;
2454 mb();
2455
2456 for (;;) {
2457 set_current_state(TASK_KILLABLE);
2458 if (!atomic_read(&dq->refcount))
2459 break;
2460 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2461 fatal_signal_pending(current)) {
0fb59cbc
KB		 2462 /*
2463 * Disable the controller first since we can't trust it
2464 * at this point, but leave the admin queue enabled
2465 * until all queue deletion requests are flushed.
2466 * FIXME: This may take a while if there are more h/w
2467 * queues than admin tags.
2468 */
4d115420 2469 set_current_state(TASK_RUNNING);
4d115420 2470 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2471 nvme_clear_queue(dev->queues[0]);
4d115420 2472 flush_kthread_worker(dq->worker);
0fb59cbc 2473 nvme_disable_queue(dev, 0);
4d115420
KB		 2474 return;
2475 }
2476 }
2477 set_current_state(TASK_RUNNING);
2478}
2479
2480static void nvme_put_dq(struct nvme_delq_ctx *dq)
2481{
2482 atomic_dec(&dq->refcount);
2483 if (dq->waiter)
2484 wake_up_process(dq->waiter);
2485}
2486
2487static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2488{
2489 atomic_inc(&dq->refcount);
2490 return dq;
2491}
2492
2493static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2494{
2495 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
4d115420
KB		 2496 nvme_put_dq(dq);
2497}
2498
2499static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2500 kthread_work_func_t fn)
2501{
2502 struct nvme_command c;
2503
2504 memset(&c, 0, sizeof(c));
2505 c.delete_queue.opcode = opcode;
2506 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2507
2508 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2509 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2510 ADMIN_TIMEOUT);
4d115420
KB		 2511}
2512
2513static void nvme_del_cq_work_handler(struct kthread_work *work)
2514{
2515 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2516 cmdinfo.work);
2517 nvme_del_queue_end(nvmeq);
2518}
2519
2520static int nvme_delete_cq(struct nvme_queue *nvmeq)
2521{
2522 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2523 nvme_del_cq_work_handler);
2524}
2525
2526static void nvme_del_sq_work_handler(struct kthread_work *work)
2527{
2528 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2529 cmdinfo.work);
2530 int status = nvmeq->cmdinfo.status;
2531
2532 if (!status)
2533 status = nvme_delete_cq(nvmeq);
2534 if (status)
2535 nvme_del_queue_end(nvmeq);
2536}
2537
2538static int nvme_delete_sq(struct nvme_queue *nvmeq)
2539{
2540 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2541 nvme_del_sq_work_handler);
2542}
2543
2544static void nvme_del_queue_start(struct kthread_work *work)
2545{
2546 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2547 cmdinfo.work);
4d115420
KB		 2548 if (nvme_delete_sq(nvmeq))
2549 nvme_del_queue_end(nvmeq);
2550}
2551
2552static void nvme_disable_io_queues(struct nvme_dev *dev)
2553{
2554 int i;
2555 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2556 struct nvme_delq_ctx dq;
2557 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2558 &worker, "nvme%d", dev->instance);
2559
2560 if (IS_ERR(kworker_task)) {
e75ec752 2561 dev_err(dev->dev,
4d115420
KB		 2562 "Failed to create queue del task\n");
2563 for (i = dev->queue_count - 1; i > 0; i--)
2564 nvme_disable_queue(dev, i);
2565 return;
2566 }
2567
2568 dq.waiter = NULL;
2569 atomic_set(&dq.refcount, 0);
2570 dq.worker = &worker;
2571 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2572 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2573
2574 if (nvme_suspend_queue(nvmeq))
2575 continue;
2576 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2577 nvmeq->cmdinfo.worker = dq.worker;
2578 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2579 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2580 }
2581 nvme_wait_dq(&dq, dev);
2582 kthread_stop(kworker_task);
2583}
2584
b9afca3e
DM		 2585/*
2586* Remove the node from the device list and check
2587* for whether or not we need to stop the nvme_thread.
2588*/
2589static void nvme_dev_list_remove(struct nvme_dev *dev)
2590{
2591 struct task_struct *tmp = NULL;
2592
2593 spin_lock(&dev_list_lock);
2594 list_del_init(&dev->node);
2595 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2596 tmp = nvme_thread;
2597 nvme_thread = NULL;
2598 }
2599 spin_unlock(&dev_list_lock);
2600
2601 if (tmp)
2602 kthread_stop(tmp);
2603}
2604
c9d3bf88
KB		 2605static void nvme_freeze_queues(struct nvme_dev *dev)
2606{
2607 struct nvme_ns *ns;
2608
2609 list_for_each_entry(ns, &dev->namespaces, list) {
2610 blk_mq_freeze_queue_start(ns->queue);
2611
cddcd72b 2612 spin_lock_irq(ns->queue->queue_lock);
c9d3bf88 2613 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
cddcd72b 2614 spin_unlock_irq(ns->queue->queue_lock);
c9d3bf88
KB		 2615
2616 blk_mq_cancel_requeue_work(ns->queue);
2617 blk_mq_stop_hw_queues(ns->queue);
2618 }
2619}
2620
2621static void nvme_unfreeze_queues(struct nvme_dev *dev)
2622{
2623 struct nvme_ns *ns;
2624
2625 list_for_each_entry(ns, &dev->namespaces, list) {
2626 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2627 blk_mq_unfreeze_queue(ns->queue);
2628 blk_mq_start_stopped_hw_queues(ns->queue, true);
2629 blk_mq_kick_requeue_list(ns->queue);
2630 }
2631}
2632
f0b50732 2633static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2634{
22404274 2635 int i;
7c1b2450 2636 u32 csts = -1;
22404274 2637
b9afca3e 2638 nvme_dev_list_remove(dev);
1fa6aead 2639
c9d3bf88
KB		 2640 if (dev->bar) {
2641 nvme_freeze_queues(dev);
7c1b2450 2642 csts = readl(&dev->bar->csts);
c9d3bf88 2643 }
7c1b2450 2644 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2645 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2646 struct nvme_queue *nvmeq = dev->queues[i];
4d115420 2647 nvme_suspend_queue(nvmeq);
4d115420
KB		 2648 }
2649 } else {
2650 nvme_disable_io_queues(dev);
1894d8f1 2651 nvme_shutdown_ctrl(dev);
4d115420
KB		 2652 nvme_disable_queue(dev, 0);
2653 }
f0b50732 2654 nvme_dev_unmap(dev);
07836e65
KB		 2655
2656 for (i = dev->queue_count - 1; i >= 0; i--)
2657 nvme_clear_queue(dev->queues[i]);
f0b50732
KB		 2658}
2659
2660static void nvme_dev_remove(struct nvme_dev *dev)
2661{
9ac27090 2662 struct nvme_ns *ns;
f0b50732 2663
a5768aa8
KB		 2664 list_for_each_entry(ns, &dev->namespaces, list)
2665 nvme_ns_remove(ns);
b60503ba
MW		 2666}
2667
091b6092
MW		 2668static int nvme_setup_prp_pools(struct nvme_dev *dev)
2669{
e75ec752 2670 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2671 PAGE_SIZE, PAGE_SIZE, 0);
2672 if (!dev->prp_page_pool)
2673 return -ENOMEM;
2674
99802a7a 2675 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2676 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2677 256, 256, 0);
2678 if (!dev->prp_small_pool) {
2679 dma_pool_destroy(dev->prp_page_pool);
2680 return -ENOMEM;
2681 }
091b6092
MW		 2682 return 0;
2683}
2684
2685static void nvme_release_prp_pools(struct nvme_dev *dev)
2686{
2687 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2688 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2689}
2690
cd58ad7d
QSA		 2691static DEFINE_IDA(nvme_instance_ida);
2692
2693static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2694{
cd58ad7d
QSA		 2695 int instance, error;
2696
2697 do {
2698 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2699 return -ENODEV;
2700
2701 spin_lock(&dev_list_lock);
2702 error = ida_get_new(&nvme_instance_ida, &instance);
2703 spin_unlock(&dev_list_lock);
2704 } while (error == -EAGAIN);
2705
2706 if (error)
2707 return -ENODEV;
2708
2709 dev->instance = instance;
2710 return 0;
b60503ba
MW		 2711}
2712
2713static void nvme_release_instance(struct nvme_dev *dev)
2714{
cd58ad7d
QSA		 2715 spin_lock(&dev_list_lock);
2716 ida_remove(&nvme_instance_ida, dev->instance);
2717 spin_unlock(&dev_list_lock);
b60503ba
MW		 2718}
2719
9ac27090
KB		 2720static void nvme_free_namespaces(struct nvme_dev *dev)
2721{
2722 struct nvme_ns *ns, *next;
2723
a5768aa8
KB		 2724 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
2725 nvme_free_namespace(ns);
9ac27090
KB		 2726}
2727
5e82e952
KB		 2728static void nvme_free_dev(struct kref *kref)
2729{
2730 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2731
e75ec752 2732 put_device(dev->dev);
b3fffdef 2733 put_device(dev->device);
9ac27090 2734 nvme_free_namespaces(dev);
285dffc9 2735 nvme_release_instance(dev);
a4aea562 2736 blk_mq_free_tag_set(&dev->tagset);
ea191d2f 2737 blk_put_queue(dev->admin_q);
5e82e952
KB		 2738 kfree(dev->queues);
2739 kfree(dev->entry);
2740 kfree(dev);
2741}
2742
2743static int nvme_dev_open(struct inode *inode, struct file *f)
2744{
b3fffdef
KB		 2745 struct nvme_dev *dev;
2746 int instance = iminor(inode);
2747 int ret = -ENODEV;
2748
2749 spin_lock(&dev_list_lock);
2750 list_for_each_entry(dev, &dev_list, node) {
2751 if (dev->instance == instance) {
2e1d8448
KB		 2752 if (!dev->admin_q) {
2753 ret = -EWOULDBLOCK;
2754 break;
2755 }
b3fffdef
KB		 2756 if (!kref_get_unless_zero(&dev->kref))
2757 break;
2758 f->private_data = dev;
2759 ret = 0;
2760 break;
2761 }
2762 }
2763 spin_unlock(&dev_list_lock);
2764
2765 return ret;
5e82e952
KB		 2766}
2767
2768static int nvme_dev_release(struct inode *inode, struct file *f)
2769{
2770 struct nvme_dev *dev = f->private_data;
2771 kref_put(&dev->kref, nvme_free_dev);
2772 return 0;
2773}
2774
2775static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2776{
2777 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2778 struct nvme_ns *ns;
2779
5e82e952
KB		 2780 switch (cmd) {
2781 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2782 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2783 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2784 if (list_empty(&dev->namespaces))
2785 return -ENOTTY;
2786 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2787 return nvme_user_cmd(dev, ns, (void __user *)arg);
4cc06521
KB		 2788 case NVME_IOCTL_RESET:
2789 dev_warn(dev->dev, "resetting controller\n");
2790 return nvme_reset(dev);
5e82e952
KB		 2791 default:
2792 return -ENOTTY;
2793 }
2794}
2795
2796static const struct file_operations nvme_dev_fops = {
2797 .owner = THIS_MODULE,
2798 .open = nvme_dev_open,
2799 .release = nvme_dev_release,
2800 .unlocked_ioctl = nvme_dev_ioctl,
2801 .compat_ioctl = nvme_dev_ioctl,
2802};
2803
a4aea562
MB		 2804static void nvme_set_irq_hints(struct nvme_dev *dev)
2805{
2806 struct nvme_queue *nvmeq;
2807 int i;
2808
2809 for (i = 0; i < dev->online_queues; i++) {
2810 nvmeq = dev->queues[i];
2811
42483228 2812 if (!nvmeq->tags || !(*nvmeq->tags))
a4aea562
MB		 2813 continue;
2814
2815 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
42483228 2816 blk_mq_tags_cpumask(*nvmeq->tags));
a4aea562
MB		 2817 }
2818}
2819
f0b50732
KB		 2820static int nvme_dev_start(struct nvme_dev *dev)
2821{
2822 int result;
b9afca3e 2823 bool start_thread = false;
f0b50732
KB		 2824
2825 result = nvme_dev_map(dev);
2826 if (result)
2827 return result;
2828
2829 result = nvme_configure_admin_queue(dev);
2830 if (result)
2831 goto unmap;
2832
2833 spin_lock(&dev_list_lock);
b9afca3e
DM		 2834 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2835 start_thread = true;
2836 nvme_thread = NULL;
2837 }
f0b50732
KB		 2838 list_add(&dev->node, &dev_list);
2839 spin_unlock(&dev_list_lock);
2840
b9afca3e
DM		 2841 if (start_thread) {
2842 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2843 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2844 } else
2845 wait_event_killable(nvme_kthread_wait, nvme_thread);
2846
2847 if (IS_ERR_OR_NULL(nvme_thread)) {
2848 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2849 goto disable;
2850 }
a4aea562
MB		 2851
2852 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 2853 result = nvme_alloc_admin_tags(dev);
2854 if (result)
2855 goto disable;
b9afca3e 2856
f0b50732 2857 result = nvme_setup_io_queues(dev);
badc34d4 2858 if (result)
0fb59cbc 2859 goto free_tags;
f0b50732 2860
a4aea562
MB		 2861 nvme_set_irq_hints(dev);
2862
1efccc9d 2863 dev->event_limit = 1;
d82e8bfd 2864 return result;
f0b50732 2865
0fb59cbc
KB		 2866 free_tags:
2867 nvme_dev_remove_admin(dev);
f0b50732 2868 disable:
a1a5ef99 2869 nvme_disable_queue(dev, 0);
b9afca3e 2870 nvme_dev_list_remove(dev);
f0b50732
KB		 2871 unmap:
2872 nvme_dev_unmap(dev);
2873 return result;
2874}
2875
9a6b9458
KB		 2876static int nvme_remove_dead_ctrl(void *arg)
2877{
2878 struct nvme_dev *dev = (struct nvme_dev *)arg;
e75ec752 2879 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2880
2881 if (pci_get_drvdata(pdev))
c81f4975 2882 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2883 kref_put(&dev->kref, nvme_free_dev);
2884 return 0;
2885}
2886
2887static void nvme_remove_disks(struct work_struct *ws)
2888{
9a6b9458
KB		 2889 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2890
5a92e700 2891 nvme_free_queues(dev, 1);
302c6727 2892 nvme_dev_remove(dev);
9a6b9458
KB		 2893}
2894
2895static int nvme_dev_resume(struct nvme_dev *dev)
2896{
2897 int ret;
2898
2899 ret = nvme_dev_start(dev);
badc34d4 2900 if (ret)
9a6b9458 2901 return ret;
badc34d4 2902 if (dev->online_queues < 2) {
9a6b9458 2903 spin_lock(&dev_list_lock);
9ca97374 2904 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2905 queue_work(nvme_workq, &dev->reset_work);
2906 spin_unlock(&dev_list_lock);
c9d3bf88
KB		 2907 } else {
2908 nvme_unfreeze_queues(dev);
a5768aa8 2909 schedule_work(&dev->scan_work);
c9d3bf88 2910 nvme_set_irq_hints(dev);
9a6b9458
KB		 2911 }
2912 return 0;
2913}
2914
2915static void nvme_dev_reset(struct nvme_dev *dev)
2916{
2917 nvme_dev_shutdown(dev);
2918 if (nvme_dev_resume(dev)) {
e75ec752 2919 dev_warn(dev->dev, "Device failed to resume\n");
9a6b9458
KB		 2920 kref_get(&dev->kref);
2921 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2922 dev->instance))) {
e75ec752 2923 dev_err(dev->dev,
9a6b9458
KB		 2924 "Failed to start controller remove task\n");
2925 kref_put(&dev->kref, nvme_free_dev);
2926 }
2927 }
2928}
2929
2930static void nvme_reset_failed_dev(struct work_struct *ws)
2931{
2932 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2933 nvme_dev_reset(dev);
2934}
2935
9ca97374
TH		 2936static void nvme_reset_workfn(struct work_struct *work)
2937{
2938 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2939 dev->reset_workfn(work);
2940}
2941
4cc06521
KB		 2942static int nvme_reset(struct nvme_dev *dev)
2943{
2944 int ret = -EBUSY;
2945
2946 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
2947 return -ENODEV;
2948
2949 spin_lock(&dev_list_lock);
2950 if (!work_pending(&dev->reset_work)) {
2951 dev->reset_workfn = nvme_reset_failed_dev;
2952 queue_work(nvme_workq, &dev->reset_work);
2953 ret = 0;
2954 }
2955 spin_unlock(&dev_list_lock);
2956
2957 if (!ret) {
2958 flush_work(&dev->reset_work);
2959 return 0;
2960 }
2961
2962 return ret;
2963}
2964
2965static ssize_t nvme_sysfs_reset(struct device *dev,
2966 struct device_attribute *attr, const char *buf,
2967 size_t count)
2968{
2969 struct nvme_dev *ndev = dev_get_drvdata(dev);
2970 int ret;
2971
2972 ret = nvme_reset(ndev);
2973 if (ret < 0)
2974 return ret;
2975
2976 return count;
2977}
2978static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
2979
2e1d8448 2980static void nvme_async_probe(struct work_struct *work);
8d85fce7 2981static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2982{
a4aea562 2983 int node, result = -ENOMEM;
b60503ba
MW		 2984 struct nvme_dev *dev;
2985
a4aea562
MB		 2986 node = dev_to_node(&pdev->dev);
2987 if (node == NUMA_NO_NODE)
2988 set_dev_node(&pdev->dev, 0);
2989
2990 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2991 if (!dev)
2992 return -ENOMEM;
a4aea562
MB		 2993 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2994 GFP_KERNEL, node);
b60503ba
MW		 2995 if (!dev->entry)
2996 goto free;
a4aea562
MB		 2997 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2998 GFP_KERNEL, node);
b60503ba
MW		 2999 if (!dev->queues)
3000 goto free;
3001
3002 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 3003 dev->reset_workfn = nvme_reset_failed_dev;
3004 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
e75ec752 3005 dev->dev = get_device(&pdev->dev);
9a6b9458 3006 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 3007 result = nvme_set_instance(dev);
3008 if (result)
a96d4f5c 3009 goto put_pci;
b60503ba 3010
091b6092
MW		 3011 result = nvme_setup_prp_pools(dev);
3012 if (result)
0877cb0d 3013 goto release;
091b6092 3014
fb35e914 3015 kref_init(&dev->kref);
b3fffdef
KB		 3016 dev->device = device_create(nvme_class, &pdev->dev,
3017 MKDEV(nvme_char_major, dev->instance),
3018 dev, "nvme%d", dev->instance);
3019 if (IS_ERR(dev->device)) {
3020 result = PTR_ERR(dev->device);
2e1d8448 3021 goto release_pools;
b3fffdef
KB		 3022 }
3023 get_device(dev->device);
4cc06521
KB		 3024 dev_set_drvdata(dev->device, dev);
3025
3026 result = device_create_file(dev->device, &dev_attr_reset_controller);
3027 if (result)
3028 goto put_dev;
740216fc 3029
e6e96d73 3030 INIT_LIST_HEAD(&dev->node);
a5768aa8 3031 INIT_WORK(&dev->scan_work, nvme_dev_scan);
2e1d8448
KB		 3032 INIT_WORK(&dev->probe_work, nvme_async_probe);
3033 schedule_work(&dev->probe_work);
b60503ba
MW		 3034 return 0;
3035
4cc06521
KB		 3036 put_dev:
3037 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3038 put_device(dev->device);
0877cb0d 3039 release_pools:
091b6092 3040 nvme_release_prp_pools(dev);
0877cb0d
KB		 3041 release:
3042 nvme_release_instance(dev);
a96d4f5c 3043 put_pci:
e75ec752 3044 put_device(dev->dev);
b60503ba
MW		 3045 free:
3046 kfree(dev->queues);
3047 kfree(dev->entry);
3048 kfree(dev);
3049 return result;
3050}
3051
2e1d8448
KB		 3052static void nvme_async_probe(struct work_struct *work)
3053{
3054 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
3055 int result;
3056
3057 result = nvme_dev_start(dev);
3058 if (result)
3059 goto reset;
3060
3061 if (dev->online_queues > 1)
3062 result = nvme_dev_add(dev);
3063 if (result)
3064 goto reset;
3065
3066 nvme_set_irq_hints(dev);
2e1d8448
KB		 3067 return;
3068 reset:
4cc06521 3069 spin_lock(&dev_list_lock);
07836e65
KB		 3070 if (!work_busy(&dev->reset_work)) {
3071 dev->reset_workfn = nvme_reset_failed_dev;
3072 queue_work(nvme_workq, &dev->reset_work);
3073 }
4cc06521 3074 spin_unlock(&dev_list_lock);
2e1d8448
KB		 3075}
3076
f0d54a54
KB		 3077static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3078{
a6739479 3079 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 3080
a6739479
KB		 3081 if (prepare)
3082 nvme_dev_shutdown(dev);
3083 else
3084 nvme_dev_resume(dev);
f0d54a54
KB		 3085}
3086
09ece142
KB		 3087static void nvme_shutdown(struct pci_dev *pdev)
3088{
3089 struct nvme_dev *dev = pci_get_drvdata(pdev);
3090 nvme_dev_shutdown(dev);
3091}
3092
8d85fce7 3093static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3094{
3095 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 3096
3097 spin_lock(&dev_list_lock);
3098 list_del_init(&dev->node);
3099 spin_unlock(&dev_list_lock);
3100
3101 pci_set_drvdata(pdev, NULL);
2e1d8448 3102 flush_work(&dev->probe_work);
9a6b9458 3103 flush_work(&dev->reset_work);
a5768aa8 3104 flush_work(&dev->scan_work);
4cc06521 3105 device_remove_file(dev->device, &dev_attr_reset_controller);
9a6b9458 3106 nvme_dev_shutdown(dev);
c9d3bf88 3107 nvme_dev_remove(dev);
a4aea562 3108 nvme_dev_remove_admin(dev);
b3fffdef 3109 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
a1a5ef99 3110 nvme_free_queues(dev, 0);
9a6b9458 3111 nvme_release_prp_pools(dev);
5e82e952 3112 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 3113}
3114
3115/* These functions are yet to be implemented */
3116#define nvme_error_detected NULL
3117#define nvme_dump_registers NULL
3118#define nvme_link_reset NULL
3119#define nvme_slot_reset NULL
3120#define nvme_error_resume NULL
cd638946 3121
671a6018 3122#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3123static int nvme_suspend(struct device *dev)
3124{
3125 struct pci_dev *pdev = to_pci_dev(dev);
3126 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3127
3128 nvme_dev_shutdown(ndev);
3129 return 0;
3130}
3131
3132static int nvme_resume(struct device *dev)
3133{
3134 struct pci_dev *pdev = to_pci_dev(dev);
3135 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3136
9a6b9458 3137 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 3138 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 3139 queue_work(nvme_workq, &ndev->reset_work);
3140 }
3141 return 0;
cd638946 3142}
671a6018 3143#endif
cd638946
KB		 3144
3145static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 3146
1d352035 3147static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 3148 .error_detected = nvme_error_detected,
3149 .mmio_enabled = nvme_dump_registers,
3150 .link_reset = nvme_link_reset,
3151 .slot_reset = nvme_slot_reset,
3152 .resume = nvme_error_resume,
f0d54a54 3153 .reset_notify = nvme_reset_notify,
b60503ba
MW		 3154};
3155
3156/* Move to pci_ids.h later */
3157#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3158
6eb0d698 3159static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 3160 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3161 { 0, }
3162};
3163MODULE_DEVICE_TABLE(pci, nvme_id_table);
3164
3165static struct pci_driver nvme_driver = {
3166 .name = "nvme",
3167 .id_table = nvme_id_table,
3168 .probe = nvme_probe,
8d85fce7 3169 .remove = nvme_remove,
09ece142 3170 .shutdown = nvme_shutdown,
cd638946
KB		 3171 .driver = {
3172 .pm = &nvme_dev_pm_ops,
3173 },
b60503ba
MW		 3174 .err_handler = &nvme_err_handler,
3175};
3176
3177static int __init nvme_init(void)
3178{
0ac13140 3179 int result;
1fa6aead 3180
b9afca3e 3181 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3182
9a6b9458
KB		 3183 nvme_workq = create_singlethread_workqueue("nvme");
3184 if (!nvme_workq)
b9afca3e 3185 return -ENOMEM;
9a6b9458 3186
5c42ea16
KB		 3187 result = register_blkdev(nvme_major, "nvme");
3188 if (result < 0)
9a6b9458 3189 goto kill_workq;
5c42ea16 3190 else if (result > 0)
0ac13140 3191 nvme_major = result;
b60503ba 3192
b3fffdef
KB		 3193 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3194 &nvme_dev_fops);
3195 if (result < 0)
3196 goto unregister_blkdev;
3197 else if (result > 0)
3198 nvme_char_major = result;
3199
3200 nvme_class = class_create(THIS_MODULE, "nvme");
c727040b
AK		 3201 if (IS_ERR(nvme_class)) {
3202 result = PTR_ERR(nvme_class);
b3fffdef 3203 goto unregister_chrdev;
c727040b 3204 }
b3fffdef 3205
f3db22fe
KB		 3206 result = pci_register_driver(&nvme_driver);
3207 if (result)
b3fffdef 3208 goto destroy_class;
1fa6aead 3209 return 0;
b60503ba 3210
b3fffdef
KB		 3211 destroy_class:
3212 class_destroy(nvme_class);
3213 unregister_chrdev:
3214 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1fa6aead 3215 unregister_blkdev:
b60503ba 3216 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3217 kill_workq:
3218 destroy_workqueue(nvme_workq);
b60503ba
MW		 3219 return result;
3220}
3221
3222static void __exit nvme_exit(void)
3223{
3224 pci_unregister_driver(&nvme_driver);
3225 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3226 destroy_workqueue(nvme_workq);
b3fffdef
KB		 3227 class_destroy(nvme_class);
3228 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
b9afca3e 3229 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3230 _nvme_check_size();
b60503ba
MW		 3231}
3232
3233MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3234MODULE_LICENSE("GPL");
c78b4713 3235MODULE_VERSION("1.0");
b60503ba
MW		 3236module_init(nvme_init);
3237module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)