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NVMe: Command abort handling fixes
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
40#include <linux/types.h>
5d0f6131 41#include <scsi/sg.h>
797a796a
HM		 42#include <asm-generic/io-64-nonatomic-lo-hi.h>
43
9d43cf64 44#define NVME_Q_DEPTH 1024
a4aea562 45#define NVME_AQ_DEPTH 64
b60503ba
MW		 46#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 48#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 49#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 50#define IOD_TIMEOUT (retry_time * HZ)
51
52static unsigned char admin_timeout = 60;
53module_param(admin_timeout, byte, 0644);
54MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 55
bd67608a
MW		 56unsigned char nvme_io_timeout = 30;
57module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 58MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 59
61e4ce08
KB		 60static unsigned char retry_time = 30;
61module_param(retry_time, byte, 0644);
62MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
63
2484f407
DM		 64static unsigned char shutdown_timeout = 5;
65module_param(shutdown_timeout, byte, 0644);
66MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
67
b60503ba
MW		 68static int nvme_major;
69module_param(nvme_major, int, 0);
70
58ffacb5
MW		 71static int use_threaded_interrupts;
72module_param(use_threaded_interrupts, int, 0);
73
1fa6aead
MW		 74static DEFINE_SPINLOCK(dev_list_lock);
75static LIST_HEAD(dev_list);
76static struct task_struct *nvme_thread;
9a6b9458 77static struct workqueue_struct *nvme_workq;
b9afca3e 78static wait_queue_head_t nvme_kthread_wait;
f3db22fe 79static struct notifier_block nvme_nb;
1fa6aead 80
d4b4ff8e 81static void nvme_reset_failed_dev(struct work_struct *ws);
a4aea562 82static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 83
4d115420
KB		 84struct async_cmd_info {
85 struct kthread_work work;
86 struct kthread_worker *worker;
a4aea562 87 struct request *req;
4d115420
KB		 88 u32 result;
89 int status;
90 void *ctx;
91};
1fa6aead 92
b60503ba
MW		 93/*
94 * An NVM Express queue. Each device has at least two (one for admin
95 * commands and one for I/O commands).
96 */
97struct nvme_queue {
f435c282 98 struct llist_node node;
b60503ba 99 struct device *q_dmadev;
091b6092 100 struct nvme_dev *dev;
3193f07b 101 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 102 spinlock_t q_lock;
103 struct nvme_command *sq_cmds;
104 volatile struct nvme_completion *cqes;
105 dma_addr_t sq_dma_addr;
106 dma_addr_t cq_dma_addr;
b60503ba
MW		 107 u32 __iomem *q_db;
108 u16 q_depth;
109 u16 cq_vector;
110 u16 sq_head;
111 u16 sq_tail;
112 u16 cq_head;
c30341dc 113 u16 qid;
e9539f47
MW		 114 u8 cq_phase;
115 u8 cqe_seen;
4d115420 116 struct async_cmd_info cmdinfo;
a4aea562 117 struct blk_mq_hw_ctx *hctx;
b60503ba
MW		 118};
119
120/*
121 * Check we didin't inadvertently grow the command struct
122 */
123static inline void _nvme_check_size(void)
124{
125 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 130 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 131 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 136 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 137}
138
edd10d33 139typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 140 struct nvme_completion *);
141
e85248e5 142struct nvme_cmd_info {
c2f5b650
MW		 143 nvme_completion_fn fn;
144 void *ctx;
c30341dc 145 int aborted;
a4aea562 146 struct nvme_queue *nvmeq;
e85248e5
MW		 147};
148
a4aea562
MB		 149static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
150 unsigned int hctx_idx)
e85248e5 151{
a4aea562
MB		 152 struct nvme_dev *dev = data;
153 struct nvme_queue *nvmeq = dev->queues[0];
154
155 WARN_ON(nvmeq->hctx);
156 nvmeq->hctx = hctx;
157 hctx->driver_data = nvmeq;
158 return 0;
e85248e5
MW		 159}
160
a4aea562
MB		 161static int nvme_admin_init_request(void *data, struct request *req,
162 unsigned int hctx_idx, unsigned int rq_idx,
163 unsigned int numa_node)
22404274 164{
a4aea562
MB		 165 struct nvme_dev *dev = data;
166 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
167 struct nvme_queue *nvmeq = dev->queues[0];
168
169 BUG_ON(!nvmeq);
170 cmd->nvmeq = nvmeq;
171 return 0;
22404274
KB		 172}
173
2c30540b
JA		 174static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
175{
176 struct nvme_queue *nvmeq = hctx->driver_data;
177
178 nvmeq->hctx = NULL;
179}
180
a4aea562
MB		 181static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
182 unsigned int hctx_idx)
b60503ba 183{
a4aea562
MB		 184 struct nvme_dev *dev = data;
185 struct nvme_queue *nvmeq = dev->queues[
186 (hctx_idx % dev->queue_count) + 1];
b60503ba 187
a4aea562
MB		 188 if (!nvmeq->hctx)
189 nvmeq->hctx = hctx;
190
191 /* nvmeq queues are shared between namespaces. We assume here that
192 * blk-mq map the tags so they match up with the nvme queue tags. */
193 WARN_ON(nvmeq->hctx->tags != hctx->tags);
b60503ba 194
a4aea562
MB		 195 hctx->driver_data = nvmeq;
196 return 0;
b60503ba
MW		 197}
198
a4aea562
MB		 199static int nvme_init_request(void *data, struct request *req,
200 unsigned int hctx_idx, unsigned int rq_idx,
201 unsigned int numa_node)
b60503ba 202{
a4aea562
MB		 203 struct nvme_dev *dev = data;
204 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
205 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
206
207 BUG_ON(!nvmeq);
208 cmd->nvmeq = nvmeq;
209 return 0;
210}
211
212static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
213 nvme_completion_fn handler)
214{
215 cmd->fn = handler;
216 cmd->ctx = ctx;
217 cmd->aborted = 0;
c917dfe5 218 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 219}
220
c2f5b650
MW		 221/* Special values must be less than 0x1000 */
222#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 223#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
224#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
225#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 226
edd10d33 227static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 228 struct nvme_completion *cqe)
229{
230 if (ctx == CMD_CTX_CANCELLED)
231 return;
c2f5b650 232 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 233 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 234 "completed id %d twice on queue %d\n",
235 cqe->command_id, le16_to_cpup(&cqe->sq_id));
236 return;
237 }
238 if (ctx == CMD_CTX_INVALID) {
edd10d33 239 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 240 "invalid id %d completed on queue %d\n",
241 cqe->command_id, le16_to_cpup(&cqe->sq_id));
242 return;
243 }
edd10d33 244 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 245}
246
a4aea562 247static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 248{
c2f5b650 249 void *ctx;
b60503ba 250
859361a2 251 if (fn)
a4aea562
MB		 252 *fn = cmd->fn;
253 ctx = cmd->ctx;
254 cmd->fn = special_completion;
255 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 256 return ctx;
b60503ba
MW		 257}
258
a4aea562
MB		 259static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
260 struct nvme_completion *cqe)
3c0cf138 261{
a4aea562 262 struct request *req = ctx;
3c0cf138 263
a4aea562
MB		 264 u32 result = le32_to_cpup(&cqe->result);
265 u16 status = le16_to_cpup(&cqe->status) >> 1;
266
267 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
268 ++nvmeq->dev->event_limit;
269 if (status == NVME_SC_SUCCESS)
270 dev_warn(nvmeq->q_dmadev,
271 "async event result %08x\n", result);
272
9d135bb8 273 blk_mq_free_hctx_request(nvmeq->hctx, req);
b60503ba
MW		 274}
275
a4aea562
MB		 276static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
277 struct nvme_completion *cqe)
5a92e700 278{
a4aea562
MB		 279 struct request *req = ctx;
280
281 u16 status = le16_to_cpup(&cqe->status) >> 1;
282 u32 result = le32_to_cpup(&cqe->result);
a51afb54 283
9d135bb8 284 blk_mq_free_hctx_request(nvmeq->hctx, req);
a51afb54 285
a4aea562
MB		 286 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
287 ++nvmeq->dev->abort_limit;
5a92e700
KB		 288}
289
a4aea562
MB		 290static void async_completion(struct nvme_queue *nvmeq, void *ctx,
291 struct nvme_completion *cqe)
b60503ba 292{
a4aea562
MB		 293 struct async_cmd_info *cmdinfo = ctx;
294 cmdinfo->result = le32_to_cpup(&cqe->result);
295 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
296 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
9d135bb8 297 blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
b60503ba
MW		 298}
299
a4aea562
MB		 300static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
301 unsigned int tag)
b60503ba 302{
a4aea562
MB		 303 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
304 struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
a51afb54 305
a4aea562 306 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 307}
308
a4aea562
MB		 309/*
310 * Called with local interrupts disabled and the q_lock held. May not sleep.
311 */
312static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
313 nvme_completion_fn *fn)
4f5099af 314{
a4aea562
MB		 315 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
316 void *ctx;
317 if (tag >= nvmeq->q_depth) {
318 *fn = special_completion;
319 return CMD_CTX_INVALID;
320 }
321 if (fn)
322 *fn = cmd->fn;
323 ctx = cmd->ctx;
324 cmd->fn = special_completion;
325 cmd->ctx = CMD_CTX_COMPLETED;
326 return ctx;
b60503ba
MW		 327}
328
329/**
714a7a22 330 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 331 * @nvmeq: The queue to use
332 * @cmd: The command to send
333 *
334 * Safe to use from interrupt context
335 */
a4aea562 336static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 337{
a4aea562
MB		 338 u16 tail = nvmeq->sq_tail;
339
b60503ba 340 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 341 if (++tail == nvmeq->q_depth)
342 tail = 0;
7547881d 343 writel(tail, nvmeq->q_db);
b60503ba 344 nvmeq->sq_tail = tail;
b60503ba
MW		 345
346 return 0;
347}
348
a4aea562
MB		 349static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
350{
351 unsigned long flags;
352 int ret;
353 spin_lock_irqsave(&nvmeq->q_lock, flags);
354 ret = __nvme_submit_cmd(nvmeq, cmd);
355 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
356 return ret;
357}
358
eca18b23 359static __le64 **iod_list(struct nvme_iod *iod)
e025344c 360{
eca18b23 361 return ((void *)iod) + iod->offset;
e025344c
SMM		 362}
363
eca18b23
MW		 364/*
365 * Will slightly overestimate the number of pages needed. This is OK
366 * as it only leads to a small amount of wasted memory for the lifetime of
367 * the I/O.
368 */
1d090624 369static int nvme_npages(unsigned size, struct nvme_dev *dev)
eca18b23 370{
1d090624
KB		 371 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
372 return DIV_ROUND_UP(8 * nprps, dev->page_size - 8);
eca18b23 373}
b60503ba 374
eca18b23 375static struct nvme_iod *
1d090624 376nvme_alloc_iod(unsigned nseg, unsigned nbytes, struct nvme_dev *dev, gfp_t gfp)
b60503ba 377{
eca18b23 378 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
1d090624 379 sizeof(__le64 *) * nvme_npages(nbytes, dev) +
eca18b23
MW		 380 sizeof(struct scatterlist) * nseg, gfp);
381
382 if (iod) {
383 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
384 iod->npages = -1;
385 iod->length = nbytes;
2b196034 386 iod->nents = 0;
edd10d33 387 iod->first_dma = 0ULL;
eca18b23
MW		 388 }
389
390 return iod;
b60503ba
MW		 391}
392
5d0f6131 393void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 394{
1d090624 395 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 396 int i;
397 __le64 **list = iod_list(iod);
398 dma_addr_t prp_dma = iod->first_dma;
399
400 if (iod->npages == 0)
401 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
402 for (i = 0; i < iod->npages; i++) {
403 __le64 *prp_list = list[i];
404 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
405 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
406 prp_dma = next_prp_dma;
407 }
408 kfree(iod);
b60503ba
MW		 409}
410
b4ff9c8d
KB		 411static int nvme_error_status(u16 status)
412{
413 switch (status & 0x7ff) {
414 case NVME_SC_SUCCESS:
415 return 0;
416 case NVME_SC_CAP_EXCEEDED:
417 return -ENOSPC;
418 default:
419 return -EIO;
420 }
421}
422
a4aea562 423static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 424 struct nvme_completion *cqe)
425{
eca18b23 426 struct nvme_iod *iod = ctx;
a4aea562
MB		 427 struct request *req = iod->private;
428 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
429
b60503ba
MW		 430 u16 status = le16_to_cpup(&cqe->status) >> 1;
431
edd10d33 432 if (unlikely(status)) {
a4aea562
MB		 433 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
434 && (jiffies - req->start_time) < req->timeout) {
435 blk_mq_requeue_request(req);
436 blk_mq_kick_requeue_list(req->q);
edd10d33
KB		 437 return;
438 }
a4aea562
MB		 439 req->errors = nvme_error_status(status);
440 } else
441 req->errors = 0;
442
443 if (cmd_rq->aborted)
444 dev_warn(&nvmeq->dev->pci_dev->dev,
445 "completing aborted command with status:%04x\n",
446 status);
447
448 if (iod->nents)
449 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
450 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
edd10d33 451 nvme_free_iod(nvmeq->dev, iod);
3291fa57 452
a4aea562 453 blk_mq_complete_request(req);
b60503ba
MW		 454}
455
184d2944 456/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 457int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
458 gfp_t gfp)
ff22b54f 459{
99802a7a 460 struct dma_pool *pool;
eca18b23
MW		 461 int length = total_len;
462 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 463 int dma_len = sg_dma_len(sg);
464 u64 dma_addr = sg_dma_address(sg);
465 int offset = offset_in_page(dma_addr);
e025344c 466 __le64 *prp_list;
eca18b23 467 __le64 **list = iod_list(iod);
e025344c 468 dma_addr_t prp_dma;
eca18b23 469 int nprps, i;
1d090624 470 u32 page_size = dev->page_size;
ff22b54f 471
1d090624 472 length -= (page_size - offset);
ff22b54f 473 if (length <= 0)
eca18b23 474 return total_len;
ff22b54f 475
1d090624 476 dma_len -= (page_size - offset);
ff22b54f 477 if (dma_len) {
1d090624 478 dma_addr += (page_size - offset);
ff22b54f
MW		 479 } else {
480 sg = sg_next(sg);
481 dma_addr = sg_dma_address(sg);
482 dma_len = sg_dma_len(sg);
483 }
484
1d090624 485 if (length <= page_size) {
edd10d33 486 iod->first_dma = dma_addr;
eca18b23 487 return total_len;
e025344c
SMM		 488 }
489
1d090624 490 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 491 if (nprps <= (256 / 8)) {
492 pool = dev->prp_small_pool;
eca18b23 493 iod->npages = 0;
99802a7a
MW		 494 } else {
495 pool = dev->prp_page_pool;
eca18b23 496 iod->npages = 1;
99802a7a
MW		 497 }
498
b77954cb
MW		 499 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
500 if (!prp_list) {
edd10d33 501 iod->first_dma = dma_addr;
eca18b23 502 iod->npages = -1;
1d090624 503 return (total_len - length) + page_size;
b77954cb 504 }
eca18b23
MW		 505 list[0] = prp_list;
506 iod->first_dma = prp_dma;
e025344c
SMM		 507 i = 0;
508 for (;;) {
1d090624 509 if (i == page_size >> 3) {
e025344c 510 __le64 *old_prp_list = prp_list;
b77954cb 511 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 512 if (!prp_list)
513 return total_len - length;
514 list[iod->npages++] = prp_list;
7523d834
MW		 515 prp_list[0] = old_prp_list[i - 1];
516 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
517 i = 1;
e025344c
SMM		 518 }
519 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 520 dma_len -= page_size;
521 dma_addr += page_size;
522 length -= page_size;
e025344c
SMM		 523 if (length <= 0)
524 break;
525 if (dma_len > 0)
526 continue;
527 BUG_ON(dma_len < 0);
528 sg = sg_next(sg);
529 dma_addr = sg_dma_address(sg);
530 dma_len = sg_dma_len(sg);
ff22b54f
MW		 531 }
532
eca18b23 533 return total_len;
ff22b54f
MW		 534}
535
a4aea562
MB		 536/*
537 * We reuse the small pool to allocate the 16-byte range here as it is not
538 * worth having a special pool for these or additional cases to handle freeing
539 * the iod.
540 */
541static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
542 struct request *req, struct nvme_iod *iod)
0e5e4f0e 543{
edd10d33
KB		 544 struct nvme_dsm_range *range =
545 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 546 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
547
0e5e4f0e 548 range->cattr = cpu_to_le32(0);
a4aea562
MB		 549 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
550 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e
KB		 551
552 memset(cmnd, 0, sizeof(*cmnd));
553 cmnd->dsm.opcode = nvme_cmd_dsm;
a4aea562 554 cmnd->dsm.command_id = req->tag;
0e5e4f0e
KB		 555 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
556 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
557 cmnd->dsm.nr = 0;
558 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
559
560 if (++nvmeq->sq_tail == nvmeq->q_depth)
561 nvmeq->sq_tail = 0;
562 writel(nvmeq->sq_tail, nvmeq->q_db);
0e5e4f0e
KB		 563}
564
a4aea562 565static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 566 int cmdid)
567{
568 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
569
570 memset(cmnd, 0, sizeof(*cmnd));
571 cmnd->common.opcode = nvme_cmd_flush;
572 cmnd->common.command_id = cmdid;
573 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
574
575 if (++nvmeq->sq_tail == nvmeq->q_depth)
576 nvmeq->sq_tail = 0;
577 writel(nvmeq->sq_tail, nvmeq->q_db);
00df5cb4
MW		 578}
579
a4aea562
MB		 580static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
581 struct nvme_ns *ns)
b60503ba 582{
a4aea562 583 struct request *req = iod->private;
ff22b54f 584 struct nvme_command *cmnd;
a4aea562
MB		 585 u16 control = 0;
586 u32 dsmgmt = 0;
00df5cb4 587
a4aea562 588 if (req->cmd_flags & REQ_FUA)
b60503ba 589 control |= NVME_RW_FUA;
a4aea562 590 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 591 control |= NVME_RW_LR;
592
a4aea562 593 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 594 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
595
ff22b54f 596 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 597 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 598
a4aea562
MB		 599 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
600 cmnd->rw.command_id = req->tag;
ff22b54f 601 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 602 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
603 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
a4aea562
MB		 604 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
605 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
ff22b54f
MW		 606 cmnd->rw.control = cpu_to_le16(control);
607 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 608
b60503ba
MW		 609 if (++nvmeq->sq_tail == nvmeq->q_depth)
610 nvmeq->sq_tail = 0;
7547881d 611 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 612
1974b1ae 613 return 0;
edd10d33
KB		 614}
615
a4aea562
MB		 616static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
617 const struct blk_mq_queue_data *bd)
edd10d33 618{
a4aea562
MB		 619 struct nvme_ns *ns = hctx->queue->queuedata;
620 struct nvme_queue *nvmeq = hctx->driver_data;
621 struct request *req = bd->rq;
622 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 623 struct nvme_iod *iod;
a4aea562 624 int psegs = req->nr_phys_segments;
a4aea562
MB		 625 enum dma_data_direction dma_dir;
626 unsigned size = !(req->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(req) :
9dbbfab7 627 sizeof(struct nvme_dsm_range);
edd10d33 628
9dbbfab7 629 iod = nvme_alloc_iod(psegs, size, ns->dev, GFP_ATOMIC);
edd10d33 630 if (!iod)
fe54303e 631 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562
MB		 632
633 iod->private = req;
edd10d33 634
a4aea562 635 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 636 void *range;
637 /*
638 * We reuse the small pool to allocate the 16-byte range here
639 * as it is not worth having a special pool for these or
640 * additional cases to handle freeing the iod.
641 */
642 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
643 GFP_ATOMIC,
644 &iod->first_dma);
a4aea562 645 if (!range)
fe54303e 646 goto retry_cmd;
edd10d33
KB		 647 iod_list(iod)[0] = (__le64 *)range;
648 iod->npages = 0;
649 } else if (psegs) {
a4aea562
MB		 650 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
651
652 sg_init_table(iod->sg, psegs);
653 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 654 if (!iod->nents)
655 goto error_cmd;
a4aea562
MB		 656
657 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 658 goto retry_cmd;
a4aea562 659
fe54303e
JA		 660 if (blk_rq_bytes(req) !=
661 nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
662 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg,
663 iod->nents, dma_dir);
664 goto retry_cmd;
665 }
edd10d33 666 }
1974b1ae 667
9af8785a 668 nvme_set_info(cmd, iod, req_completion);
a4aea562
MB		 669 spin_lock_irq(&nvmeq->q_lock);
670 if (req->cmd_flags & REQ_DISCARD)
671 nvme_submit_discard(nvmeq, ns, req, iod);
672 else if (req->cmd_flags & REQ_FLUSH)
673 nvme_submit_flush(nvmeq, ns, req->tag);
674 else
675 nvme_submit_iod(nvmeq, iod, ns);
676
677 nvme_process_cq(nvmeq);
678 spin_unlock_irq(&nvmeq->q_lock);
679 return BLK_MQ_RQ_QUEUE_OK;
680
fe54303e
JA		 681 error_cmd:
682 nvme_free_iod(nvmeq->dev, iod);
683 return BLK_MQ_RQ_QUEUE_ERROR;
684 retry_cmd:
eca18b23 685 nvme_free_iod(nvmeq->dev, iod);
fe54303e 686 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 687}
688
e9539f47 689static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 690{
82123460 691 u16 head, phase;
b60503ba 692
b60503ba 693 head = nvmeq->cq_head;
82123460 694 phase = nvmeq->cq_phase;
b60503ba
MW		 695
696 for (;;) {
c2f5b650
MW		 697 void *ctx;
698 nvme_completion_fn fn;
b60503ba 699 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 700 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 701 break;
702 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
703 if (++head == nvmeq->q_depth) {
704 head = 0;
82123460 705 phase = !phase;
b60503ba 706 }
a4aea562 707 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 708 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 709 }
710
711 /* If the controller ignores the cq head doorbell and continuously
712 * writes to the queue, it is theoretically possible to wrap around
713 * the queue twice and mistakenly return IRQ_NONE. Linux only
714 * requires that 0.1% of your interrupts are handled, so this isn't
715 * a big problem.
716 */
82123460 717 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 718 return 0;
b60503ba 719
b80d5ccc 720 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 721 nvmeq->cq_head = head;
82123460 722 nvmeq->cq_phase = phase;
b60503ba 723
e9539f47
MW		 724 nvmeq->cqe_seen = 1;
725 return 1;
b60503ba
MW		 726}
727
a4aea562
MB		 728/* Admin queue isn't initialized as a request queue. If at some point this
729 * happens anyway, make sure to notify the user */
730static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
731 const struct blk_mq_queue_data *bd)
7d822457 732{
a4aea562
MB		 733 WARN_ON_ONCE(1);
734 return BLK_MQ_RQ_QUEUE_ERROR;
7d822457
MW		 735}
736
b60503ba 737static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 738{
739 irqreturn_t result;
740 struct nvme_queue *nvmeq = data;
741 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 742 nvme_process_cq(nvmeq);
743 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
744 nvmeq->cqe_seen = 0;
58ffacb5
MW		 745 spin_unlock(&nvmeq->q_lock);
746 return result;
747}
748
749static irqreturn_t nvme_irq_check(int irq, void *data)
750{
751 struct nvme_queue *nvmeq = data;
752 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
753 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
754 return IRQ_NONE;
755 return IRQ_WAKE_THREAD;
756}
757
a4aea562
MB		 758static void nvme_abort_cmd_info(struct nvme_queue *nvmeq, struct nvme_cmd_info *
759 cmd_info)
3c0cf138
MW		 760{
761 spin_lock_irq(&nvmeq->q_lock);
a4aea562 762 cancel_cmd_info(cmd_info, NULL);
3c0cf138
MW		 763 spin_unlock_irq(&nvmeq->q_lock);
764}
765
c2f5b650
MW		 766struct sync_cmd_info {
767 struct task_struct *task;
768 u32 result;
769 int status;
770};
771
edd10d33 772static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 773 struct nvme_completion *cqe)
774{
775 struct sync_cmd_info *cmdinfo = ctx;
776 cmdinfo->result = le32_to_cpup(&cqe->result);
777 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
778 wake_up_process(cmdinfo->task);
779}
780
b60503ba
MW		 781/*
782 * Returns 0 on success. If the result is negative, it's a Linux error code;
783 * if the result is positive, it's an NVM Express status code
784 */
a4aea562 785static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
5d0f6131 786 u32 *result, unsigned timeout)
b60503ba 787{
a4aea562 788 int ret;
b60503ba 789 struct sync_cmd_info cmdinfo;
a4aea562
MB		 790 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
791 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
b60503ba
MW		 792
793 cmdinfo.task = current;
794 cmdinfo.status = -EINTR;
795
a4aea562
MB		 796 cmd->common.command_id = req->tag;
797
798 nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
b60503ba 799
3c0cf138 800 set_current_state(TASK_KILLABLE);
4f5099af
KB		 801 ret = nvme_submit_cmd(nvmeq, cmd);
802 if (ret) {
a4aea562 803 nvme_finish_cmd(nvmeq, req->tag, NULL);
4f5099af 804 set_current_state(TASK_RUNNING);
4f5099af 805 }
849c6e77 806 ret = schedule_timeout(timeout);
b60503ba 807
849c6e77
JA		 808 /*
809 * Ensure that sync_completion has either run, or that it will
810 * never run.
811 */
812 nvme_abort_cmd_info(nvmeq, blk_mq_rq_to_pdu(req));
813
814 /*
815 * We never got the completion
816 */
817 if (cmdinfo.status == -EINTR)
3c0cf138 818 return -EINTR;
3c0cf138 819
b60503ba
MW		 820 if (result)
821 *result = cmdinfo.result;
822
823 return cmdinfo.status;
824}
825
a4aea562
MB		 826static int nvme_submit_async_admin_req(struct nvme_dev *dev)
827{
828 struct nvme_queue *nvmeq = dev->queues[0];
829 struct nvme_command c;
830 struct nvme_cmd_info *cmd_info;
831 struct request *req;
832
6dcc0cf6 833 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false);
9f173b33
DC		 834 if (IS_ERR(req))
835 return PTR_ERR(req);
a4aea562 836
c917dfe5 837 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562
MB		 838 cmd_info = blk_mq_rq_to_pdu(req);
839 nvme_set_info(cmd_info, req, async_req_completion);
840
841 memset(&c, 0, sizeof(c));
842 c.common.opcode = nvme_admin_async_event;
843 c.common.command_id = req->tag;
844
845 return __nvme_submit_cmd(nvmeq, &c);
846}
847
848static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 849 struct nvme_command *cmd,
850 struct async_cmd_info *cmdinfo, unsigned timeout)
851{
a4aea562
MB		 852 struct nvme_queue *nvmeq = dev->queues[0];
853 struct request *req;
854 struct nvme_cmd_info *cmd_rq;
4d115420 855
a4aea562 856 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 857 if (IS_ERR(req))
858 return PTR_ERR(req);
a4aea562
MB		 859
860 req->timeout = timeout;
861 cmd_rq = blk_mq_rq_to_pdu(req);
862 cmdinfo->req = req;
863 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 864 cmdinfo->status = -EINTR;
a4aea562
MB		 865
866 cmd->common.command_id = req->tag;
867
4f5099af 868 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 869}
870
a64e6bb4 871static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
a4aea562 872 u32 *result, unsigned timeout)
b60503ba 873{
a4aea562
MB		 874 int res;
875 struct request *req;
876
877 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
97fe3832
JA		 878 if (IS_ERR(req))
879 return PTR_ERR(req);
a4aea562 880 res = nvme_submit_sync_cmd(req, cmd, result, timeout);
9d135bb8 881 blk_mq_free_request(req);
a4aea562 882 return res;
4f5099af
KB		 883}
884
a4aea562 885int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
4f5099af
KB		 886 u32 *result)
887{
a4aea562 888 return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 889}
890
a4aea562
MB		 891int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
892 struct nvme_command *cmd, u32 *result)
4d115420 893{
a4aea562
MB		 894 int res;
895 struct request *req;
896
897 req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
898 false);
97fe3832
JA		 899 if (IS_ERR(req))
900 return PTR_ERR(req);
a4aea562 901 res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
9d135bb8 902 blk_mq_free_request(req);
a4aea562 903 return res;
4d115420
KB		 904}
905
b60503ba
MW		 906static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
907{
b60503ba
MW		 908 struct nvme_command c;
909
910 memset(&c, 0, sizeof(c));
911 c.delete_queue.opcode = opcode;
912 c.delete_queue.qid = cpu_to_le16(id);
913
a4aea562 914 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 915}
916
917static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
918 struct nvme_queue *nvmeq)
919{
b60503ba
MW		 920 struct nvme_command c;
921 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
922
923 memset(&c, 0, sizeof(c));
924 c.create_cq.opcode = nvme_admin_create_cq;
925 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
926 c.create_cq.cqid = cpu_to_le16(qid);
927 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
928 c.create_cq.cq_flags = cpu_to_le16(flags);
929 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
930
a4aea562 931 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 932}
933
934static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
935 struct nvme_queue *nvmeq)
936{
b60503ba
MW		 937 struct nvme_command c;
938 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
939
940 memset(&c, 0, sizeof(c));
941 c.create_sq.opcode = nvme_admin_create_sq;
942 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
943 c.create_sq.sqid = cpu_to_le16(qid);
944 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
945 c.create_sq.sq_flags = cpu_to_le16(flags);
946 c.create_sq.cqid = cpu_to_le16(qid);
947
a4aea562 948 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 949}
950
951static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
952{
953 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
954}
955
956static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
957{
958 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
959}
960
5d0f6131 961int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 962 dma_addr_t dma_addr)
963{
964 struct nvme_command c;
965
966 memset(&c, 0, sizeof(c));
967 c.identify.opcode = nvme_admin_identify;
968 c.identify.nsid = cpu_to_le32(nsid);
969 c.identify.prp1 = cpu_to_le64(dma_addr);
970 c.identify.cns = cpu_to_le32(cns);
971
972 return nvme_submit_admin_cmd(dev, &c, NULL);
973}
974
5d0f6131 975int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 976 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 977{
978 struct nvme_command c;
979
980 memset(&c, 0, sizeof(c));
981 c.features.opcode = nvme_admin_get_features;
a42cecce 982 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 983 c.features.prp1 = cpu_to_le64(dma_addr);
984 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 985
08df1e05 986 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 987}
988
5d0f6131
VV		 989int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
990 dma_addr_t dma_addr, u32 *result)
df348139
MW		 991{
992 struct nvme_command c;
993
994 memset(&c, 0, sizeof(c));
995 c.features.opcode = nvme_admin_set_features;
996 c.features.prp1 = cpu_to_le64(dma_addr);
997 c.features.fid = cpu_to_le32(fid);
998 c.features.dword11 = cpu_to_le32(dword11);
999
bc5fc7e4
MW		 1000 return nvme_submit_admin_cmd(dev, &c, result);
1001}
1002
c30341dc 1003/**
a4aea562 1004 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1005 *
1006 * Schedule controller reset if the command was already aborted once before and
1007 * still hasn't been returned to the driver, or if this is the admin queue.
1008 */
a4aea562 1009static void nvme_abort_req(struct request *req)
c30341dc 1010{
a4aea562
MB		 1011 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1012 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1013 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1014 struct request *abort_req;
1015 struct nvme_cmd_info *abort_cmd;
1016 struct nvme_command cmd;
c30341dc 1017
a4aea562 1018 if (!nvmeq->qid || cmd_rq->aborted) {
c30341dc
KB		 1019 if (work_busy(&dev->reset_work))
1020 return;
1021 list_del_init(&dev->node);
1022 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1023 "I/O %d QID %d timeout, reset controller\n",
1024 req->tag, nvmeq->qid);
9ca97374 1025 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc
KB		 1026 queue_work(nvme_workq, &dev->reset_work);
1027 return;
1028 }
1029
1030 if (!dev->abort_limit)
1031 return;
1032
a4aea562
MB		 1033 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1034 false);
9f173b33 1035 if (IS_ERR(abort_req))
c30341dc
KB		 1036 return;
1037
a4aea562
MB		 1038 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1039 nvme_set_info(abort_cmd, abort_req, abort_completion);
1040
c30341dc
KB		 1041 memset(&cmd, 0, sizeof(cmd));
1042 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1043 cmd.abort.cid = req->tag;
c30341dc 1044 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1045 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1046
1047 --dev->abort_limit;
a4aea562 1048 cmd_rq->aborted = 1;
c30341dc 1049
a4aea562 1050 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1051 nvmeq->qid);
a4aea562
MB		 1052 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1053 dev_warn(nvmeq->q_dmadev,
1054 "Could not abort I/O %d QID %d",
1055 req->tag, nvmeq->qid);
c87fd540 1056 blk_mq_free_request(abort_req);
a4aea562 1057 }
c30341dc
KB		 1058}
1059
a4aea562
MB		 1060static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1061 struct request *req, void *data, bool reserved)
a09115b2 1062{
a4aea562
MB		 1063 struct nvme_queue *nvmeq = data;
1064 void *ctx;
1065 nvme_completion_fn fn;
1066 struct nvme_cmd_info *cmd;
cef6a948
KB		 1067 struct nvme_completion cqe;
1068
1069 if (!blk_mq_request_started(req))
1070 return;
a09115b2 1071
a4aea562 1072 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1073
a4aea562
MB		 1074 if (cmd->ctx == CMD_CTX_CANCELLED)
1075 return;
1076
cef6a948
KB		 1077 if (blk_queue_dying(req->q))
1078 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1079 else
1080 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1081
1082
a4aea562
MB		 1083 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1084 req->tag, nvmeq->qid);
1085 ctx = cancel_cmd_info(cmd, &fn);
1086 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1087}
1088
a4aea562 1089static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1090{
a4aea562
MB		 1091 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1092 struct nvme_queue *nvmeq = cmd->nvmeq;
1093
1094 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1095 nvmeq->qid);
c917dfe5
KB		 1096
1097 if (!nvmeq->dev->initialized) {
1098 /*
1099 * Force cancelled command frees the request, which requires we
1100 * return BLK_EH_NOT_HANDLED.
1101 */
1102 nvme_cancel_queue_ios(nvmeq->hctx, req, nvmeq, reserved);
1103 return BLK_EH_NOT_HANDLED;
1104 }
1105 nvme_abort_req(req);
a4aea562
MB		 1106
1107 /*
1108 * The aborted req will be completed on receiving the abort req.
1109 * We enable the timer again. If hit twice, it'll cause a device reset,
1110 * as the device then is in a faulty state.
1111 */
1112 return BLK_EH_RESET_TIMER;
1113}
22404274 1114
a4aea562
MB		 1115static void nvme_free_queue(struct nvme_queue *nvmeq)
1116{
9e866774
MW		 1117 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1118 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1119 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1120 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1121 kfree(nvmeq);
1122}
1123
a1a5ef99 1124static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274 1125{
f435c282
KB		 1126 LLIST_HEAD(q_list);
1127 struct nvme_queue *nvmeq, *next;
1128 struct llist_node *entry;
22404274
KB		 1129 int i;
1130
a1a5ef99 1131 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1132 struct nvme_queue *nvmeq = dev->queues[i];
f435c282 1133 llist_add(&nvmeq->node, &q_list);
22404274 1134 dev->queue_count--;
a4aea562 1135 dev->queues[i] = NULL;
22404274 1136 }
f435c282
KB		 1137 synchronize_rcu();
1138 entry = llist_del_all(&q_list);
1139 llist_for_each_entry_safe(nvmeq, next, entry, node)
1140 nvme_free_queue(nvmeq);
22404274
KB		 1141}
1142
4d115420
KB		 1143/**
1144 * nvme_suspend_queue - put queue into suspended state
1145 * @nvmeq - queue to suspend
4d115420
KB		 1146 */
1147static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1148{
2b25d981 1149 int vector;
b60503ba 1150
a09115b2 1151 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1152 if (nvmeq->cq_vector == -1) {
1153 spin_unlock_irq(&nvmeq->q_lock);
1154 return 1;
1155 }
1156 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1157 nvmeq->dev->online_queues--;
2b25d981 1158 nvmeq->cq_vector = -1;
a09115b2
MW		 1159 spin_unlock_irq(&nvmeq->q_lock);
1160
aba2080f
MW		 1161 irq_set_affinity_hint(vector, NULL);
1162 free_irq(vector, nvmeq);
b60503ba 1163
4d115420
KB		 1164 return 0;
1165}
b60503ba 1166
4d115420
KB		 1167static void nvme_clear_queue(struct nvme_queue *nvmeq)
1168{
a4aea562
MB		 1169 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1170
22404274
KB		 1171 spin_lock_irq(&nvmeq->q_lock);
1172 nvme_process_cq(nvmeq);
a4aea562
MB		 1173 if (hctx && hctx->tags)
1174 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
22404274 1175 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1176}
1177
4d115420
KB		 1178static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1179{
a4aea562 1180 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1181
1182 if (!nvmeq)
1183 return;
1184 if (nvme_suspend_queue(nvmeq))
1185 return;
1186
0e53d180
KB		 1187 /* Don't tell the adapter to delete the admin queue.
1188 * Don't tell a removed adapter to delete IO queues. */
1189 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1190 adapter_delete_sq(dev, qid);
1191 adapter_delete_cq(dev, qid);
1192 }
0fb59cbc
KB		 1193 if (!qid && dev->admin_q)
1194 blk_mq_freeze_queue_start(dev->admin_q);
4d115420 1195 nvme_clear_queue(nvmeq);
b60503ba
MW		 1196}
1197
1198static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1199 int depth)
b60503ba
MW		 1200{
1201 struct device *dmadev = &dev->pci_dev->dev;
a4aea562 1202 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1203 if (!nvmeq)
1204 return NULL;
1205
4d51abf9
JP		 1206 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1207 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1208 if (!nvmeq->cqes)
1209 goto free_nvmeq;
b60503ba
MW		 1210
1211 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1212 &nvmeq->sq_dma_addr, GFP_KERNEL);
1213 if (!nvmeq->sq_cmds)
1214 goto free_cqdma;
1215
1216 nvmeq->q_dmadev = dmadev;
091b6092 1217 nvmeq->dev = dev;
3193f07b
MW		 1218 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1219 dev->instance, qid);
b60503ba
MW		 1220 spin_lock_init(&nvmeq->q_lock);
1221 nvmeq->cq_head = 0;
82123460 1222 nvmeq->cq_phase = 1;
b80d5ccc 1223 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1224 nvmeq->q_depth = depth;
c30341dc 1225 nvmeq->qid = qid;
22404274 1226 dev->queue_count++;
a4aea562 1227 dev->queues[qid] = nvmeq;
b60503ba
MW		 1228
1229 return nvmeq;
1230
1231 free_cqdma:
68b8eca5 1232 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1233 nvmeq->cq_dma_addr);
1234 free_nvmeq:
1235 kfree(nvmeq);
1236 return NULL;
1237}
1238
3001082c
MW		 1239static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1240 const char *name)
1241{
58ffacb5
MW		 1242 if (use_threaded_interrupts)
1243 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1244 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1245 name, nvmeq);
3001082c 1246 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1247 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1248}
1249
22404274 1250static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1251{
22404274 1252 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1253
7be50e93 1254 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1255 nvmeq->sq_tail = 0;
1256 nvmeq->cq_head = 0;
1257 nvmeq->cq_phase = 1;
b80d5ccc 1258 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1259 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1260 dev->online_queues++;
7be50e93 1261 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1262}
1263
1264static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1265{
1266 struct nvme_dev *dev = nvmeq->dev;
1267 int result;
3f85d50b 1268
2b25d981 1269 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1270 result = adapter_alloc_cq(dev, qid, nvmeq);
1271 if (result < 0)
22404274 1272 return result;
b60503ba
MW		 1273
1274 result = adapter_alloc_sq(dev, qid, nvmeq);
1275 if (result < 0)
1276 goto release_cq;
1277
3193f07b 1278 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1279 if (result < 0)
1280 goto release_sq;
1281
22404274 1282 nvme_init_queue(nvmeq, qid);
22404274 1283 return result;
b60503ba
MW		 1284
1285 release_sq:
1286 adapter_delete_sq(dev, qid);
1287 release_cq:
1288 adapter_delete_cq(dev, qid);
22404274 1289 return result;
b60503ba
MW		 1290}
1291
ba47e386
MW		 1292static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1293{
1294 unsigned long timeout;
1295 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1296
1297 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1298
1299 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1300 msleep(100);
1301 if (fatal_signal_pending(current))
1302 return -EINTR;
1303 if (time_after(jiffies, timeout)) {
1304 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1305 "Device not ready; aborting %s\n", enabled ?
1306 "initialisation" : "reset");
ba47e386
MW		 1307 return -ENODEV;
1308 }
1309 }
1310
1311 return 0;
1312}
1313
1314/*
1315 * If the device has been passed off to us in an enabled state, just clear
1316 * the enabled bit. The spec says we should set the 'shutdown notification
1317 * bits', but doing so may cause the device to complete commands to the
1318 * admin queue ... and we don't know what memory that might be pointing at!
1319 */
1320static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1321{
01079522
DM		 1322 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1323 dev->ctrl_config &= ~NVME_CC_ENABLE;
1324 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1325
ba47e386
MW		 1326 return nvme_wait_ready(dev, cap, false);
1327}
1328
1329static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1330{
01079522
DM		 1331 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1332 dev->ctrl_config |= NVME_CC_ENABLE;
1333 writel(dev->ctrl_config, &dev->bar->cc);
1334
ba47e386
MW		 1335 return nvme_wait_ready(dev, cap, true);
1336}
1337
1894d8f1
KB		 1338static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1339{
1340 unsigned long timeout;
1894d8f1 1341
01079522
DM		 1342 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1343 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1344
1345 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1346
2484f407 1347 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1348 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1349 NVME_CSTS_SHST_CMPLT) {
1350 msleep(100);
1351 if (fatal_signal_pending(current))
1352 return -EINTR;
1353 if (time_after(jiffies, timeout)) {
1354 dev_err(&dev->pci_dev->dev,
1355 "Device shutdown incomplete; abort shutdown\n");
1356 return -ENODEV;
1357 }
1358 }
1359
1360 return 0;
1361}
1362
a4aea562
MB		 1363static struct blk_mq_ops nvme_mq_admin_ops = {
1364 .queue_rq = nvme_admin_queue_rq,
1365 .map_queue = blk_mq_map_queue,
1366 .init_hctx = nvme_admin_init_hctx,
2c30540b 1367 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1368 .init_request = nvme_admin_init_request,
1369 .timeout = nvme_timeout,
1370};
1371
1372static struct blk_mq_ops nvme_mq_ops = {
1373 .queue_rq = nvme_queue_rq,
1374 .map_queue = blk_mq_map_queue,
1375 .init_hctx = nvme_init_hctx,
2c30540b 1376 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1377 .init_request = nvme_init_request,
1378 .timeout = nvme_timeout,
1379};
1380
ea191d2f
KB		 1381static void nvme_dev_remove_admin(struct nvme_dev *dev)
1382{
1383 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1384 blk_cleanup_queue(dev->admin_q);
1385 blk_mq_free_tag_set(&dev->admin_tagset);
1386 }
1387}
1388
a4aea562
MB		 1389static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1390{
1391 if (!dev->admin_q) {
1392 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1393 dev->admin_tagset.nr_hw_queues = 1;
1394 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1395 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1396 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
1397 dev->admin_tagset.cmd_size = sizeof(struct nvme_cmd_info);
1398 dev->admin_tagset.driver_data = dev;
1399
1400 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1401 return -ENOMEM;
1402
1403 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1404 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1405 blk_mq_free_tag_set(&dev->admin_tagset);
1406 return -ENOMEM;
1407 }
ea191d2f
KB		 1408 if (!blk_get_queue(dev->admin_q)) {
1409 nvme_dev_remove_admin(dev);
1410 return -ENODEV;
1411 }
0fb59cbc
KB		 1412 } else
1413 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1414
1415 return 0;
1416}
1417
8d85fce7 1418static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1419{
ba47e386 1420 int result;
b60503ba 1421 u32 aqa;
ba47e386 1422 u64 cap = readq(&dev->bar->cap);
b60503ba 1423 struct nvme_queue *nvmeq;
1d090624
KB		 1424 unsigned page_shift = PAGE_SHIFT;
1425 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1426 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1427
1428 if (page_shift < dev_page_min) {
1429 dev_err(&dev->pci_dev->dev,
1430 "Minimum device page size (%u) too large for "
1431 "host (%u)\n", 1 << dev_page_min,
1432 1 << page_shift);
1433 return -ENODEV;
1434 }
1435 if (page_shift > dev_page_max) {
1436 dev_info(&dev->pci_dev->dev,
1437 "Device maximum page size (%u) smaller than "
1438 "host (%u); enabling work-around\n",
1439 1 << dev_page_max, 1 << page_shift);
1440 page_shift = dev_page_max;
1441 }
b60503ba 1442
ba47e386
MW		 1443 result = nvme_disable_ctrl(dev, cap);
1444 if (result < 0)
1445 return result;
b60503ba 1446
a4aea562 1447 nvmeq = dev->queues[0];
cd638946 1448 if (!nvmeq) {
2b25d981 1449 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1450 if (!nvmeq)
1451 return -ENOMEM;
cd638946 1452 }
b60503ba
MW		 1453
1454 aqa = nvmeq->q_depth - 1;
1455 aqa |= aqa << 16;
1456
1d090624
KB		 1457 dev->page_size = 1 << page_shift;
1458
01079522 1459 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1460 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1461 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1462 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1463
1464 writel(aqa, &dev->bar->aqa);
1465 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1466 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1467
ba47e386 1468 result = nvme_enable_ctrl(dev, cap);
025c557a 1469 if (result)
a4aea562
MB		 1470 goto free_nvmeq;
1471
2b25d981 1472 nvmeq->cq_vector = 0;
3193f07b 1473 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1474 if (result)
0fb59cbc 1475 goto free_nvmeq;
025c557a 1476
b60503ba 1477 return result;
a4aea562 1478
a4aea562
MB		 1479 free_nvmeq:
1480 nvme_free_queues(dev, 0);
1481 return result;
b60503ba
MW		 1482}
1483
5d0f6131 1484struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1485 unsigned long addr, unsigned length)
b60503ba 1486{
36c14ed9 1487 int i, err, count, nents, offset;
7fc3cdab
MW		 1488 struct scatterlist *sg;
1489 struct page **pages;
eca18b23 1490 struct nvme_iod *iod;
36c14ed9
MW		 1491
1492 if (addr & 3)
eca18b23 1493 return ERR_PTR(-EINVAL);
5460fc03 1494 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1495 return ERR_PTR(-EINVAL);
7fc3cdab 1496
36c14ed9 1497 offset = offset_in_page(addr);
7fc3cdab
MW		 1498 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1499 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1500 if (!pages)
1501 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1502
1503 err = get_user_pages_fast(addr, count, 1, pages);
1504 if (err < count) {
1505 count = err;
1506 err = -EFAULT;
1507 goto put_pages;
1508 }
7fc3cdab 1509
6808c5fb 1510 err = -ENOMEM;
1d090624 1511 iod = nvme_alloc_iod(count, length, dev, GFP_KERNEL);
6808c5fb
S		 1512 if (!iod)
1513 goto put_pages;
1514
eca18b23 1515 sg = iod->sg;
36c14ed9 1516 sg_init_table(sg, count);
d0ba1e49
MW		 1517 for (i = 0; i < count; i++) {
1518 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1519 min_t(unsigned, length, PAGE_SIZE - offset),
1520 offset);
d0ba1e49
MW		 1521 length -= (PAGE_SIZE - offset);
1522 offset = 0;
7fc3cdab 1523 }
fe304c43 1524 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1525 iod->nents = count;
7fc3cdab 1526
7fc3cdab
MW		 1527 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1528 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1529 if (!nents)
eca18b23 1530 goto free_iod;
b60503ba 1531
7fc3cdab 1532 kfree(pages);
eca18b23 1533 return iod;
b60503ba 1534
eca18b23
MW		 1535 free_iod:
1536 kfree(iod);
7fc3cdab
MW		 1537 put_pages:
1538 for (i = 0; i < count; i++)
1539 put_page(pages[i]);
1540 kfree(pages);
eca18b23 1541 return ERR_PTR(err);
7fc3cdab 1542}
b60503ba 1543
5d0f6131 1544void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1545 struct nvme_iod *iod)
7fc3cdab 1546{
1c2ad9fa 1547 int i;
b60503ba 1548
1c2ad9fa
MW		 1549 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1550 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1551
1c2ad9fa
MW		 1552 for (i = 0; i < iod->nents; i++)
1553 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1554}
b60503ba 1555
a53295b6
MW		 1556static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1557{
1558 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1559 struct nvme_user_io io;
1560 struct nvme_command c;
f410c680
KB		 1561 unsigned length, meta_len;
1562 int status, i;
1563 struct nvme_iod *iod, *meta_iod = NULL;
1564 dma_addr_t meta_dma_addr;
1565 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1566
1567 if (copy_from_user(&io, uio, sizeof(io)))
1568 return -EFAULT;
6c7d4945 1569 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1570 meta_len = (io.nblocks + 1) * ns->ms;
1571
1572 if (meta_len && ((io.metadata & 3) || !io.metadata))
1573 return -EINVAL;
6c7d4945
MW		 1574
1575 switch (io.opcode) {
1576 case nvme_cmd_write:
1577 case nvme_cmd_read:
6bbf1acd 1578 case nvme_cmd_compare:
eca18b23 1579 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1580 break;
6c7d4945 1581 default:
6bbf1acd 1582 return -EINVAL;
6c7d4945
MW		 1583 }
1584
eca18b23
MW		 1585 if (IS_ERR(iod))
1586 return PTR_ERR(iod);
a53295b6
MW		 1587
1588 memset(&c, 0, sizeof(c));
1589 c.rw.opcode = io.opcode;
1590 c.rw.flags = io.flags;
6c7d4945 1591 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1592 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1593 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1594 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1595 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1596 c.rw.reftag = cpu_to_le32(io.reftag);
1597 c.rw.apptag = cpu_to_le16(io.apptag);
1598 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1599
1600 if (meta_len) {
1b56749e
KB		 1601 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1602 meta_len);
f410c680
KB		 1603 if (IS_ERR(meta_iod)) {
1604 status = PTR_ERR(meta_iod);
1605 meta_iod = NULL;
1606 goto unmap;
1607 }
1608
1609 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1610 &meta_dma_addr, GFP_KERNEL);
1611 if (!meta_mem) {
1612 status = -ENOMEM;
1613 goto unmap;
1614 }
1615
1616 if (io.opcode & 1) {
1617 int meta_offset = 0;
1618
1619 for (i = 0; i < meta_iod->nents; i++) {
1620 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1621 meta_iod->sg[i].offset;
1622 memcpy(meta_mem + meta_offset, meta,
1623 meta_iod->sg[i].length);
1624 kunmap_atomic(meta);
1625 meta_offset += meta_iod->sg[i].length;
1626 }
1627 }
1628
1629 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1630 }
1631
edd10d33
KB		 1632 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1633 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1634 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1635
b77954cb
MW		 1636 if (length != (io.nblocks + 1) << ns->lba_shift)
1637 status = -ENOMEM;
1638 else
a4aea562 1639 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
a53295b6 1640
f410c680
KB		 1641 if (meta_len) {
1642 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1643 int meta_offset = 0;
1644
1645 for (i = 0; i < meta_iod->nents; i++) {
1646 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1647 meta_iod->sg[i].offset;
1648 memcpy(meta, meta_mem + meta_offset,
1649 meta_iod->sg[i].length);
1650 kunmap_atomic(meta);
1651 meta_offset += meta_iod->sg[i].length;
1652 }
1653 }
1654
1655 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1656 meta_dma_addr);
1657 }
1658
1659 unmap:
1c2ad9fa 1660 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1661 nvme_free_iod(dev, iod);
f410c680
KB		 1662
1663 if (meta_iod) {
1664 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1665 nvme_free_iod(dev, meta_iod);
1666 }
1667
a53295b6
MW		 1668 return status;
1669}
1670
a4aea562
MB		 1671static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1672 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1673{
7963e521 1674 struct nvme_passthru_cmd cmd;
6ee44cdc 1675 struct nvme_command c;
eca18b23 1676 int status, length;
c7d36ab8 1677 struct nvme_iod *uninitialized_var(iod);
94f370ca 1678 unsigned timeout;
6ee44cdc 1679
6bbf1acd
MW		 1680 if (!capable(CAP_SYS_ADMIN))
1681 return -EACCES;
1682 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1683 return -EFAULT;
6ee44cdc
MW		 1684
1685 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1686 c.common.opcode = cmd.opcode;
1687 c.common.flags = cmd.flags;
1688 c.common.nsid = cpu_to_le32(cmd.nsid);
1689 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1690 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1691 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1692 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1693 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1694 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1695 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1696 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1697
1698 length = cmd.data_len;
1699 if (cmd.data_len) {
49742188
MW		 1700 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1701 length);
eca18b23
MW		 1702 if (IS_ERR(iod))
1703 return PTR_ERR(iod);
edd10d33
KB		 1704 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1705 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1706 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1707 }
1708
94f370ca
KB		 1709 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1710 ADMIN_TIMEOUT;
a4aea562 1711
6bbf1acd 1712 if (length != cmd.data_len)
b77954cb 1713 status = -ENOMEM;
a4aea562
MB		 1714 else if (ns) {
1715 struct request *req;
1716
1717 req = blk_mq_alloc_request(ns->queue, WRITE,
1718 (GFP_KERNEL|__GFP_WAIT), false);
97fe3832
JA		 1719 if (IS_ERR(req))
1720 status = PTR_ERR(req);
a4aea562
MB		 1721 else {
1722 status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1723 timeout);
9d135bb8 1724 blk_mq_free_request(req);
a4aea562
MB		 1725 }
1726 } else
1727 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
eca18b23 1728
6bbf1acd 1729 if (cmd.data_len) {
1c2ad9fa 1730 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1731 nvme_free_iod(dev, iod);
6bbf1acd 1732 }
f4f117f6 1733
cf90bc48 1734 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1735 sizeof(cmd.result)))
1736 status = -EFAULT;
1737
6ee44cdc
MW		 1738 return status;
1739}
1740
b60503ba
MW		 1741static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1742 unsigned long arg)
1743{
1744 struct nvme_ns *ns = bdev->bd_disk->private_data;
1745
1746 switch (cmd) {
6bbf1acd 1747 case NVME_IOCTL_ID:
c3bfe717 1748 force_successful_syscall_return();
6bbf1acd
MW		 1749 return ns->ns_id;
1750 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1751 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1752 case NVME_IOCTL_IO_CMD:
a4aea562 1753 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1754 case NVME_IOCTL_SUBMIT_IO:
1755 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1756 case SG_GET_VERSION_NUM:
1757 return nvme_sg_get_version_num((void __user *)arg);
1758 case SG_IO:
1759 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1760 default:
1761 return -ENOTTY;
1762 }
1763}
1764
320a3827
KB		 1765#ifdef CONFIG_COMPAT
1766static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1767 unsigned int cmd, unsigned long arg)
1768{
320a3827
KB		 1769 switch (cmd) {
1770 case SG_IO:
e179729a 1771 return -ENOIOCTLCMD;
320a3827
KB		 1772 }
1773 return nvme_ioctl(bdev, mode, cmd, arg);
1774}
1775#else
1776#define nvme_compat_ioctl NULL
1777#endif
1778
9ac27090
KB		 1779static int nvme_open(struct block_device *bdev, fmode_t mode)
1780{
9e60352c
KB		 1781 int ret = 0;
1782 struct nvme_ns *ns;
9ac27090 1783
9e60352c
KB		 1784 spin_lock(&dev_list_lock);
1785 ns = bdev->bd_disk->private_data;
1786 if (!ns)
1787 ret = -ENXIO;
1788 else if (!kref_get_unless_zero(&ns->dev->kref))
1789 ret = -ENXIO;
1790 spin_unlock(&dev_list_lock);
1791
1792 return ret;
9ac27090
KB		 1793}
1794
1795static void nvme_free_dev(struct kref *kref);
1796
1797static void nvme_release(struct gendisk *disk, fmode_t mode)
1798{
1799 struct nvme_ns *ns = disk->private_data;
1800 struct nvme_dev *dev = ns->dev;
1801
1802 kref_put(&dev->kref, nvme_free_dev);
1803}
1804
4cc09e2d
KB		 1805static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1806{
1807 /* some standard values */
1808 geo->heads = 1 << 6;
1809 geo->sectors = 1 << 5;
1810 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1811 return 0;
1812}
1813
1b9dbf7f
KB		 1814static int nvme_revalidate_disk(struct gendisk *disk)
1815{
1816 struct nvme_ns *ns = disk->private_data;
1817 struct nvme_dev *dev = ns->dev;
1818 struct nvme_id_ns *id;
1819 dma_addr_t dma_addr;
1820 int lbaf;
1821
1822 id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
1823 GFP_KERNEL);
1824 if (!id) {
1825 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
1826 __func__);
1827 return 0;
1828 }
1829
1830 if (nvme_identify(dev, ns->ns_id, 0, dma_addr))
1831 goto free;
1832
1833 lbaf = id->flbas & 0xf;
1834 ns->lba_shift = id->lbaf[lbaf].ds;
1835
1836 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1837 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1838 free:
1839 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1840 return 0;
1841}
1842
b60503ba
MW		 1843static const struct block_device_operations nvme_fops = {
1844 .owner = THIS_MODULE,
1845 .ioctl = nvme_ioctl,
320a3827 1846 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1847 .open = nvme_open,
1848 .release = nvme_release,
4cc09e2d 1849 .getgeo = nvme_getgeo,
1b9dbf7f 1850 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 1851};
1852
1fa6aead
MW		 1853static int nvme_kthread(void *data)
1854{
d4b4ff8e 1855 struct nvme_dev *dev, *next;
1fa6aead
MW		 1856
1857 while (!kthread_should_stop()) {
564a232c 1858 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1859 spin_lock(&dev_list_lock);
d4b4ff8e 1860 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1861 int i;
d4b4ff8e
KB		 1862 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1863 dev->initialized) {
1864 if (work_busy(&dev->reset_work))
1865 continue;
1866 list_del_init(&dev->node);
1867 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1868 "Failed status: %x, reset controller\n",
1869 readl(&dev->bar->csts));
9ca97374 1870 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 1871 queue_work(nvme_workq, &dev->reset_work);
1872 continue;
1873 }
1fa6aead 1874 for (i = 0; i < dev->queue_count; i++) {
a4aea562 1875 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 1876 if (!nvmeq)
1877 continue;
1fa6aead 1878 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 1879 nvme_process_cq(nvmeq);
6fccf938
KB		 1880
1881 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 1882 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 1883 break;
1884 dev->event_limit--;
1885 }
1fa6aead
MW		 1886 spin_unlock_irq(&nvmeq->q_lock);
1887 }
1888 }
1889 spin_unlock(&dev_list_lock);
acb7aa0d 1890 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1891 }
1892 return 0;
1893}
1894
0e5e4f0e
KB		 1895static void nvme_config_discard(struct nvme_ns *ns)
1896{
1897 u32 logical_block_size = queue_logical_block_size(ns->queue);
1898 ns->queue->limits.discard_zeroes_data = 0;
1899 ns->queue->limits.discard_alignment = logical_block_size;
1900 ns->queue->limits.discard_granularity = logical_block_size;
1901 ns->queue->limits.max_discard_sectors = 0xffffffff;
1902 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1903}
1904
c3bfe717 1905static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1906 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1907{
1908 struct nvme_ns *ns;
1909 struct gendisk *disk;
a4aea562 1910 int node = dev_to_node(&dev->pci_dev->dev);
b60503ba
MW		 1911 int lbaf;
1912
1913 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1914 return NULL;
1915
a4aea562 1916 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba
MW		 1917 if (!ns)
1918 return NULL;
a4aea562 1919 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 1920 if (IS_ERR(ns->queue))
b60503ba 1921 goto out_free_ns;
4eeb9215
MW		 1922 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1923 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 1924 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 1925 ns->dev = dev;
1926 ns->queue->queuedata = ns;
1927
a4aea562 1928 disk = alloc_disk_node(0, node);
b60503ba
MW		 1929 if (!disk)
1930 goto out_free_queue;
a4aea562 1931
5aff9382 1932 ns->ns_id = nsid;
b60503ba
MW		 1933 ns->disk = disk;
1934 lbaf = id->flbas & 0xf;
1935 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1936 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1937 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1938 if (dev->max_hw_sectors)
1939 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 1940 if (dev->stripe_size)
1941 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 1942 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
1943 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 1944
1945 disk->major = nvme_major;
469071a3 1946 disk->first_minor = 0;
b60503ba
MW		 1947 disk->fops = &nvme_fops;
1948 disk->private_data = ns;
1949 disk->queue = ns->queue;
388f037f 1950 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1951 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1952 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1953 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1954
0e5e4f0e
KB		 1955 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1956 nvme_config_discard(ns);
1957
b60503ba
MW		 1958 return ns;
1959
1960 out_free_queue:
1961 blk_cleanup_queue(ns->queue);
1962 out_free_ns:
1963 kfree(ns);
1964 return NULL;
1965}
1966
42f61420
KB		 1967static void nvme_create_io_queues(struct nvme_dev *dev)
1968{
a4aea562 1969 unsigned i;
42f61420 1970
a4aea562 1971 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 1972 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 1973 break;
1974
a4aea562
MB		 1975 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
1976 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 1977 break;
1978}
1979
b3b06812 1980static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 1981{
1982 int status;
1983 u32 result;
b3b06812 1984 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 1985
df348139 1986 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 1987 &result);
27e8166c
MW		 1988 if (status < 0)
1989 return status;
1990 if (status > 0) {
1991 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
1992 status);
badc34d4 1993 return 0;
27e8166c 1994 }
b60503ba
MW		 1995 return min(result & 0xffff, result >> 16) + 1;
1996}
1997
9d713c2b
KB		 1998static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1999{
b80d5ccc 2000 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2001}
2002
8d85fce7 2003static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2004{
a4aea562 2005 struct nvme_queue *adminq = dev->queues[0];
fa08a396 2006 struct pci_dev *pdev = dev->pci_dev;
42f61420 2007 int result, i, vecs, nr_io_queues, size;
b60503ba 2008
42f61420 2009 nr_io_queues = num_possible_cpus();
b348b7d5 2010 result = set_queue_count(dev, nr_io_queues);
badc34d4 2011 if (result <= 0)
1b23484b 2012 return result;
b348b7d5
MW		 2013 if (result < nr_io_queues)
2014 nr_io_queues = result;
b60503ba 2015
9d713c2b
KB		 2016 size = db_bar_size(dev, nr_io_queues);
2017 if (size > 8192) {
f1938f6e 2018 iounmap(dev->bar);
9d713c2b
KB		 2019 do {
2020 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2021 if (dev->bar)
2022 break;
2023 if (!--nr_io_queues)
2024 return -ENOMEM;
2025 size = db_bar_size(dev, nr_io_queues);
2026 } while (1);
f1938f6e 2027 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2028 adminq->q_db = dev->dbs;
f1938f6e
MW		 2029 }
2030
9d713c2b 2031 /* Deregister the admin queue's interrupt */
3193f07b 2032 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2033
e32efbfc
JA		 2034 /*
2035 * If we enable msix early due to not intx, disable it again before
2036 * setting up the full range we need.
2037 */
2038 if (!pdev->irq)
2039 pci_disable_msix(pdev);
2040
be577fab 2041 for (i = 0; i < nr_io_queues; i++)
1b23484b 2042 dev->entry[i].entry = i;
be577fab
AG		 2043 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2044 if (vecs < 0) {
2045 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2046 if (vecs < 0) {
2047 vecs = 1;
2048 } else {
2049 for (i = 0; i < vecs; i++)
2050 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2051 }
2052 }
2053
063a8096
MW		 2054 /*
2055 * Should investigate if there's a performance win from allocating
2056 * more queues than interrupt vectors; it might allow the submission
2057 * path to scale better, even if the receive path is limited by the
2058 * number of interrupts.
2059 */
2060 nr_io_queues = vecs;
42f61420 2061 dev->max_qid = nr_io_queues;
063a8096 2062
3193f07b 2063 result = queue_request_irq(dev, adminq, adminq->irqname);
a4aea562 2064 if (result)
22404274 2065 goto free_queues;
1b23484b 2066
cd638946 2067 /* Free previously allocated queues that are no longer usable */
42f61420 2068 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2069 nvme_create_io_queues(dev);
9ecdc946 2070
22404274 2071 return 0;
b60503ba 2072
22404274 2073 free_queues:
a1a5ef99 2074 nvme_free_queues(dev, 1);
22404274 2075 return result;
b60503ba
MW		 2076}
2077
422ef0c7
MW		 2078/*
2079 * Return: error value if an error occurred setting up the queues or calling
2080 * Identify Device. 0 if these succeeded, even if adding some of the
2081 * namespaces failed. At the moment, these failures are silent. TBD which
2082 * failures should be reported.
2083 */
8d85fce7 2084static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2085{
68608c26 2086 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2087 int res;
2088 unsigned nn, i;
cbb6218f 2089 struct nvme_ns *ns;
51814232 2090 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2091 struct nvme_id_ns *id_ns;
2092 void *mem;
b60503ba 2093 dma_addr_t dma_addr;
159b67d7 2094 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2095
68608c26 2096 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2097 if (!mem)
2098 return -ENOMEM;
b60503ba 2099
bc5fc7e4 2100 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2101 if (res) {
27e8166c 2102 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
b60503ba 2103 res = -EIO;
cbb6218f 2104 goto out;
b60503ba
MW		 2105 }
2106
bc5fc7e4 2107 ctrl = mem;
51814232 2108 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2109 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2110 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2111 dev->vwc = ctrl->vwc;
6fccf938 2112 dev->event_limit = min(ctrl->aerl + 1, 8);
51814232
MW		 2113 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2114 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2115 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2116 if (ctrl->mdts)
8fc23e03 2117 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2118 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2119 (pdev->device == 0x0953) && ctrl->vs[3]) {
2120 unsigned int max_hw_sectors;
2121
159b67d7 2122 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2123 max_hw_sectors = dev->stripe_size >> (shift - 9);
2124 if (dev->max_hw_sectors) {
2125 dev->max_hw_sectors = min(max_hw_sectors,
2126 dev->max_hw_sectors);
2127 } else
2128 dev->max_hw_sectors = max_hw_sectors;
2129 }
2130
2131 dev->tagset.ops = &nvme_mq_ops;
2132 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2133 dev->tagset.timeout = NVME_IO_TIMEOUT;
2134 dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2135 dev->tagset.queue_depth =
2136 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2137 dev->tagset.cmd_size = sizeof(struct nvme_cmd_info);
2138 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2139 dev->tagset.driver_data = dev;
2140
2141 if (blk_mq_alloc_tag_set(&dev->tagset))
2142 goto out;
b60503ba 2143
bc5fc7e4 2144 id_ns = mem;
2b2c1896 2145 for (i = 1; i <= nn; i++) {
bc5fc7e4 2146 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2147 if (res)
2148 continue;
2149
bc5fc7e4 2150 if (id_ns->ncap == 0)
b60503ba
MW		 2151 continue;
2152
bc5fc7e4 2153 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2154 dma_addr + 4096, NULL);
b60503ba 2155 if (res)
12209036 2156 memset(mem + 4096, 0, 4096);
b60503ba 2157
bc5fc7e4 2158 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2159 if (ns)
2160 list_add_tail(&ns->list, &dev->namespaces);
2161 }
2162 list_for_each_entry(ns, &dev->namespaces, list)
2163 add_disk(ns->disk);
422ef0c7 2164 res = 0;
b60503ba 2165
bc5fc7e4 2166 out:
684f5c20 2167 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2168 return res;
2169}
2170
0877cb0d
KB		 2171static int nvme_dev_map(struct nvme_dev *dev)
2172{
42f61420 2173 u64 cap;
0877cb0d
KB		 2174 int bars, result = -ENOMEM;
2175 struct pci_dev *pdev = dev->pci_dev;
2176
2177 if (pci_enable_device_mem(pdev))
2178 return result;
2179
2180 dev->entry[0].vector = pdev->irq;
2181 pci_set_master(pdev);
2182 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2183 if (!bars)
2184 goto disable_pci;
2185
0877cb0d
KB		 2186 if (pci_request_selected_regions(pdev, bars, "nvme"))
2187 goto disable_pci;
2188
052d0efa
RK		 2189 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2190 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2191 goto disable;
0877cb0d 2192
0877cb0d
KB		 2193 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2194 if (!dev->bar)
2195 goto disable;
e32efbfc 2196
0e53d180
KB		 2197 if (readl(&dev->bar->csts) == -1) {
2198 result = -ENODEV;
2199 goto unmap;
2200 }
e32efbfc
JA		 2201
2202 /*
2203 * Some devices don't advertse INTx interrupts, pre-enable a single
2204 * MSIX vec for setup. We'll adjust this later.
2205 */
2206 if (!pdev->irq) {
2207 result = pci_enable_msix(pdev, dev->entry, 1);
2208 if (result < 0)
2209 goto unmap;
2210 }
2211
42f61420
KB		 2212 cap = readq(&dev->bar->cap);
2213 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2214 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2215 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2216
2217 return 0;
2218
0e53d180
KB		 2219 unmap:
2220 iounmap(dev->bar);
2221 dev->bar = NULL;
0877cb0d
KB		 2222 disable:
2223 pci_release_regions(pdev);
2224 disable_pci:
2225 pci_disable_device(pdev);
2226 return result;
2227}
2228
2229static void nvme_dev_unmap(struct nvme_dev *dev)
2230{
2231 if (dev->pci_dev->msi_enabled)
2232 pci_disable_msi(dev->pci_dev);
2233 else if (dev->pci_dev->msix_enabled)
2234 pci_disable_msix(dev->pci_dev);
2235
2236 if (dev->bar) {
2237 iounmap(dev->bar);
2238 dev->bar = NULL;
9a6b9458 2239 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2240 }
2241
0877cb0d
KB		 2242 if (pci_is_enabled(dev->pci_dev))
2243 pci_disable_device(dev->pci_dev);
2244}
2245
4d115420
KB		 2246struct nvme_delq_ctx {
2247 struct task_struct *waiter;
2248 struct kthread_worker *worker;
2249 atomic_t refcount;
2250};
2251
2252static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2253{
2254 dq->waiter = current;
2255 mb();
2256
2257 for (;;) {
2258 set_current_state(TASK_KILLABLE);
2259 if (!atomic_read(&dq->refcount))
2260 break;
2261 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2262 fatal_signal_pending(current)) {
0fb59cbc
KB		 2263 /*
2264 * Disable the controller first since we can't trust it
2265 * at this point, but leave the admin queue enabled
2266 * until all queue deletion requests are flushed.
2267 * FIXME: This may take a while if there are more h/w
2268 * queues than admin tags.
2269 */
4d115420 2270 set_current_state(TASK_RUNNING);
4d115420 2271 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2272 nvme_clear_queue(dev->queues[0]);
4d115420 2273 flush_kthread_worker(dq->worker);
0fb59cbc 2274 nvme_disable_queue(dev, 0);
4d115420
KB		 2275 return;
2276 }
2277 }
2278 set_current_state(TASK_RUNNING);
2279}
2280
2281static void nvme_put_dq(struct nvme_delq_ctx *dq)
2282{
2283 atomic_dec(&dq->refcount);
2284 if (dq->waiter)
2285 wake_up_process(dq->waiter);
2286}
2287
2288static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2289{
2290 atomic_inc(&dq->refcount);
2291 return dq;
2292}
2293
2294static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2295{
2296 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2297
2298 nvme_clear_queue(nvmeq);
2299 nvme_put_dq(dq);
2300}
2301
2302static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2303 kthread_work_func_t fn)
2304{
2305 struct nvme_command c;
2306
2307 memset(&c, 0, sizeof(c));
2308 c.delete_queue.opcode = opcode;
2309 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2310
2311 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2312 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2313 ADMIN_TIMEOUT);
4d115420
KB		 2314}
2315
2316static void nvme_del_cq_work_handler(struct kthread_work *work)
2317{
2318 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2319 cmdinfo.work);
2320 nvme_del_queue_end(nvmeq);
2321}
2322
2323static int nvme_delete_cq(struct nvme_queue *nvmeq)
2324{
2325 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2326 nvme_del_cq_work_handler);
2327}
2328
2329static void nvme_del_sq_work_handler(struct kthread_work *work)
2330{
2331 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2332 cmdinfo.work);
2333 int status = nvmeq->cmdinfo.status;
2334
2335 if (!status)
2336 status = nvme_delete_cq(nvmeq);
2337 if (status)
2338 nvme_del_queue_end(nvmeq);
2339}
2340
2341static int nvme_delete_sq(struct nvme_queue *nvmeq)
2342{
2343 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2344 nvme_del_sq_work_handler);
2345}
2346
2347static void nvme_del_queue_start(struct kthread_work *work)
2348{
2349 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2350 cmdinfo.work);
4d115420
KB		 2351 if (nvme_delete_sq(nvmeq))
2352 nvme_del_queue_end(nvmeq);
2353}
2354
2355static void nvme_disable_io_queues(struct nvme_dev *dev)
2356{
2357 int i;
2358 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2359 struct nvme_delq_ctx dq;
2360 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2361 &worker, "nvme%d", dev->instance);
2362
2363 if (IS_ERR(kworker_task)) {
2364 dev_err(&dev->pci_dev->dev,
2365 "Failed to create queue del task\n");
2366 for (i = dev->queue_count - 1; i > 0; i--)
2367 nvme_disable_queue(dev, i);
2368 return;
2369 }
2370
2371 dq.waiter = NULL;
2372 atomic_set(&dq.refcount, 0);
2373 dq.worker = &worker;
2374 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2375 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2376
2377 if (nvme_suspend_queue(nvmeq))
2378 continue;
2379 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2380 nvmeq->cmdinfo.worker = dq.worker;
2381 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2382 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2383 }
2384 nvme_wait_dq(&dq, dev);
2385 kthread_stop(kworker_task);
2386}
2387
b9afca3e
DM		 2388/*
2389* Remove the node from the device list and check
2390* for whether or not we need to stop the nvme_thread.
2391*/
2392static void nvme_dev_list_remove(struct nvme_dev *dev)
2393{
2394 struct task_struct *tmp = NULL;
2395
2396 spin_lock(&dev_list_lock);
2397 list_del_init(&dev->node);
2398 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2399 tmp = nvme_thread;
2400 nvme_thread = NULL;
2401 }
2402 spin_unlock(&dev_list_lock);
2403
2404 if (tmp)
2405 kthread_stop(tmp);
2406}
2407
f0b50732 2408static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2409{
22404274 2410 int i;
7c1b2450 2411 u32 csts = -1;
22404274 2412
d4b4ff8e 2413 dev->initialized = 0;
b9afca3e 2414 nvme_dev_list_remove(dev);
1fa6aead 2415
7c1b2450
KB		 2416 if (dev->bar)
2417 csts = readl(&dev->bar->csts);
2418 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2419 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2420 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2421 nvme_suspend_queue(nvmeq);
2422 nvme_clear_queue(nvmeq);
2423 }
2424 } else {
2425 nvme_disable_io_queues(dev);
1894d8f1 2426 nvme_shutdown_ctrl(dev);
4d115420
KB		 2427 nvme_disable_queue(dev, 0);
2428 }
f0b50732
KB		 2429 nvme_dev_unmap(dev);
2430}
2431
2432static void nvme_dev_remove(struct nvme_dev *dev)
2433{
9ac27090 2434 struct nvme_ns *ns;
f0b50732 2435
9ac27090
KB		 2436 list_for_each_entry(ns, &dev->namespaces, list) {
2437 if (ns->disk->flags & GENHD_FL_UP)
2438 del_gendisk(ns->disk);
cef6a948
KB		 2439 if (!blk_queue_dying(ns->queue)) {
2440 blk_mq_abort_requeue_list(ns->queue);
9ac27090 2441 blk_cleanup_queue(ns->queue);
cef6a948 2442 }
b60503ba 2443 }
b60503ba
MW		 2444}
2445
091b6092
MW		 2446static int nvme_setup_prp_pools(struct nvme_dev *dev)
2447{
2448 struct device *dmadev = &dev->pci_dev->dev;
2449 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2450 PAGE_SIZE, PAGE_SIZE, 0);
2451 if (!dev->prp_page_pool)
2452 return -ENOMEM;
2453
99802a7a
MW		 2454 /* Optimisation for I/Os between 4k and 128k */
2455 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2456 256, 256, 0);
2457 if (!dev->prp_small_pool) {
2458 dma_pool_destroy(dev->prp_page_pool);
2459 return -ENOMEM;
2460 }
091b6092
MW		 2461 return 0;
2462}
2463
2464static void nvme_release_prp_pools(struct nvme_dev *dev)
2465{
2466 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2467 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2468}
2469
cd58ad7d
QSA		 2470static DEFINE_IDA(nvme_instance_ida);
2471
2472static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2473{
cd58ad7d
QSA		 2474 int instance, error;
2475
2476 do {
2477 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2478 return -ENODEV;
2479
2480 spin_lock(&dev_list_lock);
2481 error = ida_get_new(&nvme_instance_ida, &instance);
2482 spin_unlock(&dev_list_lock);
2483 } while (error == -EAGAIN);
2484
2485 if (error)
2486 return -ENODEV;
2487
2488 dev->instance = instance;
2489 return 0;
b60503ba
MW		 2490}
2491
2492static void nvme_release_instance(struct nvme_dev *dev)
2493{
cd58ad7d
QSA		 2494 spin_lock(&dev_list_lock);
2495 ida_remove(&nvme_instance_ida, dev->instance);
2496 spin_unlock(&dev_list_lock);
b60503ba
MW		 2497}
2498
9ac27090
KB		 2499static void nvme_free_namespaces(struct nvme_dev *dev)
2500{
2501 struct nvme_ns *ns, *next;
2502
2503 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2504 list_del(&ns->list);
9e60352c
KB		 2505
2506 spin_lock(&dev_list_lock);
2507 ns->disk->private_data = NULL;
2508 spin_unlock(&dev_list_lock);
2509
9ac27090
KB		 2510 put_disk(ns->disk);
2511 kfree(ns);
2512 }
2513}
2514
5e82e952
KB		 2515static void nvme_free_dev(struct kref *kref)
2516{
2517 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2518
a96d4f5c 2519 pci_dev_put(dev->pci_dev);
9ac27090 2520 nvme_free_namespaces(dev);
285dffc9 2521 nvme_release_instance(dev);
a4aea562 2522 blk_mq_free_tag_set(&dev->tagset);
ea191d2f 2523 blk_put_queue(dev->admin_q);
5e82e952
KB		 2524 kfree(dev->queues);
2525 kfree(dev->entry);
2526 kfree(dev);
2527}
2528
2529static int nvme_dev_open(struct inode *inode, struct file *f)
2530{
2531 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2532 miscdev);
2533 kref_get(&dev->kref);
2534 f->private_data = dev;
2535 return 0;
2536}
2537
2538static int nvme_dev_release(struct inode *inode, struct file *f)
2539{
2540 struct nvme_dev *dev = f->private_data;
2541 kref_put(&dev->kref, nvme_free_dev);
2542 return 0;
2543}
2544
2545static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2546{
2547 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2548 struct nvme_ns *ns;
2549
5e82e952
KB		 2550 switch (cmd) {
2551 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2552 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2553 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2554 if (list_empty(&dev->namespaces))
2555 return -ENOTTY;
2556 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2557 return nvme_user_cmd(dev, ns, (void __user *)arg);
5e82e952
KB		 2558 default:
2559 return -ENOTTY;
2560 }
2561}
2562
2563static const struct file_operations nvme_dev_fops = {
2564 .owner = THIS_MODULE,
2565 .open = nvme_dev_open,
2566 .release = nvme_dev_release,
2567 .unlocked_ioctl = nvme_dev_ioctl,
2568 .compat_ioctl = nvme_dev_ioctl,
2569};
2570
a4aea562
MB		 2571static void nvme_set_irq_hints(struct nvme_dev *dev)
2572{
2573 struct nvme_queue *nvmeq;
2574 int i;
2575
2576 for (i = 0; i < dev->online_queues; i++) {
2577 nvmeq = dev->queues[i];
2578
2579 if (!nvmeq->hctx)
2580 continue;
2581
2582 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2583 nvmeq->hctx->cpumask);
2584 }
2585}
2586
f0b50732
KB		 2587static int nvme_dev_start(struct nvme_dev *dev)
2588{
2589 int result;
b9afca3e 2590 bool start_thread = false;
f0b50732
KB		 2591
2592 result = nvme_dev_map(dev);
2593 if (result)
2594 return result;
2595
2596 result = nvme_configure_admin_queue(dev);
2597 if (result)
2598 goto unmap;
2599
2600 spin_lock(&dev_list_lock);
b9afca3e
DM		 2601 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2602 start_thread = true;
2603 nvme_thread = NULL;
2604 }
f0b50732
KB		 2605 list_add(&dev->node, &dev_list);
2606 spin_unlock(&dev_list_lock);
2607
b9afca3e
DM		 2608 if (start_thread) {
2609 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2610 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2611 } else
2612 wait_event_killable(nvme_kthread_wait, nvme_thread);
2613
2614 if (IS_ERR_OR_NULL(nvme_thread)) {
2615 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2616 goto disable;
2617 }
a4aea562
MB		 2618
2619 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 2620 result = nvme_alloc_admin_tags(dev);
2621 if (result)
2622 goto disable;
b9afca3e 2623
f0b50732 2624 result = nvme_setup_io_queues(dev);
badc34d4 2625 if (result)
0fb59cbc 2626 goto free_tags;
f0b50732 2627
a4aea562
MB		 2628 nvme_set_irq_hints(dev);
2629
d82e8bfd 2630 return result;
f0b50732 2631
0fb59cbc
KB		 2632 free_tags:
2633 nvme_dev_remove_admin(dev);
f0b50732 2634 disable:
a1a5ef99 2635 nvme_disable_queue(dev, 0);
b9afca3e 2636 nvme_dev_list_remove(dev);
f0b50732
KB		 2637 unmap:
2638 nvme_dev_unmap(dev);
2639 return result;
2640}
2641
9a6b9458
KB		 2642static int nvme_remove_dead_ctrl(void *arg)
2643{
2644 struct nvme_dev *dev = (struct nvme_dev *)arg;
2645 struct pci_dev *pdev = dev->pci_dev;
2646
2647 if (pci_get_drvdata(pdev))
c81f4975 2648 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2649 kref_put(&dev->kref, nvme_free_dev);
2650 return 0;
2651}
2652
2653static void nvme_remove_disks(struct work_struct *ws)
2654{
9a6b9458
KB		 2655 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2656
5a92e700 2657 nvme_free_queues(dev, 1);
302c6727 2658 nvme_dev_remove(dev);
9a6b9458
KB		 2659}
2660
2661static int nvme_dev_resume(struct nvme_dev *dev)
2662{
2663 int ret;
2664
2665 ret = nvme_dev_start(dev);
badc34d4 2666 if (ret)
9a6b9458 2667 return ret;
badc34d4 2668 if (dev->online_queues < 2) {
9a6b9458 2669 spin_lock(&dev_list_lock);
9ca97374 2670 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2671 queue_work(nvme_workq, &dev->reset_work);
2672 spin_unlock(&dev_list_lock);
2673 }
d4b4ff8e 2674 dev->initialized = 1;
9a6b9458
KB		 2675 return 0;
2676}
2677
2678static void nvme_dev_reset(struct nvme_dev *dev)
2679{
2680 nvme_dev_shutdown(dev);
2681 if (nvme_dev_resume(dev)) {
a4aea562 2682 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
9a6b9458
KB		 2683 kref_get(&dev->kref);
2684 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2685 dev->instance))) {
2686 dev_err(&dev->pci_dev->dev,
2687 "Failed to start controller remove task\n");
2688 kref_put(&dev->kref, nvme_free_dev);
2689 }
2690 }
2691}
2692
2693static void nvme_reset_failed_dev(struct work_struct *ws)
2694{
2695 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2696 nvme_dev_reset(dev);
2697}
2698
9ca97374
TH		 2699static void nvme_reset_workfn(struct work_struct *work)
2700{
2701 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2702 dev->reset_workfn(work);
2703}
2704
8d85fce7 2705static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2706{
a4aea562 2707 int node, result = -ENOMEM;
b60503ba
MW		 2708 struct nvme_dev *dev;
2709
a4aea562
MB		 2710 node = dev_to_node(&pdev->dev);
2711 if (node == NUMA_NO_NODE)
2712 set_dev_node(&pdev->dev, 0);
2713
2714 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2715 if (!dev)
2716 return -ENOMEM;
a4aea562
MB		 2717 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2718 GFP_KERNEL, node);
b60503ba
MW		 2719 if (!dev->entry)
2720 goto free;
a4aea562
MB		 2721 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2722 GFP_KERNEL, node);
b60503ba
MW		 2723 if (!dev->queues)
2724 goto free;
2725
2726 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2727 dev->reset_workfn = nvme_reset_failed_dev;
2728 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
a96d4f5c 2729 dev->pci_dev = pci_dev_get(pdev);
9a6b9458 2730 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2731 result = nvme_set_instance(dev);
2732 if (result)
a96d4f5c 2733 goto put_pci;
b60503ba 2734
091b6092
MW		 2735 result = nvme_setup_prp_pools(dev);
2736 if (result)
0877cb0d 2737 goto release;
091b6092 2738
fb35e914 2739 kref_init(&dev->kref);
f0b50732 2740 result = nvme_dev_start(dev);
badc34d4 2741 if (result)
0877cb0d 2742 goto release_pools;
b60503ba 2743
badc34d4
KB		 2744 if (dev->online_queues > 1)
2745 result = nvme_dev_add(dev);
d82e8bfd 2746 if (result)
f0b50732 2747 goto shutdown;
740216fc 2748
5e82e952
KB		 2749 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2750 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2751 dev->miscdev.parent = &pdev->dev;
2752 dev->miscdev.name = dev->name;
2753 dev->miscdev.fops = &nvme_dev_fops;
2754 result = misc_register(&dev->miscdev);
2755 if (result)
2756 goto remove;
2757
a4aea562
MB		 2758 nvme_set_irq_hints(dev);
2759
d4b4ff8e 2760 dev->initialized = 1;
b60503ba
MW		 2761 return 0;
2762
5e82e952
KB		 2763 remove:
2764 nvme_dev_remove(dev);
a4aea562 2765 nvme_dev_remove_admin(dev);
9ac27090 2766 nvme_free_namespaces(dev);
f0b50732
KB		 2767 shutdown:
2768 nvme_dev_shutdown(dev);
0877cb0d 2769 release_pools:
a1a5ef99 2770 nvme_free_queues(dev, 0);
091b6092 2771 nvme_release_prp_pools(dev);
0877cb0d
KB		 2772 release:
2773 nvme_release_instance(dev);
a96d4f5c
KB		 2774 put_pci:
2775 pci_dev_put(dev->pci_dev);
b60503ba
MW		 2776 free:
2777 kfree(dev->queues);
2778 kfree(dev->entry);
2779 kfree(dev);
2780 return result;
2781}
2782
f0d54a54
KB		 2783static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2784{
a6739479 2785 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 2786
a6739479
KB		 2787 if (prepare)
2788 nvme_dev_shutdown(dev);
2789 else
2790 nvme_dev_resume(dev);
f0d54a54
KB		 2791}
2792
09ece142
KB		 2793static void nvme_shutdown(struct pci_dev *pdev)
2794{
2795 struct nvme_dev *dev = pci_get_drvdata(pdev);
2796 nvme_dev_shutdown(dev);
2797}
2798
8d85fce7 2799static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2800{
2801 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2802
2803 spin_lock(&dev_list_lock);
2804 list_del_init(&dev->node);
2805 spin_unlock(&dev_list_lock);
2806
2807 pci_set_drvdata(pdev, NULL);
2808 flush_work(&dev->reset_work);
5e82e952 2809 misc_deregister(&dev->miscdev);
a4aea562 2810 nvme_dev_remove(dev);
9a6b9458 2811 nvme_dev_shutdown(dev);
a4aea562 2812 nvme_dev_remove_admin(dev);
a1a5ef99 2813 nvme_free_queues(dev, 0);
9a6b9458 2814 nvme_release_prp_pools(dev);
5e82e952 2815 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2816}
2817
2818/* These functions are yet to be implemented */
2819#define nvme_error_detected NULL
2820#define nvme_dump_registers NULL
2821#define nvme_link_reset NULL
2822#define nvme_slot_reset NULL
2823#define nvme_error_resume NULL
cd638946 2824
671a6018 2825#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2826static int nvme_suspend(struct device *dev)
2827{
2828 struct pci_dev *pdev = to_pci_dev(dev);
2829 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2830
2831 nvme_dev_shutdown(ndev);
2832 return 0;
2833}
2834
2835static int nvme_resume(struct device *dev)
2836{
2837 struct pci_dev *pdev = to_pci_dev(dev);
2838 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2839
9a6b9458 2840 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2841 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 2842 queue_work(nvme_workq, &ndev->reset_work);
2843 }
2844 return 0;
cd638946 2845}
671a6018 2846#endif
cd638946
KB		 2847
2848static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2849
1d352035 2850static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2851 .error_detected = nvme_error_detected,
2852 .mmio_enabled = nvme_dump_registers,
2853 .link_reset = nvme_link_reset,
2854 .slot_reset = nvme_slot_reset,
2855 .resume = nvme_error_resume,
f0d54a54 2856 .reset_notify = nvme_reset_notify,
b60503ba
MW		 2857};
2858
2859/* Move to pci_ids.h later */
2860#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2861
6eb0d698 2862static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2863 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2864 { 0, }
2865};
2866MODULE_DEVICE_TABLE(pci, nvme_id_table);
2867
2868static struct pci_driver nvme_driver = {
2869 .name = "nvme",
2870 .id_table = nvme_id_table,
2871 .probe = nvme_probe,
8d85fce7 2872 .remove = nvme_remove,
09ece142 2873 .shutdown = nvme_shutdown,
cd638946
KB		 2874 .driver = {
2875 .pm = &nvme_dev_pm_ops,
2876 },
b60503ba
MW		 2877 .err_handler = &nvme_err_handler,
2878};
2879
2880static int __init nvme_init(void)
2881{
0ac13140 2882 int result;
1fa6aead 2883
b9afca3e 2884 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2885
9a6b9458
KB		 2886 nvme_workq = create_singlethread_workqueue("nvme");
2887 if (!nvme_workq)
b9afca3e 2888 return -ENOMEM;
9a6b9458 2889
5c42ea16
KB		 2890 result = register_blkdev(nvme_major, "nvme");
2891 if (result < 0)
9a6b9458 2892 goto kill_workq;
5c42ea16 2893 else if (result > 0)
0ac13140 2894 nvme_major = result;
b60503ba 2895
f3db22fe
KB		 2896 result = pci_register_driver(&nvme_driver);
2897 if (result)
a4aea562 2898 goto unregister_blkdev;
1fa6aead 2899 return 0;
b60503ba 2900
1fa6aead 2901 unregister_blkdev:
b60503ba 2902 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2903 kill_workq:
2904 destroy_workqueue(nvme_workq);
b60503ba
MW		 2905 return result;
2906}
2907
2908static void __exit nvme_exit(void)
2909{
2910 pci_unregister_driver(&nvme_driver);
f3db22fe 2911 unregister_hotcpu_notifier(&nvme_nb);
b60503ba 2912 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2913 destroy_workqueue(nvme_workq);
b9afca3e 2914 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 2915 _nvme_check_size();
b60503ba
MW		 2916}
2917
2918MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2919MODULE_LICENSE("GPL");
c78b4713 2920MODULE_VERSION("1.0");
b60503ba
MW		 2921module_init(nvme_init);
2922module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)