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Merge branch 'master' into for-3.19/drivers
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
40#include <linux/types.h>
5d0f6131 41#include <scsi/sg.h>
797a796a
HM		 42#include <asm-generic/io-64-nonatomic-lo-hi.h>
43
9d43cf64 44#define NVME_Q_DEPTH 1024
a4aea562 45#define NVME_AQ_DEPTH 64
b60503ba
MW		 46#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 48#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 49#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 50#define IOD_TIMEOUT (retry_time * HZ)
51
52static unsigned char admin_timeout = 60;
53module_param(admin_timeout, byte, 0644);
54MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 55
bd67608a
MW		 56unsigned char nvme_io_timeout = 30;
57module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 58MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 59
61e4ce08
KB		 60static unsigned char retry_time = 30;
61module_param(retry_time, byte, 0644);
62MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
63
2484f407
DM		 64static unsigned char shutdown_timeout = 5;
65module_param(shutdown_timeout, byte, 0644);
66MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
67
b60503ba
MW		 68static int nvme_major;
69module_param(nvme_major, int, 0);
70
58ffacb5
MW		 71static int use_threaded_interrupts;
72module_param(use_threaded_interrupts, int, 0);
73
1fa6aead
MW		 74static DEFINE_SPINLOCK(dev_list_lock);
75static LIST_HEAD(dev_list);
76static struct task_struct *nvme_thread;
9a6b9458 77static struct workqueue_struct *nvme_workq;
b9afca3e 78static wait_queue_head_t nvme_kthread_wait;
f3db22fe 79static struct notifier_block nvme_nb;
1fa6aead 80
d4b4ff8e 81static void nvme_reset_failed_dev(struct work_struct *ws);
a4aea562 82static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 83
4d115420
KB		 84struct async_cmd_info {
85 struct kthread_work work;
86 struct kthread_worker *worker;
a4aea562 87 struct request *req;
4d115420
KB		 88 u32 result;
89 int status;
90 void *ctx;
91};
1fa6aead 92
b60503ba
MW		 93/*
94 * An NVM Express queue. Each device has at least two (one for admin
95 * commands and one for I/O commands).
96 */
97struct nvme_queue {
f435c282 98 struct llist_node node;
b60503ba 99 struct device *q_dmadev;
091b6092 100 struct nvme_dev *dev;
3193f07b 101 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 102 spinlock_t q_lock;
103 struct nvme_command *sq_cmds;
104 volatile struct nvme_completion *cqes;
105 dma_addr_t sq_dma_addr;
106 dma_addr_t cq_dma_addr;
b60503ba
MW		 107 u32 __iomem *q_db;
108 u16 q_depth;
109 u16 cq_vector;
110 u16 sq_head;
111 u16 sq_tail;
112 u16 cq_head;
c30341dc 113 u16 qid;
e9539f47
MW		 114 u8 cq_phase;
115 u8 cqe_seen;
4d115420 116 struct async_cmd_info cmdinfo;
a4aea562 117 struct blk_mq_hw_ctx *hctx;
b60503ba
MW		 118};
119
120/*
121 * Check we didin't inadvertently grow the command struct
122 */
123static inline void _nvme_check_size(void)
124{
125 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 130 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 131 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 136 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 137}
138
edd10d33 139typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 140 struct nvme_completion *);
141
e85248e5 142struct nvme_cmd_info {
c2f5b650
MW		 143 nvme_completion_fn fn;
144 void *ctx;
c30341dc 145 int aborted;
a4aea562 146 struct nvme_queue *nvmeq;
e85248e5
MW		 147};
148
a4aea562
MB		 149static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
150 unsigned int hctx_idx)
e85248e5 151{
a4aea562
MB		 152 struct nvme_dev *dev = data;
153 struct nvme_queue *nvmeq = dev->queues[0];
154
155 WARN_ON(nvmeq->hctx);
156 nvmeq->hctx = hctx;
157 hctx->driver_data = nvmeq;
158 return 0;
e85248e5
MW		 159}
160
a4aea562
MB		 161static int nvme_admin_init_request(void *data, struct request *req,
162 unsigned int hctx_idx, unsigned int rq_idx,
163 unsigned int numa_node)
22404274 164{
a4aea562
MB		 165 struct nvme_dev *dev = data;
166 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
167 struct nvme_queue *nvmeq = dev->queues[0];
168
169 BUG_ON(!nvmeq);
170 cmd->nvmeq = nvmeq;
171 return 0;
22404274
KB		 172}
173
a4aea562
MB		 174static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
175 unsigned int hctx_idx)
b60503ba 176{
a4aea562
MB		 177 struct nvme_dev *dev = data;
178 struct nvme_queue *nvmeq = dev->queues[
179 (hctx_idx % dev->queue_count) + 1];
b60503ba 180
a4aea562
MB		 181 if (!nvmeq->hctx)
182 nvmeq->hctx = hctx;
183
184 /* nvmeq queues are shared between namespaces. We assume here that
185 * blk-mq map the tags so they match up with the nvme queue tags. */
186 WARN_ON(nvmeq->hctx->tags != hctx->tags);
b60503ba 187
a4aea562
MB		 188 hctx->driver_data = nvmeq;
189 return 0;
b60503ba
MW		 190}
191
a4aea562
MB		 192static int nvme_init_request(void *data, struct request *req,
193 unsigned int hctx_idx, unsigned int rq_idx,
194 unsigned int numa_node)
b60503ba 195{
a4aea562
MB		 196 struct nvme_dev *dev = data;
197 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
198 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
199
200 BUG_ON(!nvmeq);
201 cmd->nvmeq = nvmeq;
202 return 0;
203}
204
205static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
206 nvme_completion_fn handler)
207{
208 cmd->fn = handler;
209 cmd->ctx = ctx;
210 cmd->aborted = 0;
b60503ba
MW		 211}
212
c2f5b650
MW		 213/* Special values must be less than 0x1000 */
214#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 215#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
216#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
217#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 218
edd10d33 219static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 220 struct nvme_completion *cqe)
221{
222 if (ctx == CMD_CTX_CANCELLED)
223 return;
c2f5b650 224 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 225 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 226 "completed id %d twice on queue %d\n",
227 cqe->command_id, le16_to_cpup(&cqe->sq_id));
228 return;
229 }
230 if (ctx == CMD_CTX_INVALID) {
edd10d33 231 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 232 "invalid id %d completed on queue %d\n",
233 cqe->command_id, le16_to_cpup(&cqe->sq_id));
234 return;
235 }
edd10d33 236 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 237}
238
a4aea562 239static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 240{
c2f5b650 241 void *ctx;
b60503ba 242
859361a2 243 if (fn)
a4aea562
MB		 244 *fn = cmd->fn;
245 ctx = cmd->ctx;
246 cmd->fn = special_completion;
247 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 248 return ctx;
b60503ba
MW		 249}
250
a4aea562
MB		 251static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
252 struct nvme_completion *cqe)
3c0cf138 253{
a4aea562 254 struct request *req = ctx;
3c0cf138 255
a4aea562
MB		 256 u32 result = le32_to_cpup(&cqe->result);
257 u16 status = le16_to_cpup(&cqe->status) >> 1;
258
259 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
260 ++nvmeq->dev->event_limit;
261 if (status == NVME_SC_SUCCESS)
262 dev_warn(nvmeq->q_dmadev,
263 "async event result %08x\n", result);
264
9d135bb8 265 blk_mq_free_hctx_request(nvmeq->hctx, req);
b60503ba
MW		 266}
267
a4aea562
MB		 268static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
269 struct nvme_completion *cqe)
5a92e700 270{
a4aea562
MB		 271 struct request *req = ctx;
272
273 u16 status = le16_to_cpup(&cqe->status) >> 1;
274 u32 result = le32_to_cpup(&cqe->result);
a51afb54 275
9d135bb8 276 blk_mq_free_hctx_request(nvmeq->hctx, req);
a51afb54 277
a4aea562
MB		 278 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
279 ++nvmeq->dev->abort_limit;
5a92e700
KB		 280}
281
a4aea562
MB		 282static void async_completion(struct nvme_queue *nvmeq, void *ctx,
283 struct nvme_completion *cqe)
b60503ba 284{
a4aea562
MB		 285 struct async_cmd_info *cmdinfo = ctx;
286 cmdinfo->result = le32_to_cpup(&cqe->result);
287 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
288 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
9d135bb8 289 blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
b60503ba
MW		 290}
291
a4aea562
MB		 292static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
293 unsigned int tag)
b60503ba 294{
a4aea562
MB		 295 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
296 struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
a51afb54 297
a4aea562 298 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 299}
300
a4aea562
MB		 301/*
302 * Called with local interrupts disabled and the q_lock held. May not sleep.
303 */
304static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
305 nvme_completion_fn *fn)
4f5099af 306{
a4aea562
MB		 307 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
308 void *ctx;
309 if (tag >= nvmeq->q_depth) {
310 *fn = special_completion;
311 return CMD_CTX_INVALID;
312 }
313 if (fn)
314 *fn = cmd->fn;
315 ctx = cmd->ctx;
316 cmd->fn = special_completion;
317 cmd->ctx = CMD_CTX_COMPLETED;
318 return ctx;
b60503ba
MW		 319}
320
321/**
714a7a22 322 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 323 * @nvmeq: The queue to use
324 * @cmd: The command to send
325 *
326 * Safe to use from interrupt context
327 */
a4aea562 328static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 329{
a4aea562
MB		 330 u16 tail = nvmeq->sq_tail;
331
b60503ba 332 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 333 if (++tail == nvmeq->q_depth)
334 tail = 0;
7547881d 335 writel(tail, nvmeq->q_db);
b60503ba 336 nvmeq->sq_tail = tail;
b60503ba
MW		 337
338 return 0;
339}
340
a4aea562
MB		 341static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
342{
343 unsigned long flags;
344 int ret;
345 spin_lock_irqsave(&nvmeq->q_lock, flags);
346 ret = __nvme_submit_cmd(nvmeq, cmd);
347 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
348 return ret;
349}
350
eca18b23 351static __le64 **iod_list(struct nvme_iod *iod)
e025344c 352{
eca18b23 353 return ((void *)iod) + iod->offset;
e025344c
SMM		 354}
355
eca18b23
MW		 356/*
357 * Will slightly overestimate the number of pages needed. This is OK
358 * as it only leads to a small amount of wasted memory for the lifetime of
359 * the I/O.
360 */
1d090624 361static int nvme_npages(unsigned size, struct nvme_dev *dev)
eca18b23 362{
1d090624
KB		 363 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
364 return DIV_ROUND_UP(8 * nprps, dev->page_size - 8);
eca18b23 365}
b60503ba 366
eca18b23 367static struct nvme_iod *
1d090624 368nvme_alloc_iod(unsigned nseg, unsigned nbytes, struct nvme_dev *dev, gfp_t gfp)
b60503ba 369{
eca18b23 370 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
1d090624 371 sizeof(__le64 *) * nvme_npages(nbytes, dev) +
eca18b23
MW		 372 sizeof(struct scatterlist) * nseg, gfp);
373
374 if (iod) {
375 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
376 iod->npages = -1;
377 iod->length = nbytes;
2b196034 378 iod->nents = 0;
edd10d33 379 iod->first_dma = 0ULL;
eca18b23
MW		 380 }
381
382 return iod;
b60503ba
MW		 383}
384
5d0f6131 385void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 386{
1d090624 387 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 388 int i;
389 __le64 **list = iod_list(iod);
390 dma_addr_t prp_dma = iod->first_dma;
391
392 if (iod->npages == 0)
393 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
394 for (i = 0; i < iod->npages; i++) {
395 __le64 *prp_list = list[i];
396 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
397 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
398 prp_dma = next_prp_dma;
399 }
400 kfree(iod);
b60503ba
MW		 401}
402
b4ff9c8d
KB		 403static int nvme_error_status(u16 status)
404{
405 switch (status & 0x7ff) {
406 case NVME_SC_SUCCESS:
407 return 0;
408 case NVME_SC_CAP_EXCEEDED:
409 return -ENOSPC;
410 default:
411 return -EIO;
412 }
413}
414
a4aea562 415static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 416 struct nvme_completion *cqe)
417{
eca18b23 418 struct nvme_iod *iod = ctx;
a4aea562
MB		 419 struct request *req = iod->private;
420 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
421
b60503ba
MW		 422 u16 status = le16_to_cpup(&cqe->status) >> 1;
423
edd10d33 424 if (unlikely(status)) {
a4aea562
MB		 425 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
426 && (jiffies - req->start_time) < req->timeout) {
427 blk_mq_requeue_request(req);
428 blk_mq_kick_requeue_list(req->q);
edd10d33
KB		 429 return;
430 }
a4aea562
MB		 431 req->errors = nvme_error_status(status);
432 } else
433 req->errors = 0;
434
435 if (cmd_rq->aborted)
436 dev_warn(&nvmeq->dev->pci_dev->dev,
437 "completing aborted command with status:%04x\n",
438 status);
439
440 if (iod->nents)
441 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
442 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
edd10d33 443 nvme_free_iod(nvmeq->dev, iod);
3291fa57 444
a4aea562 445 blk_mq_complete_request(req);
b60503ba
MW		 446}
447
184d2944 448/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 449int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
450 gfp_t gfp)
ff22b54f 451{
99802a7a 452 struct dma_pool *pool;
eca18b23
MW		 453 int length = total_len;
454 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 455 int dma_len = sg_dma_len(sg);
456 u64 dma_addr = sg_dma_address(sg);
457 int offset = offset_in_page(dma_addr);
e025344c 458 __le64 *prp_list;
eca18b23 459 __le64 **list = iod_list(iod);
e025344c 460 dma_addr_t prp_dma;
eca18b23 461 int nprps, i;
1d090624 462 u32 page_size = dev->page_size;
ff22b54f 463
1d090624 464 length -= (page_size - offset);
ff22b54f 465 if (length <= 0)
eca18b23 466 return total_len;
ff22b54f 467
1d090624 468 dma_len -= (page_size - offset);
ff22b54f 469 if (dma_len) {
1d090624 470 dma_addr += (page_size - offset);
ff22b54f
MW		 471 } else {
472 sg = sg_next(sg);
473 dma_addr = sg_dma_address(sg);
474 dma_len = sg_dma_len(sg);
475 }
476
1d090624 477 if (length <= page_size) {
edd10d33 478 iod->first_dma = dma_addr;
eca18b23 479 return total_len;
e025344c
SMM		 480 }
481
1d090624 482 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 483 if (nprps <= (256 / 8)) {
484 pool = dev->prp_small_pool;
eca18b23 485 iod->npages = 0;
99802a7a
MW		 486 } else {
487 pool = dev->prp_page_pool;
eca18b23 488 iod->npages = 1;
99802a7a
MW		 489 }
490
b77954cb
MW		 491 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
492 if (!prp_list) {
edd10d33 493 iod->first_dma = dma_addr;
eca18b23 494 iod->npages = -1;
1d090624 495 return (total_len - length) + page_size;
b77954cb 496 }
eca18b23
MW		 497 list[0] = prp_list;
498 iod->first_dma = prp_dma;
e025344c
SMM		 499 i = 0;
500 for (;;) {
1d090624 501 if (i == page_size >> 3) {
e025344c 502 __le64 *old_prp_list = prp_list;
b77954cb 503 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 504 if (!prp_list)
505 return total_len - length;
506 list[iod->npages++] = prp_list;
7523d834
MW		 507 prp_list[0] = old_prp_list[i - 1];
508 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
509 i = 1;
e025344c
SMM		 510 }
511 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 512 dma_len -= page_size;
513 dma_addr += page_size;
514 length -= page_size;
e025344c
SMM		 515 if (length <= 0)
516 break;
517 if (dma_len > 0)
518 continue;
519 BUG_ON(dma_len < 0);
520 sg = sg_next(sg);
521 dma_addr = sg_dma_address(sg);
522 dma_len = sg_dma_len(sg);
ff22b54f
MW		 523 }
524
eca18b23 525 return total_len;
ff22b54f
MW		 526}
527
a4aea562
MB		 528/*
529 * We reuse the small pool to allocate the 16-byte range here as it is not
530 * worth having a special pool for these or additional cases to handle freeing
531 * the iod.
532 */
533static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
534 struct request *req, struct nvme_iod *iod)
0e5e4f0e 535{
edd10d33
KB		 536 struct nvme_dsm_range *range =
537 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 538 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
539
0e5e4f0e 540 range->cattr = cpu_to_le32(0);
a4aea562
MB		 541 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
542 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e
KB		 543
544 memset(cmnd, 0, sizeof(*cmnd));
545 cmnd->dsm.opcode = nvme_cmd_dsm;
a4aea562 546 cmnd->dsm.command_id = req->tag;
0e5e4f0e
KB		 547 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
548 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
549 cmnd->dsm.nr = 0;
550 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
551
552 if (++nvmeq->sq_tail == nvmeq->q_depth)
553 nvmeq->sq_tail = 0;
554 writel(nvmeq->sq_tail, nvmeq->q_db);
0e5e4f0e
KB		 555}
556
a4aea562 557static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 558 int cmdid)
559{
560 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
561
562 memset(cmnd, 0, sizeof(*cmnd));
563 cmnd->common.opcode = nvme_cmd_flush;
564 cmnd->common.command_id = cmdid;
565 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
566
567 if (++nvmeq->sq_tail == nvmeq->q_depth)
568 nvmeq->sq_tail = 0;
569 writel(nvmeq->sq_tail, nvmeq->q_db);
00df5cb4
MW		 570}
571
a4aea562
MB		 572static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
573 struct nvme_ns *ns)
b60503ba 574{
a4aea562 575 struct request *req = iod->private;
ff22b54f 576 struct nvme_command *cmnd;
a4aea562
MB		 577 u16 control = 0;
578 u32 dsmgmt = 0;
00df5cb4 579
a4aea562 580 if (req->cmd_flags & REQ_FUA)
b60503ba 581 control |= NVME_RW_FUA;
a4aea562 582 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 583 control |= NVME_RW_LR;
584
a4aea562 585 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 586 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
587
ff22b54f 588 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 589 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 590
a4aea562
MB		 591 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
592 cmnd->rw.command_id = req->tag;
ff22b54f 593 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 594 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
595 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
a4aea562
MB		 596 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
597 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
ff22b54f
MW		 598 cmnd->rw.control = cpu_to_le16(control);
599 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 600
b60503ba
MW		 601 if (++nvmeq->sq_tail == nvmeq->q_depth)
602 nvmeq->sq_tail = 0;
7547881d 603 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 604
1974b1ae 605 return 0;
edd10d33
KB		 606}
607
a4aea562
MB		 608static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
609 const struct blk_mq_queue_data *bd)
edd10d33 610{
a4aea562
MB		 611 struct nvme_ns *ns = hctx->queue->queuedata;
612 struct nvme_queue *nvmeq = hctx->driver_data;
613 struct request *req = bd->rq;
614 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 615 struct nvme_iod *iod;
a4aea562
MB		 616 int psegs = req->nr_phys_segments;
617 int result = BLK_MQ_RQ_QUEUE_BUSY;
618 enum dma_data_direction dma_dir;
619 unsigned size = !(req->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(req) :
9dbbfab7 620 sizeof(struct nvme_dsm_range);
edd10d33 621
a4aea562
MB		 622 /*
623 * Requeued IO has already been prepped
624 */
625 iod = req->special;
626 if (iod)
627 goto submit_iod;
edd10d33 628
9dbbfab7 629 iod = nvme_alloc_iod(psegs, size, ns->dev, GFP_ATOMIC);
edd10d33 630 if (!iod)
a4aea562
MB		 631 return result;
632
633 iod->private = req;
634 req->special = iod;
edd10d33 635
a4aea562
MB		 636 nvme_set_info(cmd, iod, req_completion);
637
638 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 639 void *range;
640 /*
641 * We reuse the small pool to allocate the 16-byte range here
642 * as it is not worth having a special pool for these or
643 * additional cases to handle freeing the iod.
644 */
645 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
646 GFP_ATOMIC,
647 &iod->first_dma);
a4aea562
MB		 648 if (!range)
649 goto finish_cmd;
edd10d33
KB		 650 iod_list(iod)[0] = (__le64 *)range;
651 iod->npages = 0;
652 } else if (psegs) {
a4aea562
MB		 653 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
654
655 sg_init_table(iod->sg, psegs);
656 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
657 if (!iod->nents) {
658 result = BLK_MQ_RQ_QUEUE_ERROR;
659 goto finish_cmd;
edd10d33 660 }
a4aea562
MB		 661
662 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
663 goto finish_cmd;
664
665 if (blk_rq_bytes(req) != nvme_setup_prps(nvmeq->dev, iod,
666 blk_rq_bytes(req), GFP_ATOMIC))
667 goto finish_cmd;
edd10d33 668 }
1974b1ae 669
a4aea562
MB		 670 blk_mq_start_request(req);
671
672 submit_iod:
673 spin_lock_irq(&nvmeq->q_lock);
674 if (req->cmd_flags & REQ_DISCARD)
675 nvme_submit_discard(nvmeq, ns, req, iod);
676 else if (req->cmd_flags & REQ_FLUSH)
677 nvme_submit_flush(nvmeq, ns, req->tag);
678 else
679 nvme_submit_iod(nvmeq, iod, ns);
680
681 nvme_process_cq(nvmeq);
682 spin_unlock_irq(&nvmeq->q_lock);
683 return BLK_MQ_RQ_QUEUE_OK;
684
685 finish_cmd:
686 nvme_finish_cmd(nvmeq, req->tag, NULL);
eca18b23 687 nvme_free_iod(nvmeq->dev, iod);
eeee3226 688 return result;
b60503ba
MW		 689}
690
e9539f47 691static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 692{
82123460 693 u16 head, phase;
b60503ba 694
b60503ba 695 head = nvmeq->cq_head;
82123460 696 phase = nvmeq->cq_phase;
b60503ba
MW		 697
698 for (;;) {
c2f5b650
MW		 699 void *ctx;
700 nvme_completion_fn fn;
b60503ba 701 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 702 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 703 break;
704 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
705 if (++head == nvmeq->q_depth) {
706 head = 0;
82123460 707 phase = !phase;
b60503ba 708 }
a4aea562 709 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 710 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 711 }
712
713 /* If the controller ignores the cq head doorbell and continuously
714 * writes to the queue, it is theoretically possible to wrap around
715 * the queue twice and mistakenly return IRQ_NONE. Linux only
716 * requires that 0.1% of your interrupts are handled, so this isn't
717 * a big problem.
718 */
82123460 719 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 720 return 0;
b60503ba 721
b80d5ccc 722 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 723 nvmeq->cq_head = head;
82123460 724 nvmeq->cq_phase = phase;
b60503ba 725
e9539f47
MW		 726 nvmeq->cqe_seen = 1;
727 return 1;
b60503ba
MW		 728}
729
a4aea562
MB		 730/* Admin queue isn't initialized as a request queue. If at some point this
731 * happens anyway, make sure to notify the user */
732static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
733 const struct blk_mq_queue_data *bd)
7d822457 734{
a4aea562
MB		 735 WARN_ON_ONCE(1);
736 return BLK_MQ_RQ_QUEUE_ERROR;
7d822457
MW		 737}
738
b60503ba 739static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 740{
741 irqreturn_t result;
742 struct nvme_queue *nvmeq = data;
743 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 744 nvme_process_cq(nvmeq);
745 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
746 nvmeq->cqe_seen = 0;
58ffacb5
MW		 747 spin_unlock(&nvmeq->q_lock);
748 return result;
749}
750
751static irqreturn_t nvme_irq_check(int irq, void *data)
752{
753 struct nvme_queue *nvmeq = data;
754 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
755 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
756 return IRQ_NONE;
757 return IRQ_WAKE_THREAD;
758}
759
a4aea562
MB		 760static void nvme_abort_cmd_info(struct nvme_queue *nvmeq, struct nvme_cmd_info *
761 cmd_info)
3c0cf138
MW		 762{
763 spin_lock_irq(&nvmeq->q_lock);
a4aea562 764 cancel_cmd_info(cmd_info, NULL);
3c0cf138
MW		 765 spin_unlock_irq(&nvmeq->q_lock);
766}
767
c2f5b650
MW		 768struct sync_cmd_info {
769 struct task_struct *task;
770 u32 result;
771 int status;
772};
773
edd10d33 774static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 775 struct nvme_completion *cqe)
776{
777 struct sync_cmd_info *cmdinfo = ctx;
778 cmdinfo->result = le32_to_cpup(&cqe->result);
779 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
780 wake_up_process(cmdinfo->task);
781}
782
b60503ba
MW		 783/*
784 * Returns 0 on success. If the result is negative, it's a Linux error code;
785 * if the result is positive, it's an NVM Express status code
786 */
a4aea562 787static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
5d0f6131 788 u32 *result, unsigned timeout)
b60503ba 789{
a4aea562 790 int ret;
b60503ba 791 struct sync_cmd_info cmdinfo;
a4aea562
MB		 792 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
793 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
b60503ba
MW		 794
795 cmdinfo.task = current;
796 cmdinfo.status = -EINTR;
797
a4aea562
MB		 798 cmd->common.command_id = req->tag;
799
800 nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
b60503ba 801
3c0cf138 802 set_current_state(TASK_KILLABLE);
4f5099af
KB		 803 ret = nvme_submit_cmd(nvmeq, cmd);
804 if (ret) {
a4aea562 805 nvme_finish_cmd(nvmeq, req->tag, NULL);
4f5099af 806 set_current_state(TASK_RUNNING);
4f5099af 807 }
78f8d257 808 schedule_timeout(timeout);
b60503ba 809
3c0cf138 810 if (cmdinfo.status == -EINTR) {
a4aea562 811 nvme_abort_cmd_info(nvmeq, blk_mq_rq_to_pdu(req));
3c0cf138
MW		 812 return -EINTR;
813 }
814
b60503ba
MW		 815 if (result)
816 *result = cmdinfo.result;
817
818 return cmdinfo.status;
819}
820
a4aea562
MB		 821static int nvme_submit_async_admin_req(struct nvme_dev *dev)
822{
823 struct nvme_queue *nvmeq = dev->queues[0];
824 struct nvme_command c;
825 struct nvme_cmd_info *cmd_info;
826 struct request *req;
827
6dcc0cf6 828 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false);
9f173b33
DC		 829 if (IS_ERR(req))
830 return PTR_ERR(req);
a4aea562
MB		 831
832 cmd_info = blk_mq_rq_to_pdu(req);
833 nvme_set_info(cmd_info, req, async_req_completion);
834
835 memset(&c, 0, sizeof(c));
836 c.common.opcode = nvme_admin_async_event;
837 c.common.command_id = req->tag;
838
839 return __nvme_submit_cmd(nvmeq, &c);
840}
841
842static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 843 struct nvme_command *cmd,
844 struct async_cmd_info *cmdinfo, unsigned timeout)
845{
a4aea562
MB		 846 struct nvme_queue *nvmeq = dev->queues[0];
847 struct request *req;
848 struct nvme_cmd_info *cmd_rq;
4d115420 849
a4aea562 850 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 851 if (IS_ERR(req))
852 return PTR_ERR(req);
a4aea562
MB		 853
854 req->timeout = timeout;
855 cmd_rq = blk_mq_rq_to_pdu(req);
856 cmdinfo->req = req;
857 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 858 cmdinfo->status = -EINTR;
a4aea562
MB		 859
860 cmd->common.command_id = req->tag;
861
4f5099af 862 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 863}
864
a64e6bb4 865static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
a4aea562 866 u32 *result, unsigned timeout)
b60503ba 867{
a4aea562
MB		 868 int res;
869 struct request *req;
870
871 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
872 if (!req)
873 return -ENOMEM;
874 res = nvme_submit_sync_cmd(req, cmd, result, timeout);
9d135bb8 875 blk_mq_free_request(req);
a4aea562 876 return res;
4f5099af
KB		 877}
878
a4aea562 879int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
4f5099af
KB		 880 u32 *result)
881{
a4aea562 882 return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 883}
884
a4aea562
MB		 885int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
886 struct nvme_command *cmd, u32 *result)
4d115420 887{
a4aea562
MB		 888 int res;
889 struct request *req;
890
891 req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
892 false);
893 if (!req)
894 return -ENOMEM;
895 res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
9d135bb8 896 blk_mq_free_request(req);
a4aea562 897 return res;
4d115420
KB		 898}
899
b60503ba
MW		 900static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
901{
b60503ba
MW		 902 struct nvme_command c;
903
904 memset(&c, 0, sizeof(c));
905 c.delete_queue.opcode = opcode;
906 c.delete_queue.qid = cpu_to_le16(id);
907
a4aea562 908 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 909}
910
911static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
912 struct nvme_queue *nvmeq)
913{
b60503ba
MW		 914 struct nvme_command c;
915 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
916
917 memset(&c, 0, sizeof(c));
918 c.create_cq.opcode = nvme_admin_create_cq;
919 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
920 c.create_cq.cqid = cpu_to_le16(qid);
921 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
922 c.create_cq.cq_flags = cpu_to_le16(flags);
923 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
924
a4aea562 925 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 926}
927
928static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
929 struct nvme_queue *nvmeq)
930{
b60503ba
MW		 931 struct nvme_command c;
932 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
933
934 memset(&c, 0, sizeof(c));
935 c.create_sq.opcode = nvme_admin_create_sq;
936 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
937 c.create_sq.sqid = cpu_to_le16(qid);
938 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
939 c.create_sq.sq_flags = cpu_to_le16(flags);
940 c.create_sq.cqid = cpu_to_le16(qid);
941
a4aea562 942 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 943}
944
945static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
946{
947 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
948}
949
950static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
951{
952 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
953}
954
5d0f6131 955int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 956 dma_addr_t dma_addr)
957{
958 struct nvme_command c;
959
960 memset(&c, 0, sizeof(c));
961 c.identify.opcode = nvme_admin_identify;
962 c.identify.nsid = cpu_to_le32(nsid);
963 c.identify.prp1 = cpu_to_le64(dma_addr);
964 c.identify.cns = cpu_to_le32(cns);
965
966 return nvme_submit_admin_cmd(dev, &c, NULL);
967}
968
5d0f6131 969int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 970 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 971{
972 struct nvme_command c;
973
974 memset(&c, 0, sizeof(c));
975 c.features.opcode = nvme_admin_get_features;
a42cecce 976 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 977 c.features.prp1 = cpu_to_le64(dma_addr);
978 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 979
08df1e05 980 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 981}
982
5d0f6131
VV		 983int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
984 dma_addr_t dma_addr, u32 *result)
df348139
MW		 985{
986 struct nvme_command c;
987
988 memset(&c, 0, sizeof(c));
989 c.features.opcode = nvme_admin_set_features;
990 c.features.prp1 = cpu_to_le64(dma_addr);
991 c.features.fid = cpu_to_le32(fid);
992 c.features.dword11 = cpu_to_le32(dword11);
993
bc5fc7e4
MW		 994 return nvme_submit_admin_cmd(dev, &c, result);
995}
996
c30341dc 997/**
a4aea562 998 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 999 *
1000 * Schedule controller reset if the command was already aborted once before and
1001 * still hasn't been returned to the driver, or if this is the admin queue.
1002 */
a4aea562 1003static void nvme_abort_req(struct request *req)
c30341dc 1004{
a4aea562
MB		 1005 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1006 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1007 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1008 struct request *abort_req;
1009 struct nvme_cmd_info *abort_cmd;
1010 struct nvme_command cmd;
c30341dc 1011
a4aea562 1012 if (!nvmeq->qid || cmd_rq->aborted) {
c30341dc
KB		 1013 if (work_busy(&dev->reset_work))
1014 return;
1015 list_del_init(&dev->node);
1016 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1017 "I/O %d QID %d timeout, reset controller\n",
1018 req->tag, nvmeq->qid);
9ca97374 1019 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc
KB		 1020 queue_work(nvme_workq, &dev->reset_work);
1021 return;
1022 }
1023
1024 if (!dev->abort_limit)
1025 return;
1026
a4aea562
MB		 1027 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1028 false);
9f173b33 1029 if (IS_ERR(abort_req))
c30341dc
KB		 1030 return;
1031
a4aea562
MB		 1032 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1033 nvme_set_info(abort_cmd, abort_req, abort_completion);
1034
c30341dc
KB		 1035 memset(&cmd, 0, sizeof(cmd));
1036 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1037 cmd.abort.cid = req->tag;
c30341dc 1038 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1039 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1040
1041 --dev->abort_limit;
a4aea562 1042 cmd_rq->aborted = 1;
c30341dc 1043
a4aea562 1044 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1045 nvmeq->qid);
a4aea562
MB		 1046 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1047 dev_warn(nvmeq->q_dmadev,
1048 "Could not abort I/O %d QID %d",
1049 req->tag, nvmeq->qid);
9d135bb8 1050 blk_mq_free_request(req);
a4aea562 1051 }
c30341dc
KB		 1052}
1053
a4aea562
MB		 1054static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1055 struct request *req, void *data, bool reserved)
a09115b2 1056{
a4aea562
MB		 1057 struct nvme_queue *nvmeq = data;
1058 void *ctx;
1059 nvme_completion_fn fn;
1060 struct nvme_cmd_info *cmd;
1061 static struct nvme_completion cqe = {
1062 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
1063 };
a09115b2 1064
a4aea562 1065 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1066
a4aea562
MB		 1067 if (cmd->ctx == CMD_CTX_CANCELLED)
1068 return;
1069
1070 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1071 req->tag, nvmeq->qid);
1072 ctx = cancel_cmd_info(cmd, &fn);
1073 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1074}
1075
a4aea562 1076static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1077{
a4aea562
MB		 1078 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1079 struct nvme_queue *nvmeq = cmd->nvmeq;
1080
1081 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1082 nvmeq->qid);
1083 if (nvmeq->dev->initialized)
1084 nvme_abort_req(req);
1085
1086 /*
1087 * The aborted req will be completed on receiving the abort req.
1088 * We enable the timer again. If hit twice, it'll cause a device reset,
1089 * as the device then is in a faulty state.
1090 */
1091 return BLK_EH_RESET_TIMER;
1092}
22404274 1093
a4aea562
MB		 1094static void nvme_free_queue(struct nvme_queue *nvmeq)
1095{
9e866774
MW		 1096 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1097 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1098 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1099 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1100 kfree(nvmeq);
1101}
1102
a1a5ef99 1103static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274 1104{
f435c282
KB		 1105 LLIST_HEAD(q_list);
1106 struct nvme_queue *nvmeq, *next;
1107 struct llist_node *entry;
22404274
KB		 1108 int i;
1109
a1a5ef99 1110 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1111 struct nvme_queue *nvmeq = dev->queues[i];
f435c282 1112 llist_add(&nvmeq->node, &q_list);
22404274 1113 dev->queue_count--;
a4aea562 1114 dev->queues[i] = NULL;
22404274 1115 }
f435c282
KB		 1116 synchronize_rcu();
1117 entry = llist_del_all(&q_list);
1118 llist_for_each_entry_safe(nvmeq, next, entry, node)
1119 nvme_free_queue(nvmeq);
22404274
KB		 1120}
1121
4d115420
KB		 1122/**
1123 * nvme_suspend_queue - put queue into suspended state
1124 * @nvmeq - queue to suspend
4d115420
KB		 1125 */
1126static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1127{
4d115420 1128 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1129
a09115b2 1130 spin_lock_irq(&nvmeq->q_lock);
42f61420 1131 nvmeq->dev->online_queues--;
a09115b2
MW		 1132 spin_unlock_irq(&nvmeq->q_lock);
1133
aba2080f
MW		 1134 irq_set_affinity_hint(vector, NULL);
1135 free_irq(vector, nvmeq);
b60503ba 1136
4d115420
KB		 1137 return 0;
1138}
b60503ba 1139
4d115420
KB		 1140static void nvme_clear_queue(struct nvme_queue *nvmeq)
1141{
a4aea562
MB		 1142 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1143
22404274
KB		 1144 spin_lock_irq(&nvmeq->q_lock);
1145 nvme_process_cq(nvmeq);
a4aea562
MB		 1146 if (hctx && hctx->tags)
1147 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
22404274 1148 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1149}
1150
4d115420
KB		 1151static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1152{
a4aea562 1153 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1154
1155 if (!nvmeq)
1156 return;
1157 if (nvme_suspend_queue(nvmeq))
1158 return;
1159
0e53d180
KB		 1160 /* Don't tell the adapter to delete the admin queue.
1161 * Don't tell a removed adapter to delete IO queues. */
1162 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1163 adapter_delete_sq(dev, qid);
1164 adapter_delete_cq(dev, qid);
1165 }
4d115420 1166 nvme_clear_queue(nvmeq);
b60503ba
MW		 1167}
1168
1169static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1170 int depth, int vector)
1171{
1172 struct device *dmadev = &dev->pci_dev->dev;
a4aea562 1173 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1174 if (!nvmeq)
1175 return NULL;
1176
4d51abf9
JP		 1177 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1178 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1179 if (!nvmeq->cqes)
1180 goto free_nvmeq;
b60503ba
MW		 1181
1182 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1183 &nvmeq->sq_dma_addr, GFP_KERNEL);
1184 if (!nvmeq->sq_cmds)
1185 goto free_cqdma;
1186
1187 nvmeq->q_dmadev = dmadev;
091b6092 1188 nvmeq->dev = dev;
3193f07b
MW		 1189 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1190 dev->instance, qid);
b60503ba
MW		 1191 spin_lock_init(&nvmeq->q_lock);
1192 nvmeq->cq_head = 0;
82123460 1193 nvmeq->cq_phase = 1;
b80d5ccc 1194 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW		 1195 nvmeq->q_depth = depth;
1196 nvmeq->cq_vector = vector;
c30341dc 1197 nvmeq->qid = qid;
22404274 1198 dev->queue_count++;
a4aea562 1199 dev->queues[qid] = nvmeq;
b60503ba
MW		 1200
1201 return nvmeq;
1202
1203 free_cqdma:
68b8eca5 1204 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1205 nvmeq->cq_dma_addr);
1206 free_nvmeq:
1207 kfree(nvmeq);
1208 return NULL;
1209}
1210
3001082c
MW		 1211static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1212 const char *name)
1213{
58ffacb5
MW		 1214 if (use_threaded_interrupts)
1215 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1216 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1217 name, nvmeq);
3001082c 1218 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1219 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1220}
1221
22404274 1222static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1223{
22404274 1224 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1225
7be50e93 1226 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1227 nvmeq->sq_tail = 0;
1228 nvmeq->cq_head = 0;
1229 nvmeq->cq_phase = 1;
b80d5ccc 1230 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1231 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1232 dev->online_queues++;
7be50e93 1233 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1234}
1235
1236static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1237{
1238 struct nvme_dev *dev = nvmeq->dev;
1239 int result;
3f85d50b 1240
b60503ba
MW		 1241 result = adapter_alloc_cq(dev, qid, nvmeq);
1242 if (result < 0)
22404274 1243 return result;
b60503ba
MW		 1244
1245 result = adapter_alloc_sq(dev, qid, nvmeq);
1246 if (result < 0)
1247 goto release_cq;
1248
3193f07b 1249 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1250 if (result < 0)
1251 goto release_sq;
1252
22404274 1253 nvme_init_queue(nvmeq, qid);
22404274 1254 return result;
b60503ba
MW		 1255
1256 release_sq:
1257 adapter_delete_sq(dev, qid);
1258 release_cq:
1259 adapter_delete_cq(dev, qid);
22404274 1260 return result;
b60503ba
MW		 1261}
1262
ba47e386
MW		 1263static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1264{
1265 unsigned long timeout;
1266 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1267
1268 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1269
1270 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1271 msleep(100);
1272 if (fatal_signal_pending(current))
1273 return -EINTR;
1274 if (time_after(jiffies, timeout)) {
1275 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1276 "Device not ready; aborting %s\n", enabled ?
1277 "initialisation" : "reset");
ba47e386
MW		 1278 return -ENODEV;
1279 }
1280 }
1281
1282 return 0;
1283}
1284
1285/*
1286 * If the device has been passed off to us in an enabled state, just clear
1287 * the enabled bit. The spec says we should set the 'shutdown notification
1288 * bits', but doing so may cause the device to complete commands to the
1289 * admin queue ... and we don't know what memory that might be pointing at!
1290 */
1291static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1292{
01079522
DM		 1293 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1294 dev->ctrl_config &= ~NVME_CC_ENABLE;
1295 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1296
ba47e386
MW		 1297 return nvme_wait_ready(dev, cap, false);
1298}
1299
1300static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1301{
01079522
DM		 1302 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1303 dev->ctrl_config |= NVME_CC_ENABLE;
1304 writel(dev->ctrl_config, &dev->bar->cc);
1305
ba47e386
MW		 1306 return nvme_wait_ready(dev, cap, true);
1307}
1308
1894d8f1
KB		 1309static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1310{
1311 unsigned long timeout;
1894d8f1 1312
01079522
DM		 1313 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1314 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1315
1316 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1317
2484f407 1318 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1319 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1320 NVME_CSTS_SHST_CMPLT) {
1321 msleep(100);
1322 if (fatal_signal_pending(current))
1323 return -EINTR;
1324 if (time_after(jiffies, timeout)) {
1325 dev_err(&dev->pci_dev->dev,
1326 "Device shutdown incomplete; abort shutdown\n");
1327 return -ENODEV;
1328 }
1329 }
1330
1331 return 0;
1332}
1333
a4aea562
MB		 1334static struct blk_mq_ops nvme_mq_admin_ops = {
1335 .queue_rq = nvme_admin_queue_rq,
1336 .map_queue = blk_mq_map_queue,
1337 .init_hctx = nvme_admin_init_hctx,
1338 .init_request = nvme_admin_init_request,
1339 .timeout = nvme_timeout,
1340};
1341
1342static struct blk_mq_ops nvme_mq_ops = {
1343 .queue_rq = nvme_queue_rq,
1344 .map_queue = blk_mq_map_queue,
1345 .init_hctx = nvme_init_hctx,
1346 .init_request = nvme_init_request,
1347 .timeout = nvme_timeout,
1348};
1349
1350static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1351{
1352 if (!dev->admin_q) {
1353 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1354 dev->admin_tagset.nr_hw_queues = 1;
1355 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1356 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1357 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
1358 dev->admin_tagset.cmd_size = sizeof(struct nvme_cmd_info);
1359 dev->admin_tagset.driver_data = dev;
1360
1361 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1362 return -ENOMEM;
1363
1364 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
1365 if (!dev->admin_q) {
1366 blk_mq_free_tag_set(&dev->admin_tagset);
1367 return -ENOMEM;
1368 }
1369 }
1370
1371 return 0;
1372}
1373
1374static void nvme_free_admin_tags(struct nvme_dev *dev)
1375{
1376 if (dev->admin_q)
1377 blk_mq_free_tag_set(&dev->admin_tagset);
1378}
1379
8d85fce7 1380static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1381{
ba47e386 1382 int result;
b60503ba 1383 u32 aqa;
ba47e386 1384 u64 cap = readq(&dev->bar->cap);
b60503ba 1385 struct nvme_queue *nvmeq;
1d090624
KB		 1386 unsigned page_shift = PAGE_SHIFT;
1387 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1388 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1389
1390 if (page_shift < dev_page_min) {
1391 dev_err(&dev->pci_dev->dev,
1392 "Minimum device page size (%u) too large for "
1393 "host (%u)\n", 1 << dev_page_min,
1394 1 << page_shift);
1395 return -ENODEV;
1396 }
1397 if (page_shift > dev_page_max) {
1398 dev_info(&dev->pci_dev->dev,
1399 "Device maximum page size (%u) smaller than "
1400 "host (%u); enabling work-around\n",
1401 1 << dev_page_max, 1 << page_shift);
1402 page_shift = dev_page_max;
1403 }
b60503ba 1404
ba47e386
MW		 1405 result = nvme_disable_ctrl(dev, cap);
1406 if (result < 0)
1407 return result;
b60503ba 1408
a4aea562 1409 nvmeq = dev->queues[0];
cd638946 1410 if (!nvmeq) {
a4aea562 1411 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, 0);
cd638946
KB		 1412 if (!nvmeq)
1413 return -ENOMEM;
cd638946 1414 }
b60503ba
MW		 1415
1416 aqa = nvmeq->q_depth - 1;
1417 aqa |= aqa << 16;
1418
1d090624
KB		 1419 dev->page_size = 1 << page_shift;
1420
01079522 1421 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1422 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1423 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1424 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1425
1426 writel(aqa, &dev->bar->aqa);
1427 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1428 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1429
ba47e386 1430 result = nvme_enable_ctrl(dev, cap);
025c557a 1431 if (result)
a4aea562
MB		 1432 goto free_nvmeq;
1433
1434 result = nvme_alloc_admin_tags(dev);
1435 if (result)
1436 goto free_nvmeq;
9e866774 1437
3193f07b 1438 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1439 if (result)
a4aea562 1440 goto free_tags;
025c557a 1441
b60503ba 1442 return result;
a4aea562
MB		 1443
1444 free_tags:
1445 nvme_free_admin_tags(dev);
1446 free_nvmeq:
1447 nvme_free_queues(dev, 0);
1448 return result;
b60503ba
MW		 1449}
1450
5d0f6131 1451struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1452 unsigned long addr, unsigned length)
b60503ba 1453{
36c14ed9 1454 int i, err, count, nents, offset;
7fc3cdab
MW		 1455 struct scatterlist *sg;
1456 struct page **pages;
eca18b23 1457 struct nvme_iod *iod;
36c14ed9
MW		 1458
1459 if (addr & 3)
eca18b23 1460 return ERR_PTR(-EINVAL);
5460fc03 1461 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1462 return ERR_PTR(-EINVAL);
7fc3cdab 1463
36c14ed9 1464 offset = offset_in_page(addr);
7fc3cdab
MW		 1465 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1466 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1467 if (!pages)
1468 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1469
1470 err = get_user_pages_fast(addr, count, 1, pages);
1471 if (err < count) {
1472 count = err;
1473 err = -EFAULT;
1474 goto put_pages;
1475 }
7fc3cdab 1476
6808c5fb 1477 err = -ENOMEM;
1d090624 1478 iod = nvme_alloc_iod(count, length, dev, GFP_KERNEL);
6808c5fb
S		 1479 if (!iod)
1480 goto put_pages;
1481
eca18b23 1482 sg = iod->sg;
36c14ed9 1483 sg_init_table(sg, count);
d0ba1e49
MW		 1484 for (i = 0; i < count; i++) {
1485 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1486 min_t(unsigned, length, PAGE_SIZE - offset),
1487 offset);
d0ba1e49
MW		 1488 length -= (PAGE_SIZE - offset);
1489 offset = 0;
7fc3cdab 1490 }
fe304c43 1491 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1492 iod->nents = count;
7fc3cdab 1493
7fc3cdab
MW		 1494 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1495 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1496 if (!nents)
eca18b23 1497 goto free_iod;
b60503ba 1498
7fc3cdab 1499 kfree(pages);
eca18b23 1500 return iod;
b60503ba 1501
eca18b23
MW		 1502 free_iod:
1503 kfree(iod);
7fc3cdab
MW		 1504 put_pages:
1505 for (i = 0; i < count; i++)
1506 put_page(pages[i]);
1507 kfree(pages);
eca18b23 1508 return ERR_PTR(err);
7fc3cdab 1509}
b60503ba 1510
5d0f6131 1511void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1512 struct nvme_iod *iod)
7fc3cdab 1513{
1c2ad9fa 1514 int i;
b60503ba 1515
1c2ad9fa
MW		 1516 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1517 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1518
1c2ad9fa
MW		 1519 for (i = 0; i < iod->nents; i++)
1520 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1521}
b60503ba 1522
a53295b6
MW		 1523static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1524{
1525 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1526 struct nvme_user_io io;
1527 struct nvme_command c;
f410c680
KB		 1528 unsigned length, meta_len;
1529 int status, i;
1530 struct nvme_iod *iod, *meta_iod = NULL;
1531 dma_addr_t meta_dma_addr;
1532 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1533
1534 if (copy_from_user(&io, uio, sizeof(io)))
1535 return -EFAULT;
6c7d4945 1536 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1537 meta_len = (io.nblocks + 1) * ns->ms;
1538
1539 if (meta_len && ((io.metadata & 3) || !io.metadata))
1540 return -EINVAL;
6c7d4945
MW		 1541
1542 switch (io.opcode) {
1543 case nvme_cmd_write:
1544 case nvme_cmd_read:
6bbf1acd 1545 case nvme_cmd_compare:
eca18b23 1546 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1547 break;
6c7d4945 1548 default:
6bbf1acd 1549 return -EINVAL;
6c7d4945
MW		 1550 }
1551
eca18b23
MW		 1552 if (IS_ERR(iod))
1553 return PTR_ERR(iod);
a53295b6
MW		 1554
1555 memset(&c, 0, sizeof(c));
1556 c.rw.opcode = io.opcode;
1557 c.rw.flags = io.flags;
6c7d4945 1558 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1559 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1560 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1561 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1562 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1563 c.rw.reftag = cpu_to_le32(io.reftag);
1564 c.rw.apptag = cpu_to_le16(io.apptag);
1565 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1566
1567 if (meta_len) {
1b56749e
KB		 1568 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1569 meta_len);
f410c680
KB		 1570 if (IS_ERR(meta_iod)) {
1571 status = PTR_ERR(meta_iod);
1572 meta_iod = NULL;
1573 goto unmap;
1574 }
1575
1576 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1577 &meta_dma_addr, GFP_KERNEL);
1578 if (!meta_mem) {
1579 status = -ENOMEM;
1580 goto unmap;
1581 }
1582
1583 if (io.opcode & 1) {
1584 int meta_offset = 0;
1585
1586 for (i = 0; i < meta_iod->nents; i++) {
1587 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1588 meta_iod->sg[i].offset;
1589 memcpy(meta_mem + meta_offset, meta,
1590 meta_iod->sg[i].length);
1591 kunmap_atomic(meta);
1592 meta_offset += meta_iod->sg[i].length;
1593 }
1594 }
1595
1596 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1597 }
1598
edd10d33
KB		 1599 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1600 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1601 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1602
b77954cb
MW		 1603 if (length != (io.nblocks + 1) << ns->lba_shift)
1604 status = -ENOMEM;
1605 else
a4aea562 1606 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
a53295b6 1607
f410c680
KB		 1608 if (meta_len) {
1609 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1610 int meta_offset = 0;
1611
1612 for (i = 0; i < meta_iod->nents; i++) {
1613 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1614 meta_iod->sg[i].offset;
1615 memcpy(meta, meta_mem + meta_offset,
1616 meta_iod->sg[i].length);
1617 kunmap_atomic(meta);
1618 meta_offset += meta_iod->sg[i].length;
1619 }
1620 }
1621
1622 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1623 meta_dma_addr);
1624 }
1625
1626 unmap:
1c2ad9fa 1627 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1628 nvme_free_iod(dev, iod);
f410c680
KB		 1629
1630 if (meta_iod) {
1631 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1632 nvme_free_iod(dev, meta_iod);
1633 }
1634
a53295b6
MW		 1635 return status;
1636}
1637
a4aea562
MB		 1638static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1639 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1640{
7963e521 1641 struct nvme_passthru_cmd cmd;
6ee44cdc 1642 struct nvme_command c;
eca18b23 1643 int status, length;
c7d36ab8 1644 struct nvme_iod *uninitialized_var(iod);
94f370ca 1645 unsigned timeout;
6ee44cdc 1646
6bbf1acd
MW		 1647 if (!capable(CAP_SYS_ADMIN))
1648 return -EACCES;
1649 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1650 return -EFAULT;
6ee44cdc
MW		 1651
1652 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1653 c.common.opcode = cmd.opcode;
1654 c.common.flags = cmd.flags;
1655 c.common.nsid = cpu_to_le32(cmd.nsid);
1656 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1657 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1658 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1659 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1660 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1661 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1662 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1663 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1664
1665 length = cmd.data_len;
1666 if (cmd.data_len) {
49742188
MW		 1667 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1668 length);
eca18b23
MW		 1669 if (IS_ERR(iod))
1670 return PTR_ERR(iod);
edd10d33
KB		 1671 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1672 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1673 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1674 }
1675
94f370ca
KB		 1676 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1677 ADMIN_TIMEOUT;
a4aea562 1678
6bbf1acd 1679 if (length != cmd.data_len)
b77954cb 1680 status = -ENOMEM;
a4aea562
MB		 1681 else if (ns) {
1682 struct request *req;
1683
1684 req = blk_mq_alloc_request(ns->queue, WRITE,
1685 (GFP_KERNEL|__GFP_WAIT), false);
1686 if (!req)
1687 status = -ENOMEM;
1688 else {
1689 status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1690 timeout);
9d135bb8 1691 blk_mq_free_request(req);
a4aea562
MB		 1692 }
1693 } else
1694 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
eca18b23 1695
6bbf1acd 1696 if (cmd.data_len) {
1c2ad9fa 1697 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1698 nvme_free_iod(dev, iod);
6bbf1acd 1699 }
f4f117f6 1700
cf90bc48 1701 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1702 sizeof(cmd.result)))
1703 status = -EFAULT;
1704
6ee44cdc
MW		 1705 return status;
1706}
1707
b60503ba
MW		 1708static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1709 unsigned long arg)
1710{
1711 struct nvme_ns *ns = bdev->bd_disk->private_data;
1712
1713 switch (cmd) {
6bbf1acd 1714 case NVME_IOCTL_ID:
c3bfe717 1715 force_successful_syscall_return();
6bbf1acd
MW		 1716 return ns->ns_id;
1717 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1718 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1719 case NVME_IOCTL_IO_CMD:
a4aea562 1720 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1721 case NVME_IOCTL_SUBMIT_IO:
1722 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1723 case SG_GET_VERSION_NUM:
1724 return nvme_sg_get_version_num((void __user *)arg);
1725 case SG_IO:
1726 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1727 default:
1728 return -ENOTTY;
1729 }
1730}
1731
320a3827
KB		 1732#ifdef CONFIG_COMPAT
1733static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1734 unsigned int cmd, unsigned long arg)
1735{
320a3827
KB		 1736 switch (cmd) {
1737 case SG_IO:
e179729a 1738 return -ENOIOCTLCMD;
320a3827
KB		 1739 }
1740 return nvme_ioctl(bdev, mode, cmd, arg);
1741}
1742#else
1743#define nvme_compat_ioctl NULL
1744#endif
1745
9ac27090
KB		 1746static int nvme_open(struct block_device *bdev, fmode_t mode)
1747{
9e60352c
KB		 1748 int ret = 0;
1749 struct nvme_ns *ns;
9ac27090 1750
9e60352c
KB		 1751 spin_lock(&dev_list_lock);
1752 ns = bdev->bd_disk->private_data;
1753 if (!ns)
1754 ret = -ENXIO;
1755 else if (!kref_get_unless_zero(&ns->dev->kref))
1756 ret = -ENXIO;
1757 spin_unlock(&dev_list_lock);
1758
1759 return ret;
9ac27090
KB		 1760}
1761
1762static void nvme_free_dev(struct kref *kref);
1763
1764static void nvme_release(struct gendisk *disk, fmode_t mode)
1765{
1766 struct nvme_ns *ns = disk->private_data;
1767 struct nvme_dev *dev = ns->dev;
1768
1769 kref_put(&dev->kref, nvme_free_dev);
1770}
1771
4cc09e2d
KB		 1772static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1773{
1774 /* some standard values */
1775 geo->heads = 1 << 6;
1776 geo->sectors = 1 << 5;
1777 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1778 return 0;
1779}
1780
1b9dbf7f
KB		 1781static int nvme_revalidate_disk(struct gendisk *disk)
1782{
1783 struct nvme_ns *ns = disk->private_data;
1784 struct nvme_dev *dev = ns->dev;
1785 struct nvme_id_ns *id;
1786 dma_addr_t dma_addr;
1787 int lbaf;
1788
1789 id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
1790 GFP_KERNEL);
1791 if (!id) {
1792 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
1793 __func__);
1794 return 0;
1795 }
1796
1797 if (nvme_identify(dev, ns->ns_id, 0, dma_addr))
1798 goto free;
1799
1800 lbaf = id->flbas & 0xf;
1801 ns->lba_shift = id->lbaf[lbaf].ds;
1802
1803 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1804 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1805 free:
1806 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1807 return 0;
1808}
1809
b60503ba
MW		 1810static const struct block_device_operations nvme_fops = {
1811 .owner = THIS_MODULE,
1812 .ioctl = nvme_ioctl,
320a3827 1813 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1814 .open = nvme_open,
1815 .release = nvme_release,
4cc09e2d 1816 .getgeo = nvme_getgeo,
1b9dbf7f 1817 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 1818};
1819
1fa6aead
MW		 1820static int nvme_kthread(void *data)
1821{
d4b4ff8e 1822 struct nvme_dev *dev, *next;
1fa6aead
MW		 1823
1824 while (!kthread_should_stop()) {
564a232c 1825 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1826 spin_lock(&dev_list_lock);
d4b4ff8e 1827 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1828 int i;
d4b4ff8e
KB		 1829 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1830 dev->initialized) {
1831 if (work_busy(&dev->reset_work))
1832 continue;
1833 list_del_init(&dev->node);
1834 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1835 "Failed status: %x, reset controller\n",
1836 readl(&dev->bar->csts));
9ca97374 1837 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 1838 queue_work(nvme_workq, &dev->reset_work);
1839 continue;
1840 }
1fa6aead 1841 for (i = 0; i < dev->queue_count; i++) {
a4aea562 1842 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 1843 if (!nvmeq)
1844 continue;
1fa6aead 1845 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 1846 nvme_process_cq(nvmeq);
6fccf938
KB		 1847
1848 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 1849 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 1850 break;
1851 dev->event_limit--;
1852 }
1fa6aead
MW		 1853 spin_unlock_irq(&nvmeq->q_lock);
1854 }
1855 }
1856 spin_unlock(&dev_list_lock);
acb7aa0d 1857 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1858 }
1859 return 0;
1860}
1861
0e5e4f0e
KB		 1862static void nvme_config_discard(struct nvme_ns *ns)
1863{
1864 u32 logical_block_size = queue_logical_block_size(ns->queue);
1865 ns->queue->limits.discard_zeroes_data = 0;
1866 ns->queue->limits.discard_alignment = logical_block_size;
1867 ns->queue->limits.discard_granularity = logical_block_size;
1868 ns->queue->limits.max_discard_sectors = 0xffffffff;
1869 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1870}
1871
c3bfe717 1872static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1873 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1874{
1875 struct nvme_ns *ns;
1876 struct gendisk *disk;
a4aea562 1877 int node = dev_to_node(&dev->pci_dev->dev);
b60503ba
MW		 1878 int lbaf;
1879
1880 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1881 return NULL;
1882
a4aea562 1883 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba
MW		 1884 if (!ns)
1885 return NULL;
a4aea562 1886 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 1887 if (IS_ERR(ns->queue))
b60503ba 1888 goto out_free_ns;
4eeb9215
MW		 1889 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1890 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 1891 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 1892 ns->dev = dev;
1893 ns->queue->queuedata = ns;
1894
a4aea562 1895 disk = alloc_disk_node(0, node);
b60503ba
MW		 1896 if (!disk)
1897 goto out_free_queue;
a4aea562 1898
5aff9382 1899 ns->ns_id = nsid;
b60503ba
MW		 1900 ns->disk = disk;
1901 lbaf = id->flbas & 0xf;
1902 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1903 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1904 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1905 if (dev->max_hw_sectors)
1906 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 1907 if (dev->stripe_size)
1908 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 1909 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
1910 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 1911
1912 disk->major = nvme_major;
469071a3 1913 disk->first_minor = 0;
b60503ba
MW		 1914 disk->fops = &nvme_fops;
1915 disk->private_data = ns;
1916 disk->queue = ns->queue;
388f037f 1917 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1918 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1919 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1920 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1921
0e5e4f0e
KB		 1922 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1923 nvme_config_discard(ns);
1924
b60503ba
MW		 1925 return ns;
1926
1927 out_free_queue:
1928 blk_cleanup_queue(ns->queue);
1929 out_free_ns:
1930 kfree(ns);
1931 return NULL;
1932}
1933
42f61420
KB		 1934static void nvme_create_io_queues(struct nvme_dev *dev)
1935{
a4aea562 1936 unsigned i;
42f61420 1937
a4aea562 1938 for (i = dev->queue_count; i <= dev->max_qid; i++)
42f61420
KB		 1939 if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1))
1940 break;
1941
a4aea562
MB		 1942 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
1943 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 1944 break;
1945}
1946
b3b06812 1947static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 1948{
1949 int status;
1950 u32 result;
b3b06812 1951 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 1952
df348139 1953 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 1954 &result);
27e8166c
MW		 1955 if (status < 0)
1956 return status;
1957 if (status > 0) {
1958 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
1959 status);
badc34d4 1960 return 0;
27e8166c 1961 }
b60503ba
MW		 1962 return min(result & 0xffff, result >> 16) + 1;
1963}
1964
9d713c2b
KB		 1965static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1966{
b80d5ccc 1967 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 1968}
1969
8d85fce7 1970static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1971{
a4aea562 1972 struct nvme_queue *adminq = dev->queues[0];
fa08a396 1973 struct pci_dev *pdev = dev->pci_dev;
42f61420 1974 int result, i, vecs, nr_io_queues, size;
b60503ba 1975
42f61420 1976 nr_io_queues = num_possible_cpus();
b348b7d5 1977 result = set_queue_count(dev, nr_io_queues);
badc34d4 1978 if (result <= 0)
1b23484b 1979 return result;
b348b7d5
MW		 1980 if (result < nr_io_queues)
1981 nr_io_queues = result;
b60503ba 1982
9d713c2b
KB		 1983 size = db_bar_size(dev, nr_io_queues);
1984 if (size > 8192) {
f1938f6e 1985 iounmap(dev->bar);
9d713c2b
KB		 1986 do {
1987 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1988 if (dev->bar)
1989 break;
1990 if (!--nr_io_queues)
1991 return -ENOMEM;
1992 size = db_bar_size(dev, nr_io_queues);
1993 } while (1);
f1938f6e 1994 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 1995 adminq->q_db = dev->dbs;
f1938f6e
MW		 1996 }
1997
9d713c2b 1998 /* Deregister the admin queue's interrupt */
3193f07b 1999 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2000
be577fab 2001 for (i = 0; i < nr_io_queues; i++)
1b23484b 2002 dev->entry[i].entry = i;
be577fab
AG		 2003 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2004 if (vecs < 0) {
2005 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2006 if (vecs < 0) {
2007 vecs = 1;
2008 } else {
2009 for (i = 0; i < vecs; i++)
2010 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2011 }
2012 }
2013
063a8096
MW		 2014 /*
2015 * Should investigate if there's a performance win from allocating
2016 * more queues than interrupt vectors; it might allow the submission
2017 * path to scale better, even if the receive path is limited by the
2018 * number of interrupts.
2019 */
2020 nr_io_queues = vecs;
42f61420 2021 dev->max_qid = nr_io_queues;
063a8096 2022
3193f07b 2023 result = queue_request_irq(dev, adminq, adminq->irqname);
a4aea562 2024 if (result)
22404274 2025 goto free_queues;
1b23484b 2026
cd638946 2027 /* Free previously allocated queues that are no longer usable */
42f61420 2028 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2029 nvme_create_io_queues(dev);
9ecdc946 2030
22404274 2031 return 0;
b60503ba 2032
22404274 2033 free_queues:
a1a5ef99 2034 nvme_free_queues(dev, 1);
22404274 2035 return result;
b60503ba
MW		 2036}
2037
422ef0c7
MW		 2038/*
2039 * Return: error value if an error occurred setting up the queues or calling
2040 * Identify Device. 0 if these succeeded, even if adding some of the
2041 * namespaces failed. At the moment, these failures are silent. TBD which
2042 * failures should be reported.
2043 */
8d85fce7 2044static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2045{
68608c26 2046 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2047 int res;
2048 unsigned nn, i;
cbb6218f 2049 struct nvme_ns *ns;
51814232 2050 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2051 struct nvme_id_ns *id_ns;
2052 void *mem;
b60503ba 2053 dma_addr_t dma_addr;
159b67d7 2054 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2055
68608c26 2056 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2057 if (!mem)
2058 return -ENOMEM;
b60503ba 2059
bc5fc7e4 2060 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2061 if (res) {
27e8166c 2062 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
b60503ba 2063 res = -EIO;
cbb6218f 2064 goto out;
b60503ba
MW		 2065 }
2066
bc5fc7e4 2067 ctrl = mem;
51814232 2068 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2069 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2070 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2071 dev->vwc = ctrl->vwc;
6fccf938 2072 dev->event_limit = min(ctrl->aerl + 1, 8);
51814232
MW		 2073 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2074 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2075 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2076 if (ctrl->mdts)
8fc23e03 2077 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2078 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2079 (pdev->device == 0x0953) && ctrl->vs[3]) {
2080 unsigned int max_hw_sectors;
2081
159b67d7 2082 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2083 max_hw_sectors = dev->stripe_size >> (shift - 9);
2084 if (dev->max_hw_sectors) {
2085 dev->max_hw_sectors = min(max_hw_sectors,
2086 dev->max_hw_sectors);
2087 } else
2088 dev->max_hw_sectors = max_hw_sectors;
2089 }
2090
2091 dev->tagset.ops = &nvme_mq_ops;
2092 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2093 dev->tagset.timeout = NVME_IO_TIMEOUT;
2094 dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2095 dev->tagset.queue_depth =
2096 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2097 dev->tagset.cmd_size = sizeof(struct nvme_cmd_info);
2098 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2099 dev->tagset.driver_data = dev;
2100
2101 if (blk_mq_alloc_tag_set(&dev->tagset))
2102 goto out;
b60503ba 2103
bc5fc7e4 2104 id_ns = mem;
2b2c1896 2105 for (i = 1; i <= nn; i++) {
bc5fc7e4 2106 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2107 if (res)
2108 continue;
2109
bc5fc7e4 2110 if (id_ns->ncap == 0)
b60503ba
MW		 2111 continue;
2112
bc5fc7e4 2113 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2114 dma_addr + 4096, NULL);
b60503ba 2115 if (res)
12209036 2116 memset(mem + 4096, 0, 4096);
b60503ba 2117
bc5fc7e4 2118 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2119 if (ns)
2120 list_add_tail(&ns->list, &dev->namespaces);
2121 }
2122 list_for_each_entry(ns, &dev->namespaces, list)
2123 add_disk(ns->disk);
422ef0c7 2124 res = 0;
b60503ba 2125
bc5fc7e4 2126 out:
684f5c20 2127 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2128 return res;
2129}
2130
0877cb0d
KB		 2131static int nvme_dev_map(struct nvme_dev *dev)
2132{
42f61420 2133 u64 cap;
0877cb0d
KB		 2134 int bars, result = -ENOMEM;
2135 struct pci_dev *pdev = dev->pci_dev;
2136
2137 if (pci_enable_device_mem(pdev))
2138 return result;
2139
2140 dev->entry[0].vector = pdev->irq;
2141 pci_set_master(pdev);
2142 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2143 if (pci_request_selected_regions(pdev, bars, "nvme"))
2144 goto disable_pci;
2145
052d0efa
RK		 2146 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2147 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2148 goto disable;
0877cb0d 2149
0877cb0d
KB		 2150 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2151 if (!dev->bar)
2152 goto disable;
0e53d180
KB		 2153 if (readl(&dev->bar->csts) == -1) {
2154 result = -ENODEV;
2155 goto unmap;
2156 }
42f61420
KB		 2157 cap = readq(&dev->bar->cap);
2158 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2159 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2160 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2161
2162 return 0;
2163
0e53d180
KB		 2164 unmap:
2165 iounmap(dev->bar);
2166 dev->bar = NULL;
0877cb0d
KB		 2167 disable:
2168 pci_release_regions(pdev);
2169 disable_pci:
2170 pci_disable_device(pdev);
2171 return result;
2172}
2173
2174static void nvme_dev_unmap(struct nvme_dev *dev)
2175{
2176 if (dev->pci_dev->msi_enabled)
2177 pci_disable_msi(dev->pci_dev);
2178 else if (dev->pci_dev->msix_enabled)
2179 pci_disable_msix(dev->pci_dev);
2180
2181 if (dev->bar) {
2182 iounmap(dev->bar);
2183 dev->bar = NULL;
9a6b9458 2184 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2185 }
2186
0877cb0d
KB		 2187 if (pci_is_enabled(dev->pci_dev))
2188 pci_disable_device(dev->pci_dev);
2189}
2190
4d115420
KB		 2191struct nvme_delq_ctx {
2192 struct task_struct *waiter;
2193 struct kthread_worker *worker;
2194 atomic_t refcount;
2195};
2196
2197static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2198{
2199 dq->waiter = current;
2200 mb();
2201
2202 for (;;) {
2203 set_current_state(TASK_KILLABLE);
2204 if (!atomic_read(&dq->refcount))
2205 break;
2206 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2207 fatal_signal_pending(current)) {
2208 set_current_state(TASK_RUNNING);
2209
2210 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2211 nvme_disable_queue(dev, 0);
2212
2213 send_sig(SIGKILL, dq->worker->task, 1);
2214 flush_kthread_worker(dq->worker);
2215 return;
2216 }
2217 }
2218 set_current_state(TASK_RUNNING);
2219}
2220
2221static void nvme_put_dq(struct nvme_delq_ctx *dq)
2222{
2223 atomic_dec(&dq->refcount);
2224 if (dq->waiter)
2225 wake_up_process(dq->waiter);
2226}
2227
2228static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2229{
2230 atomic_inc(&dq->refcount);
2231 return dq;
2232}
2233
2234static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2235{
2236 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2237
2238 nvme_clear_queue(nvmeq);
2239 nvme_put_dq(dq);
2240}
2241
2242static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2243 kthread_work_func_t fn)
2244{
2245 struct nvme_command c;
2246
2247 memset(&c, 0, sizeof(c));
2248 c.delete_queue.opcode = opcode;
2249 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2250
2251 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2252 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2253 ADMIN_TIMEOUT);
4d115420
KB		 2254}
2255
2256static void nvme_del_cq_work_handler(struct kthread_work *work)
2257{
2258 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2259 cmdinfo.work);
2260 nvme_del_queue_end(nvmeq);
2261}
2262
2263static int nvme_delete_cq(struct nvme_queue *nvmeq)
2264{
2265 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2266 nvme_del_cq_work_handler);
2267}
2268
2269static void nvme_del_sq_work_handler(struct kthread_work *work)
2270{
2271 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2272 cmdinfo.work);
2273 int status = nvmeq->cmdinfo.status;
2274
2275 if (!status)
2276 status = nvme_delete_cq(nvmeq);
2277 if (status)
2278 nvme_del_queue_end(nvmeq);
2279}
2280
2281static int nvme_delete_sq(struct nvme_queue *nvmeq)
2282{
2283 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2284 nvme_del_sq_work_handler);
2285}
2286
2287static void nvme_del_queue_start(struct kthread_work *work)
2288{
2289 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2290 cmdinfo.work);
2291 allow_signal(SIGKILL);
2292 if (nvme_delete_sq(nvmeq))
2293 nvme_del_queue_end(nvmeq);
2294}
2295
2296static void nvme_disable_io_queues(struct nvme_dev *dev)
2297{
2298 int i;
2299 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2300 struct nvme_delq_ctx dq;
2301 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2302 &worker, "nvme%d", dev->instance);
2303
2304 if (IS_ERR(kworker_task)) {
2305 dev_err(&dev->pci_dev->dev,
2306 "Failed to create queue del task\n");
2307 for (i = dev->queue_count - 1; i > 0; i--)
2308 nvme_disable_queue(dev, i);
2309 return;
2310 }
2311
2312 dq.waiter = NULL;
2313 atomic_set(&dq.refcount, 0);
2314 dq.worker = &worker;
2315 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2316 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2317
2318 if (nvme_suspend_queue(nvmeq))
2319 continue;
2320 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2321 nvmeq->cmdinfo.worker = dq.worker;
2322 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2323 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2324 }
2325 nvme_wait_dq(&dq, dev);
2326 kthread_stop(kworker_task);
2327}
2328
b9afca3e
DM		 2329/*
2330* Remove the node from the device list and check
2331* for whether or not we need to stop the nvme_thread.
2332*/
2333static void nvme_dev_list_remove(struct nvme_dev *dev)
2334{
2335 struct task_struct *tmp = NULL;
2336
2337 spin_lock(&dev_list_lock);
2338 list_del_init(&dev->node);
2339 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2340 tmp = nvme_thread;
2341 nvme_thread = NULL;
2342 }
2343 spin_unlock(&dev_list_lock);
2344
2345 if (tmp)
2346 kthread_stop(tmp);
2347}
2348
f0b50732 2349static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2350{
22404274 2351 int i;
7c1b2450 2352 u32 csts = -1;
22404274 2353
d4b4ff8e 2354 dev->initialized = 0;
b9afca3e 2355 nvme_dev_list_remove(dev);
1fa6aead 2356
7c1b2450
KB		 2357 if (dev->bar)
2358 csts = readl(&dev->bar->csts);
2359 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2360 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2361 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2362 nvme_suspend_queue(nvmeq);
2363 nvme_clear_queue(nvmeq);
2364 }
2365 } else {
2366 nvme_disable_io_queues(dev);
1894d8f1 2367 nvme_shutdown_ctrl(dev);
4d115420
KB		 2368 nvme_disable_queue(dev, 0);
2369 }
f0b50732
KB		 2370 nvme_dev_unmap(dev);
2371}
2372
a4aea562
MB		 2373static void nvme_dev_remove_admin(struct nvme_dev *dev)
2374{
2375 if (dev->admin_q && !blk_queue_dying(dev->admin_q))
2376 blk_cleanup_queue(dev->admin_q);
2377}
2378
f0b50732
KB		 2379static void nvme_dev_remove(struct nvme_dev *dev)
2380{
9ac27090 2381 struct nvme_ns *ns;
f0b50732 2382
9ac27090
KB		 2383 list_for_each_entry(ns, &dev->namespaces, list) {
2384 if (ns->disk->flags & GENHD_FL_UP)
2385 del_gendisk(ns->disk);
2386 if (!blk_queue_dying(ns->queue))
2387 blk_cleanup_queue(ns->queue);
b60503ba 2388 }
b60503ba
MW		 2389}
2390
091b6092
MW		 2391static int nvme_setup_prp_pools(struct nvme_dev *dev)
2392{
2393 struct device *dmadev = &dev->pci_dev->dev;
2394 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2395 PAGE_SIZE, PAGE_SIZE, 0);
2396 if (!dev->prp_page_pool)
2397 return -ENOMEM;
2398
99802a7a
MW		 2399 /* Optimisation for I/Os between 4k and 128k */
2400 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2401 256, 256, 0);
2402 if (!dev->prp_small_pool) {
2403 dma_pool_destroy(dev->prp_page_pool);
2404 return -ENOMEM;
2405 }
091b6092
MW		 2406 return 0;
2407}
2408
2409static void nvme_release_prp_pools(struct nvme_dev *dev)
2410{
2411 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2412 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2413}
2414
cd58ad7d
QSA		 2415static DEFINE_IDA(nvme_instance_ida);
2416
2417static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2418{
cd58ad7d
QSA		 2419 int instance, error;
2420
2421 do {
2422 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2423 return -ENODEV;
2424
2425 spin_lock(&dev_list_lock);
2426 error = ida_get_new(&nvme_instance_ida, &instance);
2427 spin_unlock(&dev_list_lock);
2428 } while (error == -EAGAIN);
2429
2430 if (error)
2431 return -ENODEV;
2432
2433 dev->instance = instance;
2434 return 0;
b60503ba
MW		 2435}
2436
2437static void nvme_release_instance(struct nvme_dev *dev)
2438{
cd58ad7d
QSA		 2439 spin_lock(&dev_list_lock);
2440 ida_remove(&nvme_instance_ida, dev->instance);
2441 spin_unlock(&dev_list_lock);
b60503ba
MW		 2442}
2443
9ac27090
KB		 2444static void nvme_free_namespaces(struct nvme_dev *dev)
2445{
2446 struct nvme_ns *ns, *next;
2447
2448 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2449 list_del(&ns->list);
9e60352c
KB		 2450
2451 spin_lock(&dev_list_lock);
2452 ns->disk->private_data = NULL;
2453 spin_unlock(&dev_list_lock);
2454
9ac27090
KB		 2455 put_disk(ns->disk);
2456 kfree(ns);
2457 }
2458}
2459
5e82e952
KB		 2460static void nvme_free_dev(struct kref *kref)
2461{
2462 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2463
a96d4f5c 2464 pci_dev_put(dev->pci_dev);
9ac27090 2465 nvme_free_namespaces(dev);
a4aea562 2466 blk_mq_free_tag_set(&dev->tagset);
5e82e952
KB		 2467 kfree(dev->queues);
2468 kfree(dev->entry);
2469 kfree(dev);
2470}
2471
2472static int nvme_dev_open(struct inode *inode, struct file *f)
2473{
2474 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2475 miscdev);
2476 kref_get(&dev->kref);
2477 f->private_data = dev;
2478 return 0;
2479}
2480
2481static int nvme_dev_release(struct inode *inode, struct file *f)
2482{
2483 struct nvme_dev *dev = f->private_data;
2484 kref_put(&dev->kref, nvme_free_dev);
2485 return 0;
2486}
2487
2488static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2489{
2490 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2491 struct nvme_ns *ns;
2492
5e82e952
KB		 2493 switch (cmd) {
2494 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2495 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2496 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2497 if (list_empty(&dev->namespaces))
2498 return -ENOTTY;
2499 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2500 return nvme_user_cmd(dev, ns, (void __user *)arg);
5e82e952
KB		 2501 default:
2502 return -ENOTTY;
2503 }
2504}
2505
2506static const struct file_operations nvme_dev_fops = {
2507 .owner = THIS_MODULE,
2508 .open = nvme_dev_open,
2509 .release = nvme_dev_release,
2510 .unlocked_ioctl = nvme_dev_ioctl,
2511 .compat_ioctl = nvme_dev_ioctl,
2512};
2513
a4aea562
MB		 2514static void nvme_set_irq_hints(struct nvme_dev *dev)
2515{
2516 struct nvme_queue *nvmeq;
2517 int i;
2518
2519 for (i = 0; i < dev->online_queues; i++) {
2520 nvmeq = dev->queues[i];
2521
2522 if (!nvmeq->hctx)
2523 continue;
2524
2525 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2526 nvmeq->hctx->cpumask);
2527 }
2528}
2529
f0b50732
KB		 2530static int nvme_dev_start(struct nvme_dev *dev)
2531{
2532 int result;
b9afca3e 2533 bool start_thread = false;
f0b50732
KB		 2534
2535 result = nvme_dev_map(dev);
2536 if (result)
2537 return result;
2538
2539 result = nvme_configure_admin_queue(dev);
2540 if (result)
2541 goto unmap;
2542
2543 spin_lock(&dev_list_lock);
b9afca3e
DM		 2544 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2545 start_thread = true;
2546 nvme_thread = NULL;
2547 }
f0b50732
KB		 2548 list_add(&dev->node, &dev_list);
2549 spin_unlock(&dev_list_lock);
2550
b9afca3e
DM		 2551 if (start_thread) {
2552 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2553 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2554 } else
2555 wait_event_killable(nvme_kthread_wait, nvme_thread);
2556
2557 if (IS_ERR_OR_NULL(nvme_thread)) {
2558 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2559 goto disable;
2560 }
a4aea562
MB		 2561
2562 nvme_init_queue(dev->queues[0], 0);
b9afca3e 2563
f0b50732 2564 result = nvme_setup_io_queues(dev);
badc34d4 2565 if (result)
f0b50732
KB		 2566 goto disable;
2567
a4aea562
MB		 2568 nvme_set_irq_hints(dev);
2569
d82e8bfd 2570 return result;
f0b50732
KB		 2571
2572 disable:
a1a5ef99 2573 nvme_disable_queue(dev, 0);
b9afca3e 2574 nvme_dev_list_remove(dev);
f0b50732
KB		 2575 unmap:
2576 nvme_dev_unmap(dev);
2577 return result;
2578}
2579
9a6b9458
KB		 2580static int nvme_remove_dead_ctrl(void *arg)
2581{
2582 struct nvme_dev *dev = (struct nvme_dev *)arg;
2583 struct pci_dev *pdev = dev->pci_dev;
2584
2585 if (pci_get_drvdata(pdev))
c81f4975 2586 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2587 kref_put(&dev->kref, nvme_free_dev);
2588 return 0;
2589}
2590
2591static void nvme_remove_disks(struct work_struct *ws)
2592{
9a6b9458
KB		 2593 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2594
5a92e700 2595 nvme_free_queues(dev, 1);
302c6727 2596 nvme_dev_remove(dev);
9a6b9458
KB		 2597}
2598
2599static int nvme_dev_resume(struct nvme_dev *dev)
2600{
2601 int ret;
2602
2603 ret = nvme_dev_start(dev);
badc34d4 2604 if (ret)
9a6b9458 2605 return ret;
badc34d4 2606 if (dev->online_queues < 2) {
9a6b9458 2607 spin_lock(&dev_list_lock);
9ca97374 2608 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2609 queue_work(nvme_workq, &dev->reset_work);
2610 spin_unlock(&dev_list_lock);
2611 }
d4b4ff8e 2612 dev->initialized = 1;
9a6b9458
KB		 2613 return 0;
2614}
2615
2616static void nvme_dev_reset(struct nvme_dev *dev)
2617{
2618 nvme_dev_shutdown(dev);
2619 if (nvme_dev_resume(dev)) {
a4aea562 2620 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
9a6b9458
KB		 2621 kref_get(&dev->kref);
2622 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2623 dev->instance))) {
2624 dev_err(&dev->pci_dev->dev,
2625 "Failed to start controller remove task\n");
2626 kref_put(&dev->kref, nvme_free_dev);
2627 }
2628 }
2629}
2630
2631static void nvme_reset_failed_dev(struct work_struct *ws)
2632{
2633 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2634 nvme_dev_reset(dev);
2635}
2636
9ca97374
TH		 2637static void nvme_reset_workfn(struct work_struct *work)
2638{
2639 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2640 dev->reset_workfn(work);
2641}
2642
8d85fce7 2643static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2644{
a4aea562 2645 int node, result = -ENOMEM;
b60503ba
MW		 2646 struct nvme_dev *dev;
2647
a4aea562
MB		 2648 node = dev_to_node(&pdev->dev);
2649 if (node == NUMA_NO_NODE)
2650 set_dev_node(&pdev->dev, 0);
2651
2652 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2653 if (!dev)
2654 return -ENOMEM;
a4aea562
MB		 2655 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2656 GFP_KERNEL, node);
b60503ba
MW		 2657 if (!dev->entry)
2658 goto free;
a4aea562
MB		 2659 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2660 GFP_KERNEL, node);
b60503ba
MW		 2661 if (!dev->queues)
2662 goto free;
2663
2664 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2665 dev->reset_workfn = nvme_reset_failed_dev;
2666 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
a96d4f5c 2667 dev->pci_dev = pci_dev_get(pdev);
9a6b9458 2668 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2669 result = nvme_set_instance(dev);
2670 if (result)
a96d4f5c 2671 goto put_pci;
b60503ba 2672
091b6092
MW		 2673 result = nvme_setup_prp_pools(dev);
2674 if (result)
0877cb0d 2675 goto release;
091b6092 2676
fb35e914 2677 kref_init(&dev->kref);
f0b50732 2678 result = nvme_dev_start(dev);
badc34d4 2679 if (result)
0877cb0d 2680 goto release_pools;
b60503ba 2681
badc34d4
KB		 2682 if (dev->online_queues > 1)
2683 result = nvme_dev_add(dev);
d82e8bfd 2684 if (result)
f0b50732 2685 goto shutdown;
740216fc 2686
5e82e952
KB		 2687 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2688 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2689 dev->miscdev.parent = &pdev->dev;
2690 dev->miscdev.name = dev->name;
2691 dev->miscdev.fops = &nvme_dev_fops;
2692 result = misc_register(&dev->miscdev);
2693 if (result)
2694 goto remove;
2695
a4aea562
MB		 2696 nvme_set_irq_hints(dev);
2697
d4b4ff8e 2698 dev->initialized = 1;
b60503ba
MW		 2699 return 0;
2700
5e82e952
KB		 2701 remove:
2702 nvme_dev_remove(dev);
a4aea562 2703 nvme_dev_remove_admin(dev);
9ac27090 2704 nvme_free_namespaces(dev);
f0b50732
KB		 2705 shutdown:
2706 nvme_dev_shutdown(dev);
0877cb0d 2707 release_pools:
a1a5ef99 2708 nvme_free_queues(dev, 0);
091b6092 2709 nvme_release_prp_pools(dev);
0877cb0d
KB		 2710 release:
2711 nvme_release_instance(dev);
a96d4f5c
KB		 2712 put_pci:
2713 pci_dev_put(dev->pci_dev);
b60503ba
MW		 2714 free:
2715 kfree(dev->queues);
2716 kfree(dev->entry);
2717 kfree(dev);
2718 return result;
2719}
2720
f0d54a54
KB		 2721static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2722{
a6739479 2723 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 2724
a6739479
KB		 2725 if (prepare)
2726 nvme_dev_shutdown(dev);
2727 else
2728 nvme_dev_resume(dev);
f0d54a54
KB		 2729}
2730
09ece142
KB		 2731static void nvme_shutdown(struct pci_dev *pdev)
2732{
2733 struct nvme_dev *dev = pci_get_drvdata(pdev);
2734 nvme_dev_shutdown(dev);
2735}
2736
8d85fce7 2737static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2738{
2739 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2740
2741 spin_lock(&dev_list_lock);
2742 list_del_init(&dev->node);
2743 spin_unlock(&dev_list_lock);
2744
2745 pci_set_drvdata(pdev, NULL);
2746 flush_work(&dev->reset_work);
5e82e952 2747 misc_deregister(&dev->miscdev);
a4aea562 2748 nvme_dev_remove(dev);
9a6b9458 2749 nvme_dev_shutdown(dev);
a4aea562 2750 nvme_dev_remove_admin(dev);
a1a5ef99 2751 nvme_free_queues(dev, 0);
a4aea562 2752 nvme_free_admin_tags(dev);
9a6b9458
KB		 2753 nvme_release_instance(dev);
2754 nvme_release_prp_pools(dev);
5e82e952 2755 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2756}
2757
2758/* These functions are yet to be implemented */
2759#define nvme_error_detected NULL
2760#define nvme_dump_registers NULL
2761#define nvme_link_reset NULL
2762#define nvme_slot_reset NULL
2763#define nvme_error_resume NULL
cd638946 2764
671a6018 2765#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2766static int nvme_suspend(struct device *dev)
2767{
2768 struct pci_dev *pdev = to_pci_dev(dev);
2769 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2770
2771 nvme_dev_shutdown(ndev);
2772 return 0;
2773}
2774
2775static int nvme_resume(struct device *dev)
2776{
2777 struct pci_dev *pdev = to_pci_dev(dev);
2778 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2779
9a6b9458 2780 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2781 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 2782 queue_work(nvme_workq, &ndev->reset_work);
2783 }
2784 return 0;
cd638946 2785}
671a6018 2786#endif
cd638946
KB		 2787
2788static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2789
1d352035 2790static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2791 .error_detected = nvme_error_detected,
2792 .mmio_enabled = nvme_dump_registers,
2793 .link_reset = nvme_link_reset,
2794 .slot_reset = nvme_slot_reset,
2795 .resume = nvme_error_resume,
f0d54a54 2796 .reset_notify = nvme_reset_notify,
b60503ba
MW		 2797};
2798
2799/* Move to pci_ids.h later */
2800#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2801
6eb0d698 2802static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2803 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2804 { 0, }
2805};
2806MODULE_DEVICE_TABLE(pci, nvme_id_table);
2807
2808static struct pci_driver nvme_driver = {
2809 .name = "nvme",
2810 .id_table = nvme_id_table,
2811 .probe = nvme_probe,
8d85fce7 2812 .remove = nvme_remove,
09ece142 2813 .shutdown = nvme_shutdown,
cd638946
KB		 2814 .driver = {
2815 .pm = &nvme_dev_pm_ops,
2816 },
b60503ba
MW		 2817 .err_handler = &nvme_err_handler,
2818};
2819
2820static int __init nvme_init(void)
2821{
0ac13140 2822 int result;
1fa6aead 2823
b9afca3e 2824 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2825
9a6b9458
KB		 2826 nvme_workq = create_singlethread_workqueue("nvme");
2827 if (!nvme_workq)
b9afca3e 2828 return -ENOMEM;
9a6b9458 2829
5c42ea16
KB		 2830 result = register_blkdev(nvme_major, "nvme");
2831 if (result < 0)
9a6b9458 2832 goto kill_workq;
5c42ea16 2833 else if (result > 0)
0ac13140 2834 nvme_major = result;
b60503ba 2835
f3db22fe
KB		 2836 result = pci_register_driver(&nvme_driver);
2837 if (result)
a4aea562 2838 goto unregister_blkdev;
1fa6aead 2839 return 0;
b60503ba 2840
1fa6aead 2841 unregister_blkdev:
b60503ba 2842 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2843 kill_workq:
2844 destroy_workqueue(nvme_workq);
b60503ba
MW		 2845 return result;
2846}
2847
2848static void __exit nvme_exit(void)
2849{
2850 pci_unregister_driver(&nvme_driver);
f3db22fe 2851 unregister_hotcpu_notifier(&nvme_nb);
b60503ba 2852 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2853 destroy_workqueue(nvme_workq);
b9afca3e 2854 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 2855 _nvme_check_size();
b60503ba
MW		 2856}
2857
2858MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2859MODULE_LICENSE("GPL");
6eb0d698 2860MODULE_VERSION("0.9");
b60503ba
MW		 2861module_init(nvme_init);
2862module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)