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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
40#include <linux/types.h>
5d0f6131 41#include <scsi/sg.h>
797a796a
HM		 42#include <asm-generic/io-64-nonatomic-lo-hi.h>
43
9d43cf64 44#define NVME_Q_DEPTH 1024
a4aea562 45#define NVME_AQ_DEPTH 64
b60503ba
MW		 46#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 48#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 49#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 50#define IOD_TIMEOUT (retry_time * HZ)
51
52static unsigned char admin_timeout = 60;
53module_param(admin_timeout, byte, 0644);
54MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 55
bd67608a
MW		 56unsigned char nvme_io_timeout = 30;
57module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 58MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 59
61e4ce08
KB		 60static unsigned char retry_time = 30;
61module_param(retry_time, byte, 0644);
62MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
63
2484f407
DM		 64static unsigned char shutdown_timeout = 5;
65module_param(shutdown_timeout, byte, 0644);
66MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
67
b60503ba
MW		 68static int nvme_major;
69module_param(nvme_major, int, 0);
70
58ffacb5
MW		 71static int use_threaded_interrupts;
72module_param(use_threaded_interrupts, int, 0);
73
1fa6aead
MW		 74static DEFINE_SPINLOCK(dev_list_lock);
75static LIST_HEAD(dev_list);
76static struct task_struct *nvme_thread;
9a6b9458 77static struct workqueue_struct *nvme_workq;
b9afca3e 78static wait_queue_head_t nvme_kthread_wait;
f3db22fe 79static struct notifier_block nvme_nb;
1fa6aead 80
d4b4ff8e 81static void nvme_reset_failed_dev(struct work_struct *ws);
a4aea562 82static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 83
4d115420
KB		 84struct async_cmd_info {
85 struct kthread_work work;
86 struct kthread_worker *worker;
a4aea562 87 struct request *req;
4d115420
KB		 88 u32 result;
89 int status;
90 void *ctx;
91};
1fa6aead 92
b60503ba
MW		 93/*
94 * An NVM Express queue. Each device has at least two (one for admin
95 * commands and one for I/O commands).
96 */
97struct nvme_queue {
f435c282 98 struct llist_node node;
b60503ba 99 struct device *q_dmadev;
091b6092 100 struct nvme_dev *dev;
3193f07b 101 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 102 spinlock_t q_lock;
103 struct nvme_command *sq_cmds;
104 volatile struct nvme_completion *cqes;
105 dma_addr_t sq_dma_addr;
106 dma_addr_t cq_dma_addr;
b60503ba
MW		 107 u32 __iomem *q_db;
108 u16 q_depth;
6222d172 109 s16 cq_vector;
b60503ba
MW		 110 u16 sq_head;
111 u16 sq_tail;
112 u16 cq_head;
c30341dc 113 u16 qid;
e9539f47
MW		 114 u8 cq_phase;
115 u8 cqe_seen;
4d115420 116 struct async_cmd_info cmdinfo;
a4aea562 117 struct blk_mq_hw_ctx *hctx;
b60503ba
MW		 118};
119
120/*
121 * Check we didin't inadvertently grow the command struct
122 */
123static inline void _nvme_check_size(void)
124{
125 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 130 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 131 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 136 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 137}
138
edd10d33 139typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 140 struct nvme_completion *);
141
e85248e5 142struct nvme_cmd_info {
c2f5b650
MW		 143 nvme_completion_fn fn;
144 void *ctx;
c30341dc 145 int aborted;
a4aea562 146 struct nvme_queue *nvmeq;
ac3dd5bd 147 struct nvme_iod iod[0];
e85248e5
MW		 148};
149
ac3dd5bd
JA		 150/*
151 * Max size of iod being embedded in the request payload
152 */
153#define NVME_INT_PAGES 2
154#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
155
156/*
157 * Will slightly overestimate the number of pages needed. This is OK
158 * as it only leads to a small amount of wasted memory for the lifetime of
159 * the I/O.
160 */
161static int nvme_npages(unsigned size, struct nvme_dev *dev)
162{
163 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
164 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
165}
166
167static unsigned int nvme_cmd_size(struct nvme_dev *dev)
168{
169 unsigned int ret = sizeof(struct nvme_cmd_info);
170
171 ret += sizeof(struct nvme_iod);
172 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
173 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
174
175 return ret;
176}
177
a4aea562
MB		 178static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
179 unsigned int hctx_idx)
e85248e5 180{
a4aea562
MB		 181 struct nvme_dev *dev = data;
182 struct nvme_queue *nvmeq = dev->queues[0];
183
184 WARN_ON(nvmeq->hctx);
185 nvmeq->hctx = hctx;
186 hctx->driver_data = nvmeq;
187 return 0;
e85248e5
MW		 188}
189
a4aea562
MB		 190static int nvme_admin_init_request(void *data, struct request *req,
191 unsigned int hctx_idx, unsigned int rq_idx,
192 unsigned int numa_node)
22404274 193{
a4aea562
MB		 194 struct nvme_dev *dev = data;
195 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
196 struct nvme_queue *nvmeq = dev->queues[0];
197
198 BUG_ON(!nvmeq);
199 cmd->nvmeq = nvmeq;
200 return 0;
22404274
KB		 201}
202
2c30540b
JA		 203static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
204{
205 struct nvme_queue *nvmeq = hctx->driver_data;
206
207 nvmeq->hctx = NULL;
208}
209
a4aea562
MB		 210static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
211 unsigned int hctx_idx)
b60503ba 212{
a4aea562
MB		 213 struct nvme_dev *dev = data;
214 struct nvme_queue *nvmeq = dev->queues[
215 (hctx_idx % dev->queue_count) + 1];
b60503ba 216
a4aea562
MB		 217 if (!nvmeq->hctx)
218 nvmeq->hctx = hctx;
219
220 /* nvmeq queues are shared between namespaces. We assume here that
221 * blk-mq map the tags so they match up with the nvme queue tags. */
222 WARN_ON(nvmeq->hctx->tags != hctx->tags);
b60503ba 223
a4aea562
MB		 224 hctx->driver_data = nvmeq;
225 return 0;
b60503ba
MW		 226}
227
a4aea562
MB		 228static int nvme_init_request(void *data, struct request *req,
229 unsigned int hctx_idx, unsigned int rq_idx,
230 unsigned int numa_node)
b60503ba 231{
a4aea562
MB		 232 struct nvme_dev *dev = data;
233 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
234 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
235
236 BUG_ON(!nvmeq);
237 cmd->nvmeq = nvmeq;
238 return 0;
239}
240
241static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
242 nvme_completion_fn handler)
243{
244 cmd->fn = handler;
245 cmd->ctx = ctx;
246 cmd->aborted = 0;
c917dfe5 247 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 248}
249
ac3dd5bd
JA		 250static void *iod_get_private(struct nvme_iod *iod)
251{
252 return (void *) (iod->private & ~0x1UL);
253}
254
255/*
256 * If bit 0 is set, the iod is embedded in the request payload.
257 */
258static bool iod_should_kfree(struct nvme_iod *iod)
259{
260 return (iod->private & 0x01) == 0;
261}
262
c2f5b650
MW		 263/* Special values must be less than 0x1000 */
264#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 265#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
266#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
267#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 268
edd10d33 269static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 270 struct nvme_completion *cqe)
271{
272 if (ctx == CMD_CTX_CANCELLED)
273 return;
c2f5b650 274 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 275 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 276 "completed id %d twice on queue %d\n",
277 cqe->command_id, le16_to_cpup(&cqe->sq_id));
278 return;
279 }
280 if (ctx == CMD_CTX_INVALID) {
edd10d33 281 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 282 "invalid id %d completed on queue %d\n",
283 cqe->command_id, le16_to_cpup(&cqe->sq_id));
284 return;
285 }
edd10d33 286 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 287}
288
a4aea562 289static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 290{
c2f5b650 291 void *ctx;
b60503ba 292
859361a2 293 if (fn)
a4aea562
MB		 294 *fn = cmd->fn;
295 ctx = cmd->ctx;
296 cmd->fn = special_completion;
297 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 298 return ctx;
b60503ba
MW		 299}
300
a4aea562
MB		 301static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
302 struct nvme_completion *cqe)
3c0cf138 303{
a4aea562 304 struct request *req = ctx;
3c0cf138 305
a4aea562
MB		 306 u32 result = le32_to_cpup(&cqe->result);
307 u16 status = le16_to_cpup(&cqe->status) >> 1;
308
309 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
310 ++nvmeq->dev->event_limit;
311 if (status == NVME_SC_SUCCESS)
312 dev_warn(nvmeq->q_dmadev,
313 "async event result %08x\n", result);
314
9d135bb8 315 blk_mq_free_hctx_request(nvmeq->hctx, req);
b60503ba
MW		 316}
317
a4aea562
MB		 318static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
319 struct nvme_completion *cqe)
5a92e700 320{
a4aea562
MB		 321 struct request *req = ctx;
322
323 u16 status = le16_to_cpup(&cqe->status) >> 1;
324 u32 result = le32_to_cpup(&cqe->result);
a51afb54 325
9d135bb8 326 blk_mq_free_hctx_request(nvmeq->hctx, req);
a51afb54 327
a4aea562
MB		 328 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
329 ++nvmeq->dev->abort_limit;
5a92e700
KB		 330}
331
a4aea562
MB		 332static void async_completion(struct nvme_queue *nvmeq, void *ctx,
333 struct nvme_completion *cqe)
b60503ba 334{
a4aea562
MB		 335 struct async_cmd_info *cmdinfo = ctx;
336 cmdinfo->result = le32_to_cpup(&cqe->result);
337 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
338 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
9d135bb8 339 blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
b60503ba
MW		 340}
341
a4aea562
MB		 342static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
343 unsigned int tag)
b60503ba 344{
a4aea562
MB		 345 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
346 struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
a51afb54 347
a4aea562 348 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 349}
350
a4aea562
MB		 351/*
352 * Called with local interrupts disabled and the q_lock held. May not sleep.
353 */
354static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
355 nvme_completion_fn *fn)
4f5099af 356{
a4aea562
MB		 357 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
358 void *ctx;
359 if (tag >= nvmeq->q_depth) {
360 *fn = special_completion;
361 return CMD_CTX_INVALID;
362 }
363 if (fn)
364 *fn = cmd->fn;
365 ctx = cmd->ctx;
366 cmd->fn = special_completion;
367 cmd->ctx = CMD_CTX_COMPLETED;
368 return ctx;
b60503ba
MW		 369}
370
371/**
714a7a22 372 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 373 * @nvmeq: The queue to use
374 * @cmd: The command to send
375 *
376 * Safe to use from interrupt context
377 */
a4aea562 378static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 379{
a4aea562
MB		 380 u16 tail = nvmeq->sq_tail;
381
b60503ba 382 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 383 if (++tail == nvmeq->q_depth)
384 tail = 0;
7547881d 385 writel(tail, nvmeq->q_db);
b60503ba 386 nvmeq->sq_tail = tail;
b60503ba
MW		 387
388 return 0;
389}
390
a4aea562
MB		 391static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
392{
393 unsigned long flags;
394 int ret;
395 spin_lock_irqsave(&nvmeq->q_lock, flags);
396 ret = __nvme_submit_cmd(nvmeq, cmd);
397 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
398 return ret;
399}
400
eca18b23 401static __le64 **iod_list(struct nvme_iod *iod)
e025344c 402{
eca18b23 403 return ((void *)iod) + iod->offset;
e025344c
SMM		 404}
405
ac3dd5bd
JA		 406static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
407 unsigned nseg, unsigned long private)
eca18b23 408{
ac3dd5bd
JA		 409 iod->private = private;
410 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
411 iod->npages = -1;
412 iod->length = nbytes;
413 iod->nents = 0;
eca18b23 414}
b60503ba 415
eca18b23 416static struct nvme_iod *
ac3dd5bd
JA		 417__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
418 unsigned long priv, gfp_t gfp)
b60503ba 419{
eca18b23 420 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 421 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 422 sizeof(struct scatterlist) * nseg, gfp);
423
ac3dd5bd
JA		 424 if (iod)
425 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 426
427 return iod;
b60503ba
MW		 428}
429
ac3dd5bd
JA		 430static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
431 gfp_t gfp)
432{
433 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
434 sizeof(struct nvme_dsm_range);
435 unsigned long mask = 0;
436 struct nvme_iod *iod;
437
438 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
439 size <= NVME_INT_BYTES(dev)) {
440 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
441
442 iod = cmd->iod;
443 mask = 0x01;
444 iod_init(iod, size, rq->nr_phys_segments,
445 (unsigned long) rq | 0x01);
446 return iod;
447 }
448
449 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
450 (unsigned long) rq, gfp);
451}
452
5d0f6131 453void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 454{
1d090624 455 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 456 int i;
457 __le64 **list = iod_list(iod);
458 dma_addr_t prp_dma = iod->first_dma;
459
460 if (iod->npages == 0)
461 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
462 for (i = 0; i < iod->npages; i++) {
463 __le64 *prp_list = list[i];
464 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
465 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
466 prp_dma = next_prp_dma;
467 }
ac3dd5bd
JA		 468
469 if (iod_should_kfree(iod))
470 kfree(iod);
b60503ba
MW		 471}
472
b4ff9c8d
KB		 473static int nvme_error_status(u16 status)
474{
475 switch (status & 0x7ff) {
476 case NVME_SC_SUCCESS:
477 return 0;
478 case NVME_SC_CAP_EXCEEDED:
479 return -ENOSPC;
480 default:
481 return -EIO;
482 }
483}
484
a4aea562 485static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 486 struct nvme_completion *cqe)
487{
eca18b23 488 struct nvme_iod *iod = ctx;
ac3dd5bd 489 struct request *req = iod_get_private(iod);
a4aea562
MB		 490 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
491
b60503ba
MW		 492 u16 status = le16_to_cpup(&cqe->status) >> 1;
493
edd10d33 494 if (unlikely(status)) {
a4aea562
MB		 495 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
496 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 497 unsigned long flags;
498
a4aea562 499 blk_mq_requeue_request(req);
c9d3bf88
KB		 500 spin_lock_irqsave(req->q->queue_lock, flags);
501 if (!blk_queue_stopped(req->q))
502 blk_mq_kick_requeue_list(req->q);
503 spin_unlock_irqrestore(req->q->queue_lock, flags);
edd10d33
KB		 504 return;
505 }
a4aea562
MB		 506 req->errors = nvme_error_status(status);
507 } else
508 req->errors = 0;
509
510 if (cmd_rq->aborted)
511 dev_warn(&nvmeq->dev->pci_dev->dev,
512 "completing aborted command with status:%04x\n",
513 status);
514
515 if (iod->nents)
516 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
517 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
edd10d33 518 nvme_free_iod(nvmeq->dev, iod);
3291fa57 519
a4aea562 520 blk_mq_complete_request(req);
b60503ba
MW		 521}
522
184d2944 523/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 524int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
525 gfp_t gfp)
ff22b54f 526{
99802a7a 527 struct dma_pool *pool;
eca18b23
MW		 528 int length = total_len;
529 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 530 int dma_len = sg_dma_len(sg);
531 u64 dma_addr = sg_dma_address(sg);
532 int offset = offset_in_page(dma_addr);
e025344c 533 __le64 *prp_list;
eca18b23 534 __le64 **list = iod_list(iod);
e025344c 535 dma_addr_t prp_dma;
eca18b23 536 int nprps, i;
1d090624 537 u32 page_size = dev->page_size;
ff22b54f 538
1d090624 539 length -= (page_size - offset);
ff22b54f 540 if (length <= 0)
eca18b23 541 return total_len;
ff22b54f 542
1d090624 543 dma_len -= (page_size - offset);
ff22b54f 544 if (dma_len) {
1d090624 545 dma_addr += (page_size - offset);
ff22b54f
MW		 546 } else {
547 sg = sg_next(sg);
548 dma_addr = sg_dma_address(sg);
549 dma_len = sg_dma_len(sg);
550 }
551
1d090624 552 if (length <= page_size) {
edd10d33 553 iod->first_dma = dma_addr;
eca18b23 554 return total_len;
e025344c
SMM		 555 }
556
1d090624 557 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 558 if (nprps <= (256 / 8)) {
559 pool = dev->prp_small_pool;
eca18b23 560 iod->npages = 0;
99802a7a
MW		 561 } else {
562 pool = dev->prp_page_pool;
eca18b23 563 iod->npages = 1;
99802a7a
MW		 564 }
565
b77954cb
MW		 566 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
567 if (!prp_list) {
edd10d33 568 iod->first_dma = dma_addr;
eca18b23 569 iod->npages = -1;
1d090624 570 return (total_len - length) + page_size;
b77954cb 571 }
eca18b23
MW		 572 list[0] = prp_list;
573 iod->first_dma = prp_dma;
e025344c
SMM		 574 i = 0;
575 for (;;) {
1d090624 576 if (i == page_size >> 3) {
e025344c 577 __le64 *old_prp_list = prp_list;
b77954cb 578 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 579 if (!prp_list)
580 return total_len - length;
581 list[iod->npages++] = prp_list;
7523d834
MW		 582 prp_list[0] = old_prp_list[i - 1];
583 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
584 i = 1;
e025344c
SMM		 585 }
586 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 587 dma_len -= page_size;
588 dma_addr += page_size;
589 length -= page_size;
e025344c
SMM		 590 if (length <= 0)
591 break;
592 if (dma_len > 0)
593 continue;
594 BUG_ON(dma_len < 0);
595 sg = sg_next(sg);
596 dma_addr = sg_dma_address(sg);
597 dma_len = sg_dma_len(sg);
ff22b54f
MW		 598 }
599
eca18b23 600 return total_len;
ff22b54f
MW		 601}
602
a4aea562
MB		 603/*
604 * We reuse the small pool to allocate the 16-byte range here as it is not
605 * worth having a special pool for these or additional cases to handle freeing
606 * the iod.
607 */
608static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
609 struct request *req, struct nvme_iod *iod)
0e5e4f0e 610{
edd10d33
KB		 611 struct nvme_dsm_range *range =
612 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 613 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
614
0e5e4f0e 615 range->cattr = cpu_to_le32(0);
a4aea562
MB		 616 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
617 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e
KB		 618
619 memset(cmnd, 0, sizeof(*cmnd));
620 cmnd->dsm.opcode = nvme_cmd_dsm;
a4aea562 621 cmnd->dsm.command_id = req->tag;
0e5e4f0e
KB		 622 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
623 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
624 cmnd->dsm.nr = 0;
625 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
626
627 if (++nvmeq->sq_tail == nvmeq->q_depth)
628 nvmeq->sq_tail = 0;
629 writel(nvmeq->sq_tail, nvmeq->q_db);
0e5e4f0e
KB		 630}
631
a4aea562 632static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 633 int cmdid)
634{
635 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
636
637 memset(cmnd, 0, sizeof(*cmnd));
638 cmnd->common.opcode = nvme_cmd_flush;
639 cmnd->common.command_id = cmdid;
640 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
641
642 if (++nvmeq->sq_tail == nvmeq->q_depth)
643 nvmeq->sq_tail = 0;
644 writel(nvmeq->sq_tail, nvmeq->q_db);
00df5cb4
MW		 645}
646
a4aea562
MB		 647static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
648 struct nvme_ns *ns)
b60503ba 649{
ac3dd5bd 650 struct request *req = iod_get_private(iod);
ff22b54f 651 struct nvme_command *cmnd;
a4aea562
MB		 652 u16 control = 0;
653 u32 dsmgmt = 0;
00df5cb4 654
a4aea562 655 if (req->cmd_flags & REQ_FUA)
b60503ba 656 control |= NVME_RW_FUA;
a4aea562 657 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 658 control |= NVME_RW_LR;
659
a4aea562 660 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 661 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
662
ff22b54f 663 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 664 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 665
a4aea562
MB		 666 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
667 cmnd->rw.command_id = req->tag;
ff22b54f 668 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 669 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
670 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
a4aea562
MB		 671 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
672 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
ff22b54f
MW		 673 cmnd->rw.control = cpu_to_le16(control);
674 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 675
b60503ba
MW		 676 if (++nvmeq->sq_tail == nvmeq->q_depth)
677 nvmeq->sq_tail = 0;
7547881d 678 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 679
1974b1ae 680 return 0;
edd10d33
KB		 681}
682
a4aea562
MB		 683static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
684 const struct blk_mq_queue_data *bd)
edd10d33 685{
a4aea562
MB		 686 struct nvme_ns *ns = hctx->queue->queuedata;
687 struct nvme_queue *nvmeq = hctx->driver_data;
688 struct request *req = bd->rq;
689 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 690 struct nvme_iod *iod;
a4aea562 691 enum dma_data_direction dma_dir;
edd10d33 692
ac3dd5bd 693 iod = nvme_alloc_iod(req, ns->dev, GFP_ATOMIC);
edd10d33 694 if (!iod)
fe54303e 695 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 696
a4aea562 697 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 698 void *range;
699 /*
700 * We reuse the small pool to allocate the 16-byte range here
701 * as it is not worth having a special pool for these or
702 * additional cases to handle freeing the iod.
703 */
704 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
705 GFP_ATOMIC,
706 &iod->first_dma);
a4aea562 707 if (!range)
fe54303e 708 goto retry_cmd;
edd10d33
KB		 709 iod_list(iod)[0] = (__le64 *)range;
710 iod->npages = 0;
ac3dd5bd 711 } else if (req->nr_phys_segments) {
a4aea562
MB		 712 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
713
ac3dd5bd 714 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 715 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 716 if (!iod->nents)
717 goto error_cmd;
a4aea562
MB		 718
719 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 720 goto retry_cmd;
a4aea562 721
fe54303e
JA		 722 if (blk_rq_bytes(req) !=
723 nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
724 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg,
725 iod->nents, dma_dir);
726 goto retry_cmd;
727 }
edd10d33 728 }
1974b1ae 729
9af8785a 730 nvme_set_info(cmd, iod, req_completion);
a4aea562
MB		 731 spin_lock_irq(&nvmeq->q_lock);
732 if (req->cmd_flags & REQ_DISCARD)
733 nvme_submit_discard(nvmeq, ns, req, iod);
734 else if (req->cmd_flags & REQ_FLUSH)
735 nvme_submit_flush(nvmeq, ns, req->tag);
736 else
737 nvme_submit_iod(nvmeq, iod, ns);
738
739 nvme_process_cq(nvmeq);
740 spin_unlock_irq(&nvmeq->q_lock);
741 return BLK_MQ_RQ_QUEUE_OK;
742
fe54303e
JA		 743 error_cmd:
744 nvme_free_iod(nvmeq->dev, iod);
745 return BLK_MQ_RQ_QUEUE_ERROR;
746 retry_cmd:
eca18b23 747 nvme_free_iod(nvmeq->dev, iod);
fe54303e 748 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 749}
750
e9539f47 751static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 752{
82123460 753 u16 head, phase;
b60503ba 754
b60503ba 755 head = nvmeq->cq_head;
82123460 756 phase = nvmeq->cq_phase;
b60503ba
MW		 757
758 for (;;) {
c2f5b650
MW		 759 void *ctx;
760 nvme_completion_fn fn;
b60503ba 761 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 762 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 763 break;
764 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
765 if (++head == nvmeq->q_depth) {
766 head = 0;
82123460 767 phase = !phase;
b60503ba 768 }
a4aea562 769 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 770 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 771 }
772
773 /* If the controller ignores the cq head doorbell and continuously
774 * writes to the queue, it is theoretically possible to wrap around
775 * the queue twice and mistakenly return IRQ_NONE. Linux only
776 * requires that 0.1% of your interrupts are handled, so this isn't
777 * a big problem.
778 */
82123460 779 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 780 return 0;
b60503ba 781
b80d5ccc 782 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 783 nvmeq->cq_head = head;
82123460 784 nvmeq->cq_phase = phase;
b60503ba 785
e9539f47
MW		 786 nvmeq->cqe_seen = 1;
787 return 1;
b60503ba
MW		 788}
789
a4aea562
MB		 790/* Admin queue isn't initialized as a request queue. If at some point this
791 * happens anyway, make sure to notify the user */
792static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
793 const struct blk_mq_queue_data *bd)
7d822457 794{
a4aea562
MB		 795 WARN_ON_ONCE(1);
796 return BLK_MQ_RQ_QUEUE_ERROR;
7d822457
MW		 797}
798
b60503ba 799static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 800{
801 irqreturn_t result;
802 struct nvme_queue *nvmeq = data;
803 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 804 nvme_process_cq(nvmeq);
805 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
806 nvmeq->cqe_seen = 0;
58ffacb5
MW		 807 spin_unlock(&nvmeq->q_lock);
808 return result;
809}
810
811static irqreturn_t nvme_irq_check(int irq, void *data)
812{
813 struct nvme_queue *nvmeq = data;
814 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
815 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
816 return IRQ_NONE;
817 return IRQ_WAKE_THREAD;
818}
819
a4aea562
MB		 820static void nvme_abort_cmd_info(struct nvme_queue *nvmeq, struct nvme_cmd_info *
821 cmd_info)
3c0cf138
MW		 822{
823 spin_lock_irq(&nvmeq->q_lock);
a4aea562 824 cancel_cmd_info(cmd_info, NULL);
3c0cf138
MW		 825 spin_unlock_irq(&nvmeq->q_lock);
826}
827
c2f5b650
MW		 828struct sync_cmd_info {
829 struct task_struct *task;
830 u32 result;
831 int status;
832};
833
edd10d33 834static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 835 struct nvme_completion *cqe)
836{
837 struct sync_cmd_info *cmdinfo = ctx;
838 cmdinfo->result = le32_to_cpup(&cqe->result);
839 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
840 wake_up_process(cmdinfo->task);
841}
842
b60503ba
MW		 843/*
844 * Returns 0 on success. If the result is negative, it's a Linux error code;
845 * if the result is positive, it's an NVM Express status code
846 */
a4aea562 847static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
5d0f6131 848 u32 *result, unsigned timeout)
b60503ba 849{
a4aea562 850 int ret;
b60503ba 851 struct sync_cmd_info cmdinfo;
a4aea562
MB		 852 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
853 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
b60503ba
MW		 854
855 cmdinfo.task = current;
856 cmdinfo.status = -EINTR;
857
a4aea562
MB		 858 cmd->common.command_id = req->tag;
859
860 nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
b60503ba 861
3c0cf138 862 set_current_state(TASK_KILLABLE);
4f5099af
KB		 863 ret = nvme_submit_cmd(nvmeq, cmd);
864 if (ret) {
a4aea562 865 nvme_finish_cmd(nvmeq, req->tag, NULL);
4f5099af 866 set_current_state(TASK_RUNNING);
4f5099af 867 }
849c6e77 868 ret = schedule_timeout(timeout);
b60503ba 869
849c6e77
JA		 870 /*
871 * Ensure that sync_completion has either run, or that it will
872 * never run.
873 */
874 nvme_abort_cmd_info(nvmeq, blk_mq_rq_to_pdu(req));
875
876 /*
877 * We never got the completion
878 */
879 if (cmdinfo.status == -EINTR)
3c0cf138 880 return -EINTR;
3c0cf138 881
b60503ba
MW		 882 if (result)
883 *result = cmdinfo.result;
884
885 return cmdinfo.status;
886}
887
a4aea562
MB		 888static int nvme_submit_async_admin_req(struct nvme_dev *dev)
889{
890 struct nvme_queue *nvmeq = dev->queues[0];
891 struct nvme_command c;
892 struct nvme_cmd_info *cmd_info;
893 struct request *req;
894
6dcc0cf6 895 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false);
9f173b33
DC		 896 if (IS_ERR(req))
897 return PTR_ERR(req);
a4aea562 898
c917dfe5 899 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562
MB		 900 cmd_info = blk_mq_rq_to_pdu(req);
901 nvme_set_info(cmd_info, req, async_req_completion);
902
903 memset(&c, 0, sizeof(c));
904 c.common.opcode = nvme_admin_async_event;
905 c.common.command_id = req->tag;
906
907 return __nvme_submit_cmd(nvmeq, &c);
908}
909
910static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 911 struct nvme_command *cmd,
912 struct async_cmd_info *cmdinfo, unsigned timeout)
913{
a4aea562
MB		 914 struct nvme_queue *nvmeq = dev->queues[0];
915 struct request *req;
916 struct nvme_cmd_info *cmd_rq;
4d115420 917
a4aea562 918 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 919 if (IS_ERR(req))
920 return PTR_ERR(req);
a4aea562
MB		 921
922 req->timeout = timeout;
923 cmd_rq = blk_mq_rq_to_pdu(req);
924 cmdinfo->req = req;
925 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 926 cmdinfo->status = -EINTR;
a4aea562
MB		 927
928 cmd->common.command_id = req->tag;
929
4f5099af 930 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 931}
932
a64e6bb4 933static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
a4aea562 934 u32 *result, unsigned timeout)
b60503ba 935{
a4aea562
MB		 936 int res;
937 struct request *req;
938
939 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
97fe3832
JA		 940 if (IS_ERR(req))
941 return PTR_ERR(req);
a4aea562 942 res = nvme_submit_sync_cmd(req, cmd, result, timeout);
9d135bb8 943 blk_mq_free_request(req);
a4aea562 944 return res;
4f5099af
KB		 945}
946
a4aea562 947int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
4f5099af
KB		 948 u32 *result)
949{
a4aea562 950 return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 951}
952
a4aea562
MB		 953int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
954 struct nvme_command *cmd, u32 *result)
4d115420 955{
a4aea562
MB		 956 int res;
957 struct request *req;
958
959 req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
960 false);
97fe3832
JA		 961 if (IS_ERR(req))
962 return PTR_ERR(req);
a4aea562 963 res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
9d135bb8 964 blk_mq_free_request(req);
a4aea562 965 return res;
4d115420
KB		 966}
967
b60503ba
MW		 968static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
969{
b60503ba
MW		 970 struct nvme_command c;
971
972 memset(&c, 0, sizeof(c));
973 c.delete_queue.opcode = opcode;
974 c.delete_queue.qid = cpu_to_le16(id);
975
a4aea562 976 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 977}
978
979static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
980 struct nvme_queue *nvmeq)
981{
b60503ba
MW		 982 struct nvme_command c;
983 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
984
985 memset(&c, 0, sizeof(c));
986 c.create_cq.opcode = nvme_admin_create_cq;
987 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
988 c.create_cq.cqid = cpu_to_le16(qid);
989 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
990 c.create_cq.cq_flags = cpu_to_le16(flags);
991 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
992
a4aea562 993 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 994}
995
996static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
997 struct nvme_queue *nvmeq)
998{
b60503ba
MW		 999 struct nvme_command c;
1000 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1001
1002 memset(&c, 0, sizeof(c));
1003 c.create_sq.opcode = nvme_admin_create_sq;
1004 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1005 c.create_sq.sqid = cpu_to_le16(qid);
1006 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1007 c.create_sq.sq_flags = cpu_to_le16(flags);
1008 c.create_sq.cqid = cpu_to_le16(qid);
1009
a4aea562 1010 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 1011}
1012
1013static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1014{
1015 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1016}
1017
1018static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1019{
1020 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1021}
1022
5d0f6131 1023int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 1024 dma_addr_t dma_addr)
1025{
1026 struct nvme_command c;
1027
1028 memset(&c, 0, sizeof(c));
1029 c.identify.opcode = nvme_admin_identify;
1030 c.identify.nsid = cpu_to_le32(nsid);
1031 c.identify.prp1 = cpu_to_le64(dma_addr);
1032 c.identify.cns = cpu_to_le32(cns);
1033
1034 return nvme_submit_admin_cmd(dev, &c, NULL);
1035}
1036
5d0f6131 1037int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1038 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1039{
1040 struct nvme_command c;
1041
1042 memset(&c, 0, sizeof(c));
1043 c.features.opcode = nvme_admin_get_features;
a42cecce 1044 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1045 c.features.prp1 = cpu_to_le64(dma_addr);
1046 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1047
08df1e05 1048 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 1049}
1050
5d0f6131
VV		 1051int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1052 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1053{
1054 struct nvme_command c;
1055
1056 memset(&c, 0, sizeof(c));
1057 c.features.opcode = nvme_admin_set_features;
1058 c.features.prp1 = cpu_to_le64(dma_addr);
1059 c.features.fid = cpu_to_le32(fid);
1060 c.features.dword11 = cpu_to_le32(dword11);
1061
bc5fc7e4
MW		 1062 return nvme_submit_admin_cmd(dev, &c, result);
1063}
1064
c30341dc 1065/**
a4aea562 1066 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1067 *
1068 * Schedule controller reset if the command was already aborted once before and
1069 * still hasn't been returned to the driver, or if this is the admin queue.
1070 */
a4aea562 1071static void nvme_abort_req(struct request *req)
c30341dc 1072{
a4aea562
MB		 1073 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1074 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1075 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1076 struct request *abort_req;
1077 struct nvme_cmd_info *abort_cmd;
1078 struct nvme_command cmd;
c30341dc 1079
a4aea562 1080 if (!nvmeq->qid || cmd_rq->aborted) {
7a509a6b
KB		 1081 unsigned long flags;
1082
1083 spin_lock_irqsave(&dev_list_lock, flags);
c30341dc 1084 if (work_busy(&dev->reset_work))
7a509a6b 1085 goto out;
c30341dc
KB		 1086 list_del_init(&dev->node);
1087 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1088 "I/O %d QID %d timeout, reset controller\n",
1089 req->tag, nvmeq->qid);
9ca97374 1090 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc 1091 queue_work(nvme_workq, &dev->reset_work);
7a509a6b
KB		 1092 out:
1093 spin_unlock_irqrestore(&dev_list_lock, flags);
c30341dc
KB		 1094 return;
1095 }
1096
1097 if (!dev->abort_limit)
1098 return;
1099
a4aea562
MB		 1100 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1101 false);
9f173b33 1102 if (IS_ERR(abort_req))
c30341dc
KB		 1103 return;
1104
a4aea562
MB		 1105 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1106 nvme_set_info(abort_cmd, abort_req, abort_completion);
1107
c30341dc
KB		 1108 memset(&cmd, 0, sizeof(cmd));
1109 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1110 cmd.abort.cid = req->tag;
c30341dc 1111 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1112 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1113
1114 --dev->abort_limit;
a4aea562 1115 cmd_rq->aborted = 1;
c30341dc 1116
a4aea562 1117 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1118 nvmeq->qid);
a4aea562
MB		 1119 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1120 dev_warn(nvmeq->q_dmadev,
1121 "Could not abort I/O %d QID %d",
1122 req->tag, nvmeq->qid);
c87fd540 1123 blk_mq_free_request(abort_req);
a4aea562 1124 }
c30341dc
KB		 1125}
1126
a4aea562
MB		 1127static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1128 struct request *req, void *data, bool reserved)
a09115b2 1129{
a4aea562
MB		 1130 struct nvme_queue *nvmeq = data;
1131 void *ctx;
1132 nvme_completion_fn fn;
1133 struct nvme_cmd_info *cmd;
cef6a948
KB		 1134 struct nvme_completion cqe;
1135
1136 if (!blk_mq_request_started(req))
1137 return;
a09115b2 1138
a4aea562 1139 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1140
a4aea562
MB		 1141 if (cmd->ctx == CMD_CTX_CANCELLED)
1142 return;
1143
cef6a948
KB		 1144 if (blk_queue_dying(req->q))
1145 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1146 else
1147 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1148
1149
a4aea562
MB		 1150 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1151 req->tag, nvmeq->qid);
1152 ctx = cancel_cmd_info(cmd, &fn);
1153 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1154}
1155
a4aea562 1156static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1157{
a4aea562
MB		 1158 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1159 struct nvme_queue *nvmeq = cmd->nvmeq;
1160
7a509a6b
KB		 1161 /*
1162 * The aborted req will be completed on receiving the abort req.
1163 * We enable the timer again. If hit twice, it'll cause a device reset,
1164 * as the device then is in a faulty state.
1165 */
1166 int ret = BLK_EH_RESET_TIMER;
1167
a4aea562
MB		 1168 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1169 nvmeq->qid);
c917dfe5 1170
7a509a6b 1171 spin_lock_irq(&nvmeq->q_lock);
c917dfe5
KB		 1172 if (!nvmeq->dev->initialized) {
1173 /*
1174 * Force cancelled command frees the request, which requires we
1175 * return BLK_EH_NOT_HANDLED.
1176 */
1177 nvme_cancel_queue_ios(nvmeq->hctx, req, nvmeq, reserved);
7a509a6b
KB		 1178 ret = BLK_EH_NOT_HANDLED;
1179 } else
1180 nvme_abort_req(req);
1181 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1182
7a509a6b 1183 return ret;
a4aea562 1184}
22404274 1185
a4aea562
MB		 1186static void nvme_free_queue(struct nvme_queue *nvmeq)
1187{
9e866774
MW		 1188 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1189 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1190 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1191 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1192 kfree(nvmeq);
1193}
1194
a1a5ef99 1195static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1196{
1197 int i;
1198
a1a5ef99 1199 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1200 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1201 dev->queue_count--;
a4aea562 1202 dev->queues[i] = NULL;
f435c282 1203 nvme_free_queue(nvmeq);
121c7ad4 1204 }
22404274
KB		 1205}
1206
4d115420
KB		 1207/**
1208 * nvme_suspend_queue - put queue into suspended state
1209 * @nvmeq - queue to suspend
4d115420
KB		 1210 */
1211static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1212{
2b25d981 1213 int vector;
b60503ba 1214
a09115b2 1215 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1216 if (nvmeq->cq_vector == -1) {
1217 spin_unlock_irq(&nvmeq->q_lock);
1218 return 1;
1219 }
1220 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1221 nvmeq->dev->online_queues--;
2b25d981 1222 nvmeq->cq_vector = -1;
a09115b2
MW		 1223 spin_unlock_irq(&nvmeq->q_lock);
1224
aba2080f
MW		 1225 irq_set_affinity_hint(vector, NULL);
1226 free_irq(vector, nvmeq);
b60503ba 1227
4d115420
KB		 1228 return 0;
1229}
b60503ba 1230
4d115420
KB		 1231static void nvme_clear_queue(struct nvme_queue *nvmeq)
1232{
a4aea562
MB		 1233 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1234
22404274
KB		 1235 spin_lock_irq(&nvmeq->q_lock);
1236 nvme_process_cq(nvmeq);
a4aea562
MB		 1237 if (hctx && hctx->tags)
1238 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
22404274 1239 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1240}
1241
4d115420
KB		 1242static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1243{
a4aea562 1244 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1245
1246 if (!nvmeq)
1247 return;
1248 if (nvme_suspend_queue(nvmeq))
1249 return;
1250
0e53d180
KB		 1251 /* Don't tell the adapter to delete the admin queue.
1252 * Don't tell a removed adapter to delete IO queues. */
1253 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1254 adapter_delete_sq(dev, qid);
1255 adapter_delete_cq(dev, qid);
1256 }
0fb59cbc
KB		 1257 if (!qid && dev->admin_q)
1258 blk_mq_freeze_queue_start(dev->admin_q);
4d115420 1259 nvme_clear_queue(nvmeq);
b60503ba
MW		 1260}
1261
1262static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1263 int depth)
b60503ba
MW		 1264{
1265 struct device *dmadev = &dev->pci_dev->dev;
a4aea562 1266 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1267 if (!nvmeq)
1268 return NULL;
1269
4d51abf9
JP		 1270 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1271 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1272 if (!nvmeq->cqes)
1273 goto free_nvmeq;
b60503ba
MW		 1274
1275 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1276 &nvmeq->sq_dma_addr, GFP_KERNEL);
1277 if (!nvmeq->sq_cmds)
1278 goto free_cqdma;
1279
1280 nvmeq->q_dmadev = dmadev;
091b6092 1281 nvmeq->dev = dev;
3193f07b
MW		 1282 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1283 dev->instance, qid);
b60503ba
MW		 1284 spin_lock_init(&nvmeq->q_lock);
1285 nvmeq->cq_head = 0;
82123460 1286 nvmeq->cq_phase = 1;
b80d5ccc 1287 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1288 nvmeq->q_depth = depth;
c30341dc 1289 nvmeq->qid = qid;
22404274 1290 dev->queue_count++;
a4aea562 1291 dev->queues[qid] = nvmeq;
b60503ba
MW		 1292
1293 return nvmeq;
1294
1295 free_cqdma:
68b8eca5 1296 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1297 nvmeq->cq_dma_addr);
1298 free_nvmeq:
1299 kfree(nvmeq);
1300 return NULL;
1301}
1302
3001082c
MW		 1303static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1304 const char *name)
1305{
58ffacb5
MW		 1306 if (use_threaded_interrupts)
1307 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1308 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1309 name, nvmeq);
3001082c 1310 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1311 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1312}
1313
22404274 1314static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1315{
22404274 1316 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1317
7be50e93 1318 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1319 nvmeq->sq_tail = 0;
1320 nvmeq->cq_head = 0;
1321 nvmeq->cq_phase = 1;
b80d5ccc 1322 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1323 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1324 dev->online_queues++;
7be50e93 1325 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1326}
1327
1328static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1329{
1330 struct nvme_dev *dev = nvmeq->dev;
1331 int result;
3f85d50b 1332
2b25d981 1333 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1334 result = adapter_alloc_cq(dev, qid, nvmeq);
1335 if (result < 0)
22404274 1336 return result;
b60503ba
MW		 1337
1338 result = adapter_alloc_sq(dev, qid, nvmeq);
1339 if (result < 0)
1340 goto release_cq;
1341
3193f07b 1342 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1343 if (result < 0)
1344 goto release_sq;
1345
22404274 1346 nvme_init_queue(nvmeq, qid);
22404274 1347 return result;
b60503ba
MW		 1348
1349 release_sq:
1350 adapter_delete_sq(dev, qid);
1351 release_cq:
1352 adapter_delete_cq(dev, qid);
22404274 1353 return result;
b60503ba
MW		 1354}
1355
ba47e386
MW		 1356static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1357{
1358 unsigned long timeout;
1359 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1360
1361 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1362
1363 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1364 msleep(100);
1365 if (fatal_signal_pending(current))
1366 return -EINTR;
1367 if (time_after(jiffies, timeout)) {
1368 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1369 "Device not ready; aborting %s\n", enabled ?
1370 "initialisation" : "reset");
ba47e386
MW		 1371 return -ENODEV;
1372 }
1373 }
1374
1375 return 0;
1376}
1377
1378/*
1379 * If the device has been passed off to us in an enabled state, just clear
1380 * the enabled bit. The spec says we should set the 'shutdown notification
1381 * bits', but doing so may cause the device to complete commands to the
1382 * admin queue ... and we don't know what memory that might be pointing at!
1383 */
1384static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1385{
01079522
DM		 1386 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1387 dev->ctrl_config &= ~NVME_CC_ENABLE;
1388 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1389
ba47e386
MW		 1390 return nvme_wait_ready(dev, cap, false);
1391}
1392
1393static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1394{
01079522
DM		 1395 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1396 dev->ctrl_config |= NVME_CC_ENABLE;
1397 writel(dev->ctrl_config, &dev->bar->cc);
1398
ba47e386
MW		 1399 return nvme_wait_ready(dev, cap, true);
1400}
1401
1894d8f1
KB		 1402static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1403{
1404 unsigned long timeout;
1894d8f1 1405
01079522
DM		 1406 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1407 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1408
1409 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1410
2484f407 1411 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1412 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1413 NVME_CSTS_SHST_CMPLT) {
1414 msleep(100);
1415 if (fatal_signal_pending(current))
1416 return -EINTR;
1417 if (time_after(jiffies, timeout)) {
1418 dev_err(&dev->pci_dev->dev,
1419 "Device shutdown incomplete; abort shutdown\n");
1420 return -ENODEV;
1421 }
1422 }
1423
1424 return 0;
1425}
1426
a4aea562
MB		 1427static struct blk_mq_ops nvme_mq_admin_ops = {
1428 .queue_rq = nvme_admin_queue_rq,
1429 .map_queue = blk_mq_map_queue,
1430 .init_hctx = nvme_admin_init_hctx,
2c30540b 1431 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1432 .init_request = nvme_admin_init_request,
1433 .timeout = nvme_timeout,
1434};
1435
1436static struct blk_mq_ops nvme_mq_ops = {
1437 .queue_rq = nvme_queue_rq,
1438 .map_queue = blk_mq_map_queue,
1439 .init_hctx = nvme_init_hctx,
2c30540b 1440 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1441 .init_request = nvme_init_request,
1442 .timeout = nvme_timeout,
1443};
1444
ea191d2f
KB		 1445static void nvme_dev_remove_admin(struct nvme_dev *dev)
1446{
1447 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1448 blk_cleanup_queue(dev->admin_q);
1449 blk_mq_free_tag_set(&dev->admin_tagset);
1450 }
1451}
1452
a4aea562
MB		 1453static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1454{
1455 if (!dev->admin_q) {
1456 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1457 dev->admin_tagset.nr_hw_queues = 1;
1458 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1459 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1460 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
ac3dd5bd 1461 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1462 dev->admin_tagset.driver_data = dev;
1463
1464 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1465 return -ENOMEM;
1466
1467 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1468 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1469 blk_mq_free_tag_set(&dev->admin_tagset);
1470 return -ENOMEM;
1471 }
ea191d2f
KB		 1472 if (!blk_get_queue(dev->admin_q)) {
1473 nvme_dev_remove_admin(dev);
1474 return -ENODEV;
1475 }
0fb59cbc
KB		 1476 } else
1477 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1478
1479 return 0;
1480}
1481
8d85fce7 1482static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1483{
ba47e386 1484 int result;
b60503ba 1485 u32 aqa;
ba47e386 1486 u64 cap = readq(&dev->bar->cap);
b60503ba 1487 struct nvme_queue *nvmeq;
1d090624
KB		 1488 unsigned page_shift = PAGE_SHIFT;
1489 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1490 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1491
1492 if (page_shift < dev_page_min) {
1493 dev_err(&dev->pci_dev->dev,
1494 "Minimum device page size (%u) too large for "
1495 "host (%u)\n", 1 << dev_page_min,
1496 1 << page_shift);
1497 return -ENODEV;
1498 }
1499 if (page_shift > dev_page_max) {
1500 dev_info(&dev->pci_dev->dev,
1501 "Device maximum page size (%u) smaller than "
1502 "host (%u); enabling work-around\n",
1503 1 << dev_page_max, 1 << page_shift);
1504 page_shift = dev_page_max;
1505 }
b60503ba 1506
ba47e386
MW		 1507 result = nvme_disable_ctrl(dev, cap);
1508 if (result < 0)
1509 return result;
b60503ba 1510
a4aea562 1511 nvmeq = dev->queues[0];
cd638946 1512 if (!nvmeq) {
2b25d981 1513 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1514 if (!nvmeq)
1515 return -ENOMEM;
cd638946 1516 }
b60503ba
MW		 1517
1518 aqa = nvmeq->q_depth - 1;
1519 aqa |= aqa << 16;
1520
1d090624
KB		 1521 dev->page_size = 1 << page_shift;
1522
01079522 1523 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1524 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1525 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1526 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1527
1528 writel(aqa, &dev->bar->aqa);
1529 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1530 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1531
ba47e386 1532 result = nvme_enable_ctrl(dev, cap);
025c557a 1533 if (result)
a4aea562
MB		 1534 goto free_nvmeq;
1535
2b25d981 1536 nvmeq->cq_vector = 0;
3193f07b 1537 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1538 if (result)
0fb59cbc 1539 goto free_nvmeq;
025c557a 1540
b60503ba 1541 return result;
a4aea562 1542
a4aea562
MB		 1543 free_nvmeq:
1544 nvme_free_queues(dev, 0);
1545 return result;
b60503ba
MW		 1546}
1547
5d0f6131 1548struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1549 unsigned long addr, unsigned length)
b60503ba 1550{
36c14ed9 1551 int i, err, count, nents, offset;
7fc3cdab
MW		 1552 struct scatterlist *sg;
1553 struct page **pages;
eca18b23 1554 struct nvme_iod *iod;
36c14ed9
MW		 1555
1556 if (addr & 3)
eca18b23 1557 return ERR_PTR(-EINVAL);
5460fc03 1558 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1559 return ERR_PTR(-EINVAL);
7fc3cdab 1560
36c14ed9 1561 offset = offset_in_page(addr);
7fc3cdab
MW		 1562 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1563 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1564 if (!pages)
1565 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1566
1567 err = get_user_pages_fast(addr, count, 1, pages);
1568 if (err < count) {
1569 count = err;
1570 err = -EFAULT;
1571 goto put_pages;
1572 }
7fc3cdab 1573
6808c5fb 1574 err = -ENOMEM;
ac3dd5bd 1575 iod = __nvme_alloc_iod(count, length, dev, 0, GFP_KERNEL);
6808c5fb
S		 1576 if (!iod)
1577 goto put_pages;
1578
eca18b23 1579 sg = iod->sg;
36c14ed9 1580 sg_init_table(sg, count);
d0ba1e49
MW		 1581 for (i = 0; i < count; i++) {
1582 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1583 min_t(unsigned, length, PAGE_SIZE - offset),
1584 offset);
d0ba1e49
MW		 1585 length -= (PAGE_SIZE - offset);
1586 offset = 0;
7fc3cdab 1587 }
fe304c43 1588 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1589 iod->nents = count;
7fc3cdab 1590
7fc3cdab
MW		 1591 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1592 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1593 if (!nents)
eca18b23 1594 goto free_iod;
b60503ba 1595
7fc3cdab 1596 kfree(pages);
eca18b23 1597 return iod;
b60503ba 1598
eca18b23
MW		 1599 free_iod:
1600 kfree(iod);
7fc3cdab
MW		 1601 put_pages:
1602 for (i = 0; i < count; i++)
1603 put_page(pages[i]);
1604 kfree(pages);
eca18b23 1605 return ERR_PTR(err);
7fc3cdab 1606}
b60503ba 1607
5d0f6131 1608void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1609 struct nvme_iod *iod)
7fc3cdab 1610{
1c2ad9fa 1611 int i;
b60503ba 1612
1c2ad9fa
MW		 1613 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1614 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1615
1c2ad9fa
MW		 1616 for (i = 0; i < iod->nents; i++)
1617 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1618}
b60503ba 1619
a53295b6
MW		 1620static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1621{
1622 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1623 struct nvme_user_io io;
1624 struct nvme_command c;
f410c680
KB		 1625 unsigned length, meta_len;
1626 int status, i;
1627 struct nvme_iod *iod, *meta_iod = NULL;
1628 dma_addr_t meta_dma_addr;
1629 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1630
1631 if (copy_from_user(&io, uio, sizeof(io)))
1632 return -EFAULT;
6c7d4945 1633 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1634 meta_len = (io.nblocks + 1) * ns->ms;
1635
1636 if (meta_len && ((io.metadata & 3) || !io.metadata))
1637 return -EINVAL;
6c7d4945
MW		 1638
1639 switch (io.opcode) {
1640 case nvme_cmd_write:
1641 case nvme_cmd_read:
6bbf1acd 1642 case nvme_cmd_compare:
eca18b23 1643 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1644 break;
6c7d4945 1645 default:
6bbf1acd 1646 return -EINVAL;
6c7d4945
MW		 1647 }
1648
eca18b23
MW		 1649 if (IS_ERR(iod))
1650 return PTR_ERR(iod);
a53295b6
MW		 1651
1652 memset(&c, 0, sizeof(c));
1653 c.rw.opcode = io.opcode;
1654 c.rw.flags = io.flags;
6c7d4945 1655 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1656 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1657 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1658 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1659 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1660 c.rw.reftag = cpu_to_le32(io.reftag);
1661 c.rw.apptag = cpu_to_le16(io.apptag);
1662 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1663
1664 if (meta_len) {
1b56749e
KB		 1665 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1666 meta_len);
f410c680
KB		 1667 if (IS_ERR(meta_iod)) {
1668 status = PTR_ERR(meta_iod);
1669 meta_iod = NULL;
1670 goto unmap;
1671 }
1672
1673 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1674 &meta_dma_addr, GFP_KERNEL);
1675 if (!meta_mem) {
1676 status = -ENOMEM;
1677 goto unmap;
1678 }
1679
1680 if (io.opcode & 1) {
1681 int meta_offset = 0;
1682
1683 for (i = 0; i < meta_iod->nents; i++) {
1684 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1685 meta_iod->sg[i].offset;
1686 memcpy(meta_mem + meta_offset, meta,
1687 meta_iod->sg[i].length);
1688 kunmap_atomic(meta);
1689 meta_offset += meta_iod->sg[i].length;
1690 }
1691 }
1692
1693 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1694 }
1695
edd10d33
KB		 1696 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1697 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1698 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1699
b77954cb
MW		 1700 if (length != (io.nblocks + 1) << ns->lba_shift)
1701 status = -ENOMEM;
1702 else
a4aea562 1703 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
a53295b6 1704
f410c680
KB		 1705 if (meta_len) {
1706 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1707 int meta_offset = 0;
1708
1709 for (i = 0; i < meta_iod->nents; i++) {
1710 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1711 meta_iod->sg[i].offset;
1712 memcpy(meta, meta_mem + meta_offset,
1713 meta_iod->sg[i].length);
1714 kunmap_atomic(meta);
1715 meta_offset += meta_iod->sg[i].length;
1716 }
1717 }
1718
1719 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1720 meta_dma_addr);
1721 }
1722
1723 unmap:
1c2ad9fa 1724 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1725 nvme_free_iod(dev, iod);
f410c680
KB		 1726
1727 if (meta_iod) {
1728 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1729 nvme_free_iod(dev, meta_iod);
1730 }
1731
a53295b6
MW		 1732 return status;
1733}
1734
a4aea562
MB		 1735static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1736 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1737{
7963e521 1738 struct nvme_passthru_cmd cmd;
6ee44cdc 1739 struct nvme_command c;
eca18b23 1740 int status, length;
c7d36ab8 1741 struct nvme_iod *uninitialized_var(iod);
94f370ca 1742 unsigned timeout;
6ee44cdc 1743
6bbf1acd
MW		 1744 if (!capable(CAP_SYS_ADMIN))
1745 return -EACCES;
1746 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1747 return -EFAULT;
6ee44cdc
MW		 1748
1749 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1750 c.common.opcode = cmd.opcode;
1751 c.common.flags = cmd.flags;
1752 c.common.nsid = cpu_to_le32(cmd.nsid);
1753 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1754 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1755 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1756 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1757 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1758 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1759 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1760 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1761
1762 length = cmd.data_len;
1763 if (cmd.data_len) {
49742188
MW		 1764 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1765 length);
eca18b23
MW		 1766 if (IS_ERR(iod))
1767 return PTR_ERR(iod);
edd10d33
KB		 1768 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1769 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1770 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1771 }
1772
94f370ca
KB		 1773 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1774 ADMIN_TIMEOUT;
a4aea562 1775
6bbf1acd 1776 if (length != cmd.data_len)
b77954cb 1777 status = -ENOMEM;
a4aea562
MB		 1778 else if (ns) {
1779 struct request *req;
1780
1781 req = blk_mq_alloc_request(ns->queue, WRITE,
1782 (GFP_KERNEL|__GFP_WAIT), false);
97fe3832
JA		 1783 if (IS_ERR(req))
1784 status = PTR_ERR(req);
a4aea562
MB		 1785 else {
1786 status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1787 timeout);
9d135bb8 1788 blk_mq_free_request(req);
a4aea562
MB		 1789 }
1790 } else
1791 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
eca18b23 1792
6bbf1acd 1793 if (cmd.data_len) {
1c2ad9fa 1794 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1795 nvme_free_iod(dev, iod);
6bbf1acd 1796 }
f4f117f6 1797
cf90bc48 1798 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1799 sizeof(cmd.result)))
1800 status = -EFAULT;
1801
6ee44cdc
MW		 1802 return status;
1803}
1804
b60503ba
MW		 1805static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1806 unsigned long arg)
1807{
1808 struct nvme_ns *ns = bdev->bd_disk->private_data;
1809
1810 switch (cmd) {
6bbf1acd 1811 case NVME_IOCTL_ID:
c3bfe717 1812 force_successful_syscall_return();
6bbf1acd
MW		 1813 return ns->ns_id;
1814 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1815 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1816 case NVME_IOCTL_IO_CMD:
a4aea562 1817 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1818 case NVME_IOCTL_SUBMIT_IO:
1819 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1820 case SG_GET_VERSION_NUM:
1821 return nvme_sg_get_version_num((void __user *)arg);
1822 case SG_IO:
1823 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1824 default:
1825 return -ENOTTY;
1826 }
1827}
1828
320a3827
KB		 1829#ifdef CONFIG_COMPAT
1830static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1831 unsigned int cmd, unsigned long arg)
1832{
320a3827
KB		 1833 switch (cmd) {
1834 case SG_IO:
e179729a 1835 return -ENOIOCTLCMD;
320a3827
KB		 1836 }
1837 return nvme_ioctl(bdev, mode, cmd, arg);
1838}
1839#else
1840#define nvme_compat_ioctl NULL
1841#endif
1842
9ac27090
KB		 1843static int nvme_open(struct block_device *bdev, fmode_t mode)
1844{
9e60352c
KB		 1845 int ret = 0;
1846 struct nvme_ns *ns;
9ac27090 1847
9e60352c
KB		 1848 spin_lock(&dev_list_lock);
1849 ns = bdev->bd_disk->private_data;
1850 if (!ns)
1851 ret = -ENXIO;
1852 else if (!kref_get_unless_zero(&ns->dev->kref))
1853 ret = -ENXIO;
1854 spin_unlock(&dev_list_lock);
1855
1856 return ret;
9ac27090
KB		 1857}
1858
1859static void nvme_free_dev(struct kref *kref);
1860
1861static void nvme_release(struct gendisk *disk, fmode_t mode)
1862{
1863 struct nvme_ns *ns = disk->private_data;
1864 struct nvme_dev *dev = ns->dev;
1865
1866 kref_put(&dev->kref, nvme_free_dev);
1867}
1868
4cc09e2d
KB		 1869static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1870{
1871 /* some standard values */
1872 geo->heads = 1 << 6;
1873 geo->sectors = 1 << 5;
1874 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1875 return 0;
1876}
1877
1b9dbf7f
KB		 1878static int nvme_revalidate_disk(struct gendisk *disk)
1879{
1880 struct nvme_ns *ns = disk->private_data;
1881 struct nvme_dev *dev = ns->dev;
1882 struct nvme_id_ns *id;
1883 dma_addr_t dma_addr;
1884 int lbaf;
1885
1886 id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
1887 GFP_KERNEL);
1888 if (!id) {
1889 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
1890 __func__);
1891 return 0;
1892 }
1893
1894 if (nvme_identify(dev, ns->ns_id, 0, dma_addr))
1895 goto free;
1896
1897 lbaf = id->flbas & 0xf;
1898 ns->lba_shift = id->lbaf[lbaf].ds;
1899
1900 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1901 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1902 free:
1903 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1904 return 0;
1905}
1906
b60503ba
MW		 1907static const struct block_device_operations nvme_fops = {
1908 .owner = THIS_MODULE,
1909 .ioctl = nvme_ioctl,
320a3827 1910 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1911 .open = nvme_open,
1912 .release = nvme_release,
4cc09e2d 1913 .getgeo = nvme_getgeo,
1b9dbf7f 1914 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 1915};
1916
1fa6aead
MW		 1917static int nvme_kthread(void *data)
1918{
d4b4ff8e 1919 struct nvme_dev *dev, *next;
1fa6aead
MW		 1920
1921 while (!kthread_should_stop()) {
564a232c 1922 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1923 spin_lock(&dev_list_lock);
d4b4ff8e 1924 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1925 int i;
d4b4ff8e
KB		 1926 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1927 dev->initialized) {
1928 if (work_busy(&dev->reset_work))
1929 continue;
1930 list_del_init(&dev->node);
1931 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1932 "Failed status: %x, reset controller\n",
1933 readl(&dev->bar->csts));
9ca97374 1934 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 1935 queue_work(nvme_workq, &dev->reset_work);
1936 continue;
1937 }
1fa6aead 1938 for (i = 0; i < dev->queue_count; i++) {
a4aea562 1939 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 1940 if (!nvmeq)
1941 continue;
1fa6aead 1942 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 1943 nvme_process_cq(nvmeq);
6fccf938
KB		 1944
1945 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 1946 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 1947 break;
1948 dev->event_limit--;
1949 }
1fa6aead
MW		 1950 spin_unlock_irq(&nvmeq->q_lock);
1951 }
1952 }
1953 spin_unlock(&dev_list_lock);
acb7aa0d 1954 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1955 }
1956 return 0;
1957}
1958
0e5e4f0e
KB		 1959static void nvme_config_discard(struct nvme_ns *ns)
1960{
1961 u32 logical_block_size = queue_logical_block_size(ns->queue);
1962 ns->queue->limits.discard_zeroes_data = 0;
1963 ns->queue->limits.discard_alignment = logical_block_size;
1964 ns->queue->limits.discard_granularity = logical_block_size;
1965 ns->queue->limits.max_discard_sectors = 0xffffffff;
1966 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1967}
1968
c3bfe717 1969static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1970 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1971{
1972 struct nvme_ns *ns;
1973 struct gendisk *disk;
a4aea562 1974 int node = dev_to_node(&dev->pci_dev->dev);
b60503ba
MW		 1975 int lbaf;
1976
1977 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1978 return NULL;
1979
a4aea562 1980 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba
MW		 1981 if (!ns)
1982 return NULL;
a4aea562 1983 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 1984 if (IS_ERR(ns->queue))
b60503ba 1985 goto out_free_ns;
4eeb9215
MW		 1986 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1987 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 1988 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 1989 ns->dev = dev;
1990 ns->queue->queuedata = ns;
1991
a4aea562 1992 disk = alloc_disk_node(0, node);
b60503ba
MW		 1993 if (!disk)
1994 goto out_free_queue;
a4aea562 1995
5aff9382 1996 ns->ns_id = nsid;
b60503ba
MW		 1997 ns->disk = disk;
1998 lbaf = id->flbas & 0xf;
1999 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 2000 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 2001 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 2002 if (dev->max_hw_sectors)
2003 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 2004 if (dev->stripe_size)
2005 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2006 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2007 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 2008
2009 disk->major = nvme_major;
469071a3 2010 disk->first_minor = 0;
b60503ba
MW		 2011 disk->fops = &nvme_fops;
2012 disk->private_data = ns;
2013 disk->queue = ns->queue;
388f037f 2014 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 2015 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2016 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 2017 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2018
0e5e4f0e
KB		 2019 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2020 nvme_config_discard(ns);
2021
b60503ba
MW		 2022 return ns;
2023
2024 out_free_queue:
2025 blk_cleanup_queue(ns->queue);
2026 out_free_ns:
2027 kfree(ns);
2028 return NULL;
2029}
2030
42f61420
KB		 2031static void nvme_create_io_queues(struct nvme_dev *dev)
2032{
a4aea562 2033 unsigned i;
42f61420 2034
a4aea562 2035 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2036 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2037 break;
2038
a4aea562
MB		 2039 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2040 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 2041 break;
2042}
2043
b3b06812 2044static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2045{
2046 int status;
2047 u32 result;
b3b06812 2048 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2049
df348139 2050 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2051 &result);
27e8166c
MW		 2052 if (status < 0)
2053 return status;
2054 if (status > 0) {
2055 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2056 status);
badc34d4 2057 return 0;
27e8166c 2058 }
b60503ba
MW		 2059 return min(result & 0xffff, result >> 16) + 1;
2060}
2061
9d713c2b
KB		 2062static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2063{
b80d5ccc 2064 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2065}
2066
8d85fce7 2067static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2068{
a4aea562 2069 struct nvme_queue *adminq = dev->queues[0];
fa08a396 2070 struct pci_dev *pdev = dev->pci_dev;
42f61420 2071 int result, i, vecs, nr_io_queues, size;
b60503ba 2072
42f61420 2073 nr_io_queues = num_possible_cpus();
b348b7d5 2074 result = set_queue_count(dev, nr_io_queues);
badc34d4 2075 if (result <= 0)
1b23484b 2076 return result;
b348b7d5
MW		 2077 if (result < nr_io_queues)
2078 nr_io_queues = result;
b60503ba 2079
9d713c2b
KB		 2080 size = db_bar_size(dev, nr_io_queues);
2081 if (size > 8192) {
f1938f6e 2082 iounmap(dev->bar);
9d713c2b
KB		 2083 do {
2084 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2085 if (dev->bar)
2086 break;
2087 if (!--nr_io_queues)
2088 return -ENOMEM;
2089 size = db_bar_size(dev, nr_io_queues);
2090 } while (1);
f1938f6e 2091 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2092 adminq->q_db = dev->dbs;
f1938f6e
MW		 2093 }
2094
9d713c2b 2095 /* Deregister the admin queue's interrupt */
3193f07b 2096 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2097
e32efbfc
JA		 2098 /*
2099 * If we enable msix early due to not intx, disable it again before
2100 * setting up the full range we need.
2101 */
2102 if (!pdev->irq)
2103 pci_disable_msix(pdev);
2104
be577fab 2105 for (i = 0; i < nr_io_queues; i++)
1b23484b 2106 dev->entry[i].entry = i;
be577fab
AG		 2107 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2108 if (vecs < 0) {
2109 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2110 if (vecs < 0) {
2111 vecs = 1;
2112 } else {
2113 for (i = 0; i < vecs; i++)
2114 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2115 }
2116 }
2117
063a8096
MW		 2118 /*
2119 * Should investigate if there's a performance win from allocating
2120 * more queues than interrupt vectors; it might allow the submission
2121 * path to scale better, even if the receive path is limited by the
2122 * number of interrupts.
2123 */
2124 nr_io_queues = vecs;
42f61420 2125 dev->max_qid = nr_io_queues;
063a8096 2126
3193f07b 2127 result = queue_request_irq(dev, adminq, adminq->irqname);
a4aea562 2128 if (result)
22404274 2129 goto free_queues;
1b23484b 2130
cd638946 2131 /* Free previously allocated queues that are no longer usable */
42f61420 2132 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2133 nvme_create_io_queues(dev);
9ecdc946 2134
22404274 2135 return 0;
b60503ba 2136
22404274 2137 free_queues:
a1a5ef99 2138 nvme_free_queues(dev, 1);
22404274 2139 return result;
b60503ba
MW		 2140}
2141
422ef0c7
MW		 2142/*
2143 * Return: error value if an error occurred setting up the queues or calling
2144 * Identify Device. 0 if these succeeded, even if adding some of the
2145 * namespaces failed. At the moment, these failures are silent. TBD which
2146 * failures should be reported.
2147 */
8d85fce7 2148static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2149{
68608c26 2150 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2151 int res;
2152 unsigned nn, i;
cbb6218f 2153 struct nvme_ns *ns;
51814232 2154 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2155 struct nvme_id_ns *id_ns;
2156 void *mem;
b60503ba 2157 dma_addr_t dma_addr;
159b67d7 2158 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2159
68608c26 2160 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2161 if (!mem)
2162 return -ENOMEM;
b60503ba 2163
bc5fc7e4 2164 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2165 if (res) {
27e8166c 2166 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
b60503ba 2167 res = -EIO;
cbb6218f 2168 goto out;
b60503ba
MW		 2169 }
2170
bc5fc7e4 2171 ctrl = mem;
51814232 2172 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2173 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2174 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2175 dev->vwc = ctrl->vwc;
6fccf938 2176 dev->event_limit = min(ctrl->aerl + 1, 8);
51814232
MW		 2177 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2178 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2179 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2180 if (ctrl->mdts)
8fc23e03 2181 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2182 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2183 (pdev->device == 0x0953) && ctrl->vs[3]) {
2184 unsigned int max_hw_sectors;
2185
159b67d7 2186 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2187 max_hw_sectors = dev->stripe_size >> (shift - 9);
2188 if (dev->max_hw_sectors) {
2189 dev->max_hw_sectors = min(max_hw_sectors,
2190 dev->max_hw_sectors);
2191 } else
2192 dev->max_hw_sectors = max_hw_sectors;
2193 }
2194
2195 dev->tagset.ops = &nvme_mq_ops;
2196 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2197 dev->tagset.timeout = NVME_IO_TIMEOUT;
2198 dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2199 dev->tagset.queue_depth =
2200 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ac3dd5bd 2201 dev->tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 2202 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2203 dev->tagset.driver_data = dev;
2204
2205 if (blk_mq_alloc_tag_set(&dev->tagset))
2206 goto out;
b60503ba 2207
bc5fc7e4 2208 id_ns = mem;
2b2c1896 2209 for (i = 1; i <= nn; i++) {
bc5fc7e4 2210 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2211 if (res)
2212 continue;
2213
bc5fc7e4 2214 if (id_ns->ncap == 0)
b60503ba
MW		 2215 continue;
2216
bc5fc7e4 2217 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2218 dma_addr + 4096, NULL);
b60503ba 2219 if (res)
12209036 2220 memset(mem + 4096, 0, 4096);
b60503ba 2221
bc5fc7e4 2222 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2223 if (ns)
2224 list_add_tail(&ns->list, &dev->namespaces);
2225 }
2226 list_for_each_entry(ns, &dev->namespaces, list)
2227 add_disk(ns->disk);
422ef0c7 2228 res = 0;
b60503ba 2229
bc5fc7e4 2230 out:
684f5c20 2231 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2232 return res;
2233}
2234
0877cb0d
KB		 2235static int nvme_dev_map(struct nvme_dev *dev)
2236{
42f61420 2237 u64 cap;
0877cb0d
KB		 2238 int bars, result = -ENOMEM;
2239 struct pci_dev *pdev = dev->pci_dev;
2240
2241 if (pci_enable_device_mem(pdev))
2242 return result;
2243
2244 dev->entry[0].vector = pdev->irq;
2245 pci_set_master(pdev);
2246 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2247 if (!bars)
2248 goto disable_pci;
2249
0877cb0d
KB		 2250 if (pci_request_selected_regions(pdev, bars, "nvme"))
2251 goto disable_pci;
2252
052d0efa
RK		 2253 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2254 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2255 goto disable;
0877cb0d 2256
0877cb0d
KB		 2257 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2258 if (!dev->bar)
2259 goto disable;
e32efbfc 2260
0e53d180
KB		 2261 if (readl(&dev->bar->csts) == -1) {
2262 result = -ENODEV;
2263 goto unmap;
2264 }
e32efbfc
JA		 2265
2266 /*
2267 * Some devices don't advertse INTx interrupts, pre-enable a single
2268 * MSIX vec for setup. We'll adjust this later.
2269 */
2270 if (!pdev->irq) {
2271 result = pci_enable_msix(pdev, dev->entry, 1);
2272 if (result < 0)
2273 goto unmap;
2274 }
2275
42f61420
KB		 2276 cap = readq(&dev->bar->cap);
2277 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2278 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2279 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2280
2281 return 0;
2282
0e53d180
KB		 2283 unmap:
2284 iounmap(dev->bar);
2285 dev->bar = NULL;
0877cb0d
KB		 2286 disable:
2287 pci_release_regions(pdev);
2288 disable_pci:
2289 pci_disable_device(pdev);
2290 return result;
2291}
2292
2293static void nvme_dev_unmap(struct nvme_dev *dev)
2294{
2295 if (dev->pci_dev->msi_enabled)
2296 pci_disable_msi(dev->pci_dev);
2297 else if (dev->pci_dev->msix_enabled)
2298 pci_disable_msix(dev->pci_dev);
2299
2300 if (dev->bar) {
2301 iounmap(dev->bar);
2302 dev->bar = NULL;
9a6b9458 2303 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2304 }
2305
0877cb0d
KB		 2306 if (pci_is_enabled(dev->pci_dev))
2307 pci_disable_device(dev->pci_dev);
2308}
2309
4d115420
KB		 2310struct nvme_delq_ctx {
2311 struct task_struct *waiter;
2312 struct kthread_worker *worker;
2313 atomic_t refcount;
2314};
2315
2316static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2317{
2318 dq->waiter = current;
2319 mb();
2320
2321 for (;;) {
2322 set_current_state(TASK_KILLABLE);
2323 if (!atomic_read(&dq->refcount))
2324 break;
2325 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2326 fatal_signal_pending(current)) {
0fb59cbc
KB		 2327 /*
2328 * Disable the controller first since we can't trust it
2329 * at this point, but leave the admin queue enabled
2330 * until all queue deletion requests are flushed.
2331 * FIXME: This may take a while if there are more h/w
2332 * queues than admin tags.
2333 */
4d115420 2334 set_current_state(TASK_RUNNING);
4d115420 2335 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2336 nvme_clear_queue(dev->queues[0]);
4d115420 2337 flush_kthread_worker(dq->worker);
0fb59cbc 2338 nvme_disable_queue(dev, 0);
4d115420
KB		 2339 return;
2340 }
2341 }
2342 set_current_state(TASK_RUNNING);
2343}
2344
2345static void nvme_put_dq(struct nvme_delq_ctx *dq)
2346{
2347 atomic_dec(&dq->refcount);
2348 if (dq->waiter)
2349 wake_up_process(dq->waiter);
2350}
2351
2352static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2353{
2354 atomic_inc(&dq->refcount);
2355 return dq;
2356}
2357
2358static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2359{
2360 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2361
2362 nvme_clear_queue(nvmeq);
2363 nvme_put_dq(dq);
2364}
2365
2366static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2367 kthread_work_func_t fn)
2368{
2369 struct nvme_command c;
2370
2371 memset(&c, 0, sizeof(c));
2372 c.delete_queue.opcode = opcode;
2373 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2374
2375 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2376 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2377 ADMIN_TIMEOUT);
4d115420
KB		 2378}
2379
2380static void nvme_del_cq_work_handler(struct kthread_work *work)
2381{
2382 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2383 cmdinfo.work);
2384 nvme_del_queue_end(nvmeq);
2385}
2386
2387static int nvme_delete_cq(struct nvme_queue *nvmeq)
2388{
2389 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2390 nvme_del_cq_work_handler);
2391}
2392
2393static void nvme_del_sq_work_handler(struct kthread_work *work)
2394{
2395 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2396 cmdinfo.work);
2397 int status = nvmeq->cmdinfo.status;
2398
2399 if (!status)
2400 status = nvme_delete_cq(nvmeq);
2401 if (status)
2402 nvme_del_queue_end(nvmeq);
2403}
2404
2405static int nvme_delete_sq(struct nvme_queue *nvmeq)
2406{
2407 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2408 nvme_del_sq_work_handler);
2409}
2410
2411static void nvme_del_queue_start(struct kthread_work *work)
2412{
2413 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2414 cmdinfo.work);
4d115420
KB		 2415 if (nvme_delete_sq(nvmeq))
2416 nvme_del_queue_end(nvmeq);
2417}
2418
2419static void nvme_disable_io_queues(struct nvme_dev *dev)
2420{
2421 int i;
2422 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2423 struct nvme_delq_ctx dq;
2424 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2425 &worker, "nvme%d", dev->instance);
2426
2427 if (IS_ERR(kworker_task)) {
2428 dev_err(&dev->pci_dev->dev,
2429 "Failed to create queue del task\n");
2430 for (i = dev->queue_count - 1; i > 0; i--)
2431 nvme_disable_queue(dev, i);
2432 return;
2433 }
2434
2435 dq.waiter = NULL;
2436 atomic_set(&dq.refcount, 0);
2437 dq.worker = &worker;
2438 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2439 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2440
2441 if (nvme_suspend_queue(nvmeq))
2442 continue;
2443 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2444 nvmeq->cmdinfo.worker = dq.worker;
2445 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2446 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2447 }
2448 nvme_wait_dq(&dq, dev);
2449 kthread_stop(kworker_task);
2450}
2451
b9afca3e
DM		 2452/*
2453* Remove the node from the device list and check
2454* for whether or not we need to stop the nvme_thread.
2455*/
2456static void nvme_dev_list_remove(struct nvme_dev *dev)
2457{
2458 struct task_struct *tmp = NULL;
2459
2460 spin_lock(&dev_list_lock);
2461 list_del_init(&dev->node);
2462 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2463 tmp = nvme_thread;
2464 nvme_thread = NULL;
2465 }
2466 spin_unlock(&dev_list_lock);
2467
2468 if (tmp)
2469 kthread_stop(tmp);
2470}
2471
c9d3bf88
KB		 2472static void nvme_freeze_queues(struct nvme_dev *dev)
2473{
2474 struct nvme_ns *ns;
2475
2476 list_for_each_entry(ns, &dev->namespaces, list) {
2477 blk_mq_freeze_queue_start(ns->queue);
2478
2479 spin_lock(ns->queue->queue_lock);
2480 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2481 spin_unlock(ns->queue->queue_lock);
2482
2483 blk_mq_cancel_requeue_work(ns->queue);
2484 blk_mq_stop_hw_queues(ns->queue);
2485 }
2486}
2487
2488static void nvme_unfreeze_queues(struct nvme_dev *dev)
2489{
2490 struct nvme_ns *ns;
2491
2492 list_for_each_entry(ns, &dev->namespaces, list) {
2493 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2494 blk_mq_unfreeze_queue(ns->queue);
2495 blk_mq_start_stopped_hw_queues(ns->queue, true);
2496 blk_mq_kick_requeue_list(ns->queue);
2497 }
2498}
2499
f0b50732 2500static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2501{
22404274 2502 int i;
7c1b2450 2503 u32 csts = -1;
22404274 2504
d4b4ff8e 2505 dev->initialized = 0;
b9afca3e 2506 nvme_dev_list_remove(dev);
1fa6aead 2507
c9d3bf88
KB		 2508 if (dev->bar) {
2509 nvme_freeze_queues(dev);
7c1b2450 2510 csts = readl(&dev->bar->csts);
c9d3bf88 2511 }
7c1b2450 2512 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2513 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2514 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2515 nvme_suspend_queue(nvmeq);
2516 nvme_clear_queue(nvmeq);
2517 }
2518 } else {
2519 nvme_disable_io_queues(dev);
1894d8f1 2520 nvme_shutdown_ctrl(dev);
4d115420
KB		 2521 nvme_disable_queue(dev, 0);
2522 }
f0b50732
KB		 2523 nvme_dev_unmap(dev);
2524}
2525
2526static void nvme_dev_remove(struct nvme_dev *dev)
2527{
9ac27090 2528 struct nvme_ns *ns;
f0b50732 2529
9ac27090
KB		 2530 list_for_each_entry(ns, &dev->namespaces, list) {
2531 if (ns->disk->flags & GENHD_FL_UP)
2532 del_gendisk(ns->disk);
cef6a948
KB		 2533 if (!blk_queue_dying(ns->queue)) {
2534 blk_mq_abort_requeue_list(ns->queue);
9ac27090 2535 blk_cleanup_queue(ns->queue);
cef6a948 2536 }
b60503ba 2537 }
b60503ba
MW		 2538}
2539
091b6092
MW		 2540static int nvme_setup_prp_pools(struct nvme_dev *dev)
2541{
2542 struct device *dmadev = &dev->pci_dev->dev;
2543 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2544 PAGE_SIZE, PAGE_SIZE, 0);
2545 if (!dev->prp_page_pool)
2546 return -ENOMEM;
2547
99802a7a
MW		 2548 /* Optimisation for I/Os between 4k and 128k */
2549 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2550 256, 256, 0);
2551 if (!dev->prp_small_pool) {
2552 dma_pool_destroy(dev->prp_page_pool);
2553 return -ENOMEM;
2554 }
091b6092
MW		 2555 return 0;
2556}
2557
2558static void nvme_release_prp_pools(struct nvme_dev *dev)
2559{
2560 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2561 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2562}
2563
cd58ad7d
QSA		 2564static DEFINE_IDA(nvme_instance_ida);
2565
2566static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2567{
cd58ad7d
QSA		 2568 int instance, error;
2569
2570 do {
2571 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2572 return -ENODEV;
2573
2574 spin_lock(&dev_list_lock);
2575 error = ida_get_new(&nvme_instance_ida, &instance);
2576 spin_unlock(&dev_list_lock);
2577 } while (error == -EAGAIN);
2578
2579 if (error)
2580 return -ENODEV;
2581
2582 dev->instance = instance;
2583 return 0;
b60503ba
MW		 2584}
2585
2586static void nvme_release_instance(struct nvme_dev *dev)
2587{
cd58ad7d
QSA		 2588 spin_lock(&dev_list_lock);
2589 ida_remove(&nvme_instance_ida, dev->instance);
2590 spin_unlock(&dev_list_lock);
b60503ba
MW		 2591}
2592
9ac27090
KB		 2593static void nvme_free_namespaces(struct nvme_dev *dev)
2594{
2595 struct nvme_ns *ns, *next;
2596
2597 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2598 list_del(&ns->list);
9e60352c
KB		 2599
2600 spin_lock(&dev_list_lock);
2601 ns->disk->private_data = NULL;
2602 spin_unlock(&dev_list_lock);
2603
9ac27090
KB		 2604 put_disk(ns->disk);
2605 kfree(ns);
2606 }
2607}
2608
5e82e952
KB		 2609static void nvme_free_dev(struct kref *kref)
2610{
2611 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2612
a96d4f5c 2613 pci_dev_put(dev->pci_dev);
9ac27090 2614 nvme_free_namespaces(dev);
285dffc9 2615 nvme_release_instance(dev);
a4aea562 2616 blk_mq_free_tag_set(&dev->tagset);
ea191d2f 2617 blk_put_queue(dev->admin_q);
5e82e952
KB		 2618 kfree(dev->queues);
2619 kfree(dev->entry);
2620 kfree(dev);
2621}
2622
2623static int nvme_dev_open(struct inode *inode, struct file *f)
2624{
2625 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2626 miscdev);
2627 kref_get(&dev->kref);
2628 f->private_data = dev;
2629 return 0;
2630}
2631
2632static int nvme_dev_release(struct inode *inode, struct file *f)
2633{
2634 struct nvme_dev *dev = f->private_data;
2635 kref_put(&dev->kref, nvme_free_dev);
2636 return 0;
2637}
2638
2639static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2640{
2641 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2642 struct nvme_ns *ns;
2643
5e82e952
KB		 2644 switch (cmd) {
2645 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2646 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2647 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2648 if (list_empty(&dev->namespaces))
2649 return -ENOTTY;
2650 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2651 return nvme_user_cmd(dev, ns, (void __user *)arg);
5e82e952
KB		 2652 default:
2653 return -ENOTTY;
2654 }
2655}
2656
2657static const struct file_operations nvme_dev_fops = {
2658 .owner = THIS_MODULE,
2659 .open = nvme_dev_open,
2660 .release = nvme_dev_release,
2661 .unlocked_ioctl = nvme_dev_ioctl,
2662 .compat_ioctl = nvme_dev_ioctl,
2663};
2664
a4aea562
MB		 2665static void nvme_set_irq_hints(struct nvme_dev *dev)
2666{
2667 struct nvme_queue *nvmeq;
2668 int i;
2669
2670 for (i = 0; i < dev->online_queues; i++) {
2671 nvmeq = dev->queues[i];
2672
2673 if (!nvmeq->hctx)
2674 continue;
2675
2676 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2677 nvmeq->hctx->cpumask);
2678 }
2679}
2680
f0b50732
KB		 2681static int nvme_dev_start(struct nvme_dev *dev)
2682{
2683 int result;
b9afca3e 2684 bool start_thread = false;
f0b50732
KB		 2685
2686 result = nvme_dev_map(dev);
2687 if (result)
2688 return result;
2689
2690 result = nvme_configure_admin_queue(dev);
2691 if (result)
2692 goto unmap;
2693
2694 spin_lock(&dev_list_lock);
b9afca3e
DM		 2695 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2696 start_thread = true;
2697 nvme_thread = NULL;
2698 }
f0b50732
KB		 2699 list_add(&dev->node, &dev_list);
2700 spin_unlock(&dev_list_lock);
2701
b9afca3e
DM		 2702 if (start_thread) {
2703 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2704 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2705 } else
2706 wait_event_killable(nvme_kthread_wait, nvme_thread);
2707
2708 if (IS_ERR_OR_NULL(nvme_thread)) {
2709 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2710 goto disable;
2711 }
a4aea562
MB		 2712
2713 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 2714 result = nvme_alloc_admin_tags(dev);
2715 if (result)
2716 goto disable;
b9afca3e 2717
f0b50732 2718 result = nvme_setup_io_queues(dev);
badc34d4 2719 if (result)
0fb59cbc 2720 goto free_tags;
f0b50732 2721
a4aea562
MB		 2722 nvme_set_irq_hints(dev);
2723
d82e8bfd 2724 return result;
f0b50732 2725
0fb59cbc
KB		 2726 free_tags:
2727 nvme_dev_remove_admin(dev);
f0b50732 2728 disable:
a1a5ef99 2729 nvme_disable_queue(dev, 0);
b9afca3e 2730 nvme_dev_list_remove(dev);
f0b50732
KB		 2731 unmap:
2732 nvme_dev_unmap(dev);
2733 return result;
2734}
2735
9a6b9458
KB		 2736static int nvme_remove_dead_ctrl(void *arg)
2737{
2738 struct nvme_dev *dev = (struct nvme_dev *)arg;
2739 struct pci_dev *pdev = dev->pci_dev;
2740
2741 if (pci_get_drvdata(pdev))
c81f4975 2742 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2743 kref_put(&dev->kref, nvme_free_dev);
2744 return 0;
2745}
2746
2747static void nvme_remove_disks(struct work_struct *ws)
2748{
9a6b9458
KB		 2749 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2750
5a92e700 2751 nvme_free_queues(dev, 1);
302c6727 2752 nvme_dev_remove(dev);
9a6b9458
KB		 2753}
2754
2755static int nvme_dev_resume(struct nvme_dev *dev)
2756{
2757 int ret;
2758
2759 ret = nvme_dev_start(dev);
badc34d4 2760 if (ret)
9a6b9458 2761 return ret;
badc34d4 2762 if (dev->online_queues < 2) {
9a6b9458 2763 spin_lock(&dev_list_lock);
9ca97374 2764 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2765 queue_work(nvme_workq, &dev->reset_work);
2766 spin_unlock(&dev_list_lock);
c9d3bf88
KB		 2767 } else {
2768 nvme_unfreeze_queues(dev);
2769 nvme_set_irq_hints(dev);
9a6b9458 2770 }
d4b4ff8e 2771 dev->initialized = 1;
9a6b9458
KB		 2772 return 0;
2773}
2774
2775static void nvme_dev_reset(struct nvme_dev *dev)
2776{
2777 nvme_dev_shutdown(dev);
2778 if (nvme_dev_resume(dev)) {
a4aea562 2779 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
9a6b9458
KB		 2780 kref_get(&dev->kref);
2781 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2782 dev->instance))) {
2783 dev_err(&dev->pci_dev->dev,
2784 "Failed to start controller remove task\n");
2785 kref_put(&dev->kref, nvme_free_dev);
2786 }
2787 }
2788}
2789
2790static void nvme_reset_failed_dev(struct work_struct *ws)
2791{
2792 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2793 nvme_dev_reset(dev);
2794}
2795
9ca97374
TH		 2796static void nvme_reset_workfn(struct work_struct *work)
2797{
2798 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2799 dev->reset_workfn(work);
2800}
2801
8d85fce7 2802static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2803{
a4aea562 2804 int node, result = -ENOMEM;
b60503ba
MW		 2805 struct nvme_dev *dev;
2806
a4aea562
MB		 2807 node = dev_to_node(&pdev->dev);
2808 if (node == NUMA_NO_NODE)
2809 set_dev_node(&pdev->dev, 0);
2810
2811 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2812 if (!dev)
2813 return -ENOMEM;
a4aea562
MB		 2814 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2815 GFP_KERNEL, node);
b60503ba
MW		 2816 if (!dev->entry)
2817 goto free;
a4aea562
MB		 2818 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2819 GFP_KERNEL, node);
b60503ba
MW		 2820 if (!dev->queues)
2821 goto free;
2822
2823 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2824 dev->reset_workfn = nvme_reset_failed_dev;
2825 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
a96d4f5c 2826 dev->pci_dev = pci_dev_get(pdev);
9a6b9458 2827 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2828 result = nvme_set_instance(dev);
2829 if (result)
a96d4f5c 2830 goto put_pci;
b60503ba 2831
091b6092
MW		 2832 result = nvme_setup_prp_pools(dev);
2833 if (result)
0877cb0d 2834 goto release;
091b6092 2835
fb35e914 2836 kref_init(&dev->kref);
f0b50732 2837 result = nvme_dev_start(dev);
badc34d4 2838 if (result)
0877cb0d 2839 goto release_pools;
b60503ba 2840
badc34d4
KB		 2841 if (dev->online_queues > 1)
2842 result = nvme_dev_add(dev);
d82e8bfd 2843 if (result)
f0b50732 2844 goto shutdown;
740216fc 2845
5e82e952
KB		 2846 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2847 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2848 dev->miscdev.parent = &pdev->dev;
2849 dev->miscdev.name = dev->name;
2850 dev->miscdev.fops = &nvme_dev_fops;
2851 result = misc_register(&dev->miscdev);
2852 if (result)
2853 goto remove;
2854
a4aea562
MB		 2855 nvme_set_irq_hints(dev);
2856
d4b4ff8e 2857 dev->initialized = 1;
b60503ba
MW		 2858 return 0;
2859
5e82e952
KB		 2860 remove:
2861 nvme_dev_remove(dev);
a4aea562 2862 nvme_dev_remove_admin(dev);
9ac27090 2863 nvme_free_namespaces(dev);
f0b50732
KB		 2864 shutdown:
2865 nvme_dev_shutdown(dev);
0877cb0d 2866 release_pools:
a1a5ef99 2867 nvme_free_queues(dev, 0);
091b6092 2868 nvme_release_prp_pools(dev);
0877cb0d
KB		 2869 release:
2870 nvme_release_instance(dev);
a96d4f5c
KB		 2871 put_pci:
2872 pci_dev_put(dev->pci_dev);
b60503ba
MW		 2873 free:
2874 kfree(dev->queues);
2875 kfree(dev->entry);
2876 kfree(dev);
2877 return result;
2878}
2879
f0d54a54
KB		 2880static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2881{
a6739479 2882 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 2883
a6739479
KB		 2884 if (prepare)
2885 nvme_dev_shutdown(dev);
2886 else
2887 nvme_dev_resume(dev);
f0d54a54
KB		 2888}
2889
09ece142
KB		 2890static void nvme_shutdown(struct pci_dev *pdev)
2891{
2892 struct nvme_dev *dev = pci_get_drvdata(pdev);
2893 nvme_dev_shutdown(dev);
2894}
2895
8d85fce7 2896static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2897{
2898 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2899
2900 spin_lock(&dev_list_lock);
2901 list_del_init(&dev->node);
2902 spin_unlock(&dev_list_lock);
2903
2904 pci_set_drvdata(pdev, NULL);
2905 flush_work(&dev->reset_work);
5e82e952 2906 misc_deregister(&dev->miscdev);
9a6b9458 2907 nvme_dev_shutdown(dev);
c9d3bf88 2908 nvme_dev_remove(dev);
a4aea562 2909 nvme_dev_remove_admin(dev);
a1a5ef99 2910 nvme_free_queues(dev, 0);
9a6b9458 2911 nvme_release_prp_pools(dev);
5e82e952 2912 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2913}
2914
2915/* These functions are yet to be implemented */
2916#define nvme_error_detected NULL
2917#define nvme_dump_registers NULL
2918#define nvme_link_reset NULL
2919#define nvme_slot_reset NULL
2920#define nvme_error_resume NULL
cd638946 2921
671a6018 2922#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2923static int nvme_suspend(struct device *dev)
2924{
2925 struct pci_dev *pdev = to_pci_dev(dev);
2926 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2927
2928 nvme_dev_shutdown(ndev);
2929 return 0;
2930}
2931
2932static int nvme_resume(struct device *dev)
2933{
2934 struct pci_dev *pdev = to_pci_dev(dev);
2935 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2936
9a6b9458 2937 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2938 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 2939 queue_work(nvme_workq, &ndev->reset_work);
2940 }
2941 return 0;
cd638946 2942}
671a6018 2943#endif
cd638946
KB		 2944
2945static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2946
1d352035 2947static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2948 .error_detected = nvme_error_detected,
2949 .mmio_enabled = nvme_dump_registers,
2950 .link_reset = nvme_link_reset,
2951 .slot_reset = nvme_slot_reset,
2952 .resume = nvme_error_resume,
f0d54a54 2953 .reset_notify = nvme_reset_notify,
b60503ba
MW		 2954};
2955
2956/* Move to pci_ids.h later */
2957#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2958
6eb0d698 2959static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2960 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2961 { 0, }
2962};
2963MODULE_DEVICE_TABLE(pci, nvme_id_table);
2964
2965static struct pci_driver nvme_driver = {
2966 .name = "nvme",
2967 .id_table = nvme_id_table,
2968 .probe = nvme_probe,
8d85fce7 2969 .remove = nvme_remove,
09ece142 2970 .shutdown = nvme_shutdown,
cd638946
KB		 2971 .driver = {
2972 .pm = &nvme_dev_pm_ops,
2973 },
b60503ba
MW		 2974 .err_handler = &nvme_err_handler,
2975};
2976
2977static int __init nvme_init(void)
2978{
0ac13140 2979 int result;
1fa6aead 2980
b9afca3e 2981 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2982
9a6b9458
KB		 2983 nvme_workq = create_singlethread_workqueue("nvme");
2984 if (!nvme_workq)
b9afca3e 2985 return -ENOMEM;
9a6b9458 2986
5c42ea16
KB		 2987 result = register_blkdev(nvme_major, "nvme");
2988 if (result < 0)
9a6b9458 2989 goto kill_workq;
5c42ea16 2990 else if (result > 0)
0ac13140 2991 nvme_major = result;
b60503ba 2992
f3db22fe
KB		 2993 result = pci_register_driver(&nvme_driver);
2994 if (result)
a4aea562 2995 goto unregister_blkdev;
1fa6aead 2996 return 0;
b60503ba 2997
1fa6aead 2998 unregister_blkdev:
b60503ba 2999 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3000 kill_workq:
3001 destroy_workqueue(nvme_workq);
b60503ba
MW		 3002 return result;
3003}
3004
3005static void __exit nvme_exit(void)
3006{
3007 pci_unregister_driver(&nvme_driver);
f3db22fe 3008 unregister_hotcpu_notifier(&nvme_nb);
b60503ba 3009 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3010 destroy_workqueue(nvme_workq);
b9afca3e 3011 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3012 _nvme_check_size();
b60503ba
MW		 3013}
3014
3015MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3016MODULE_LICENSE("GPL");
c78b4713 3017MODULE_VERSION("1.0");
b60503ba
MW		 3018module_init(nvme_init);
3019module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)