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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
15 | #include <linux/nvme.h> | |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
42f61420 | 19 | #include <linux/cpu.h> |
fd63e9ce | 20 | #include <linux/delay.h> |
b60503ba MW |
21 | #include <linux/errno.h> |
22 | #include <linux/fs.h> | |
23 | #include <linux/genhd.h> | |
4cc09e2d | 24 | #include <linux/hdreg.h> |
5aff9382 | 25 | #include <linux/idr.h> |
b60503ba MW |
26 | #include <linux/init.h> |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kdev_t.h> | |
1fa6aead | 30 | #include <linux/kthread.h> |
b60503ba | 31 | #include <linux/kernel.h> |
a5768aa8 | 32 | #include <linux/list_sort.h> |
b60503ba MW |
33 | #include <linux/mm.h> |
34 | #include <linux/module.h> | |
35 | #include <linux/moduleparam.h> | |
36 | #include <linux/pci.h> | |
be7b6275 | 37 | #include <linux/poison.h> |
c3bfe717 | 38 | #include <linux/ptrace.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
e1e5e564 | 41 | #include <linux/t10-pi.h> |
b60503ba | 42 | #include <linux/types.h> |
5d0f6131 | 43 | #include <scsi/sg.h> |
797a796a HM |
44 | #include <asm-generic/io-64-nonatomic-lo-hi.h> |
45 | ||
b3fffdef | 46 | #define NVME_MINORS (1U << MINORBITS) |
9d43cf64 | 47 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 48 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
49 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
50 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
9d43cf64 | 51 | #define ADMIN_TIMEOUT (admin_timeout * HZ) |
2484f407 | 52 | #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ) |
9d43cf64 KB |
53 | |
54 | static unsigned char admin_timeout = 60; | |
55 | module_param(admin_timeout, byte, 0644); | |
56 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); | |
b60503ba | 57 | |
bd67608a MW |
58 | unsigned char nvme_io_timeout = 30; |
59 | module_param_named(io_timeout, nvme_io_timeout, byte, 0644); | |
b355084a | 60 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
b60503ba | 61 | |
2484f407 DM |
62 | static unsigned char shutdown_timeout = 5; |
63 | module_param(shutdown_timeout, byte, 0644); | |
64 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
65 | ||
b60503ba MW |
66 | static int nvme_major; |
67 | module_param(nvme_major, int, 0); | |
68 | ||
b3fffdef KB |
69 | static int nvme_char_major; |
70 | module_param(nvme_char_major, int, 0); | |
71 | ||
58ffacb5 MW |
72 | static int use_threaded_interrupts; |
73 | module_param(use_threaded_interrupts, int, 0); | |
74 | ||
8ffaadf7 JD |
75 | static bool use_cmb_sqes = true; |
76 | module_param(use_cmb_sqes, bool, 0644); | |
77 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
78 | ||
1fa6aead MW |
79 | static DEFINE_SPINLOCK(dev_list_lock); |
80 | static LIST_HEAD(dev_list); | |
81 | static struct task_struct *nvme_thread; | |
9a6b9458 | 82 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 83 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 84 | |
b3fffdef KB |
85 | static struct class *nvme_class; |
86 | ||
d4b4ff8e | 87 | static void nvme_reset_failed_dev(struct work_struct *ws); |
4cc06521 | 88 | static int nvme_reset(struct nvme_dev *dev); |
a4aea562 | 89 | static int nvme_process_cq(struct nvme_queue *nvmeq); |
d4b4ff8e | 90 | |
4d115420 KB |
91 | struct async_cmd_info { |
92 | struct kthread_work work; | |
93 | struct kthread_worker *worker; | |
a4aea562 | 94 | struct request *req; |
4d115420 KB |
95 | u32 result; |
96 | int status; | |
97 | void *ctx; | |
98 | }; | |
1fa6aead | 99 | |
b60503ba MW |
100 | /* |
101 | * An NVM Express queue. Each device has at least two (one for admin | |
102 | * commands and one for I/O commands). | |
103 | */ | |
104 | struct nvme_queue { | |
105 | struct device *q_dmadev; | |
091b6092 | 106 | struct nvme_dev *dev; |
3193f07b | 107 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
108 | spinlock_t q_lock; |
109 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 110 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 111 | volatile struct nvme_completion *cqes; |
42483228 | 112 | struct blk_mq_tags **tags; |
b60503ba MW |
113 | dma_addr_t sq_dma_addr; |
114 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
115 | u32 __iomem *q_db; |
116 | u16 q_depth; | |
6222d172 | 117 | s16 cq_vector; |
b60503ba MW |
118 | u16 sq_head; |
119 | u16 sq_tail; | |
120 | u16 cq_head; | |
c30341dc | 121 | u16 qid; |
e9539f47 MW |
122 | u8 cq_phase; |
123 | u8 cqe_seen; | |
4d115420 | 124 | struct async_cmd_info cmdinfo; |
b60503ba MW |
125 | }; |
126 | ||
127 | /* | |
128 | * Check we didin't inadvertently grow the command struct | |
129 | */ | |
130 | static inline void _nvme_check_size(void) | |
131 | { | |
132 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
133 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
134 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
135 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
136 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 137 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 138 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
139 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
140 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
141 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
142 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 143 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
144 | } |
145 | ||
edd10d33 | 146 | typedef void (*nvme_completion_fn)(struct nvme_queue *, void *, |
c2f5b650 MW |
147 | struct nvme_completion *); |
148 | ||
e85248e5 | 149 | struct nvme_cmd_info { |
c2f5b650 MW |
150 | nvme_completion_fn fn; |
151 | void *ctx; | |
c30341dc | 152 | int aborted; |
a4aea562 | 153 | struct nvme_queue *nvmeq; |
ac3dd5bd | 154 | struct nvme_iod iod[0]; |
e85248e5 MW |
155 | }; |
156 | ||
ac3dd5bd JA |
157 | /* |
158 | * Max size of iod being embedded in the request payload | |
159 | */ | |
160 | #define NVME_INT_PAGES 2 | |
161 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size) | |
fda631ff | 162 | #define NVME_INT_MASK 0x01 |
ac3dd5bd JA |
163 | |
164 | /* | |
165 | * Will slightly overestimate the number of pages needed. This is OK | |
166 | * as it only leads to a small amount of wasted memory for the lifetime of | |
167 | * the I/O. | |
168 | */ | |
169 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
170 | { | |
171 | unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size); | |
172 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); | |
173 | } | |
174 | ||
175 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) | |
176 | { | |
177 | unsigned int ret = sizeof(struct nvme_cmd_info); | |
178 | ||
179 | ret += sizeof(struct nvme_iod); | |
180 | ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev); | |
181 | ret += sizeof(struct scatterlist) * NVME_INT_PAGES; | |
182 | ||
183 | return ret; | |
184 | } | |
185 | ||
a4aea562 MB |
186 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
187 | unsigned int hctx_idx) | |
e85248e5 | 188 | { |
a4aea562 MB |
189 | struct nvme_dev *dev = data; |
190 | struct nvme_queue *nvmeq = dev->queues[0]; | |
191 | ||
42483228 KB |
192 | WARN_ON(hctx_idx != 0); |
193 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
194 | WARN_ON(nvmeq->tags); | |
195 | ||
a4aea562 | 196 | hctx->driver_data = nvmeq; |
42483228 | 197 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 198 | return 0; |
e85248e5 MW |
199 | } |
200 | ||
4af0e21c KB |
201 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
202 | { | |
203 | struct nvme_queue *nvmeq = hctx->driver_data; | |
204 | ||
205 | nvmeq->tags = NULL; | |
206 | } | |
207 | ||
a4aea562 MB |
208 | static int nvme_admin_init_request(void *data, struct request *req, |
209 | unsigned int hctx_idx, unsigned int rq_idx, | |
210 | unsigned int numa_node) | |
22404274 | 211 | { |
a4aea562 MB |
212 | struct nvme_dev *dev = data; |
213 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
214 | struct nvme_queue *nvmeq = dev->queues[0]; | |
215 | ||
216 | BUG_ON(!nvmeq); | |
217 | cmd->nvmeq = nvmeq; | |
218 | return 0; | |
22404274 KB |
219 | } |
220 | ||
a4aea562 MB |
221 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
222 | unsigned int hctx_idx) | |
b60503ba | 223 | { |
a4aea562 | 224 | struct nvme_dev *dev = data; |
42483228 | 225 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 226 | |
42483228 KB |
227 | if (!nvmeq->tags) |
228 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 229 | |
42483228 | 230 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
231 | hctx->driver_data = nvmeq; |
232 | return 0; | |
b60503ba MW |
233 | } |
234 | ||
a4aea562 MB |
235 | static int nvme_init_request(void *data, struct request *req, |
236 | unsigned int hctx_idx, unsigned int rq_idx, | |
237 | unsigned int numa_node) | |
b60503ba | 238 | { |
a4aea562 MB |
239 | struct nvme_dev *dev = data; |
240 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
241 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; | |
242 | ||
243 | BUG_ON(!nvmeq); | |
244 | cmd->nvmeq = nvmeq; | |
245 | return 0; | |
246 | } | |
247 | ||
248 | static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx, | |
249 | nvme_completion_fn handler) | |
250 | { | |
251 | cmd->fn = handler; | |
252 | cmd->ctx = ctx; | |
253 | cmd->aborted = 0; | |
c917dfe5 | 254 | blk_mq_start_request(blk_mq_rq_from_pdu(cmd)); |
b60503ba MW |
255 | } |
256 | ||
ac3dd5bd JA |
257 | static void *iod_get_private(struct nvme_iod *iod) |
258 | { | |
259 | return (void *) (iod->private & ~0x1UL); | |
260 | } | |
261 | ||
262 | /* | |
263 | * If bit 0 is set, the iod is embedded in the request payload. | |
264 | */ | |
265 | static bool iod_should_kfree(struct nvme_iod *iod) | |
266 | { | |
fda631ff | 267 | return (iod->private & NVME_INT_MASK) == 0; |
ac3dd5bd JA |
268 | } |
269 | ||
c2f5b650 MW |
270 | /* Special values must be less than 0x1000 */ |
271 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
272 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
273 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
274 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
be7b6275 | 275 | |
edd10d33 | 276 | static void special_completion(struct nvme_queue *nvmeq, void *ctx, |
c2f5b650 MW |
277 | struct nvme_completion *cqe) |
278 | { | |
279 | if (ctx == CMD_CTX_CANCELLED) | |
280 | return; | |
c2f5b650 | 281 | if (ctx == CMD_CTX_COMPLETED) { |
edd10d33 | 282 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
283 | "completed id %d twice on queue %d\n", |
284 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
285 | return; | |
286 | } | |
287 | if (ctx == CMD_CTX_INVALID) { | |
edd10d33 | 288 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
289 | "invalid id %d completed on queue %d\n", |
290 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
291 | return; | |
292 | } | |
edd10d33 | 293 | dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
294 | } |
295 | ||
a4aea562 | 296 | static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn) |
b60503ba | 297 | { |
c2f5b650 | 298 | void *ctx; |
b60503ba | 299 | |
859361a2 | 300 | if (fn) |
a4aea562 MB |
301 | *fn = cmd->fn; |
302 | ctx = cmd->ctx; | |
303 | cmd->fn = special_completion; | |
304 | cmd->ctx = CMD_CTX_CANCELLED; | |
c2f5b650 | 305 | return ctx; |
b60503ba MW |
306 | } |
307 | ||
a4aea562 MB |
308 | static void async_req_completion(struct nvme_queue *nvmeq, void *ctx, |
309 | struct nvme_completion *cqe) | |
3c0cf138 | 310 | { |
a4aea562 MB |
311 | u32 result = le32_to_cpup(&cqe->result); |
312 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
313 | ||
314 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) | |
315 | ++nvmeq->dev->event_limit; | |
a5768aa8 KB |
316 | if (status != NVME_SC_SUCCESS) |
317 | return; | |
318 | ||
319 | switch (result & 0xff07) { | |
320 | case NVME_AER_NOTICE_NS_CHANGED: | |
321 | dev_info(nvmeq->q_dmadev, "rescanning\n"); | |
322 | schedule_work(&nvmeq->dev->scan_work); | |
323 | default: | |
324 | dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result); | |
325 | } | |
b60503ba MW |
326 | } |
327 | ||
a4aea562 MB |
328 | static void abort_completion(struct nvme_queue *nvmeq, void *ctx, |
329 | struct nvme_completion *cqe) | |
5a92e700 | 330 | { |
a4aea562 MB |
331 | struct request *req = ctx; |
332 | ||
333 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
334 | u32 result = le32_to_cpup(&cqe->result); | |
a51afb54 | 335 | |
42483228 | 336 | blk_mq_free_request(req); |
a51afb54 | 337 | |
a4aea562 MB |
338 | dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); |
339 | ++nvmeq->dev->abort_limit; | |
5a92e700 KB |
340 | } |
341 | ||
a4aea562 MB |
342 | static void async_completion(struct nvme_queue *nvmeq, void *ctx, |
343 | struct nvme_completion *cqe) | |
b60503ba | 344 | { |
a4aea562 MB |
345 | struct async_cmd_info *cmdinfo = ctx; |
346 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
347 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
348 | queue_kthread_work(cmdinfo->worker, &cmdinfo->work); | |
42483228 | 349 | blk_mq_free_request(cmdinfo->req); |
b60503ba MW |
350 | } |
351 | ||
a4aea562 MB |
352 | static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq, |
353 | unsigned int tag) | |
b60503ba | 354 | { |
42483228 | 355 | struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag); |
a51afb54 | 356 | |
a4aea562 | 357 | return blk_mq_rq_to_pdu(req); |
4f5099af KB |
358 | } |
359 | ||
a4aea562 MB |
360 | /* |
361 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
362 | */ | |
363 | static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag, | |
364 | nvme_completion_fn *fn) | |
4f5099af | 365 | { |
a4aea562 MB |
366 | struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag); |
367 | void *ctx; | |
368 | if (tag >= nvmeq->q_depth) { | |
369 | *fn = special_completion; | |
370 | return CMD_CTX_INVALID; | |
371 | } | |
372 | if (fn) | |
373 | *fn = cmd->fn; | |
374 | ctx = cmd->ctx; | |
375 | cmd->fn = special_completion; | |
376 | cmd->ctx = CMD_CTX_COMPLETED; | |
377 | return ctx; | |
b60503ba MW |
378 | } |
379 | ||
380 | /** | |
714a7a22 | 381 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
382 | * @nvmeq: The queue to use |
383 | * @cmd: The command to send | |
384 | * | |
385 | * Safe to use from interrupt context | |
386 | */ | |
a4aea562 | 387 | static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) |
b60503ba | 388 | { |
a4aea562 MB |
389 | u16 tail = nvmeq->sq_tail; |
390 | ||
8ffaadf7 JD |
391 | if (nvmeq->sq_cmds_io) |
392 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
393 | else | |
394 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
395 | ||
b60503ba MW |
396 | if (++tail == nvmeq->q_depth) |
397 | tail = 0; | |
7547881d | 398 | writel(tail, nvmeq->q_db); |
b60503ba | 399 | nvmeq->sq_tail = tail; |
b60503ba MW |
400 | |
401 | return 0; | |
402 | } | |
403 | ||
a4aea562 MB |
404 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) |
405 | { | |
406 | unsigned long flags; | |
407 | int ret; | |
408 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
409 | ret = __nvme_submit_cmd(nvmeq, cmd); | |
410 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
411 | return ret; | |
412 | } | |
413 | ||
eca18b23 | 414 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 415 | { |
eca18b23 | 416 | return ((void *)iod) + iod->offset; |
e025344c SMM |
417 | } |
418 | ||
ac3dd5bd JA |
419 | static inline void iod_init(struct nvme_iod *iod, unsigned nbytes, |
420 | unsigned nseg, unsigned long private) | |
eca18b23 | 421 | { |
ac3dd5bd JA |
422 | iod->private = private; |
423 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
424 | iod->npages = -1; | |
425 | iod->length = nbytes; | |
426 | iod->nents = 0; | |
eca18b23 | 427 | } |
b60503ba | 428 | |
eca18b23 | 429 | static struct nvme_iod * |
ac3dd5bd JA |
430 | __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev, |
431 | unsigned long priv, gfp_t gfp) | |
b60503ba | 432 | { |
eca18b23 | 433 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
ac3dd5bd | 434 | sizeof(__le64 *) * nvme_npages(bytes, dev) + |
eca18b23 MW |
435 | sizeof(struct scatterlist) * nseg, gfp); |
436 | ||
ac3dd5bd JA |
437 | if (iod) |
438 | iod_init(iod, bytes, nseg, priv); | |
eca18b23 MW |
439 | |
440 | return iod; | |
b60503ba MW |
441 | } |
442 | ||
ac3dd5bd JA |
443 | static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev, |
444 | gfp_t gfp) | |
445 | { | |
446 | unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) : | |
447 | sizeof(struct nvme_dsm_range); | |
ac3dd5bd JA |
448 | struct nvme_iod *iod; |
449 | ||
450 | if (rq->nr_phys_segments <= NVME_INT_PAGES && | |
451 | size <= NVME_INT_BYTES(dev)) { | |
452 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq); | |
453 | ||
454 | iod = cmd->iod; | |
ac3dd5bd | 455 | iod_init(iod, size, rq->nr_phys_segments, |
fda631ff | 456 | (unsigned long) rq | NVME_INT_MASK); |
ac3dd5bd JA |
457 | return iod; |
458 | } | |
459 | ||
460 | return __nvme_alloc_iod(rq->nr_phys_segments, size, dev, | |
461 | (unsigned long) rq, gfp); | |
462 | } | |
463 | ||
d29ec824 | 464 | static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 465 | { |
1d090624 | 466 | const int last_prp = dev->page_size / 8 - 1; |
eca18b23 MW |
467 | int i; |
468 | __le64 **list = iod_list(iod); | |
469 | dma_addr_t prp_dma = iod->first_dma; | |
470 | ||
471 | if (iod->npages == 0) | |
472 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
473 | for (i = 0; i < iod->npages; i++) { | |
474 | __le64 *prp_list = list[i]; | |
475 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
476 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
477 | prp_dma = next_prp_dma; | |
478 | } | |
ac3dd5bd JA |
479 | |
480 | if (iod_should_kfree(iod)) | |
481 | kfree(iod); | |
b60503ba MW |
482 | } |
483 | ||
b4ff9c8d KB |
484 | static int nvme_error_status(u16 status) |
485 | { | |
486 | switch (status & 0x7ff) { | |
487 | case NVME_SC_SUCCESS: | |
488 | return 0; | |
489 | case NVME_SC_CAP_EXCEEDED: | |
490 | return -ENOSPC; | |
491 | default: | |
492 | return -EIO; | |
493 | } | |
494 | } | |
495 | ||
52b68d7e | 496 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
497 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
498 | { | |
499 | if (be32_to_cpu(pi->ref_tag) == v) | |
500 | pi->ref_tag = cpu_to_be32(p); | |
501 | } | |
502 | ||
503 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
504 | { | |
505 | if (be32_to_cpu(pi->ref_tag) == p) | |
506 | pi->ref_tag = cpu_to_be32(v); | |
507 | } | |
508 | ||
509 | /** | |
510 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
511 | * | |
512 | * The virtual start sector is the one that was originally submitted by the | |
513 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
514 | * start sector may be different. Remap protection information to match the | |
515 | * physical LBA on writes, and back to the original seed on reads. | |
516 | * | |
517 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
518 | */ | |
519 | static void nvme_dif_remap(struct request *req, | |
520 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
521 | { | |
522 | struct nvme_ns *ns = req->rq_disk->private_data; | |
523 | struct bio_integrity_payload *bip; | |
524 | struct t10_pi_tuple *pi; | |
525 | void *p, *pmap; | |
526 | u32 i, nlb, ts, phys, virt; | |
527 | ||
528 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
529 | return; | |
530 | ||
531 | bip = bio_integrity(req->bio); | |
532 | if (!bip) | |
533 | return; | |
534 | ||
535 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
536 | |
537 | p = pmap; | |
538 | virt = bip_get_seed(bip); | |
539 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
540 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
541 | ts = ns->disk->integrity->tuple_size; | |
542 | ||
543 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
544 | pi = (struct t10_pi_tuple *)p; | |
545 | dif_swap(phys, virt, pi); | |
546 | p += ts; | |
547 | } | |
548 | kunmap_atomic(pmap); | |
549 | } | |
550 | ||
52b68d7e KB |
551 | static int nvme_noop_verify(struct blk_integrity_iter *iter) |
552 | { | |
553 | return 0; | |
554 | } | |
555 | ||
556 | static int nvme_noop_generate(struct blk_integrity_iter *iter) | |
557 | { | |
558 | return 0; | |
559 | } | |
560 | ||
561 | struct blk_integrity nvme_meta_noop = { | |
562 | .name = "NVME_META_NOOP", | |
563 | .generate_fn = nvme_noop_generate, | |
564 | .verify_fn = nvme_noop_verify, | |
565 | }; | |
566 | ||
567 | static void nvme_init_integrity(struct nvme_ns *ns) | |
568 | { | |
569 | struct blk_integrity integrity; | |
570 | ||
571 | switch (ns->pi_type) { | |
572 | case NVME_NS_DPS_PI_TYPE3: | |
573 | integrity = t10_pi_type3_crc; | |
574 | break; | |
575 | case NVME_NS_DPS_PI_TYPE1: | |
576 | case NVME_NS_DPS_PI_TYPE2: | |
577 | integrity = t10_pi_type1_crc; | |
578 | break; | |
579 | default: | |
580 | integrity = nvme_meta_noop; | |
581 | break; | |
582 | } | |
583 | integrity.tuple_size = ns->ms; | |
584 | blk_integrity_register(ns->disk, &integrity); | |
585 | blk_queue_max_integrity_segments(ns->queue, 1); | |
586 | } | |
587 | #else /* CONFIG_BLK_DEV_INTEGRITY */ | |
588 | static void nvme_dif_remap(struct request *req, | |
589 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
590 | { | |
591 | } | |
592 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
593 | { | |
594 | } | |
595 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
596 | { | |
597 | } | |
598 | static void nvme_init_integrity(struct nvme_ns *ns) | |
599 | { | |
600 | } | |
601 | #endif | |
602 | ||
a4aea562 | 603 | static void req_completion(struct nvme_queue *nvmeq, void *ctx, |
b60503ba MW |
604 | struct nvme_completion *cqe) |
605 | { | |
eca18b23 | 606 | struct nvme_iod *iod = ctx; |
ac3dd5bd | 607 | struct request *req = iod_get_private(iod); |
a4aea562 MB |
608 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
609 | ||
b60503ba MW |
610 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
611 | ||
edd10d33 | 612 | if (unlikely(status)) { |
a4aea562 MB |
613 | if (!(status & NVME_SC_DNR || blk_noretry_request(req)) |
614 | && (jiffies - req->start_time) < req->timeout) { | |
c9d3bf88 KB |
615 | unsigned long flags; |
616 | ||
a4aea562 | 617 | blk_mq_requeue_request(req); |
c9d3bf88 KB |
618 | spin_lock_irqsave(req->q->queue_lock, flags); |
619 | if (!blk_queue_stopped(req->q)) | |
620 | blk_mq_kick_requeue_list(req->q); | |
621 | spin_unlock_irqrestore(req->q->queue_lock, flags); | |
edd10d33 KB |
622 | return; |
623 | } | |
d29ec824 | 624 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { |
17188bb4 KB |
625 | if (cmd_rq->ctx == CMD_CTX_CANCELLED) |
626 | req->errors = -EINTR; | |
627 | else | |
628 | req->errors = status; | |
d29ec824 CH |
629 | } else { |
630 | req->errors = nvme_error_status(status); | |
631 | } | |
a4aea562 MB |
632 | } else |
633 | req->errors = 0; | |
a0a931d6 KB |
634 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { |
635 | u32 result = le32_to_cpup(&cqe->result); | |
636 | req->special = (void *)(uintptr_t)result; | |
637 | } | |
a4aea562 MB |
638 | |
639 | if (cmd_rq->aborted) | |
e75ec752 | 640 | dev_warn(nvmeq->dev->dev, |
a4aea562 MB |
641 | "completing aborted command with status:%04x\n", |
642 | status); | |
643 | ||
e1e5e564 | 644 | if (iod->nents) { |
e75ec752 | 645 | dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents, |
a4aea562 | 646 | rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
e1e5e564 KB |
647 | if (blk_integrity_rq(req)) { |
648 | if (!rq_data_dir(req)) | |
649 | nvme_dif_remap(req, nvme_dif_complete); | |
e75ec752 | 650 | dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1, |
e1e5e564 KB |
651 | rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
652 | } | |
653 | } | |
edd10d33 | 654 | nvme_free_iod(nvmeq->dev, iod); |
3291fa57 | 655 | |
a4aea562 | 656 | blk_mq_complete_request(req); |
b60503ba MW |
657 | } |
658 | ||
184d2944 | 659 | /* length is in bytes. gfp flags indicates whether we may sleep. */ |
d29ec824 CH |
660 | static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, |
661 | int total_len, gfp_t gfp) | |
ff22b54f | 662 | { |
99802a7a | 663 | struct dma_pool *pool; |
eca18b23 MW |
664 | int length = total_len; |
665 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
666 | int dma_len = sg_dma_len(sg); |
667 | u64 dma_addr = sg_dma_address(sg); | |
f137e0f1 MI |
668 | u32 page_size = dev->page_size; |
669 | int offset = dma_addr & (page_size - 1); | |
e025344c | 670 | __le64 *prp_list; |
eca18b23 | 671 | __le64 **list = iod_list(iod); |
e025344c | 672 | dma_addr_t prp_dma; |
eca18b23 | 673 | int nprps, i; |
ff22b54f | 674 | |
1d090624 | 675 | length -= (page_size - offset); |
ff22b54f | 676 | if (length <= 0) |
eca18b23 | 677 | return total_len; |
ff22b54f | 678 | |
1d090624 | 679 | dma_len -= (page_size - offset); |
ff22b54f | 680 | if (dma_len) { |
1d090624 | 681 | dma_addr += (page_size - offset); |
ff22b54f MW |
682 | } else { |
683 | sg = sg_next(sg); | |
684 | dma_addr = sg_dma_address(sg); | |
685 | dma_len = sg_dma_len(sg); | |
686 | } | |
687 | ||
1d090624 | 688 | if (length <= page_size) { |
edd10d33 | 689 | iod->first_dma = dma_addr; |
eca18b23 | 690 | return total_len; |
e025344c SMM |
691 | } |
692 | ||
1d090624 | 693 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
694 | if (nprps <= (256 / 8)) { |
695 | pool = dev->prp_small_pool; | |
eca18b23 | 696 | iod->npages = 0; |
99802a7a MW |
697 | } else { |
698 | pool = dev->prp_page_pool; | |
eca18b23 | 699 | iod->npages = 1; |
99802a7a MW |
700 | } |
701 | ||
b77954cb MW |
702 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
703 | if (!prp_list) { | |
edd10d33 | 704 | iod->first_dma = dma_addr; |
eca18b23 | 705 | iod->npages = -1; |
1d090624 | 706 | return (total_len - length) + page_size; |
b77954cb | 707 | } |
eca18b23 MW |
708 | list[0] = prp_list; |
709 | iod->first_dma = prp_dma; | |
e025344c SMM |
710 | i = 0; |
711 | for (;;) { | |
1d090624 | 712 | if (i == page_size >> 3) { |
e025344c | 713 | __le64 *old_prp_list = prp_list; |
b77954cb | 714 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
eca18b23 MW |
715 | if (!prp_list) |
716 | return total_len - length; | |
717 | list[iod->npages++] = prp_list; | |
7523d834 MW |
718 | prp_list[0] = old_prp_list[i - 1]; |
719 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
720 | i = 1; | |
e025344c SMM |
721 | } |
722 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
723 | dma_len -= page_size; |
724 | dma_addr += page_size; | |
725 | length -= page_size; | |
e025344c SMM |
726 | if (length <= 0) |
727 | break; | |
728 | if (dma_len > 0) | |
729 | continue; | |
730 | BUG_ON(dma_len < 0); | |
731 | sg = sg_next(sg); | |
732 | dma_addr = sg_dma_address(sg); | |
733 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
734 | } |
735 | ||
eca18b23 | 736 | return total_len; |
ff22b54f MW |
737 | } |
738 | ||
d29ec824 CH |
739 | static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req, |
740 | struct nvme_iod *iod) | |
741 | { | |
498c4394 | 742 | struct nvme_command cmnd; |
d29ec824 | 743 | |
498c4394 JD |
744 | memcpy(&cmnd, req->cmd, sizeof(cmnd)); |
745 | cmnd.rw.command_id = req->tag; | |
d29ec824 | 746 | if (req->nr_phys_segments) { |
498c4394 JD |
747 | cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
748 | cmnd.rw.prp2 = cpu_to_le64(iod->first_dma); | |
d29ec824 CH |
749 | } |
750 | ||
498c4394 | 751 | __nvme_submit_cmd(nvmeq, &cmnd); |
d29ec824 CH |
752 | } |
753 | ||
a4aea562 MB |
754 | /* |
755 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
756 | * worth having a special pool for these or additional cases to handle freeing | |
757 | * the iod. | |
758 | */ | |
759 | static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, | |
760 | struct request *req, struct nvme_iod *iod) | |
0e5e4f0e | 761 | { |
edd10d33 KB |
762 | struct nvme_dsm_range *range = |
763 | (struct nvme_dsm_range *)iod_list(iod)[0]; | |
498c4394 | 764 | struct nvme_command cmnd; |
0e5e4f0e | 765 | |
0e5e4f0e | 766 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
767 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
768 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e | 769 | |
498c4394 JD |
770 | memset(&cmnd, 0, sizeof(cmnd)); |
771 | cmnd.dsm.opcode = nvme_cmd_dsm; | |
772 | cmnd.dsm.command_id = req->tag; | |
773 | cmnd.dsm.nsid = cpu_to_le32(ns->ns_id); | |
774 | cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma); | |
775 | cmnd.dsm.nr = 0; | |
776 | cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
0e5e4f0e | 777 | |
498c4394 | 778 | __nvme_submit_cmd(nvmeq, &cmnd); |
0e5e4f0e KB |
779 | } |
780 | ||
a4aea562 | 781 | static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
00df5cb4 MW |
782 | int cmdid) |
783 | { | |
498c4394 | 784 | struct nvme_command cmnd; |
00df5cb4 | 785 | |
498c4394 JD |
786 | memset(&cmnd, 0, sizeof(cmnd)); |
787 | cmnd.common.opcode = nvme_cmd_flush; | |
788 | cmnd.common.command_id = cmdid; | |
789 | cmnd.common.nsid = cpu_to_le32(ns->ns_id); | |
00df5cb4 | 790 | |
498c4394 | 791 | __nvme_submit_cmd(nvmeq, &cmnd); |
00df5cb4 MW |
792 | } |
793 | ||
a4aea562 MB |
794 | static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod, |
795 | struct nvme_ns *ns) | |
b60503ba | 796 | { |
ac3dd5bd | 797 | struct request *req = iod_get_private(iod); |
498c4394 | 798 | struct nvme_command cmnd; |
a4aea562 MB |
799 | u16 control = 0; |
800 | u32 dsmgmt = 0; | |
00df5cb4 | 801 | |
a4aea562 | 802 | if (req->cmd_flags & REQ_FUA) |
b60503ba | 803 | control |= NVME_RW_FUA; |
a4aea562 | 804 | if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD)) |
b60503ba MW |
805 | control |= NVME_RW_LR; |
806 | ||
a4aea562 | 807 | if (req->cmd_flags & REQ_RAHEAD) |
b60503ba MW |
808 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; |
809 | ||
498c4394 JD |
810 | memset(&cmnd, 0, sizeof(cmnd)); |
811 | cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read); | |
812 | cmnd.rw.command_id = req->tag; | |
813 | cmnd.rw.nsid = cpu_to_le32(ns->ns_id); | |
814 | cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); | |
815 | cmnd.rw.prp2 = cpu_to_le64(iod->first_dma); | |
816 | cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
817 | cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1); | |
e1e5e564 KB |
818 | |
819 | if (blk_integrity_rq(req)) { | |
498c4394 | 820 | cmnd.rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg)); |
e1e5e564 KB |
821 | switch (ns->pi_type) { |
822 | case NVME_NS_DPS_PI_TYPE3: | |
823 | control |= NVME_RW_PRINFO_PRCHK_GUARD; | |
824 | break; | |
825 | case NVME_NS_DPS_PI_TYPE1: | |
826 | case NVME_NS_DPS_PI_TYPE2: | |
827 | control |= NVME_RW_PRINFO_PRCHK_GUARD | | |
828 | NVME_RW_PRINFO_PRCHK_REF; | |
498c4394 | 829 | cmnd.rw.reftag = cpu_to_le32( |
e1e5e564 KB |
830 | nvme_block_nr(ns, blk_rq_pos(req))); |
831 | break; | |
832 | } | |
833 | } else if (ns->ms) | |
834 | control |= NVME_RW_PRINFO_PRACT; | |
835 | ||
498c4394 JD |
836 | cmnd.rw.control = cpu_to_le16(control); |
837 | cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba | 838 | |
498c4394 | 839 | __nvme_submit_cmd(nvmeq, &cmnd); |
b60503ba | 840 | |
1974b1ae | 841 | return 0; |
edd10d33 KB |
842 | } |
843 | ||
d29ec824 CH |
844 | /* |
845 | * NOTE: ns is NULL when called on the admin queue. | |
846 | */ | |
a4aea562 MB |
847 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
848 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 849 | { |
a4aea562 MB |
850 | struct nvme_ns *ns = hctx->queue->queuedata; |
851 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 852 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
853 | struct request *req = bd->rq; |
854 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
edd10d33 | 855 | struct nvme_iod *iod; |
a4aea562 | 856 | enum dma_data_direction dma_dir; |
edd10d33 | 857 | |
e1e5e564 KB |
858 | /* |
859 | * If formated with metadata, require the block layer provide a buffer | |
860 | * unless this namespace is formated such that the metadata can be | |
861 | * stripped/generated by the controller with PRACT=1. | |
862 | */ | |
d29ec824 | 863 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
864 | if (!(ns->pi_type && ns->ms == 8) && |
865 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
e1e5e564 KB |
866 | req->errors = -EFAULT; |
867 | blk_mq_complete_request(req); | |
868 | return BLK_MQ_RQ_QUEUE_OK; | |
869 | } | |
870 | } | |
871 | ||
d29ec824 | 872 | iod = nvme_alloc_iod(req, dev, GFP_ATOMIC); |
edd10d33 | 873 | if (!iod) |
fe54303e | 874 | return BLK_MQ_RQ_QUEUE_BUSY; |
a4aea562 | 875 | |
a4aea562 | 876 | if (req->cmd_flags & REQ_DISCARD) { |
edd10d33 KB |
877 | void *range; |
878 | /* | |
879 | * We reuse the small pool to allocate the 16-byte range here | |
880 | * as it is not worth having a special pool for these or | |
881 | * additional cases to handle freeing the iod. | |
882 | */ | |
d29ec824 | 883 | range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC, |
edd10d33 | 884 | &iod->first_dma); |
a4aea562 | 885 | if (!range) |
fe54303e | 886 | goto retry_cmd; |
edd10d33 KB |
887 | iod_list(iod)[0] = (__le64 *)range; |
888 | iod->npages = 0; | |
ac3dd5bd | 889 | } else if (req->nr_phys_segments) { |
a4aea562 MB |
890 | dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE; |
891 | ||
ac3dd5bd | 892 | sg_init_table(iod->sg, req->nr_phys_segments); |
a4aea562 | 893 | iod->nents = blk_rq_map_sg(req->q, req, iod->sg); |
fe54303e JA |
894 | if (!iod->nents) |
895 | goto error_cmd; | |
a4aea562 MB |
896 | |
897 | if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir)) | |
fe54303e | 898 | goto retry_cmd; |
a4aea562 | 899 | |
fe54303e | 900 | if (blk_rq_bytes(req) != |
d29ec824 CH |
901 | nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) { |
902 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
fe54303e JA |
903 | goto retry_cmd; |
904 | } | |
e1e5e564 KB |
905 | if (blk_integrity_rq(req)) { |
906 | if (blk_rq_count_integrity_sg(req->q, req->bio) != 1) | |
907 | goto error_cmd; | |
908 | ||
909 | sg_init_table(iod->meta_sg, 1); | |
910 | if (blk_rq_map_integrity_sg( | |
911 | req->q, req->bio, iod->meta_sg) != 1) | |
912 | goto error_cmd; | |
913 | ||
914 | if (rq_data_dir(req)) | |
915 | nvme_dif_remap(req, nvme_dif_prep); | |
916 | ||
917 | if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir)) | |
918 | goto error_cmd; | |
919 | } | |
edd10d33 | 920 | } |
1974b1ae | 921 | |
9af8785a | 922 | nvme_set_info(cmd, iod, req_completion); |
a4aea562 | 923 | spin_lock_irq(&nvmeq->q_lock); |
d29ec824 CH |
924 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) |
925 | nvme_submit_priv(nvmeq, req, iod); | |
926 | else if (req->cmd_flags & REQ_DISCARD) | |
a4aea562 MB |
927 | nvme_submit_discard(nvmeq, ns, req, iod); |
928 | else if (req->cmd_flags & REQ_FLUSH) | |
929 | nvme_submit_flush(nvmeq, ns, req->tag); | |
930 | else | |
931 | nvme_submit_iod(nvmeq, iod, ns); | |
932 | ||
933 | nvme_process_cq(nvmeq); | |
934 | spin_unlock_irq(&nvmeq->q_lock); | |
935 | return BLK_MQ_RQ_QUEUE_OK; | |
936 | ||
fe54303e | 937 | error_cmd: |
d29ec824 | 938 | nvme_free_iod(dev, iod); |
fe54303e JA |
939 | return BLK_MQ_RQ_QUEUE_ERROR; |
940 | retry_cmd: | |
d29ec824 | 941 | nvme_free_iod(dev, iod); |
fe54303e | 942 | return BLK_MQ_RQ_QUEUE_BUSY; |
b60503ba MW |
943 | } |
944 | ||
e9539f47 | 945 | static int nvme_process_cq(struct nvme_queue *nvmeq) |
b60503ba | 946 | { |
82123460 | 947 | u16 head, phase; |
b60503ba | 948 | |
b60503ba | 949 | head = nvmeq->cq_head; |
82123460 | 950 | phase = nvmeq->cq_phase; |
b60503ba MW |
951 | |
952 | for (;;) { | |
c2f5b650 MW |
953 | void *ctx; |
954 | nvme_completion_fn fn; | |
b60503ba | 955 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 956 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
957 | break; |
958 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
959 | if (++head == nvmeq->q_depth) { | |
960 | head = 0; | |
82123460 | 961 | phase = !phase; |
b60503ba | 962 | } |
a4aea562 | 963 | ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn); |
edd10d33 | 964 | fn(nvmeq, ctx, &cqe); |
b60503ba MW |
965 | } |
966 | ||
967 | /* If the controller ignores the cq head doorbell and continuously | |
968 | * writes to the queue, it is theoretically possible to wrap around | |
969 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
970 | * requires that 0.1% of your interrupts are handled, so this isn't | |
971 | * a big problem. | |
972 | */ | |
82123460 | 973 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
e9539f47 | 974 | return 0; |
b60503ba | 975 | |
b80d5ccc | 976 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); |
b60503ba | 977 | nvmeq->cq_head = head; |
82123460 | 978 | nvmeq->cq_phase = phase; |
b60503ba | 979 | |
e9539f47 MW |
980 | nvmeq->cqe_seen = 1; |
981 | return 1; | |
b60503ba MW |
982 | } |
983 | ||
984 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
985 | { |
986 | irqreturn_t result; | |
987 | struct nvme_queue *nvmeq = data; | |
988 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
989 | nvme_process_cq(nvmeq); |
990 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
991 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
992 | spin_unlock(&nvmeq->q_lock); |
993 | return result; | |
994 | } | |
995 | ||
996 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
997 | { | |
998 | struct nvme_queue *nvmeq = data; | |
999 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
1000 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
1001 | return IRQ_NONE; | |
1002 | return IRQ_WAKE_THREAD; | |
1003 | } | |
1004 | ||
b60503ba MW |
1005 | /* |
1006 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
1007 | * if the result is positive, it's an NVM Express status code | |
1008 | */ | |
d29ec824 CH |
1009 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
1010 | void *buffer, void __user *ubuffer, unsigned bufflen, | |
1011 | u32 *result, unsigned timeout) | |
b60503ba | 1012 | { |
d29ec824 CH |
1013 | bool write = cmd->common.opcode & 1; |
1014 | struct bio *bio = NULL; | |
f705f837 | 1015 | struct request *req; |
d29ec824 | 1016 | int ret; |
b60503ba | 1017 | |
d29ec824 | 1018 | req = blk_mq_alloc_request(q, write, GFP_KERNEL, false); |
f705f837 CH |
1019 | if (IS_ERR(req)) |
1020 | return PTR_ERR(req); | |
b60503ba | 1021 | |
d29ec824 | 1022 | req->cmd_type = REQ_TYPE_DRV_PRIV; |
e112af0d | 1023 | req->cmd_flags |= REQ_FAILFAST_DRIVER; |
d29ec824 CH |
1024 | req->__data_len = 0; |
1025 | req->__sector = (sector_t) -1; | |
1026 | req->bio = req->biotail = NULL; | |
b60503ba | 1027 | |
f4ff414a | 1028 | req->timeout = timeout ? timeout : ADMIN_TIMEOUT; |
a4aea562 | 1029 | |
d29ec824 CH |
1030 | req->cmd = (unsigned char *)cmd; |
1031 | req->cmd_len = sizeof(struct nvme_command); | |
a0a931d6 | 1032 | req->special = (void *)0; |
b60503ba | 1033 | |
d29ec824 CH |
1034 | if (buffer && bufflen) { |
1035 | ret = blk_rq_map_kern(q, req, buffer, bufflen, __GFP_WAIT); | |
1036 | if (ret) | |
1037 | goto out; | |
1038 | } else if (ubuffer && bufflen) { | |
1039 | ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen, __GFP_WAIT); | |
1040 | if (ret) | |
1041 | goto out; | |
1042 | bio = req->bio; | |
1043 | } | |
3c0cf138 | 1044 | |
d29ec824 CH |
1045 | blk_execute_rq(req->q, NULL, req, 0); |
1046 | if (bio) | |
1047 | blk_rq_unmap_user(bio); | |
b60503ba | 1048 | if (result) |
a0a931d6 | 1049 | *result = (u32)(uintptr_t)req->special; |
d29ec824 CH |
1050 | ret = req->errors; |
1051 | out: | |
f705f837 | 1052 | blk_mq_free_request(req); |
d29ec824 | 1053 | return ret; |
f705f837 CH |
1054 | } |
1055 | ||
d29ec824 CH |
1056 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
1057 | void *buffer, unsigned bufflen) | |
f705f837 | 1058 | { |
d29ec824 | 1059 | return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0); |
b60503ba MW |
1060 | } |
1061 | ||
a4aea562 MB |
1062 | static int nvme_submit_async_admin_req(struct nvme_dev *dev) |
1063 | { | |
1064 | struct nvme_queue *nvmeq = dev->queues[0]; | |
1065 | struct nvme_command c; | |
1066 | struct nvme_cmd_info *cmd_info; | |
1067 | struct request *req; | |
1068 | ||
1efccc9d | 1069 | req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true); |
9f173b33 DC |
1070 | if (IS_ERR(req)) |
1071 | return PTR_ERR(req); | |
a4aea562 | 1072 | |
c917dfe5 | 1073 | req->cmd_flags |= REQ_NO_TIMEOUT; |
a4aea562 | 1074 | cmd_info = blk_mq_rq_to_pdu(req); |
1efccc9d | 1075 | nvme_set_info(cmd_info, NULL, async_req_completion); |
a4aea562 MB |
1076 | |
1077 | memset(&c, 0, sizeof(c)); | |
1078 | c.common.opcode = nvme_admin_async_event; | |
1079 | c.common.command_id = req->tag; | |
1080 | ||
42483228 | 1081 | blk_mq_free_request(req); |
a4aea562 MB |
1082 | return __nvme_submit_cmd(nvmeq, &c); |
1083 | } | |
1084 | ||
1085 | static int nvme_submit_admin_async_cmd(struct nvme_dev *dev, | |
4d115420 KB |
1086 | struct nvme_command *cmd, |
1087 | struct async_cmd_info *cmdinfo, unsigned timeout) | |
1088 | { | |
a4aea562 MB |
1089 | struct nvme_queue *nvmeq = dev->queues[0]; |
1090 | struct request *req; | |
1091 | struct nvme_cmd_info *cmd_rq; | |
4d115420 | 1092 | |
a4aea562 | 1093 | req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false); |
9f173b33 DC |
1094 | if (IS_ERR(req)) |
1095 | return PTR_ERR(req); | |
a4aea562 MB |
1096 | |
1097 | req->timeout = timeout; | |
1098 | cmd_rq = blk_mq_rq_to_pdu(req); | |
1099 | cmdinfo->req = req; | |
1100 | nvme_set_info(cmd_rq, cmdinfo, async_completion); | |
4d115420 | 1101 | cmdinfo->status = -EINTR; |
a4aea562 MB |
1102 | |
1103 | cmd->common.command_id = req->tag; | |
1104 | ||
4f5099af | 1105 | return nvme_submit_cmd(nvmeq, cmd); |
4d115420 KB |
1106 | } |
1107 | ||
b60503ba MW |
1108 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
1109 | { | |
b60503ba MW |
1110 | struct nvme_command c; |
1111 | ||
1112 | memset(&c, 0, sizeof(c)); | |
1113 | c.delete_queue.opcode = opcode; | |
1114 | c.delete_queue.qid = cpu_to_le16(id); | |
1115 | ||
d29ec824 | 1116 | return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0); |
b60503ba MW |
1117 | } |
1118 | ||
1119 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
1120 | struct nvme_queue *nvmeq) | |
1121 | { | |
b60503ba MW |
1122 | struct nvme_command c; |
1123 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
1124 | ||
d29ec824 CH |
1125 | /* |
1126 | * Note: we (ab)use the fact the the prp fields survive if no data | |
1127 | * is attached to the request. | |
1128 | */ | |
b60503ba MW |
1129 | memset(&c, 0, sizeof(c)); |
1130 | c.create_cq.opcode = nvme_admin_create_cq; | |
1131 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1132 | c.create_cq.cqid = cpu_to_le16(qid); | |
1133 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1134 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
1135 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
1136 | ||
d29ec824 | 1137 | return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0); |
b60503ba MW |
1138 | } |
1139 | ||
1140 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1141 | struct nvme_queue *nvmeq) | |
1142 | { | |
b60503ba MW |
1143 | struct nvme_command c; |
1144 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
1145 | ||
d29ec824 CH |
1146 | /* |
1147 | * Note: we (ab)use the fact the the prp fields survive if no data | |
1148 | * is attached to the request. | |
1149 | */ | |
b60503ba MW |
1150 | memset(&c, 0, sizeof(c)); |
1151 | c.create_sq.opcode = nvme_admin_create_sq; | |
1152 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1153 | c.create_sq.sqid = cpu_to_le16(qid); | |
1154 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1155 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1156 | c.create_sq.cqid = cpu_to_le16(qid); | |
1157 | ||
d29ec824 | 1158 | return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0); |
b60503ba MW |
1159 | } |
1160 | ||
1161 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1162 | { | |
1163 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1164 | } | |
1165 | ||
1166 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1167 | { | |
1168 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1169 | } | |
1170 | ||
d29ec824 | 1171 | int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id) |
bc5fc7e4 | 1172 | { |
e44ac588 | 1173 | struct nvme_command c = { }; |
d29ec824 | 1174 | int error; |
bc5fc7e4 | 1175 | |
e44ac588 AM |
1176 | /* gcc-4.4.4 (at least) has issues with initializers and anon unions */ |
1177 | c.identify.opcode = nvme_admin_identify; | |
1178 | c.identify.cns = cpu_to_le32(1); | |
1179 | ||
d29ec824 CH |
1180 | *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL); |
1181 | if (!*id) | |
1182 | return -ENOMEM; | |
bc5fc7e4 | 1183 | |
d29ec824 CH |
1184 | error = nvme_submit_sync_cmd(dev->admin_q, &c, *id, |
1185 | sizeof(struct nvme_id_ctrl)); | |
1186 | if (error) | |
1187 | kfree(*id); | |
1188 | return error; | |
1189 | } | |
1190 | ||
1191 | int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid, | |
1192 | struct nvme_id_ns **id) | |
1193 | { | |
e44ac588 | 1194 | struct nvme_command c = { }; |
d29ec824 | 1195 | int error; |
bc5fc7e4 | 1196 | |
e44ac588 AM |
1197 | /* gcc-4.4.4 (at least) has issues with initializers and anon unions */ |
1198 | c.identify.opcode = nvme_admin_identify, | |
1199 | c.identify.nsid = cpu_to_le32(nsid), | |
1200 | ||
d29ec824 CH |
1201 | *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL); |
1202 | if (!*id) | |
1203 | return -ENOMEM; | |
1204 | ||
1205 | error = nvme_submit_sync_cmd(dev->admin_q, &c, *id, | |
1206 | sizeof(struct nvme_id_ns)); | |
1207 | if (error) | |
1208 | kfree(*id); | |
1209 | return error; | |
bc5fc7e4 MW |
1210 | } |
1211 | ||
5d0f6131 | 1212 | int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, |
08df1e05 | 1213 | dma_addr_t dma_addr, u32 *result) |
bc5fc7e4 MW |
1214 | { |
1215 | struct nvme_command c; | |
1216 | ||
1217 | memset(&c, 0, sizeof(c)); | |
1218 | c.features.opcode = nvme_admin_get_features; | |
a42cecce | 1219 | c.features.nsid = cpu_to_le32(nsid); |
bc5fc7e4 MW |
1220 | c.features.prp1 = cpu_to_le64(dma_addr); |
1221 | c.features.fid = cpu_to_le32(fid); | |
bc5fc7e4 | 1222 | |
d29ec824 CH |
1223 | return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0, |
1224 | result, 0); | |
df348139 MW |
1225 | } |
1226 | ||
5d0f6131 VV |
1227 | int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, |
1228 | dma_addr_t dma_addr, u32 *result) | |
df348139 MW |
1229 | { |
1230 | struct nvme_command c; | |
1231 | ||
1232 | memset(&c, 0, sizeof(c)); | |
1233 | c.features.opcode = nvme_admin_set_features; | |
1234 | c.features.prp1 = cpu_to_le64(dma_addr); | |
1235 | c.features.fid = cpu_to_le32(fid); | |
1236 | c.features.dword11 = cpu_to_le32(dword11); | |
1237 | ||
d29ec824 CH |
1238 | return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0, |
1239 | result, 0); | |
1240 | } | |
1241 | ||
1242 | int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log) | |
1243 | { | |
e44ac588 AM |
1244 | struct nvme_command c = { }; |
1245 | int error; | |
1246 | ||
1247 | c.common.opcode = nvme_admin_get_log_page, | |
1248 | c.common.nsid = cpu_to_le32(0xFFFFFFFF), | |
1249 | c.common.cdw10[0] = cpu_to_le32( | |
d29ec824 CH |
1250 | (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) | |
1251 | NVME_LOG_SMART), | |
d29ec824 CH |
1252 | |
1253 | *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL); | |
1254 | if (!*log) | |
1255 | return -ENOMEM; | |
1256 | ||
1257 | error = nvme_submit_sync_cmd(dev->admin_q, &c, *log, | |
1258 | sizeof(struct nvme_smart_log)); | |
1259 | if (error) | |
1260 | kfree(*log); | |
1261 | return error; | |
bc5fc7e4 MW |
1262 | } |
1263 | ||
c30341dc | 1264 | /** |
a4aea562 | 1265 | * nvme_abort_req - Attempt aborting a request |
c30341dc KB |
1266 | * |
1267 | * Schedule controller reset if the command was already aborted once before and | |
1268 | * still hasn't been returned to the driver, or if this is the admin queue. | |
1269 | */ | |
a4aea562 | 1270 | static void nvme_abort_req(struct request *req) |
c30341dc | 1271 | { |
a4aea562 MB |
1272 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
1273 | struct nvme_queue *nvmeq = cmd_rq->nvmeq; | |
c30341dc | 1274 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
1275 | struct request *abort_req; |
1276 | struct nvme_cmd_info *abort_cmd; | |
1277 | struct nvme_command cmd; | |
c30341dc | 1278 | |
a4aea562 | 1279 | if (!nvmeq->qid || cmd_rq->aborted) { |
7a509a6b KB |
1280 | unsigned long flags; |
1281 | ||
1282 | spin_lock_irqsave(&dev_list_lock, flags); | |
c30341dc | 1283 | if (work_busy(&dev->reset_work)) |
7a509a6b | 1284 | goto out; |
c30341dc | 1285 | list_del_init(&dev->node); |
e75ec752 | 1286 | dev_warn(dev->dev, "I/O %d QID %d timeout, reset controller\n", |
a4aea562 | 1287 | req->tag, nvmeq->qid); |
9ca97374 | 1288 | dev->reset_workfn = nvme_reset_failed_dev; |
c30341dc | 1289 | queue_work(nvme_workq, &dev->reset_work); |
7a509a6b KB |
1290 | out: |
1291 | spin_unlock_irqrestore(&dev_list_lock, flags); | |
c30341dc KB |
1292 | return; |
1293 | } | |
1294 | ||
1295 | if (!dev->abort_limit) | |
1296 | return; | |
1297 | ||
a4aea562 MB |
1298 | abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, |
1299 | false); | |
9f173b33 | 1300 | if (IS_ERR(abort_req)) |
c30341dc KB |
1301 | return; |
1302 | ||
a4aea562 MB |
1303 | abort_cmd = blk_mq_rq_to_pdu(abort_req); |
1304 | nvme_set_info(abort_cmd, abort_req, abort_completion); | |
1305 | ||
c30341dc KB |
1306 | memset(&cmd, 0, sizeof(cmd)); |
1307 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1308 | cmd.abort.cid = req->tag; |
c30341dc | 1309 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
a4aea562 | 1310 | cmd.abort.command_id = abort_req->tag; |
c30341dc KB |
1311 | |
1312 | --dev->abort_limit; | |
a4aea562 | 1313 | cmd_rq->aborted = 1; |
c30341dc | 1314 | |
a4aea562 | 1315 | dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag, |
c30341dc | 1316 | nvmeq->qid); |
a4aea562 MB |
1317 | if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) { |
1318 | dev_warn(nvmeq->q_dmadev, | |
1319 | "Could not abort I/O %d QID %d", | |
1320 | req->tag, nvmeq->qid); | |
c87fd540 | 1321 | blk_mq_free_request(abort_req); |
a4aea562 | 1322 | } |
c30341dc KB |
1323 | } |
1324 | ||
42483228 | 1325 | static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) |
a09115b2 | 1326 | { |
a4aea562 MB |
1327 | struct nvme_queue *nvmeq = data; |
1328 | void *ctx; | |
1329 | nvme_completion_fn fn; | |
1330 | struct nvme_cmd_info *cmd; | |
cef6a948 KB |
1331 | struct nvme_completion cqe; |
1332 | ||
1333 | if (!blk_mq_request_started(req)) | |
1334 | return; | |
a09115b2 | 1335 | |
a4aea562 | 1336 | cmd = blk_mq_rq_to_pdu(req); |
a09115b2 | 1337 | |
a4aea562 MB |
1338 | if (cmd->ctx == CMD_CTX_CANCELLED) |
1339 | return; | |
1340 | ||
cef6a948 KB |
1341 | if (blk_queue_dying(req->q)) |
1342 | cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1); | |
1343 | else | |
1344 | cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1); | |
1345 | ||
1346 | ||
a4aea562 MB |
1347 | dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", |
1348 | req->tag, nvmeq->qid); | |
1349 | ctx = cancel_cmd_info(cmd, &fn); | |
1350 | fn(nvmeq, ctx, &cqe); | |
a09115b2 MW |
1351 | } |
1352 | ||
a4aea562 | 1353 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
9e866774 | 1354 | { |
a4aea562 MB |
1355 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); |
1356 | struct nvme_queue *nvmeq = cmd->nvmeq; | |
1357 | ||
1358 | dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag, | |
1359 | nvmeq->qid); | |
7a509a6b | 1360 | spin_lock_irq(&nvmeq->q_lock); |
07836e65 | 1361 | nvme_abort_req(req); |
7a509a6b | 1362 | spin_unlock_irq(&nvmeq->q_lock); |
a4aea562 | 1363 | |
07836e65 KB |
1364 | /* |
1365 | * The aborted req will be completed on receiving the abort req. | |
1366 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1367 | * as the device then is in a faulty state. | |
1368 | */ | |
1369 | return BLK_EH_RESET_TIMER; | |
a4aea562 | 1370 | } |
22404274 | 1371 | |
a4aea562 MB |
1372 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1373 | { | |
9e866774 MW |
1374 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1375 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1376 | if (nvmeq->sq_cmds) |
1377 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1378 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1379 | kfree(nvmeq); | |
1380 | } | |
1381 | ||
a1a5ef99 | 1382 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1383 | { |
1384 | int i; | |
1385 | ||
a1a5ef99 | 1386 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1387 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1388 | dev->queue_count--; |
a4aea562 | 1389 | dev->queues[i] = NULL; |
f435c282 | 1390 | nvme_free_queue(nvmeq); |
121c7ad4 | 1391 | } |
22404274 KB |
1392 | } |
1393 | ||
4d115420 KB |
1394 | /** |
1395 | * nvme_suspend_queue - put queue into suspended state | |
1396 | * @nvmeq - queue to suspend | |
4d115420 KB |
1397 | */ |
1398 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1399 | { |
2b25d981 | 1400 | int vector; |
b60503ba | 1401 | |
a09115b2 | 1402 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1403 | if (nvmeq->cq_vector == -1) { |
1404 | spin_unlock_irq(&nvmeq->q_lock); | |
1405 | return 1; | |
1406 | } | |
1407 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1408 | nvmeq->dev->online_queues--; |
2b25d981 | 1409 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1410 | spin_unlock_irq(&nvmeq->q_lock); |
1411 | ||
6df3dbc8 KB |
1412 | if (!nvmeq->qid && nvmeq->dev->admin_q) |
1413 | blk_mq_freeze_queue_start(nvmeq->dev->admin_q); | |
1414 | ||
aba2080f MW |
1415 | irq_set_affinity_hint(vector, NULL); |
1416 | free_irq(vector, nvmeq); | |
b60503ba | 1417 | |
4d115420 KB |
1418 | return 0; |
1419 | } | |
b60503ba | 1420 | |
4d115420 KB |
1421 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1422 | { | |
22404274 | 1423 | spin_lock_irq(&nvmeq->q_lock); |
42483228 KB |
1424 | if (nvmeq->tags && *nvmeq->tags) |
1425 | blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1426 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1427 | } |
1428 | ||
4d115420 KB |
1429 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) |
1430 | { | |
a4aea562 | 1431 | struct nvme_queue *nvmeq = dev->queues[qid]; |
4d115420 KB |
1432 | |
1433 | if (!nvmeq) | |
1434 | return; | |
1435 | if (nvme_suspend_queue(nvmeq)) | |
1436 | return; | |
1437 | ||
0e53d180 KB |
1438 | /* Don't tell the adapter to delete the admin queue. |
1439 | * Don't tell a removed adapter to delete IO queues. */ | |
1440 | if (qid && readl(&dev->bar->csts) != -1) { | |
b60503ba MW |
1441 | adapter_delete_sq(dev, qid); |
1442 | adapter_delete_cq(dev, qid); | |
1443 | } | |
07836e65 KB |
1444 | |
1445 | spin_lock_irq(&nvmeq->q_lock); | |
1446 | nvme_process_cq(nvmeq); | |
1447 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1448 | } |
1449 | ||
8ffaadf7 JD |
1450 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1451 | int entry_size) | |
1452 | { | |
1453 | int q_depth = dev->q_depth; | |
1454 | unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size); | |
1455 | ||
1456 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 JD |
1457 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
1458 | mem_per_q = round_down(mem_per_q, dev->page_size); | |
1459 | q_depth = div_u64(mem_per_q, entry_size); | |
8ffaadf7 JD |
1460 | |
1461 | /* | |
1462 | * Ensure the reduced q_depth is above some threshold where it | |
1463 | * would be better to map queues in system memory with the | |
1464 | * original depth | |
1465 | */ | |
1466 | if (q_depth < 64) | |
1467 | return -ENOMEM; | |
1468 | } | |
1469 | ||
1470 | return q_depth; | |
1471 | } | |
1472 | ||
1473 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1474 | int qid, int depth) | |
1475 | { | |
1476 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
1477 | unsigned offset = (qid - 1) * | |
1478 | roundup(SQ_SIZE(depth), dev->page_size); | |
1479 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; | |
1480 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1481 | } else { | |
1482 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1483 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1484 | if (!nvmeq->sq_cmds) | |
1485 | return -ENOMEM; | |
1486 | } | |
1487 | ||
1488 | return 0; | |
1489 | } | |
1490 | ||
b60503ba | 1491 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1492 | int depth) |
b60503ba | 1493 | { |
a4aea562 | 1494 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1495 | if (!nvmeq) |
1496 | return NULL; | |
1497 | ||
e75ec752 | 1498 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1499 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1500 | if (!nvmeq->cqes) |
1501 | goto free_nvmeq; | |
b60503ba | 1502 | |
8ffaadf7 | 1503 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1504 | goto free_cqdma; |
1505 | ||
e75ec752 | 1506 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1507 | nvmeq->dev = dev; |
3193f07b MW |
1508 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1509 | dev->instance, qid); | |
b60503ba MW |
1510 | spin_lock_init(&nvmeq->q_lock); |
1511 | nvmeq->cq_head = 0; | |
82123460 | 1512 | nvmeq->cq_phase = 1; |
b80d5ccc | 1513 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1514 | nvmeq->q_depth = depth; |
c30341dc | 1515 | nvmeq->qid = qid; |
758dd7fd | 1516 | nvmeq->cq_vector = -1; |
a4aea562 | 1517 | dev->queues[qid] = nvmeq; |
b60503ba | 1518 | |
36a7e993 JD |
1519 | /* make sure queue descriptor is set before queue count, for kthread */ |
1520 | mb(); | |
1521 | dev->queue_count++; | |
1522 | ||
b60503ba MW |
1523 | return nvmeq; |
1524 | ||
1525 | free_cqdma: | |
e75ec752 | 1526 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1527 | nvmeq->cq_dma_addr); |
1528 | free_nvmeq: | |
1529 | kfree(nvmeq); | |
1530 | return NULL; | |
1531 | } | |
1532 | ||
3001082c MW |
1533 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1534 | const char *name) | |
1535 | { | |
58ffacb5 MW |
1536 | if (use_threaded_interrupts) |
1537 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1538 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1539 | name, nvmeq); |
3001082c | 1540 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1541 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1542 | } |
1543 | ||
22404274 | 1544 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1545 | { |
22404274 | 1546 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1547 | |
7be50e93 | 1548 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1549 | nvmeq->sq_tail = 0; |
1550 | nvmeq->cq_head = 0; | |
1551 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1552 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1553 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1554 | dev->online_queues++; |
7be50e93 | 1555 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1556 | } |
1557 | ||
1558 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1559 | { | |
1560 | struct nvme_dev *dev = nvmeq->dev; | |
1561 | int result; | |
3f85d50b | 1562 | |
2b25d981 | 1563 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1564 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1565 | if (result < 0) | |
22404274 | 1566 | return result; |
b60503ba MW |
1567 | |
1568 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1569 | if (result < 0) | |
1570 | goto release_cq; | |
1571 | ||
3193f07b | 1572 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1573 | if (result < 0) |
1574 | goto release_sq; | |
1575 | ||
22404274 | 1576 | nvme_init_queue(nvmeq, qid); |
22404274 | 1577 | return result; |
b60503ba MW |
1578 | |
1579 | release_sq: | |
1580 | adapter_delete_sq(dev, qid); | |
1581 | release_cq: | |
1582 | adapter_delete_cq(dev, qid); | |
22404274 | 1583 | return result; |
b60503ba MW |
1584 | } |
1585 | ||
ba47e386 MW |
1586 | static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled) |
1587 | { | |
1588 | unsigned long timeout; | |
1589 | u32 bit = enabled ? NVME_CSTS_RDY : 0; | |
1590 | ||
1591 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
1592 | ||
1593 | while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) { | |
1594 | msleep(100); | |
1595 | if (fatal_signal_pending(current)) | |
1596 | return -EINTR; | |
1597 | if (time_after(jiffies, timeout)) { | |
e75ec752 | 1598 | dev_err(dev->dev, |
27e8166c MW |
1599 | "Device not ready; aborting %s\n", enabled ? |
1600 | "initialisation" : "reset"); | |
ba47e386 MW |
1601 | return -ENODEV; |
1602 | } | |
1603 | } | |
1604 | ||
1605 | return 0; | |
1606 | } | |
1607 | ||
1608 | /* | |
1609 | * If the device has been passed off to us in an enabled state, just clear | |
1610 | * the enabled bit. The spec says we should set the 'shutdown notification | |
1611 | * bits', but doing so may cause the device to complete commands to the | |
1612 | * admin queue ... and we don't know what memory that might be pointing at! | |
1613 | */ | |
1614 | static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap) | |
1615 | { | |
01079522 DM |
1616 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1617 | dev->ctrl_config &= ~NVME_CC_ENABLE; | |
1618 | writel(dev->ctrl_config, &dev->bar->cc); | |
44af146a | 1619 | |
ba47e386 MW |
1620 | return nvme_wait_ready(dev, cap, false); |
1621 | } | |
1622 | ||
1623 | static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap) | |
1624 | { | |
01079522 DM |
1625 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1626 | dev->ctrl_config |= NVME_CC_ENABLE; | |
1627 | writel(dev->ctrl_config, &dev->bar->cc); | |
1628 | ||
ba47e386 MW |
1629 | return nvme_wait_ready(dev, cap, true); |
1630 | } | |
1631 | ||
1894d8f1 KB |
1632 | static int nvme_shutdown_ctrl(struct nvme_dev *dev) |
1633 | { | |
1634 | unsigned long timeout; | |
1894d8f1 | 1635 | |
01079522 DM |
1636 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1637 | dev->ctrl_config |= NVME_CC_SHN_NORMAL; | |
1638 | ||
1639 | writel(dev->ctrl_config, &dev->bar->cc); | |
1894d8f1 | 1640 | |
2484f407 | 1641 | timeout = SHUTDOWN_TIMEOUT + jiffies; |
1894d8f1 KB |
1642 | while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) != |
1643 | NVME_CSTS_SHST_CMPLT) { | |
1644 | msleep(100); | |
1645 | if (fatal_signal_pending(current)) | |
1646 | return -EINTR; | |
1647 | if (time_after(jiffies, timeout)) { | |
e75ec752 | 1648 | dev_err(dev->dev, |
1894d8f1 KB |
1649 | "Device shutdown incomplete; abort shutdown\n"); |
1650 | return -ENODEV; | |
1651 | } | |
1652 | } | |
1653 | ||
1654 | return 0; | |
1655 | } | |
1656 | ||
a4aea562 | 1657 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1658 | .queue_rq = nvme_queue_rq, |
a4aea562 MB |
1659 | .map_queue = blk_mq_map_queue, |
1660 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1661 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1662 | .init_request = nvme_admin_init_request, |
1663 | .timeout = nvme_timeout, | |
1664 | }; | |
1665 | ||
1666 | static struct blk_mq_ops nvme_mq_ops = { | |
1667 | .queue_rq = nvme_queue_rq, | |
1668 | .map_queue = blk_mq_map_queue, | |
1669 | .init_hctx = nvme_init_hctx, | |
1670 | .init_request = nvme_init_request, | |
1671 | .timeout = nvme_timeout, | |
1672 | }; | |
1673 | ||
ea191d2f KB |
1674 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1675 | { | |
1676 | if (dev->admin_q && !blk_queue_dying(dev->admin_q)) { | |
1677 | blk_cleanup_queue(dev->admin_q); | |
1678 | blk_mq_free_tag_set(&dev->admin_tagset); | |
1679 | } | |
1680 | } | |
1681 | ||
a4aea562 MB |
1682 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1683 | { | |
1684 | if (!dev->admin_q) { | |
1685 | dev->admin_tagset.ops = &nvme_mq_admin_ops; | |
1686 | dev->admin_tagset.nr_hw_queues = 1; | |
1687 | dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1; | |
1efccc9d | 1688 | dev->admin_tagset.reserved_tags = 1; |
a4aea562 | 1689 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1690 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1691 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1692 | dev->admin_tagset.driver_data = dev; |
1693 | ||
1694 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1695 | return -ENOMEM; | |
1696 | ||
1697 | dev->admin_q = blk_mq_init_queue(&dev->admin_tagset); | |
35b489d3 | 1698 | if (IS_ERR(dev->admin_q)) { |
a4aea562 MB |
1699 | blk_mq_free_tag_set(&dev->admin_tagset); |
1700 | return -ENOMEM; | |
1701 | } | |
ea191d2f KB |
1702 | if (!blk_get_queue(dev->admin_q)) { |
1703 | nvme_dev_remove_admin(dev); | |
4af0e21c | 1704 | dev->admin_q = NULL; |
ea191d2f KB |
1705 | return -ENODEV; |
1706 | } | |
0fb59cbc KB |
1707 | } else |
1708 | blk_mq_unfreeze_queue(dev->admin_q); | |
a4aea562 MB |
1709 | |
1710 | return 0; | |
1711 | } | |
1712 | ||
8d85fce7 | 1713 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1714 | { |
ba47e386 | 1715 | int result; |
b60503ba | 1716 | u32 aqa; |
ba47e386 | 1717 | u64 cap = readq(&dev->bar->cap); |
b60503ba | 1718 | struct nvme_queue *nvmeq; |
1d090624 KB |
1719 | unsigned page_shift = PAGE_SHIFT; |
1720 | unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12; | |
1721 | unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12; | |
1722 | ||
1723 | if (page_shift < dev_page_min) { | |
e75ec752 | 1724 | dev_err(dev->dev, |
1d090624 KB |
1725 | "Minimum device page size (%u) too large for " |
1726 | "host (%u)\n", 1 << dev_page_min, | |
1727 | 1 << page_shift); | |
1728 | return -ENODEV; | |
1729 | } | |
1730 | if (page_shift > dev_page_max) { | |
e75ec752 | 1731 | dev_info(dev->dev, |
1d090624 KB |
1732 | "Device maximum page size (%u) smaller than " |
1733 | "host (%u); enabling work-around\n", | |
1734 | 1 << dev_page_max, 1 << page_shift); | |
1735 | page_shift = dev_page_max; | |
1736 | } | |
b60503ba | 1737 | |
dfbac8c7 KB |
1738 | dev->subsystem = readl(&dev->bar->vs) >= NVME_VS(1, 1) ? |
1739 | NVME_CAP_NSSRC(cap) : 0; | |
1740 | ||
1741 | if (dev->subsystem && (readl(&dev->bar->csts) & NVME_CSTS_NSSRO)) | |
1742 | writel(NVME_CSTS_NSSRO, &dev->bar->csts); | |
1743 | ||
ba47e386 MW |
1744 | result = nvme_disable_ctrl(dev, cap); |
1745 | if (result < 0) | |
1746 | return result; | |
b60503ba | 1747 | |
a4aea562 | 1748 | nvmeq = dev->queues[0]; |
cd638946 | 1749 | if (!nvmeq) { |
2b25d981 | 1750 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1751 | if (!nvmeq) |
1752 | return -ENOMEM; | |
cd638946 | 1753 | } |
b60503ba MW |
1754 | |
1755 | aqa = nvmeq->q_depth - 1; | |
1756 | aqa |= aqa << 16; | |
1757 | ||
1d090624 KB |
1758 | dev->page_size = 1 << page_shift; |
1759 | ||
01079522 | 1760 | dev->ctrl_config = NVME_CC_CSS_NVM; |
1d090624 | 1761 | dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT; |
b60503ba | 1762 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; |
7f53f9d2 | 1763 | dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
b60503ba MW |
1764 | |
1765 | writel(aqa, &dev->bar->aqa); | |
1766 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
1767 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
b60503ba | 1768 | |
ba47e386 | 1769 | result = nvme_enable_ctrl(dev, cap); |
025c557a | 1770 | if (result) |
a4aea562 MB |
1771 | goto free_nvmeq; |
1772 | ||
2b25d981 | 1773 | nvmeq->cq_vector = 0; |
3193f07b | 1774 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1775 | if (result) { |
1776 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1777 | goto free_nvmeq; |
758dd7fd | 1778 | } |
025c557a | 1779 | |
b60503ba | 1780 | return result; |
a4aea562 | 1781 | |
a4aea562 MB |
1782 | free_nvmeq: |
1783 | nvme_free_queues(dev, 0); | |
1784 | return result; | |
b60503ba MW |
1785 | } |
1786 | ||
a53295b6 MW |
1787 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
1788 | { | |
1789 | struct nvme_dev *dev = ns->dev; | |
a53295b6 MW |
1790 | struct nvme_user_io io; |
1791 | struct nvme_command c; | |
d29ec824 | 1792 | unsigned length, meta_len; |
a67a9513 | 1793 | int status, write; |
a67a9513 KB |
1794 | dma_addr_t meta_dma = 0; |
1795 | void *meta = NULL; | |
fec558b5 | 1796 | void __user *metadata; |
a53295b6 MW |
1797 | |
1798 | if (copy_from_user(&io, uio, sizeof(io))) | |
1799 | return -EFAULT; | |
6c7d4945 MW |
1800 | |
1801 | switch (io.opcode) { | |
1802 | case nvme_cmd_write: | |
1803 | case nvme_cmd_read: | |
6bbf1acd | 1804 | case nvme_cmd_compare: |
6413214c | 1805 | break; |
6c7d4945 | 1806 | default: |
6bbf1acd | 1807 | return -EINVAL; |
6c7d4945 MW |
1808 | } |
1809 | ||
d29ec824 CH |
1810 | length = (io.nblocks + 1) << ns->lba_shift; |
1811 | meta_len = (io.nblocks + 1) * ns->ms; | |
6a398a3e | 1812 | metadata = (void __user *)(unsigned long)io.metadata; |
d29ec824 | 1813 | write = io.opcode & 1; |
a53295b6 | 1814 | |
71feb364 KB |
1815 | if (ns->ext) { |
1816 | length += meta_len; | |
1817 | meta_len = 0; | |
a67a9513 KB |
1818 | } |
1819 | if (meta_len) { | |
d29ec824 CH |
1820 | if (((io.metadata & 3) || !io.metadata) && !ns->ext) |
1821 | return -EINVAL; | |
1822 | ||
e75ec752 | 1823 | meta = dma_alloc_coherent(dev->dev, meta_len, |
a67a9513 | 1824 | &meta_dma, GFP_KERNEL); |
fec558b5 | 1825 | |
a67a9513 KB |
1826 | if (!meta) { |
1827 | status = -ENOMEM; | |
1828 | goto unmap; | |
1829 | } | |
1830 | if (write) { | |
fec558b5 | 1831 | if (copy_from_user(meta, metadata, meta_len)) { |
a67a9513 KB |
1832 | status = -EFAULT; |
1833 | goto unmap; | |
1834 | } | |
1835 | } | |
1836 | } | |
1837 | ||
a53295b6 MW |
1838 | memset(&c, 0, sizeof(c)); |
1839 | c.rw.opcode = io.opcode; | |
1840 | c.rw.flags = io.flags; | |
6c7d4945 | 1841 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
a53295b6 | 1842 | c.rw.slba = cpu_to_le64(io.slba); |
6c7d4945 | 1843 | c.rw.length = cpu_to_le16(io.nblocks); |
a53295b6 | 1844 | c.rw.control = cpu_to_le16(io.control); |
1c9b5265 MW |
1845 | c.rw.dsmgmt = cpu_to_le32(io.dsmgmt); |
1846 | c.rw.reftag = cpu_to_le32(io.reftag); | |
1847 | c.rw.apptag = cpu_to_le16(io.apptag); | |
1848 | c.rw.appmask = cpu_to_le16(io.appmask); | |
a67a9513 | 1849 | c.rw.metadata = cpu_to_le64(meta_dma); |
d29ec824 CH |
1850 | |
1851 | status = __nvme_submit_sync_cmd(ns->queue, &c, NULL, | |
1852 | (void __user *)io.addr, length, NULL, 0); | |
f410c680 | 1853 | unmap: |
a67a9513 KB |
1854 | if (meta) { |
1855 | if (status == NVME_SC_SUCCESS && !write) { | |
fec558b5 | 1856 | if (copy_to_user(metadata, meta, meta_len)) |
a67a9513 KB |
1857 | status = -EFAULT; |
1858 | } | |
e75ec752 | 1859 | dma_free_coherent(dev->dev, meta_len, meta, meta_dma); |
f410c680 | 1860 | } |
a53295b6 MW |
1861 | return status; |
1862 | } | |
1863 | ||
a4aea562 MB |
1864 | static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns, |
1865 | struct nvme_passthru_cmd __user *ucmd) | |
6ee44cdc | 1866 | { |
7963e521 | 1867 | struct nvme_passthru_cmd cmd; |
6ee44cdc | 1868 | struct nvme_command c; |
d29ec824 CH |
1869 | unsigned timeout = 0; |
1870 | int status; | |
6ee44cdc | 1871 | |
6bbf1acd MW |
1872 | if (!capable(CAP_SYS_ADMIN)) |
1873 | return -EACCES; | |
1874 | if (copy_from_user(&cmd, ucmd, sizeof(cmd))) | |
6ee44cdc | 1875 | return -EFAULT; |
6ee44cdc MW |
1876 | |
1877 | memset(&c, 0, sizeof(c)); | |
6bbf1acd MW |
1878 | c.common.opcode = cmd.opcode; |
1879 | c.common.flags = cmd.flags; | |
1880 | c.common.nsid = cpu_to_le32(cmd.nsid); | |
1881 | c.common.cdw2[0] = cpu_to_le32(cmd.cdw2); | |
1882 | c.common.cdw2[1] = cpu_to_le32(cmd.cdw3); | |
1883 | c.common.cdw10[0] = cpu_to_le32(cmd.cdw10); | |
1884 | c.common.cdw10[1] = cpu_to_le32(cmd.cdw11); | |
1885 | c.common.cdw10[2] = cpu_to_le32(cmd.cdw12); | |
1886 | c.common.cdw10[3] = cpu_to_le32(cmd.cdw13); | |
1887 | c.common.cdw10[4] = cpu_to_le32(cmd.cdw14); | |
1888 | c.common.cdw10[5] = cpu_to_le32(cmd.cdw15); | |
1889 | ||
d29ec824 CH |
1890 | if (cmd.timeout_ms) |
1891 | timeout = msecs_to_jiffies(cmd.timeout_ms); | |
eca18b23 | 1892 | |
f705f837 | 1893 | status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c, |
d29ec824 CH |
1894 | NULL, (void __user *)cmd.addr, cmd.data_len, |
1895 | &cmd.result, timeout); | |
1896 | if (status >= 0) { | |
1897 | if (put_user(cmd.result, &ucmd->result)) | |
1898 | return -EFAULT; | |
6bbf1acd | 1899 | } |
f4f117f6 | 1900 | |
6ee44cdc MW |
1901 | return status; |
1902 | } | |
1903 | ||
81f03fed JD |
1904 | static int nvme_subsys_reset(struct nvme_dev *dev) |
1905 | { | |
1906 | if (!dev->subsystem) | |
1907 | return -ENOTTY; | |
1908 | ||
1909 | writel(0x4E564D65, &dev->bar->nssr); /* "NVMe" */ | |
1910 | return 0; | |
1911 | } | |
1912 | ||
b60503ba MW |
1913 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1914 | unsigned long arg) | |
1915 | { | |
1916 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1917 | ||
1918 | switch (cmd) { | |
6bbf1acd | 1919 | case NVME_IOCTL_ID: |
c3bfe717 | 1920 | force_successful_syscall_return(); |
6bbf1acd MW |
1921 | return ns->ns_id; |
1922 | case NVME_IOCTL_ADMIN_CMD: | |
a4aea562 | 1923 | return nvme_user_cmd(ns->dev, NULL, (void __user *)arg); |
7963e521 | 1924 | case NVME_IOCTL_IO_CMD: |
a4aea562 | 1925 | return nvme_user_cmd(ns->dev, ns, (void __user *)arg); |
a53295b6 MW |
1926 | case NVME_IOCTL_SUBMIT_IO: |
1927 | return nvme_submit_io(ns, (void __user *)arg); | |
5d0f6131 VV |
1928 | case SG_GET_VERSION_NUM: |
1929 | return nvme_sg_get_version_num((void __user *)arg); | |
1930 | case SG_IO: | |
1931 | return nvme_sg_io(ns, (void __user *)arg); | |
b60503ba MW |
1932 | default: |
1933 | return -ENOTTY; | |
1934 | } | |
1935 | } | |
1936 | ||
320a3827 KB |
1937 | #ifdef CONFIG_COMPAT |
1938 | static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode, | |
1939 | unsigned int cmd, unsigned long arg) | |
1940 | { | |
320a3827 KB |
1941 | switch (cmd) { |
1942 | case SG_IO: | |
e179729a | 1943 | return -ENOIOCTLCMD; |
320a3827 KB |
1944 | } |
1945 | return nvme_ioctl(bdev, mode, cmd, arg); | |
1946 | } | |
1947 | #else | |
1948 | #define nvme_compat_ioctl NULL | |
1949 | #endif | |
1950 | ||
9ac27090 KB |
1951 | static int nvme_open(struct block_device *bdev, fmode_t mode) |
1952 | { | |
9e60352c KB |
1953 | int ret = 0; |
1954 | struct nvme_ns *ns; | |
9ac27090 | 1955 | |
9e60352c KB |
1956 | spin_lock(&dev_list_lock); |
1957 | ns = bdev->bd_disk->private_data; | |
1958 | if (!ns) | |
1959 | ret = -ENXIO; | |
1960 | else if (!kref_get_unless_zero(&ns->dev->kref)) | |
1961 | ret = -ENXIO; | |
1962 | spin_unlock(&dev_list_lock); | |
1963 | ||
1964 | return ret; | |
9ac27090 KB |
1965 | } |
1966 | ||
1967 | static void nvme_free_dev(struct kref *kref); | |
1968 | ||
1969 | static void nvme_release(struct gendisk *disk, fmode_t mode) | |
1970 | { | |
1971 | struct nvme_ns *ns = disk->private_data; | |
1972 | struct nvme_dev *dev = ns->dev; | |
1973 | ||
1974 | kref_put(&dev->kref, nvme_free_dev); | |
1975 | } | |
1976 | ||
4cc09e2d KB |
1977 | static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo) |
1978 | { | |
1979 | /* some standard values */ | |
1980 | geo->heads = 1 << 6; | |
1981 | geo->sectors = 1 << 5; | |
1982 | geo->cylinders = get_capacity(bd->bd_disk) >> 11; | |
1983 | return 0; | |
1984 | } | |
1985 | ||
e1e5e564 KB |
1986 | static void nvme_config_discard(struct nvme_ns *ns) |
1987 | { | |
1988 | u32 logical_block_size = queue_logical_block_size(ns->queue); | |
1989 | ns->queue->limits.discard_zeroes_data = 0; | |
1990 | ns->queue->limits.discard_alignment = logical_block_size; | |
1991 | ns->queue->limits.discard_granularity = logical_block_size; | |
2bb4cd5c | 1992 | blk_queue_max_discard_sectors(ns->queue, 0xffffffff); |
e1e5e564 KB |
1993 | queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); |
1994 | } | |
1995 | ||
1b9dbf7f KB |
1996 | static int nvme_revalidate_disk(struct gendisk *disk) |
1997 | { | |
1998 | struct nvme_ns *ns = disk->private_data; | |
1999 | struct nvme_dev *dev = ns->dev; | |
2000 | struct nvme_id_ns *id; | |
a67a9513 KB |
2001 | u8 lbaf, pi_type; |
2002 | u16 old_ms; | |
e1e5e564 | 2003 | unsigned short bs; |
1b9dbf7f | 2004 | |
d29ec824 | 2005 | if (nvme_identify_ns(dev, ns->ns_id, &id)) { |
a5768aa8 KB |
2006 | dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__, |
2007 | dev->instance, ns->ns_id); | |
2008 | return -ENODEV; | |
1b9dbf7f | 2009 | } |
a5768aa8 KB |
2010 | if (id->ncap == 0) { |
2011 | kfree(id); | |
2012 | return -ENODEV; | |
e1e5e564 | 2013 | } |
1b9dbf7f | 2014 | |
e1e5e564 KB |
2015 | old_ms = ns->ms; |
2016 | lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK; | |
1b9dbf7f | 2017 | ns->lba_shift = id->lbaf[lbaf].ds; |
e1e5e564 | 2018 | ns->ms = le16_to_cpu(id->lbaf[lbaf].ms); |
a67a9513 | 2019 | ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT); |
e1e5e564 KB |
2020 | |
2021 | /* | |
2022 | * If identify namespace failed, use default 512 byte block size so | |
2023 | * block layer can use before failing read/write for 0 capacity. | |
2024 | */ | |
2025 | if (ns->lba_shift == 0) | |
2026 | ns->lba_shift = 9; | |
2027 | bs = 1 << ns->lba_shift; | |
2028 | ||
2029 | /* XXX: PI implementation requires metadata equal t10 pi tuple size */ | |
2030 | pi_type = ns->ms == sizeof(struct t10_pi_tuple) ? | |
2031 | id->dps & NVME_NS_DPS_PI_MASK : 0; | |
2032 | ||
52b68d7e KB |
2033 | if (blk_get_integrity(disk) && (ns->pi_type != pi_type || |
2034 | ns->ms != old_ms || | |
e1e5e564 | 2035 | bs != queue_logical_block_size(disk->queue) || |
a67a9513 | 2036 | (ns->ms && ns->ext))) |
e1e5e564 KB |
2037 | blk_integrity_unregister(disk); |
2038 | ||
2039 | ns->pi_type = pi_type; | |
2040 | blk_queue_logical_block_size(ns->queue, bs); | |
2041 | ||
52b68d7e | 2042 | if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) && |
a67a9513 | 2043 | !ns->ext) |
e1e5e564 KB |
2044 | nvme_init_integrity(ns); |
2045 | ||
a5768aa8 | 2046 | if (ns->ms && !blk_get_integrity(disk)) |
e1e5e564 KB |
2047 | set_capacity(disk, 0); |
2048 | else | |
2049 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); | |
2050 | ||
2051 | if (dev->oncs & NVME_CTRL_ONCS_DSM) | |
2052 | nvme_config_discard(ns); | |
1b9dbf7f | 2053 | |
d29ec824 | 2054 | kfree(id); |
1b9dbf7f KB |
2055 | return 0; |
2056 | } | |
2057 | ||
b60503ba MW |
2058 | static const struct block_device_operations nvme_fops = { |
2059 | .owner = THIS_MODULE, | |
2060 | .ioctl = nvme_ioctl, | |
320a3827 | 2061 | .compat_ioctl = nvme_compat_ioctl, |
9ac27090 KB |
2062 | .open = nvme_open, |
2063 | .release = nvme_release, | |
4cc09e2d | 2064 | .getgeo = nvme_getgeo, |
1b9dbf7f | 2065 | .revalidate_disk= nvme_revalidate_disk, |
b60503ba MW |
2066 | }; |
2067 | ||
1fa6aead MW |
2068 | static int nvme_kthread(void *data) |
2069 | { | |
d4b4ff8e | 2070 | struct nvme_dev *dev, *next; |
1fa6aead MW |
2071 | |
2072 | while (!kthread_should_stop()) { | |
564a232c | 2073 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 2074 | spin_lock(&dev_list_lock); |
d4b4ff8e | 2075 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 2076 | int i; |
dfbac8c7 KB |
2077 | u32 csts = readl(&dev->bar->csts); |
2078 | ||
2079 | if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || | |
2080 | csts & NVME_CSTS_CFS) { | |
d4b4ff8e KB |
2081 | if (work_busy(&dev->reset_work)) |
2082 | continue; | |
2083 | list_del_init(&dev->node); | |
e75ec752 | 2084 | dev_warn(dev->dev, |
a4aea562 MB |
2085 | "Failed status: %x, reset controller\n", |
2086 | readl(&dev->bar->csts)); | |
9ca97374 | 2087 | dev->reset_workfn = nvme_reset_failed_dev; |
d4b4ff8e KB |
2088 | queue_work(nvme_workq, &dev->reset_work); |
2089 | continue; | |
2090 | } | |
1fa6aead | 2091 | for (i = 0; i < dev->queue_count; i++) { |
a4aea562 | 2092 | struct nvme_queue *nvmeq = dev->queues[i]; |
740216fc MW |
2093 | if (!nvmeq) |
2094 | continue; | |
1fa6aead | 2095 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 2096 | nvme_process_cq(nvmeq); |
6fccf938 KB |
2097 | |
2098 | while ((i == 0) && (dev->event_limit > 0)) { | |
a4aea562 | 2099 | if (nvme_submit_async_admin_req(dev)) |
6fccf938 KB |
2100 | break; |
2101 | dev->event_limit--; | |
2102 | } | |
1fa6aead MW |
2103 | spin_unlock_irq(&nvmeq->q_lock); |
2104 | } | |
2105 | } | |
2106 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 2107 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
2108 | } |
2109 | return 0; | |
2110 | } | |
2111 | ||
e1e5e564 | 2112 | static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid) |
b60503ba MW |
2113 | { |
2114 | struct nvme_ns *ns; | |
2115 | struct gendisk *disk; | |
e75ec752 | 2116 | int node = dev_to_node(dev->dev); |
b60503ba | 2117 | |
a4aea562 | 2118 | ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node); |
b60503ba | 2119 | if (!ns) |
e1e5e564 KB |
2120 | return; |
2121 | ||
a4aea562 | 2122 | ns->queue = blk_mq_init_queue(&dev->tagset); |
9f173b33 | 2123 | if (IS_ERR(ns->queue)) |
b60503ba | 2124 | goto out_free_ns; |
4eeb9215 MW |
2125 | queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue); |
2126 | queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue); | |
a4aea562 | 2127 | queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue); |
b60503ba MW |
2128 | ns->dev = dev; |
2129 | ns->queue->queuedata = ns; | |
2130 | ||
a4aea562 | 2131 | disk = alloc_disk_node(0, node); |
b60503ba MW |
2132 | if (!disk) |
2133 | goto out_free_queue; | |
a4aea562 | 2134 | |
5aff9382 | 2135 | ns->ns_id = nsid; |
b60503ba | 2136 | ns->disk = disk; |
e1e5e564 KB |
2137 | ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */ |
2138 | list_add_tail(&ns->list, &dev->namespaces); | |
2139 | ||
e9ef4636 | 2140 | blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift); |
e824410f | 2141 | if (dev->max_hw_sectors) { |
8fc23e03 | 2142 | blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors); |
e824410f KB |
2143 | blk_queue_max_segments(ns->queue, |
2144 | ((dev->max_hw_sectors << 9) / dev->page_size) + 1); | |
2145 | } | |
a4aea562 MB |
2146 | if (dev->stripe_size) |
2147 | blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9); | |
a7d2ce28 KB |
2148 | if (dev->vwc & NVME_CTRL_VWC_PRESENT) |
2149 | blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA); | |
b60503ba MW |
2150 | |
2151 | disk->major = nvme_major; | |
469071a3 | 2152 | disk->first_minor = 0; |
b60503ba MW |
2153 | disk->fops = &nvme_fops; |
2154 | disk->private_data = ns; | |
2155 | disk->queue = ns->queue; | |
b3fffdef | 2156 | disk->driverfs_dev = dev->device; |
469071a3 | 2157 | disk->flags = GENHD_FL_EXT_DEVT; |
5aff9382 | 2158 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid); |
b60503ba | 2159 | |
e1e5e564 KB |
2160 | /* |
2161 | * Initialize capacity to 0 until we establish the namespace format and | |
2162 | * setup integrity extentions if necessary. The revalidate_disk after | |
2163 | * add_disk allows the driver to register with integrity if the format | |
2164 | * requires it. | |
2165 | */ | |
2166 | set_capacity(disk, 0); | |
a5768aa8 KB |
2167 | if (nvme_revalidate_disk(ns->disk)) |
2168 | goto out_free_disk; | |
2169 | ||
e1e5e564 | 2170 | add_disk(ns->disk); |
7bee6074 KB |
2171 | if (ns->ms) { |
2172 | struct block_device *bd = bdget_disk(ns->disk, 0); | |
2173 | if (!bd) | |
2174 | return; | |
2175 | if (blkdev_get(bd, FMODE_READ, NULL)) { | |
2176 | bdput(bd); | |
2177 | return; | |
2178 | } | |
2179 | blkdev_reread_part(bd); | |
2180 | blkdev_put(bd, FMODE_READ); | |
2181 | } | |
e1e5e564 | 2182 | return; |
a5768aa8 KB |
2183 | out_free_disk: |
2184 | kfree(disk); | |
2185 | list_del(&ns->list); | |
b60503ba MW |
2186 | out_free_queue: |
2187 | blk_cleanup_queue(ns->queue); | |
2188 | out_free_ns: | |
2189 | kfree(ns); | |
b60503ba MW |
2190 | } |
2191 | ||
42f61420 KB |
2192 | static void nvme_create_io_queues(struct nvme_dev *dev) |
2193 | { | |
a4aea562 | 2194 | unsigned i; |
42f61420 | 2195 | |
a4aea562 | 2196 | for (i = dev->queue_count; i <= dev->max_qid; i++) |
2b25d981 | 2197 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) |
42f61420 KB |
2198 | break; |
2199 | ||
a4aea562 MB |
2200 | for (i = dev->online_queues; i <= dev->queue_count - 1; i++) |
2201 | if (nvme_create_queue(dev->queues[i], i)) | |
42f61420 KB |
2202 | break; |
2203 | } | |
2204 | ||
b3b06812 | 2205 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
2206 | { |
2207 | int status; | |
2208 | u32 result; | |
b3b06812 | 2209 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba | 2210 | |
df348139 | 2211 | status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0, |
bc5fc7e4 | 2212 | &result); |
27e8166c MW |
2213 | if (status < 0) |
2214 | return status; | |
2215 | if (status > 0) { | |
e75ec752 | 2216 | dev_err(dev->dev, "Could not set queue count (%d)\n", status); |
badc34d4 | 2217 | return 0; |
27e8166c | 2218 | } |
b60503ba MW |
2219 | return min(result & 0xffff, result >> 16) + 1; |
2220 | } | |
2221 | ||
8ffaadf7 JD |
2222 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
2223 | { | |
2224 | u64 szu, size, offset; | |
2225 | u32 cmbloc; | |
2226 | resource_size_t bar_size; | |
2227 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
2228 | void __iomem *cmb; | |
2229 | dma_addr_t dma_addr; | |
2230 | ||
2231 | if (!use_cmb_sqes) | |
2232 | return NULL; | |
2233 | ||
2234 | dev->cmbsz = readl(&dev->bar->cmbsz); | |
2235 | if (!(NVME_CMB_SZ(dev->cmbsz))) | |
2236 | return NULL; | |
2237 | ||
2238 | cmbloc = readl(&dev->bar->cmbloc); | |
2239 | ||
2240 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
2241 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
2242 | offset = szu * NVME_CMB_OFST(cmbloc); | |
2243 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
2244 | ||
2245 | if (offset > bar_size) | |
2246 | return NULL; | |
2247 | ||
2248 | /* | |
2249 | * Controllers may support a CMB size larger than their BAR, | |
2250 | * for example, due to being behind a bridge. Reduce the CMB to | |
2251 | * the reported size of the BAR | |
2252 | */ | |
2253 | if (size > bar_size - offset) | |
2254 | size = bar_size - offset; | |
2255 | ||
2256 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
2257 | cmb = ioremap_wc(dma_addr, size); | |
2258 | if (!cmb) | |
2259 | return NULL; | |
2260 | ||
2261 | dev->cmb_dma_addr = dma_addr; | |
2262 | dev->cmb_size = size; | |
2263 | return cmb; | |
2264 | } | |
2265 | ||
2266 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
2267 | { | |
2268 | if (dev->cmb) { | |
2269 | iounmap(dev->cmb); | |
2270 | dev->cmb = NULL; | |
2271 | } | |
2272 | } | |
2273 | ||
9d713c2b KB |
2274 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
2275 | { | |
b80d5ccc | 2276 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
2277 | } |
2278 | ||
8d85fce7 | 2279 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 2280 | { |
a4aea562 | 2281 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 2282 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 2283 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 2284 | |
42f61420 | 2285 | nr_io_queues = num_possible_cpus(); |
b348b7d5 | 2286 | result = set_queue_count(dev, nr_io_queues); |
badc34d4 | 2287 | if (result <= 0) |
1b23484b | 2288 | return result; |
b348b7d5 MW |
2289 | if (result < nr_io_queues) |
2290 | nr_io_queues = result; | |
b60503ba | 2291 | |
8ffaadf7 JD |
2292 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
2293 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
2294 | sizeof(struct nvme_command)); | |
2295 | if (result > 0) | |
2296 | dev->q_depth = result; | |
2297 | else | |
2298 | nvme_release_cmb(dev); | |
2299 | } | |
2300 | ||
9d713c2b KB |
2301 | size = db_bar_size(dev, nr_io_queues); |
2302 | if (size > 8192) { | |
f1938f6e | 2303 | iounmap(dev->bar); |
9d713c2b KB |
2304 | do { |
2305 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
2306 | if (dev->bar) | |
2307 | break; | |
2308 | if (!--nr_io_queues) | |
2309 | return -ENOMEM; | |
2310 | size = db_bar_size(dev, nr_io_queues); | |
2311 | } while (1); | |
f1938f6e | 2312 | dev->dbs = ((void __iomem *)dev->bar) + 4096; |
5a92e700 | 2313 | adminq->q_db = dev->dbs; |
f1938f6e MW |
2314 | } |
2315 | ||
9d713c2b | 2316 | /* Deregister the admin queue's interrupt */ |
3193f07b | 2317 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 2318 | |
e32efbfc JA |
2319 | /* |
2320 | * If we enable msix early due to not intx, disable it again before | |
2321 | * setting up the full range we need. | |
2322 | */ | |
2323 | if (!pdev->irq) | |
2324 | pci_disable_msix(pdev); | |
2325 | ||
be577fab | 2326 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 2327 | dev->entry[i].entry = i; |
be577fab AG |
2328 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
2329 | if (vecs < 0) { | |
2330 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
2331 | if (vecs < 0) { | |
2332 | vecs = 1; | |
2333 | } else { | |
2334 | for (i = 0; i < vecs; i++) | |
2335 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
2336 | } |
2337 | } | |
2338 | ||
063a8096 MW |
2339 | /* |
2340 | * Should investigate if there's a performance win from allocating | |
2341 | * more queues than interrupt vectors; it might allow the submission | |
2342 | * path to scale better, even if the receive path is limited by the | |
2343 | * number of interrupts. | |
2344 | */ | |
2345 | nr_io_queues = vecs; | |
42f61420 | 2346 | dev->max_qid = nr_io_queues; |
063a8096 | 2347 | |
3193f07b | 2348 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
2349 | if (result) { |
2350 | adminq->cq_vector = -1; | |
22404274 | 2351 | goto free_queues; |
758dd7fd | 2352 | } |
1b23484b | 2353 | |
cd638946 | 2354 | /* Free previously allocated queues that are no longer usable */ |
42f61420 | 2355 | nvme_free_queues(dev, nr_io_queues + 1); |
a4aea562 | 2356 | nvme_create_io_queues(dev); |
9ecdc946 | 2357 | |
22404274 | 2358 | return 0; |
b60503ba | 2359 | |
22404274 | 2360 | free_queues: |
a1a5ef99 | 2361 | nvme_free_queues(dev, 1); |
22404274 | 2362 | return result; |
b60503ba MW |
2363 | } |
2364 | ||
a5768aa8 KB |
2365 | static void nvme_free_namespace(struct nvme_ns *ns) |
2366 | { | |
2367 | list_del(&ns->list); | |
2368 | ||
2369 | spin_lock(&dev_list_lock); | |
2370 | ns->disk->private_data = NULL; | |
2371 | spin_unlock(&dev_list_lock); | |
2372 | ||
2373 | put_disk(ns->disk); | |
2374 | kfree(ns); | |
2375 | } | |
2376 | ||
2377 | static int ns_cmp(void *priv, struct list_head *a, struct list_head *b) | |
2378 | { | |
2379 | struct nvme_ns *nsa = container_of(a, struct nvme_ns, list); | |
2380 | struct nvme_ns *nsb = container_of(b, struct nvme_ns, list); | |
2381 | ||
2382 | return nsa->ns_id - nsb->ns_id; | |
2383 | } | |
2384 | ||
2385 | static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid) | |
2386 | { | |
2387 | struct nvme_ns *ns; | |
2388 | ||
2389 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2390 | if (ns->ns_id == nsid) | |
2391 | return ns; | |
2392 | if (ns->ns_id > nsid) | |
2393 | break; | |
2394 | } | |
2395 | return NULL; | |
2396 | } | |
2397 | ||
2398 | static inline bool nvme_io_incapable(struct nvme_dev *dev) | |
2399 | { | |
2400 | return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS || | |
2401 | dev->online_queues < 2); | |
2402 | } | |
2403 | ||
2404 | static void nvme_ns_remove(struct nvme_ns *ns) | |
2405 | { | |
2406 | bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue); | |
2407 | ||
2408 | if (kill) | |
2409 | blk_set_queue_dying(ns->queue); | |
2410 | if (ns->disk->flags & GENHD_FL_UP) { | |
2411 | if (blk_get_integrity(ns->disk)) | |
2412 | blk_integrity_unregister(ns->disk); | |
2413 | del_gendisk(ns->disk); | |
2414 | } | |
2415 | if (kill || !blk_queue_dying(ns->queue)) { | |
2416 | blk_mq_abort_requeue_list(ns->queue); | |
2417 | blk_cleanup_queue(ns->queue); | |
2418 | } | |
2419 | } | |
2420 | ||
2421 | static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn) | |
2422 | { | |
2423 | struct nvme_ns *ns, *next; | |
2424 | unsigned i; | |
2425 | ||
2426 | for (i = 1; i <= nn; i++) { | |
2427 | ns = nvme_find_ns(dev, i); | |
2428 | if (ns) { | |
2429 | if (revalidate_disk(ns->disk)) { | |
2430 | nvme_ns_remove(ns); | |
2431 | nvme_free_namespace(ns); | |
2432 | } | |
2433 | } else | |
2434 | nvme_alloc_ns(dev, i); | |
2435 | } | |
2436 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
2437 | if (ns->ns_id > nn) { | |
2438 | nvme_ns_remove(ns); | |
2439 | nvme_free_namespace(ns); | |
2440 | } | |
2441 | } | |
2442 | list_sort(NULL, &dev->namespaces, ns_cmp); | |
2443 | } | |
2444 | ||
2445 | static void nvme_dev_scan(struct work_struct *work) | |
2446 | { | |
2447 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); | |
2448 | struct nvme_id_ctrl *ctrl; | |
2449 | ||
2450 | if (!dev->tagset.tags) | |
2451 | return; | |
2452 | if (nvme_identify_ctrl(dev, &ctrl)) | |
2453 | return; | |
2454 | nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn)); | |
2455 | kfree(ctrl); | |
2456 | } | |
2457 | ||
422ef0c7 MW |
2458 | /* |
2459 | * Return: error value if an error occurred setting up the queues or calling | |
2460 | * Identify Device. 0 if these succeeded, even if adding some of the | |
2461 | * namespaces failed. At the moment, these failures are silent. TBD which | |
2462 | * failures should be reported. | |
2463 | */ | |
8d85fce7 | 2464 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 2465 | { |
e75ec752 | 2466 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
c3bfe717 | 2467 | int res; |
51814232 | 2468 | struct nvme_id_ctrl *ctrl; |
159b67d7 | 2469 | int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12; |
b60503ba | 2470 | |
d29ec824 | 2471 | res = nvme_identify_ctrl(dev, &ctrl); |
b60503ba | 2472 | if (res) { |
e75ec752 | 2473 | dev_err(dev->dev, "Identify Controller failed (%d)\n", res); |
e1e5e564 | 2474 | return -EIO; |
b60503ba MW |
2475 | } |
2476 | ||
0e5e4f0e | 2477 | dev->oncs = le16_to_cpup(&ctrl->oncs); |
c30341dc | 2478 | dev->abort_limit = ctrl->acl + 1; |
a7d2ce28 | 2479 | dev->vwc = ctrl->vwc; |
51814232 MW |
2480 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); |
2481 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
2482 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
159b67d7 | 2483 | if (ctrl->mdts) |
8fc23e03 | 2484 | dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9); |
68608c26 | 2485 | if ((pdev->vendor == PCI_VENDOR_ID_INTEL) && |
a4aea562 MB |
2486 | (pdev->device == 0x0953) && ctrl->vs[3]) { |
2487 | unsigned int max_hw_sectors; | |
2488 | ||
159b67d7 | 2489 | dev->stripe_size = 1 << (ctrl->vs[3] + shift); |
a4aea562 MB |
2490 | max_hw_sectors = dev->stripe_size >> (shift - 9); |
2491 | if (dev->max_hw_sectors) { | |
2492 | dev->max_hw_sectors = min(max_hw_sectors, | |
2493 | dev->max_hw_sectors); | |
2494 | } else | |
2495 | dev->max_hw_sectors = max_hw_sectors; | |
2496 | } | |
d29ec824 | 2497 | kfree(ctrl); |
a4aea562 | 2498 | |
ffe7704d KB |
2499 | if (!dev->tagset.tags) { |
2500 | dev->tagset.ops = &nvme_mq_ops; | |
2501 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
2502 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
2503 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
2504 | dev->tagset.queue_depth = | |
a4aea562 | 2505 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
2506 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
2507 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
2508 | dev->tagset.driver_data = dev; | |
b60503ba | 2509 | |
ffe7704d KB |
2510 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
2511 | return 0; | |
2512 | } | |
a5768aa8 | 2513 | schedule_work(&dev->scan_work); |
e1e5e564 | 2514 | return 0; |
b60503ba MW |
2515 | } |
2516 | ||
0877cb0d KB |
2517 | static int nvme_dev_map(struct nvme_dev *dev) |
2518 | { | |
42f61420 | 2519 | u64 cap; |
0877cb0d | 2520 | int bars, result = -ENOMEM; |
e75ec752 | 2521 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
2522 | |
2523 | if (pci_enable_device_mem(pdev)) | |
2524 | return result; | |
2525 | ||
2526 | dev->entry[0].vector = pdev->irq; | |
2527 | pci_set_master(pdev); | |
2528 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
2529 | if (!bars) |
2530 | goto disable_pci; | |
2531 | ||
0877cb0d KB |
2532 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
2533 | goto disable_pci; | |
2534 | ||
e75ec752 CH |
2535 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
2536 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 2537 | goto disable; |
0877cb0d | 2538 | |
0877cb0d KB |
2539 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
2540 | if (!dev->bar) | |
2541 | goto disable; | |
e32efbfc | 2542 | |
0e53d180 KB |
2543 | if (readl(&dev->bar->csts) == -1) { |
2544 | result = -ENODEV; | |
2545 | goto unmap; | |
2546 | } | |
e32efbfc JA |
2547 | |
2548 | /* | |
2549 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
2550 | * MSIX vec for setup. We'll adjust this later. | |
2551 | */ | |
2552 | if (!pdev->irq) { | |
2553 | result = pci_enable_msix(pdev, dev->entry, 1); | |
2554 | if (result < 0) | |
2555 | goto unmap; | |
2556 | } | |
2557 | ||
42f61420 KB |
2558 | cap = readq(&dev->bar->cap); |
2559 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); | |
2560 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
0877cb0d | 2561 | dev->dbs = ((void __iomem *)dev->bar) + 4096; |
8ffaadf7 JD |
2562 | if (readl(&dev->bar->vs) >= NVME_VS(1, 2)) |
2563 | dev->cmb = nvme_map_cmb(dev); | |
0877cb0d KB |
2564 | |
2565 | return 0; | |
2566 | ||
0e53d180 KB |
2567 | unmap: |
2568 | iounmap(dev->bar); | |
2569 | dev->bar = NULL; | |
0877cb0d KB |
2570 | disable: |
2571 | pci_release_regions(pdev); | |
2572 | disable_pci: | |
2573 | pci_disable_device(pdev); | |
2574 | return result; | |
2575 | } | |
2576 | ||
2577 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
2578 | { | |
e75ec752 CH |
2579 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2580 | ||
2581 | if (pdev->msi_enabled) | |
2582 | pci_disable_msi(pdev); | |
2583 | else if (pdev->msix_enabled) | |
2584 | pci_disable_msix(pdev); | |
0877cb0d KB |
2585 | |
2586 | if (dev->bar) { | |
2587 | iounmap(dev->bar); | |
2588 | dev->bar = NULL; | |
e75ec752 | 2589 | pci_release_regions(pdev); |
0877cb0d KB |
2590 | } |
2591 | ||
e75ec752 CH |
2592 | if (pci_is_enabled(pdev)) |
2593 | pci_disable_device(pdev); | |
0877cb0d KB |
2594 | } |
2595 | ||
4d115420 KB |
2596 | struct nvme_delq_ctx { |
2597 | struct task_struct *waiter; | |
2598 | struct kthread_worker *worker; | |
2599 | atomic_t refcount; | |
2600 | }; | |
2601 | ||
2602 | static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) | |
2603 | { | |
2604 | dq->waiter = current; | |
2605 | mb(); | |
2606 | ||
2607 | for (;;) { | |
2608 | set_current_state(TASK_KILLABLE); | |
2609 | if (!atomic_read(&dq->refcount)) | |
2610 | break; | |
2611 | if (!schedule_timeout(ADMIN_TIMEOUT) || | |
2612 | fatal_signal_pending(current)) { | |
0fb59cbc KB |
2613 | /* |
2614 | * Disable the controller first since we can't trust it | |
2615 | * at this point, but leave the admin queue enabled | |
2616 | * until all queue deletion requests are flushed. | |
2617 | * FIXME: This may take a while if there are more h/w | |
2618 | * queues than admin tags. | |
2619 | */ | |
4d115420 | 2620 | set_current_state(TASK_RUNNING); |
4d115420 | 2621 | nvme_disable_ctrl(dev, readq(&dev->bar->cap)); |
0fb59cbc | 2622 | nvme_clear_queue(dev->queues[0]); |
4d115420 | 2623 | flush_kthread_worker(dq->worker); |
0fb59cbc | 2624 | nvme_disable_queue(dev, 0); |
4d115420 KB |
2625 | return; |
2626 | } | |
2627 | } | |
2628 | set_current_state(TASK_RUNNING); | |
2629 | } | |
2630 | ||
2631 | static void nvme_put_dq(struct nvme_delq_ctx *dq) | |
2632 | { | |
2633 | atomic_dec(&dq->refcount); | |
2634 | if (dq->waiter) | |
2635 | wake_up_process(dq->waiter); | |
2636 | } | |
2637 | ||
2638 | static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) | |
2639 | { | |
2640 | atomic_inc(&dq->refcount); | |
2641 | return dq; | |
2642 | } | |
2643 | ||
2644 | static void nvme_del_queue_end(struct nvme_queue *nvmeq) | |
2645 | { | |
2646 | struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; | |
4d115420 KB |
2647 | nvme_put_dq(dq); |
2648 | } | |
2649 | ||
2650 | static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, | |
2651 | kthread_work_func_t fn) | |
2652 | { | |
2653 | struct nvme_command c; | |
2654 | ||
2655 | memset(&c, 0, sizeof(c)); | |
2656 | c.delete_queue.opcode = opcode; | |
2657 | c.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
2658 | ||
2659 | init_kthread_work(&nvmeq->cmdinfo.work, fn); | |
a4aea562 MB |
2660 | return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo, |
2661 | ADMIN_TIMEOUT); | |
4d115420 KB |
2662 | } |
2663 | ||
2664 | static void nvme_del_cq_work_handler(struct kthread_work *work) | |
2665 | { | |
2666 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2667 | cmdinfo.work); | |
2668 | nvme_del_queue_end(nvmeq); | |
2669 | } | |
2670 | ||
2671 | static int nvme_delete_cq(struct nvme_queue *nvmeq) | |
2672 | { | |
2673 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, | |
2674 | nvme_del_cq_work_handler); | |
2675 | } | |
2676 | ||
2677 | static void nvme_del_sq_work_handler(struct kthread_work *work) | |
2678 | { | |
2679 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2680 | cmdinfo.work); | |
2681 | int status = nvmeq->cmdinfo.status; | |
2682 | ||
2683 | if (!status) | |
2684 | status = nvme_delete_cq(nvmeq); | |
2685 | if (status) | |
2686 | nvme_del_queue_end(nvmeq); | |
2687 | } | |
2688 | ||
2689 | static int nvme_delete_sq(struct nvme_queue *nvmeq) | |
2690 | { | |
2691 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, | |
2692 | nvme_del_sq_work_handler); | |
2693 | } | |
2694 | ||
2695 | static void nvme_del_queue_start(struct kthread_work *work) | |
2696 | { | |
2697 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2698 | cmdinfo.work); | |
4d115420 KB |
2699 | if (nvme_delete_sq(nvmeq)) |
2700 | nvme_del_queue_end(nvmeq); | |
2701 | } | |
2702 | ||
2703 | static void nvme_disable_io_queues(struct nvme_dev *dev) | |
2704 | { | |
2705 | int i; | |
2706 | DEFINE_KTHREAD_WORKER_ONSTACK(worker); | |
2707 | struct nvme_delq_ctx dq; | |
2708 | struct task_struct *kworker_task = kthread_run(kthread_worker_fn, | |
2709 | &worker, "nvme%d", dev->instance); | |
2710 | ||
2711 | if (IS_ERR(kworker_task)) { | |
e75ec752 | 2712 | dev_err(dev->dev, |
4d115420 KB |
2713 | "Failed to create queue del task\n"); |
2714 | for (i = dev->queue_count - 1; i > 0; i--) | |
2715 | nvme_disable_queue(dev, i); | |
2716 | return; | |
2717 | } | |
2718 | ||
2719 | dq.waiter = NULL; | |
2720 | atomic_set(&dq.refcount, 0); | |
2721 | dq.worker = &worker; | |
2722 | for (i = dev->queue_count - 1; i > 0; i--) { | |
a4aea562 | 2723 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 KB |
2724 | |
2725 | if (nvme_suspend_queue(nvmeq)) | |
2726 | continue; | |
2727 | nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); | |
2728 | nvmeq->cmdinfo.worker = dq.worker; | |
2729 | init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); | |
2730 | queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); | |
2731 | } | |
2732 | nvme_wait_dq(&dq, dev); | |
2733 | kthread_stop(kworker_task); | |
2734 | } | |
2735 | ||
b9afca3e DM |
2736 | /* |
2737 | * Remove the node from the device list and check | |
2738 | * for whether or not we need to stop the nvme_thread. | |
2739 | */ | |
2740 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
2741 | { | |
2742 | struct task_struct *tmp = NULL; | |
2743 | ||
2744 | spin_lock(&dev_list_lock); | |
2745 | list_del_init(&dev->node); | |
2746 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
2747 | tmp = nvme_thread; | |
2748 | nvme_thread = NULL; | |
2749 | } | |
2750 | spin_unlock(&dev_list_lock); | |
2751 | ||
2752 | if (tmp) | |
2753 | kthread_stop(tmp); | |
2754 | } | |
2755 | ||
c9d3bf88 KB |
2756 | static void nvme_freeze_queues(struct nvme_dev *dev) |
2757 | { | |
2758 | struct nvme_ns *ns; | |
2759 | ||
2760 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2761 | blk_mq_freeze_queue_start(ns->queue); | |
2762 | ||
cddcd72b | 2763 | spin_lock_irq(ns->queue->queue_lock); |
c9d3bf88 | 2764 | queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); |
cddcd72b | 2765 | spin_unlock_irq(ns->queue->queue_lock); |
c9d3bf88 KB |
2766 | |
2767 | blk_mq_cancel_requeue_work(ns->queue); | |
2768 | blk_mq_stop_hw_queues(ns->queue); | |
2769 | } | |
2770 | } | |
2771 | ||
2772 | static void nvme_unfreeze_queues(struct nvme_dev *dev) | |
2773 | { | |
2774 | struct nvme_ns *ns; | |
2775 | ||
2776 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2777 | queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); | |
2778 | blk_mq_unfreeze_queue(ns->queue); | |
2779 | blk_mq_start_stopped_hw_queues(ns->queue, true); | |
2780 | blk_mq_kick_requeue_list(ns->queue); | |
2781 | } | |
2782 | } | |
2783 | ||
f0b50732 | 2784 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 2785 | { |
22404274 | 2786 | int i; |
7c1b2450 | 2787 | u32 csts = -1; |
22404274 | 2788 | |
b9afca3e | 2789 | nvme_dev_list_remove(dev); |
1fa6aead | 2790 | |
c9d3bf88 KB |
2791 | if (dev->bar) { |
2792 | nvme_freeze_queues(dev); | |
7c1b2450 | 2793 | csts = readl(&dev->bar->csts); |
c9d3bf88 | 2794 | } |
7c1b2450 | 2795 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 2796 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 2797 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 2798 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
2799 | } |
2800 | } else { | |
2801 | nvme_disable_io_queues(dev); | |
1894d8f1 | 2802 | nvme_shutdown_ctrl(dev); |
4d115420 KB |
2803 | nvme_disable_queue(dev, 0); |
2804 | } | |
f0b50732 | 2805 | nvme_dev_unmap(dev); |
07836e65 KB |
2806 | |
2807 | for (i = dev->queue_count - 1; i >= 0; i--) | |
2808 | nvme_clear_queue(dev->queues[i]); | |
f0b50732 KB |
2809 | } |
2810 | ||
2811 | static void nvme_dev_remove(struct nvme_dev *dev) | |
2812 | { | |
9ac27090 | 2813 | struct nvme_ns *ns; |
f0b50732 | 2814 | |
a5768aa8 KB |
2815 | list_for_each_entry(ns, &dev->namespaces, list) |
2816 | nvme_ns_remove(ns); | |
b60503ba MW |
2817 | } |
2818 | ||
091b6092 MW |
2819 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2820 | { | |
e75ec752 | 2821 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
2822 | PAGE_SIZE, PAGE_SIZE, 0); |
2823 | if (!dev->prp_page_pool) | |
2824 | return -ENOMEM; | |
2825 | ||
99802a7a | 2826 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2827 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2828 | 256, 256, 0); |
2829 | if (!dev->prp_small_pool) { | |
2830 | dma_pool_destroy(dev->prp_page_pool); | |
2831 | return -ENOMEM; | |
2832 | } | |
091b6092 MW |
2833 | return 0; |
2834 | } | |
2835 | ||
2836 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2837 | { | |
2838 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2839 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2840 | } |
2841 | ||
cd58ad7d QSA |
2842 | static DEFINE_IDA(nvme_instance_ida); |
2843 | ||
2844 | static int nvme_set_instance(struct nvme_dev *dev) | |
b60503ba | 2845 | { |
cd58ad7d QSA |
2846 | int instance, error; |
2847 | ||
2848 | do { | |
2849 | if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL)) | |
2850 | return -ENODEV; | |
2851 | ||
2852 | spin_lock(&dev_list_lock); | |
2853 | error = ida_get_new(&nvme_instance_ida, &instance); | |
2854 | spin_unlock(&dev_list_lock); | |
2855 | } while (error == -EAGAIN); | |
2856 | ||
2857 | if (error) | |
2858 | return -ENODEV; | |
2859 | ||
2860 | dev->instance = instance; | |
2861 | return 0; | |
b60503ba MW |
2862 | } |
2863 | ||
2864 | static void nvme_release_instance(struct nvme_dev *dev) | |
2865 | { | |
cd58ad7d QSA |
2866 | spin_lock(&dev_list_lock); |
2867 | ida_remove(&nvme_instance_ida, dev->instance); | |
2868 | spin_unlock(&dev_list_lock); | |
b60503ba MW |
2869 | } |
2870 | ||
9ac27090 KB |
2871 | static void nvme_free_namespaces(struct nvme_dev *dev) |
2872 | { | |
2873 | struct nvme_ns *ns, *next; | |
2874 | ||
a5768aa8 KB |
2875 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) |
2876 | nvme_free_namespace(ns); | |
9ac27090 KB |
2877 | } |
2878 | ||
5e82e952 KB |
2879 | static void nvme_free_dev(struct kref *kref) |
2880 | { | |
2881 | struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref); | |
9ac27090 | 2882 | |
e75ec752 | 2883 | put_device(dev->dev); |
b3fffdef | 2884 | put_device(dev->device); |
9ac27090 | 2885 | nvme_free_namespaces(dev); |
285dffc9 | 2886 | nvme_release_instance(dev); |
4af0e21c KB |
2887 | if (dev->tagset.tags) |
2888 | blk_mq_free_tag_set(&dev->tagset); | |
2889 | if (dev->admin_q) | |
2890 | blk_put_queue(dev->admin_q); | |
5e82e952 KB |
2891 | kfree(dev->queues); |
2892 | kfree(dev->entry); | |
2893 | kfree(dev); | |
2894 | } | |
2895 | ||
2896 | static int nvme_dev_open(struct inode *inode, struct file *f) | |
2897 | { | |
b3fffdef KB |
2898 | struct nvme_dev *dev; |
2899 | int instance = iminor(inode); | |
2900 | int ret = -ENODEV; | |
2901 | ||
2902 | spin_lock(&dev_list_lock); | |
2903 | list_for_each_entry(dev, &dev_list, node) { | |
2904 | if (dev->instance == instance) { | |
2e1d8448 KB |
2905 | if (!dev->admin_q) { |
2906 | ret = -EWOULDBLOCK; | |
2907 | break; | |
2908 | } | |
b3fffdef KB |
2909 | if (!kref_get_unless_zero(&dev->kref)) |
2910 | break; | |
2911 | f->private_data = dev; | |
2912 | ret = 0; | |
2913 | break; | |
2914 | } | |
2915 | } | |
2916 | spin_unlock(&dev_list_lock); | |
2917 | ||
2918 | return ret; | |
5e82e952 KB |
2919 | } |
2920 | ||
2921 | static int nvme_dev_release(struct inode *inode, struct file *f) | |
2922 | { | |
2923 | struct nvme_dev *dev = f->private_data; | |
2924 | kref_put(&dev->kref, nvme_free_dev); | |
2925 | return 0; | |
2926 | } | |
2927 | ||
2928 | static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg) | |
2929 | { | |
2930 | struct nvme_dev *dev = f->private_data; | |
a4aea562 MB |
2931 | struct nvme_ns *ns; |
2932 | ||
5e82e952 KB |
2933 | switch (cmd) { |
2934 | case NVME_IOCTL_ADMIN_CMD: | |
a4aea562 | 2935 | return nvme_user_cmd(dev, NULL, (void __user *)arg); |
7963e521 | 2936 | case NVME_IOCTL_IO_CMD: |
a4aea562 MB |
2937 | if (list_empty(&dev->namespaces)) |
2938 | return -ENOTTY; | |
2939 | ns = list_first_entry(&dev->namespaces, struct nvme_ns, list); | |
2940 | return nvme_user_cmd(dev, ns, (void __user *)arg); | |
4cc06521 KB |
2941 | case NVME_IOCTL_RESET: |
2942 | dev_warn(dev->dev, "resetting controller\n"); | |
2943 | return nvme_reset(dev); | |
81f03fed JD |
2944 | case NVME_IOCTL_SUBSYS_RESET: |
2945 | return nvme_subsys_reset(dev); | |
5e82e952 KB |
2946 | default: |
2947 | return -ENOTTY; | |
2948 | } | |
2949 | } | |
2950 | ||
2951 | static const struct file_operations nvme_dev_fops = { | |
2952 | .owner = THIS_MODULE, | |
2953 | .open = nvme_dev_open, | |
2954 | .release = nvme_dev_release, | |
2955 | .unlocked_ioctl = nvme_dev_ioctl, | |
2956 | .compat_ioctl = nvme_dev_ioctl, | |
2957 | }; | |
2958 | ||
a4aea562 MB |
2959 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
2960 | { | |
2961 | struct nvme_queue *nvmeq; | |
2962 | int i; | |
2963 | ||
2964 | for (i = 0; i < dev->online_queues; i++) { | |
2965 | nvmeq = dev->queues[i]; | |
2966 | ||
42483228 | 2967 | if (!nvmeq->tags || !(*nvmeq->tags)) |
a4aea562 MB |
2968 | continue; |
2969 | ||
2970 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, | |
42483228 | 2971 | blk_mq_tags_cpumask(*nvmeq->tags)); |
a4aea562 MB |
2972 | } |
2973 | } | |
2974 | ||
f0b50732 KB |
2975 | static int nvme_dev_start(struct nvme_dev *dev) |
2976 | { | |
2977 | int result; | |
b9afca3e | 2978 | bool start_thread = false; |
f0b50732 KB |
2979 | |
2980 | result = nvme_dev_map(dev); | |
2981 | if (result) | |
2982 | return result; | |
2983 | ||
2984 | result = nvme_configure_admin_queue(dev); | |
2985 | if (result) | |
2986 | goto unmap; | |
2987 | ||
2988 | spin_lock(&dev_list_lock); | |
b9afca3e DM |
2989 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { |
2990 | start_thread = true; | |
2991 | nvme_thread = NULL; | |
2992 | } | |
f0b50732 KB |
2993 | list_add(&dev->node, &dev_list); |
2994 | spin_unlock(&dev_list_lock); | |
2995 | ||
b9afca3e DM |
2996 | if (start_thread) { |
2997 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
387caa5a | 2998 | wake_up_all(&nvme_kthread_wait); |
b9afca3e DM |
2999 | } else |
3000 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
3001 | ||
3002 | if (IS_ERR_OR_NULL(nvme_thread)) { | |
3003 | result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
3004 | goto disable; | |
3005 | } | |
a4aea562 MB |
3006 | |
3007 | nvme_init_queue(dev->queues[0], 0); | |
0fb59cbc KB |
3008 | result = nvme_alloc_admin_tags(dev); |
3009 | if (result) | |
3010 | goto disable; | |
b9afca3e | 3011 | |
f0b50732 | 3012 | result = nvme_setup_io_queues(dev); |
badc34d4 | 3013 | if (result) |
0fb59cbc | 3014 | goto free_tags; |
f0b50732 | 3015 | |
a4aea562 MB |
3016 | nvme_set_irq_hints(dev); |
3017 | ||
1efccc9d | 3018 | dev->event_limit = 1; |
d82e8bfd | 3019 | return result; |
f0b50732 | 3020 | |
0fb59cbc KB |
3021 | free_tags: |
3022 | nvme_dev_remove_admin(dev); | |
4af0e21c KB |
3023 | blk_put_queue(dev->admin_q); |
3024 | dev->admin_q = NULL; | |
3025 | dev->queues[0]->tags = NULL; | |
f0b50732 | 3026 | disable: |
a1a5ef99 | 3027 | nvme_disable_queue(dev, 0); |
b9afca3e | 3028 | nvme_dev_list_remove(dev); |
f0b50732 KB |
3029 | unmap: |
3030 | nvme_dev_unmap(dev); | |
3031 | return result; | |
3032 | } | |
3033 | ||
9a6b9458 KB |
3034 | static int nvme_remove_dead_ctrl(void *arg) |
3035 | { | |
3036 | struct nvme_dev *dev = (struct nvme_dev *)arg; | |
e75ec752 | 3037 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
3038 | |
3039 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 3040 | pci_stop_and_remove_bus_device_locked(pdev); |
9a6b9458 KB |
3041 | kref_put(&dev->kref, nvme_free_dev); |
3042 | return 0; | |
3043 | } | |
3044 | ||
3045 | static void nvme_remove_disks(struct work_struct *ws) | |
3046 | { | |
9a6b9458 KB |
3047 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); |
3048 | ||
5a92e700 | 3049 | nvme_free_queues(dev, 1); |
302c6727 | 3050 | nvme_dev_remove(dev); |
9a6b9458 KB |
3051 | } |
3052 | ||
3053 | static int nvme_dev_resume(struct nvme_dev *dev) | |
3054 | { | |
3055 | int ret; | |
3056 | ||
3057 | ret = nvme_dev_start(dev); | |
badc34d4 | 3058 | if (ret) |
9a6b9458 | 3059 | return ret; |
badc34d4 | 3060 | if (dev->online_queues < 2) { |
9a6b9458 | 3061 | spin_lock(&dev_list_lock); |
9ca97374 | 3062 | dev->reset_workfn = nvme_remove_disks; |
9a6b9458 KB |
3063 | queue_work(nvme_workq, &dev->reset_work); |
3064 | spin_unlock(&dev_list_lock); | |
c9d3bf88 KB |
3065 | } else { |
3066 | nvme_unfreeze_queues(dev); | |
ffe7704d | 3067 | nvme_dev_add(dev); |
c9d3bf88 | 3068 | nvme_set_irq_hints(dev); |
9a6b9458 KB |
3069 | } |
3070 | return 0; | |
3071 | } | |
3072 | ||
de3eff2b KB |
3073 | static void nvme_dead_ctrl(struct nvme_dev *dev) |
3074 | { | |
3075 | dev_warn(dev->dev, "Device failed to resume\n"); | |
3076 | kref_get(&dev->kref); | |
3077 | if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d", | |
3078 | dev->instance))) { | |
3079 | dev_err(dev->dev, | |
3080 | "Failed to start controller remove task\n"); | |
3081 | kref_put(&dev->kref, nvme_free_dev); | |
3082 | } | |
3083 | } | |
3084 | ||
9a6b9458 KB |
3085 | static void nvme_dev_reset(struct nvme_dev *dev) |
3086 | { | |
ffe7704d KB |
3087 | bool in_probe = work_busy(&dev->probe_work); |
3088 | ||
9a6b9458 | 3089 | nvme_dev_shutdown(dev); |
ffe7704d KB |
3090 | |
3091 | /* Synchronize with device probe so that work will see failure status | |
3092 | * and exit gracefully without trying to schedule another reset */ | |
3093 | flush_work(&dev->probe_work); | |
3094 | ||
3095 | /* Fail this device if reset occured during probe to avoid | |
3096 | * infinite initialization loops. */ | |
3097 | if (in_probe) { | |
de3eff2b | 3098 | nvme_dead_ctrl(dev); |
ffe7704d | 3099 | return; |
9a6b9458 | 3100 | } |
ffe7704d KB |
3101 | /* Schedule device resume asynchronously so the reset work is available |
3102 | * to cleanup errors that may occur during reinitialization */ | |
3103 | schedule_work(&dev->probe_work); | |
9a6b9458 KB |
3104 | } |
3105 | ||
3106 | static void nvme_reset_failed_dev(struct work_struct *ws) | |
3107 | { | |
3108 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); | |
3109 | nvme_dev_reset(dev); | |
3110 | } | |
3111 | ||
9ca97374 TH |
3112 | static void nvme_reset_workfn(struct work_struct *work) |
3113 | { | |
3114 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); | |
3115 | dev->reset_workfn(work); | |
3116 | } | |
3117 | ||
4cc06521 KB |
3118 | static int nvme_reset(struct nvme_dev *dev) |
3119 | { | |
3120 | int ret = -EBUSY; | |
3121 | ||
3122 | if (!dev->admin_q || blk_queue_dying(dev->admin_q)) | |
3123 | return -ENODEV; | |
3124 | ||
3125 | spin_lock(&dev_list_lock); | |
3126 | if (!work_pending(&dev->reset_work)) { | |
3127 | dev->reset_workfn = nvme_reset_failed_dev; | |
3128 | queue_work(nvme_workq, &dev->reset_work); | |
3129 | ret = 0; | |
3130 | } | |
3131 | spin_unlock(&dev_list_lock); | |
3132 | ||
3133 | if (!ret) { | |
3134 | flush_work(&dev->reset_work); | |
ffe7704d | 3135 | flush_work(&dev->probe_work); |
4cc06521 KB |
3136 | return 0; |
3137 | } | |
3138 | ||
3139 | return ret; | |
3140 | } | |
3141 | ||
3142 | static ssize_t nvme_sysfs_reset(struct device *dev, | |
3143 | struct device_attribute *attr, const char *buf, | |
3144 | size_t count) | |
3145 | { | |
3146 | struct nvme_dev *ndev = dev_get_drvdata(dev); | |
3147 | int ret; | |
3148 | ||
3149 | ret = nvme_reset(ndev); | |
3150 | if (ret < 0) | |
3151 | return ret; | |
3152 | ||
3153 | return count; | |
3154 | } | |
3155 | static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset); | |
3156 | ||
2e1d8448 | 3157 | static void nvme_async_probe(struct work_struct *work); |
8d85fce7 | 3158 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 3159 | { |
a4aea562 | 3160 | int node, result = -ENOMEM; |
b60503ba MW |
3161 | struct nvme_dev *dev; |
3162 | ||
a4aea562 MB |
3163 | node = dev_to_node(&pdev->dev); |
3164 | if (node == NUMA_NO_NODE) | |
3165 | set_dev_node(&pdev->dev, 0); | |
3166 | ||
3167 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
3168 | if (!dev) |
3169 | return -ENOMEM; | |
a4aea562 MB |
3170 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
3171 | GFP_KERNEL, node); | |
b60503ba MW |
3172 | if (!dev->entry) |
3173 | goto free; | |
a4aea562 MB |
3174 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
3175 | GFP_KERNEL, node); | |
b60503ba MW |
3176 | if (!dev->queues) |
3177 | goto free; | |
3178 | ||
3179 | INIT_LIST_HEAD(&dev->namespaces); | |
9ca97374 TH |
3180 | dev->reset_workfn = nvme_reset_failed_dev; |
3181 | INIT_WORK(&dev->reset_work, nvme_reset_workfn); | |
e75ec752 | 3182 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 3183 | pci_set_drvdata(pdev, dev); |
cd58ad7d QSA |
3184 | result = nvme_set_instance(dev); |
3185 | if (result) | |
a96d4f5c | 3186 | goto put_pci; |
b60503ba | 3187 | |
091b6092 MW |
3188 | result = nvme_setup_prp_pools(dev); |
3189 | if (result) | |
0877cb0d | 3190 | goto release; |
091b6092 | 3191 | |
fb35e914 | 3192 | kref_init(&dev->kref); |
b3fffdef KB |
3193 | dev->device = device_create(nvme_class, &pdev->dev, |
3194 | MKDEV(nvme_char_major, dev->instance), | |
3195 | dev, "nvme%d", dev->instance); | |
3196 | if (IS_ERR(dev->device)) { | |
3197 | result = PTR_ERR(dev->device); | |
2e1d8448 | 3198 | goto release_pools; |
b3fffdef KB |
3199 | } |
3200 | get_device(dev->device); | |
4cc06521 KB |
3201 | dev_set_drvdata(dev->device, dev); |
3202 | ||
3203 | result = device_create_file(dev->device, &dev_attr_reset_controller); | |
3204 | if (result) | |
3205 | goto put_dev; | |
740216fc | 3206 | |
e6e96d73 | 3207 | INIT_LIST_HEAD(&dev->node); |
a5768aa8 | 3208 | INIT_WORK(&dev->scan_work, nvme_dev_scan); |
2e1d8448 KB |
3209 | INIT_WORK(&dev->probe_work, nvme_async_probe); |
3210 | schedule_work(&dev->probe_work); | |
b60503ba MW |
3211 | return 0; |
3212 | ||
4cc06521 KB |
3213 | put_dev: |
3214 | device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance)); | |
3215 | put_device(dev->device); | |
0877cb0d | 3216 | release_pools: |
091b6092 | 3217 | nvme_release_prp_pools(dev); |
0877cb0d KB |
3218 | release: |
3219 | nvme_release_instance(dev); | |
a96d4f5c | 3220 | put_pci: |
e75ec752 | 3221 | put_device(dev->dev); |
b60503ba MW |
3222 | free: |
3223 | kfree(dev->queues); | |
3224 | kfree(dev->entry); | |
3225 | kfree(dev); | |
3226 | return result; | |
3227 | } | |
3228 | ||
2e1d8448 KB |
3229 | static void nvme_async_probe(struct work_struct *work) |
3230 | { | |
3231 | struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work); | |
2e1d8448 | 3232 | |
de3eff2b KB |
3233 | if (nvme_dev_resume(dev) && !work_busy(&dev->reset_work)) |
3234 | nvme_dead_ctrl(dev); | |
2e1d8448 KB |
3235 | } |
3236 | ||
f0d54a54 KB |
3237 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
3238 | { | |
a6739479 | 3239 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 3240 | |
a6739479 KB |
3241 | if (prepare) |
3242 | nvme_dev_shutdown(dev); | |
3243 | else | |
3244 | nvme_dev_resume(dev); | |
f0d54a54 KB |
3245 | } |
3246 | ||
09ece142 KB |
3247 | static void nvme_shutdown(struct pci_dev *pdev) |
3248 | { | |
3249 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
3250 | nvme_dev_shutdown(dev); | |
3251 | } | |
3252 | ||
8d85fce7 | 3253 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
3254 | { |
3255 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
3256 | |
3257 | spin_lock(&dev_list_lock); | |
3258 | list_del_init(&dev->node); | |
3259 | spin_unlock(&dev_list_lock); | |
3260 | ||
3261 | pci_set_drvdata(pdev, NULL); | |
2e1d8448 | 3262 | flush_work(&dev->probe_work); |
9a6b9458 | 3263 | flush_work(&dev->reset_work); |
a5768aa8 | 3264 | flush_work(&dev->scan_work); |
4cc06521 | 3265 | device_remove_file(dev->device, &dev_attr_reset_controller); |
c9d3bf88 | 3266 | nvme_dev_remove(dev); |
3399a3f7 | 3267 | nvme_dev_shutdown(dev); |
a4aea562 | 3268 | nvme_dev_remove_admin(dev); |
b3fffdef | 3269 | device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance)); |
a1a5ef99 | 3270 | nvme_free_queues(dev, 0); |
8ffaadf7 | 3271 | nvme_release_cmb(dev); |
9a6b9458 | 3272 | nvme_release_prp_pools(dev); |
5e82e952 | 3273 | kref_put(&dev->kref, nvme_free_dev); |
b60503ba MW |
3274 | } |
3275 | ||
3276 | /* These functions are yet to be implemented */ | |
3277 | #define nvme_error_detected NULL | |
3278 | #define nvme_dump_registers NULL | |
3279 | #define nvme_link_reset NULL | |
3280 | #define nvme_slot_reset NULL | |
3281 | #define nvme_error_resume NULL | |
cd638946 | 3282 | |
671a6018 | 3283 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
3284 | static int nvme_suspend(struct device *dev) |
3285 | { | |
3286 | struct pci_dev *pdev = to_pci_dev(dev); | |
3287 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
3288 | ||
3289 | nvme_dev_shutdown(ndev); | |
3290 | return 0; | |
3291 | } | |
3292 | ||
3293 | static int nvme_resume(struct device *dev) | |
3294 | { | |
3295 | struct pci_dev *pdev = to_pci_dev(dev); | |
3296 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 3297 | |
9a6b9458 | 3298 | if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) { |
9ca97374 | 3299 | ndev->reset_workfn = nvme_reset_failed_dev; |
9a6b9458 KB |
3300 | queue_work(nvme_workq, &ndev->reset_work); |
3301 | } | |
3302 | return 0; | |
cd638946 | 3303 | } |
671a6018 | 3304 | #endif |
cd638946 KB |
3305 | |
3306 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 3307 | |
1d352035 | 3308 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
3309 | .error_detected = nvme_error_detected, |
3310 | .mmio_enabled = nvme_dump_registers, | |
3311 | .link_reset = nvme_link_reset, | |
3312 | .slot_reset = nvme_slot_reset, | |
3313 | .resume = nvme_error_resume, | |
f0d54a54 | 3314 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
3315 | }; |
3316 | ||
3317 | /* Move to pci_ids.h later */ | |
3318 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
3319 | ||
6eb0d698 | 3320 | static const struct pci_device_id nvme_id_table[] = { |
b60503ba MW |
3321 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
3322 | { 0, } | |
3323 | }; | |
3324 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
3325 | ||
3326 | static struct pci_driver nvme_driver = { | |
3327 | .name = "nvme", | |
3328 | .id_table = nvme_id_table, | |
3329 | .probe = nvme_probe, | |
8d85fce7 | 3330 | .remove = nvme_remove, |
09ece142 | 3331 | .shutdown = nvme_shutdown, |
cd638946 KB |
3332 | .driver = { |
3333 | .pm = &nvme_dev_pm_ops, | |
3334 | }, | |
b60503ba MW |
3335 | .err_handler = &nvme_err_handler, |
3336 | }; | |
3337 | ||
3338 | static int __init nvme_init(void) | |
3339 | { | |
0ac13140 | 3340 | int result; |
1fa6aead | 3341 | |
b9afca3e | 3342 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 3343 | |
9a6b9458 KB |
3344 | nvme_workq = create_singlethread_workqueue("nvme"); |
3345 | if (!nvme_workq) | |
b9afca3e | 3346 | return -ENOMEM; |
9a6b9458 | 3347 | |
5c42ea16 KB |
3348 | result = register_blkdev(nvme_major, "nvme"); |
3349 | if (result < 0) | |
9a6b9458 | 3350 | goto kill_workq; |
5c42ea16 | 3351 | else if (result > 0) |
0ac13140 | 3352 | nvme_major = result; |
b60503ba | 3353 | |
b3fffdef KB |
3354 | result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme", |
3355 | &nvme_dev_fops); | |
3356 | if (result < 0) | |
3357 | goto unregister_blkdev; | |
3358 | else if (result > 0) | |
3359 | nvme_char_major = result; | |
3360 | ||
3361 | nvme_class = class_create(THIS_MODULE, "nvme"); | |
c727040b AK |
3362 | if (IS_ERR(nvme_class)) { |
3363 | result = PTR_ERR(nvme_class); | |
b3fffdef | 3364 | goto unregister_chrdev; |
c727040b | 3365 | } |
b3fffdef | 3366 | |
f3db22fe KB |
3367 | result = pci_register_driver(&nvme_driver); |
3368 | if (result) | |
b3fffdef | 3369 | goto destroy_class; |
1fa6aead | 3370 | return 0; |
b60503ba | 3371 | |
b3fffdef KB |
3372 | destroy_class: |
3373 | class_destroy(nvme_class); | |
3374 | unregister_chrdev: | |
3375 | __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme"); | |
1fa6aead | 3376 | unregister_blkdev: |
b60503ba | 3377 | unregister_blkdev(nvme_major, "nvme"); |
9a6b9458 KB |
3378 | kill_workq: |
3379 | destroy_workqueue(nvme_workq); | |
b60503ba MW |
3380 | return result; |
3381 | } | |
3382 | ||
3383 | static void __exit nvme_exit(void) | |
3384 | { | |
3385 | pci_unregister_driver(&nvme_driver); | |
3386 | unregister_blkdev(nvme_major, "nvme"); | |
9a6b9458 | 3387 | destroy_workqueue(nvme_workq); |
b3fffdef KB |
3388 | class_destroy(nvme_class); |
3389 | __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme"); | |
b9afca3e | 3390 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 3391 | _nvme_check_size(); |
b60503ba MW |
3392 | } |
3393 | ||
3394 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
3395 | MODULE_LICENSE("GPL"); | |
c78b4713 | 3396 | MODULE_VERSION("1.0"); |
b60503ba MW |
3397 | module_init(nvme_init); |
3398 | module_exit(nvme_exit); |