NVMe: Skip orderly shutdown on failed devices
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
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1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
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13 */
14
15#include <linux/nvme.h>
16#include <linux/bio.h>
8de05535 17#include <linux/bitops.h>
b60503ba 18#include <linux/blkdev.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
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21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
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26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
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31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
42f61420 36#include <linux/percpu.h>
be7b6275 37#include <linux/poison.h>
c3bfe717 38#include <linux/ptrace.h>
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39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
5d0f6131 42#include <scsi/sg.h>
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43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
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45#include <trace/events/block.h>
46
9d43cf64 47#define NVME_Q_DEPTH 1024
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48#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
49#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
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50#define ADMIN_TIMEOUT (admin_timeout * HZ)
51#define IOD_TIMEOUT (retry_time * HZ)
52
53static unsigned char admin_timeout = 60;
54module_param(admin_timeout, byte, 0644);
55MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 56
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57unsigned char nvme_io_timeout = 30;
58module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 59MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 60
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61static unsigned char retry_time = 30;
62module_param(retry_time, byte, 0644);
63MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
64
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65static int nvme_major;
66module_param(nvme_major, int, 0);
67
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68static int use_threaded_interrupts;
69module_param(use_threaded_interrupts, int, 0);
70
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71static DEFINE_SPINLOCK(dev_list_lock);
72static LIST_HEAD(dev_list);
73static struct task_struct *nvme_thread;
9a6b9458 74static struct workqueue_struct *nvme_workq;
b9afca3e 75static wait_queue_head_t nvme_kthread_wait;
f3db22fe 76static struct notifier_block nvme_nb;
1fa6aead 77
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78static void nvme_reset_failed_dev(struct work_struct *ws);
79
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80struct async_cmd_info {
81 struct kthread_work work;
82 struct kthread_worker *worker;
83 u32 result;
84 int status;
85 void *ctx;
86};
1fa6aead 87
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88/*
89 * An NVM Express queue. Each device has at least two (one for admin
90 * commands and one for I/O commands).
91 */
92struct nvme_queue {
5a92e700 93 struct rcu_head r_head;
b60503ba 94 struct device *q_dmadev;
091b6092 95 struct nvme_dev *dev;
3193f07b 96 char irqname[24]; /* nvme4294967295-65535\0 */
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97 spinlock_t q_lock;
98 struct nvme_command *sq_cmds;
99 volatile struct nvme_completion *cqes;
100 dma_addr_t sq_dma_addr;
101 dma_addr_t cq_dma_addr;
102 wait_queue_head_t sq_full;
1fa6aead 103 wait_queue_t sq_cong_wait;
b60503ba 104 struct bio_list sq_cong;
edd10d33 105 struct list_head iod_bio;
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106 u32 __iomem *q_db;
107 u16 q_depth;
108 u16 cq_vector;
109 u16 sq_head;
110 u16 sq_tail;
111 u16 cq_head;
c30341dc 112 u16 qid;
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113 u8 cq_phase;
114 u8 cqe_seen;
22404274 115 u8 q_suspended;
42f61420 116 cpumask_var_t cpu_mask;
4d115420 117 struct async_cmd_info cmdinfo;
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118 unsigned long cmdid_data[];
119};
120
121/*
122 * Check we didin't inadvertently grow the command struct
123 */
124static inline void _nvme_check_size(void)
125{
126 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 131 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 132 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
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133 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
136 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 137 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
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138}
139
edd10d33 140typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
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141 struct nvme_completion *);
142
e85248e5 143struct nvme_cmd_info {
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144 nvme_completion_fn fn;
145 void *ctx;
e85248e5 146 unsigned long timeout;
c30341dc 147 int aborted;
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148};
149
150static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
151{
152 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
153}
154
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155static unsigned nvme_queue_extra(int depth)
156{
157 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
158}
159
b60503ba 160/**
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161 * alloc_cmdid() - Allocate a Command ID
162 * @nvmeq: The queue that will be used for this command
163 * @ctx: A pointer that will be passed to the handler
c2f5b650 164 * @handler: The function to call on completion
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165 *
166 * Allocate a Command ID for a queue. The data passed in will
167 * be passed to the completion handler. This is implemented by using
168 * the bottom two bits of the ctx pointer to store the handler ID.
169 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
170 * We can change this if it becomes a problem.
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171 *
172 * May be called with local interrupts disabled and the q_lock held,
173 * or with interrupts enabled and no locks held.
b60503ba 174 */
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175static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
176 nvme_completion_fn handler, unsigned timeout)
b60503ba 177{
e6d15f79 178 int depth = nvmeq->q_depth - 1;
e85248e5 179 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
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180 int cmdid;
181
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182 do {
183 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
184 if (cmdid >= depth)
185 return -EBUSY;
186 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
187
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188 info[cmdid].fn = handler;
189 info[cmdid].ctx = ctx;
e85248e5 190 info[cmdid].timeout = jiffies + timeout;
c30341dc 191 info[cmdid].aborted = 0;
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192 return cmdid;
193}
194
195static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 196 nvme_completion_fn handler, unsigned timeout)
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197{
198 int cmdid;
199 wait_event_killable(nvmeq->sq_full,
e85248e5 200 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
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201 return (cmdid < 0) ? -EINTR : cmdid;
202}
203
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204/* Special values must be less than 0x1000 */
205#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
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206#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
207#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
208#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
53562be7 209#define CMD_CTX_ABORT (0x318 + CMD_CTX_BASE)
6fccf938 210#define CMD_CTX_ASYNC (0x31C + CMD_CTX_BASE)
be7b6275 211
edd10d33 212static void special_completion(struct nvme_queue *nvmeq, void *ctx,
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213 struct nvme_completion *cqe)
214{
215 if (ctx == CMD_CTX_CANCELLED)
216 return;
c30341dc 217 if (ctx == CMD_CTX_ABORT) {
edd10d33 218 ++nvmeq->dev->abort_limit;
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219 return;
220 }
c2f5b650 221 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 222 dev_warn(nvmeq->q_dmadev,
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223 "completed id %d twice on queue %d\n",
224 cqe->command_id, le16_to_cpup(&cqe->sq_id));
225 return;
226 }
227 if (ctx == CMD_CTX_INVALID) {
edd10d33 228 dev_warn(nvmeq->q_dmadev,
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229 "invalid id %d completed on queue %d\n",
230 cqe->command_id, le16_to_cpup(&cqe->sq_id));
231 return;
232 }
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233 if (ctx == CMD_CTX_ASYNC) {
234 u32 result = le32_to_cpup(&cqe->result);
235 u16 status = le16_to_cpup(&cqe->status) >> 1;
236
237 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
238 ++nvmeq->dev->event_limit;
239 if (status == NVME_SC_SUCCESS)
240 dev_warn(nvmeq->q_dmadev,
241 "async event result %08x\n", result);
242 return;
243 }
c2f5b650 244
edd10d33 245 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
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246}
247
edd10d33 248static void async_completion(struct nvme_queue *nvmeq, void *ctx,
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249 struct nvme_completion *cqe)
250{
251 struct async_cmd_info *cmdinfo = ctx;
252 cmdinfo->result = le32_to_cpup(&cqe->result);
253 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
254 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
255}
256
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257/*
258 * Called with local interrupts disabled and the q_lock held. May not sleep.
259 */
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260static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
261 nvme_completion_fn *fn)
b60503ba 262{
c2f5b650 263 void *ctx;
e85248e5 264 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 265
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266 if (cmdid >= nvmeq->q_depth || !info[cmdid].fn) {
267 if (fn)
268 *fn = special_completion;
48e3d398 269 return CMD_CTX_INVALID;
c2f5b650 270 }
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271 if (fn)
272 *fn = info[cmdid].fn;
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273 ctx = info[cmdid].ctx;
274 info[cmdid].fn = special_completion;
e85248e5 275 info[cmdid].ctx = CMD_CTX_COMPLETED;
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276 clear_bit(cmdid, nvmeq->cmdid_data);
277 wake_up(&nvmeq->sq_full);
c2f5b650 278 return ctx;
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279}
280
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281static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
282 nvme_completion_fn *fn)
3c0cf138 283{
c2f5b650 284 void *ctx;
e85248e5 285 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
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286 if (fn)
287 *fn = info[cmdid].fn;
288 ctx = info[cmdid].ctx;
289 info[cmdid].fn = special_completion;
e85248e5 290 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 291 return ctx;
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292}
293
5a92e700 294static struct nvme_queue *raw_nvmeq(struct nvme_dev *dev, int qid)
b60503ba 295{
5a92e700 296 return rcu_dereference_raw(dev->queues[qid]);
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297}
298
4f5099af 299static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) __acquires(RCU)
5a92e700 300{
a51afb54 301 struct nvme_queue *nvmeq;
42f61420 302 unsigned queue_id = get_cpu_var(*dev->io_queue);
a51afb54 303
5a92e700 304 rcu_read_lock();
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305 nvmeq = rcu_dereference(dev->queues[queue_id]);
306 if (nvmeq)
307 return nvmeq;
308
309 rcu_read_unlock();
310 put_cpu_var(*dev->io_queue);
311 return NULL;
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312}
313
4f5099af 314static void put_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
b60503ba 315{
5a92e700 316 rcu_read_unlock();
42f61420 317 put_cpu_var(nvmeq->dev->io_queue);
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318}
319
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320static struct nvme_queue *lock_nvmeq(struct nvme_dev *dev, int q_idx)
321 __acquires(RCU)
b60503ba 322{
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323 struct nvme_queue *nvmeq;
324
4f5099af 325 rcu_read_lock();
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326 nvmeq = rcu_dereference(dev->queues[q_idx]);
327 if (nvmeq)
328 return nvmeq;
329
330 rcu_read_unlock();
331 return NULL;
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332}
333
334static void unlock_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
335{
336 rcu_read_unlock();
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337}
338
339/**
714a7a22 340 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
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341 * @nvmeq: The queue to use
342 * @cmd: The command to send
343 *
344 * Safe to use from interrupt context
345 */
346static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
347{
348 unsigned long flags;
349 u16 tail;
b60503ba 350 spin_lock_irqsave(&nvmeq->q_lock, flags);
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351 if (nvmeq->q_suspended) {
352 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
353 return -EBUSY;
354 }
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355 tail = nvmeq->sq_tail;
356 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
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357 if (++tail == nvmeq->q_depth)
358 tail = 0;
7547881d 359 writel(tail, nvmeq->q_db);
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360 nvmeq->sq_tail = tail;
361 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
362
363 return 0;
364}
365
eca18b23 366static __le64 **iod_list(struct nvme_iod *iod)
e025344c 367{
eca18b23 368 return ((void *)iod) + iod->offset;
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369}
370
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371/*
372 * Will slightly overestimate the number of pages needed. This is OK
373 * as it only leads to a small amount of wasted memory for the lifetime of
374 * the I/O.
375 */
1d090624 376static int nvme_npages(unsigned size, struct nvme_dev *dev)
eca18b23 377{
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378 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
379 return DIV_ROUND_UP(8 * nprps, dev->page_size - 8);
eca18b23 380}
b60503ba 381
eca18b23 382static struct nvme_iod *
1d090624 383nvme_alloc_iod(unsigned nseg, unsigned nbytes, struct nvme_dev *dev, gfp_t gfp)
b60503ba 384{
eca18b23 385 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
1d090624 386 sizeof(__le64 *) * nvme_npages(nbytes, dev) +
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387 sizeof(struct scatterlist) * nseg, gfp);
388
389 if (iod) {
390 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
391 iod->npages = -1;
392 iod->length = nbytes;
2b196034 393 iod->nents = 0;
edd10d33 394 iod->first_dma = 0ULL;
6198221f 395 iod->start_time = jiffies;
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396 }
397
398 return iod;
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399}
400
5d0f6131 401void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 402{
1d090624 403 const int last_prp = dev->page_size / 8 - 1;
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404 int i;
405 __le64 **list = iod_list(iod);
406 dma_addr_t prp_dma = iod->first_dma;
407
408 if (iod->npages == 0)
409 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
410 for (i = 0; i < iod->npages; i++) {
411 __le64 *prp_list = list[i];
412 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
413 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
414 prp_dma = next_prp_dma;
415 }
416 kfree(iod);
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417}
418
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419static void nvme_start_io_acct(struct bio *bio)
420{
421 struct gendisk *disk = bio->bi_bdev->bd_disk;
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422 if (blk_queue_io_stat(disk->queue)) {
423 const int rw = bio_data_dir(bio);
424 int cpu = part_stat_lock();
425 part_round_stats(cpu, &disk->part0);
426 part_stat_inc(cpu, &disk->part0, ios[rw]);
427 part_stat_add(cpu, &disk->part0, sectors[rw],
428 bio_sectors(bio));
429 part_inc_in_flight(&disk->part0, rw);
430 part_stat_unlock();
431 }
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432}
433
434static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
435{
436 struct gendisk *disk = bio->bi_bdev->bd_disk;
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437 if (blk_queue_io_stat(disk->queue)) {
438 const int rw = bio_data_dir(bio);
439 unsigned long duration = jiffies - start_time;
440 int cpu = part_stat_lock();
441 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
442 part_round_stats(cpu, &disk->part0);
443 part_dec_in_flight(&disk->part0, rw);
444 part_stat_unlock();
445 }
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446}
447
edd10d33 448static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
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449 struct nvme_completion *cqe)
450{
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451 struct nvme_iod *iod = ctx;
452 struct bio *bio = iod->private;
b60503ba 453 u16 status = le16_to_cpup(&cqe->status) >> 1;
3291fa57 454 int error = 0;
b60503ba 455
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456 if (unlikely(status)) {
457 if (!(status & NVME_SC_DNR ||
458 bio->bi_rw & REQ_FAILFAST_MASK) &&
459 (jiffies - iod->start_time) < IOD_TIMEOUT) {
460 if (!waitqueue_active(&nvmeq->sq_full))
461 add_wait_queue(&nvmeq->sq_full,
462 &nvmeq->sq_cong_wait);
463 list_add_tail(&iod->node, &nvmeq->iod_bio);
464 wake_up(&nvmeq->sq_full);
465 return;
466 }
3291fa57 467 error = -EIO;
edd10d33 468 }
9e59d091 469 if (iod->nents) {
edd10d33 470 dma_unmap_sg(nvmeq->q_dmadev, iod->sg, iod->nents,
b60503ba 471 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
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472 nvme_end_io_acct(bio, iod->start_time);
473 }
edd10d33 474 nvme_free_iod(nvmeq->dev, iod);
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475
476 trace_block_bio_complete(bdev_get_queue(bio->bi_bdev), bio, error);
477 bio_endio(bio, error);
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478}
479
184d2944 480/* length is in bytes. gfp flags indicates whether we may sleep. */
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481int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
482 gfp_t gfp)
ff22b54f 483{
99802a7a 484 struct dma_pool *pool;
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485 int length = total_len;
486 struct scatterlist *sg = iod->sg;
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487 int dma_len = sg_dma_len(sg);
488 u64 dma_addr = sg_dma_address(sg);
489 int offset = offset_in_page(dma_addr);
e025344c 490 __le64 *prp_list;
eca18b23 491 __le64 **list = iod_list(iod);
e025344c 492 dma_addr_t prp_dma;
eca18b23 493 int nprps, i;
1d090624 494 u32 page_size = dev->page_size;
ff22b54f 495
1d090624 496 length -= (page_size - offset);
ff22b54f 497 if (length <= 0)
eca18b23 498 return total_len;
ff22b54f 499
1d090624 500 dma_len -= (page_size - offset);
ff22b54f 501 if (dma_len) {
1d090624 502 dma_addr += (page_size - offset);
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503 } else {
504 sg = sg_next(sg);
505 dma_addr = sg_dma_address(sg);
506 dma_len = sg_dma_len(sg);
507 }
508
1d090624 509 if (length <= page_size) {
edd10d33 510 iod->first_dma = dma_addr;
eca18b23 511 return total_len;
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512 }
513
1d090624 514 nprps = DIV_ROUND_UP(length, page_size);
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515 if (nprps <= (256 / 8)) {
516 pool = dev->prp_small_pool;
eca18b23 517 iod->npages = 0;
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518 } else {
519 pool = dev->prp_page_pool;
eca18b23 520 iod->npages = 1;
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521 }
522
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523 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
524 if (!prp_list) {
edd10d33 525 iod->first_dma = dma_addr;
eca18b23 526 iod->npages = -1;
1d090624 527 return (total_len - length) + page_size;
b77954cb 528 }
eca18b23
MW
529 list[0] = prp_list;
530 iod->first_dma = prp_dma;
e025344c
SMM
531 i = 0;
532 for (;;) {
1d090624 533 if (i == page_size >> 3) {
e025344c 534 __le64 *old_prp_list = prp_list;
b77954cb 535 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW
536 if (!prp_list)
537 return total_len - length;
538 list[iod->npages++] = prp_list;
7523d834
MW
539 prp_list[0] = old_prp_list[i - 1];
540 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
541 i = 1;
e025344c
SMM
542 }
543 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB
544 dma_len -= page_size;
545 dma_addr += page_size;
546 length -= page_size;
e025344c
SMM
547 if (length <= 0)
548 break;
549 if (dma_len > 0)
550 continue;
551 BUG_ON(dma_len < 0);
552 sg = sg_next(sg);
553 dma_addr = sg_dma_address(sg);
554 dma_len = sg_dma_len(sg);
ff22b54f
MW
555 }
556
eca18b23 557 return total_len;
ff22b54f
MW
558}
559
427e9708 560static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
20d0189b 561 int len)
427e9708 562{
20d0189b
KO
563 struct bio *split = bio_split(bio, len >> 9, GFP_ATOMIC, NULL);
564 if (!split)
427e9708
KB
565 return -ENOMEM;
566
3291fa57
KB
567 trace_block_split(bdev_get_queue(bio->bi_bdev), bio,
568 split->bi_iter.bi_sector);
20d0189b
KO
569 bio_chain(split, bio);
570
edd10d33 571 if (!waitqueue_active(&nvmeq->sq_full))
427e9708 572 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
20d0189b
KO
573 bio_list_add(&nvmeq->sq_cong, split);
574 bio_list_add(&nvmeq->sq_cong, bio);
edd10d33 575 wake_up(&nvmeq->sq_full);
427e9708
KB
576
577 return 0;
578}
579
1ad2f893
MW
580/* NVMe scatterlists require no holes in the virtual address */
581#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
582 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
583
427e9708 584static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
b60503ba
MW
585 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
586{
7988613b
KO
587 struct bio_vec bvec, bvprv;
588 struct bvec_iter iter;
76830840 589 struct scatterlist *sg = NULL;
7988613b
KO
590 int length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size;
591 int first = 1;
159b67d7
KB
592
593 if (nvmeq->dev->stripe_size)
594 split_len = nvmeq->dev->stripe_size -
4f024f37
KO
595 ((bio->bi_iter.bi_sector << 9) &
596 (nvmeq->dev->stripe_size - 1));
b60503ba 597
eca18b23 598 sg_init_table(iod->sg, psegs);
7988613b
KO
599 bio_for_each_segment(bvec, bio, iter) {
600 if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) {
601 sg->length += bvec.bv_len;
76830840 602 } else {
7988613b
KO
603 if (!first && BIOVEC_NOT_VIRT_MERGEABLE(&bvprv, &bvec))
604 return nvme_split_and_submit(bio, nvmeq,
20d0189b 605 length);
427e9708 606
eca18b23 607 sg = sg ? sg + 1 : iod->sg;
7988613b
KO
608 sg_set_page(sg, bvec.bv_page,
609 bvec.bv_len, bvec.bv_offset);
76830840
MW
610 nsegs++;
611 }
159b67d7 612
7988613b 613 if (split_len - length < bvec.bv_len)
20d0189b 614 return nvme_split_and_submit(bio, nvmeq, split_len);
7988613b 615 length += bvec.bv_len;
76830840 616 bvprv = bvec;
7988613b 617 first = 0;
b60503ba 618 }
eca18b23 619 iod->nents = nsegs;
76830840 620 sg_mark_end(sg);
427e9708 621 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
1ad2f893 622 return -ENOMEM;
427e9708 623
4f024f37 624 BUG_ON(length != bio->bi_iter.bi_size);
1ad2f893 625 return length;
b60503ba
MW
626}
627
0e5e4f0e
KB
628static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
629 struct bio *bio, struct nvme_iod *iod, int cmdid)
630{
edd10d33
KB
631 struct nvme_dsm_range *range =
632 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB
633 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
634
0e5e4f0e 635 range->cattr = cpu_to_le32(0);
4f024f37
KO
636 range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift);
637 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
0e5e4f0e
KB
638
639 memset(cmnd, 0, sizeof(*cmnd));
640 cmnd->dsm.opcode = nvme_cmd_dsm;
641 cmnd->dsm.command_id = cmdid;
642 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
643 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
644 cmnd->dsm.nr = 0;
645 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
646
647 if (++nvmeq->sq_tail == nvmeq->q_depth)
648 nvmeq->sq_tail = 0;
649 writel(nvmeq->sq_tail, nvmeq->q_db);
650
651 return 0;
652}
653
00df5cb4
MW
654static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
655 int cmdid)
656{
657 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
658
659 memset(cmnd, 0, sizeof(*cmnd));
660 cmnd->common.opcode = nvme_cmd_flush;
661 cmnd->common.command_id = cmdid;
662 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
663
664 if (++nvmeq->sq_tail == nvmeq->q_depth)
665 nvmeq->sq_tail = 0;
666 writel(nvmeq->sq_tail, nvmeq->q_db);
667
668 return 0;
669}
670
edd10d33 671static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod)
b60503ba 672{
edd10d33
KB
673 struct bio *bio = iod->private;
674 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
ff22b54f 675 struct nvme_command *cmnd;
edd10d33 676 int cmdid;
b60503ba
MW
677 u16 control;
678 u32 dsmgmt;
00df5cb4 679
ff976d72 680 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 681 if (unlikely(cmdid < 0))
edd10d33 682 return cmdid;
b60503ba 683
edd10d33
KB
684 if (bio->bi_rw & REQ_DISCARD)
685 return nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
53562be7 686 if (bio->bi_rw & REQ_FLUSH)
00df5cb4
MW
687 return nvme_submit_flush(nvmeq, ns, cmdid);
688
b60503ba
MW
689 control = 0;
690 if (bio->bi_rw & REQ_FUA)
691 control |= NVME_RW_FUA;
692 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
693 control |= NVME_RW_LR;
694
695 dsmgmt = 0;
696 if (bio->bi_rw & REQ_RAHEAD)
697 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
698
ff22b54f 699 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 700 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 701
edd10d33 702 cmnd->rw.opcode = bio_data_dir(bio) ? nvme_cmd_write : nvme_cmd_read;
ff22b54f
MW
703 cmnd->rw.command_id = cmdid;
704 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB
705 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
706 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
4f024f37 707 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
edd10d33
KB
708 cmnd->rw.length =
709 cpu_to_le16((bio->bi_iter.bi_size >> ns->lba_shift) - 1);
ff22b54f
MW
710 cmnd->rw.control = cpu_to_le16(control);
711 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 712
b60503ba
MW
713 if (++nvmeq->sq_tail == nvmeq->q_depth)
714 nvmeq->sq_tail = 0;
7547881d 715 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 716
1974b1ae 717 return 0;
edd10d33
KB
718}
719
53562be7
KB
720static int nvme_split_flush_data(struct nvme_queue *nvmeq, struct bio *bio)
721{
722 struct bio *split = bio_clone(bio, GFP_ATOMIC);
723 if (!split)
724 return -ENOMEM;
725
726 split->bi_iter.bi_size = 0;
727 split->bi_phys_segments = 0;
728 bio->bi_rw &= ~REQ_FLUSH;
729 bio_chain(split, bio);
730
731 if (!waitqueue_active(&nvmeq->sq_full))
732 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
733 bio_list_add(&nvmeq->sq_cong, split);
734 bio_list_add(&nvmeq->sq_cong, bio);
735 wake_up_process(nvme_thread);
736
737 return 0;
738}
739
edd10d33
KB
740/*
741 * Called with local interrupts disabled and the q_lock held. May not sleep.
742 */
743static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
744 struct bio *bio)
745{
746 struct nvme_iod *iod;
747 int psegs = bio_phys_segments(ns->queue, bio);
748 int result;
749
53562be7
KB
750 if ((bio->bi_rw & REQ_FLUSH) && psegs)
751 return nvme_split_flush_data(nvmeq, bio);
edd10d33 752
1d090624 753 iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, ns->dev, GFP_ATOMIC);
edd10d33
KB
754 if (!iod)
755 return -ENOMEM;
756
757 iod->private = bio;
758 if (bio->bi_rw & REQ_DISCARD) {
759 void *range;
760 /*
761 * We reuse the small pool to allocate the 16-byte range here
762 * as it is not worth having a special pool for these or
763 * additional cases to handle freeing the iod.
764 */
765 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
766 GFP_ATOMIC,
767 &iod->first_dma);
768 if (!range) {
769 result = -ENOMEM;
770 goto free_iod;
771 }
772 iod_list(iod)[0] = (__le64 *)range;
773 iod->npages = 0;
774 } else if (psegs) {
775 result = nvme_map_bio(nvmeq, iod, bio,
776 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
777 psegs);
778 if (result <= 0)
779 goto free_iod;
780 if (nvme_setup_prps(nvmeq->dev, iod, result, GFP_ATOMIC) !=
781 result) {
782 result = -ENOMEM;
783 goto free_iod;
784 }
785 nvme_start_io_acct(bio);
786 }
787 if (unlikely(nvme_submit_iod(nvmeq, iod))) {
788 if (!waitqueue_active(&nvmeq->sq_full))
789 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
790 list_add_tail(&iod->node, &nvmeq->iod_bio);
791 }
792 return 0;
1974b1ae 793
eca18b23
MW
794 free_iod:
795 nvme_free_iod(nvmeq->dev, iod);
eeee3226 796 return result;
b60503ba
MW
797}
798
e9539f47 799static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 800{
82123460 801 u16 head, phase;
b60503ba 802
b60503ba 803 head = nvmeq->cq_head;
82123460 804 phase = nvmeq->cq_phase;
b60503ba
MW
805
806 for (;;) {
c2f5b650
MW
807 void *ctx;
808 nvme_completion_fn fn;
b60503ba 809 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 810 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW
811 break;
812 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
813 if (++head == nvmeq->q_depth) {
814 head = 0;
82123460 815 phase = !phase;
b60503ba
MW
816 }
817
c2f5b650 818 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
edd10d33 819 fn(nvmeq, ctx, &cqe);
b60503ba
MW
820 }
821
822 /* If the controller ignores the cq head doorbell and continuously
823 * writes to the queue, it is theoretically possible to wrap around
824 * the queue twice and mistakenly return IRQ_NONE. Linux only
825 * requires that 0.1% of your interrupts are handled, so this isn't
826 * a big problem.
827 */
82123460 828 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 829 return 0;
b60503ba 830
b80d5ccc 831 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 832 nvmeq->cq_head = head;
82123460 833 nvmeq->cq_phase = phase;
b60503ba 834
e9539f47
MW
835 nvmeq->cqe_seen = 1;
836 return 1;
b60503ba
MW
837}
838
7d822457
MW
839static void nvme_make_request(struct request_queue *q, struct bio *bio)
840{
841 struct nvme_ns *ns = q->queuedata;
842 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
843 int result = -EBUSY;
844
cd638946 845 if (!nvmeq) {
cd638946
KB
846 bio_endio(bio, -EIO);
847 return;
848 }
849
7d822457 850 spin_lock_irq(&nvmeq->q_lock);
22404274 851 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
7d822457
MW
852 result = nvme_submit_bio_queue(nvmeq, ns, bio);
853 if (unlikely(result)) {
edd10d33 854 if (!waitqueue_active(&nvmeq->sq_full))
7d822457
MW
855 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
856 bio_list_add(&nvmeq->sq_cong, bio);
857 }
858
859 nvme_process_cq(nvmeq);
860 spin_unlock_irq(&nvmeq->q_lock);
861 put_nvmeq(nvmeq);
862}
863
b60503ba 864static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW
865{
866 irqreturn_t result;
867 struct nvme_queue *nvmeq = data;
868 spin_lock(&nvmeq->q_lock);
e9539f47
MW
869 nvme_process_cq(nvmeq);
870 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
871 nvmeq->cqe_seen = 0;
58ffacb5
MW
872 spin_unlock(&nvmeq->q_lock);
873 return result;
874}
875
876static irqreturn_t nvme_irq_check(int irq, void *data)
877{
878 struct nvme_queue *nvmeq = data;
879 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
880 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
881 return IRQ_NONE;
882 return IRQ_WAKE_THREAD;
883}
884
3c0cf138
MW
885static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
886{
887 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 888 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW
889 spin_unlock_irq(&nvmeq->q_lock);
890}
891
c2f5b650
MW
892struct sync_cmd_info {
893 struct task_struct *task;
894 u32 result;
895 int status;
896};
897
edd10d33 898static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW
899 struct nvme_completion *cqe)
900{
901 struct sync_cmd_info *cmdinfo = ctx;
902 cmdinfo->result = le32_to_cpup(&cqe->result);
903 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
904 wake_up_process(cmdinfo->task);
905}
906
b60503ba
MW
907/*
908 * Returns 0 on success. If the result is negative, it's a Linux error code;
909 * if the result is positive, it's an NVM Express status code
910 */
4f5099af
KB
911static int nvme_submit_sync_cmd(struct nvme_dev *dev, int q_idx,
912 struct nvme_command *cmd,
5d0f6131 913 u32 *result, unsigned timeout)
b60503ba 914{
4f5099af 915 int cmdid, ret;
b60503ba 916 struct sync_cmd_info cmdinfo;
4f5099af
KB
917 struct nvme_queue *nvmeq;
918
919 nvmeq = lock_nvmeq(dev, q_idx);
a51afb54 920 if (!nvmeq)
4f5099af 921 return -ENODEV;
b60503ba
MW
922
923 cmdinfo.task = current;
924 cmdinfo.status = -EINTR;
925
4f5099af
KB
926 cmdid = alloc_cmdid(nvmeq, &cmdinfo, sync_completion, timeout);
927 if (cmdid < 0) {
928 unlock_nvmeq(nvmeq);
b60503ba 929 return cmdid;
4f5099af 930 }
b60503ba
MW
931 cmd->common.command_id = cmdid;
932
3c0cf138 933 set_current_state(TASK_KILLABLE);
4f5099af
KB
934 ret = nvme_submit_cmd(nvmeq, cmd);
935 if (ret) {
936 free_cmdid(nvmeq, cmdid, NULL);
937 unlock_nvmeq(nvmeq);
938 set_current_state(TASK_RUNNING);
939 return ret;
940 }
941 unlock_nvmeq(nvmeq);
78f8d257 942 schedule_timeout(timeout);
b60503ba 943
3c0cf138 944 if (cmdinfo.status == -EINTR) {
4f5099af 945 nvmeq = lock_nvmeq(dev, q_idx);
a51afb54 946 if (nvmeq) {
4f5099af 947 nvme_abort_command(nvmeq, cmdid);
a51afb54
KB
948 unlock_nvmeq(nvmeq);
949 }
3c0cf138
MW
950 return -EINTR;
951 }
952
b60503ba
MW
953 if (result)
954 *result = cmdinfo.result;
955
956 return cmdinfo.status;
957}
958
4d115420
KB
959static int nvme_submit_async_cmd(struct nvme_queue *nvmeq,
960 struct nvme_command *cmd,
961 struct async_cmd_info *cmdinfo, unsigned timeout)
962{
963 int cmdid;
964
965 cmdid = alloc_cmdid_killable(nvmeq, cmdinfo, async_completion, timeout);
966 if (cmdid < 0)
967 return cmdid;
968 cmdinfo->status = -EINTR;
969 cmd->common.command_id = cmdid;
4f5099af 970 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB
971}
972
5d0f6131 973int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
b60503ba
MW
974 u32 *result)
975{
4f5099af
KB
976 return nvme_submit_sync_cmd(dev, 0, cmd, result, ADMIN_TIMEOUT);
977}
978
979int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
980 u32 *result)
981{
982 return nvme_submit_sync_cmd(dev, smp_processor_id() + 1, cmd, result,
983 NVME_IO_TIMEOUT);
b60503ba
MW
984}
985
4d115420
KB
986static int nvme_submit_admin_cmd_async(struct nvme_dev *dev,
987 struct nvme_command *cmd, struct async_cmd_info *cmdinfo)
988{
5a92e700 989 return nvme_submit_async_cmd(raw_nvmeq(dev, 0), cmd, cmdinfo,
4d115420
KB
990 ADMIN_TIMEOUT);
991}
992
b60503ba
MW
993static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
994{
995 int status;
996 struct nvme_command c;
997
998 memset(&c, 0, sizeof(c));
999 c.delete_queue.opcode = opcode;
1000 c.delete_queue.qid = cpu_to_le16(id);
1001
1002 status = nvme_submit_admin_cmd(dev, &c, NULL);
1003 if (status)
1004 return -EIO;
1005 return 0;
1006}
1007
1008static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1009 struct nvme_queue *nvmeq)
1010{
1011 int status;
1012 struct nvme_command c;
1013 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1014
1015 memset(&c, 0, sizeof(c));
1016 c.create_cq.opcode = nvme_admin_create_cq;
1017 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1018 c.create_cq.cqid = cpu_to_le16(qid);
1019 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1020 c.create_cq.cq_flags = cpu_to_le16(flags);
1021 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1022
1023 status = nvme_submit_admin_cmd(dev, &c, NULL);
1024 if (status)
1025 return -EIO;
1026 return 0;
1027}
1028
1029static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1030 struct nvme_queue *nvmeq)
1031{
1032 int status;
1033 struct nvme_command c;
1034 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1035
1036 memset(&c, 0, sizeof(c));
1037 c.create_sq.opcode = nvme_admin_create_sq;
1038 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1039 c.create_sq.sqid = cpu_to_le16(qid);
1040 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1041 c.create_sq.sq_flags = cpu_to_le16(flags);
1042 c.create_sq.cqid = cpu_to_le16(qid);
1043
1044 status = nvme_submit_admin_cmd(dev, &c, NULL);
1045 if (status)
1046 return -EIO;
1047 return 0;
1048}
1049
1050static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1051{
1052 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1053}
1054
1055static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1056{
1057 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1058}
1059
5d0f6131 1060int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW
1061 dma_addr_t dma_addr)
1062{
1063 struct nvme_command c;
1064
1065 memset(&c, 0, sizeof(c));
1066 c.identify.opcode = nvme_admin_identify;
1067 c.identify.nsid = cpu_to_le32(nsid);
1068 c.identify.prp1 = cpu_to_le64(dma_addr);
1069 c.identify.cns = cpu_to_le32(cns);
1070
1071 return nvme_submit_admin_cmd(dev, &c, NULL);
1072}
1073
5d0f6131 1074int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1075 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW
1076{
1077 struct nvme_command c;
1078
1079 memset(&c, 0, sizeof(c));
1080 c.features.opcode = nvme_admin_get_features;
a42cecce 1081 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW
1082 c.features.prp1 = cpu_to_le64(dma_addr);
1083 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1084
08df1e05 1085 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW
1086}
1087
5d0f6131
VV
1088int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1089 dma_addr_t dma_addr, u32 *result)
df348139
MW
1090{
1091 struct nvme_command c;
1092
1093 memset(&c, 0, sizeof(c));
1094 c.features.opcode = nvme_admin_set_features;
1095 c.features.prp1 = cpu_to_le64(dma_addr);
1096 c.features.fid = cpu_to_le32(fid);
1097 c.features.dword11 = cpu_to_le32(dword11);
1098
bc5fc7e4
MW
1099 return nvme_submit_admin_cmd(dev, &c, result);
1100}
1101
c30341dc
KB
1102/**
1103 * nvme_abort_cmd - Attempt aborting a command
1104 * @cmdid: Command id of a timed out IO
1105 * @queue: The queue with timed out IO
1106 *
1107 * Schedule controller reset if the command was already aborted once before and
1108 * still hasn't been returned to the driver, or if this is the admin queue.
1109 */
1110static void nvme_abort_cmd(int cmdid, struct nvme_queue *nvmeq)
1111{
1112 int a_cmdid;
1113 struct nvme_command cmd;
1114 struct nvme_dev *dev = nvmeq->dev;
1115 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
5a92e700 1116 struct nvme_queue *adminq;
c30341dc
KB
1117
1118 if (!nvmeq->qid || info[cmdid].aborted) {
1119 if (work_busy(&dev->reset_work))
1120 return;
1121 list_del_init(&dev->node);
1122 dev_warn(&dev->pci_dev->dev,
1123 "I/O %d QID %d timeout, reset controller\n", cmdid,
1124 nvmeq->qid);
9ca97374 1125 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc
KB
1126 queue_work(nvme_workq, &dev->reset_work);
1127 return;
1128 }
1129
1130 if (!dev->abort_limit)
1131 return;
1132
5a92e700
KB
1133 adminq = rcu_dereference(dev->queues[0]);
1134 a_cmdid = alloc_cmdid(adminq, CMD_CTX_ABORT, special_completion,
c30341dc
KB
1135 ADMIN_TIMEOUT);
1136 if (a_cmdid < 0)
1137 return;
1138
1139 memset(&cmd, 0, sizeof(cmd));
1140 cmd.abort.opcode = nvme_admin_abort_cmd;
1141 cmd.abort.cid = cmdid;
1142 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1143 cmd.abort.command_id = a_cmdid;
1144
1145 --dev->abort_limit;
1146 info[cmdid].aborted = 1;
1147 info[cmdid].timeout = jiffies + ADMIN_TIMEOUT;
1148
1149 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", cmdid,
1150 nvmeq->qid);
5a92e700 1151 nvme_submit_cmd(adminq, &cmd);
c30341dc
KB
1152}
1153
a09115b2
MW
1154/**
1155 * nvme_cancel_ios - Cancel outstanding I/Os
1156 * @queue: The queue to cancel I/Os on
1157 * @timeout: True to only cancel I/Os which have timed out
1158 */
1159static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1160{
1161 int depth = nvmeq->q_depth - 1;
1162 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1163 unsigned long now = jiffies;
1164 int cmdid;
1165
1166 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1167 void *ctx;
1168 nvme_completion_fn fn;
1169 static struct nvme_completion cqe = {
af2d9ca7 1170 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
a09115b2
MW
1171 };
1172
1173 if (timeout && !time_after(now, info[cmdid].timeout))
1174 continue;
053ab702
KB
1175 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1176 continue;
6fccf938
KB
1177 if (timeout && info[cmdid].ctx == CMD_CTX_ASYNC)
1178 continue;
c30341dc
KB
1179 if (timeout && nvmeq->dev->initialized) {
1180 nvme_abort_cmd(cmdid, nvmeq);
1181 continue;
1182 }
1183 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", cmdid,
1184 nvmeq->qid);
a09115b2 1185 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
edd10d33 1186 fn(nvmeq, ctx, &cqe);
a09115b2
MW
1187 }
1188}
1189
5a92e700 1190static void nvme_free_queue(struct rcu_head *r)
9e866774 1191{
5a92e700
KB
1192 struct nvme_queue *nvmeq = container_of(r, struct nvme_queue, r_head);
1193
22404274
KB
1194 spin_lock_irq(&nvmeq->q_lock);
1195 while (bio_list_peek(&nvmeq->sq_cong)) {
1196 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1197 bio_endio(bio, -EIO);
1198 }
edd10d33
KB
1199 while (!list_empty(&nvmeq->iod_bio)) {
1200 static struct nvme_completion cqe = {
1201 .status = cpu_to_le16(
1202 (NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1),
1203 };
1204 struct nvme_iod *iod = list_first_entry(&nvmeq->iod_bio,
1205 struct nvme_iod,
1206 node);
1207 list_del(&iod->node);
1208 bio_completion(nvmeq, iod, &cqe);
1209 }
22404274
KB
1210 spin_unlock_irq(&nvmeq->q_lock);
1211
9e866774
MW
1212 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1213 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1214 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1215 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
42f61420
KB
1216 if (nvmeq->qid)
1217 free_cpumask_var(nvmeq->cpu_mask);
9e866774
MW
1218 kfree(nvmeq);
1219}
1220
a1a5ef99 1221static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB
1222{
1223 int i;
1224
a1a5ef99 1225 for (i = dev->queue_count - 1; i >= lowest; i--) {
5a92e700
KB
1226 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
1227 rcu_assign_pointer(dev->queues[i], NULL);
1228 call_rcu(&nvmeq->r_head, nvme_free_queue);
22404274 1229 dev->queue_count--;
22404274
KB
1230 }
1231}
1232
4d115420
KB
1233/**
1234 * nvme_suspend_queue - put queue into suspended state
1235 * @nvmeq - queue to suspend
1236 *
1237 * Returns 1 if already suspended, 0 otherwise.
1238 */
1239static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1240{
4d115420 1241 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1242
a09115b2 1243 spin_lock_irq(&nvmeq->q_lock);
22404274
KB
1244 if (nvmeq->q_suspended) {
1245 spin_unlock_irq(&nvmeq->q_lock);
4d115420 1246 return 1;
3295874b 1247 }
22404274 1248 nvmeq->q_suspended = 1;
42f61420 1249 nvmeq->dev->online_queues--;
a09115b2
MW
1250 spin_unlock_irq(&nvmeq->q_lock);
1251
aba2080f
MW
1252 irq_set_affinity_hint(vector, NULL);
1253 free_irq(vector, nvmeq);
b60503ba 1254
4d115420
KB
1255 return 0;
1256}
b60503ba 1257
4d115420
KB
1258static void nvme_clear_queue(struct nvme_queue *nvmeq)
1259{
22404274
KB
1260 spin_lock_irq(&nvmeq->q_lock);
1261 nvme_process_cq(nvmeq);
1262 nvme_cancel_ios(nvmeq, false);
1263 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW
1264}
1265
4d115420
KB
1266static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1267{
5a92e700 1268 struct nvme_queue *nvmeq = raw_nvmeq(dev, qid);
4d115420
KB
1269
1270 if (!nvmeq)
1271 return;
1272 if (nvme_suspend_queue(nvmeq))
1273 return;
1274
0e53d180
KB
1275 /* Don't tell the adapter to delete the admin queue.
1276 * Don't tell a removed adapter to delete IO queues. */
1277 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW
1278 adapter_delete_sq(dev, qid);
1279 adapter_delete_cq(dev, qid);
1280 }
4d115420 1281 nvme_clear_queue(nvmeq);
b60503ba
MW
1282}
1283
1284static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1285 int depth, int vector)
1286{
1287 struct device *dmadev = &dev->pci_dev->dev;
22404274 1288 unsigned extra = nvme_queue_extra(depth);
b60503ba
MW
1289 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1290 if (!nvmeq)
1291 return NULL;
1292
4d51abf9
JP
1293 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1294 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW
1295 if (!nvmeq->cqes)
1296 goto free_nvmeq;
b60503ba
MW
1297
1298 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1299 &nvmeq->sq_dma_addr, GFP_KERNEL);
1300 if (!nvmeq->sq_cmds)
1301 goto free_cqdma;
1302
42f61420
KB
1303 if (qid && !zalloc_cpumask_var(&nvmeq->cpu_mask, GFP_KERNEL))
1304 goto free_sqdma;
1305
b60503ba 1306 nvmeq->q_dmadev = dmadev;
091b6092 1307 nvmeq->dev = dev;
3193f07b
MW
1308 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1309 dev->instance, qid);
b60503ba
MW
1310 spin_lock_init(&nvmeq->q_lock);
1311 nvmeq->cq_head = 0;
82123460 1312 nvmeq->cq_phase = 1;
b60503ba 1313 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1314 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1315 bio_list_init(&nvmeq->sq_cong);
edd10d33 1316 INIT_LIST_HEAD(&nvmeq->iod_bio);
b80d5ccc 1317 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW
1318 nvmeq->q_depth = depth;
1319 nvmeq->cq_vector = vector;
c30341dc 1320 nvmeq->qid = qid;
22404274
KB
1321 nvmeq->q_suspended = 1;
1322 dev->queue_count++;
5a92e700 1323 rcu_assign_pointer(dev->queues[qid], nvmeq);
b60503ba
MW
1324
1325 return nvmeq;
1326
42f61420
KB
1327 free_sqdma:
1328 dma_free_coherent(dmadev, SQ_SIZE(depth), (void *)nvmeq->sq_cmds,
1329 nvmeq->sq_dma_addr);
b60503ba 1330 free_cqdma:
68b8eca5 1331 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW
1332 nvmeq->cq_dma_addr);
1333 free_nvmeq:
1334 kfree(nvmeq);
1335 return NULL;
1336}
1337
3001082c
MW
1338static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1339 const char *name)
1340{
58ffacb5
MW
1341 if (use_threaded_interrupts)
1342 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1343 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1344 name, nvmeq);
3001082c 1345 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1346 IRQF_SHARED, name, nvmeq);
3001082c
MW
1347}
1348
22404274 1349static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1350{
22404274
KB
1351 struct nvme_dev *dev = nvmeq->dev;
1352 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
b60503ba 1353
22404274
KB
1354 nvmeq->sq_tail = 0;
1355 nvmeq->cq_head = 0;
1356 nvmeq->cq_phase = 1;
b80d5ccc 1357 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274
KB
1358 memset(nvmeq->cmdid_data, 0, extra);
1359 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1360 nvme_cancel_ios(nvmeq, false);
1361 nvmeq->q_suspended = 0;
42f61420 1362 dev->online_queues++;
22404274
KB
1363}
1364
1365static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1366{
1367 struct nvme_dev *dev = nvmeq->dev;
1368 int result;
3f85d50b 1369
b60503ba
MW
1370 result = adapter_alloc_cq(dev, qid, nvmeq);
1371 if (result < 0)
22404274 1372 return result;
b60503ba
MW
1373
1374 result = adapter_alloc_sq(dev, qid, nvmeq);
1375 if (result < 0)
1376 goto release_cq;
1377
3193f07b 1378 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW
1379 if (result < 0)
1380 goto release_sq;
1381
0a8d44cb 1382 spin_lock_irq(&nvmeq->q_lock);
22404274 1383 nvme_init_queue(nvmeq, qid);
0a8d44cb 1384 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB
1385
1386 return result;
b60503ba
MW
1387
1388 release_sq:
1389 adapter_delete_sq(dev, qid);
1390 release_cq:
1391 adapter_delete_cq(dev, qid);
22404274 1392 return result;
b60503ba
MW
1393}
1394
ba47e386
MW
1395static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1396{
1397 unsigned long timeout;
1398 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1399
1400 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1401
1402 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1403 msleep(100);
1404 if (fatal_signal_pending(current))
1405 return -EINTR;
1406 if (time_after(jiffies, timeout)) {
1407 dev_err(&dev->pci_dev->dev,
27e8166c
MW
1408 "Device not ready; aborting %s\n", enabled ?
1409 "initialisation" : "reset");
ba47e386
MW
1410 return -ENODEV;
1411 }
1412 }
1413
1414 return 0;
1415}
1416
1417/*
1418 * If the device has been passed off to us in an enabled state, just clear
1419 * the enabled bit. The spec says we should set the 'shutdown notification
1420 * bits', but doing so may cause the device to complete commands to the
1421 * admin queue ... and we don't know what memory that might be pointing at!
1422 */
1423static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1424{
01079522
DM
1425 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1426 dev->ctrl_config &= ~NVME_CC_ENABLE;
1427 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1428
ba47e386
MW
1429 return nvme_wait_ready(dev, cap, false);
1430}
1431
1432static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1433{
01079522
DM
1434 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1435 dev->ctrl_config |= NVME_CC_ENABLE;
1436 writel(dev->ctrl_config, &dev->bar->cc);
1437
ba47e386
MW
1438 return nvme_wait_ready(dev, cap, true);
1439}
1440
1894d8f1
KB
1441static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1442{
1443 unsigned long timeout;
1894d8f1 1444
01079522
DM
1445 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1446 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1447
1448 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1
KB
1449
1450 timeout = 2 * HZ + jiffies;
1451 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1452 NVME_CSTS_SHST_CMPLT) {
1453 msleep(100);
1454 if (fatal_signal_pending(current))
1455 return -EINTR;
1456 if (time_after(jiffies, timeout)) {
1457 dev_err(&dev->pci_dev->dev,
1458 "Device shutdown incomplete; abort shutdown\n");
1459 return -ENODEV;
1460 }
1461 }
1462
1463 return 0;
1464}
1465
8d85fce7 1466static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1467{
ba47e386 1468 int result;
b60503ba 1469 u32 aqa;
ba47e386 1470 u64 cap = readq(&dev->bar->cap);
b60503ba 1471 struct nvme_queue *nvmeq;
1d090624
KB
1472 unsigned page_shift = PAGE_SHIFT;
1473 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1474 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1475
1476 if (page_shift < dev_page_min) {
1477 dev_err(&dev->pci_dev->dev,
1478 "Minimum device page size (%u) too large for "
1479 "host (%u)\n", 1 << dev_page_min,
1480 1 << page_shift);
1481 return -ENODEV;
1482 }
1483 if (page_shift > dev_page_max) {
1484 dev_info(&dev->pci_dev->dev,
1485 "Device maximum page size (%u) smaller than "
1486 "host (%u); enabling work-around\n",
1487 1 << dev_page_max, 1 << page_shift);
1488 page_shift = dev_page_max;
1489 }
b60503ba 1490
ba47e386
MW
1491 result = nvme_disable_ctrl(dev, cap);
1492 if (result < 0)
1493 return result;
b60503ba 1494
5a92e700 1495 nvmeq = raw_nvmeq(dev, 0);
cd638946
KB
1496 if (!nvmeq) {
1497 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1498 if (!nvmeq)
1499 return -ENOMEM;
cd638946 1500 }
b60503ba
MW
1501
1502 aqa = nvmeq->q_depth - 1;
1503 aqa |= aqa << 16;
1504
1d090624
KB
1505 dev->page_size = 1 << page_shift;
1506
01079522 1507 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1508 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1509 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1510 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW
1511
1512 writel(aqa, &dev->bar->aqa);
1513 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1514 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1515
ba47e386 1516 result = nvme_enable_ctrl(dev, cap);
025c557a 1517 if (result)
cd638946 1518 return result;
9e866774 1519
3193f07b 1520 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1521 if (result)
cd638946 1522 return result;
025c557a 1523
0a8d44cb 1524 spin_lock_irq(&nvmeq->q_lock);
22404274 1525 nvme_init_queue(nvmeq, 0);
0a8d44cb 1526 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW
1527 return result;
1528}
1529
5d0f6131 1530struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1531 unsigned long addr, unsigned length)
b60503ba 1532{
36c14ed9 1533 int i, err, count, nents, offset;
7fc3cdab
MW
1534 struct scatterlist *sg;
1535 struct page **pages;
eca18b23 1536 struct nvme_iod *iod;
36c14ed9
MW
1537
1538 if (addr & 3)
eca18b23 1539 return ERR_PTR(-EINVAL);
5460fc03 1540 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1541 return ERR_PTR(-EINVAL);
7fc3cdab 1542
36c14ed9 1543 offset = offset_in_page(addr);
7fc3cdab
MW
1544 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1545 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC
1546 if (!pages)
1547 return ERR_PTR(-ENOMEM);
36c14ed9
MW
1548
1549 err = get_user_pages_fast(addr, count, 1, pages);
1550 if (err < count) {
1551 count = err;
1552 err = -EFAULT;
1553 goto put_pages;
1554 }
7fc3cdab 1555
6808c5fb 1556 err = -ENOMEM;
1d090624 1557 iod = nvme_alloc_iod(count, length, dev, GFP_KERNEL);
6808c5fb
S
1558 if (!iod)
1559 goto put_pages;
1560
eca18b23 1561 sg = iod->sg;
36c14ed9 1562 sg_init_table(sg, count);
d0ba1e49
MW
1563 for (i = 0; i < count; i++) {
1564 sg_set_page(&sg[i], pages[i],
5460fc03
DC
1565 min_t(unsigned, length, PAGE_SIZE - offset),
1566 offset);
d0ba1e49
MW
1567 length -= (PAGE_SIZE - offset);
1568 offset = 0;
7fc3cdab 1569 }
fe304c43 1570 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1571 iod->nents = count;
7fc3cdab 1572
7fc3cdab
MW
1573 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1574 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1575 if (!nents)
eca18b23 1576 goto free_iod;
b60503ba 1577
7fc3cdab 1578 kfree(pages);
eca18b23 1579 return iod;
b60503ba 1580
eca18b23
MW
1581 free_iod:
1582 kfree(iod);
7fc3cdab
MW
1583 put_pages:
1584 for (i = 0; i < count; i++)
1585 put_page(pages[i]);
1586 kfree(pages);
eca18b23 1587 return ERR_PTR(err);
7fc3cdab 1588}
b60503ba 1589
5d0f6131 1590void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1591 struct nvme_iod *iod)
7fc3cdab 1592{
1c2ad9fa 1593 int i;
b60503ba 1594
1c2ad9fa
MW
1595 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1596 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1597
1c2ad9fa
MW
1598 for (i = 0; i < iod->nents; i++)
1599 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1600}
b60503ba 1601
a53295b6
MW
1602static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1603{
1604 struct nvme_dev *dev = ns->dev;
a53295b6
MW
1605 struct nvme_user_io io;
1606 struct nvme_command c;
f410c680
KB
1607 unsigned length, meta_len;
1608 int status, i;
1609 struct nvme_iod *iod, *meta_iod = NULL;
1610 dma_addr_t meta_dma_addr;
1611 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW
1612
1613 if (copy_from_user(&io, uio, sizeof(io)))
1614 return -EFAULT;
6c7d4945 1615 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB
1616 meta_len = (io.nblocks + 1) * ns->ms;
1617
1618 if (meta_len && ((io.metadata & 3) || !io.metadata))
1619 return -EINVAL;
6c7d4945
MW
1620
1621 switch (io.opcode) {
1622 case nvme_cmd_write:
1623 case nvme_cmd_read:
6bbf1acd 1624 case nvme_cmd_compare:
eca18b23 1625 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1626 break;
6c7d4945 1627 default:
6bbf1acd 1628 return -EINVAL;
6c7d4945
MW
1629 }
1630
eca18b23
MW
1631 if (IS_ERR(iod))
1632 return PTR_ERR(iod);
a53295b6
MW
1633
1634 memset(&c, 0, sizeof(c));
1635 c.rw.opcode = io.opcode;
1636 c.rw.flags = io.flags;
6c7d4945 1637 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1638 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1639 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1640 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW
1641 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1642 c.rw.reftag = cpu_to_le32(io.reftag);
1643 c.rw.apptag = cpu_to_le16(io.apptag);
1644 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB
1645
1646 if (meta_len) {
1b56749e
KB
1647 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1648 meta_len);
f410c680
KB
1649 if (IS_ERR(meta_iod)) {
1650 status = PTR_ERR(meta_iod);
1651 meta_iod = NULL;
1652 goto unmap;
1653 }
1654
1655 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1656 &meta_dma_addr, GFP_KERNEL);
1657 if (!meta_mem) {
1658 status = -ENOMEM;
1659 goto unmap;
1660 }
1661
1662 if (io.opcode & 1) {
1663 int meta_offset = 0;
1664
1665 for (i = 0; i < meta_iod->nents; i++) {
1666 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1667 meta_iod->sg[i].offset;
1668 memcpy(meta_mem + meta_offset, meta,
1669 meta_iod->sg[i].length);
1670 kunmap_atomic(meta);
1671 meta_offset += meta_iod->sg[i].length;
1672 }
1673 }
1674
1675 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1676 }
1677
edd10d33
KB
1678 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1679 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1680 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1681
b77954cb
MW
1682 if (length != (io.nblocks + 1) << ns->lba_shift)
1683 status = -ENOMEM;
1684 else
4f5099af 1685 status = nvme_submit_io_cmd(dev, &c, NULL);
a53295b6 1686
f410c680
KB
1687 if (meta_len) {
1688 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1689 int meta_offset = 0;
1690
1691 for (i = 0; i < meta_iod->nents; i++) {
1692 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1693 meta_iod->sg[i].offset;
1694 memcpy(meta, meta_mem + meta_offset,
1695 meta_iod->sg[i].length);
1696 kunmap_atomic(meta);
1697 meta_offset += meta_iod->sg[i].length;
1698 }
1699 }
1700
1701 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1702 meta_dma_addr);
1703 }
1704
1705 unmap:
1c2ad9fa 1706 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1707 nvme_free_iod(dev, iod);
f410c680
KB
1708
1709 if (meta_iod) {
1710 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1711 nvme_free_iod(dev, meta_iod);
1712 }
1713
a53295b6
MW
1714 return status;
1715}
1716
50af8bae 1717static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1718 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1719{
6bbf1acd 1720 struct nvme_admin_cmd cmd;
6ee44cdc 1721 struct nvme_command c;
eca18b23 1722 int status, length;
c7d36ab8 1723 struct nvme_iod *uninitialized_var(iod);
94f370ca 1724 unsigned timeout;
6ee44cdc 1725
6bbf1acd
MW
1726 if (!capable(CAP_SYS_ADMIN))
1727 return -EACCES;
1728 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1729 return -EFAULT;
6ee44cdc
MW
1730
1731 memset(&c, 0, sizeof(c));
6bbf1acd
MW
1732 c.common.opcode = cmd.opcode;
1733 c.common.flags = cmd.flags;
1734 c.common.nsid = cpu_to_le32(cmd.nsid);
1735 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1736 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1737 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1738 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1739 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1740 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1741 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1742 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1743
1744 length = cmd.data_len;
1745 if (cmd.data_len) {
49742188
MW
1746 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1747 length);
eca18b23
MW
1748 if (IS_ERR(iod))
1749 return PTR_ERR(iod);
edd10d33
KB
1750 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1751 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1752 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW
1753 }
1754
94f370ca
KB
1755 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1756 ADMIN_TIMEOUT;
6bbf1acd 1757 if (length != cmd.data_len)
b77954cb
MW
1758 status = -ENOMEM;
1759 else
4f5099af 1760 status = nvme_submit_sync_cmd(dev, 0, &c, &cmd.result, timeout);
eca18b23 1761
6bbf1acd 1762 if (cmd.data_len) {
1c2ad9fa 1763 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1764 nvme_free_iod(dev, iod);
6bbf1acd 1765 }
f4f117f6 1766
cf90bc48 1767 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB
1768 sizeof(cmd.result)))
1769 status = -EFAULT;
1770
6ee44cdc
MW
1771 return status;
1772}
1773
b60503ba
MW
1774static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1775 unsigned long arg)
1776{
1777 struct nvme_ns *ns = bdev->bd_disk->private_data;
1778
1779 switch (cmd) {
6bbf1acd 1780 case NVME_IOCTL_ID:
c3bfe717 1781 force_successful_syscall_return();
6bbf1acd
MW
1782 return ns->ns_id;
1783 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1784 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW
1785 case NVME_IOCTL_SUBMIT_IO:
1786 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV
1787 case SG_GET_VERSION_NUM:
1788 return nvme_sg_get_version_num((void __user *)arg);
1789 case SG_IO:
1790 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW
1791 default:
1792 return -ENOTTY;
1793 }
1794}
1795
320a3827
KB
1796#ifdef CONFIG_COMPAT
1797static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1798 unsigned int cmd, unsigned long arg)
1799{
1800 struct nvme_ns *ns = bdev->bd_disk->private_data;
1801
1802 switch (cmd) {
1803 case SG_IO:
1804 return nvme_sg_io32(ns, arg);
1805 }
1806 return nvme_ioctl(bdev, mode, cmd, arg);
1807}
1808#else
1809#define nvme_compat_ioctl NULL
1810#endif
1811
9ac27090
KB
1812static int nvme_open(struct block_device *bdev, fmode_t mode)
1813{
1814 struct nvme_ns *ns = bdev->bd_disk->private_data;
1815 struct nvme_dev *dev = ns->dev;
1816
1817 kref_get(&dev->kref);
1818 return 0;
1819}
1820
1821static void nvme_free_dev(struct kref *kref);
1822
1823static void nvme_release(struct gendisk *disk, fmode_t mode)
1824{
1825 struct nvme_ns *ns = disk->private_data;
1826 struct nvme_dev *dev = ns->dev;
1827
1828 kref_put(&dev->kref, nvme_free_dev);
1829}
1830
4cc09e2d
KB
1831static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1832{
1833 /* some standard values */
1834 geo->heads = 1 << 6;
1835 geo->sectors = 1 << 5;
1836 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1837 return 0;
1838}
1839
b60503ba
MW
1840static const struct block_device_operations nvme_fops = {
1841 .owner = THIS_MODULE,
1842 .ioctl = nvme_ioctl,
320a3827 1843 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB
1844 .open = nvme_open,
1845 .release = nvme_release,
4cc09e2d 1846 .getgeo = nvme_getgeo,
b60503ba
MW
1847};
1848
edd10d33
KB
1849static void nvme_resubmit_iods(struct nvme_queue *nvmeq)
1850{
1851 struct nvme_iod *iod, *next;
1852
1853 list_for_each_entry_safe(iod, next, &nvmeq->iod_bio, node) {
1854 if (unlikely(nvme_submit_iod(nvmeq, iod)))
1855 break;
1856 list_del(&iod->node);
1857 if (bio_list_empty(&nvmeq->sq_cong) &&
1858 list_empty(&nvmeq->iod_bio))
1859 remove_wait_queue(&nvmeq->sq_full,
1860 &nvmeq->sq_cong_wait);
1861 }
1862}
1863
1fa6aead
MW
1864static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1865{
1866 while (bio_list_peek(&nvmeq->sq_cong)) {
1867 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1868 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
427e9708 1869
edd10d33
KB
1870 if (bio_list_empty(&nvmeq->sq_cong) &&
1871 list_empty(&nvmeq->iod_bio))
427e9708
KB
1872 remove_wait_queue(&nvmeq->sq_full,
1873 &nvmeq->sq_cong_wait);
1fa6aead 1874 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
edd10d33 1875 if (!waitqueue_active(&nvmeq->sq_full))
427e9708
KB
1876 add_wait_queue(&nvmeq->sq_full,
1877 &nvmeq->sq_cong_wait);
1fa6aead
MW
1878 bio_list_add_head(&nvmeq->sq_cong, bio);
1879 break;
1880 }
1881 }
1882}
1883
6fccf938
KB
1884static int nvme_submit_async_req(struct nvme_queue *nvmeq)
1885{
1886 struct nvme_command *c;
1887 int cmdid;
1888
1889 cmdid = alloc_cmdid(nvmeq, CMD_CTX_ASYNC, special_completion, 0);
1890 if (cmdid < 0)
1891 return cmdid;
1892
1893 c = &nvmeq->sq_cmds[nvmeq->sq_tail];
1894 memset(c, 0, sizeof(*c));
1895 c->common.opcode = nvme_admin_async_event;
1896 c->common.command_id = cmdid;
1897
1898 if (++nvmeq->sq_tail == nvmeq->q_depth)
1899 nvmeq->sq_tail = 0;
1900 writel(nvmeq->sq_tail, nvmeq->q_db);
1901
1902 return 0;
1903}
1904
1fa6aead
MW
1905static int nvme_kthread(void *data)
1906{
d4b4ff8e 1907 struct nvme_dev *dev, *next;
1fa6aead
MW
1908
1909 while (!kthread_should_stop()) {
564a232c 1910 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1911 spin_lock(&dev_list_lock);
d4b4ff8e 1912 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1913 int i;
d4b4ff8e
KB
1914 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1915 dev->initialized) {
1916 if (work_busy(&dev->reset_work))
1917 continue;
1918 list_del_init(&dev->node);
1919 dev_warn(&dev->pci_dev->dev,
1920 "Failed status, reset controller\n");
9ca97374 1921 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB
1922 queue_work(nvme_workq, &dev->reset_work);
1923 continue;
1924 }
5a92e700 1925 rcu_read_lock();
1fa6aead 1926 for (i = 0; i < dev->queue_count; i++) {
5a92e700
KB
1927 struct nvme_queue *nvmeq =
1928 rcu_dereference(dev->queues[i]);
740216fc
MW
1929 if (!nvmeq)
1930 continue;
1fa6aead 1931 spin_lock_irq(&nvmeq->q_lock);
22404274
KB
1932 if (nvmeq->q_suspended)
1933 goto unlock;
bc57a0f7 1934 nvme_process_cq(nvmeq);
a09115b2 1935 nvme_cancel_ios(nvmeq, true);
1fa6aead 1936 nvme_resubmit_bios(nvmeq);
edd10d33 1937 nvme_resubmit_iods(nvmeq);
6fccf938
KB
1938
1939 while ((i == 0) && (dev->event_limit > 0)) {
1940 if (nvme_submit_async_req(nvmeq))
1941 break;
1942 dev->event_limit--;
1943 }
22404274 1944 unlock:
1fa6aead
MW
1945 spin_unlock_irq(&nvmeq->q_lock);
1946 }
5a92e700 1947 rcu_read_unlock();
1fa6aead
MW
1948 }
1949 spin_unlock(&dev_list_lock);
acb7aa0d 1950 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW
1951 }
1952 return 0;
1953}
1954
0e5e4f0e
KB
1955static void nvme_config_discard(struct nvme_ns *ns)
1956{
1957 u32 logical_block_size = queue_logical_block_size(ns->queue);
1958 ns->queue->limits.discard_zeroes_data = 0;
1959 ns->queue->limits.discard_alignment = logical_block_size;
1960 ns->queue->limits.discard_granularity = logical_block_size;
1961 ns->queue->limits.max_discard_sectors = 0xffffffff;
1962 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1963}
1964
c3bfe717 1965static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW
1966 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1967{
1968 struct nvme_ns *ns;
1969 struct gendisk *disk;
1970 int lbaf;
1971
1972 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1973 return NULL;
1974
1975 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1976 if (!ns)
1977 return NULL;
1978 ns->queue = blk_alloc_queue(GFP_KERNEL);
1979 if (!ns->queue)
1980 goto out_free_ns;
4eeb9215
MW
1981 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1982 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1983 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b277da0a 1984 queue_flag_clear_unlocked(QUEUE_FLAG_ADD_RANDOM, ns->queue);
b60503ba
MW
1985 blk_queue_make_request(ns->queue, nvme_make_request);
1986 ns->dev = dev;
1987 ns->queue->queuedata = ns;
1988
469071a3 1989 disk = alloc_disk(0);
b60503ba
MW
1990 if (!disk)
1991 goto out_free_queue;
5aff9382 1992 ns->ns_id = nsid;
b60503ba
MW
1993 ns->disk = disk;
1994 lbaf = id->flbas & 0xf;
1995 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1996 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1997 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB
1998 if (dev->max_hw_sectors)
1999 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a7d2ce28
KB
2000 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2001 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW
2002
2003 disk->major = nvme_major;
469071a3 2004 disk->first_minor = 0;
b60503ba
MW
2005 disk->fops = &nvme_fops;
2006 disk->private_data = ns;
2007 disk->queue = ns->queue;
388f037f 2008 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 2009 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2010 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW
2011 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2012
0e5e4f0e
KB
2013 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2014 nvme_config_discard(ns);
2015
b60503ba
MW
2016 return ns;
2017
2018 out_free_queue:
2019 blk_cleanup_queue(ns->queue);
2020 out_free_ns:
2021 kfree(ns);
2022 return NULL;
2023}
2024
42f61420
KB
2025static int nvme_find_closest_node(int node)
2026{
2027 int n, val, min_val = INT_MAX, best_node = node;
2028
2029 for_each_online_node(n) {
2030 if (n == node)
2031 continue;
2032 val = node_distance(node, n);
2033 if (val < min_val) {
2034 min_val = val;
2035 best_node = n;
2036 }
2037 }
2038 return best_node;
2039}
2040
2041static void nvme_set_queue_cpus(cpumask_t *qmask, struct nvme_queue *nvmeq,
2042 int count)
2043{
2044 int cpu;
2045 for_each_cpu(cpu, qmask) {
2046 if (cpumask_weight(nvmeq->cpu_mask) >= count)
2047 break;
2048 if (!cpumask_test_and_set_cpu(cpu, nvmeq->cpu_mask))
2049 *per_cpu_ptr(nvmeq->dev->io_queue, cpu) = nvmeq->qid;
2050 }
2051}
2052
2053static void nvme_add_cpus(cpumask_t *mask, const cpumask_t *unassigned_cpus,
2054 const cpumask_t *new_mask, struct nvme_queue *nvmeq, int cpus_per_queue)
2055{
2056 int next_cpu;
2057 for_each_cpu(next_cpu, new_mask) {
2058 cpumask_or(mask, mask, get_cpu_mask(next_cpu));
2059 cpumask_or(mask, mask, topology_thread_cpumask(next_cpu));
2060 cpumask_and(mask, mask, unassigned_cpus);
2061 nvme_set_queue_cpus(mask, nvmeq, cpus_per_queue);
2062 }
2063}
2064
2065static void nvme_create_io_queues(struct nvme_dev *dev)
2066{
2067 unsigned i, max;
2068
2069 max = min(dev->max_qid, num_online_cpus());
2070 for (i = dev->queue_count; i <= max; i++)
2071 if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1))
2072 break;
2073
2074 max = min(dev->queue_count - 1, num_online_cpus());
2075 for (i = dev->online_queues; i <= max; i++)
2076 if (nvme_create_queue(raw_nvmeq(dev, i), i))
2077 break;
2078}
2079
2080/*
2081 * If there are fewer queues than online cpus, this will try to optimally
2082 * assign a queue to multiple cpus by grouping cpus that are "close" together:
2083 * thread siblings, core, socket, closest node, then whatever else is
2084 * available.
2085 */
2086static void nvme_assign_io_queues(struct nvme_dev *dev)
2087{
2088 unsigned cpu, cpus_per_queue, queues, remainder, i;
2089 cpumask_var_t unassigned_cpus;
2090
2091 nvme_create_io_queues(dev);
2092
2093 queues = min(dev->online_queues - 1, num_online_cpus());
2094 if (!queues)
2095 return;
2096
2097 cpus_per_queue = num_online_cpus() / queues;
2098 remainder = queues - (num_online_cpus() - queues * cpus_per_queue);
2099
2100 if (!alloc_cpumask_var(&unassigned_cpus, GFP_KERNEL))
2101 return;
2102
2103 cpumask_copy(unassigned_cpus, cpu_online_mask);
2104 cpu = cpumask_first(unassigned_cpus);
2105 for (i = 1; i <= queues; i++) {
2106 struct nvme_queue *nvmeq = lock_nvmeq(dev, i);
2107 cpumask_t mask;
2108
2109 cpumask_clear(nvmeq->cpu_mask);
2110 if (!cpumask_weight(unassigned_cpus)) {
2111 unlock_nvmeq(nvmeq);
2112 break;
2113 }
2114
2115 mask = *get_cpu_mask(cpu);
2116 nvme_set_queue_cpus(&mask, nvmeq, cpus_per_queue);
2117 if (cpus_weight(mask) < cpus_per_queue)
2118 nvme_add_cpus(&mask, unassigned_cpus,
2119 topology_thread_cpumask(cpu),
2120 nvmeq, cpus_per_queue);
2121 if (cpus_weight(mask) < cpus_per_queue)
2122 nvme_add_cpus(&mask, unassigned_cpus,
2123 topology_core_cpumask(cpu),
2124 nvmeq, cpus_per_queue);
2125 if (cpus_weight(mask) < cpus_per_queue)
2126 nvme_add_cpus(&mask, unassigned_cpus,
2127 cpumask_of_node(cpu_to_node(cpu)),
2128 nvmeq, cpus_per_queue);
2129 if (cpus_weight(mask) < cpus_per_queue)
2130 nvme_add_cpus(&mask, unassigned_cpus,
2131 cpumask_of_node(
2132 nvme_find_closest_node(
2133 cpu_to_node(cpu))),
2134 nvmeq, cpus_per_queue);
2135 if (cpus_weight(mask) < cpus_per_queue)
2136 nvme_add_cpus(&mask, unassigned_cpus,
2137 unassigned_cpus,
2138 nvmeq, cpus_per_queue);
2139
2140 WARN(cpumask_weight(nvmeq->cpu_mask) != cpus_per_queue,
2141 "nvme%d qid:%d mis-matched queue-to-cpu assignment\n",
2142 dev->instance, i);
2143
2144 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2145 nvmeq->cpu_mask);
2146 cpumask_andnot(unassigned_cpus, unassigned_cpus,
2147 nvmeq->cpu_mask);
2148 cpu = cpumask_next(cpu, unassigned_cpus);
2149 if (remainder && !--remainder)
2150 cpus_per_queue++;
2151 unlock_nvmeq(nvmeq);
2152 }
2153 WARN(cpumask_weight(unassigned_cpus), "nvme%d unassigned online cpus\n",
2154 dev->instance);
2155 i = 0;
2156 cpumask_andnot(unassigned_cpus, cpu_possible_mask, cpu_online_mask);
2157 for_each_cpu(cpu, unassigned_cpus)
2158 *per_cpu_ptr(dev->io_queue, cpu) = (i++ % queues) + 1;
2159 free_cpumask_var(unassigned_cpus);
2160}
2161
b3b06812 2162static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW
2163{
2164 int status;
2165 u32 result;
b3b06812 2166 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2167
df348139 2168 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2169 &result);
27e8166c
MW
2170 if (status < 0)
2171 return status;
2172 if (status > 0) {
2173 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2174 status);
badc34d4 2175 return 0;
27e8166c 2176 }
b60503ba
MW
2177 return min(result & 0xffff, result >> 16) + 1;
2178}
2179
9d713c2b
KB
2180static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2181{
b80d5ccc 2182 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB
2183}
2184
f3db22fe
KB
2185static void nvme_cpu_workfn(struct work_struct *work)
2186{
2187 struct nvme_dev *dev = container_of(work, struct nvme_dev, cpu_work);
2188 if (dev->initialized)
2189 nvme_assign_io_queues(dev);
2190}
2191
33b1e95c
KB
2192static int nvme_cpu_notify(struct notifier_block *self,
2193 unsigned long action, void *hcpu)
2194{
f3db22fe
KB
2195 struct nvme_dev *dev;
2196
33b1e95c
KB
2197 switch (action) {
2198 case CPU_ONLINE:
2199 case CPU_DEAD:
f3db22fe
KB
2200 spin_lock(&dev_list_lock);
2201 list_for_each_entry(dev, &dev_list, node)
2202 schedule_work(&dev->cpu_work);
2203 spin_unlock(&dev_list_lock);
33b1e95c
KB
2204 break;
2205 }
2206 return NOTIFY_OK;
2207}
2208
8d85fce7 2209static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2210{
5a92e700 2211 struct nvme_queue *adminq = raw_nvmeq(dev, 0);
fa08a396 2212 struct pci_dev *pdev = dev->pci_dev;
42f61420 2213 int result, i, vecs, nr_io_queues, size;
b60503ba 2214
42f61420 2215 nr_io_queues = num_possible_cpus();
b348b7d5 2216 result = set_queue_count(dev, nr_io_queues);
badc34d4 2217 if (result <= 0)
1b23484b 2218 return result;
b348b7d5
MW
2219 if (result < nr_io_queues)
2220 nr_io_queues = result;
b60503ba 2221
9d713c2b
KB
2222 size = db_bar_size(dev, nr_io_queues);
2223 if (size > 8192) {
f1938f6e 2224 iounmap(dev->bar);
9d713c2b
KB
2225 do {
2226 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2227 if (dev->bar)
2228 break;
2229 if (!--nr_io_queues)
2230 return -ENOMEM;
2231 size = db_bar_size(dev, nr_io_queues);
2232 } while (1);
f1938f6e 2233 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2234 adminq->q_db = dev->dbs;
f1938f6e
MW
2235 }
2236
9d713c2b 2237 /* Deregister the admin queue's interrupt */
3193f07b 2238 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2239
be577fab 2240 for (i = 0; i < nr_io_queues; i++)
1b23484b 2241 dev->entry[i].entry = i;
be577fab
AG
2242 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2243 if (vecs < 0) {
2244 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2245 if (vecs < 0) {
2246 vecs = 1;
2247 } else {
2248 for (i = 0; i < vecs; i++)
2249 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG
2250 }
2251 }
2252
063a8096
MW
2253 /*
2254 * Should investigate if there's a performance win from allocating
2255 * more queues than interrupt vectors; it might allow the submission
2256 * path to scale better, even if the receive path is limited by the
2257 * number of interrupts.
2258 */
2259 nr_io_queues = vecs;
42f61420 2260 dev->max_qid = nr_io_queues;
063a8096 2261
3193f07b 2262 result = queue_request_irq(dev, adminq, adminq->irqname);
9d713c2b 2263 if (result) {
3193f07b 2264 adminq->q_suspended = 1;
22404274 2265 goto free_queues;
9d713c2b 2266 }
1b23484b 2267
cd638946 2268 /* Free previously allocated queues that are no longer usable */
42f61420
KB
2269 nvme_free_queues(dev, nr_io_queues + 1);
2270 nvme_assign_io_queues(dev);
9ecdc946 2271
22404274 2272 return 0;
b60503ba 2273
22404274 2274 free_queues:
a1a5ef99 2275 nvme_free_queues(dev, 1);
22404274 2276 return result;
b60503ba
MW
2277}
2278
422ef0c7
MW
2279/*
2280 * Return: error value if an error occurred setting up the queues or calling
2281 * Identify Device. 0 if these succeeded, even if adding some of the
2282 * namespaces failed. At the moment, these failures are silent. TBD which
2283 * failures should be reported.
2284 */
8d85fce7 2285static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2286{
68608c26 2287 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW
2288 int res;
2289 unsigned nn, i;
cbb6218f 2290 struct nvme_ns *ns;
51814232 2291 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW
2292 struct nvme_id_ns *id_ns;
2293 void *mem;
b60503ba 2294 dma_addr_t dma_addr;
159b67d7 2295 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2296
68608c26 2297 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB
2298 if (!mem)
2299 return -ENOMEM;
b60503ba 2300
bc5fc7e4 2301 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2302 if (res) {
27e8166c 2303 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
b60503ba 2304 res = -EIO;
cbb6218f 2305 goto out;
b60503ba
MW
2306 }
2307
bc5fc7e4 2308 ctrl = mem;
51814232 2309 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2310 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2311 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2312 dev->vwc = ctrl->vwc;
6fccf938 2313 dev->event_limit = min(ctrl->aerl + 1, 8);
51814232
MW
2314 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2315 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2316 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2317 if (ctrl->mdts)
8fc23e03 2318 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26
MW
2319 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2320 (pdev->device == 0x0953) && ctrl->vs[3])
159b67d7 2321 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
b60503ba 2322
bc5fc7e4 2323 id_ns = mem;
2b2c1896 2324 for (i = 1; i <= nn; i++) {
bc5fc7e4 2325 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW
2326 if (res)
2327 continue;
2328
bc5fc7e4 2329 if (id_ns->ncap == 0)
b60503ba
MW
2330 continue;
2331
bc5fc7e4 2332 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2333 dma_addr + 4096, NULL);
b60503ba 2334 if (res)
12209036 2335 memset(mem + 4096, 0, 4096);
b60503ba 2336
bc5fc7e4 2337 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW
2338 if (ns)
2339 list_add_tail(&ns->list, &dev->namespaces);
2340 }
2341 list_for_each_entry(ns, &dev->namespaces, list)
2342 add_disk(ns->disk);
422ef0c7 2343 res = 0;
b60503ba 2344
bc5fc7e4 2345 out:
684f5c20 2346 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW
2347 return res;
2348}
2349
0877cb0d
KB
2350static int nvme_dev_map(struct nvme_dev *dev)
2351{
42f61420 2352 u64 cap;
0877cb0d
KB
2353 int bars, result = -ENOMEM;
2354 struct pci_dev *pdev = dev->pci_dev;
2355
2356 if (pci_enable_device_mem(pdev))
2357 return result;
2358
2359 dev->entry[0].vector = pdev->irq;
2360 pci_set_master(pdev);
2361 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2362 if (pci_request_selected_regions(pdev, bars, "nvme"))
2363 goto disable_pci;
2364
052d0efa
RK
2365 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2366 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2367 goto disable;
0877cb0d 2368
0877cb0d
KB
2369 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2370 if (!dev->bar)
2371 goto disable;
0e53d180
KB
2372 if (readl(&dev->bar->csts) == -1) {
2373 result = -ENODEV;
2374 goto unmap;
2375 }
42f61420
KB
2376 cap = readq(&dev->bar->cap);
2377 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2378 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB
2379 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2380
2381 return 0;
2382
0e53d180
KB
2383 unmap:
2384 iounmap(dev->bar);
2385 dev->bar = NULL;
0877cb0d
KB
2386 disable:
2387 pci_release_regions(pdev);
2388 disable_pci:
2389 pci_disable_device(pdev);
2390 return result;
2391}
2392
2393static void nvme_dev_unmap(struct nvme_dev *dev)
2394{
2395 if (dev->pci_dev->msi_enabled)
2396 pci_disable_msi(dev->pci_dev);
2397 else if (dev->pci_dev->msix_enabled)
2398 pci_disable_msix(dev->pci_dev);
2399
2400 if (dev->bar) {
2401 iounmap(dev->bar);
2402 dev->bar = NULL;
9a6b9458 2403 pci_release_regions(dev->pci_dev);
0877cb0d
KB
2404 }
2405
0877cb0d
KB
2406 if (pci_is_enabled(dev->pci_dev))
2407 pci_disable_device(dev->pci_dev);
2408}
2409
4d115420
KB
2410struct nvme_delq_ctx {
2411 struct task_struct *waiter;
2412 struct kthread_worker *worker;
2413 atomic_t refcount;
2414};
2415
2416static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2417{
2418 dq->waiter = current;
2419 mb();
2420
2421 for (;;) {
2422 set_current_state(TASK_KILLABLE);
2423 if (!atomic_read(&dq->refcount))
2424 break;
2425 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2426 fatal_signal_pending(current)) {
2427 set_current_state(TASK_RUNNING);
2428
2429 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2430 nvme_disable_queue(dev, 0);
2431
2432 send_sig(SIGKILL, dq->worker->task, 1);
2433 flush_kthread_worker(dq->worker);
2434 return;
2435 }
2436 }
2437 set_current_state(TASK_RUNNING);
2438}
2439
2440static void nvme_put_dq(struct nvme_delq_ctx *dq)
2441{
2442 atomic_dec(&dq->refcount);
2443 if (dq->waiter)
2444 wake_up_process(dq->waiter);
2445}
2446
2447static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2448{
2449 atomic_inc(&dq->refcount);
2450 return dq;
2451}
2452
2453static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2454{
2455 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2456
2457 nvme_clear_queue(nvmeq);
2458 nvme_put_dq(dq);
2459}
2460
2461static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2462 kthread_work_func_t fn)
2463{
2464 struct nvme_command c;
2465
2466 memset(&c, 0, sizeof(c));
2467 c.delete_queue.opcode = opcode;
2468 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2469
2470 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2471 return nvme_submit_admin_cmd_async(nvmeq->dev, &c, &nvmeq->cmdinfo);
2472}
2473
2474static void nvme_del_cq_work_handler(struct kthread_work *work)
2475{
2476 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2477 cmdinfo.work);
2478 nvme_del_queue_end(nvmeq);
2479}
2480
2481static int nvme_delete_cq(struct nvme_queue *nvmeq)
2482{
2483 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2484 nvme_del_cq_work_handler);
2485}
2486
2487static void nvme_del_sq_work_handler(struct kthread_work *work)
2488{
2489 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2490 cmdinfo.work);
2491 int status = nvmeq->cmdinfo.status;
2492
2493 if (!status)
2494 status = nvme_delete_cq(nvmeq);
2495 if (status)
2496 nvme_del_queue_end(nvmeq);
2497}
2498
2499static int nvme_delete_sq(struct nvme_queue *nvmeq)
2500{
2501 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2502 nvme_del_sq_work_handler);
2503}
2504
2505static void nvme_del_queue_start(struct kthread_work *work)
2506{
2507 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2508 cmdinfo.work);
2509 allow_signal(SIGKILL);
2510 if (nvme_delete_sq(nvmeq))
2511 nvme_del_queue_end(nvmeq);
2512}
2513
2514static void nvme_disable_io_queues(struct nvme_dev *dev)
2515{
2516 int i;
2517 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2518 struct nvme_delq_ctx dq;
2519 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2520 &worker, "nvme%d", dev->instance);
2521
2522 if (IS_ERR(kworker_task)) {
2523 dev_err(&dev->pci_dev->dev,
2524 "Failed to create queue del task\n");
2525 for (i = dev->queue_count - 1; i > 0; i--)
2526 nvme_disable_queue(dev, i);
2527 return;
2528 }
2529
2530 dq.waiter = NULL;
2531 atomic_set(&dq.refcount, 0);
2532 dq.worker = &worker;
2533 for (i = dev->queue_count - 1; i > 0; i--) {
5a92e700 2534 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB
2535
2536 if (nvme_suspend_queue(nvmeq))
2537 continue;
2538 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2539 nvmeq->cmdinfo.worker = dq.worker;
2540 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2541 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2542 }
2543 nvme_wait_dq(&dq, dev);
2544 kthread_stop(kworker_task);
2545}
2546
b9afca3e
DM
2547/*
2548* Remove the node from the device list and check
2549* for whether or not we need to stop the nvme_thread.
2550*/
2551static void nvme_dev_list_remove(struct nvme_dev *dev)
2552{
2553 struct task_struct *tmp = NULL;
2554
2555 spin_lock(&dev_list_lock);
2556 list_del_init(&dev->node);
2557 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2558 tmp = nvme_thread;
2559 nvme_thread = NULL;
2560 }
2561 spin_unlock(&dev_list_lock);
2562
2563 if (tmp)
2564 kthread_stop(tmp);
2565}
2566
f0b50732 2567static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2568{
22404274 2569 int i;
7c1b2450 2570 u32 csts = -1;
22404274 2571
d4b4ff8e 2572 dev->initialized = 0;
b9afca3e 2573 nvme_dev_list_remove(dev);
1fa6aead 2574
7c1b2450
KB
2575 if (dev->bar)
2576 csts = readl(&dev->bar->csts);
2577 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2578 for (i = dev->queue_count - 1; i >= 0; i--) {
5a92e700 2579 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB
2580 nvme_suspend_queue(nvmeq);
2581 nvme_clear_queue(nvmeq);
2582 }
2583 } else {
2584 nvme_disable_io_queues(dev);
1894d8f1 2585 nvme_shutdown_ctrl(dev);
4d115420
KB
2586 nvme_disable_queue(dev, 0);
2587 }
f0b50732
KB
2588 nvme_dev_unmap(dev);
2589}
2590
2591static void nvme_dev_remove(struct nvme_dev *dev)
2592{
9ac27090 2593 struct nvme_ns *ns;
f0b50732 2594
9ac27090
KB
2595 list_for_each_entry(ns, &dev->namespaces, list) {
2596 if (ns->disk->flags & GENHD_FL_UP)
2597 del_gendisk(ns->disk);
2598 if (!blk_queue_dying(ns->queue))
2599 blk_cleanup_queue(ns->queue);
b60503ba 2600 }
b60503ba
MW
2601}
2602
091b6092
MW
2603static int nvme_setup_prp_pools(struct nvme_dev *dev)
2604{
2605 struct device *dmadev = &dev->pci_dev->dev;
2606 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2607 PAGE_SIZE, PAGE_SIZE, 0);
2608 if (!dev->prp_page_pool)
2609 return -ENOMEM;
2610
99802a7a
MW
2611 /* Optimisation for I/Os between 4k and 128k */
2612 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2613 256, 256, 0);
2614 if (!dev->prp_small_pool) {
2615 dma_pool_destroy(dev->prp_page_pool);
2616 return -ENOMEM;
2617 }
091b6092
MW
2618 return 0;
2619}
2620
2621static void nvme_release_prp_pools(struct nvme_dev *dev)
2622{
2623 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2624 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW
2625}
2626
cd58ad7d
QSA
2627static DEFINE_IDA(nvme_instance_ida);
2628
2629static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2630{
cd58ad7d
QSA
2631 int instance, error;
2632
2633 do {
2634 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2635 return -ENODEV;
2636
2637 spin_lock(&dev_list_lock);
2638 error = ida_get_new(&nvme_instance_ida, &instance);
2639 spin_unlock(&dev_list_lock);
2640 } while (error == -EAGAIN);
2641
2642 if (error)
2643 return -ENODEV;
2644
2645 dev->instance = instance;
2646 return 0;
b60503ba
MW
2647}
2648
2649static void nvme_release_instance(struct nvme_dev *dev)
2650{
cd58ad7d
QSA
2651 spin_lock(&dev_list_lock);
2652 ida_remove(&nvme_instance_ida, dev->instance);
2653 spin_unlock(&dev_list_lock);
b60503ba
MW
2654}
2655
9ac27090
KB
2656static void nvme_free_namespaces(struct nvme_dev *dev)
2657{
2658 struct nvme_ns *ns, *next;
2659
2660 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2661 list_del(&ns->list);
2662 put_disk(ns->disk);
2663 kfree(ns);
2664 }
2665}
2666
5e82e952
KB
2667static void nvme_free_dev(struct kref *kref)
2668{
2669 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090
KB
2670
2671 nvme_free_namespaces(dev);
42f61420 2672 free_percpu(dev->io_queue);
5e82e952
KB
2673 kfree(dev->queues);
2674 kfree(dev->entry);
2675 kfree(dev);
2676}
2677
2678static int nvme_dev_open(struct inode *inode, struct file *f)
2679{
2680 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2681 miscdev);
2682 kref_get(&dev->kref);
2683 f->private_data = dev;
2684 return 0;
2685}
2686
2687static int nvme_dev_release(struct inode *inode, struct file *f)
2688{
2689 struct nvme_dev *dev = f->private_data;
2690 kref_put(&dev->kref, nvme_free_dev);
2691 return 0;
2692}
2693
2694static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2695{
2696 struct nvme_dev *dev = f->private_data;
2697 switch (cmd) {
2698 case NVME_IOCTL_ADMIN_CMD:
2699 return nvme_user_admin_cmd(dev, (void __user *)arg);
2700 default:
2701 return -ENOTTY;
2702 }
2703}
2704
2705static const struct file_operations nvme_dev_fops = {
2706 .owner = THIS_MODULE,
2707 .open = nvme_dev_open,
2708 .release = nvme_dev_release,
2709 .unlocked_ioctl = nvme_dev_ioctl,
2710 .compat_ioctl = nvme_dev_ioctl,
2711};
2712
f0b50732
KB
2713static int nvme_dev_start(struct nvme_dev *dev)
2714{
2715 int result;
b9afca3e 2716 bool start_thread = false;
f0b50732
KB
2717
2718 result = nvme_dev_map(dev);
2719 if (result)
2720 return result;
2721
2722 result = nvme_configure_admin_queue(dev);
2723 if (result)
2724 goto unmap;
2725
2726 spin_lock(&dev_list_lock);
b9afca3e
DM
2727 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2728 start_thread = true;
2729 nvme_thread = NULL;
2730 }
f0b50732
KB
2731 list_add(&dev->node, &dev_list);
2732 spin_unlock(&dev_list_lock);
2733
b9afca3e
DM
2734 if (start_thread) {
2735 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2736 wake_up(&nvme_kthread_wait);
2737 } else
2738 wait_event_killable(nvme_kthread_wait, nvme_thread);
2739
2740 if (IS_ERR_OR_NULL(nvme_thread)) {
2741 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2742 goto disable;
2743 }
2744
f0b50732 2745 result = nvme_setup_io_queues(dev);
badc34d4 2746 if (result)
f0b50732
KB
2747 goto disable;
2748
d82e8bfd 2749 return result;
f0b50732
KB
2750
2751 disable:
a1a5ef99 2752 nvme_disable_queue(dev, 0);
b9afca3e 2753 nvme_dev_list_remove(dev);
f0b50732
KB
2754 unmap:
2755 nvme_dev_unmap(dev);
2756 return result;
2757}
2758
9a6b9458
KB
2759static int nvme_remove_dead_ctrl(void *arg)
2760{
2761 struct nvme_dev *dev = (struct nvme_dev *)arg;
2762 struct pci_dev *pdev = dev->pci_dev;
2763
2764 if (pci_get_drvdata(pdev))
c81f4975 2765 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB
2766 kref_put(&dev->kref, nvme_free_dev);
2767 return 0;
2768}
2769
2770static void nvme_remove_disks(struct work_struct *ws)
2771{
9a6b9458
KB
2772 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2773
2774 nvme_dev_remove(dev);
5a92e700 2775 nvme_free_queues(dev, 1);
9a6b9458
KB
2776}
2777
2778static int nvme_dev_resume(struct nvme_dev *dev)
2779{
2780 int ret;
2781
2782 ret = nvme_dev_start(dev);
badc34d4 2783 if (ret)
9a6b9458 2784 return ret;
badc34d4 2785 if (dev->online_queues < 2) {
9a6b9458 2786 spin_lock(&dev_list_lock);
9ca97374 2787 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB
2788 queue_work(nvme_workq, &dev->reset_work);
2789 spin_unlock(&dev_list_lock);
2790 }
d4b4ff8e 2791 dev->initialized = 1;
9a6b9458
KB
2792 return 0;
2793}
2794
2795static void nvme_dev_reset(struct nvme_dev *dev)
2796{
2797 nvme_dev_shutdown(dev);
2798 if (nvme_dev_resume(dev)) {
2799 dev_err(&dev->pci_dev->dev, "Device failed to resume\n");
2800 kref_get(&dev->kref);
2801 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2802 dev->instance))) {
2803 dev_err(&dev->pci_dev->dev,
2804 "Failed to start controller remove task\n");
2805 kref_put(&dev->kref, nvme_free_dev);
2806 }
2807 }
2808}
2809
2810static void nvme_reset_failed_dev(struct work_struct *ws)
2811{
2812 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2813 nvme_dev_reset(dev);
2814}
2815
9ca97374
TH
2816static void nvme_reset_workfn(struct work_struct *work)
2817{
2818 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2819 dev->reset_workfn(work);
2820}
2821
8d85fce7 2822static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2823{
0877cb0d 2824 int result = -ENOMEM;
b60503ba
MW
2825 struct nvme_dev *dev;
2826
2827 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2828 if (!dev)
2829 return -ENOMEM;
2830 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2831 GFP_KERNEL);
2832 if (!dev->entry)
2833 goto free;
1b23484b
MW
2834 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2835 GFP_KERNEL);
b60503ba
MW
2836 if (!dev->queues)
2837 goto free;
42f61420
KB
2838 dev->io_queue = alloc_percpu(unsigned short);
2839 if (!dev->io_queue)
2840 goto free;
b60503ba
MW
2841
2842 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH
2843 dev->reset_workfn = nvme_reset_failed_dev;
2844 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
f3db22fe 2845 INIT_WORK(&dev->cpu_work, nvme_cpu_workfn);
b60503ba 2846 dev->pci_dev = pdev;
9a6b9458 2847 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA
2848 result = nvme_set_instance(dev);
2849 if (result)
0877cb0d 2850 goto free;
b60503ba 2851
091b6092
MW
2852 result = nvme_setup_prp_pools(dev);
2853 if (result)
0877cb0d 2854 goto release;
091b6092 2855
fb35e914 2856 kref_init(&dev->kref);
f0b50732 2857 result = nvme_dev_start(dev);
badc34d4 2858 if (result)
0877cb0d 2859 goto release_pools;
b60503ba 2860
badc34d4
KB
2861 if (dev->online_queues > 1)
2862 result = nvme_dev_add(dev);
d82e8bfd 2863 if (result)
f0b50732 2864 goto shutdown;
740216fc 2865
5e82e952
KB
2866 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2867 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2868 dev->miscdev.parent = &pdev->dev;
2869 dev->miscdev.name = dev->name;
2870 dev->miscdev.fops = &nvme_dev_fops;
2871 result = misc_register(&dev->miscdev);
2872 if (result)
2873 goto remove;
2874
d4b4ff8e 2875 dev->initialized = 1;
b60503ba
MW
2876 return 0;
2877
5e82e952
KB
2878 remove:
2879 nvme_dev_remove(dev);
9ac27090 2880 nvme_free_namespaces(dev);
f0b50732
KB
2881 shutdown:
2882 nvme_dev_shutdown(dev);
0877cb0d 2883 release_pools:
a1a5ef99 2884 nvme_free_queues(dev, 0);
091b6092 2885 nvme_release_prp_pools(dev);
0877cb0d
KB
2886 release:
2887 nvme_release_instance(dev);
b60503ba 2888 free:
42f61420 2889 free_percpu(dev->io_queue);
b60503ba
MW
2890 kfree(dev->queues);
2891 kfree(dev->entry);
2892 kfree(dev);
2893 return result;
2894}
2895
f0d54a54
KB
2896static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2897{
a6739479 2898 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 2899
a6739479
KB
2900 if (prepare)
2901 nvme_dev_shutdown(dev);
2902 else
2903 nvme_dev_resume(dev);
f0d54a54
KB
2904}
2905
09ece142
KB
2906static void nvme_shutdown(struct pci_dev *pdev)
2907{
2908 struct nvme_dev *dev = pci_get_drvdata(pdev);
2909 nvme_dev_shutdown(dev);
2910}
2911
8d85fce7 2912static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW
2913{
2914 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB
2915
2916 spin_lock(&dev_list_lock);
2917 list_del_init(&dev->node);
2918 spin_unlock(&dev_list_lock);
2919
2920 pci_set_drvdata(pdev, NULL);
2921 flush_work(&dev->reset_work);
f3db22fe 2922 flush_work(&dev->cpu_work);
5e82e952 2923 misc_deregister(&dev->miscdev);
9a6b9458
KB
2924 nvme_dev_remove(dev);
2925 nvme_dev_shutdown(dev);
a1a5ef99 2926 nvme_free_queues(dev, 0);
5a92e700 2927 rcu_barrier();
9a6b9458
KB
2928 nvme_release_instance(dev);
2929 nvme_release_prp_pools(dev);
5e82e952 2930 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW
2931}
2932
2933/* These functions are yet to be implemented */
2934#define nvme_error_detected NULL
2935#define nvme_dump_registers NULL
2936#define nvme_link_reset NULL
2937#define nvme_slot_reset NULL
2938#define nvme_error_resume NULL
cd638946 2939
671a6018 2940#ifdef CONFIG_PM_SLEEP
cd638946
KB
2941static int nvme_suspend(struct device *dev)
2942{
2943 struct pci_dev *pdev = to_pci_dev(dev);
2944 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2945
2946 nvme_dev_shutdown(ndev);
2947 return 0;
2948}
2949
2950static int nvme_resume(struct device *dev)
2951{
2952 struct pci_dev *pdev = to_pci_dev(dev);
2953 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2954
9a6b9458 2955 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2956 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB
2957 queue_work(nvme_workq, &ndev->reset_work);
2958 }
2959 return 0;
cd638946 2960}
671a6018 2961#endif
cd638946
KB
2962
2963static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2964
1d352035 2965static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW
2966 .error_detected = nvme_error_detected,
2967 .mmio_enabled = nvme_dump_registers,
2968 .link_reset = nvme_link_reset,
2969 .slot_reset = nvme_slot_reset,
2970 .resume = nvme_error_resume,
f0d54a54 2971 .reset_notify = nvme_reset_notify,
b60503ba
MW
2972};
2973
2974/* Move to pci_ids.h later */
2975#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2976
6eb0d698 2977static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW
2978 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2979 { 0, }
2980};
2981MODULE_DEVICE_TABLE(pci, nvme_id_table);
2982
2983static struct pci_driver nvme_driver = {
2984 .name = "nvme",
2985 .id_table = nvme_id_table,
2986 .probe = nvme_probe,
8d85fce7 2987 .remove = nvme_remove,
09ece142 2988 .shutdown = nvme_shutdown,
cd638946
KB
2989 .driver = {
2990 .pm = &nvme_dev_pm_ops,
2991 },
b60503ba
MW
2992 .err_handler = &nvme_err_handler,
2993};
2994
2995static int __init nvme_init(void)
2996{
0ac13140 2997 int result;
1fa6aead 2998
b9afca3e 2999 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3000
9a6b9458
KB
3001 nvme_workq = create_singlethread_workqueue("nvme");
3002 if (!nvme_workq)
b9afca3e 3003 return -ENOMEM;
9a6b9458 3004
5c42ea16
KB
3005 result = register_blkdev(nvme_major, "nvme");
3006 if (result < 0)
9a6b9458 3007 goto kill_workq;
5c42ea16 3008 else if (result > 0)
0ac13140 3009 nvme_major = result;
b60503ba 3010
f3db22fe
KB
3011 nvme_nb.notifier_call = &nvme_cpu_notify;
3012 result = register_hotcpu_notifier(&nvme_nb);
1fa6aead
MW
3013 if (result)
3014 goto unregister_blkdev;
f3db22fe
KB
3015
3016 result = pci_register_driver(&nvme_driver);
3017 if (result)
3018 goto unregister_hotcpu;
1fa6aead 3019 return 0;
b60503ba 3020
f3db22fe
KB
3021 unregister_hotcpu:
3022 unregister_hotcpu_notifier(&nvme_nb);
1fa6aead 3023 unregister_blkdev:
b60503ba 3024 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB
3025 kill_workq:
3026 destroy_workqueue(nvme_workq);
b60503ba
MW
3027 return result;
3028}
3029
3030static void __exit nvme_exit(void)
3031{
3032 pci_unregister_driver(&nvme_driver);
f3db22fe 3033 unregister_hotcpu_notifier(&nvme_nb);
b60503ba 3034 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3035 destroy_workqueue(nvme_workq);
b9afca3e 3036 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3037 _nvme_check_size();
b60503ba
MW
3038}
3039
3040MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3041MODULE_LICENSE("GPL");
6eb0d698 3042MODULE_VERSION("0.9");
b60503ba
MW
3043module_init(nvme_init);
3044module_exit(nvme_exit);