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NVMe: Make iod bio timeout a parameter
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
16#include <linux/bio.h>
8de05535 17#include <linux/bitops.h>
b60503ba 18#include <linux/blkdev.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
42f61420 36#include <linux/percpu.h>
be7b6275 37#include <linux/poison.h>
c3bfe717 38#include <linux/ptrace.h>
b60503ba
MW		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
5d0f6131 42#include <scsi/sg.h>
797a796a
HM		 43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
3291fa57
KB		 45#include <trace/events/block.h>
46
b60503ba
MW		 47#define NVME_Q_DEPTH 1024
48#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
49#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
e85248e5 50#define ADMIN_TIMEOUT (60 * HZ)
61e4ce08 51#define IOD_TIMEOUT (retry_time * HZ)
b60503ba 52
b355084a
KB		 53unsigned char io_timeout = 30;
54module_param(io_timeout, byte, 0644);
55MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 56
61e4ce08
KB		 57static unsigned char retry_time = 30;
58module_param(retry_time, byte, 0644);
59MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
60
b60503ba
MW		 61static int nvme_major;
62module_param(nvme_major, int, 0);
63
58ffacb5
MW		 64static int use_threaded_interrupts;
65module_param(use_threaded_interrupts, int, 0);
66
1fa6aead
MW		 67static DEFINE_SPINLOCK(dev_list_lock);
68static LIST_HEAD(dev_list);
69static struct task_struct *nvme_thread;
9a6b9458 70static struct workqueue_struct *nvme_workq;
b9afca3e 71static wait_queue_head_t nvme_kthread_wait;
1fa6aead 72
d4b4ff8e
KB		 73static void nvme_reset_failed_dev(struct work_struct *ws);
74
4d115420
KB		 75struct async_cmd_info {
76 struct kthread_work work;
77 struct kthread_worker *worker;
78 u32 result;
79 int status;
80 void *ctx;
81};
1fa6aead 82
b60503ba
MW		 83/*
84 * An NVM Express queue. Each device has at least two (one for admin
85 * commands and one for I/O commands).
86 */
87struct nvme_queue {
5a92e700 88 struct rcu_head r_head;
b60503ba 89 struct device *q_dmadev;
091b6092 90 struct nvme_dev *dev;
3193f07b 91 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 92 spinlock_t q_lock;
93 struct nvme_command *sq_cmds;
94 volatile struct nvme_completion *cqes;
95 dma_addr_t sq_dma_addr;
96 dma_addr_t cq_dma_addr;
97 wait_queue_head_t sq_full;
1fa6aead 98 wait_queue_t sq_cong_wait;
b60503ba 99 struct bio_list sq_cong;
edd10d33 100 struct list_head iod_bio;
b60503ba
MW		 101 u32 __iomem *q_db;
102 u16 q_depth;
103 u16 cq_vector;
104 u16 sq_head;
105 u16 sq_tail;
106 u16 cq_head;
c30341dc 107 u16 qid;
e9539f47
MW		 108 u8 cq_phase;
109 u8 cqe_seen;
22404274 110 u8 q_suspended;
42f61420 111 cpumask_var_t cpu_mask;
4d115420 112 struct async_cmd_info cmdinfo;
b60503ba
MW		 113 unsigned long cmdid_data[];
114};
115
116/*
117 * Check we didin't inadvertently grow the command struct
118 */
119static inline void _nvme_check_size(void)
120{
121 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
122 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
123 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
124 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
125 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 126 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 127 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 128 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
130 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
131 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 132 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 133}
134
edd10d33 135typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 136 struct nvme_completion *);
137
e85248e5 138struct nvme_cmd_info {
c2f5b650
MW		 139 nvme_completion_fn fn;
140 void *ctx;
e85248e5 141 unsigned long timeout;
c30341dc 142 int aborted;
e85248e5
MW		 143};
144
145static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
146{
147 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
148}
149
22404274
KB		 150static unsigned nvme_queue_extra(int depth)
151{
152 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
153}
154
b60503ba 155/**
714a7a22
MW		 156 * alloc_cmdid() - Allocate a Command ID
157 * @nvmeq: The queue that will be used for this command
158 * @ctx: A pointer that will be passed to the handler
c2f5b650 159 * @handler: The function to call on completion
b60503ba
MW		 160 *
161 * Allocate a Command ID for a queue. The data passed in will
162 * be passed to the completion handler. This is implemented by using
163 * the bottom two bits of the ctx pointer to store the handler ID.
164 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
165 * We can change this if it becomes a problem.
184d2944
MW		 166 *
167 * May be called with local interrupts disabled and the q_lock held,
168 * or with interrupts enabled and no locks held.
b60503ba 169 */
c2f5b650
MW		 170static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
171 nvme_completion_fn handler, unsigned timeout)
b60503ba 172{
e6d15f79 173 int depth = nvmeq->q_depth - 1;
e85248e5 174 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba
MW		 175 int cmdid;
176
b60503ba
MW		 177 do {
178 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
179 if (cmdid >= depth)
180 return -EBUSY;
181 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
182
c2f5b650
MW		 183 info[cmdid].fn = handler;
184 info[cmdid].ctx = ctx;
e85248e5 185 info[cmdid].timeout = jiffies + timeout;
c30341dc 186 info[cmdid].aborted = 0;
b60503ba
MW		 187 return cmdid;
188}
189
190static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 191 nvme_completion_fn handler, unsigned timeout)
b60503ba
MW		 192{
193 int cmdid;
194 wait_event_killable(nvmeq->sq_full,
e85248e5 195 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
b60503ba
MW		 196 return (cmdid < 0) ? -EINTR : cmdid;
197}
198
c2f5b650
MW		 199/* Special values must be less than 0x1000 */
200#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 201#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
202#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
203#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
53562be7 204#define CMD_CTX_ABORT (0x318 + CMD_CTX_BASE)
be7b6275 205
edd10d33 206static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 207 struct nvme_completion *cqe)
208{
209 if (ctx == CMD_CTX_CANCELLED)
210 return;
c30341dc 211 if (ctx == CMD_CTX_ABORT) {
edd10d33 212 ++nvmeq->dev->abort_limit;
c30341dc
KB		 213 return;
214 }
c2f5b650 215 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 216 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 217 "completed id %d twice on queue %d\n",
218 cqe->command_id, le16_to_cpup(&cqe->sq_id));
219 return;
220 }
221 if (ctx == CMD_CTX_INVALID) {
edd10d33 222 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 223 "invalid id %d completed on queue %d\n",
224 cqe->command_id, le16_to_cpup(&cqe->sq_id));
225 return;
226 }
227
edd10d33 228 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 229}
230
edd10d33 231static void async_completion(struct nvme_queue *nvmeq, void *ctx,
4d115420
KB		 232 struct nvme_completion *cqe)
233{
234 struct async_cmd_info *cmdinfo = ctx;
235 cmdinfo->result = le32_to_cpup(&cqe->result);
236 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
237 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
238}
239
184d2944
MW		 240/*
241 * Called with local interrupts disabled and the q_lock held. May not sleep.
242 */
c2f5b650
MW		 243static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
244 nvme_completion_fn *fn)
b60503ba 245{
c2f5b650 246 void *ctx;
e85248e5 247 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 248
94bbac40
KB		 249 if (cmdid >= nvmeq->q_depth || !info[cmdid].fn) {
250 if (fn)
251 *fn = special_completion;
48e3d398 252 return CMD_CTX_INVALID;
c2f5b650 253 }
859361a2
KB		 254 if (fn)
255 *fn = info[cmdid].fn;
c2f5b650
MW		 256 ctx = info[cmdid].ctx;
257 info[cmdid].fn = special_completion;
e85248e5 258 info[cmdid].ctx = CMD_CTX_COMPLETED;
b60503ba
MW		 259 clear_bit(cmdid, nvmeq->cmdid_data);
260 wake_up(&nvmeq->sq_full);
c2f5b650 261 return ctx;
b60503ba
MW		 262}
263
c2f5b650
MW		 264static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
265 nvme_completion_fn *fn)
3c0cf138 266{
c2f5b650 267 void *ctx;
e85248e5 268 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
c2f5b650
MW		 269 if (fn)
270 *fn = info[cmdid].fn;
271 ctx = info[cmdid].ctx;
272 info[cmdid].fn = special_completion;
e85248e5 273 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 274 return ctx;
3c0cf138
MW		 275}
276
5a92e700 277static struct nvme_queue *raw_nvmeq(struct nvme_dev *dev, int qid)
b60503ba 278{
5a92e700 279 return rcu_dereference_raw(dev->queues[qid]);
b60503ba
MW		 280}
281
4f5099af 282static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) __acquires(RCU)
5a92e700 283{
42f61420 284 unsigned queue_id = get_cpu_var(*dev->io_queue);
5a92e700 285 rcu_read_lock();
42f61420 286 return rcu_dereference(dev->queues[queue_id]);
5a92e700
KB		 287}
288
4f5099af 289static void put_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
b60503ba 290{
5a92e700 291 rcu_read_unlock();
42f61420 292 put_cpu_var(nvmeq->dev->io_queue);
b60503ba
MW		 293}
294
4f5099af
KB		 295static struct nvme_queue *lock_nvmeq(struct nvme_dev *dev, int q_idx)
296 __acquires(RCU)
b60503ba 297{
4f5099af
KB		 298 rcu_read_lock();
299 return rcu_dereference(dev->queues[q_idx]);
300}
301
302static void unlock_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
303{
304 rcu_read_unlock();
b60503ba
MW		 305}
306
307/**
714a7a22 308 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 309 * @nvmeq: The queue to use
310 * @cmd: The command to send
311 *
312 * Safe to use from interrupt context
313 */
314static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
315{
316 unsigned long flags;
317 u16 tail;
b60503ba 318 spin_lock_irqsave(&nvmeq->q_lock, flags);
4f5099af
KB		 319 if (nvmeq->q_suspended) {
320 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
321 return -EBUSY;
322 }
b60503ba
MW		 323 tail = nvmeq->sq_tail;
324 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 325 if (++tail == nvmeq->q_depth)
326 tail = 0;
7547881d 327 writel(tail, nvmeq->q_db);
b60503ba
MW		 328 nvmeq->sq_tail = tail;
329 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
330
331 return 0;
332}
333
eca18b23 334static __le64 **iod_list(struct nvme_iod *iod)
e025344c 335{
eca18b23 336 return ((void *)iod) + iod->offset;
e025344c
SMM		 337}
338
eca18b23
MW		 339/*
340 * Will slightly overestimate the number of pages needed. This is OK
341 * as it only leads to a small amount of wasted memory for the lifetime of
342 * the I/O.
343 */
344static int nvme_npages(unsigned size)
345{
346 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
347 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
348}
b60503ba 349
eca18b23
MW		 350static struct nvme_iod *
351nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
b60503ba 352{
eca18b23
MW		 353 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
354 sizeof(__le64 *) * nvme_npages(nbytes) +
355 sizeof(struct scatterlist) * nseg, gfp);
356
357 if (iod) {
358 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
359 iod->npages = -1;
360 iod->length = nbytes;
2b196034 361 iod->nents = 0;
edd10d33 362 iod->first_dma = 0ULL;
6198221f 363 iod->start_time = jiffies;
eca18b23
MW		 364 }
365
366 return iod;
b60503ba
MW		 367}
368
5d0f6131 369void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 370{
eca18b23
MW		 371 const int last_prp = PAGE_SIZE / 8 - 1;
372 int i;
373 __le64 **list = iod_list(iod);
374 dma_addr_t prp_dma = iod->first_dma;
375
376 if (iod->npages == 0)
377 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
378 for (i = 0; i < iod->npages; i++) {
379 __le64 *prp_list = list[i];
380 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
381 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
382 prp_dma = next_prp_dma;
383 }
384 kfree(iod);
b60503ba
MW		 385}
386
6198221f
KB		 387static void nvme_start_io_acct(struct bio *bio)
388{
389 struct gendisk *disk = bio->bi_bdev->bd_disk;
390 const int rw = bio_data_dir(bio);
391 int cpu = part_stat_lock();
392 part_round_stats(cpu, &disk->part0);
393 part_stat_inc(cpu, &disk->part0, ios[rw]);
394 part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio));
395 part_inc_in_flight(&disk->part0, rw);
396 part_stat_unlock();
397}
398
399static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
400{
401 struct gendisk *disk = bio->bi_bdev->bd_disk;
402 const int rw = bio_data_dir(bio);
403 unsigned long duration = jiffies - start_time;
404 int cpu = part_stat_lock();
405 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
406 part_round_stats(cpu, &disk->part0);
407 part_dec_in_flight(&disk->part0, rw);
408 part_stat_unlock();
409}
410
edd10d33 411static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 412 struct nvme_completion *cqe)
413{
eca18b23
MW		 414 struct nvme_iod *iod = ctx;
415 struct bio *bio = iod->private;
b60503ba 416 u16 status = le16_to_cpup(&cqe->status) >> 1;
3291fa57 417 int error = 0;
b60503ba 418
edd10d33
KB		 419 if (unlikely(status)) {
420 if (!(status & NVME_SC_DNR ||
421 bio->bi_rw & REQ_FAILFAST_MASK) &&
422 (jiffies - iod->start_time) < IOD_TIMEOUT) {
423 if (!waitqueue_active(&nvmeq->sq_full))
424 add_wait_queue(&nvmeq->sq_full,
425 &nvmeq->sq_cong_wait);
426 list_add_tail(&iod->node, &nvmeq->iod_bio);
427 wake_up(&nvmeq->sq_full);
428 return;
429 }
3291fa57 430 error = -EIO;
edd10d33 431 }
9e59d091 432 if (iod->nents) {
edd10d33 433 dma_unmap_sg(nvmeq->q_dmadev, iod->sg, iod->nents,
b60503ba 434 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9e59d091
KB		 435 nvme_end_io_acct(bio, iod->start_time);
436 }
edd10d33 437 nvme_free_iod(nvmeq->dev, iod);
3291fa57
KB		 438
439 trace_block_bio_complete(bdev_get_queue(bio->bi_bdev), bio, error);
440 bio_endio(bio, error);
b60503ba
MW		 441}
442
184d2944 443/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 444int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
445 gfp_t gfp)
ff22b54f 446{
99802a7a 447 struct dma_pool *pool;
eca18b23
MW		 448 int length = total_len;
449 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 450 int dma_len = sg_dma_len(sg);
451 u64 dma_addr = sg_dma_address(sg);
452 int offset = offset_in_page(dma_addr);
e025344c 453 __le64 *prp_list;
eca18b23 454 __le64 **list = iod_list(iod);
e025344c 455 dma_addr_t prp_dma;
eca18b23 456 int nprps, i;
ff22b54f 457
ff22b54f
MW		 458 length -= (PAGE_SIZE - offset);
459 if (length <= 0)
eca18b23 460 return total_len;
ff22b54f
MW		 461
462 dma_len -= (PAGE_SIZE - offset);
463 if (dma_len) {
464 dma_addr += (PAGE_SIZE - offset);
465 } else {
466 sg = sg_next(sg);
467 dma_addr = sg_dma_address(sg);
468 dma_len = sg_dma_len(sg);
469 }
470
471 if (length <= PAGE_SIZE) {
edd10d33 472 iod->first_dma = dma_addr;
eca18b23 473 return total_len;
e025344c
SMM		 474 }
475
476 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
99802a7a
MW		 477 if (nprps <= (256 / 8)) {
478 pool = dev->prp_small_pool;
eca18b23 479 iod->npages = 0;
99802a7a
MW		 480 } else {
481 pool = dev->prp_page_pool;
eca18b23 482 iod->npages = 1;
99802a7a
MW		 483 }
484
b77954cb
MW		 485 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
486 if (!prp_list) {
edd10d33 487 iod->first_dma = dma_addr;
eca18b23
MW		 488 iod->npages = -1;
489 return (total_len - length) + PAGE_SIZE;
b77954cb 490 }
eca18b23
MW		 491 list[0] = prp_list;
492 iod->first_dma = prp_dma;
e025344c
SMM		 493 i = 0;
494 for (;;) {
7523d834 495 if (i == PAGE_SIZE / 8) {
e025344c 496 __le64 *old_prp_list = prp_list;
b77954cb 497 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 498 if (!prp_list)
499 return total_len - length;
500 list[iod->npages++] = prp_list;
7523d834
MW		 501 prp_list[0] = old_prp_list[i - 1];
502 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
503 i = 1;
e025344c
SMM		 504 }
505 prp_list[i++] = cpu_to_le64(dma_addr);
506 dma_len -= PAGE_SIZE;
507 dma_addr += PAGE_SIZE;
508 length -= PAGE_SIZE;
509 if (length <= 0)
510 break;
511 if (dma_len > 0)
512 continue;
513 BUG_ON(dma_len < 0);
514 sg = sg_next(sg);
515 dma_addr = sg_dma_address(sg);
516 dma_len = sg_dma_len(sg);
ff22b54f
MW		 517 }
518
eca18b23 519 return total_len;
ff22b54f
MW		 520}
521
427e9708 522static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
20d0189b 523 int len)
427e9708 524{
20d0189b
KO		 525 struct bio *split = bio_split(bio, len >> 9, GFP_ATOMIC, NULL);
526 if (!split)
427e9708
KB		 527 return -ENOMEM;
528
3291fa57
KB		 529 trace_block_split(bdev_get_queue(bio->bi_bdev), bio,
530 split->bi_iter.bi_sector);
20d0189b
KO		 531 bio_chain(split, bio);
532
edd10d33 533 if (!waitqueue_active(&nvmeq->sq_full))
427e9708 534 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
20d0189b
KO		 535 bio_list_add(&nvmeq->sq_cong, split);
536 bio_list_add(&nvmeq->sq_cong, bio);
edd10d33 537 wake_up(&nvmeq->sq_full);
427e9708
KB		 538
539 return 0;
540}
541
1ad2f893
MW		 542/* NVMe scatterlists require no holes in the virtual address */
543#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
544 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
545
427e9708 546static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
b60503ba
MW		 547 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
548{
7988613b
KO		 549 struct bio_vec bvec, bvprv;
550 struct bvec_iter iter;
76830840 551 struct scatterlist *sg = NULL;
7988613b
KO		 552 int length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size;
553 int first = 1;
159b67d7
KB		 554
555 if (nvmeq->dev->stripe_size)
556 split_len = nvmeq->dev->stripe_size -
4f024f37
KO		 557 ((bio->bi_iter.bi_sector << 9) &
558 (nvmeq->dev->stripe_size - 1));
b60503ba 559
eca18b23 560 sg_init_table(iod->sg, psegs);
7988613b
KO		 561 bio_for_each_segment(bvec, bio, iter) {
562 if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) {
563 sg->length += bvec.bv_len;
76830840 564 } else {
7988613b
KO		 565 if (!first && BIOVEC_NOT_VIRT_MERGEABLE(&bvprv, &bvec))
566 return nvme_split_and_submit(bio, nvmeq,
20d0189b 567 length);
427e9708 568
eca18b23 569 sg = sg ? sg + 1 : iod->sg;
7988613b
KO		 570 sg_set_page(sg, bvec.bv_page,
571 bvec.bv_len, bvec.bv_offset);
76830840
MW		 572 nsegs++;
573 }
159b67d7 574
7988613b 575 if (split_len - length < bvec.bv_len)
20d0189b 576 return nvme_split_and_submit(bio, nvmeq, split_len);
7988613b 577 length += bvec.bv_len;
76830840 578 bvprv = bvec;
7988613b 579 first = 0;
b60503ba 580 }
eca18b23 581 iod->nents = nsegs;
76830840 582 sg_mark_end(sg);
427e9708 583 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
1ad2f893 584 return -ENOMEM;
427e9708 585
4f024f37 586 BUG_ON(length != bio->bi_iter.bi_size);
1ad2f893 587 return length;
b60503ba
MW		 588}
589
0e5e4f0e
KB		 590static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
591 struct bio *bio, struct nvme_iod *iod, int cmdid)
592{
edd10d33
KB		 593 struct nvme_dsm_range *range =
594 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 595 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
596
0e5e4f0e 597 range->cattr = cpu_to_le32(0);
4f024f37
KO		 598 range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift);
599 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
0e5e4f0e
KB		 600
601 memset(cmnd, 0, sizeof(*cmnd));
602 cmnd->dsm.opcode = nvme_cmd_dsm;
603 cmnd->dsm.command_id = cmdid;
604 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
605 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
606 cmnd->dsm.nr = 0;
607 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
608
609 if (++nvmeq->sq_tail == nvmeq->q_depth)
610 nvmeq->sq_tail = 0;
611 writel(nvmeq->sq_tail, nvmeq->q_db);
612
613 return 0;
614}
615
00df5cb4
MW		 616static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
617 int cmdid)
618{
619 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
620
621 memset(cmnd, 0, sizeof(*cmnd));
622 cmnd->common.opcode = nvme_cmd_flush;
623 cmnd->common.command_id = cmdid;
624 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
625
626 if (++nvmeq->sq_tail == nvmeq->q_depth)
627 nvmeq->sq_tail = 0;
628 writel(nvmeq->sq_tail, nvmeq->q_db);
629
630 return 0;
631}
632
edd10d33 633static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod)
b60503ba 634{
edd10d33
KB		 635 struct bio *bio = iod->private;
636 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
ff22b54f 637 struct nvme_command *cmnd;
edd10d33 638 int cmdid;
b60503ba
MW		 639 u16 control;
640 u32 dsmgmt;
00df5cb4 641
ff976d72 642 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 643 if (unlikely(cmdid < 0))
edd10d33 644 return cmdid;
b60503ba 645
edd10d33
KB		 646 if (bio->bi_rw & REQ_DISCARD)
647 return nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
53562be7 648 if (bio->bi_rw & REQ_FLUSH)
00df5cb4
MW		 649 return nvme_submit_flush(nvmeq, ns, cmdid);
650
b60503ba
MW		 651 control = 0;
652 if (bio->bi_rw & REQ_FUA)
653 control |= NVME_RW_FUA;
654 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
655 control |= NVME_RW_LR;
656
657 dsmgmt = 0;
658 if (bio->bi_rw & REQ_RAHEAD)
659 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
660
ff22b54f 661 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 662 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 663
edd10d33 664 cmnd->rw.opcode = bio_data_dir(bio) ? nvme_cmd_write : nvme_cmd_read;
ff22b54f
MW		 665 cmnd->rw.command_id = cmdid;
666 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 667 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
668 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
4f024f37 669 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
edd10d33
KB		 670 cmnd->rw.length =
671 cpu_to_le16((bio->bi_iter.bi_size >> ns->lba_shift) - 1);
ff22b54f
MW		 672 cmnd->rw.control = cpu_to_le16(control);
673 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 674
b60503ba
MW		 675 if (++nvmeq->sq_tail == nvmeq->q_depth)
676 nvmeq->sq_tail = 0;
7547881d 677 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 678
1974b1ae 679 return 0;
edd10d33
KB		 680}
681
53562be7
KB		 682static int nvme_split_flush_data(struct nvme_queue *nvmeq, struct bio *bio)
683{
684 struct bio *split = bio_clone(bio, GFP_ATOMIC);
685 if (!split)
686 return -ENOMEM;
687
688 split->bi_iter.bi_size = 0;
689 split->bi_phys_segments = 0;
690 bio->bi_rw &= ~REQ_FLUSH;
691 bio_chain(split, bio);
692
693 if (!waitqueue_active(&nvmeq->sq_full))
694 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
695 bio_list_add(&nvmeq->sq_cong, split);
696 bio_list_add(&nvmeq->sq_cong, bio);
697 wake_up_process(nvme_thread);
698
699 return 0;
700}
701
edd10d33
KB		 702/*
703 * Called with local interrupts disabled and the q_lock held. May not sleep.
704 */
705static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
706 struct bio *bio)
707{
708 struct nvme_iod *iod;
709 int psegs = bio_phys_segments(ns->queue, bio);
710 int result;
711
53562be7
KB		 712 if ((bio->bi_rw & REQ_FLUSH) && psegs)
713 return nvme_split_flush_data(nvmeq, bio);
edd10d33
KB		 714
715 iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, GFP_ATOMIC);
716 if (!iod)
717 return -ENOMEM;
718
719 iod->private = bio;
720 if (bio->bi_rw & REQ_DISCARD) {
721 void *range;
722 /*
723 * We reuse the small pool to allocate the 16-byte range here
724 * as it is not worth having a special pool for these or
725 * additional cases to handle freeing the iod.
726 */
727 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
728 GFP_ATOMIC,
729 &iod->first_dma);
730 if (!range) {
731 result = -ENOMEM;
732 goto free_iod;
733 }
734 iod_list(iod)[0] = (__le64 *)range;
735 iod->npages = 0;
736 } else if (psegs) {
737 result = nvme_map_bio(nvmeq, iod, bio,
738 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
739 psegs);
740 if (result <= 0)
741 goto free_iod;
742 if (nvme_setup_prps(nvmeq->dev, iod, result, GFP_ATOMIC) !=
743 result) {
744 result = -ENOMEM;
745 goto free_iod;
746 }
747 nvme_start_io_acct(bio);
748 }
749 if (unlikely(nvme_submit_iod(nvmeq, iod))) {
750 if (!waitqueue_active(&nvmeq->sq_full))
751 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
752 list_add_tail(&iod->node, &nvmeq->iod_bio);
753 }
754 return 0;
1974b1ae 755
eca18b23
MW		 756 free_iod:
757 nvme_free_iod(nvmeq->dev, iod);
eeee3226 758 return result;
b60503ba
MW		 759}
760
e9539f47 761static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 762{
82123460 763 u16 head, phase;
b60503ba 764
b60503ba 765 head = nvmeq->cq_head;
82123460 766 phase = nvmeq->cq_phase;
b60503ba
MW		 767
768 for (;;) {
c2f5b650
MW		 769 void *ctx;
770 nvme_completion_fn fn;
b60503ba 771 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 772 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 773 break;
774 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
775 if (++head == nvmeq->q_depth) {
776 head = 0;
82123460 777 phase = !phase;
b60503ba
MW		 778 }
779
c2f5b650 780 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
edd10d33 781 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 782 }
783
784 /* If the controller ignores the cq head doorbell and continuously
785 * writes to the queue, it is theoretically possible to wrap around
786 * the queue twice and mistakenly return IRQ_NONE. Linux only
787 * requires that 0.1% of your interrupts are handled, so this isn't
788 * a big problem.
789 */
82123460 790 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 791 return 0;
b60503ba 792
b80d5ccc 793 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 794 nvmeq->cq_head = head;
82123460 795 nvmeq->cq_phase = phase;
b60503ba 796
e9539f47
MW		 797 nvmeq->cqe_seen = 1;
798 return 1;
b60503ba
MW		 799}
800
7d822457
MW		 801static void nvme_make_request(struct request_queue *q, struct bio *bio)
802{
803 struct nvme_ns *ns = q->queuedata;
804 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
805 int result = -EBUSY;
806
cd638946
KB		 807 if (!nvmeq) {
808 put_nvmeq(NULL);
809 bio_endio(bio, -EIO);
810 return;
811 }
812
7d822457 813 spin_lock_irq(&nvmeq->q_lock);
22404274 814 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
7d822457
MW		 815 result = nvme_submit_bio_queue(nvmeq, ns, bio);
816 if (unlikely(result)) {
edd10d33 817 if (!waitqueue_active(&nvmeq->sq_full))
7d822457
MW		 818 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
819 bio_list_add(&nvmeq->sq_cong, bio);
820 }
821
822 nvme_process_cq(nvmeq);
823 spin_unlock_irq(&nvmeq->q_lock);
824 put_nvmeq(nvmeq);
825}
826
b60503ba 827static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 828{
829 irqreturn_t result;
830 struct nvme_queue *nvmeq = data;
831 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 832 nvme_process_cq(nvmeq);
833 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
834 nvmeq->cqe_seen = 0;
58ffacb5
MW		 835 spin_unlock(&nvmeq->q_lock);
836 return result;
837}
838
839static irqreturn_t nvme_irq_check(int irq, void *data)
840{
841 struct nvme_queue *nvmeq = data;
842 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
843 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
844 return IRQ_NONE;
845 return IRQ_WAKE_THREAD;
846}
847
3c0cf138
MW		 848static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
849{
850 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 851 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW		 852 spin_unlock_irq(&nvmeq->q_lock);
853}
854
c2f5b650
MW		 855struct sync_cmd_info {
856 struct task_struct *task;
857 u32 result;
858 int status;
859};
860
edd10d33 861static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 862 struct nvme_completion *cqe)
863{
864 struct sync_cmd_info *cmdinfo = ctx;
865 cmdinfo->result = le32_to_cpup(&cqe->result);
866 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
867 wake_up_process(cmdinfo->task);
868}
869
b60503ba
MW		 870/*
871 * Returns 0 on success. If the result is negative, it's a Linux error code;
872 * if the result is positive, it's an NVM Express status code
873 */
4f5099af
KB		 874static int nvme_submit_sync_cmd(struct nvme_dev *dev, int q_idx,
875 struct nvme_command *cmd,
5d0f6131 876 u32 *result, unsigned timeout)
b60503ba 877{
4f5099af 878 int cmdid, ret;
b60503ba 879 struct sync_cmd_info cmdinfo;
4f5099af
KB		 880 struct nvme_queue *nvmeq;
881
882 nvmeq = lock_nvmeq(dev, q_idx);
883 if (!nvmeq) {
884 unlock_nvmeq(nvmeq);
885 return -ENODEV;
886 }
b60503ba
MW		 887
888 cmdinfo.task = current;
889 cmdinfo.status = -EINTR;
890
4f5099af
KB		 891 cmdid = alloc_cmdid(nvmeq, &cmdinfo, sync_completion, timeout);
892 if (cmdid < 0) {
893 unlock_nvmeq(nvmeq);
b60503ba 894 return cmdid;
4f5099af 895 }
b60503ba
MW		 896 cmd->common.command_id = cmdid;
897
3c0cf138 898 set_current_state(TASK_KILLABLE);
4f5099af
KB		 899 ret = nvme_submit_cmd(nvmeq, cmd);
900 if (ret) {
901 free_cmdid(nvmeq, cmdid, NULL);
902 unlock_nvmeq(nvmeq);
903 set_current_state(TASK_RUNNING);
904 return ret;
905 }
906 unlock_nvmeq(nvmeq);
78f8d257 907 schedule_timeout(timeout);
b60503ba 908
3c0cf138 909 if (cmdinfo.status == -EINTR) {
4f5099af
KB		 910 nvmeq = lock_nvmeq(dev, q_idx);
911 if (nvmeq)
912 nvme_abort_command(nvmeq, cmdid);
913 unlock_nvmeq(nvmeq);
3c0cf138
MW		 914 return -EINTR;
915 }
916
b60503ba
MW		 917 if (result)
918 *result = cmdinfo.result;
919
920 return cmdinfo.status;
921}
922
4d115420
KB		 923static int nvme_submit_async_cmd(struct nvme_queue *nvmeq,
924 struct nvme_command *cmd,
925 struct async_cmd_info *cmdinfo, unsigned timeout)
926{
927 int cmdid;
928
929 cmdid = alloc_cmdid_killable(nvmeq, cmdinfo, async_completion, timeout);
930 if (cmdid < 0)
931 return cmdid;
932 cmdinfo->status = -EINTR;
933 cmd->common.command_id = cmdid;
4f5099af 934 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 935}
936
5d0f6131 937int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
b60503ba
MW		 938 u32 *result)
939{
4f5099af
KB		 940 return nvme_submit_sync_cmd(dev, 0, cmd, result, ADMIN_TIMEOUT);
941}
942
943int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
944 u32 *result)
945{
946 return nvme_submit_sync_cmd(dev, smp_processor_id() + 1, cmd, result,
947 NVME_IO_TIMEOUT);
b60503ba
MW		 948}
949
4d115420
KB		 950static int nvme_submit_admin_cmd_async(struct nvme_dev *dev,
951 struct nvme_command *cmd, struct async_cmd_info *cmdinfo)
952{
5a92e700 953 return nvme_submit_async_cmd(raw_nvmeq(dev, 0), cmd, cmdinfo,
4d115420
KB		 954 ADMIN_TIMEOUT);
955}
956
b60503ba
MW		 957static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
958{
959 int status;
960 struct nvme_command c;
961
962 memset(&c, 0, sizeof(c));
963 c.delete_queue.opcode = opcode;
964 c.delete_queue.qid = cpu_to_le16(id);
965
966 status = nvme_submit_admin_cmd(dev, &c, NULL);
967 if (status)
968 return -EIO;
969 return 0;
970}
971
972static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
973 struct nvme_queue *nvmeq)
974{
975 int status;
976 struct nvme_command c;
977 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
978
979 memset(&c, 0, sizeof(c));
980 c.create_cq.opcode = nvme_admin_create_cq;
981 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
982 c.create_cq.cqid = cpu_to_le16(qid);
983 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
984 c.create_cq.cq_flags = cpu_to_le16(flags);
985 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
986
987 status = nvme_submit_admin_cmd(dev, &c, NULL);
988 if (status)
989 return -EIO;
990 return 0;
991}
992
993static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
994 struct nvme_queue *nvmeq)
995{
996 int status;
997 struct nvme_command c;
998 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
999
1000 memset(&c, 0, sizeof(c));
1001 c.create_sq.opcode = nvme_admin_create_sq;
1002 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1003 c.create_sq.sqid = cpu_to_le16(qid);
1004 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1005 c.create_sq.sq_flags = cpu_to_le16(flags);
1006 c.create_sq.cqid = cpu_to_le16(qid);
1007
1008 status = nvme_submit_admin_cmd(dev, &c, NULL);
1009 if (status)
1010 return -EIO;
1011 return 0;
1012}
1013
1014static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1015{
1016 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1017}
1018
1019static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1020{
1021 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1022}
1023
5d0f6131 1024int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 1025 dma_addr_t dma_addr)
1026{
1027 struct nvme_command c;
1028
1029 memset(&c, 0, sizeof(c));
1030 c.identify.opcode = nvme_admin_identify;
1031 c.identify.nsid = cpu_to_le32(nsid);
1032 c.identify.prp1 = cpu_to_le64(dma_addr);
1033 c.identify.cns = cpu_to_le32(cns);
1034
1035 return nvme_submit_admin_cmd(dev, &c, NULL);
1036}
1037
5d0f6131 1038int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1039 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1040{
1041 struct nvme_command c;
1042
1043 memset(&c, 0, sizeof(c));
1044 c.features.opcode = nvme_admin_get_features;
a42cecce 1045 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1046 c.features.prp1 = cpu_to_le64(dma_addr);
1047 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1048
08df1e05 1049 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 1050}
1051
5d0f6131
VV		 1052int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1053 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1054{
1055 struct nvme_command c;
1056
1057 memset(&c, 0, sizeof(c));
1058 c.features.opcode = nvme_admin_set_features;
1059 c.features.prp1 = cpu_to_le64(dma_addr);
1060 c.features.fid = cpu_to_le32(fid);
1061 c.features.dword11 = cpu_to_le32(dword11);
1062
bc5fc7e4
MW		 1063 return nvme_submit_admin_cmd(dev, &c, result);
1064}
1065
c30341dc
KB		 1066/**
1067 * nvme_abort_cmd - Attempt aborting a command
1068 * @cmdid: Command id of a timed out IO
1069 * @queue: The queue with timed out IO
1070 *
1071 * Schedule controller reset if the command was already aborted once before and
1072 * still hasn't been returned to the driver, or if this is the admin queue.
1073 */
1074static void nvme_abort_cmd(int cmdid, struct nvme_queue *nvmeq)
1075{
1076 int a_cmdid;
1077 struct nvme_command cmd;
1078 struct nvme_dev *dev = nvmeq->dev;
1079 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
5a92e700 1080 struct nvme_queue *adminq;
c30341dc
KB		 1081
1082 if (!nvmeq->qid || info[cmdid].aborted) {
1083 if (work_busy(&dev->reset_work))
1084 return;
1085 list_del_init(&dev->node);
1086 dev_warn(&dev->pci_dev->dev,
1087 "I/O %d QID %d timeout, reset controller\n", cmdid,
1088 nvmeq->qid);
9ca97374 1089 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc
KB		 1090 queue_work(nvme_workq, &dev->reset_work);
1091 return;
1092 }
1093
1094 if (!dev->abort_limit)
1095 return;
1096
5a92e700
KB		 1097 adminq = rcu_dereference(dev->queues[0]);
1098 a_cmdid = alloc_cmdid(adminq, CMD_CTX_ABORT, special_completion,
c30341dc
KB		 1099 ADMIN_TIMEOUT);
1100 if (a_cmdid < 0)
1101 return;
1102
1103 memset(&cmd, 0, sizeof(cmd));
1104 cmd.abort.opcode = nvme_admin_abort_cmd;
1105 cmd.abort.cid = cmdid;
1106 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1107 cmd.abort.command_id = a_cmdid;
1108
1109 --dev->abort_limit;
1110 info[cmdid].aborted = 1;
1111 info[cmdid].timeout = jiffies + ADMIN_TIMEOUT;
1112
1113 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", cmdid,
1114 nvmeq->qid);
5a92e700 1115 nvme_submit_cmd(adminq, &cmd);
c30341dc
KB		 1116}
1117
a09115b2
MW		 1118/**
1119 * nvme_cancel_ios - Cancel outstanding I/Os
1120 * @queue: The queue to cancel I/Os on
1121 * @timeout: True to only cancel I/Os which have timed out
1122 */
1123static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1124{
1125 int depth = nvmeq->q_depth - 1;
1126 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1127 unsigned long now = jiffies;
1128 int cmdid;
1129
1130 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1131 void *ctx;
1132 nvme_completion_fn fn;
1133 static struct nvme_completion cqe = {
af2d9ca7 1134 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
a09115b2
MW		 1135 };
1136
1137 if (timeout && !time_after(now, info[cmdid].timeout))
1138 continue;
053ab702
KB		 1139 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1140 continue;
c30341dc
KB		 1141 if (timeout && nvmeq->dev->initialized) {
1142 nvme_abort_cmd(cmdid, nvmeq);
1143 continue;
1144 }
1145 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", cmdid,
1146 nvmeq->qid);
a09115b2 1147 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
edd10d33 1148 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1149 }
1150}
1151
5a92e700 1152static void nvme_free_queue(struct rcu_head *r)
9e866774 1153{
5a92e700
KB		 1154 struct nvme_queue *nvmeq = container_of(r, struct nvme_queue, r_head);
1155
22404274
KB		 1156 spin_lock_irq(&nvmeq->q_lock);
1157 while (bio_list_peek(&nvmeq->sq_cong)) {
1158 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1159 bio_endio(bio, -EIO);
1160 }
edd10d33
KB		 1161 while (!list_empty(&nvmeq->iod_bio)) {
1162 static struct nvme_completion cqe = {
1163 .status = cpu_to_le16(
1164 (NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1),
1165 };
1166 struct nvme_iod *iod = list_first_entry(&nvmeq->iod_bio,
1167 struct nvme_iod,
1168 node);
1169 list_del(&iod->node);
1170 bio_completion(nvmeq, iod, &cqe);
1171 }
22404274
KB		 1172 spin_unlock_irq(&nvmeq->q_lock);
1173
9e866774
MW		 1174 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1175 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1176 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1177 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
42f61420
KB		 1178 if (nvmeq->qid)
1179 free_cpumask_var(nvmeq->cpu_mask);
9e866774
MW		 1180 kfree(nvmeq);
1181}
1182
a1a5ef99 1183static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1184{
1185 int i;
1186
a1a5ef99 1187 for (i = dev->queue_count - 1; i >= lowest; i--) {
5a92e700
KB		 1188 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
1189 rcu_assign_pointer(dev->queues[i], NULL);
1190 call_rcu(&nvmeq->r_head, nvme_free_queue);
22404274 1191 dev->queue_count--;
22404274
KB		 1192 }
1193}
1194
4d115420
KB		 1195/**
1196 * nvme_suspend_queue - put queue into suspended state
1197 * @nvmeq - queue to suspend
1198 *
1199 * Returns 1 if already suspended, 0 otherwise.
1200 */
1201static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1202{
4d115420 1203 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1204
a09115b2 1205 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1206 if (nvmeq->q_suspended) {
1207 spin_unlock_irq(&nvmeq->q_lock);
4d115420 1208 return 1;
3295874b 1209 }
22404274 1210 nvmeq->q_suspended = 1;
42f61420 1211 nvmeq->dev->online_queues--;
a09115b2
MW		 1212 spin_unlock_irq(&nvmeq->q_lock);
1213
aba2080f
MW		 1214 irq_set_affinity_hint(vector, NULL);
1215 free_irq(vector, nvmeq);
b60503ba 1216
4d115420
KB		 1217 return 0;
1218}
b60503ba 1219
4d115420
KB		 1220static void nvme_clear_queue(struct nvme_queue *nvmeq)
1221{
22404274
KB		 1222 spin_lock_irq(&nvmeq->q_lock);
1223 nvme_process_cq(nvmeq);
1224 nvme_cancel_ios(nvmeq, false);
1225 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1226}
1227
4d115420
KB		 1228static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1229{
5a92e700 1230 struct nvme_queue *nvmeq = raw_nvmeq(dev, qid);
4d115420
KB		 1231
1232 if (!nvmeq)
1233 return;
1234 if (nvme_suspend_queue(nvmeq))
1235 return;
1236
0e53d180
KB		 1237 /* Don't tell the adapter to delete the admin queue.
1238 * Don't tell a removed adapter to delete IO queues. */
1239 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1240 adapter_delete_sq(dev, qid);
1241 adapter_delete_cq(dev, qid);
1242 }
4d115420 1243 nvme_clear_queue(nvmeq);
b60503ba
MW		 1244}
1245
1246static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1247 int depth, int vector)
1248{
1249 struct device *dmadev = &dev->pci_dev->dev;
22404274 1250 unsigned extra = nvme_queue_extra(depth);
b60503ba
MW		 1251 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1252 if (!nvmeq)
1253 return NULL;
1254
1255 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1256 &nvmeq->cq_dma_addr, GFP_KERNEL);
1257 if (!nvmeq->cqes)
1258 goto free_nvmeq;
1259 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1260
1261 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1262 &nvmeq->sq_dma_addr, GFP_KERNEL);
1263 if (!nvmeq->sq_cmds)
1264 goto free_cqdma;
1265
42f61420
KB		 1266 if (qid && !zalloc_cpumask_var(&nvmeq->cpu_mask, GFP_KERNEL))
1267 goto free_sqdma;
1268
b60503ba 1269 nvmeq->q_dmadev = dmadev;
091b6092 1270 nvmeq->dev = dev;
3193f07b
MW		 1271 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1272 dev->instance, qid);
b60503ba
MW		 1273 spin_lock_init(&nvmeq->q_lock);
1274 nvmeq->cq_head = 0;
82123460 1275 nvmeq->cq_phase = 1;
b60503ba 1276 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1277 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1278 bio_list_init(&nvmeq->sq_cong);
edd10d33 1279 INIT_LIST_HEAD(&nvmeq->iod_bio);
b80d5ccc 1280 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW		 1281 nvmeq->q_depth = depth;
1282 nvmeq->cq_vector = vector;
c30341dc 1283 nvmeq->qid = qid;
22404274
KB		 1284 nvmeq->q_suspended = 1;
1285 dev->queue_count++;
5a92e700 1286 rcu_assign_pointer(dev->queues[qid], nvmeq);
b60503ba
MW		 1287
1288 return nvmeq;
1289
42f61420
KB		 1290 free_sqdma:
1291 dma_free_coherent(dmadev, SQ_SIZE(depth), (void *)nvmeq->sq_cmds,
1292 nvmeq->sq_dma_addr);
b60503ba 1293 free_cqdma:
68b8eca5 1294 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1295 nvmeq->cq_dma_addr);
1296 free_nvmeq:
1297 kfree(nvmeq);
1298 return NULL;
1299}
1300
3001082c
MW		 1301static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1302 const char *name)
1303{
58ffacb5
MW		 1304 if (use_threaded_interrupts)
1305 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1306 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1307 name, nvmeq);
3001082c 1308 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1309 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1310}
1311
22404274 1312static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1313{
22404274
KB		 1314 struct nvme_dev *dev = nvmeq->dev;
1315 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
b60503ba 1316
22404274
KB		 1317 nvmeq->sq_tail = 0;
1318 nvmeq->cq_head = 0;
1319 nvmeq->cq_phase = 1;
b80d5ccc 1320 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274
KB		 1321 memset(nvmeq->cmdid_data, 0, extra);
1322 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1323 nvme_cancel_ios(nvmeq, false);
1324 nvmeq->q_suspended = 0;
42f61420 1325 dev->online_queues++;
22404274
KB		 1326}
1327
1328static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1329{
1330 struct nvme_dev *dev = nvmeq->dev;
1331 int result;
3f85d50b 1332
b60503ba
MW		 1333 result = adapter_alloc_cq(dev, qid, nvmeq);
1334 if (result < 0)
22404274 1335 return result;
b60503ba
MW		 1336
1337 result = adapter_alloc_sq(dev, qid, nvmeq);
1338 if (result < 0)
1339 goto release_cq;
1340
3193f07b 1341 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1342 if (result < 0)
1343 goto release_sq;
1344
0a8d44cb 1345 spin_lock_irq(&nvmeq->q_lock);
22404274 1346 nvme_init_queue(nvmeq, qid);
0a8d44cb 1347 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1348
1349 return result;
b60503ba
MW		 1350
1351 release_sq:
1352 adapter_delete_sq(dev, qid);
1353 release_cq:
1354 adapter_delete_cq(dev, qid);
22404274 1355 return result;
b60503ba
MW		 1356}
1357
ba47e386
MW		 1358static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1359{
1360 unsigned long timeout;
1361 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1362
1363 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1364
1365 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1366 msleep(100);
1367 if (fatal_signal_pending(current))
1368 return -EINTR;
1369 if (time_after(jiffies, timeout)) {
1370 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1371 "Device not ready; aborting %s\n", enabled ?
1372 "initialisation" : "reset");
ba47e386
MW		 1373 return -ENODEV;
1374 }
1375 }
1376
1377 return 0;
1378}
1379
1380/*
1381 * If the device has been passed off to us in an enabled state, just clear
1382 * the enabled bit. The spec says we should set the 'shutdown notification
1383 * bits', but doing so may cause the device to complete commands to the
1384 * admin queue ... and we don't know what memory that might be pointing at!
1385 */
1386static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1387{
44af146a
MW		 1388 u32 cc = readl(&dev->bar->cc);
1389
1390 if (cc & NVME_CC_ENABLE)
1391 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
ba47e386
MW		 1392 return nvme_wait_ready(dev, cap, false);
1393}
1394
1395static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1396{
1397 return nvme_wait_ready(dev, cap, true);
1398}
1399
1894d8f1
KB		 1400static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1401{
1402 unsigned long timeout;
1403 u32 cc;
1404
1405 cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
1406 writel(cc, &dev->bar->cc);
1407
1408 timeout = 2 * HZ + jiffies;
1409 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1410 NVME_CSTS_SHST_CMPLT) {
1411 msleep(100);
1412 if (fatal_signal_pending(current))
1413 return -EINTR;
1414 if (time_after(jiffies, timeout)) {
1415 dev_err(&dev->pci_dev->dev,
1416 "Device shutdown incomplete; abort shutdown\n");
1417 return -ENODEV;
1418 }
1419 }
1420
1421 return 0;
1422}
1423
8d85fce7 1424static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1425{
ba47e386 1426 int result;
b60503ba 1427 u32 aqa;
ba47e386 1428 u64 cap = readq(&dev->bar->cap);
b60503ba
MW		 1429 struct nvme_queue *nvmeq;
1430
ba47e386
MW		 1431 result = nvme_disable_ctrl(dev, cap);
1432 if (result < 0)
1433 return result;
b60503ba 1434
5a92e700 1435 nvmeq = raw_nvmeq(dev, 0);
cd638946
KB		 1436 if (!nvmeq) {
1437 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1438 if (!nvmeq)
1439 return -ENOMEM;
cd638946 1440 }
b60503ba
MW		 1441
1442 aqa = nvmeq->q_depth - 1;
1443 aqa |= aqa << 16;
1444
1445 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1446 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1447 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1448 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1449
1450 writel(aqa, &dev->bar->aqa);
1451 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1452 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1453 writel(dev->ctrl_config, &dev->bar->cc);
1454
ba47e386 1455 result = nvme_enable_ctrl(dev, cap);
025c557a 1456 if (result)
cd638946 1457 return result;
9e866774 1458
3193f07b 1459 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1460 if (result)
cd638946 1461 return result;
025c557a 1462
0a8d44cb 1463 spin_lock_irq(&nvmeq->q_lock);
22404274 1464 nvme_init_queue(nvmeq, 0);
0a8d44cb 1465 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1466 return result;
1467}
1468
5d0f6131 1469struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1470 unsigned long addr, unsigned length)
b60503ba 1471{
36c14ed9 1472 int i, err, count, nents, offset;
7fc3cdab
MW		 1473 struct scatterlist *sg;
1474 struct page **pages;
eca18b23 1475 struct nvme_iod *iod;
36c14ed9
MW		 1476
1477 if (addr & 3)
eca18b23 1478 return ERR_PTR(-EINVAL);
5460fc03 1479 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1480 return ERR_PTR(-EINVAL);
7fc3cdab 1481
36c14ed9 1482 offset = offset_in_page(addr);
7fc3cdab
MW		 1483 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1484 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1485 if (!pages)
1486 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1487
1488 err = get_user_pages_fast(addr, count, 1, pages);
1489 if (err < count) {
1490 count = err;
1491 err = -EFAULT;
1492 goto put_pages;
1493 }
7fc3cdab 1494
6808c5fb 1495 err = -ENOMEM;
eca18b23 1496 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
6808c5fb
S		 1497 if (!iod)
1498 goto put_pages;
1499
eca18b23 1500 sg = iod->sg;
36c14ed9 1501 sg_init_table(sg, count);
d0ba1e49
MW		 1502 for (i = 0; i < count; i++) {
1503 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1504 min_t(unsigned, length, PAGE_SIZE - offset),
1505 offset);
d0ba1e49
MW		 1506 length -= (PAGE_SIZE - offset);
1507 offset = 0;
7fc3cdab 1508 }
fe304c43 1509 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1510 iod->nents = count;
7fc3cdab 1511
7fc3cdab
MW		 1512 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1513 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1514 if (!nents)
eca18b23 1515 goto free_iod;
b60503ba 1516
7fc3cdab 1517 kfree(pages);
eca18b23 1518 return iod;
b60503ba 1519
eca18b23
MW		 1520 free_iod:
1521 kfree(iod);
7fc3cdab
MW		 1522 put_pages:
1523 for (i = 0; i < count; i++)
1524 put_page(pages[i]);
1525 kfree(pages);
eca18b23 1526 return ERR_PTR(err);
7fc3cdab 1527}
b60503ba 1528
5d0f6131 1529void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1530 struct nvme_iod *iod)
7fc3cdab 1531{
1c2ad9fa 1532 int i;
b60503ba 1533
1c2ad9fa
MW		 1534 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1535 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1536
1c2ad9fa
MW		 1537 for (i = 0; i < iod->nents; i++)
1538 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1539}
b60503ba 1540
a53295b6
MW		 1541static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1542{
1543 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1544 struct nvme_user_io io;
1545 struct nvme_command c;
f410c680
KB		 1546 unsigned length, meta_len;
1547 int status, i;
1548 struct nvme_iod *iod, *meta_iod = NULL;
1549 dma_addr_t meta_dma_addr;
1550 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1551
1552 if (copy_from_user(&io, uio, sizeof(io)))
1553 return -EFAULT;
6c7d4945 1554 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1555 meta_len = (io.nblocks + 1) * ns->ms;
1556
1557 if (meta_len && ((io.metadata & 3) || !io.metadata))
1558 return -EINVAL;
6c7d4945
MW		 1559
1560 switch (io.opcode) {
1561 case nvme_cmd_write:
1562 case nvme_cmd_read:
6bbf1acd 1563 case nvme_cmd_compare:
eca18b23 1564 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1565 break;
6c7d4945 1566 default:
6bbf1acd 1567 return -EINVAL;
6c7d4945
MW		 1568 }
1569
eca18b23
MW		 1570 if (IS_ERR(iod))
1571 return PTR_ERR(iod);
a53295b6
MW		 1572
1573 memset(&c, 0, sizeof(c));
1574 c.rw.opcode = io.opcode;
1575 c.rw.flags = io.flags;
6c7d4945 1576 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1577 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1578 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1579 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1580 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1581 c.rw.reftag = cpu_to_le32(io.reftag);
1582 c.rw.apptag = cpu_to_le16(io.apptag);
1583 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1584
1585 if (meta_len) {
1b56749e
KB		 1586 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1587 meta_len);
f410c680
KB		 1588 if (IS_ERR(meta_iod)) {
1589 status = PTR_ERR(meta_iod);
1590 meta_iod = NULL;
1591 goto unmap;
1592 }
1593
1594 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1595 &meta_dma_addr, GFP_KERNEL);
1596 if (!meta_mem) {
1597 status = -ENOMEM;
1598 goto unmap;
1599 }
1600
1601 if (io.opcode & 1) {
1602 int meta_offset = 0;
1603
1604 for (i = 0; i < meta_iod->nents; i++) {
1605 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1606 meta_iod->sg[i].offset;
1607 memcpy(meta_mem + meta_offset, meta,
1608 meta_iod->sg[i].length);
1609 kunmap_atomic(meta);
1610 meta_offset += meta_iod->sg[i].length;
1611 }
1612 }
1613
1614 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1615 }
1616
edd10d33
KB		 1617 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1618 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1619 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1620
b77954cb
MW		 1621 if (length != (io.nblocks + 1) << ns->lba_shift)
1622 status = -ENOMEM;
1623 else
4f5099af 1624 status = nvme_submit_io_cmd(dev, &c, NULL);
a53295b6 1625
f410c680
KB		 1626 if (meta_len) {
1627 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1628 int meta_offset = 0;
1629
1630 for (i = 0; i < meta_iod->nents; i++) {
1631 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1632 meta_iod->sg[i].offset;
1633 memcpy(meta, meta_mem + meta_offset,
1634 meta_iod->sg[i].length);
1635 kunmap_atomic(meta);
1636 meta_offset += meta_iod->sg[i].length;
1637 }
1638 }
1639
1640 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1641 meta_dma_addr);
1642 }
1643
1644 unmap:
1c2ad9fa 1645 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1646 nvme_free_iod(dev, iod);
f410c680
KB		 1647
1648 if (meta_iod) {
1649 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1650 nvme_free_iod(dev, meta_iod);
1651 }
1652
a53295b6
MW		 1653 return status;
1654}
1655
50af8bae 1656static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1657 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1658{
6bbf1acd 1659 struct nvme_admin_cmd cmd;
6ee44cdc 1660 struct nvme_command c;
eca18b23 1661 int status, length;
c7d36ab8 1662 struct nvme_iod *uninitialized_var(iod);
94f370ca 1663 unsigned timeout;
6ee44cdc 1664
6bbf1acd
MW		 1665 if (!capable(CAP_SYS_ADMIN))
1666 return -EACCES;
1667 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1668 return -EFAULT;
6ee44cdc
MW		 1669
1670 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1671 c.common.opcode = cmd.opcode;
1672 c.common.flags = cmd.flags;
1673 c.common.nsid = cpu_to_le32(cmd.nsid);
1674 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1675 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1676 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1677 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1678 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1679 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1680 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1681 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1682
1683 length = cmd.data_len;
1684 if (cmd.data_len) {
49742188
MW		 1685 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1686 length);
eca18b23
MW		 1687 if (IS_ERR(iod))
1688 return PTR_ERR(iod);
edd10d33
KB		 1689 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1690 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1691 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1692 }
1693
94f370ca
KB		 1694 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1695 ADMIN_TIMEOUT;
6bbf1acd 1696 if (length != cmd.data_len)
b77954cb
MW		 1697 status = -ENOMEM;
1698 else
4f5099af 1699 status = nvme_submit_sync_cmd(dev, 0, &c, &cmd.result, timeout);
eca18b23 1700
6bbf1acd 1701 if (cmd.data_len) {
1c2ad9fa 1702 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1703 nvme_free_iod(dev, iod);
6bbf1acd 1704 }
f4f117f6 1705
cf90bc48 1706 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1707 sizeof(cmd.result)))
1708 status = -EFAULT;
1709
6ee44cdc
MW		 1710 return status;
1711}
1712
b60503ba
MW		 1713static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1714 unsigned long arg)
1715{
1716 struct nvme_ns *ns = bdev->bd_disk->private_data;
1717
1718 switch (cmd) {
6bbf1acd 1719 case NVME_IOCTL_ID:
c3bfe717 1720 force_successful_syscall_return();
6bbf1acd
MW		 1721 return ns->ns_id;
1722 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1723 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW		 1724 case NVME_IOCTL_SUBMIT_IO:
1725 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1726 case SG_GET_VERSION_NUM:
1727 return nvme_sg_get_version_num((void __user *)arg);
1728 case SG_IO:
1729 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1730 default:
1731 return -ENOTTY;
1732 }
1733}
1734
320a3827
KB		 1735#ifdef CONFIG_COMPAT
1736static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1737 unsigned int cmd, unsigned long arg)
1738{
1739 struct nvme_ns *ns = bdev->bd_disk->private_data;
1740
1741 switch (cmd) {
1742 case SG_IO:
1743 return nvme_sg_io32(ns, arg);
1744 }
1745 return nvme_ioctl(bdev, mode, cmd, arg);
1746}
1747#else
1748#define nvme_compat_ioctl NULL
1749#endif
1750
9ac27090
KB		 1751static int nvme_open(struct block_device *bdev, fmode_t mode)
1752{
1753 struct nvme_ns *ns = bdev->bd_disk->private_data;
1754 struct nvme_dev *dev = ns->dev;
1755
1756 kref_get(&dev->kref);
1757 return 0;
1758}
1759
1760static void nvme_free_dev(struct kref *kref);
1761
1762static void nvme_release(struct gendisk *disk, fmode_t mode)
1763{
1764 struct nvme_ns *ns = disk->private_data;
1765 struct nvme_dev *dev = ns->dev;
1766
1767 kref_put(&dev->kref, nvme_free_dev);
1768}
1769
4cc09e2d
KB		 1770static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1771{
1772 /* some standard values */
1773 geo->heads = 1 << 6;
1774 geo->sectors = 1 << 5;
1775 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1776 return 0;
1777}
1778
b60503ba
MW		 1779static const struct block_device_operations nvme_fops = {
1780 .owner = THIS_MODULE,
1781 .ioctl = nvme_ioctl,
320a3827 1782 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1783 .open = nvme_open,
1784 .release = nvme_release,
4cc09e2d 1785 .getgeo = nvme_getgeo,
b60503ba
MW		 1786};
1787
edd10d33
KB		 1788static void nvme_resubmit_iods(struct nvme_queue *nvmeq)
1789{
1790 struct nvme_iod *iod, *next;
1791
1792 list_for_each_entry_safe(iod, next, &nvmeq->iod_bio, node) {
1793 if (unlikely(nvme_submit_iod(nvmeq, iod)))
1794 break;
1795 list_del(&iod->node);
1796 if (bio_list_empty(&nvmeq->sq_cong) &&
1797 list_empty(&nvmeq->iod_bio))
1798 remove_wait_queue(&nvmeq->sq_full,
1799 &nvmeq->sq_cong_wait);
1800 }
1801}
1802
1fa6aead
MW		 1803static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1804{
1805 while (bio_list_peek(&nvmeq->sq_cong)) {
1806 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1807 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
427e9708 1808
edd10d33
KB		 1809 if (bio_list_empty(&nvmeq->sq_cong) &&
1810 list_empty(&nvmeq->iod_bio))
427e9708
KB		 1811 remove_wait_queue(&nvmeq->sq_full,
1812 &nvmeq->sq_cong_wait);
1fa6aead 1813 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
edd10d33 1814 if (!waitqueue_active(&nvmeq->sq_full))
427e9708
KB		 1815 add_wait_queue(&nvmeq->sq_full,
1816 &nvmeq->sq_cong_wait);
1fa6aead
MW		 1817 bio_list_add_head(&nvmeq->sq_cong, bio);
1818 break;
1819 }
1820 }
1821}
1822
1823static int nvme_kthread(void *data)
1824{
d4b4ff8e 1825 struct nvme_dev *dev, *next;
1fa6aead
MW		 1826
1827 while (!kthread_should_stop()) {
564a232c 1828 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1829 spin_lock(&dev_list_lock);
d4b4ff8e 1830 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1831 int i;
d4b4ff8e
KB		 1832 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1833 dev->initialized) {
1834 if (work_busy(&dev->reset_work))
1835 continue;
1836 list_del_init(&dev->node);
1837 dev_warn(&dev->pci_dev->dev,
1838 "Failed status, reset controller\n");
9ca97374 1839 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 1840 queue_work(nvme_workq, &dev->reset_work);
1841 continue;
1842 }
5a92e700 1843 rcu_read_lock();
1fa6aead 1844 for (i = 0; i < dev->queue_count; i++) {
5a92e700
KB		 1845 struct nvme_queue *nvmeq =
1846 rcu_dereference(dev->queues[i]);
740216fc
MW		 1847 if (!nvmeq)
1848 continue;
1fa6aead 1849 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1850 if (nvmeq->q_suspended)
1851 goto unlock;
bc57a0f7 1852 nvme_process_cq(nvmeq);
a09115b2 1853 nvme_cancel_ios(nvmeq, true);
1fa6aead 1854 nvme_resubmit_bios(nvmeq);
edd10d33 1855 nvme_resubmit_iods(nvmeq);
22404274 1856 unlock:
1fa6aead
MW		 1857 spin_unlock_irq(&nvmeq->q_lock);
1858 }
5a92e700 1859 rcu_read_unlock();
1fa6aead
MW		 1860 }
1861 spin_unlock(&dev_list_lock);
acb7aa0d 1862 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1863 }
1864 return 0;
1865}
1866
0e5e4f0e
KB		 1867static void nvme_config_discard(struct nvme_ns *ns)
1868{
1869 u32 logical_block_size = queue_logical_block_size(ns->queue);
1870 ns->queue->limits.discard_zeroes_data = 0;
1871 ns->queue->limits.discard_alignment = logical_block_size;
1872 ns->queue->limits.discard_granularity = logical_block_size;
1873 ns->queue->limits.max_discard_sectors = 0xffffffff;
1874 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1875}
1876
c3bfe717 1877static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1878 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1879{
1880 struct nvme_ns *ns;
1881 struct gendisk *disk;
1882 int lbaf;
1883
1884 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1885 return NULL;
1886
1887 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1888 if (!ns)
1889 return NULL;
1890 ns->queue = blk_alloc_queue(GFP_KERNEL);
1891 if (!ns->queue)
1892 goto out_free_ns;
4eeb9215
MW		 1893 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1894 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1895 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 1896 blk_queue_make_request(ns->queue, nvme_make_request);
1897 ns->dev = dev;
1898 ns->queue->queuedata = ns;
1899
469071a3 1900 disk = alloc_disk(0);
b60503ba
MW		 1901 if (!disk)
1902 goto out_free_queue;
5aff9382 1903 ns->ns_id = nsid;
b60503ba
MW		 1904 ns->disk = disk;
1905 lbaf = id->flbas & 0xf;
1906 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1907 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1908 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1909 if (dev->max_hw_sectors)
1910 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a7d2ce28
KB		 1911 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
1912 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 1913
1914 disk->major = nvme_major;
469071a3 1915 disk->first_minor = 0;
b60503ba
MW		 1916 disk->fops = &nvme_fops;
1917 disk->private_data = ns;
1918 disk->queue = ns->queue;
388f037f 1919 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1920 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1921 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1922 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1923
0e5e4f0e
KB		 1924 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1925 nvme_config_discard(ns);
1926
b60503ba
MW		 1927 return ns;
1928
1929 out_free_queue:
1930 blk_cleanup_queue(ns->queue);
1931 out_free_ns:
1932 kfree(ns);
1933 return NULL;
1934}
1935
42f61420
KB		 1936static int nvme_find_closest_node(int node)
1937{
1938 int n, val, min_val = INT_MAX, best_node = node;
1939
1940 for_each_online_node(n) {
1941 if (n == node)
1942 continue;
1943 val = node_distance(node, n);
1944 if (val < min_val) {
1945 min_val = val;
1946 best_node = n;
1947 }
1948 }
1949 return best_node;
1950}
1951
1952static void nvme_set_queue_cpus(cpumask_t *qmask, struct nvme_queue *nvmeq,
1953 int count)
1954{
1955 int cpu;
1956 for_each_cpu(cpu, qmask) {
1957 if (cpumask_weight(nvmeq->cpu_mask) >= count)
1958 break;
1959 if (!cpumask_test_and_set_cpu(cpu, nvmeq->cpu_mask))
1960 *per_cpu_ptr(nvmeq->dev->io_queue, cpu) = nvmeq->qid;
1961 }
1962}
1963
1964static void nvme_add_cpus(cpumask_t *mask, const cpumask_t *unassigned_cpus,
1965 const cpumask_t *new_mask, struct nvme_queue *nvmeq, int cpus_per_queue)
1966{
1967 int next_cpu;
1968 for_each_cpu(next_cpu, new_mask) {
1969 cpumask_or(mask, mask, get_cpu_mask(next_cpu));
1970 cpumask_or(mask, mask, topology_thread_cpumask(next_cpu));
1971 cpumask_and(mask, mask, unassigned_cpus);
1972 nvme_set_queue_cpus(mask, nvmeq, cpus_per_queue);
1973 }
1974}
1975
1976static void nvme_create_io_queues(struct nvme_dev *dev)
1977{
1978 unsigned i, max;
1979
1980 max = min(dev->max_qid, num_online_cpus());
1981 for (i = dev->queue_count; i <= max; i++)
1982 if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1))
1983 break;
1984
1985 max = min(dev->queue_count - 1, num_online_cpus());
1986 for (i = dev->online_queues; i <= max; i++)
1987 if (nvme_create_queue(raw_nvmeq(dev, i), i))
1988 break;
1989}
1990
1991/*
1992 * If there are fewer queues than online cpus, this will try to optimally
1993 * assign a queue to multiple cpus by grouping cpus that are "close" together:
1994 * thread siblings, core, socket, closest node, then whatever else is
1995 * available.
1996 */
1997static void nvme_assign_io_queues(struct nvme_dev *dev)
1998{
1999 unsigned cpu, cpus_per_queue, queues, remainder, i;
2000 cpumask_var_t unassigned_cpus;
2001
2002 nvme_create_io_queues(dev);
2003
2004 queues = min(dev->online_queues - 1, num_online_cpus());
2005 if (!queues)
2006 return;
2007
2008 cpus_per_queue = num_online_cpus() / queues;
2009 remainder = queues - (num_online_cpus() - queues * cpus_per_queue);
2010
2011 if (!alloc_cpumask_var(&unassigned_cpus, GFP_KERNEL))
2012 return;
2013
2014 cpumask_copy(unassigned_cpus, cpu_online_mask);
2015 cpu = cpumask_first(unassigned_cpus);
2016 for (i = 1; i <= queues; i++) {
2017 struct nvme_queue *nvmeq = lock_nvmeq(dev, i);
2018 cpumask_t mask;
2019
2020 cpumask_clear(nvmeq->cpu_mask);
2021 if (!cpumask_weight(unassigned_cpus)) {
2022 unlock_nvmeq(nvmeq);
2023 break;
2024 }
2025
2026 mask = *get_cpu_mask(cpu);
2027 nvme_set_queue_cpus(&mask, nvmeq, cpus_per_queue);
2028 if (cpus_weight(mask) < cpus_per_queue)
2029 nvme_add_cpus(&mask, unassigned_cpus,
2030 topology_thread_cpumask(cpu),
2031 nvmeq, cpus_per_queue);
2032 if (cpus_weight(mask) < cpus_per_queue)
2033 nvme_add_cpus(&mask, unassigned_cpus,
2034 topology_core_cpumask(cpu),
2035 nvmeq, cpus_per_queue);
2036 if (cpus_weight(mask) < cpus_per_queue)
2037 nvme_add_cpus(&mask, unassigned_cpus,
2038 cpumask_of_node(cpu_to_node(cpu)),
2039 nvmeq, cpus_per_queue);
2040 if (cpus_weight(mask) < cpus_per_queue)
2041 nvme_add_cpus(&mask, unassigned_cpus,
2042 cpumask_of_node(
2043 nvme_find_closest_node(
2044 cpu_to_node(cpu))),
2045 nvmeq, cpus_per_queue);
2046 if (cpus_weight(mask) < cpus_per_queue)
2047 nvme_add_cpus(&mask, unassigned_cpus,
2048 unassigned_cpus,
2049 nvmeq, cpus_per_queue);
2050
2051 WARN(cpumask_weight(nvmeq->cpu_mask) != cpus_per_queue,
2052 "nvme%d qid:%d mis-matched queue-to-cpu assignment\n",
2053 dev->instance, i);
2054
2055 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2056 nvmeq->cpu_mask);
2057 cpumask_andnot(unassigned_cpus, unassigned_cpus,
2058 nvmeq->cpu_mask);
2059 cpu = cpumask_next(cpu, unassigned_cpus);
2060 if (remainder && !--remainder)
2061 cpus_per_queue++;
2062 unlock_nvmeq(nvmeq);
2063 }
2064 WARN(cpumask_weight(unassigned_cpus), "nvme%d unassigned online cpus\n",
2065 dev->instance);
2066 i = 0;
2067 cpumask_andnot(unassigned_cpus, cpu_possible_mask, cpu_online_mask);
2068 for_each_cpu(cpu, unassigned_cpus)
2069 *per_cpu_ptr(dev->io_queue, cpu) = (i++ % queues) + 1;
2070 free_cpumask_var(unassigned_cpus);
2071}
2072
b3b06812 2073static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2074{
2075 int status;
2076 u32 result;
b3b06812 2077 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2078
df348139 2079 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2080 &result);
27e8166c
MW		 2081 if (status < 0)
2082 return status;
2083 if (status > 0) {
2084 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2085 status);
2086 return -EBUSY;
2087 }
b60503ba
MW		 2088 return min(result & 0xffff, result >> 16) + 1;
2089}
2090
9d713c2b
KB		 2091static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2092{
b80d5ccc 2093 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2094}
2095
33b1e95c
KB		 2096static int nvme_cpu_notify(struct notifier_block *self,
2097 unsigned long action, void *hcpu)
2098{
2099 struct nvme_dev *dev = container_of(self, struct nvme_dev, nb);
2100 switch (action) {
2101 case CPU_ONLINE:
2102 case CPU_DEAD:
2103 nvme_assign_io_queues(dev);
2104 break;
2105 }
2106 return NOTIFY_OK;
2107}
2108
8d85fce7 2109static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2110{
5a92e700 2111 struct nvme_queue *adminq = raw_nvmeq(dev, 0);
fa08a396 2112 struct pci_dev *pdev = dev->pci_dev;
42f61420 2113 int result, i, vecs, nr_io_queues, size;
b60503ba 2114
42f61420 2115 nr_io_queues = num_possible_cpus();
b348b7d5 2116 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW		 2117 if (result < 0)
2118 return result;
b348b7d5
MW		 2119 if (result < nr_io_queues)
2120 nr_io_queues = result;
b60503ba 2121
9d713c2b
KB		 2122 size = db_bar_size(dev, nr_io_queues);
2123 if (size > 8192) {
f1938f6e 2124 iounmap(dev->bar);
9d713c2b
KB		 2125 do {
2126 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2127 if (dev->bar)
2128 break;
2129 if (!--nr_io_queues)
2130 return -ENOMEM;
2131 size = db_bar_size(dev, nr_io_queues);
2132 } while (1);
f1938f6e 2133 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2134 adminq->q_db = dev->dbs;
f1938f6e
MW		 2135 }
2136
9d713c2b 2137 /* Deregister the admin queue's interrupt */
3193f07b 2138 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2139
be577fab 2140 for (i = 0; i < nr_io_queues; i++)
1b23484b 2141 dev->entry[i].entry = i;
be577fab
AG		 2142 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2143 if (vecs < 0) {
2144 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2145 if (vecs < 0) {
2146 vecs = 1;
2147 } else {
2148 for (i = 0; i < vecs; i++)
2149 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2150 }
2151 }
2152
063a8096
MW		 2153 /*
2154 * Should investigate if there's a performance win from allocating
2155 * more queues than interrupt vectors; it might allow the submission
2156 * path to scale better, even if the receive path is limited by the
2157 * number of interrupts.
2158 */
2159 nr_io_queues = vecs;
42f61420 2160 dev->max_qid = nr_io_queues;
063a8096 2161
3193f07b 2162 result = queue_request_irq(dev, adminq, adminq->irqname);
9d713c2b 2163 if (result) {
3193f07b 2164 adminq->q_suspended = 1;
22404274 2165 goto free_queues;
9d713c2b 2166 }
1b23484b 2167
cd638946 2168 /* Free previously allocated queues that are no longer usable */
42f61420
KB		 2169 nvme_free_queues(dev, nr_io_queues + 1);
2170 nvme_assign_io_queues(dev);
9ecdc946 2171
33b1e95c
KB		 2172 dev->nb.notifier_call = &nvme_cpu_notify;
2173 result = register_hotcpu_notifier(&dev->nb);
2174 if (result)
2175 goto free_queues;
b60503ba 2176
22404274 2177 return 0;
b60503ba 2178
22404274 2179 free_queues:
a1a5ef99 2180 nvme_free_queues(dev, 1);
22404274 2181 return result;
b60503ba
MW		 2182}
2183
422ef0c7
MW		 2184/*
2185 * Return: error value if an error occurred setting up the queues or calling
2186 * Identify Device. 0 if these succeeded, even if adding some of the
2187 * namespaces failed. At the moment, these failures are silent. TBD which
2188 * failures should be reported.
2189 */
8d85fce7 2190static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2191{
68608c26 2192 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2193 int res;
2194 unsigned nn, i;
cbb6218f 2195 struct nvme_ns *ns;
51814232 2196 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2197 struct nvme_id_ns *id_ns;
2198 void *mem;
b60503ba 2199 dma_addr_t dma_addr;
159b67d7 2200 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2201
68608c26 2202 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2203 if (!mem)
2204 return -ENOMEM;
b60503ba 2205
bc5fc7e4 2206 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2207 if (res) {
27e8166c 2208 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
b60503ba 2209 res = -EIO;
cbb6218f 2210 goto out;
b60503ba
MW		 2211 }
2212
bc5fc7e4 2213 ctrl = mem;
51814232 2214 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2215 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2216 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2217 dev->vwc = ctrl->vwc;
51814232
MW		 2218 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2219 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2220 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2221 if (ctrl->mdts)
8fc23e03 2222 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26
MW		 2223 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2224 (pdev->device == 0x0953) && ctrl->vs[3])
159b67d7 2225 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
b60503ba 2226
bc5fc7e4 2227 id_ns = mem;
2b2c1896 2228 for (i = 1; i <= nn; i++) {
bc5fc7e4 2229 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2230 if (res)
2231 continue;
2232
bc5fc7e4 2233 if (id_ns->ncap == 0)
b60503ba
MW		 2234 continue;
2235
bc5fc7e4 2236 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2237 dma_addr + 4096, NULL);
b60503ba 2238 if (res)
12209036 2239 memset(mem + 4096, 0, 4096);
b60503ba 2240
bc5fc7e4 2241 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2242 if (ns)
2243 list_add_tail(&ns->list, &dev->namespaces);
2244 }
2245 list_for_each_entry(ns, &dev->namespaces, list)
2246 add_disk(ns->disk);
422ef0c7 2247 res = 0;
b60503ba 2248
bc5fc7e4 2249 out:
684f5c20 2250 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2251 return res;
2252}
2253
0877cb0d
KB		 2254static int nvme_dev_map(struct nvme_dev *dev)
2255{
42f61420 2256 u64 cap;
0877cb0d
KB		 2257 int bars, result = -ENOMEM;
2258 struct pci_dev *pdev = dev->pci_dev;
2259
2260 if (pci_enable_device_mem(pdev))
2261 return result;
2262
2263 dev->entry[0].vector = pdev->irq;
2264 pci_set_master(pdev);
2265 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2266 if (pci_request_selected_regions(pdev, bars, "nvme"))
2267 goto disable_pci;
2268
052d0efa
RK		 2269 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2270 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2271 goto disable;
0877cb0d 2272
0877cb0d
KB		 2273 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2274 if (!dev->bar)
2275 goto disable;
0e53d180
KB		 2276 if (readl(&dev->bar->csts) == -1) {
2277 result = -ENODEV;
2278 goto unmap;
2279 }
42f61420
KB		 2280 cap = readq(&dev->bar->cap);
2281 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2282 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2283 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2284
2285 return 0;
2286
0e53d180
KB		 2287 unmap:
2288 iounmap(dev->bar);
2289 dev->bar = NULL;
0877cb0d
KB		 2290 disable:
2291 pci_release_regions(pdev);
2292 disable_pci:
2293 pci_disable_device(pdev);
2294 return result;
2295}
2296
2297static void nvme_dev_unmap(struct nvme_dev *dev)
2298{
2299 if (dev->pci_dev->msi_enabled)
2300 pci_disable_msi(dev->pci_dev);
2301 else if (dev->pci_dev->msix_enabled)
2302 pci_disable_msix(dev->pci_dev);
2303
2304 if (dev->bar) {
2305 iounmap(dev->bar);
2306 dev->bar = NULL;
9a6b9458 2307 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2308 }
2309
0877cb0d
KB		 2310 if (pci_is_enabled(dev->pci_dev))
2311 pci_disable_device(dev->pci_dev);
2312}
2313
4d115420
KB		 2314struct nvme_delq_ctx {
2315 struct task_struct *waiter;
2316 struct kthread_worker *worker;
2317 atomic_t refcount;
2318};
2319
2320static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2321{
2322 dq->waiter = current;
2323 mb();
2324
2325 for (;;) {
2326 set_current_state(TASK_KILLABLE);
2327 if (!atomic_read(&dq->refcount))
2328 break;
2329 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2330 fatal_signal_pending(current)) {
2331 set_current_state(TASK_RUNNING);
2332
2333 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2334 nvme_disable_queue(dev, 0);
2335
2336 send_sig(SIGKILL, dq->worker->task, 1);
2337 flush_kthread_worker(dq->worker);
2338 return;
2339 }
2340 }
2341 set_current_state(TASK_RUNNING);
2342}
2343
2344static void nvme_put_dq(struct nvme_delq_ctx *dq)
2345{
2346 atomic_dec(&dq->refcount);
2347 if (dq->waiter)
2348 wake_up_process(dq->waiter);
2349}
2350
2351static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2352{
2353 atomic_inc(&dq->refcount);
2354 return dq;
2355}
2356
2357static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2358{
2359 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2360
2361 nvme_clear_queue(nvmeq);
2362 nvme_put_dq(dq);
2363}
2364
2365static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2366 kthread_work_func_t fn)
2367{
2368 struct nvme_command c;
2369
2370 memset(&c, 0, sizeof(c));
2371 c.delete_queue.opcode = opcode;
2372 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2373
2374 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2375 return nvme_submit_admin_cmd_async(nvmeq->dev, &c, &nvmeq->cmdinfo);
2376}
2377
2378static void nvme_del_cq_work_handler(struct kthread_work *work)
2379{
2380 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2381 cmdinfo.work);
2382 nvme_del_queue_end(nvmeq);
2383}
2384
2385static int nvme_delete_cq(struct nvme_queue *nvmeq)
2386{
2387 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2388 nvme_del_cq_work_handler);
2389}
2390
2391static void nvme_del_sq_work_handler(struct kthread_work *work)
2392{
2393 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2394 cmdinfo.work);
2395 int status = nvmeq->cmdinfo.status;
2396
2397 if (!status)
2398 status = nvme_delete_cq(nvmeq);
2399 if (status)
2400 nvme_del_queue_end(nvmeq);
2401}
2402
2403static int nvme_delete_sq(struct nvme_queue *nvmeq)
2404{
2405 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2406 nvme_del_sq_work_handler);
2407}
2408
2409static void nvme_del_queue_start(struct kthread_work *work)
2410{
2411 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2412 cmdinfo.work);
2413 allow_signal(SIGKILL);
2414 if (nvme_delete_sq(nvmeq))
2415 nvme_del_queue_end(nvmeq);
2416}
2417
2418static void nvme_disable_io_queues(struct nvme_dev *dev)
2419{
2420 int i;
2421 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2422 struct nvme_delq_ctx dq;
2423 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2424 &worker, "nvme%d", dev->instance);
2425
2426 if (IS_ERR(kworker_task)) {
2427 dev_err(&dev->pci_dev->dev,
2428 "Failed to create queue del task\n");
2429 for (i = dev->queue_count - 1; i > 0; i--)
2430 nvme_disable_queue(dev, i);
2431 return;
2432 }
2433
2434 dq.waiter = NULL;
2435 atomic_set(&dq.refcount, 0);
2436 dq.worker = &worker;
2437 for (i = dev->queue_count - 1; i > 0; i--) {
5a92e700 2438 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2439
2440 if (nvme_suspend_queue(nvmeq))
2441 continue;
2442 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2443 nvmeq->cmdinfo.worker = dq.worker;
2444 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2445 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2446 }
2447 nvme_wait_dq(&dq, dev);
2448 kthread_stop(kworker_task);
2449}
2450
b9afca3e
DM		 2451/*
2452* Remove the node from the device list and check
2453* for whether or not we need to stop the nvme_thread.
2454*/
2455static void nvme_dev_list_remove(struct nvme_dev *dev)
2456{
2457 struct task_struct *tmp = NULL;
2458
2459 spin_lock(&dev_list_lock);
2460 list_del_init(&dev->node);
2461 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2462 tmp = nvme_thread;
2463 nvme_thread = NULL;
2464 }
2465 spin_unlock(&dev_list_lock);
2466
2467 if (tmp)
2468 kthread_stop(tmp);
2469}
2470
f0b50732 2471static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2472{
22404274
KB		 2473 int i;
2474
d4b4ff8e 2475 dev->initialized = 0;
33b1e95c 2476 unregister_hotcpu_notifier(&dev->nb);
b60503ba 2477
b9afca3e 2478 nvme_dev_list_remove(dev);
1fa6aead 2479
4d115420
KB		 2480 if (!dev->bar || (dev->bar && readl(&dev->bar->csts) == -1)) {
2481 for (i = dev->queue_count - 1; i >= 0; i--) {
5a92e700 2482 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2483 nvme_suspend_queue(nvmeq);
2484 nvme_clear_queue(nvmeq);
2485 }
2486 } else {
2487 nvme_disable_io_queues(dev);
1894d8f1 2488 nvme_shutdown_ctrl(dev);
4d115420
KB		 2489 nvme_disable_queue(dev, 0);
2490 }
f0b50732
KB		 2491 nvme_dev_unmap(dev);
2492}
2493
2494static void nvme_dev_remove(struct nvme_dev *dev)
2495{
9ac27090 2496 struct nvme_ns *ns;
f0b50732 2497
9ac27090
KB		 2498 list_for_each_entry(ns, &dev->namespaces, list) {
2499 if (ns->disk->flags & GENHD_FL_UP)
2500 del_gendisk(ns->disk);
2501 if (!blk_queue_dying(ns->queue))
2502 blk_cleanup_queue(ns->queue);
b60503ba 2503 }
b60503ba
MW		 2504}
2505
091b6092
MW		 2506static int nvme_setup_prp_pools(struct nvme_dev *dev)
2507{
2508 struct device *dmadev = &dev->pci_dev->dev;
2509 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2510 PAGE_SIZE, PAGE_SIZE, 0);
2511 if (!dev->prp_page_pool)
2512 return -ENOMEM;
2513
99802a7a
MW		 2514 /* Optimisation for I/Os between 4k and 128k */
2515 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2516 256, 256, 0);
2517 if (!dev->prp_small_pool) {
2518 dma_pool_destroy(dev->prp_page_pool);
2519 return -ENOMEM;
2520 }
091b6092
MW		 2521 return 0;
2522}
2523
2524static void nvme_release_prp_pools(struct nvme_dev *dev)
2525{
2526 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2527 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2528}
2529
cd58ad7d
QSA		 2530static DEFINE_IDA(nvme_instance_ida);
2531
2532static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2533{
cd58ad7d
QSA		 2534 int instance, error;
2535
2536 do {
2537 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2538 return -ENODEV;
2539
2540 spin_lock(&dev_list_lock);
2541 error = ida_get_new(&nvme_instance_ida, &instance);
2542 spin_unlock(&dev_list_lock);
2543 } while (error == -EAGAIN);
2544
2545 if (error)
2546 return -ENODEV;
2547
2548 dev->instance = instance;
2549 return 0;
b60503ba
MW		 2550}
2551
2552static void nvme_release_instance(struct nvme_dev *dev)
2553{
cd58ad7d
QSA		 2554 spin_lock(&dev_list_lock);
2555 ida_remove(&nvme_instance_ida, dev->instance);
2556 spin_unlock(&dev_list_lock);
b60503ba
MW		 2557}
2558
9ac27090
KB		 2559static void nvme_free_namespaces(struct nvme_dev *dev)
2560{
2561 struct nvme_ns *ns, *next;
2562
2563 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2564 list_del(&ns->list);
2565 put_disk(ns->disk);
2566 kfree(ns);
2567 }
2568}
2569
5e82e952
KB		 2570static void nvme_free_dev(struct kref *kref)
2571{
2572 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090
KB		 2573
2574 nvme_free_namespaces(dev);
42f61420 2575 free_percpu(dev->io_queue);
5e82e952
KB		 2576 kfree(dev->queues);
2577 kfree(dev->entry);
2578 kfree(dev);
2579}
2580
2581static int nvme_dev_open(struct inode *inode, struct file *f)
2582{
2583 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2584 miscdev);
2585 kref_get(&dev->kref);
2586 f->private_data = dev;
2587 return 0;
2588}
2589
2590static int nvme_dev_release(struct inode *inode, struct file *f)
2591{
2592 struct nvme_dev *dev = f->private_data;
2593 kref_put(&dev->kref, nvme_free_dev);
2594 return 0;
2595}
2596
2597static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2598{
2599 struct nvme_dev *dev = f->private_data;
2600 switch (cmd) {
2601 case NVME_IOCTL_ADMIN_CMD:
2602 return nvme_user_admin_cmd(dev, (void __user *)arg);
2603 default:
2604 return -ENOTTY;
2605 }
2606}
2607
2608static const struct file_operations nvme_dev_fops = {
2609 .owner = THIS_MODULE,
2610 .open = nvme_dev_open,
2611 .release = nvme_dev_release,
2612 .unlocked_ioctl = nvme_dev_ioctl,
2613 .compat_ioctl = nvme_dev_ioctl,
2614};
2615
f0b50732
KB		 2616static int nvme_dev_start(struct nvme_dev *dev)
2617{
2618 int result;
b9afca3e 2619 bool start_thread = false;
f0b50732
KB		 2620
2621 result = nvme_dev_map(dev);
2622 if (result)
2623 return result;
2624
2625 result = nvme_configure_admin_queue(dev);
2626 if (result)
2627 goto unmap;
2628
2629 spin_lock(&dev_list_lock);
b9afca3e
DM		 2630 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2631 start_thread = true;
2632 nvme_thread = NULL;
2633 }
f0b50732
KB		 2634 list_add(&dev->node, &dev_list);
2635 spin_unlock(&dev_list_lock);
2636
b9afca3e
DM		 2637 if (start_thread) {
2638 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2639 wake_up(&nvme_kthread_wait);
2640 } else
2641 wait_event_killable(nvme_kthread_wait, nvme_thread);
2642
2643 if (IS_ERR_OR_NULL(nvme_thread)) {
2644 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2645 goto disable;
2646 }
2647
f0b50732 2648 result = nvme_setup_io_queues(dev);
d82e8bfd 2649 if (result && result != -EBUSY)
f0b50732
KB		 2650 goto disable;
2651
d82e8bfd 2652 return result;
f0b50732
KB		 2653
2654 disable:
a1a5ef99 2655 nvme_disable_queue(dev, 0);
b9afca3e 2656 nvme_dev_list_remove(dev);
f0b50732
KB		 2657 unmap:
2658 nvme_dev_unmap(dev);
2659 return result;
2660}
2661
9a6b9458
KB		 2662static int nvme_remove_dead_ctrl(void *arg)
2663{
2664 struct nvme_dev *dev = (struct nvme_dev *)arg;
2665 struct pci_dev *pdev = dev->pci_dev;
2666
2667 if (pci_get_drvdata(pdev))
2668 pci_stop_and_remove_bus_device(pdev);
2669 kref_put(&dev->kref, nvme_free_dev);
2670 return 0;
2671}
2672
2673static void nvme_remove_disks(struct work_struct *ws)
2674{
9a6b9458
KB		 2675 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2676
2677 nvme_dev_remove(dev);
5a92e700 2678 nvme_free_queues(dev, 1);
9a6b9458
KB		 2679}
2680
2681static int nvme_dev_resume(struct nvme_dev *dev)
2682{
2683 int ret;
2684
2685 ret = nvme_dev_start(dev);
2686 if (ret && ret != -EBUSY)
2687 return ret;
2688 if (ret == -EBUSY) {
2689 spin_lock(&dev_list_lock);
9ca97374 2690 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2691 queue_work(nvme_workq, &dev->reset_work);
2692 spin_unlock(&dev_list_lock);
2693 }
d4b4ff8e 2694 dev->initialized = 1;
9a6b9458
KB		 2695 return 0;
2696}
2697
2698static void nvme_dev_reset(struct nvme_dev *dev)
2699{
2700 nvme_dev_shutdown(dev);
2701 if (nvme_dev_resume(dev)) {
2702 dev_err(&dev->pci_dev->dev, "Device failed to resume\n");
2703 kref_get(&dev->kref);
2704 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2705 dev->instance))) {
2706 dev_err(&dev->pci_dev->dev,
2707 "Failed to start controller remove task\n");
2708 kref_put(&dev->kref, nvme_free_dev);
2709 }
2710 }
2711}
2712
2713static void nvme_reset_failed_dev(struct work_struct *ws)
2714{
2715 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2716 nvme_dev_reset(dev);
2717}
2718
9ca97374
TH		 2719static void nvme_reset_workfn(struct work_struct *work)
2720{
2721 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2722 dev->reset_workfn(work);
2723}
2724
8d85fce7 2725static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2726{
0877cb0d 2727 int result = -ENOMEM;
b60503ba
MW		 2728 struct nvme_dev *dev;
2729
2730 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2731 if (!dev)
2732 return -ENOMEM;
2733 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2734 GFP_KERNEL);
2735 if (!dev->entry)
2736 goto free;
1b23484b
MW		 2737 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2738 GFP_KERNEL);
b60503ba
MW		 2739 if (!dev->queues)
2740 goto free;
42f61420
KB		 2741 dev->io_queue = alloc_percpu(unsigned short);
2742 if (!dev->io_queue)
2743 goto free;
b60503ba
MW		 2744
2745 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2746 dev->reset_workfn = nvme_reset_failed_dev;
2747 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
b60503ba 2748 dev->pci_dev = pdev;
9a6b9458 2749 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2750 result = nvme_set_instance(dev);
2751 if (result)
0877cb0d 2752 goto free;
b60503ba 2753
091b6092
MW		 2754 result = nvme_setup_prp_pools(dev);
2755 if (result)
0877cb0d 2756 goto release;
091b6092 2757
fb35e914 2758 kref_init(&dev->kref);
f0b50732 2759 result = nvme_dev_start(dev);
d82e8bfd
KB		 2760 if (result) {
2761 if (result == -EBUSY)
2762 goto create_cdev;
0877cb0d 2763 goto release_pools;
d82e8bfd 2764 }
b60503ba 2765
740216fc 2766 result = nvme_dev_add(dev);
d82e8bfd 2767 if (result)
f0b50732 2768 goto shutdown;
740216fc 2769
d82e8bfd 2770 create_cdev:
5e82e952
KB		 2771 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2772 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2773 dev->miscdev.parent = &pdev->dev;
2774 dev->miscdev.name = dev->name;
2775 dev->miscdev.fops = &nvme_dev_fops;
2776 result = misc_register(&dev->miscdev);
2777 if (result)
2778 goto remove;
2779
d4b4ff8e 2780 dev->initialized = 1;
b60503ba
MW		 2781 return 0;
2782
5e82e952
KB		 2783 remove:
2784 nvme_dev_remove(dev);
9ac27090 2785 nvme_free_namespaces(dev);
f0b50732
KB		 2786 shutdown:
2787 nvme_dev_shutdown(dev);
0877cb0d 2788 release_pools:
a1a5ef99 2789 nvme_free_queues(dev, 0);
091b6092 2790 nvme_release_prp_pools(dev);
0877cb0d
KB		 2791 release:
2792 nvme_release_instance(dev);
b60503ba 2793 free:
42f61420 2794 free_percpu(dev->io_queue);
b60503ba
MW		 2795 kfree(dev->queues);
2796 kfree(dev->entry);
2797 kfree(dev);
2798 return result;
2799}
2800
09ece142
KB		 2801static void nvme_shutdown(struct pci_dev *pdev)
2802{
2803 struct nvme_dev *dev = pci_get_drvdata(pdev);
2804 nvme_dev_shutdown(dev);
2805}
2806
8d85fce7 2807static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2808{
2809 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2810
2811 spin_lock(&dev_list_lock);
2812 list_del_init(&dev->node);
2813 spin_unlock(&dev_list_lock);
2814
2815 pci_set_drvdata(pdev, NULL);
2816 flush_work(&dev->reset_work);
5e82e952 2817 misc_deregister(&dev->miscdev);
9a6b9458
KB		 2818 nvme_dev_remove(dev);
2819 nvme_dev_shutdown(dev);
a1a5ef99 2820 nvme_free_queues(dev, 0);
5a92e700 2821 rcu_barrier();
9a6b9458
KB		 2822 nvme_release_instance(dev);
2823 nvme_release_prp_pools(dev);
5e82e952 2824 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2825}
2826
2827/* These functions are yet to be implemented */
2828#define nvme_error_detected NULL
2829#define nvme_dump_registers NULL
2830#define nvme_link_reset NULL
2831#define nvme_slot_reset NULL
2832#define nvme_error_resume NULL
cd638946 2833
671a6018 2834#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2835static int nvme_suspend(struct device *dev)
2836{
2837 struct pci_dev *pdev = to_pci_dev(dev);
2838 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2839
2840 nvme_dev_shutdown(ndev);
2841 return 0;
2842}
2843
2844static int nvme_resume(struct device *dev)
2845{
2846 struct pci_dev *pdev = to_pci_dev(dev);
2847 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2848
9a6b9458 2849 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2850 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 2851 queue_work(nvme_workq, &ndev->reset_work);
2852 }
2853 return 0;
cd638946 2854}
671a6018 2855#endif
cd638946
KB		 2856
2857static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2858
1d352035 2859static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2860 .error_detected = nvme_error_detected,
2861 .mmio_enabled = nvme_dump_registers,
2862 .link_reset = nvme_link_reset,
2863 .slot_reset = nvme_slot_reset,
2864 .resume = nvme_error_resume,
2865};
2866
2867/* Move to pci_ids.h later */
2868#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2869
6eb0d698 2870static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2871 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2872 { 0, }
2873};
2874MODULE_DEVICE_TABLE(pci, nvme_id_table);
2875
2876static struct pci_driver nvme_driver = {
2877 .name = "nvme",
2878 .id_table = nvme_id_table,
2879 .probe = nvme_probe,
8d85fce7 2880 .remove = nvme_remove,
09ece142 2881 .shutdown = nvme_shutdown,
cd638946
KB		 2882 .driver = {
2883 .pm = &nvme_dev_pm_ops,
2884 },
b60503ba
MW		 2885 .err_handler = &nvme_err_handler,
2886};
2887
2888static int __init nvme_init(void)
2889{
0ac13140 2890 int result;
1fa6aead 2891
b9afca3e 2892 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2893
9a6b9458
KB		 2894 nvme_workq = create_singlethread_workqueue("nvme");
2895 if (!nvme_workq)
b9afca3e 2896 return -ENOMEM;
9a6b9458 2897
5c42ea16
KB		 2898 result = register_blkdev(nvme_major, "nvme");
2899 if (result < 0)
9a6b9458 2900 goto kill_workq;
5c42ea16 2901 else if (result > 0)
0ac13140 2902 nvme_major = result;
b60503ba
MW		 2903
2904 result = pci_register_driver(&nvme_driver);
1fa6aead
MW		 2905 if (result)
2906 goto unregister_blkdev;
2907 return 0;
b60503ba 2908
1fa6aead 2909 unregister_blkdev:
b60503ba 2910 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2911 kill_workq:
2912 destroy_workqueue(nvme_workq);
b60503ba
MW		 2913 return result;
2914}
2915
2916static void __exit nvme_exit(void)
2917{
2918 pci_unregister_driver(&nvme_driver);
2919 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2920 destroy_workqueue(nvme_workq);
b9afca3e 2921 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 2922 _nvme_check_size();
b60503ba
MW		 2923}
2924
2925MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2926MODULE_LICENSE("GPL");
6eb0d698 2927MODULE_VERSION("0.9");
b60503ba
MW		 2928module_init(nvme_init);
2929module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)