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NVMe: RCU protected access to io queues
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/nvme.h>
20#include <linux/bio.h>
8de05535 21#include <linux/bitops.h>
b60503ba 22#include <linux/blkdev.h>
fd63e9ce 23#include <linux/delay.h>
b60503ba
MW		 24#include <linux/errno.h>
25#include <linux/fs.h>
26#include <linux/genhd.h>
5aff9382 27#include <linux/idr.h>
b60503ba
MW		 28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/kdev_t.h>
1fa6aead 32#include <linux/kthread.h>
b60503ba
MW		 33#include <linux/kernel.h>
34#include <linux/mm.h>
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/pci.h>
be7b6275 38#include <linux/poison.h>
c3bfe717 39#include <linux/ptrace.h>
b60503ba
MW		 40#include <linux/sched.h>
41#include <linux/slab.h>
42#include <linux/types.h>
5d0f6131 43#include <scsi/sg.h>
797a796a
HM		 44#include <asm-generic/io-64-nonatomic-lo-hi.h>
45
b60503ba
MW		 46#define NVME_Q_DEPTH 1024
47#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
48#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
e85248e5 49#define ADMIN_TIMEOUT (60 * HZ)
b60503ba
MW		 50
51static int nvme_major;
52module_param(nvme_major, int, 0);
53
58ffacb5
MW		 54static int use_threaded_interrupts;
55module_param(use_threaded_interrupts, int, 0);
56
1fa6aead
MW		 57static DEFINE_SPINLOCK(dev_list_lock);
58static LIST_HEAD(dev_list);
59static struct task_struct *nvme_thread;
9a6b9458 60static struct workqueue_struct *nvme_workq;
1fa6aead 61
d4b4ff8e
KB		 62static void nvme_reset_failed_dev(struct work_struct *ws);
63
4d115420
KB		 64struct async_cmd_info {
65 struct kthread_work work;
66 struct kthread_worker *worker;
67 u32 result;
68 int status;
69 void *ctx;
70};
1fa6aead 71
b60503ba
MW		 72/*
73 * An NVM Express queue. Each device has at least two (one for admin
74 * commands and one for I/O commands).
75 */
76struct nvme_queue {
5a92e700 77 struct rcu_head r_head;
b60503ba 78 struct device *q_dmadev;
091b6092 79 struct nvme_dev *dev;
3193f07b 80 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 81 spinlock_t q_lock;
82 struct nvme_command *sq_cmds;
83 volatile struct nvme_completion *cqes;
84 dma_addr_t sq_dma_addr;
85 dma_addr_t cq_dma_addr;
86 wait_queue_head_t sq_full;
1fa6aead 87 wait_queue_t sq_cong_wait;
b60503ba
MW		 88 struct bio_list sq_cong;
89 u32 __iomem *q_db;
90 u16 q_depth;
91 u16 cq_vector;
92 u16 sq_head;
93 u16 sq_tail;
94 u16 cq_head;
c30341dc 95 u16 qid;
e9539f47
MW		 96 u8 cq_phase;
97 u8 cqe_seen;
22404274 98 u8 q_suspended;
4d115420 99 struct async_cmd_info cmdinfo;
b60503ba
MW		 100 unsigned long cmdid_data[];
101};
102
103/*
104 * Check we didin't inadvertently grow the command struct
105 */
106static inline void _nvme_check_size(void)
107{
108 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
109 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
110 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
111 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
112 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 113 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 114 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 115 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
116 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
117 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
118 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 119 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 120}
121
5c1281a3 122typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
c2f5b650
MW		 123 struct nvme_completion *);
124
e85248e5 125struct nvme_cmd_info {
c2f5b650
MW		 126 nvme_completion_fn fn;
127 void *ctx;
e85248e5 128 unsigned long timeout;
c30341dc 129 int aborted;
e85248e5
MW		 130};
131
132static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
133{
134 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
135}
136
22404274
KB		 137static unsigned nvme_queue_extra(int depth)
138{
139 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
140}
141
b60503ba 142/**
714a7a22
MW		 143 * alloc_cmdid() - Allocate a Command ID
144 * @nvmeq: The queue that will be used for this command
145 * @ctx: A pointer that will be passed to the handler
c2f5b650 146 * @handler: The function to call on completion
b60503ba
MW		 147 *
148 * Allocate a Command ID for a queue. The data passed in will
149 * be passed to the completion handler. This is implemented by using
150 * the bottom two bits of the ctx pointer to store the handler ID.
151 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
152 * We can change this if it becomes a problem.
184d2944
MW		 153 *
154 * May be called with local interrupts disabled and the q_lock held,
155 * or with interrupts enabled and no locks held.
b60503ba 156 */
c2f5b650
MW		 157static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
158 nvme_completion_fn handler, unsigned timeout)
b60503ba 159{
e6d15f79 160 int depth = nvmeq->q_depth - 1;
e85248e5 161 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba
MW		 162 int cmdid;
163
b60503ba
MW		 164 do {
165 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
166 if (cmdid >= depth)
167 return -EBUSY;
168 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
169
c2f5b650
MW		 170 info[cmdid].fn = handler;
171 info[cmdid].ctx = ctx;
e85248e5 172 info[cmdid].timeout = jiffies + timeout;
c30341dc 173 info[cmdid].aborted = 0;
b60503ba
MW		 174 return cmdid;
175}
176
177static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 178 nvme_completion_fn handler, unsigned timeout)
b60503ba
MW		 179{
180 int cmdid;
181 wait_event_killable(nvmeq->sq_full,
e85248e5 182 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
b60503ba
MW		 183 return (cmdid < 0) ? -EINTR : cmdid;
184}
185
c2f5b650
MW		 186/* Special values must be less than 0x1000 */
187#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 188#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
189#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
190#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
00df5cb4 191#define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
c30341dc 192#define CMD_CTX_ABORT (0x31C + CMD_CTX_BASE)
be7b6275 193
5c1281a3 194static void special_completion(struct nvme_dev *dev, void *ctx,
c2f5b650
MW		 195 struct nvme_completion *cqe)
196{
197 if (ctx == CMD_CTX_CANCELLED)
198 return;
199 if (ctx == CMD_CTX_FLUSH)
200 return;
c30341dc
KB		 201 if (ctx == CMD_CTX_ABORT) {
202 ++dev->abort_limit;
203 return;
204 }
c2f5b650 205 if (ctx == CMD_CTX_COMPLETED) {
5c1281a3 206 dev_warn(&dev->pci_dev->dev,
c2f5b650
MW		 207 "completed id %d twice on queue %d\n",
208 cqe->command_id, le16_to_cpup(&cqe->sq_id));
209 return;
210 }
211 if (ctx == CMD_CTX_INVALID) {
5c1281a3 212 dev_warn(&dev->pci_dev->dev,
c2f5b650
MW		 213 "invalid id %d completed on queue %d\n",
214 cqe->command_id, le16_to_cpup(&cqe->sq_id));
215 return;
216 }
217
5c1281a3 218 dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 219}
220
4d115420
KB		 221static void async_completion(struct nvme_dev *dev, void *ctx,
222 struct nvme_completion *cqe)
223{
224 struct async_cmd_info *cmdinfo = ctx;
225 cmdinfo->result = le32_to_cpup(&cqe->result);
226 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
227 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
228}
229
184d2944
MW		 230/*
231 * Called with local interrupts disabled and the q_lock held. May not sleep.
232 */
c2f5b650
MW		 233static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
234 nvme_completion_fn *fn)
b60503ba 235{
c2f5b650 236 void *ctx;
e85248e5 237 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 238
c2f5b650
MW		 239 if (cmdid >= nvmeq->q_depth) {
240 *fn = special_completion;
48e3d398 241 return CMD_CTX_INVALID;
c2f5b650 242 }
859361a2
KB		 243 if (fn)
244 *fn = info[cmdid].fn;
c2f5b650
MW		 245 ctx = info[cmdid].ctx;
246 info[cmdid].fn = special_completion;
e85248e5 247 info[cmdid].ctx = CMD_CTX_COMPLETED;
b60503ba
MW		 248 clear_bit(cmdid, nvmeq->cmdid_data);
249 wake_up(&nvmeq->sq_full);
c2f5b650 250 return ctx;
b60503ba
MW		 251}
252
c2f5b650
MW		 253static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
254 nvme_completion_fn *fn)
3c0cf138 255{
c2f5b650 256 void *ctx;
e85248e5 257 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
c2f5b650
MW		 258 if (fn)
259 *fn = info[cmdid].fn;
260 ctx = info[cmdid].ctx;
261 info[cmdid].fn = special_completion;
e85248e5 262 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 263 return ctx;
3c0cf138
MW		 264}
265
5a92e700 266static struct nvme_queue *raw_nvmeq(struct nvme_dev *dev, int qid)
b60503ba 267{
5a92e700 268 return rcu_dereference_raw(dev->queues[qid]);
b60503ba
MW		 269}
270
5a92e700
KB		 271struct nvme_queue *get_nvmeq(struct nvme_dev *dev) __acquires(RCU)
272{
273 rcu_read_lock();
274 return rcu_dereference(dev->queues[get_cpu() + 1]);
275}
276
277void put_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
b60503ba 278{
1b23484b 279 put_cpu();
5a92e700 280 rcu_read_unlock();
b60503ba
MW		 281}
282
283/**
714a7a22 284 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 285 * @nvmeq: The queue to use
286 * @cmd: The command to send
287 *
288 * Safe to use from interrupt context
289 */
290static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
291{
292 unsigned long flags;
293 u16 tail;
b60503ba
MW		 294 spin_lock_irqsave(&nvmeq->q_lock, flags);
295 tail = nvmeq->sq_tail;
296 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 297 if (++tail == nvmeq->q_depth)
298 tail = 0;
7547881d 299 writel(tail, nvmeq->q_db);
b60503ba
MW		 300 nvmeq->sq_tail = tail;
301 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
302
303 return 0;
304}
305
eca18b23 306static __le64 **iod_list(struct nvme_iod *iod)
e025344c 307{
eca18b23 308 return ((void *)iod) + iod->offset;
e025344c
SMM		 309}
310
eca18b23
MW		 311/*
312 * Will slightly overestimate the number of pages needed. This is OK
313 * as it only leads to a small amount of wasted memory for the lifetime of
314 * the I/O.
315 */
316static int nvme_npages(unsigned size)
317{
318 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
319 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
320}
b60503ba 321
eca18b23
MW		 322static struct nvme_iod *
323nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
b60503ba 324{
eca18b23
MW		 325 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
326 sizeof(__le64 *) * nvme_npages(nbytes) +
327 sizeof(struct scatterlist) * nseg, gfp);
328
329 if (iod) {
330 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
331 iod->npages = -1;
332 iod->length = nbytes;
2b196034 333 iod->nents = 0;
6198221f 334 iod->start_time = jiffies;
eca18b23
MW		 335 }
336
337 return iod;
b60503ba
MW		 338}
339
5d0f6131 340void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 341{
eca18b23
MW		 342 const int last_prp = PAGE_SIZE / 8 - 1;
343 int i;
344 __le64 **list = iod_list(iod);
345 dma_addr_t prp_dma = iod->first_dma;
346
347 if (iod->npages == 0)
348 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
349 for (i = 0; i < iod->npages; i++) {
350 __le64 *prp_list = list[i];
351 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
352 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
353 prp_dma = next_prp_dma;
354 }
355 kfree(iod);
b60503ba
MW		 356}
357
6198221f
KB		 358static void nvme_start_io_acct(struct bio *bio)
359{
360 struct gendisk *disk = bio->bi_bdev->bd_disk;
361 const int rw = bio_data_dir(bio);
362 int cpu = part_stat_lock();
363 part_round_stats(cpu, &disk->part0);
364 part_stat_inc(cpu, &disk->part0, ios[rw]);
365 part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio));
366 part_inc_in_flight(&disk->part0, rw);
367 part_stat_unlock();
368}
369
370static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
371{
372 struct gendisk *disk = bio->bi_bdev->bd_disk;
373 const int rw = bio_data_dir(bio);
374 unsigned long duration = jiffies - start_time;
375 int cpu = part_stat_lock();
376 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
377 part_round_stats(cpu, &disk->part0);
378 part_dec_in_flight(&disk->part0, rw);
379 part_stat_unlock();
380}
381
5c1281a3 382static void bio_completion(struct nvme_dev *dev, void *ctx,
b60503ba
MW		 383 struct nvme_completion *cqe)
384{
eca18b23
MW		 385 struct nvme_iod *iod = ctx;
386 struct bio *bio = iod->private;
b60503ba
MW		 387 u16 status = le16_to_cpup(&cqe->status) >> 1;
388
9e59d091 389 if (iod->nents) {
2b196034 390 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
b60503ba 391 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9e59d091
KB		 392 nvme_end_io_acct(bio, iod->start_time);
393 }
eca18b23 394 nvme_free_iod(dev, iod);
427e9708 395 if (status)
1ad2f893 396 bio_endio(bio, -EIO);
427e9708 397 else
1ad2f893 398 bio_endio(bio, 0);
b60503ba
MW		 399}
400
184d2944 401/* length is in bytes. gfp flags indicates whether we may sleep. */
5d0f6131
VV		 402int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd,
403 struct nvme_iod *iod, int total_len, gfp_t gfp)
ff22b54f 404{
99802a7a 405 struct dma_pool *pool;
eca18b23
MW		 406 int length = total_len;
407 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 408 int dma_len = sg_dma_len(sg);
409 u64 dma_addr = sg_dma_address(sg);
410 int offset = offset_in_page(dma_addr);
e025344c 411 __le64 *prp_list;
eca18b23 412 __le64 **list = iod_list(iod);
e025344c 413 dma_addr_t prp_dma;
eca18b23 414 int nprps, i;
ff22b54f
MW		 415
416 cmd->prp1 = cpu_to_le64(dma_addr);
417 length -= (PAGE_SIZE - offset);
418 if (length <= 0)
eca18b23 419 return total_len;
ff22b54f
MW		 420
421 dma_len -= (PAGE_SIZE - offset);
422 if (dma_len) {
423 dma_addr += (PAGE_SIZE - offset);
424 } else {
425 sg = sg_next(sg);
426 dma_addr = sg_dma_address(sg);
427 dma_len = sg_dma_len(sg);
428 }
429
430 if (length <= PAGE_SIZE) {
431 cmd->prp2 = cpu_to_le64(dma_addr);
eca18b23 432 return total_len;
e025344c
SMM		 433 }
434
435 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
99802a7a
MW		 436 if (nprps <= (256 / 8)) {
437 pool = dev->prp_small_pool;
eca18b23 438 iod->npages = 0;
99802a7a
MW		 439 } else {
440 pool = dev->prp_page_pool;
eca18b23 441 iod->npages = 1;
99802a7a
MW		 442 }
443
b77954cb
MW		 444 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
445 if (!prp_list) {
446 cmd->prp2 = cpu_to_le64(dma_addr);
eca18b23
MW		 447 iod->npages = -1;
448 return (total_len - length) + PAGE_SIZE;
b77954cb 449 }
eca18b23
MW		 450 list[0] = prp_list;
451 iod->first_dma = prp_dma;
e025344c
SMM		 452 cmd->prp2 = cpu_to_le64(prp_dma);
453 i = 0;
454 for (;;) {
7523d834 455 if (i == PAGE_SIZE / 8) {
e025344c 456 __le64 *old_prp_list = prp_list;
b77954cb 457 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 458 if (!prp_list)
459 return total_len - length;
460 list[iod->npages++] = prp_list;
7523d834
MW		 461 prp_list[0] = old_prp_list[i - 1];
462 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
463 i = 1;
e025344c
SMM		 464 }
465 prp_list[i++] = cpu_to_le64(dma_addr);
466 dma_len -= PAGE_SIZE;
467 dma_addr += PAGE_SIZE;
468 length -= PAGE_SIZE;
469 if (length <= 0)
470 break;
471 if (dma_len > 0)
472 continue;
473 BUG_ON(dma_len < 0);
474 sg = sg_next(sg);
475 dma_addr = sg_dma_address(sg);
476 dma_len = sg_dma_len(sg);
ff22b54f
MW		 477 }
478
eca18b23 479 return total_len;
ff22b54f
MW		 480}
481
427e9708 482static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
20d0189b 483 int len)
427e9708 484{
20d0189b
KO		 485 struct bio *split = bio_split(bio, len >> 9, GFP_ATOMIC, NULL);
486 if (!split)
427e9708
KB		 487 return -ENOMEM;
488
20d0189b
KO		 489 bio_chain(split, bio);
490
427e9708
KB		 491 if (bio_list_empty(&nvmeq->sq_cong))
492 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
20d0189b
KO		 493 bio_list_add(&nvmeq->sq_cong, split);
494 bio_list_add(&nvmeq->sq_cong, bio);
427e9708
KB		 495
496 return 0;
497}
498
1ad2f893
MW		 499/* NVMe scatterlists require no holes in the virtual address */
500#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
501 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
502
427e9708 503static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
b60503ba
MW		 504 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
505{
7988613b
KO		 506 struct bio_vec bvec, bvprv;
507 struct bvec_iter iter;
76830840 508 struct scatterlist *sg = NULL;
7988613b
KO		 509 int length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size;
510 int first = 1;
159b67d7
KB		 511
512 if (nvmeq->dev->stripe_size)
513 split_len = nvmeq->dev->stripe_size -
4f024f37
KO		 514 ((bio->bi_iter.bi_sector << 9) &
515 (nvmeq->dev->stripe_size - 1));
b60503ba 516
eca18b23 517 sg_init_table(iod->sg, psegs);
7988613b
KO		 518 bio_for_each_segment(bvec, bio, iter) {
519 if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) {
520 sg->length += bvec.bv_len;
76830840 521 } else {
7988613b
KO		 522 if (!first && BIOVEC_NOT_VIRT_MERGEABLE(&bvprv, &bvec))
523 return nvme_split_and_submit(bio, nvmeq,
20d0189b 524 length);
427e9708 525
eca18b23 526 sg = sg ? sg + 1 : iod->sg;
7988613b
KO		 527 sg_set_page(sg, bvec.bv_page,
528 bvec.bv_len, bvec.bv_offset);
76830840
MW		 529 nsegs++;
530 }
159b67d7 531
7988613b 532 if (split_len - length < bvec.bv_len)
20d0189b 533 return nvme_split_and_submit(bio, nvmeq, split_len);
7988613b 534 length += bvec.bv_len;
76830840 535 bvprv = bvec;
7988613b 536 first = 0;
b60503ba 537 }
eca18b23 538 iod->nents = nsegs;
76830840 539 sg_mark_end(sg);
427e9708 540 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
1ad2f893 541 return -ENOMEM;
427e9708 542
4f024f37 543 BUG_ON(length != bio->bi_iter.bi_size);
1ad2f893 544 return length;
b60503ba
MW		 545}
546
0e5e4f0e
KB		 547/*
548 * We reuse the small pool to allocate the 16-byte range here as it is not
549 * worth having a special pool for these or additional cases to handle freeing
550 * the iod.
551 */
552static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
553 struct bio *bio, struct nvme_iod *iod, int cmdid)
554{
555 struct nvme_dsm_range *range;
556 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
557
558 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
559 &iod->first_dma);
560 if (!range)
561 return -ENOMEM;
562
563 iod_list(iod)[0] = (__le64 *)range;
564 iod->npages = 0;
565
566 range->cattr = cpu_to_le32(0);
4f024f37
KO		 567 range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift);
568 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
0e5e4f0e
KB		 569
570 memset(cmnd, 0, sizeof(*cmnd));
571 cmnd->dsm.opcode = nvme_cmd_dsm;
572 cmnd->dsm.command_id = cmdid;
573 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
574 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
575 cmnd->dsm.nr = 0;
576 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
577
578 if (++nvmeq->sq_tail == nvmeq->q_depth)
579 nvmeq->sq_tail = 0;
580 writel(nvmeq->sq_tail, nvmeq->q_db);
581
582 return 0;
583}
584
00df5cb4
MW		 585static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
586 int cmdid)
587{
588 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
589
590 memset(cmnd, 0, sizeof(*cmnd));
591 cmnd->common.opcode = nvme_cmd_flush;
592 cmnd->common.command_id = cmdid;
593 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
594
595 if (++nvmeq->sq_tail == nvmeq->q_depth)
596 nvmeq->sq_tail = 0;
597 writel(nvmeq->sq_tail, nvmeq->q_db);
598
599 return 0;
600}
601
5d0f6131 602int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
00df5cb4
MW		 603{
604 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
ff976d72 605 special_completion, NVME_IO_TIMEOUT);
00df5cb4
MW		 606 if (unlikely(cmdid < 0))
607 return cmdid;
608
609 return nvme_submit_flush(nvmeq, ns, cmdid);
610}
611
184d2944
MW		 612/*
613 * Called with local interrupts disabled and the q_lock held. May not sleep.
614 */
b60503ba
MW		 615static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
616 struct bio *bio)
617{
ff22b54f 618 struct nvme_command *cmnd;
eca18b23 619 struct nvme_iod *iod;
b60503ba 620 enum dma_data_direction dma_dir;
1287dabd 621 int cmdid, length, result;
b60503ba
MW		 622 u16 control;
623 u32 dsmgmt;
b60503ba
MW		 624 int psegs = bio_phys_segments(ns->queue, bio);
625
00df5cb4
MW		 626 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
627 result = nvme_submit_flush_data(nvmeq, ns);
628 if (result)
629 return result;
630 }
631
1287dabd 632 result = -ENOMEM;
4f024f37 633 iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, GFP_ATOMIC);
eca18b23 634 if (!iod)
eeee3226 635 goto nomem;
eca18b23 636 iod->private = bio;
b60503ba 637
eeee3226 638 result = -EBUSY;
ff976d72 639 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 640 if (unlikely(cmdid < 0))
eca18b23 641 goto free_iod;
b60503ba 642
0e5e4f0e
KB		 643 if (bio->bi_rw & REQ_DISCARD) {
644 result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
645 if (result)
646 goto free_cmdid;
647 return result;
648 }
00df5cb4
MW		 649 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
650 return nvme_submit_flush(nvmeq, ns, cmdid);
651
b60503ba
MW		 652 control = 0;
653 if (bio->bi_rw & REQ_FUA)
654 control |= NVME_RW_FUA;
655 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
656 control |= NVME_RW_LR;
657
658 dsmgmt = 0;
659 if (bio->bi_rw & REQ_RAHEAD)
660 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
661
ff22b54f 662 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b60503ba 663
b8deb62c 664 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 665 if (bio_data_dir(bio)) {
ff22b54f 666 cmnd->rw.opcode = nvme_cmd_write;
b60503ba
MW		 667 dma_dir = DMA_TO_DEVICE;
668 } else {
ff22b54f 669 cmnd->rw.opcode = nvme_cmd_read;
b60503ba
MW		 670 dma_dir = DMA_FROM_DEVICE;
671 }
672
427e9708
KB		 673 result = nvme_map_bio(nvmeq, iod, bio, dma_dir, psegs);
674 if (result <= 0)
859361a2 675 goto free_cmdid;
1ad2f893 676 length = result;
b60503ba 677
ff22b54f
MW		 678 cmnd->rw.command_id = cmdid;
679 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
eca18b23
MW		 680 length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
681 GFP_ATOMIC);
4f024f37 682 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
1ad2f893 683 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
ff22b54f
MW		 684 cmnd->rw.control = cpu_to_le16(control);
685 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 686
6198221f 687 nvme_start_io_acct(bio);
b60503ba
MW		 688 if (++nvmeq->sq_tail == nvmeq->q_depth)
689 nvmeq->sq_tail = 0;
7547881d 690 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 691
1974b1ae
MW		 692 return 0;
693
859361a2
KB		 694 free_cmdid:
695 free_cmdid(nvmeq, cmdid, NULL);
eca18b23
MW		 696 free_iod:
697 nvme_free_iod(nvmeq->dev, iod);
eeee3226
MW		 698 nomem:
699 return result;
b60503ba
MW		 700}
701
e9539f47 702static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 703{
82123460 704 u16 head, phase;
b60503ba 705
b60503ba 706 head = nvmeq->cq_head;
82123460 707 phase = nvmeq->cq_phase;
b60503ba
MW		 708
709 for (;;) {
c2f5b650
MW		 710 void *ctx;
711 nvme_completion_fn fn;
b60503ba 712 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 713 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 714 break;
715 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
716 if (++head == nvmeq->q_depth) {
717 head = 0;
82123460 718 phase = !phase;
b60503ba
MW		 719 }
720
c2f5b650 721 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
5c1281a3 722 fn(nvmeq->dev, ctx, &cqe);
b60503ba
MW		 723 }
724
725 /* If the controller ignores the cq head doorbell and continuously
726 * writes to the queue, it is theoretically possible to wrap around
727 * the queue twice and mistakenly return IRQ_NONE. Linux only
728 * requires that 0.1% of your interrupts are handled, so this isn't
729 * a big problem.
730 */
82123460 731 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 732 return 0;
b60503ba 733
b80d5ccc 734 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 735 nvmeq->cq_head = head;
82123460 736 nvmeq->cq_phase = phase;
b60503ba 737
e9539f47
MW		 738 nvmeq->cqe_seen = 1;
739 return 1;
b60503ba
MW		 740}
741
7d822457
MW		 742static void nvme_make_request(struct request_queue *q, struct bio *bio)
743{
744 struct nvme_ns *ns = q->queuedata;
745 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
746 int result = -EBUSY;
747
cd638946
KB		 748 if (!nvmeq) {
749 put_nvmeq(NULL);
750 bio_endio(bio, -EIO);
751 return;
752 }
753
7d822457 754 spin_lock_irq(&nvmeq->q_lock);
22404274 755 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
7d822457
MW		 756 result = nvme_submit_bio_queue(nvmeq, ns, bio);
757 if (unlikely(result)) {
758 if (bio_list_empty(&nvmeq->sq_cong))
759 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
760 bio_list_add(&nvmeq->sq_cong, bio);
761 }
762
763 nvme_process_cq(nvmeq);
764 spin_unlock_irq(&nvmeq->q_lock);
765 put_nvmeq(nvmeq);
766}
767
b60503ba 768static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 769{
770 irqreturn_t result;
771 struct nvme_queue *nvmeq = data;
772 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 773 nvme_process_cq(nvmeq);
774 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
775 nvmeq->cqe_seen = 0;
58ffacb5
MW		 776 spin_unlock(&nvmeq->q_lock);
777 return result;
778}
779
780static irqreturn_t nvme_irq_check(int irq, void *data)
781{
782 struct nvme_queue *nvmeq = data;
783 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
784 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
785 return IRQ_NONE;
786 return IRQ_WAKE_THREAD;
787}
788
3c0cf138
MW		 789static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
790{
791 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 792 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW		 793 spin_unlock_irq(&nvmeq->q_lock);
794}
795
c2f5b650
MW		 796struct sync_cmd_info {
797 struct task_struct *task;
798 u32 result;
799 int status;
800};
801
5c1281a3 802static void sync_completion(struct nvme_dev *dev, void *ctx,
c2f5b650
MW		 803 struct nvme_completion *cqe)
804{
805 struct sync_cmd_info *cmdinfo = ctx;
806 cmdinfo->result = le32_to_cpup(&cqe->result);
807 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
808 wake_up_process(cmdinfo->task);
809}
810
b60503ba
MW		 811/*
812 * Returns 0 on success. If the result is negative, it's a Linux error code;
813 * if the result is positive, it's an NVM Express status code
814 */
5d0f6131
VV		 815int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
816 u32 *result, unsigned timeout)
b60503ba
MW		 817{
818 int cmdid;
819 struct sync_cmd_info cmdinfo;
820
821 cmdinfo.task = current;
822 cmdinfo.status = -EINTR;
823
c2f5b650 824 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion,
e85248e5 825 timeout);
b60503ba
MW		 826 if (cmdid < 0)
827 return cmdid;
828 cmd->common.command_id = cmdid;
829
3c0cf138
MW		 830 set_current_state(TASK_KILLABLE);
831 nvme_submit_cmd(nvmeq, cmd);
78f8d257 832 schedule_timeout(timeout);
b60503ba 833
3c0cf138
MW		 834 if (cmdinfo.status == -EINTR) {
835 nvme_abort_command(nvmeq, cmdid);
836 return -EINTR;
837 }
838
b60503ba
MW		 839 if (result)
840 *result = cmdinfo.result;
841
842 return cmdinfo.status;
843}
844
4d115420
KB		 845static int nvme_submit_async_cmd(struct nvme_queue *nvmeq,
846 struct nvme_command *cmd,
847 struct async_cmd_info *cmdinfo, unsigned timeout)
848{
849 int cmdid;
850
851 cmdid = alloc_cmdid_killable(nvmeq, cmdinfo, async_completion, timeout);
852 if (cmdid < 0)
853 return cmdid;
854 cmdinfo->status = -EINTR;
855 cmd->common.command_id = cmdid;
856 nvme_submit_cmd(nvmeq, cmd);
857 return 0;
858}
859
5d0f6131 860int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
b60503ba
MW		 861 u32 *result)
862{
5a92e700
KB		 863 return nvme_submit_sync_cmd(raw_nvmeq(dev, 0), cmd, result,
864 ADMIN_TIMEOUT);
b60503ba
MW		 865}
866
4d115420
KB		 867static int nvme_submit_admin_cmd_async(struct nvme_dev *dev,
868 struct nvme_command *cmd, struct async_cmd_info *cmdinfo)
869{
5a92e700 870 return nvme_submit_async_cmd(raw_nvmeq(dev, 0), cmd, cmdinfo,
4d115420
KB		 871 ADMIN_TIMEOUT);
872}
873
b60503ba
MW		 874static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
875{
876 int status;
877 struct nvme_command c;
878
879 memset(&c, 0, sizeof(c));
880 c.delete_queue.opcode = opcode;
881 c.delete_queue.qid = cpu_to_le16(id);
882
883 status = nvme_submit_admin_cmd(dev, &c, NULL);
884 if (status)
885 return -EIO;
886 return 0;
887}
888
889static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
890 struct nvme_queue *nvmeq)
891{
892 int status;
893 struct nvme_command c;
894 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
895
896 memset(&c, 0, sizeof(c));
897 c.create_cq.opcode = nvme_admin_create_cq;
898 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
899 c.create_cq.cqid = cpu_to_le16(qid);
900 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
901 c.create_cq.cq_flags = cpu_to_le16(flags);
902 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
903
904 status = nvme_submit_admin_cmd(dev, &c, NULL);
905 if (status)
906 return -EIO;
907 return 0;
908}
909
910static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
911 struct nvme_queue *nvmeq)
912{
913 int status;
914 struct nvme_command c;
915 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
916
917 memset(&c, 0, sizeof(c));
918 c.create_sq.opcode = nvme_admin_create_sq;
919 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
920 c.create_sq.sqid = cpu_to_le16(qid);
921 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
922 c.create_sq.sq_flags = cpu_to_le16(flags);
923 c.create_sq.cqid = cpu_to_le16(qid);
924
925 status = nvme_submit_admin_cmd(dev, &c, NULL);
926 if (status)
927 return -EIO;
928 return 0;
929}
930
931static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
932{
933 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
934}
935
936static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
937{
938 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
939}
940
5d0f6131 941int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 942 dma_addr_t dma_addr)
943{
944 struct nvme_command c;
945
946 memset(&c, 0, sizeof(c));
947 c.identify.opcode = nvme_admin_identify;
948 c.identify.nsid = cpu_to_le32(nsid);
949 c.identify.prp1 = cpu_to_le64(dma_addr);
950 c.identify.cns = cpu_to_le32(cns);
951
952 return nvme_submit_admin_cmd(dev, &c, NULL);
953}
954
5d0f6131 955int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 956 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 957{
958 struct nvme_command c;
959
960 memset(&c, 0, sizeof(c));
961 c.features.opcode = nvme_admin_get_features;
a42cecce 962 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 963 c.features.prp1 = cpu_to_le64(dma_addr);
964 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 965
08df1e05 966 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 967}
968
5d0f6131
VV		 969int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
970 dma_addr_t dma_addr, u32 *result)
df348139
MW		 971{
972 struct nvme_command c;
973
974 memset(&c, 0, sizeof(c));
975 c.features.opcode = nvme_admin_set_features;
976 c.features.prp1 = cpu_to_le64(dma_addr);
977 c.features.fid = cpu_to_le32(fid);
978 c.features.dword11 = cpu_to_le32(dword11);
979
bc5fc7e4
MW		 980 return nvme_submit_admin_cmd(dev, &c, result);
981}
982
c30341dc
KB		 983/**
984 * nvme_abort_cmd - Attempt aborting a command
985 * @cmdid: Command id of a timed out IO
986 * @queue: The queue with timed out IO
987 *
988 * Schedule controller reset if the command was already aborted once before and
989 * still hasn't been returned to the driver, or if this is the admin queue.
990 */
991static void nvme_abort_cmd(int cmdid, struct nvme_queue *nvmeq)
992{
993 int a_cmdid;
994 struct nvme_command cmd;
995 struct nvme_dev *dev = nvmeq->dev;
996 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
5a92e700 997 struct nvme_queue *adminq;
c30341dc
KB		 998
999 if (!nvmeq->qid || info[cmdid].aborted) {
1000 if (work_busy(&dev->reset_work))
1001 return;
1002 list_del_init(&dev->node);
1003 dev_warn(&dev->pci_dev->dev,
1004 "I/O %d QID %d timeout, reset controller\n", cmdid,
1005 nvmeq->qid);
bdfd70fd 1006 PREPARE_WORK(&dev->reset_work, nvme_reset_failed_dev);
c30341dc
KB		 1007 queue_work(nvme_workq, &dev->reset_work);
1008 return;
1009 }
1010
1011 if (!dev->abort_limit)
1012 return;
1013
5a92e700
KB		 1014 adminq = rcu_dereference(dev->queues[0]);
1015 a_cmdid = alloc_cmdid(adminq, CMD_CTX_ABORT, special_completion,
c30341dc
KB		 1016 ADMIN_TIMEOUT);
1017 if (a_cmdid < 0)
1018 return;
1019
1020 memset(&cmd, 0, sizeof(cmd));
1021 cmd.abort.opcode = nvme_admin_abort_cmd;
1022 cmd.abort.cid = cmdid;
1023 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1024 cmd.abort.command_id = a_cmdid;
1025
1026 --dev->abort_limit;
1027 info[cmdid].aborted = 1;
1028 info[cmdid].timeout = jiffies + ADMIN_TIMEOUT;
1029
1030 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", cmdid,
1031 nvmeq->qid);
5a92e700 1032 nvme_submit_cmd(adminq, &cmd);
c30341dc
KB		 1033}
1034
a09115b2
MW		 1035/**
1036 * nvme_cancel_ios - Cancel outstanding I/Os
1037 * @queue: The queue to cancel I/Os on
1038 * @timeout: True to only cancel I/Os which have timed out
1039 */
1040static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1041{
1042 int depth = nvmeq->q_depth - 1;
1043 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1044 unsigned long now = jiffies;
1045 int cmdid;
1046
1047 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1048 void *ctx;
1049 nvme_completion_fn fn;
1050 static struct nvme_completion cqe = {
af2d9ca7 1051 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
a09115b2
MW		 1052 };
1053
1054 if (timeout && !time_after(now, info[cmdid].timeout))
1055 continue;
053ab702
KB		 1056 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1057 continue;
c30341dc
KB		 1058 if (timeout && nvmeq->dev->initialized) {
1059 nvme_abort_cmd(cmdid, nvmeq);
1060 continue;
1061 }
1062 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", cmdid,
1063 nvmeq->qid);
a09115b2
MW		 1064 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
1065 fn(nvmeq->dev, ctx, &cqe);
1066 }
1067}
1068
5a92e700 1069static void nvme_free_queue(struct rcu_head *r)
9e866774 1070{
5a92e700
KB		 1071 struct nvme_queue *nvmeq = container_of(r, struct nvme_queue, r_head);
1072
22404274
KB		 1073 spin_lock_irq(&nvmeq->q_lock);
1074 while (bio_list_peek(&nvmeq->sq_cong)) {
1075 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1076 bio_endio(bio, -EIO);
1077 }
1078 spin_unlock_irq(&nvmeq->q_lock);
1079
9e866774
MW		 1080 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1081 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1082 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1083 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1084 kfree(nvmeq);
1085}
1086
a1a5ef99 1087static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1088{
1089 int i;
1090
5a92e700
KB		 1091 for (i = num_possible_cpus(); i > dev->queue_count - 1; i--)
1092 rcu_assign_pointer(dev->queues[i], NULL);
a1a5ef99 1093 for (i = dev->queue_count - 1; i >= lowest; i--) {
5a92e700
KB		 1094 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
1095 rcu_assign_pointer(dev->queues[i], NULL);
1096 call_rcu(&nvmeq->r_head, nvme_free_queue);
22404274 1097 dev->queue_count--;
22404274
KB		 1098 }
1099}
1100
4d115420
KB		 1101/**
1102 * nvme_suspend_queue - put queue into suspended state
1103 * @nvmeq - queue to suspend
1104 *
1105 * Returns 1 if already suspended, 0 otherwise.
1106 */
1107static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1108{
4d115420 1109 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1110
a09115b2 1111 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1112 if (nvmeq->q_suspended) {
1113 spin_unlock_irq(&nvmeq->q_lock);
4d115420 1114 return 1;
3295874b 1115 }
22404274 1116 nvmeq->q_suspended = 1;
a09115b2
MW		 1117 spin_unlock_irq(&nvmeq->q_lock);
1118
aba2080f
MW		 1119 irq_set_affinity_hint(vector, NULL);
1120 free_irq(vector, nvmeq);
b60503ba 1121
4d115420
KB		 1122 return 0;
1123}
b60503ba 1124
4d115420
KB		 1125static void nvme_clear_queue(struct nvme_queue *nvmeq)
1126{
22404274
KB		 1127 spin_lock_irq(&nvmeq->q_lock);
1128 nvme_process_cq(nvmeq);
1129 nvme_cancel_ios(nvmeq, false);
1130 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1131}
1132
4d115420
KB		 1133static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1134{
5a92e700 1135 struct nvme_queue *nvmeq = raw_nvmeq(dev, qid);
4d115420
KB		 1136
1137 if (!nvmeq)
1138 return;
1139 if (nvme_suspend_queue(nvmeq))
1140 return;
1141
0e53d180
KB		 1142 /* Don't tell the adapter to delete the admin queue.
1143 * Don't tell a removed adapter to delete IO queues. */
1144 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1145 adapter_delete_sq(dev, qid);
1146 adapter_delete_cq(dev, qid);
1147 }
4d115420 1148 nvme_clear_queue(nvmeq);
b60503ba
MW		 1149}
1150
1151static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1152 int depth, int vector)
1153{
1154 struct device *dmadev = &dev->pci_dev->dev;
22404274 1155 unsigned extra = nvme_queue_extra(depth);
b60503ba
MW		 1156 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1157 if (!nvmeq)
1158 return NULL;
1159
1160 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1161 &nvmeq->cq_dma_addr, GFP_KERNEL);
1162 if (!nvmeq->cqes)
1163 goto free_nvmeq;
1164 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1165
1166 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1167 &nvmeq->sq_dma_addr, GFP_KERNEL);
1168 if (!nvmeq->sq_cmds)
1169 goto free_cqdma;
1170
1171 nvmeq->q_dmadev = dmadev;
091b6092 1172 nvmeq->dev = dev;
3193f07b
MW		 1173 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1174 dev->instance, qid);
b60503ba
MW		 1175 spin_lock_init(&nvmeq->q_lock);
1176 nvmeq->cq_head = 0;
82123460 1177 nvmeq->cq_phase = 1;
b60503ba 1178 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1179 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1180 bio_list_init(&nvmeq->sq_cong);
b80d5ccc 1181 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW		 1182 nvmeq->q_depth = depth;
1183 nvmeq->cq_vector = vector;
c30341dc 1184 nvmeq->qid = qid;
22404274
KB		 1185 nvmeq->q_suspended = 1;
1186 dev->queue_count++;
5a92e700 1187 rcu_assign_pointer(dev->queues[qid], nvmeq);
b60503ba
MW		 1188
1189 return nvmeq;
1190
1191 free_cqdma:
68b8eca5 1192 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1193 nvmeq->cq_dma_addr);
1194 free_nvmeq:
1195 kfree(nvmeq);
1196 return NULL;
1197}
1198
3001082c
MW		 1199static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1200 const char *name)
1201{
58ffacb5
MW		 1202 if (use_threaded_interrupts)
1203 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1204 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1205 name, nvmeq);
3001082c 1206 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1207 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1208}
1209
22404274 1210static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1211{
22404274
KB		 1212 struct nvme_dev *dev = nvmeq->dev;
1213 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
b60503ba 1214
22404274
KB		 1215 nvmeq->sq_tail = 0;
1216 nvmeq->cq_head = 0;
1217 nvmeq->cq_phase = 1;
b80d5ccc 1218 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274
KB		 1219 memset(nvmeq->cmdid_data, 0, extra);
1220 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1221 nvme_cancel_ios(nvmeq, false);
1222 nvmeq->q_suspended = 0;
1223}
1224
1225static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1226{
1227 struct nvme_dev *dev = nvmeq->dev;
1228 int result;
3f85d50b 1229
b60503ba
MW		 1230 result = adapter_alloc_cq(dev, qid, nvmeq);
1231 if (result < 0)
22404274 1232 return result;
b60503ba
MW		 1233
1234 result = adapter_alloc_sq(dev, qid, nvmeq);
1235 if (result < 0)
1236 goto release_cq;
1237
3193f07b 1238 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1239 if (result < 0)
1240 goto release_sq;
1241
0a8d44cb 1242 spin_lock_irq(&nvmeq->q_lock);
22404274 1243 nvme_init_queue(nvmeq, qid);
0a8d44cb 1244 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1245
1246 return result;
b60503ba
MW		 1247
1248 release_sq:
1249 adapter_delete_sq(dev, qid);
1250 release_cq:
1251 adapter_delete_cq(dev, qid);
22404274 1252 return result;
b60503ba
MW		 1253}
1254
ba47e386
MW		 1255static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1256{
1257 unsigned long timeout;
1258 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1259
1260 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1261
1262 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1263 msleep(100);
1264 if (fatal_signal_pending(current))
1265 return -EINTR;
1266 if (time_after(jiffies, timeout)) {
1267 dev_err(&dev->pci_dev->dev,
1268 "Device not ready; aborting initialisation\n");
1269 return -ENODEV;
1270 }
1271 }
1272
1273 return 0;
1274}
1275
1276/*
1277 * If the device has been passed off to us in an enabled state, just clear
1278 * the enabled bit. The spec says we should set the 'shutdown notification
1279 * bits', but doing so may cause the device to complete commands to the
1280 * admin queue ... and we don't know what memory that might be pointing at!
1281 */
1282static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1283{
44af146a
MW		 1284 u32 cc = readl(&dev->bar->cc);
1285
1286 if (cc & NVME_CC_ENABLE)
1287 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
ba47e386
MW		 1288 return nvme_wait_ready(dev, cap, false);
1289}
1290
1291static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1292{
1293 return nvme_wait_ready(dev, cap, true);
1294}
1295
1894d8f1
KB		 1296static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1297{
1298 unsigned long timeout;
1299 u32 cc;
1300
1301 cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
1302 writel(cc, &dev->bar->cc);
1303
1304 timeout = 2 * HZ + jiffies;
1305 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1306 NVME_CSTS_SHST_CMPLT) {
1307 msleep(100);
1308 if (fatal_signal_pending(current))
1309 return -EINTR;
1310 if (time_after(jiffies, timeout)) {
1311 dev_err(&dev->pci_dev->dev,
1312 "Device shutdown incomplete; abort shutdown\n");
1313 return -ENODEV;
1314 }
1315 }
1316
1317 return 0;
1318}
1319
8d85fce7 1320static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1321{
ba47e386 1322 int result;
b60503ba 1323 u32 aqa;
ba47e386 1324 u64 cap = readq(&dev->bar->cap);
b60503ba
MW		 1325 struct nvme_queue *nvmeq;
1326
ba47e386
MW		 1327 result = nvme_disable_ctrl(dev, cap);
1328 if (result < 0)
1329 return result;
b60503ba 1330
5a92e700 1331 nvmeq = raw_nvmeq(dev, 0);
cd638946
KB		 1332 if (!nvmeq) {
1333 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1334 if (!nvmeq)
1335 return -ENOMEM;
cd638946 1336 }
b60503ba
MW		 1337
1338 aqa = nvmeq->q_depth - 1;
1339 aqa |= aqa << 16;
1340
1341 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1342 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1343 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1344 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1345
1346 writel(aqa, &dev->bar->aqa);
1347 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1348 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1349 writel(dev->ctrl_config, &dev->bar->cc);
1350
ba47e386 1351 result = nvme_enable_ctrl(dev, cap);
025c557a 1352 if (result)
cd638946 1353 return result;
9e866774 1354
3193f07b 1355 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1356 if (result)
cd638946 1357 return result;
025c557a 1358
0a8d44cb 1359 spin_lock_irq(&nvmeq->q_lock);
22404274 1360 nvme_init_queue(nvmeq, 0);
0a8d44cb 1361 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1362 return result;
1363}
1364
5d0f6131 1365struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1366 unsigned long addr, unsigned length)
b60503ba 1367{
36c14ed9 1368 int i, err, count, nents, offset;
7fc3cdab
MW		 1369 struct scatterlist *sg;
1370 struct page **pages;
eca18b23 1371 struct nvme_iod *iod;
36c14ed9
MW		 1372
1373 if (addr & 3)
eca18b23 1374 return ERR_PTR(-EINVAL);
5460fc03 1375 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1376 return ERR_PTR(-EINVAL);
7fc3cdab 1377
36c14ed9 1378 offset = offset_in_page(addr);
7fc3cdab
MW		 1379 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1380 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1381 if (!pages)
1382 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1383
1384 err = get_user_pages_fast(addr, count, 1, pages);
1385 if (err < count) {
1386 count = err;
1387 err = -EFAULT;
1388 goto put_pages;
1389 }
7fc3cdab 1390
eca18b23
MW		 1391 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1392 sg = iod->sg;
36c14ed9 1393 sg_init_table(sg, count);
d0ba1e49
MW		 1394 for (i = 0; i < count; i++) {
1395 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1396 min_t(unsigned, length, PAGE_SIZE - offset),
1397 offset);
d0ba1e49
MW		 1398 length -= (PAGE_SIZE - offset);
1399 offset = 0;
7fc3cdab 1400 }
fe304c43 1401 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1402 iod->nents = count;
7fc3cdab
MW		 1403
1404 err = -ENOMEM;
1405 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1406 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1407 if (!nents)
eca18b23 1408 goto free_iod;
b60503ba 1409
7fc3cdab 1410 kfree(pages);
eca18b23 1411 return iod;
b60503ba 1412
eca18b23
MW		 1413 free_iod:
1414 kfree(iod);
7fc3cdab
MW		 1415 put_pages:
1416 for (i = 0; i < count; i++)
1417 put_page(pages[i]);
1418 kfree(pages);
eca18b23 1419 return ERR_PTR(err);
7fc3cdab 1420}
b60503ba 1421
5d0f6131 1422void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1423 struct nvme_iod *iod)
7fc3cdab 1424{
1c2ad9fa 1425 int i;
b60503ba 1426
1c2ad9fa
MW		 1427 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1428 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1429
1c2ad9fa
MW		 1430 for (i = 0; i < iod->nents; i++)
1431 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1432}
b60503ba 1433
a53295b6
MW		 1434static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1435{
1436 struct nvme_dev *dev = ns->dev;
1437 struct nvme_queue *nvmeq;
1438 struct nvme_user_io io;
1439 struct nvme_command c;
f410c680
KB		 1440 unsigned length, meta_len;
1441 int status, i;
1442 struct nvme_iod *iod, *meta_iod = NULL;
1443 dma_addr_t meta_dma_addr;
1444 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1445
1446 if (copy_from_user(&io, uio, sizeof(io)))
1447 return -EFAULT;
6c7d4945 1448 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1449 meta_len = (io.nblocks + 1) * ns->ms;
1450
1451 if (meta_len && ((io.metadata & 3) || !io.metadata))
1452 return -EINVAL;
6c7d4945
MW		 1453
1454 switch (io.opcode) {
1455 case nvme_cmd_write:
1456 case nvme_cmd_read:
6bbf1acd 1457 case nvme_cmd_compare:
eca18b23 1458 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1459 break;
6c7d4945 1460 default:
6bbf1acd 1461 return -EINVAL;
6c7d4945
MW		 1462 }
1463
eca18b23
MW		 1464 if (IS_ERR(iod))
1465 return PTR_ERR(iod);
a53295b6
MW		 1466
1467 memset(&c, 0, sizeof(c));
1468 c.rw.opcode = io.opcode;
1469 c.rw.flags = io.flags;
6c7d4945 1470 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1471 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1472 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1473 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1474 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1475 c.rw.reftag = cpu_to_le32(io.reftag);
1476 c.rw.apptag = cpu_to_le16(io.apptag);
1477 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1478
1479 if (meta_len) {
1b56749e
KB		 1480 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1481 meta_len);
f410c680
KB		 1482 if (IS_ERR(meta_iod)) {
1483 status = PTR_ERR(meta_iod);
1484 meta_iod = NULL;
1485 goto unmap;
1486 }
1487
1488 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1489 &meta_dma_addr, GFP_KERNEL);
1490 if (!meta_mem) {
1491 status = -ENOMEM;
1492 goto unmap;
1493 }
1494
1495 if (io.opcode & 1) {
1496 int meta_offset = 0;
1497
1498 for (i = 0; i < meta_iod->nents; i++) {
1499 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1500 meta_iod->sg[i].offset;
1501 memcpy(meta_mem + meta_offset, meta,
1502 meta_iod->sg[i].length);
1503 kunmap_atomic(meta);
1504 meta_offset += meta_iod->sg[i].length;
1505 }
1506 }
1507
1508 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1509 }
1510
eca18b23 1511 length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
a53295b6 1512
040a93b5 1513 nvmeq = get_nvmeq(dev);
fa922821
MW		 1514 /*
1515 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
b1ad37ef
MW		 1516 * disabled. We may be preempted at any point, and be rescheduled
1517 * to a different CPU. That will cause cacheline bouncing, but no
1518 * additional races since q_lock already protects against other CPUs.
1519 */
a53295b6 1520 put_nvmeq(nvmeq);
b77954cb
MW		 1521 if (length != (io.nblocks + 1) << ns->lba_shift)
1522 status = -ENOMEM;
22404274
KB		 1523 else if (!nvmeq || nvmeq->q_suspended)
1524 status = -EBUSY;
b77954cb 1525 else
ff976d72 1526 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
a53295b6 1527
f410c680
KB		 1528 if (meta_len) {
1529 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1530 int meta_offset = 0;
1531
1532 for (i = 0; i < meta_iod->nents; i++) {
1533 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1534 meta_iod->sg[i].offset;
1535 memcpy(meta, meta_mem + meta_offset,
1536 meta_iod->sg[i].length);
1537 kunmap_atomic(meta);
1538 meta_offset += meta_iod->sg[i].length;
1539 }
1540 }
1541
1542 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1543 meta_dma_addr);
1544 }
1545
1546 unmap:
1c2ad9fa 1547 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1548 nvme_free_iod(dev, iod);
f410c680
KB		 1549
1550 if (meta_iod) {
1551 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1552 nvme_free_iod(dev, meta_iod);
1553 }
1554
a53295b6
MW		 1555 return status;
1556}
1557
50af8bae 1558static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1559 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1560{
6bbf1acd 1561 struct nvme_admin_cmd cmd;
6ee44cdc 1562 struct nvme_command c;
eca18b23 1563 int status, length;
c7d36ab8 1564 struct nvme_iod *uninitialized_var(iod);
94f370ca 1565 unsigned timeout;
6ee44cdc 1566
6bbf1acd
MW		 1567 if (!capable(CAP_SYS_ADMIN))
1568 return -EACCES;
1569 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1570 return -EFAULT;
6ee44cdc
MW		 1571
1572 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1573 c.common.opcode = cmd.opcode;
1574 c.common.flags = cmd.flags;
1575 c.common.nsid = cpu_to_le32(cmd.nsid);
1576 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1577 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1578 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1579 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1580 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1581 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1582 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1583 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1584
1585 length = cmd.data_len;
1586 if (cmd.data_len) {
49742188
MW		 1587 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1588 length);
eca18b23
MW		 1589 if (IS_ERR(iod))
1590 return PTR_ERR(iod);
1591 length = nvme_setup_prps(dev, &c.common, iod, length,
1592 GFP_KERNEL);
6bbf1acd
MW		 1593 }
1594
94f370ca
KB		 1595 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1596 ADMIN_TIMEOUT;
6bbf1acd 1597 if (length != cmd.data_len)
b77954cb
MW		 1598 status = -ENOMEM;
1599 else
5a92e700
KB		 1600 status = nvme_submit_sync_cmd(raw_nvmeq(dev, 0), &c,
1601 &cmd.result, timeout);
eca18b23 1602
6bbf1acd 1603 if (cmd.data_len) {
1c2ad9fa 1604 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1605 nvme_free_iod(dev, iod);
6bbf1acd 1606 }
f4f117f6 1607
cf90bc48 1608 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1609 sizeof(cmd.result)))
1610 status = -EFAULT;
1611
6ee44cdc
MW		 1612 return status;
1613}
1614
b60503ba
MW		 1615static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1616 unsigned long arg)
1617{
1618 struct nvme_ns *ns = bdev->bd_disk->private_data;
1619
1620 switch (cmd) {
6bbf1acd 1621 case NVME_IOCTL_ID:
c3bfe717 1622 force_successful_syscall_return();
6bbf1acd
MW		 1623 return ns->ns_id;
1624 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1625 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW		 1626 case NVME_IOCTL_SUBMIT_IO:
1627 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1628 case SG_GET_VERSION_NUM:
1629 return nvme_sg_get_version_num((void __user *)arg);
1630 case SG_IO:
1631 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1632 default:
1633 return -ENOTTY;
1634 }
1635}
1636
320a3827
KB		 1637#ifdef CONFIG_COMPAT
1638static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1639 unsigned int cmd, unsigned long arg)
1640{
1641 struct nvme_ns *ns = bdev->bd_disk->private_data;
1642
1643 switch (cmd) {
1644 case SG_IO:
1645 return nvme_sg_io32(ns, arg);
1646 }
1647 return nvme_ioctl(bdev, mode, cmd, arg);
1648}
1649#else
1650#define nvme_compat_ioctl NULL
1651#endif
1652
9ac27090
KB		 1653static int nvme_open(struct block_device *bdev, fmode_t mode)
1654{
1655 struct nvme_ns *ns = bdev->bd_disk->private_data;
1656 struct nvme_dev *dev = ns->dev;
1657
1658 kref_get(&dev->kref);
1659 return 0;
1660}
1661
1662static void nvme_free_dev(struct kref *kref);
1663
1664static void nvme_release(struct gendisk *disk, fmode_t mode)
1665{
1666 struct nvme_ns *ns = disk->private_data;
1667 struct nvme_dev *dev = ns->dev;
1668
1669 kref_put(&dev->kref, nvme_free_dev);
1670}
1671
b60503ba
MW		 1672static const struct block_device_operations nvme_fops = {
1673 .owner = THIS_MODULE,
1674 .ioctl = nvme_ioctl,
320a3827 1675 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1676 .open = nvme_open,
1677 .release = nvme_release,
b60503ba
MW		 1678};
1679
1fa6aead
MW		 1680static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1681{
1682 while (bio_list_peek(&nvmeq->sq_cong)) {
1683 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1684 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
427e9708
KB		 1685
1686 if (bio_list_empty(&nvmeq->sq_cong))
1687 remove_wait_queue(&nvmeq->sq_full,
1688 &nvmeq->sq_cong_wait);
1fa6aead 1689 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
427e9708
KB		 1690 if (bio_list_empty(&nvmeq->sq_cong))
1691 add_wait_queue(&nvmeq->sq_full,
1692 &nvmeq->sq_cong_wait);
1fa6aead
MW		 1693 bio_list_add_head(&nvmeq->sq_cong, bio);
1694 break;
1695 }
1696 }
1697}
1698
1699static int nvme_kthread(void *data)
1700{
d4b4ff8e 1701 struct nvme_dev *dev, *next;
1fa6aead
MW		 1702
1703 while (!kthread_should_stop()) {
564a232c 1704 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1705 spin_lock(&dev_list_lock);
d4b4ff8e 1706 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1707 int i;
d4b4ff8e
KB		 1708 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1709 dev->initialized) {
1710 if (work_busy(&dev->reset_work))
1711 continue;
1712 list_del_init(&dev->node);
1713 dev_warn(&dev->pci_dev->dev,
1714 "Failed status, reset controller\n");
bdfd70fd 1715 PREPARE_WORK(&dev->reset_work,
d4b4ff8e
KB		 1716 nvme_reset_failed_dev);
1717 queue_work(nvme_workq, &dev->reset_work);
1718 continue;
1719 }
5a92e700 1720 rcu_read_lock();
1fa6aead 1721 for (i = 0; i < dev->queue_count; i++) {
5a92e700
KB		 1722 struct nvme_queue *nvmeq =
1723 rcu_dereference(dev->queues[i]);
740216fc
MW		 1724 if (!nvmeq)
1725 continue;
1fa6aead 1726 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1727 if (nvmeq->q_suspended)
1728 goto unlock;
bc57a0f7 1729 nvme_process_cq(nvmeq);
a09115b2 1730 nvme_cancel_ios(nvmeq, true);
1fa6aead 1731 nvme_resubmit_bios(nvmeq);
22404274 1732 unlock:
1fa6aead
MW		 1733 spin_unlock_irq(&nvmeq->q_lock);
1734 }
5a92e700 1735 rcu_read_unlock();
1fa6aead
MW		 1736 }
1737 spin_unlock(&dev_list_lock);
acb7aa0d 1738 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1739 }
1740 return 0;
1741}
1742
0e5e4f0e
KB		 1743static void nvme_config_discard(struct nvme_ns *ns)
1744{
1745 u32 logical_block_size = queue_logical_block_size(ns->queue);
1746 ns->queue->limits.discard_zeroes_data = 0;
1747 ns->queue->limits.discard_alignment = logical_block_size;
1748 ns->queue->limits.discard_granularity = logical_block_size;
1749 ns->queue->limits.max_discard_sectors = 0xffffffff;
1750 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1751}
1752
c3bfe717 1753static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1754 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1755{
1756 struct nvme_ns *ns;
1757 struct gendisk *disk;
1758 int lbaf;
1759
1760 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1761 return NULL;
1762
1763 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1764 if (!ns)
1765 return NULL;
1766 ns->queue = blk_alloc_queue(GFP_KERNEL);
1767 if (!ns->queue)
1768 goto out_free_ns;
4eeb9215
MW		 1769 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1770 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1771 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 1772 blk_queue_make_request(ns->queue, nvme_make_request);
1773 ns->dev = dev;
1774 ns->queue->queuedata = ns;
1775
469071a3 1776 disk = alloc_disk(0);
b60503ba
MW		 1777 if (!disk)
1778 goto out_free_queue;
5aff9382 1779 ns->ns_id = nsid;
b60503ba
MW		 1780 ns->disk = disk;
1781 lbaf = id->flbas & 0xf;
1782 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1783 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1784 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1785 if (dev->max_hw_sectors)
1786 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
b60503ba
MW		 1787
1788 disk->major = nvme_major;
469071a3 1789 disk->first_minor = 0;
b60503ba
MW		 1790 disk->fops = &nvme_fops;
1791 disk->private_data = ns;
1792 disk->queue = ns->queue;
388f037f 1793 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1794 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1795 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1796 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1797
0e5e4f0e
KB		 1798 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1799 nvme_config_discard(ns);
1800
b60503ba
MW		 1801 return ns;
1802
1803 out_free_queue:
1804 blk_cleanup_queue(ns->queue);
1805 out_free_ns:
1806 kfree(ns);
1807 return NULL;
1808}
1809
b3b06812 1810static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 1811{
1812 int status;
1813 u32 result;
b3b06812 1814 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 1815
df348139 1816 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 1817 &result);
b60503ba 1818 if (status)
7e03b124 1819 return status < 0 ? -EIO : -EBUSY;
b60503ba
MW		 1820 return min(result & 0xffff, result >> 16) + 1;
1821}
1822
9d713c2b
KB		 1823static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1824{
b80d5ccc 1825 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 1826}
1827
8d85fce7 1828static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1829{
5a92e700 1830 struct nvme_queue *adminq = raw_nvmeq(dev, 0);
fa08a396 1831 struct pci_dev *pdev = dev->pci_dev;
9d713c2b 1832 int result, cpu, i, vecs, nr_io_queues, size, q_depth;
b60503ba 1833
b348b7d5
MW		 1834 nr_io_queues = num_online_cpus();
1835 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW		 1836 if (result < 0)
1837 return result;
b348b7d5
MW		 1838 if (result < nr_io_queues)
1839 nr_io_queues = result;
b60503ba 1840
9d713c2b
KB		 1841 size = db_bar_size(dev, nr_io_queues);
1842 if (size > 8192) {
f1938f6e 1843 iounmap(dev->bar);
9d713c2b
KB		 1844 do {
1845 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1846 if (dev->bar)
1847 break;
1848 if (!--nr_io_queues)
1849 return -ENOMEM;
1850 size = db_bar_size(dev, nr_io_queues);
1851 } while (1);
f1938f6e 1852 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 1853 adminq->q_db = dev->dbs;
f1938f6e
MW		 1854 }
1855
9d713c2b 1856 /* Deregister the admin queue's interrupt */
3193f07b 1857 free_irq(dev->entry[0].vector, adminq);
9d713c2b 1858
063a8096
MW		 1859 vecs = nr_io_queues;
1860 for (i = 0; i < vecs; i++)
1b23484b
MW		 1861 dev->entry[i].entry = i;
1862 for (;;) {
063a8096
MW		 1863 result = pci_enable_msix(pdev, dev->entry, vecs);
1864 if (result <= 0)
1b23484b 1865 break;
063a8096 1866 vecs = result;
1b23484b
MW		 1867 }
1868
063a8096
MW		 1869 if (result < 0) {
1870 vecs = nr_io_queues;
1871 if (vecs > 32)
1872 vecs = 32;
fa08a396 1873 for (;;) {
063a8096 1874 result = pci_enable_msi_block(pdev, vecs);
fa08a396 1875 if (result == 0) {
063a8096 1876 for (i = 0; i < vecs; i++)
fa08a396
RRG		 1877 dev->entry[i].vector = i + pdev->irq;
1878 break;
063a8096
MW		 1879 } else if (result < 0) {
1880 vecs = 1;
fa08a396
RRG		 1881 break;
1882 }
063a8096 1883 vecs = result;
fa08a396
RRG		 1884 }
1885 }
1886
063a8096
MW		 1887 /*
1888 * Should investigate if there's a performance win from allocating
1889 * more queues than interrupt vectors; it might allow the submission
1890 * path to scale better, even if the receive path is limited by the
1891 * number of interrupts.
1892 */
1893 nr_io_queues = vecs;
1894
3193f07b 1895 result = queue_request_irq(dev, adminq, adminq->irqname);
9d713c2b 1896 if (result) {
3193f07b 1897 adminq->q_suspended = 1;
22404274 1898 goto free_queues;
9d713c2b 1899 }
1b23484b 1900
cd638946 1901 /* Free previously allocated queues that are no longer usable */
5a92e700 1902 nvme_free_queues(dev, nr_io_queues);
cd638946 1903
1b23484b 1904 cpu = cpumask_first(cpu_online_mask);
b348b7d5 1905 for (i = 0; i < nr_io_queues; i++) {
1b23484b
MW		 1906 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1907 cpu = cpumask_next(cpu, cpu_online_mask);
1908 }
1909
a0cadb85
KB		 1910 q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1,
1911 NVME_Q_DEPTH);
cd638946 1912 for (i = dev->queue_count - 1; i < nr_io_queues; i++) {
5a92e700 1913 if (!nvme_alloc_queue(dev, i + 1, q_depth, i)) {
22404274
KB		 1914 result = -ENOMEM;
1915 goto free_queues;
1916 }
1b23484b 1917 }
b60503ba 1918
9ecdc946
MW		 1919 for (; i < num_possible_cpus(); i++) {
1920 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
5a92e700 1921 rcu_assign_pointer(dev->queues[i + 1], dev->queues[target + 1]);
9ecdc946
MW		 1922 }
1923
22404274 1924 for (i = 1; i < dev->queue_count; i++) {
5a92e700 1925 result = nvme_create_queue(raw_nvmeq(dev, i), i);
22404274
KB		 1926 if (result) {
1927 for (--i; i > 0; i--)
1928 nvme_disable_queue(dev, i);
1929 goto free_queues;
1930 }
1931 }
b60503ba 1932
22404274 1933 return 0;
b60503ba 1934
22404274 1935 free_queues:
a1a5ef99 1936 nvme_free_queues(dev, 1);
22404274 1937 return result;
b60503ba
MW		 1938}
1939
422ef0c7
MW		 1940/*
1941 * Return: error value if an error occurred setting up the queues or calling
1942 * Identify Device. 0 if these succeeded, even if adding some of the
1943 * namespaces failed. At the moment, these failures are silent. TBD which
1944 * failures should be reported.
1945 */
8d85fce7 1946static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 1947{
68608c26 1948 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 1949 int res;
1950 unsigned nn, i;
cbb6218f 1951 struct nvme_ns *ns;
51814232 1952 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 1953 struct nvme_id_ns *id_ns;
1954 void *mem;
b60503ba 1955 dma_addr_t dma_addr;
159b67d7 1956 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 1957
68608c26 1958 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 1959 if (!mem)
1960 return -ENOMEM;
b60503ba 1961
bc5fc7e4 1962 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba
MW		 1963 if (res) {
1964 res = -EIO;
cbb6218f 1965 goto out;
b60503ba
MW		 1966 }
1967
bc5fc7e4 1968 ctrl = mem;
51814232 1969 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 1970 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 1971 dev->abort_limit = ctrl->acl + 1;
51814232
MW		 1972 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1973 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1974 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 1975 if (ctrl->mdts)
8fc23e03 1976 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26
MW		 1977 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
1978 (pdev->device == 0x0953) && ctrl->vs[3])
159b67d7 1979 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
b60503ba 1980
bc5fc7e4 1981 id_ns = mem;
2b2c1896 1982 for (i = 1; i <= nn; i++) {
bc5fc7e4 1983 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 1984 if (res)
1985 continue;
1986
bc5fc7e4 1987 if (id_ns->ncap == 0)
b60503ba
MW		 1988 continue;
1989
bc5fc7e4 1990 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 1991 dma_addr + 4096, NULL);
b60503ba 1992 if (res)
12209036 1993 memset(mem + 4096, 0, 4096);
b60503ba 1994
bc5fc7e4 1995 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 1996 if (ns)
1997 list_add_tail(&ns->list, &dev->namespaces);
1998 }
1999 list_for_each_entry(ns, &dev->namespaces, list)
2000 add_disk(ns->disk);
422ef0c7 2001 res = 0;
b60503ba 2002
bc5fc7e4 2003 out:
684f5c20 2004 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2005 return res;
2006}
2007
0877cb0d
KB		 2008static int nvme_dev_map(struct nvme_dev *dev)
2009{
2010 int bars, result = -ENOMEM;
2011 struct pci_dev *pdev = dev->pci_dev;
2012
2013 if (pci_enable_device_mem(pdev))
2014 return result;
2015
2016 dev->entry[0].vector = pdev->irq;
2017 pci_set_master(pdev);
2018 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2019 if (pci_request_selected_regions(pdev, bars, "nvme"))
2020 goto disable_pci;
2021
052d0efa
RK		 2022 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2023 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2024 goto disable;
0877cb0d 2025
0877cb0d
KB		 2026 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2027 if (!dev->bar)
2028 goto disable;
0e53d180
KB		 2029 if (readl(&dev->bar->csts) == -1) {
2030 result = -ENODEV;
2031 goto unmap;
2032 }
b80d5ccc 2033 dev->db_stride = 1 << NVME_CAP_STRIDE(readq(&dev->bar->cap));
0877cb0d
KB		 2034 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2035
2036 return 0;
2037
0e53d180
KB		 2038 unmap:
2039 iounmap(dev->bar);
2040 dev->bar = NULL;
0877cb0d
KB		 2041 disable:
2042 pci_release_regions(pdev);
2043 disable_pci:
2044 pci_disable_device(pdev);
2045 return result;
2046}
2047
2048static void nvme_dev_unmap(struct nvme_dev *dev)
2049{
2050 if (dev->pci_dev->msi_enabled)
2051 pci_disable_msi(dev->pci_dev);
2052 else if (dev->pci_dev->msix_enabled)
2053 pci_disable_msix(dev->pci_dev);
2054
2055 if (dev->bar) {
2056 iounmap(dev->bar);
2057 dev->bar = NULL;
9a6b9458 2058 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2059 }
2060
0877cb0d
KB		 2061 if (pci_is_enabled(dev->pci_dev))
2062 pci_disable_device(dev->pci_dev);
2063}
2064
4d115420
KB		 2065struct nvme_delq_ctx {
2066 struct task_struct *waiter;
2067 struct kthread_worker *worker;
2068 atomic_t refcount;
2069};
2070
2071static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2072{
2073 dq->waiter = current;
2074 mb();
2075
2076 for (;;) {
2077 set_current_state(TASK_KILLABLE);
2078 if (!atomic_read(&dq->refcount))
2079 break;
2080 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2081 fatal_signal_pending(current)) {
2082 set_current_state(TASK_RUNNING);
2083
2084 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2085 nvme_disable_queue(dev, 0);
2086
2087 send_sig(SIGKILL, dq->worker->task, 1);
2088 flush_kthread_worker(dq->worker);
2089 return;
2090 }
2091 }
2092 set_current_state(TASK_RUNNING);
2093}
2094
2095static void nvme_put_dq(struct nvme_delq_ctx *dq)
2096{
2097 atomic_dec(&dq->refcount);
2098 if (dq->waiter)
2099 wake_up_process(dq->waiter);
2100}
2101
2102static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2103{
2104 atomic_inc(&dq->refcount);
2105 return dq;
2106}
2107
2108static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2109{
2110 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2111
2112 nvme_clear_queue(nvmeq);
2113 nvme_put_dq(dq);
2114}
2115
2116static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2117 kthread_work_func_t fn)
2118{
2119 struct nvme_command c;
2120
2121 memset(&c, 0, sizeof(c));
2122 c.delete_queue.opcode = opcode;
2123 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2124
2125 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2126 return nvme_submit_admin_cmd_async(nvmeq->dev, &c, &nvmeq->cmdinfo);
2127}
2128
2129static void nvme_del_cq_work_handler(struct kthread_work *work)
2130{
2131 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2132 cmdinfo.work);
2133 nvme_del_queue_end(nvmeq);
2134}
2135
2136static int nvme_delete_cq(struct nvme_queue *nvmeq)
2137{
2138 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2139 nvme_del_cq_work_handler);
2140}
2141
2142static void nvme_del_sq_work_handler(struct kthread_work *work)
2143{
2144 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2145 cmdinfo.work);
2146 int status = nvmeq->cmdinfo.status;
2147
2148 if (!status)
2149 status = nvme_delete_cq(nvmeq);
2150 if (status)
2151 nvme_del_queue_end(nvmeq);
2152}
2153
2154static int nvme_delete_sq(struct nvme_queue *nvmeq)
2155{
2156 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2157 nvme_del_sq_work_handler);
2158}
2159
2160static void nvme_del_queue_start(struct kthread_work *work)
2161{
2162 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2163 cmdinfo.work);
2164 allow_signal(SIGKILL);
2165 if (nvme_delete_sq(nvmeq))
2166 nvme_del_queue_end(nvmeq);
2167}
2168
2169static void nvme_disable_io_queues(struct nvme_dev *dev)
2170{
2171 int i;
2172 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2173 struct nvme_delq_ctx dq;
2174 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2175 &worker, "nvme%d", dev->instance);
2176
2177 if (IS_ERR(kworker_task)) {
2178 dev_err(&dev->pci_dev->dev,
2179 "Failed to create queue del task\n");
2180 for (i = dev->queue_count - 1; i > 0; i--)
2181 nvme_disable_queue(dev, i);
2182 return;
2183 }
2184
2185 dq.waiter = NULL;
2186 atomic_set(&dq.refcount, 0);
2187 dq.worker = &worker;
2188 for (i = dev->queue_count - 1; i > 0; i--) {
5a92e700 2189 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2190
2191 if (nvme_suspend_queue(nvmeq))
2192 continue;
2193 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2194 nvmeq->cmdinfo.worker = dq.worker;
2195 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2196 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2197 }
2198 nvme_wait_dq(&dq, dev);
2199 kthread_stop(kworker_task);
2200}
2201
f0b50732 2202static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2203{
22404274
KB		 2204 int i;
2205
d4b4ff8e 2206 dev->initialized = 0;
b60503ba 2207
1fa6aead 2208 spin_lock(&dev_list_lock);
f0b50732 2209 list_del_init(&dev->node);
1fa6aead
MW		 2210 spin_unlock(&dev_list_lock);
2211
4d115420
KB		 2212 if (!dev->bar || (dev->bar && readl(&dev->bar->csts) == -1)) {
2213 for (i = dev->queue_count - 1; i >= 0; i--) {
5a92e700 2214 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2215 nvme_suspend_queue(nvmeq);
2216 nvme_clear_queue(nvmeq);
2217 }
2218 } else {
2219 nvme_disable_io_queues(dev);
1894d8f1 2220 nvme_shutdown_ctrl(dev);
4d115420
KB		 2221 nvme_disable_queue(dev, 0);
2222 }
f0b50732
KB		 2223 nvme_dev_unmap(dev);
2224}
2225
2226static void nvme_dev_remove(struct nvme_dev *dev)
2227{
9ac27090 2228 struct nvme_ns *ns;
f0b50732 2229
9ac27090
KB		 2230 list_for_each_entry(ns, &dev->namespaces, list) {
2231 if (ns->disk->flags & GENHD_FL_UP)
2232 del_gendisk(ns->disk);
2233 if (!blk_queue_dying(ns->queue))
2234 blk_cleanup_queue(ns->queue);
b60503ba 2235 }
b60503ba
MW		 2236}
2237
091b6092
MW		 2238static int nvme_setup_prp_pools(struct nvme_dev *dev)
2239{
2240 struct device *dmadev = &dev->pci_dev->dev;
2241 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2242 PAGE_SIZE, PAGE_SIZE, 0);
2243 if (!dev->prp_page_pool)
2244 return -ENOMEM;
2245
99802a7a
MW		 2246 /* Optimisation for I/Os between 4k and 128k */
2247 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2248 256, 256, 0);
2249 if (!dev->prp_small_pool) {
2250 dma_pool_destroy(dev->prp_page_pool);
2251 return -ENOMEM;
2252 }
091b6092
MW		 2253 return 0;
2254}
2255
2256static void nvme_release_prp_pools(struct nvme_dev *dev)
2257{
2258 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2259 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2260}
2261
cd58ad7d
QSA		 2262static DEFINE_IDA(nvme_instance_ida);
2263
2264static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2265{
cd58ad7d
QSA		 2266 int instance, error;
2267
2268 do {
2269 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2270 return -ENODEV;
2271
2272 spin_lock(&dev_list_lock);
2273 error = ida_get_new(&nvme_instance_ida, &instance);
2274 spin_unlock(&dev_list_lock);
2275 } while (error == -EAGAIN);
2276
2277 if (error)
2278 return -ENODEV;
2279
2280 dev->instance = instance;
2281 return 0;
b60503ba
MW		 2282}
2283
2284static void nvme_release_instance(struct nvme_dev *dev)
2285{
cd58ad7d
QSA		 2286 spin_lock(&dev_list_lock);
2287 ida_remove(&nvme_instance_ida, dev->instance);
2288 spin_unlock(&dev_list_lock);
b60503ba
MW		 2289}
2290
9ac27090
KB		 2291static void nvme_free_namespaces(struct nvme_dev *dev)
2292{
2293 struct nvme_ns *ns, *next;
2294
2295 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2296 list_del(&ns->list);
2297 put_disk(ns->disk);
2298 kfree(ns);
2299 }
2300}
2301
5e82e952
KB		 2302static void nvme_free_dev(struct kref *kref)
2303{
2304 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090
KB		 2305
2306 nvme_free_namespaces(dev);
5e82e952
KB		 2307 kfree(dev->queues);
2308 kfree(dev->entry);
2309 kfree(dev);
2310}
2311
2312static int nvme_dev_open(struct inode *inode, struct file *f)
2313{
2314 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2315 miscdev);
2316 kref_get(&dev->kref);
2317 f->private_data = dev;
2318 return 0;
2319}
2320
2321static int nvme_dev_release(struct inode *inode, struct file *f)
2322{
2323 struct nvme_dev *dev = f->private_data;
2324 kref_put(&dev->kref, nvme_free_dev);
2325 return 0;
2326}
2327
2328static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2329{
2330 struct nvme_dev *dev = f->private_data;
2331 switch (cmd) {
2332 case NVME_IOCTL_ADMIN_CMD:
2333 return nvme_user_admin_cmd(dev, (void __user *)arg);
2334 default:
2335 return -ENOTTY;
2336 }
2337}
2338
2339static const struct file_operations nvme_dev_fops = {
2340 .owner = THIS_MODULE,
2341 .open = nvme_dev_open,
2342 .release = nvme_dev_release,
2343 .unlocked_ioctl = nvme_dev_ioctl,
2344 .compat_ioctl = nvme_dev_ioctl,
2345};
2346
f0b50732
KB		 2347static int nvme_dev_start(struct nvme_dev *dev)
2348{
2349 int result;
2350
2351 result = nvme_dev_map(dev);
2352 if (result)
2353 return result;
2354
2355 result = nvme_configure_admin_queue(dev);
2356 if (result)
2357 goto unmap;
2358
2359 spin_lock(&dev_list_lock);
2360 list_add(&dev->node, &dev_list);
2361 spin_unlock(&dev_list_lock);
2362
2363 result = nvme_setup_io_queues(dev);
d82e8bfd 2364 if (result && result != -EBUSY)
f0b50732
KB		 2365 goto disable;
2366
d82e8bfd 2367 return result;
f0b50732
KB		 2368
2369 disable:
a1a5ef99 2370 nvme_disable_queue(dev, 0);
f0b50732
KB		 2371 spin_lock(&dev_list_lock);
2372 list_del_init(&dev->node);
2373 spin_unlock(&dev_list_lock);
2374 unmap:
2375 nvme_dev_unmap(dev);
2376 return result;
2377}
2378
9a6b9458
KB		 2379static int nvme_remove_dead_ctrl(void *arg)
2380{
2381 struct nvme_dev *dev = (struct nvme_dev *)arg;
2382 struct pci_dev *pdev = dev->pci_dev;
2383
2384 if (pci_get_drvdata(pdev))
2385 pci_stop_and_remove_bus_device(pdev);
2386 kref_put(&dev->kref, nvme_free_dev);
2387 return 0;
2388}
2389
2390static void nvme_remove_disks(struct work_struct *ws)
2391{
9a6b9458
KB		 2392 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2393
2394 nvme_dev_remove(dev);
5a92e700 2395 nvme_free_queues(dev, 1);
9a6b9458
KB		 2396}
2397
2398static int nvme_dev_resume(struct nvme_dev *dev)
2399{
2400 int ret;
2401
2402 ret = nvme_dev_start(dev);
2403 if (ret && ret != -EBUSY)
2404 return ret;
2405 if (ret == -EBUSY) {
2406 spin_lock(&dev_list_lock);
bdfd70fd 2407 PREPARE_WORK(&dev->reset_work, nvme_remove_disks);
9a6b9458
KB		 2408 queue_work(nvme_workq, &dev->reset_work);
2409 spin_unlock(&dev_list_lock);
2410 }
d4b4ff8e 2411 dev->initialized = 1;
9a6b9458
KB		 2412 return 0;
2413}
2414
2415static void nvme_dev_reset(struct nvme_dev *dev)
2416{
2417 nvme_dev_shutdown(dev);
2418 if (nvme_dev_resume(dev)) {
2419 dev_err(&dev->pci_dev->dev, "Device failed to resume\n");
2420 kref_get(&dev->kref);
2421 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2422 dev->instance))) {
2423 dev_err(&dev->pci_dev->dev,
2424 "Failed to start controller remove task\n");
2425 kref_put(&dev->kref, nvme_free_dev);
2426 }
2427 }
2428}
2429
2430static void nvme_reset_failed_dev(struct work_struct *ws)
2431{
2432 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2433 nvme_dev_reset(dev);
2434}
2435
8d85fce7 2436static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2437{
0877cb0d 2438 int result = -ENOMEM;
b60503ba
MW		 2439 struct nvme_dev *dev;
2440
2441 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2442 if (!dev)
2443 return -ENOMEM;
2444 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2445 GFP_KERNEL);
2446 if (!dev->entry)
2447 goto free;
1b23484b
MW		 2448 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2449 GFP_KERNEL);
b60503ba
MW		 2450 if (!dev->queues)
2451 goto free;
2452
2453 INIT_LIST_HEAD(&dev->namespaces);
bdfd70fd 2454 INIT_WORK(&dev->reset_work, nvme_reset_failed_dev);
b60503ba 2455 dev->pci_dev = pdev;
9a6b9458 2456 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2457 result = nvme_set_instance(dev);
2458 if (result)
0877cb0d 2459 goto free;
b60503ba 2460
091b6092
MW		 2461 result = nvme_setup_prp_pools(dev);
2462 if (result)
0877cb0d 2463 goto release;
091b6092 2464
fb35e914 2465 kref_init(&dev->kref);
f0b50732 2466 result = nvme_dev_start(dev);
d82e8bfd
KB		 2467 if (result) {
2468 if (result == -EBUSY)
2469 goto create_cdev;
0877cb0d 2470 goto release_pools;
d82e8bfd 2471 }
b60503ba 2472
740216fc 2473 result = nvme_dev_add(dev);
d82e8bfd 2474 if (result)
f0b50732 2475 goto shutdown;
740216fc 2476
d82e8bfd 2477 create_cdev:
5e82e952
KB		 2478 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2479 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2480 dev->miscdev.parent = &pdev->dev;
2481 dev->miscdev.name = dev->name;
2482 dev->miscdev.fops = &nvme_dev_fops;
2483 result = misc_register(&dev->miscdev);
2484 if (result)
2485 goto remove;
2486
d4b4ff8e 2487 dev->initialized = 1;
b60503ba
MW		 2488 return 0;
2489
5e82e952
KB		 2490 remove:
2491 nvme_dev_remove(dev);
9ac27090 2492 nvme_free_namespaces(dev);
f0b50732
KB		 2493 shutdown:
2494 nvme_dev_shutdown(dev);
0877cb0d 2495 release_pools:
a1a5ef99 2496 nvme_free_queues(dev, 0);
091b6092 2497 nvme_release_prp_pools(dev);
0877cb0d
KB		 2498 release:
2499 nvme_release_instance(dev);
b60503ba
MW		 2500 free:
2501 kfree(dev->queues);
2502 kfree(dev->entry);
2503 kfree(dev);
2504 return result;
2505}
2506
09ece142
KB		 2507static void nvme_shutdown(struct pci_dev *pdev)
2508{
2509 struct nvme_dev *dev = pci_get_drvdata(pdev);
2510 nvme_dev_shutdown(dev);
2511}
2512
8d85fce7 2513static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2514{
2515 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2516
2517 spin_lock(&dev_list_lock);
2518 list_del_init(&dev->node);
2519 spin_unlock(&dev_list_lock);
2520
2521 pci_set_drvdata(pdev, NULL);
2522 flush_work(&dev->reset_work);
5e82e952 2523 misc_deregister(&dev->miscdev);
9a6b9458
KB		 2524 nvme_dev_remove(dev);
2525 nvme_dev_shutdown(dev);
a1a5ef99 2526 nvme_free_queues(dev, 0);
5a92e700 2527 rcu_barrier();
9a6b9458
KB		 2528 nvme_release_instance(dev);
2529 nvme_release_prp_pools(dev);
5e82e952 2530 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2531}
2532
2533/* These functions are yet to be implemented */
2534#define nvme_error_detected NULL
2535#define nvme_dump_registers NULL
2536#define nvme_link_reset NULL
2537#define nvme_slot_reset NULL
2538#define nvme_error_resume NULL
cd638946 2539
671a6018 2540#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2541static int nvme_suspend(struct device *dev)
2542{
2543 struct pci_dev *pdev = to_pci_dev(dev);
2544 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2545
2546 nvme_dev_shutdown(ndev);
2547 return 0;
2548}
2549
2550static int nvme_resume(struct device *dev)
2551{
2552 struct pci_dev *pdev = to_pci_dev(dev);
2553 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2554
9a6b9458 2555 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
bdfd70fd 2556 PREPARE_WORK(&ndev->reset_work, nvme_reset_failed_dev);
9a6b9458
KB		 2557 queue_work(nvme_workq, &ndev->reset_work);
2558 }
2559 return 0;
cd638946 2560}
671a6018 2561#endif
cd638946
KB		 2562
2563static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2564
1d352035 2565static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2566 .error_detected = nvme_error_detected,
2567 .mmio_enabled = nvme_dump_registers,
2568 .link_reset = nvme_link_reset,
2569 .slot_reset = nvme_slot_reset,
2570 .resume = nvme_error_resume,
2571};
2572
2573/* Move to pci_ids.h later */
2574#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2575
2576static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
2577 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2578 { 0, }
2579};
2580MODULE_DEVICE_TABLE(pci, nvme_id_table);
2581
2582static struct pci_driver nvme_driver = {
2583 .name = "nvme",
2584 .id_table = nvme_id_table,
2585 .probe = nvme_probe,
8d85fce7 2586 .remove = nvme_remove,
09ece142 2587 .shutdown = nvme_shutdown,
cd638946
KB		 2588 .driver = {
2589 .pm = &nvme_dev_pm_ops,
2590 },
b60503ba
MW		 2591 .err_handler = &nvme_err_handler,
2592};
2593
2594static int __init nvme_init(void)
2595{
0ac13140 2596 int result;
1fa6aead
MW		 2597
2598 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2599 if (IS_ERR(nvme_thread))
2600 return PTR_ERR(nvme_thread);
b60503ba 2601
9a6b9458
KB		 2602 result = -ENOMEM;
2603 nvme_workq = create_singlethread_workqueue("nvme");
2604 if (!nvme_workq)
2605 goto kill_kthread;
2606
5c42ea16
KB		 2607 result = register_blkdev(nvme_major, "nvme");
2608 if (result < 0)
9a6b9458 2609 goto kill_workq;
5c42ea16 2610 else if (result > 0)
0ac13140 2611 nvme_major = result;
b60503ba
MW		 2612
2613 result = pci_register_driver(&nvme_driver);
1fa6aead
MW		 2614 if (result)
2615 goto unregister_blkdev;
2616 return 0;
b60503ba 2617
1fa6aead 2618 unregister_blkdev:
b60503ba 2619 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2620 kill_workq:
2621 destroy_workqueue(nvme_workq);
1fa6aead
MW		 2622 kill_kthread:
2623 kthread_stop(nvme_thread);
b60503ba
MW		 2624 return result;
2625}
2626
2627static void __exit nvme_exit(void)
2628{
2629 pci_unregister_driver(&nvme_driver);
2630 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2631 destroy_workqueue(nvme_workq);
1fa6aead 2632 kthread_stop(nvme_thread);
b60503ba
MW		 2633}
2634
2635MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2636MODULE_LICENSE("GPL");
366e8217 2637MODULE_VERSION("0.8");
b60503ba
MW		 2638module_init(nvme_init);
2639module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)