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NVMe: Add getgeo to block ops
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/nvme.h>
20#include <linux/bio.h>
8de05535 21#include <linux/bitops.h>
b60503ba 22#include <linux/blkdev.h>
42f61420 23#include <linux/cpu.h>
fd63e9ce 24#include <linux/delay.h>
b60503ba
MW		 25#include <linux/errno.h>
26#include <linux/fs.h>
27#include <linux/genhd.h>
4cc09e2d 28#include <linux/hdreg.h>
5aff9382 29#include <linux/idr.h>
b60503ba
MW		 30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/kdev_t.h>
1fa6aead 34#include <linux/kthread.h>
b60503ba
MW		 35#include <linux/kernel.h>
36#include <linux/mm.h>
37#include <linux/module.h>
38#include <linux/moduleparam.h>
39#include <linux/pci.h>
42f61420 40#include <linux/percpu.h>
be7b6275 41#include <linux/poison.h>
c3bfe717 42#include <linux/ptrace.h>
b60503ba
MW		 43#include <linux/sched.h>
44#include <linux/slab.h>
45#include <linux/types.h>
5d0f6131 46#include <scsi/sg.h>
797a796a
HM		 47#include <asm-generic/io-64-nonatomic-lo-hi.h>
48
b60503ba
MW		 49#define NVME_Q_DEPTH 1024
50#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
51#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
e85248e5 52#define ADMIN_TIMEOUT (60 * HZ)
b60503ba 53
b355084a
KB		 54unsigned char io_timeout = 30;
55module_param(io_timeout, byte, 0644);
56MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
57
b60503ba
MW		 58static int nvme_major;
59module_param(nvme_major, int, 0);
60
58ffacb5
MW		 61static int use_threaded_interrupts;
62module_param(use_threaded_interrupts, int, 0);
63
1fa6aead
MW		 64static DEFINE_SPINLOCK(dev_list_lock);
65static LIST_HEAD(dev_list);
66static struct task_struct *nvme_thread;
9a6b9458 67static struct workqueue_struct *nvme_workq;
b9afca3e 68static wait_queue_head_t nvme_kthread_wait;
1fa6aead 69
d4b4ff8e
KB		 70static void nvme_reset_failed_dev(struct work_struct *ws);
71
4d115420
KB		 72struct async_cmd_info {
73 struct kthread_work work;
74 struct kthread_worker *worker;
75 u32 result;
76 int status;
77 void *ctx;
78};
1fa6aead 79
b60503ba
MW		 80/*
81 * An NVM Express queue. Each device has at least two (one for admin
82 * commands and one for I/O commands).
83 */
84struct nvme_queue {
5a92e700 85 struct rcu_head r_head;
b60503ba 86 struct device *q_dmadev;
091b6092 87 struct nvme_dev *dev;
3193f07b 88 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 89 spinlock_t q_lock;
90 struct nvme_command *sq_cmds;
91 volatile struct nvme_completion *cqes;
92 dma_addr_t sq_dma_addr;
93 dma_addr_t cq_dma_addr;
94 wait_queue_head_t sq_full;
1fa6aead 95 wait_queue_t sq_cong_wait;
b60503ba
MW		 96 struct bio_list sq_cong;
97 u32 __iomem *q_db;
98 u16 q_depth;
99 u16 cq_vector;
100 u16 sq_head;
101 u16 sq_tail;
102 u16 cq_head;
c30341dc 103 u16 qid;
e9539f47
MW		 104 u8 cq_phase;
105 u8 cqe_seen;
22404274 106 u8 q_suspended;
42f61420 107 cpumask_var_t cpu_mask;
4d115420 108 struct async_cmd_info cmdinfo;
b60503ba
MW		 109 unsigned long cmdid_data[];
110};
111
112/*
113 * Check we didin't inadvertently grow the command struct
114 */
115static inline void _nvme_check_size(void)
116{
117 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
118 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
119 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
120 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
121 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 122 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 123 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 124 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
125 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
126 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
127 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 128 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 129}
130
5c1281a3 131typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
c2f5b650
MW		 132 struct nvme_completion *);
133
e85248e5 134struct nvme_cmd_info {
c2f5b650
MW		 135 nvme_completion_fn fn;
136 void *ctx;
e85248e5 137 unsigned long timeout;
c30341dc 138 int aborted;
e85248e5
MW		 139};
140
141static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
142{
143 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
144}
145
22404274
KB		 146static unsigned nvme_queue_extra(int depth)
147{
148 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
149}
150
b60503ba 151/**
714a7a22
MW		 152 * alloc_cmdid() - Allocate a Command ID
153 * @nvmeq: The queue that will be used for this command
154 * @ctx: A pointer that will be passed to the handler
c2f5b650 155 * @handler: The function to call on completion
b60503ba
MW		 156 *
157 * Allocate a Command ID for a queue. The data passed in will
158 * be passed to the completion handler. This is implemented by using
159 * the bottom two bits of the ctx pointer to store the handler ID.
160 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
161 * We can change this if it becomes a problem.
184d2944
MW		 162 *
163 * May be called with local interrupts disabled and the q_lock held,
164 * or with interrupts enabled and no locks held.
b60503ba 165 */
c2f5b650
MW		 166static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
167 nvme_completion_fn handler, unsigned timeout)
b60503ba 168{
e6d15f79 169 int depth = nvmeq->q_depth - 1;
e85248e5 170 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba
MW		 171 int cmdid;
172
b60503ba
MW		 173 do {
174 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
175 if (cmdid >= depth)
176 return -EBUSY;
177 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
178
c2f5b650
MW		 179 info[cmdid].fn = handler;
180 info[cmdid].ctx = ctx;
e85248e5 181 info[cmdid].timeout = jiffies + timeout;
c30341dc 182 info[cmdid].aborted = 0;
b60503ba
MW		 183 return cmdid;
184}
185
186static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 187 nvme_completion_fn handler, unsigned timeout)
b60503ba
MW		 188{
189 int cmdid;
190 wait_event_killable(nvmeq->sq_full,
e85248e5 191 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
b60503ba
MW		 192 return (cmdid < 0) ? -EINTR : cmdid;
193}
194
c2f5b650
MW		 195/* Special values must be less than 0x1000 */
196#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 197#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
198#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
199#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
00df5cb4 200#define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
c30341dc 201#define CMD_CTX_ABORT (0x31C + CMD_CTX_BASE)
be7b6275 202
5c1281a3 203static void special_completion(struct nvme_dev *dev, void *ctx,
c2f5b650
MW		 204 struct nvme_completion *cqe)
205{
206 if (ctx == CMD_CTX_CANCELLED)
207 return;
208 if (ctx == CMD_CTX_FLUSH)
209 return;
c30341dc
KB		 210 if (ctx == CMD_CTX_ABORT) {
211 ++dev->abort_limit;
212 return;
213 }
c2f5b650 214 if (ctx == CMD_CTX_COMPLETED) {
5c1281a3 215 dev_warn(&dev->pci_dev->dev,
c2f5b650
MW		 216 "completed id %d twice on queue %d\n",
217 cqe->command_id, le16_to_cpup(&cqe->sq_id));
218 return;
219 }
220 if (ctx == CMD_CTX_INVALID) {
5c1281a3 221 dev_warn(&dev->pci_dev->dev,
c2f5b650
MW		 222 "invalid id %d completed on queue %d\n",
223 cqe->command_id, le16_to_cpup(&cqe->sq_id));
224 return;
225 }
226
5c1281a3 227 dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 228}
229
4d115420
KB		 230static void async_completion(struct nvme_dev *dev, void *ctx,
231 struct nvme_completion *cqe)
232{
233 struct async_cmd_info *cmdinfo = ctx;
234 cmdinfo->result = le32_to_cpup(&cqe->result);
235 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
236 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
237}
238
184d2944
MW		 239/*
240 * Called with local interrupts disabled and the q_lock held. May not sleep.
241 */
c2f5b650
MW		 242static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
243 nvme_completion_fn *fn)
b60503ba 244{
c2f5b650 245 void *ctx;
e85248e5 246 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 247
c2f5b650
MW		 248 if (cmdid >= nvmeq->q_depth) {
249 *fn = special_completion;
48e3d398 250 return CMD_CTX_INVALID;
c2f5b650 251 }
859361a2
KB		 252 if (fn)
253 *fn = info[cmdid].fn;
c2f5b650
MW		 254 ctx = info[cmdid].ctx;
255 info[cmdid].fn = special_completion;
e85248e5 256 info[cmdid].ctx = CMD_CTX_COMPLETED;
b60503ba
MW		 257 clear_bit(cmdid, nvmeq->cmdid_data);
258 wake_up(&nvmeq->sq_full);
c2f5b650 259 return ctx;
b60503ba
MW		 260}
261
c2f5b650
MW		 262static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
263 nvme_completion_fn *fn)
3c0cf138 264{
c2f5b650 265 void *ctx;
e85248e5 266 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
c2f5b650
MW		 267 if (fn)
268 *fn = info[cmdid].fn;
269 ctx = info[cmdid].ctx;
270 info[cmdid].fn = special_completion;
e85248e5 271 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 272 return ctx;
3c0cf138
MW		 273}
274
5a92e700 275static struct nvme_queue *raw_nvmeq(struct nvme_dev *dev, int qid)
b60503ba 276{
5a92e700 277 return rcu_dereference_raw(dev->queues[qid]);
b60503ba
MW		 278}
279
4f5099af 280static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) __acquires(RCU)
5a92e700 281{
42f61420 282 unsigned queue_id = get_cpu_var(*dev->io_queue);
5a92e700 283 rcu_read_lock();
42f61420 284 return rcu_dereference(dev->queues[queue_id]);
5a92e700
KB		 285}
286
4f5099af 287static void put_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
b60503ba 288{
5a92e700 289 rcu_read_unlock();
42f61420 290 put_cpu_var(nvmeq->dev->io_queue);
b60503ba
MW		 291}
292
4f5099af
KB		 293static struct nvme_queue *lock_nvmeq(struct nvme_dev *dev, int q_idx)
294 __acquires(RCU)
295{
296 rcu_read_lock();
297 return rcu_dereference(dev->queues[q_idx]);
298}
299
300static void unlock_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
301{
302 rcu_read_unlock();
303}
304
b60503ba 305/**
714a7a22 306 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 307 * @nvmeq: The queue to use
308 * @cmd: The command to send
309 *
310 * Safe to use from interrupt context
311 */
312static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
313{
314 unsigned long flags;
315 u16 tail;
b60503ba 316 spin_lock_irqsave(&nvmeq->q_lock, flags);
4f5099af
KB		 317 if (nvmeq->q_suspended) {
318 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
319 return -EBUSY;
320 }
b60503ba
MW		 321 tail = nvmeq->sq_tail;
322 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 323 if (++tail == nvmeq->q_depth)
324 tail = 0;
7547881d 325 writel(tail, nvmeq->q_db);
b60503ba
MW		 326 nvmeq->sq_tail = tail;
327 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
328
329 return 0;
330}
331
eca18b23 332static __le64 **iod_list(struct nvme_iod *iod)
e025344c 333{
eca18b23 334 return ((void *)iod) + iod->offset;
e025344c
SMM		 335}
336
eca18b23
MW		 337/*
338 * Will slightly overestimate the number of pages needed. This is OK
339 * as it only leads to a small amount of wasted memory for the lifetime of
340 * the I/O.
341 */
342static int nvme_npages(unsigned size)
343{
344 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
345 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
346}
b60503ba 347
eca18b23
MW		 348static struct nvme_iod *
349nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
b60503ba 350{
eca18b23
MW		 351 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
352 sizeof(__le64 *) * nvme_npages(nbytes) +
353 sizeof(struct scatterlist) * nseg, gfp);
354
355 if (iod) {
356 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
357 iod->npages = -1;
358 iod->length = nbytes;
2b196034 359 iod->nents = 0;
6198221f 360 iod->start_time = jiffies;
eca18b23
MW		 361 }
362
363 return iod;
b60503ba
MW		 364}
365
5d0f6131 366void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 367{
eca18b23
MW		 368 const int last_prp = PAGE_SIZE / 8 - 1;
369 int i;
370 __le64 **list = iod_list(iod);
371 dma_addr_t prp_dma = iod->first_dma;
372
373 if (iod->npages == 0)
374 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
375 for (i = 0; i < iod->npages; i++) {
376 __le64 *prp_list = list[i];
377 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
378 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
379 prp_dma = next_prp_dma;
380 }
381 kfree(iod);
b60503ba
MW		 382}
383
6198221f
KB		 384static void nvme_start_io_acct(struct bio *bio)
385{
386 struct gendisk *disk = bio->bi_bdev->bd_disk;
387 const int rw = bio_data_dir(bio);
388 int cpu = part_stat_lock();
389 part_round_stats(cpu, &disk->part0);
390 part_stat_inc(cpu, &disk->part0, ios[rw]);
391 part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio));
392 part_inc_in_flight(&disk->part0, rw);
393 part_stat_unlock();
394}
395
396static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
397{
398 struct gendisk *disk = bio->bi_bdev->bd_disk;
399 const int rw = bio_data_dir(bio);
400 unsigned long duration = jiffies - start_time;
401 int cpu = part_stat_lock();
402 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
403 part_round_stats(cpu, &disk->part0);
404 part_dec_in_flight(&disk->part0, rw);
405 part_stat_unlock();
406}
407
5c1281a3 408static void bio_completion(struct nvme_dev *dev, void *ctx,
b60503ba
MW		 409 struct nvme_completion *cqe)
410{
eca18b23
MW		 411 struct nvme_iod *iod = ctx;
412 struct bio *bio = iod->private;
b60503ba
MW		 413 u16 status = le16_to_cpup(&cqe->status) >> 1;
414
9e59d091 415 if (iod->nents) {
2b196034 416 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
b60503ba 417 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9e59d091
KB		 418 nvme_end_io_acct(bio, iod->start_time);
419 }
eca18b23 420 nvme_free_iod(dev, iod);
427e9708 421 if (status)
1ad2f893 422 bio_endio(bio, -EIO);
427e9708 423 else
1ad2f893 424 bio_endio(bio, 0);
b60503ba
MW		 425}
426
184d2944 427/* length is in bytes. gfp flags indicates whether we may sleep. */
5d0f6131
VV		 428int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd,
429 struct nvme_iod *iod, int total_len, gfp_t gfp)
ff22b54f 430{
99802a7a 431 struct dma_pool *pool;
eca18b23
MW		 432 int length = total_len;
433 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 434 int dma_len = sg_dma_len(sg);
435 u64 dma_addr = sg_dma_address(sg);
436 int offset = offset_in_page(dma_addr);
e025344c 437 __le64 *prp_list;
eca18b23 438 __le64 **list = iod_list(iod);
e025344c 439 dma_addr_t prp_dma;
eca18b23 440 int nprps, i;
ff22b54f
MW		 441
442 cmd->prp1 = cpu_to_le64(dma_addr);
443 length -= (PAGE_SIZE - offset);
444 if (length <= 0)
eca18b23 445 return total_len;
ff22b54f
MW		 446
447 dma_len -= (PAGE_SIZE - offset);
448 if (dma_len) {
449 dma_addr += (PAGE_SIZE - offset);
450 } else {
451 sg = sg_next(sg);
452 dma_addr = sg_dma_address(sg);
453 dma_len = sg_dma_len(sg);
454 }
455
456 if (length <= PAGE_SIZE) {
457 cmd->prp2 = cpu_to_le64(dma_addr);
eca18b23 458 return total_len;
e025344c
SMM		 459 }
460
461 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
99802a7a
MW		 462 if (nprps <= (256 / 8)) {
463 pool = dev->prp_small_pool;
eca18b23 464 iod->npages = 0;
99802a7a
MW		 465 } else {
466 pool = dev->prp_page_pool;
eca18b23 467 iod->npages = 1;
99802a7a
MW		 468 }
469
b77954cb
MW		 470 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
471 if (!prp_list) {
472 cmd->prp2 = cpu_to_le64(dma_addr);
eca18b23
MW		 473 iod->npages = -1;
474 return (total_len - length) + PAGE_SIZE;
b77954cb 475 }
eca18b23
MW		 476 list[0] = prp_list;
477 iod->first_dma = prp_dma;
e025344c
SMM		 478 cmd->prp2 = cpu_to_le64(prp_dma);
479 i = 0;
480 for (;;) {
7523d834 481 if (i == PAGE_SIZE / 8) {
e025344c 482 __le64 *old_prp_list = prp_list;
b77954cb 483 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 484 if (!prp_list)
485 return total_len - length;
486 list[iod->npages++] = prp_list;
7523d834
MW		 487 prp_list[0] = old_prp_list[i - 1];
488 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
489 i = 1;
e025344c
SMM		 490 }
491 prp_list[i++] = cpu_to_le64(dma_addr);
492 dma_len -= PAGE_SIZE;
493 dma_addr += PAGE_SIZE;
494 length -= PAGE_SIZE;
495 if (length <= 0)
496 break;
497 if (dma_len > 0)
498 continue;
499 BUG_ON(dma_len < 0);
500 sg = sg_next(sg);
501 dma_addr = sg_dma_address(sg);
502 dma_len = sg_dma_len(sg);
ff22b54f
MW		 503 }
504
eca18b23 505 return total_len;
ff22b54f
MW		 506}
507
427e9708 508static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
20d0189b 509 int len)
427e9708 510{
20d0189b
KO		 511 struct bio *split = bio_split(bio, len >> 9, GFP_ATOMIC, NULL);
512 if (!split)
427e9708
KB		 513 return -ENOMEM;
514
20d0189b
KO		 515 bio_chain(split, bio);
516
427e9708
KB		 517 if (bio_list_empty(&nvmeq->sq_cong))
518 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
20d0189b
KO		 519 bio_list_add(&nvmeq->sq_cong, split);
520 bio_list_add(&nvmeq->sq_cong, bio);
427e9708
KB		 521
522 return 0;
523}
524
1ad2f893
MW		 525/* NVMe scatterlists require no holes in the virtual address */
526#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
527 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
528
427e9708 529static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
b60503ba
MW		 530 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
531{
7988613b
KO		 532 struct bio_vec bvec, bvprv;
533 struct bvec_iter iter;
76830840 534 struct scatterlist *sg = NULL;
7988613b
KO		 535 int length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size;
536 int first = 1;
159b67d7
KB		 537
538 if (nvmeq->dev->stripe_size)
539 split_len = nvmeq->dev->stripe_size -
4f024f37
KO		 540 ((bio->bi_iter.bi_sector << 9) &
541 (nvmeq->dev->stripe_size - 1));
b60503ba 542
eca18b23 543 sg_init_table(iod->sg, psegs);
7988613b
KO		 544 bio_for_each_segment(bvec, bio, iter) {
545 if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) {
546 sg->length += bvec.bv_len;
76830840 547 } else {
7988613b
KO		 548 if (!first && BIOVEC_NOT_VIRT_MERGEABLE(&bvprv, &bvec))
549 return nvme_split_and_submit(bio, nvmeq,
20d0189b 550 length);
427e9708 551
eca18b23 552 sg = sg ? sg + 1 : iod->sg;
7988613b
KO		 553 sg_set_page(sg, bvec.bv_page,
554 bvec.bv_len, bvec.bv_offset);
76830840
MW		 555 nsegs++;
556 }
159b67d7 557
7988613b 558 if (split_len - length < bvec.bv_len)
20d0189b 559 return nvme_split_and_submit(bio, nvmeq, split_len);
7988613b 560 length += bvec.bv_len;
76830840 561 bvprv = bvec;
7988613b 562 first = 0;
b60503ba 563 }
eca18b23 564 iod->nents = nsegs;
76830840 565 sg_mark_end(sg);
427e9708 566 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
1ad2f893 567 return -ENOMEM;
427e9708 568
4f024f37 569 BUG_ON(length != bio->bi_iter.bi_size);
1ad2f893 570 return length;
b60503ba
MW		 571}
572
0e5e4f0e
KB		 573/*
574 * We reuse the small pool to allocate the 16-byte range here as it is not
575 * worth having a special pool for these or additional cases to handle freeing
576 * the iod.
577 */
578static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
579 struct bio *bio, struct nvme_iod *iod, int cmdid)
580{
581 struct nvme_dsm_range *range;
582 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
583
584 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
585 &iod->first_dma);
586 if (!range)
587 return -ENOMEM;
588
589 iod_list(iod)[0] = (__le64 *)range;
590 iod->npages = 0;
591
592 range->cattr = cpu_to_le32(0);
4f024f37
KO		 593 range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift);
594 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
0e5e4f0e
KB		 595
596 memset(cmnd, 0, sizeof(*cmnd));
597 cmnd->dsm.opcode = nvme_cmd_dsm;
598 cmnd->dsm.command_id = cmdid;
599 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
600 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
601 cmnd->dsm.nr = 0;
602 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
603
604 if (++nvmeq->sq_tail == nvmeq->q_depth)
605 nvmeq->sq_tail = 0;
606 writel(nvmeq->sq_tail, nvmeq->q_db);
607
608 return 0;
609}
610
00df5cb4
MW		 611static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
612 int cmdid)
613{
614 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
615
616 memset(cmnd, 0, sizeof(*cmnd));
617 cmnd->common.opcode = nvme_cmd_flush;
618 cmnd->common.command_id = cmdid;
619 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
620
621 if (++nvmeq->sq_tail == nvmeq->q_depth)
622 nvmeq->sq_tail = 0;
623 writel(nvmeq->sq_tail, nvmeq->q_db);
624
625 return 0;
626}
627
5d0f6131 628int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
00df5cb4
MW		 629{
630 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
ff976d72 631 special_completion, NVME_IO_TIMEOUT);
00df5cb4
MW		 632 if (unlikely(cmdid < 0))
633 return cmdid;
634
635 return nvme_submit_flush(nvmeq, ns, cmdid);
636}
637
184d2944
MW		 638/*
639 * Called with local interrupts disabled and the q_lock held. May not sleep.
640 */
b60503ba
MW		 641static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
642 struct bio *bio)
643{
ff22b54f 644 struct nvme_command *cmnd;
eca18b23 645 struct nvme_iod *iod;
b60503ba 646 enum dma_data_direction dma_dir;
1287dabd 647 int cmdid, length, result;
b60503ba
MW		 648 u16 control;
649 u32 dsmgmt;
b60503ba
MW		 650 int psegs = bio_phys_segments(ns->queue, bio);
651
00df5cb4
MW		 652 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
653 result = nvme_submit_flush_data(nvmeq, ns);
654 if (result)
655 return result;
656 }
657
1287dabd 658 result = -ENOMEM;
4f024f37 659 iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, GFP_ATOMIC);
eca18b23 660 if (!iod)
eeee3226 661 goto nomem;
eca18b23 662 iod->private = bio;
b60503ba 663
eeee3226 664 result = -EBUSY;
ff976d72 665 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 666 if (unlikely(cmdid < 0))
eca18b23 667 goto free_iod;
b60503ba 668
0e5e4f0e
KB		 669 if (bio->bi_rw & REQ_DISCARD) {
670 result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
671 if (result)
672 goto free_cmdid;
673 return result;
674 }
00df5cb4
MW		 675 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
676 return nvme_submit_flush(nvmeq, ns, cmdid);
677
b60503ba
MW		 678 control = 0;
679 if (bio->bi_rw & REQ_FUA)
680 control |= NVME_RW_FUA;
681 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
682 control |= NVME_RW_LR;
683
684 dsmgmt = 0;
685 if (bio->bi_rw & REQ_RAHEAD)
686 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
687
ff22b54f 688 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b60503ba 689
b8deb62c 690 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 691 if (bio_data_dir(bio)) {
ff22b54f 692 cmnd->rw.opcode = nvme_cmd_write;
b60503ba
MW		 693 dma_dir = DMA_TO_DEVICE;
694 } else {
ff22b54f 695 cmnd->rw.opcode = nvme_cmd_read;
b60503ba
MW		 696 dma_dir = DMA_FROM_DEVICE;
697 }
698
427e9708
KB		 699 result = nvme_map_bio(nvmeq, iod, bio, dma_dir, psegs);
700 if (result <= 0)
859361a2 701 goto free_cmdid;
1ad2f893 702 length = result;
b60503ba 703
ff22b54f
MW		 704 cmnd->rw.command_id = cmdid;
705 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
eca18b23
MW		 706 length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
707 GFP_ATOMIC);
4f024f37 708 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
1ad2f893 709 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
ff22b54f
MW		 710 cmnd->rw.control = cpu_to_le16(control);
711 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 712
6198221f 713 nvme_start_io_acct(bio);
b60503ba
MW		 714 if (++nvmeq->sq_tail == nvmeq->q_depth)
715 nvmeq->sq_tail = 0;
7547881d 716 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 717
1974b1ae
MW		 718 return 0;
719
859361a2
KB		 720 free_cmdid:
721 free_cmdid(nvmeq, cmdid, NULL);
eca18b23
MW		 722 free_iod:
723 nvme_free_iod(nvmeq->dev, iod);
eeee3226
MW		 724 nomem:
725 return result;
b60503ba
MW		 726}
727
e9539f47 728static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 729{
82123460 730 u16 head, phase;
b60503ba 731
b60503ba 732 head = nvmeq->cq_head;
82123460 733 phase = nvmeq->cq_phase;
b60503ba
MW		 734
735 for (;;) {
c2f5b650
MW		 736 void *ctx;
737 nvme_completion_fn fn;
b60503ba 738 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 739 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 740 break;
741 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
742 if (++head == nvmeq->q_depth) {
743 head = 0;
82123460 744 phase = !phase;
b60503ba
MW		 745 }
746
c2f5b650 747 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
5c1281a3 748 fn(nvmeq->dev, ctx, &cqe);
b60503ba
MW		 749 }
750
751 /* If the controller ignores the cq head doorbell and continuously
752 * writes to the queue, it is theoretically possible to wrap around
753 * the queue twice and mistakenly return IRQ_NONE. Linux only
754 * requires that 0.1% of your interrupts are handled, so this isn't
755 * a big problem.
756 */
82123460 757 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 758 return 0;
b60503ba 759
b80d5ccc 760 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 761 nvmeq->cq_head = head;
82123460 762 nvmeq->cq_phase = phase;
b60503ba 763
e9539f47
MW		 764 nvmeq->cqe_seen = 1;
765 return 1;
b60503ba
MW		 766}
767
7d822457
MW		 768static void nvme_make_request(struct request_queue *q, struct bio *bio)
769{
770 struct nvme_ns *ns = q->queuedata;
771 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
772 int result = -EBUSY;
773
cd638946
KB		 774 if (!nvmeq) {
775 put_nvmeq(NULL);
776 bio_endio(bio, -EIO);
777 return;
778 }
779
7d822457 780 spin_lock_irq(&nvmeq->q_lock);
22404274 781 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
7d822457
MW		 782 result = nvme_submit_bio_queue(nvmeq, ns, bio);
783 if (unlikely(result)) {
784 if (bio_list_empty(&nvmeq->sq_cong))
785 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
786 bio_list_add(&nvmeq->sq_cong, bio);
787 }
788
789 nvme_process_cq(nvmeq);
790 spin_unlock_irq(&nvmeq->q_lock);
791 put_nvmeq(nvmeq);
792}
793
b60503ba 794static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 795{
796 irqreturn_t result;
797 struct nvme_queue *nvmeq = data;
798 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 799 nvme_process_cq(nvmeq);
800 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
801 nvmeq->cqe_seen = 0;
58ffacb5
MW		 802 spin_unlock(&nvmeq->q_lock);
803 return result;
804}
805
806static irqreturn_t nvme_irq_check(int irq, void *data)
807{
808 struct nvme_queue *nvmeq = data;
809 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
810 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
811 return IRQ_NONE;
812 return IRQ_WAKE_THREAD;
813}
814
3c0cf138
MW		 815static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
816{
817 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 818 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW		 819 spin_unlock_irq(&nvmeq->q_lock);
820}
821
c2f5b650
MW		 822struct sync_cmd_info {
823 struct task_struct *task;
824 u32 result;
825 int status;
826};
827
5c1281a3 828static void sync_completion(struct nvme_dev *dev, void *ctx,
c2f5b650
MW		 829 struct nvme_completion *cqe)
830{
831 struct sync_cmd_info *cmdinfo = ctx;
832 cmdinfo->result = le32_to_cpup(&cqe->result);
833 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
834 wake_up_process(cmdinfo->task);
835}
836
b60503ba
MW		 837/*
838 * Returns 0 on success. If the result is negative, it's a Linux error code;
839 * if the result is positive, it's an NVM Express status code
840 */
4f5099af
KB		 841static int nvme_submit_sync_cmd(struct nvme_dev *dev, int q_idx,
842 struct nvme_command *cmd,
5d0f6131 843 u32 *result, unsigned timeout)
b60503ba 844{
4f5099af 845 int cmdid, ret;
b60503ba 846 struct sync_cmd_info cmdinfo;
4f5099af
KB		 847 struct nvme_queue *nvmeq;
848
849 nvmeq = lock_nvmeq(dev, q_idx);
850 if (!nvmeq) {
851 unlock_nvmeq(nvmeq);
852 return -ENODEV;
853 }
b60503ba
MW		 854
855 cmdinfo.task = current;
856 cmdinfo.status = -EINTR;
857
4f5099af
KB		 858 cmdid = alloc_cmdid(nvmeq, &cmdinfo, sync_completion, timeout);
859 if (cmdid < 0) {
860 unlock_nvmeq(nvmeq);
b60503ba 861 return cmdid;
4f5099af 862 }
b60503ba
MW		 863 cmd->common.command_id = cmdid;
864
3c0cf138 865 set_current_state(TASK_KILLABLE);
4f5099af
KB		 866 ret = nvme_submit_cmd(nvmeq, cmd);
867 if (ret) {
868 free_cmdid(nvmeq, cmdid, NULL);
869 unlock_nvmeq(nvmeq);
870 set_current_state(TASK_RUNNING);
871 return ret;
872 }
873 unlock_nvmeq(nvmeq);
78f8d257 874 schedule_timeout(timeout);
b60503ba 875
3c0cf138 876 if (cmdinfo.status == -EINTR) {
4f5099af
KB		 877 nvmeq = lock_nvmeq(dev, q_idx);
878 if (nvmeq)
879 nvme_abort_command(nvmeq, cmdid);
880 unlock_nvmeq(nvmeq);
3c0cf138
MW		 881 return -EINTR;
882 }
883
b60503ba
MW		 884 if (result)
885 *result = cmdinfo.result;
886
887 return cmdinfo.status;
888}
889
4d115420
KB		 890static int nvme_submit_async_cmd(struct nvme_queue *nvmeq,
891 struct nvme_command *cmd,
892 struct async_cmd_info *cmdinfo, unsigned timeout)
893{
894 int cmdid;
895
896 cmdid = alloc_cmdid_killable(nvmeq, cmdinfo, async_completion, timeout);
897 if (cmdid < 0)
898 return cmdid;
899 cmdinfo->status = -EINTR;
900 cmd->common.command_id = cmdid;
4f5099af 901 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 902}
903
5d0f6131 904int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
b60503ba
MW		 905 u32 *result)
906{
4f5099af
KB		 907 return nvme_submit_sync_cmd(dev, 0, cmd, result, ADMIN_TIMEOUT);
908}
909
910int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
911 u32 *result)
912{
913 return nvme_submit_sync_cmd(dev, smp_processor_id() + 1, cmd, result,
914 NVME_IO_TIMEOUT);
b60503ba
MW		 915}
916
4d115420
KB		 917static int nvme_submit_admin_cmd_async(struct nvme_dev *dev,
918 struct nvme_command *cmd, struct async_cmd_info *cmdinfo)
919{
5a92e700 920 return nvme_submit_async_cmd(raw_nvmeq(dev, 0), cmd, cmdinfo,
4d115420
KB		 921 ADMIN_TIMEOUT);
922}
923
b60503ba
MW		 924static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
925{
926 int status;
927 struct nvme_command c;
928
929 memset(&c, 0, sizeof(c));
930 c.delete_queue.opcode = opcode;
931 c.delete_queue.qid = cpu_to_le16(id);
932
933 status = nvme_submit_admin_cmd(dev, &c, NULL);
934 if (status)
935 return -EIO;
936 return 0;
937}
938
939static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
940 struct nvme_queue *nvmeq)
941{
942 int status;
943 struct nvme_command c;
944 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
945
946 memset(&c, 0, sizeof(c));
947 c.create_cq.opcode = nvme_admin_create_cq;
948 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
949 c.create_cq.cqid = cpu_to_le16(qid);
950 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
951 c.create_cq.cq_flags = cpu_to_le16(flags);
952 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
953
954 status = nvme_submit_admin_cmd(dev, &c, NULL);
955 if (status)
956 return -EIO;
957 return 0;
958}
959
960static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
961 struct nvme_queue *nvmeq)
962{
963 int status;
964 struct nvme_command c;
965 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
966
967 memset(&c, 0, sizeof(c));
968 c.create_sq.opcode = nvme_admin_create_sq;
969 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
970 c.create_sq.sqid = cpu_to_le16(qid);
971 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
972 c.create_sq.sq_flags = cpu_to_le16(flags);
973 c.create_sq.cqid = cpu_to_le16(qid);
974
975 status = nvme_submit_admin_cmd(dev, &c, NULL);
976 if (status)
977 return -EIO;
978 return 0;
979}
980
981static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
982{
983 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
984}
985
986static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
987{
988 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
989}
990
5d0f6131 991int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 992 dma_addr_t dma_addr)
993{
994 struct nvme_command c;
995
996 memset(&c, 0, sizeof(c));
997 c.identify.opcode = nvme_admin_identify;
998 c.identify.nsid = cpu_to_le32(nsid);
999 c.identify.prp1 = cpu_to_le64(dma_addr);
1000 c.identify.cns = cpu_to_le32(cns);
1001
1002 return nvme_submit_admin_cmd(dev, &c, NULL);
1003}
1004
5d0f6131 1005int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1006 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1007{
1008 struct nvme_command c;
1009
1010 memset(&c, 0, sizeof(c));
1011 c.features.opcode = nvme_admin_get_features;
a42cecce 1012 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1013 c.features.prp1 = cpu_to_le64(dma_addr);
1014 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1015
08df1e05 1016 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 1017}
1018
5d0f6131
VV		 1019int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1020 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1021{
1022 struct nvme_command c;
1023
1024 memset(&c, 0, sizeof(c));
1025 c.features.opcode = nvme_admin_set_features;
1026 c.features.prp1 = cpu_to_le64(dma_addr);
1027 c.features.fid = cpu_to_le32(fid);
1028 c.features.dword11 = cpu_to_le32(dword11);
1029
bc5fc7e4
MW		 1030 return nvme_submit_admin_cmd(dev, &c, result);
1031}
1032
c30341dc
KB		 1033/**
1034 * nvme_abort_cmd - Attempt aborting a command
1035 * @cmdid: Command id of a timed out IO
1036 * @queue: The queue with timed out IO
1037 *
1038 * Schedule controller reset if the command was already aborted once before and
1039 * still hasn't been returned to the driver, or if this is the admin queue.
1040 */
1041static void nvme_abort_cmd(int cmdid, struct nvme_queue *nvmeq)
1042{
1043 int a_cmdid;
1044 struct nvme_command cmd;
1045 struct nvme_dev *dev = nvmeq->dev;
1046 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
5a92e700 1047 struct nvme_queue *adminq;
c30341dc
KB		 1048
1049 if (!nvmeq->qid || info[cmdid].aborted) {
1050 if (work_busy(&dev->reset_work))
1051 return;
1052 list_del_init(&dev->node);
1053 dev_warn(&dev->pci_dev->dev,
1054 "I/O %d QID %d timeout, reset controller\n", cmdid,
1055 nvmeq->qid);
bdfd70fd 1056 PREPARE_WORK(&dev->reset_work, nvme_reset_failed_dev);
c30341dc
KB		 1057 queue_work(nvme_workq, &dev->reset_work);
1058 return;
1059 }
1060
1061 if (!dev->abort_limit)
1062 return;
1063
5a92e700
KB		 1064 adminq = rcu_dereference(dev->queues[0]);
1065 a_cmdid = alloc_cmdid(adminq, CMD_CTX_ABORT, special_completion,
c30341dc
KB		 1066 ADMIN_TIMEOUT);
1067 if (a_cmdid < 0)
1068 return;
1069
1070 memset(&cmd, 0, sizeof(cmd));
1071 cmd.abort.opcode = nvme_admin_abort_cmd;
1072 cmd.abort.cid = cmdid;
1073 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1074 cmd.abort.command_id = a_cmdid;
1075
1076 --dev->abort_limit;
1077 info[cmdid].aborted = 1;
1078 info[cmdid].timeout = jiffies + ADMIN_TIMEOUT;
1079
1080 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", cmdid,
1081 nvmeq->qid);
5a92e700 1082 nvme_submit_cmd(adminq, &cmd);
c30341dc
KB		 1083}
1084
a09115b2
MW		 1085/**
1086 * nvme_cancel_ios - Cancel outstanding I/Os
1087 * @queue: The queue to cancel I/Os on
1088 * @timeout: True to only cancel I/Os which have timed out
1089 */
1090static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1091{
1092 int depth = nvmeq->q_depth - 1;
1093 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1094 unsigned long now = jiffies;
1095 int cmdid;
1096
1097 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1098 void *ctx;
1099 nvme_completion_fn fn;
1100 static struct nvme_completion cqe = {
af2d9ca7 1101 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
a09115b2
MW		 1102 };
1103
1104 if (timeout && !time_after(now, info[cmdid].timeout))
1105 continue;
053ab702
KB		 1106 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1107 continue;
c30341dc
KB		 1108 if (timeout && nvmeq->dev->initialized) {
1109 nvme_abort_cmd(cmdid, nvmeq);
1110 continue;
1111 }
1112 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", cmdid,
1113 nvmeq->qid);
a09115b2
MW		 1114 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
1115 fn(nvmeq->dev, ctx, &cqe);
1116 }
1117}
1118
5a92e700 1119static void nvme_free_queue(struct rcu_head *r)
9e866774 1120{
5a92e700
KB		 1121 struct nvme_queue *nvmeq = container_of(r, struct nvme_queue, r_head);
1122
22404274
KB		 1123 spin_lock_irq(&nvmeq->q_lock);
1124 while (bio_list_peek(&nvmeq->sq_cong)) {
1125 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1126 bio_endio(bio, -EIO);
1127 }
1128 spin_unlock_irq(&nvmeq->q_lock);
1129
9e866774
MW		 1130 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1131 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1132 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1133 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
42f61420
KB		 1134 if (nvmeq->qid)
1135 free_cpumask_var(nvmeq->cpu_mask);
9e866774
MW		 1136 kfree(nvmeq);
1137}
1138
a1a5ef99 1139static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1140{
1141 int i;
1142
a1a5ef99 1143 for (i = dev->queue_count - 1; i >= lowest; i--) {
5a92e700
KB		 1144 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
1145 rcu_assign_pointer(dev->queues[i], NULL);
1146 call_rcu(&nvmeq->r_head, nvme_free_queue);
22404274 1147 dev->queue_count--;
22404274
KB		 1148 }
1149}
1150
4d115420
KB		 1151/**
1152 * nvme_suspend_queue - put queue into suspended state
1153 * @nvmeq - queue to suspend
1154 *
1155 * Returns 1 if already suspended, 0 otherwise.
1156 */
1157static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1158{
4d115420 1159 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1160
a09115b2 1161 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1162 if (nvmeq->q_suspended) {
1163 spin_unlock_irq(&nvmeq->q_lock);
4d115420 1164 return 1;
3295874b 1165 }
22404274 1166 nvmeq->q_suspended = 1;
42f61420 1167 nvmeq->dev->online_queues--;
a09115b2
MW		 1168 spin_unlock_irq(&nvmeq->q_lock);
1169
aba2080f
MW		 1170 irq_set_affinity_hint(vector, NULL);
1171 free_irq(vector, nvmeq);
b60503ba 1172
4d115420
KB		 1173 return 0;
1174}
b60503ba 1175
4d115420
KB		 1176static void nvme_clear_queue(struct nvme_queue *nvmeq)
1177{
22404274
KB		 1178 spin_lock_irq(&nvmeq->q_lock);
1179 nvme_process_cq(nvmeq);
1180 nvme_cancel_ios(nvmeq, false);
1181 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1182}
1183
4d115420
KB		 1184static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1185{
5a92e700 1186 struct nvme_queue *nvmeq = raw_nvmeq(dev, qid);
4d115420
KB		 1187
1188 if (!nvmeq)
1189 return;
1190 if (nvme_suspend_queue(nvmeq))
1191 return;
1192
0e53d180
KB		 1193 /* Don't tell the adapter to delete the admin queue.
1194 * Don't tell a removed adapter to delete IO queues. */
1195 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1196 adapter_delete_sq(dev, qid);
1197 adapter_delete_cq(dev, qid);
1198 }
4d115420 1199 nvme_clear_queue(nvmeq);
b60503ba
MW		 1200}
1201
1202static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1203 int depth, int vector)
1204{
1205 struct device *dmadev = &dev->pci_dev->dev;
22404274 1206 unsigned extra = nvme_queue_extra(depth);
b60503ba
MW		 1207 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1208 if (!nvmeq)
1209 return NULL;
1210
1211 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1212 &nvmeq->cq_dma_addr, GFP_KERNEL);
1213 if (!nvmeq->cqes)
1214 goto free_nvmeq;
1215 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1216
1217 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1218 &nvmeq->sq_dma_addr, GFP_KERNEL);
1219 if (!nvmeq->sq_cmds)
1220 goto free_cqdma;
1221
42f61420
KB		 1222 if (qid && !zalloc_cpumask_var(&nvmeq->cpu_mask, GFP_KERNEL))
1223 goto free_sqdma;
1224
b60503ba 1225 nvmeq->q_dmadev = dmadev;
091b6092 1226 nvmeq->dev = dev;
3193f07b
MW		 1227 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1228 dev->instance, qid);
b60503ba
MW		 1229 spin_lock_init(&nvmeq->q_lock);
1230 nvmeq->cq_head = 0;
82123460 1231 nvmeq->cq_phase = 1;
b60503ba 1232 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1233 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1234 bio_list_init(&nvmeq->sq_cong);
b80d5ccc 1235 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW		 1236 nvmeq->q_depth = depth;
1237 nvmeq->cq_vector = vector;
c30341dc 1238 nvmeq->qid = qid;
22404274
KB		 1239 nvmeq->q_suspended = 1;
1240 dev->queue_count++;
5a92e700 1241 rcu_assign_pointer(dev->queues[qid], nvmeq);
b60503ba
MW		 1242
1243 return nvmeq;
1244
42f61420
KB		 1245 free_sqdma:
1246 dma_free_coherent(dmadev, SQ_SIZE(depth), (void *)nvmeq->sq_cmds,
1247 nvmeq->sq_dma_addr);
b60503ba 1248 free_cqdma:
68b8eca5 1249 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1250 nvmeq->cq_dma_addr);
1251 free_nvmeq:
1252 kfree(nvmeq);
1253 return NULL;
1254}
1255
3001082c
MW		 1256static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1257 const char *name)
1258{
58ffacb5
MW		 1259 if (use_threaded_interrupts)
1260 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1261 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1262 name, nvmeq);
3001082c 1263 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1264 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1265}
1266
22404274 1267static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1268{
22404274
KB		 1269 struct nvme_dev *dev = nvmeq->dev;
1270 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
b60503ba 1271
22404274
KB		 1272 nvmeq->sq_tail = 0;
1273 nvmeq->cq_head = 0;
1274 nvmeq->cq_phase = 1;
b80d5ccc 1275 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274
KB		 1276 memset(nvmeq->cmdid_data, 0, extra);
1277 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1278 nvme_cancel_ios(nvmeq, false);
1279 nvmeq->q_suspended = 0;
42f61420 1280 dev->online_queues++;
22404274
KB		 1281}
1282
1283static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1284{
1285 struct nvme_dev *dev = nvmeq->dev;
1286 int result;
3f85d50b 1287
b60503ba
MW		 1288 result = adapter_alloc_cq(dev, qid, nvmeq);
1289 if (result < 0)
22404274 1290 return result;
b60503ba
MW		 1291
1292 result = adapter_alloc_sq(dev, qid, nvmeq);
1293 if (result < 0)
1294 goto release_cq;
1295
3193f07b 1296 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1297 if (result < 0)
1298 goto release_sq;
1299
0a8d44cb 1300 spin_lock_irq(&nvmeq->q_lock);
22404274 1301 nvme_init_queue(nvmeq, qid);
0a8d44cb 1302 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1303
1304 return result;
b60503ba
MW		 1305
1306 release_sq:
1307 adapter_delete_sq(dev, qid);
1308 release_cq:
1309 adapter_delete_cq(dev, qid);
22404274 1310 return result;
b60503ba
MW		 1311}
1312
ba47e386
MW		 1313static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1314{
1315 unsigned long timeout;
1316 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1317
1318 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1319
1320 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1321 msleep(100);
1322 if (fatal_signal_pending(current))
1323 return -EINTR;
1324 if (time_after(jiffies, timeout)) {
1325 dev_err(&dev->pci_dev->dev,
1326 "Device not ready; aborting initialisation\n");
1327 return -ENODEV;
1328 }
1329 }
1330
1331 return 0;
1332}
1333
1334/*
1335 * If the device has been passed off to us in an enabled state, just clear
1336 * the enabled bit. The spec says we should set the 'shutdown notification
1337 * bits', but doing so may cause the device to complete commands to the
1338 * admin queue ... and we don't know what memory that might be pointing at!
1339 */
1340static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1341{
44af146a
MW		 1342 u32 cc = readl(&dev->bar->cc);
1343
1344 if (cc & NVME_CC_ENABLE)
1345 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
ba47e386
MW		 1346 return nvme_wait_ready(dev, cap, false);
1347}
1348
1349static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1350{
1351 return nvme_wait_ready(dev, cap, true);
1352}
1353
1894d8f1
KB		 1354static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1355{
1356 unsigned long timeout;
1357 u32 cc;
1358
1359 cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
1360 writel(cc, &dev->bar->cc);
1361
1362 timeout = 2 * HZ + jiffies;
1363 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1364 NVME_CSTS_SHST_CMPLT) {
1365 msleep(100);
1366 if (fatal_signal_pending(current))
1367 return -EINTR;
1368 if (time_after(jiffies, timeout)) {
1369 dev_err(&dev->pci_dev->dev,
1370 "Device shutdown incomplete; abort shutdown\n");
1371 return -ENODEV;
1372 }
1373 }
1374
1375 return 0;
1376}
1377
8d85fce7 1378static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1379{
ba47e386 1380 int result;
b60503ba 1381 u32 aqa;
ba47e386 1382 u64 cap = readq(&dev->bar->cap);
b60503ba
MW		 1383 struct nvme_queue *nvmeq;
1384
ba47e386
MW		 1385 result = nvme_disable_ctrl(dev, cap);
1386 if (result < 0)
1387 return result;
b60503ba 1388
5a92e700 1389 nvmeq = raw_nvmeq(dev, 0);
cd638946
KB		 1390 if (!nvmeq) {
1391 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1392 if (!nvmeq)
1393 return -ENOMEM;
cd638946 1394 }
b60503ba
MW		 1395
1396 aqa = nvmeq->q_depth - 1;
1397 aqa |= aqa << 16;
1398
1399 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1400 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1401 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1402 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1403
1404 writel(aqa, &dev->bar->aqa);
1405 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1406 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1407 writel(dev->ctrl_config, &dev->bar->cc);
1408
ba47e386 1409 result = nvme_enable_ctrl(dev, cap);
025c557a 1410 if (result)
cd638946 1411 return result;
9e866774 1412
3193f07b 1413 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1414 if (result)
cd638946 1415 return result;
025c557a 1416
0a8d44cb 1417 spin_lock_irq(&nvmeq->q_lock);
22404274 1418 nvme_init_queue(nvmeq, 0);
0a8d44cb 1419 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1420 return result;
1421}
1422
5d0f6131 1423struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1424 unsigned long addr, unsigned length)
b60503ba 1425{
36c14ed9 1426 int i, err, count, nents, offset;
7fc3cdab
MW		 1427 struct scatterlist *sg;
1428 struct page **pages;
eca18b23 1429 struct nvme_iod *iod;
36c14ed9
MW		 1430
1431 if (addr & 3)
eca18b23 1432 return ERR_PTR(-EINVAL);
5460fc03 1433 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1434 return ERR_PTR(-EINVAL);
7fc3cdab 1435
36c14ed9 1436 offset = offset_in_page(addr);
7fc3cdab
MW		 1437 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1438 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1439 if (!pages)
1440 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1441
1442 err = get_user_pages_fast(addr, count, 1, pages);
1443 if (err < count) {
1444 count = err;
1445 err = -EFAULT;
1446 goto put_pages;
1447 }
7fc3cdab 1448
eca18b23
MW		 1449 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1450 sg = iod->sg;
36c14ed9 1451 sg_init_table(sg, count);
d0ba1e49
MW		 1452 for (i = 0; i < count; i++) {
1453 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1454 min_t(unsigned, length, PAGE_SIZE - offset),
1455 offset);
d0ba1e49
MW		 1456 length -= (PAGE_SIZE - offset);
1457 offset = 0;
7fc3cdab 1458 }
fe304c43 1459 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1460 iod->nents = count;
7fc3cdab
MW		 1461
1462 err = -ENOMEM;
1463 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1464 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1465 if (!nents)
eca18b23 1466 goto free_iod;
b60503ba 1467
7fc3cdab 1468 kfree(pages);
eca18b23 1469 return iod;
b60503ba 1470
eca18b23
MW		 1471 free_iod:
1472 kfree(iod);
7fc3cdab
MW		 1473 put_pages:
1474 for (i = 0; i < count; i++)
1475 put_page(pages[i]);
1476 kfree(pages);
eca18b23 1477 return ERR_PTR(err);
7fc3cdab 1478}
b60503ba 1479
5d0f6131 1480void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1481 struct nvme_iod *iod)
7fc3cdab 1482{
1c2ad9fa 1483 int i;
b60503ba 1484
1c2ad9fa
MW		 1485 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1486 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1487
1c2ad9fa
MW		 1488 for (i = 0; i < iod->nents; i++)
1489 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1490}
b60503ba 1491
a53295b6
MW		 1492static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1493{
1494 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1495 struct nvme_user_io io;
1496 struct nvme_command c;
f410c680
KB		 1497 unsigned length, meta_len;
1498 int status, i;
1499 struct nvme_iod *iod, *meta_iod = NULL;
1500 dma_addr_t meta_dma_addr;
1501 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1502
1503 if (copy_from_user(&io, uio, sizeof(io)))
1504 return -EFAULT;
6c7d4945 1505 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1506 meta_len = (io.nblocks + 1) * ns->ms;
1507
1508 if (meta_len && ((io.metadata & 3) || !io.metadata))
1509 return -EINVAL;
6c7d4945
MW		 1510
1511 switch (io.opcode) {
1512 case nvme_cmd_write:
1513 case nvme_cmd_read:
6bbf1acd 1514 case nvme_cmd_compare:
eca18b23 1515 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1516 break;
6c7d4945 1517 default:
6bbf1acd 1518 return -EINVAL;
6c7d4945
MW		 1519 }
1520
eca18b23
MW		 1521 if (IS_ERR(iod))
1522 return PTR_ERR(iod);
a53295b6
MW		 1523
1524 memset(&c, 0, sizeof(c));
1525 c.rw.opcode = io.opcode;
1526 c.rw.flags = io.flags;
6c7d4945 1527 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1528 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1529 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1530 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1531 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1532 c.rw.reftag = cpu_to_le32(io.reftag);
1533 c.rw.apptag = cpu_to_le16(io.apptag);
1534 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1535
1536 if (meta_len) {
1b56749e
KB		 1537 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1538 meta_len);
f410c680
KB		 1539 if (IS_ERR(meta_iod)) {
1540 status = PTR_ERR(meta_iod);
1541 meta_iod = NULL;
1542 goto unmap;
1543 }
1544
1545 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1546 &meta_dma_addr, GFP_KERNEL);
1547 if (!meta_mem) {
1548 status = -ENOMEM;
1549 goto unmap;
1550 }
1551
1552 if (io.opcode & 1) {
1553 int meta_offset = 0;
1554
1555 for (i = 0; i < meta_iod->nents; i++) {
1556 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1557 meta_iod->sg[i].offset;
1558 memcpy(meta_mem + meta_offset, meta,
1559 meta_iod->sg[i].length);
1560 kunmap_atomic(meta);
1561 meta_offset += meta_iod->sg[i].length;
1562 }
1563 }
1564
1565 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1566 }
1567
eca18b23 1568 length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
a53295b6 1569
b77954cb
MW		 1570 if (length != (io.nblocks + 1) << ns->lba_shift)
1571 status = -ENOMEM;
1572 else
4f5099af 1573 status = nvme_submit_io_cmd(dev, &c, NULL);
a53295b6 1574
f410c680
KB		 1575 if (meta_len) {
1576 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1577 int meta_offset = 0;
1578
1579 for (i = 0; i < meta_iod->nents; i++) {
1580 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1581 meta_iod->sg[i].offset;
1582 memcpy(meta, meta_mem + meta_offset,
1583 meta_iod->sg[i].length);
1584 kunmap_atomic(meta);
1585 meta_offset += meta_iod->sg[i].length;
1586 }
1587 }
1588
1589 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1590 meta_dma_addr);
1591 }
1592
1593 unmap:
1c2ad9fa 1594 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1595 nvme_free_iod(dev, iod);
f410c680
KB		 1596
1597 if (meta_iod) {
1598 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1599 nvme_free_iod(dev, meta_iod);
1600 }
1601
a53295b6
MW		 1602 return status;
1603}
1604
50af8bae 1605static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1606 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1607{
6bbf1acd 1608 struct nvme_admin_cmd cmd;
6ee44cdc 1609 struct nvme_command c;
eca18b23 1610 int status, length;
c7d36ab8 1611 struct nvme_iod *uninitialized_var(iod);
94f370ca 1612 unsigned timeout;
6ee44cdc 1613
6bbf1acd
MW		 1614 if (!capable(CAP_SYS_ADMIN))
1615 return -EACCES;
1616 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1617 return -EFAULT;
6ee44cdc
MW		 1618
1619 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1620 c.common.opcode = cmd.opcode;
1621 c.common.flags = cmd.flags;
1622 c.common.nsid = cpu_to_le32(cmd.nsid);
1623 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1624 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1625 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1626 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1627 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1628 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1629 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1630 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1631
1632 length = cmd.data_len;
1633 if (cmd.data_len) {
49742188
MW		 1634 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1635 length);
eca18b23
MW		 1636 if (IS_ERR(iod))
1637 return PTR_ERR(iod);
1638 length = nvme_setup_prps(dev, &c.common, iod, length,
1639 GFP_KERNEL);
6bbf1acd
MW		 1640 }
1641
94f370ca
KB		 1642 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1643 ADMIN_TIMEOUT;
6bbf1acd 1644 if (length != cmd.data_len)
b77954cb
MW		 1645 status = -ENOMEM;
1646 else
4f5099af 1647 status = nvme_submit_sync_cmd(dev, 0, &c, &cmd.result, timeout);
eca18b23 1648
6bbf1acd 1649 if (cmd.data_len) {
1c2ad9fa 1650 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1651 nvme_free_iod(dev, iod);
6bbf1acd 1652 }
f4f117f6 1653
cf90bc48 1654 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1655 sizeof(cmd.result)))
1656 status = -EFAULT;
1657
6ee44cdc
MW		 1658 return status;
1659}
1660
b60503ba
MW		 1661static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1662 unsigned long arg)
1663{
1664 struct nvme_ns *ns = bdev->bd_disk->private_data;
1665
1666 switch (cmd) {
6bbf1acd 1667 case NVME_IOCTL_ID:
c3bfe717 1668 force_successful_syscall_return();
6bbf1acd
MW		 1669 return ns->ns_id;
1670 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1671 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW		 1672 case NVME_IOCTL_SUBMIT_IO:
1673 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1674 case SG_GET_VERSION_NUM:
1675 return nvme_sg_get_version_num((void __user *)arg);
1676 case SG_IO:
1677 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1678 default:
1679 return -ENOTTY;
1680 }
1681}
1682
320a3827
KB		 1683#ifdef CONFIG_COMPAT
1684static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1685 unsigned int cmd, unsigned long arg)
1686{
1687 struct nvme_ns *ns = bdev->bd_disk->private_data;
1688
1689 switch (cmd) {
1690 case SG_IO:
1691 return nvme_sg_io32(ns, arg);
1692 }
1693 return nvme_ioctl(bdev, mode, cmd, arg);
1694}
1695#else
1696#define nvme_compat_ioctl NULL
1697#endif
1698
9ac27090
KB		 1699static int nvme_open(struct block_device *bdev, fmode_t mode)
1700{
1701 struct nvme_ns *ns = bdev->bd_disk->private_data;
1702 struct nvme_dev *dev = ns->dev;
1703
1704 kref_get(&dev->kref);
1705 return 0;
1706}
1707
1708static void nvme_free_dev(struct kref *kref);
1709
1710static void nvme_release(struct gendisk *disk, fmode_t mode)
1711{
1712 struct nvme_ns *ns = disk->private_data;
1713 struct nvme_dev *dev = ns->dev;
1714
1715 kref_put(&dev->kref, nvme_free_dev);
1716}
1717
4cc09e2d
KB		 1718static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1719{
1720 /* some standard values */
1721 geo->heads = 1 << 6;
1722 geo->sectors = 1 << 5;
1723 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1724 return 0;
1725}
1726
b60503ba
MW		 1727static const struct block_device_operations nvme_fops = {
1728 .owner = THIS_MODULE,
1729 .ioctl = nvme_ioctl,
320a3827 1730 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1731 .open = nvme_open,
1732 .release = nvme_release,
4cc09e2d 1733 .getgeo = nvme_getgeo,
b60503ba
MW		 1734};
1735
1fa6aead
MW		 1736static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1737{
1738 while (bio_list_peek(&nvmeq->sq_cong)) {
1739 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1740 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
427e9708
KB		 1741
1742 if (bio_list_empty(&nvmeq->sq_cong))
1743 remove_wait_queue(&nvmeq->sq_full,
1744 &nvmeq->sq_cong_wait);
1fa6aead 1745 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
427e9708
KB		 1746 if (bio_list_empty(&nvmeq->sq_cong))
1747 add_wait_queue(&nvmeq->sq_full,
1748 &nvmeq->sq_cong_wait);
1fa6aead
MW		 1749 bio_list_add_head(&nvmeq->sq_cong, bio);
1750 break;
1751 }
1752 }
1753}
1754
1755static int nvme_kthread(void *data)
1756{
d4b4ff8e 1757 struct nvme_dev *dev, *next;
1fa6aead
MW		 1758
1759 while (!kthread_should_stop()) {
564a232c 1760 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1761 spin_lock(&dev_list_lock);
d4b4ff8e 1762 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1763 int i;
d4b4ff8e
KB		 1764 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1765 dev->initialized) {
1766 if (work_busy(&dev->reset_work))
1767 continue;
1768 list_del_init(&dev->node);
1769 dev_warn(&dev->pci_dev->dev,
1770 "Failed status, reset controller\n");
bdfd70fd 1771 PREPARE_WORK(&dev->reset_work,
d4b4ff8e
KB		 1772 nvme_reset_failed_dev);
1773 queue_work(nvme_workq, &dev->reset_work);
1774 continue;
1775 }
5a92e700 1776 rcu_read_lock();
1fa6aead 1777 for (i = 0; i < dev->queue_count; i++) {
5a92e700
KB		 1778 struct nvme_queue *nvmeq =
1779 rcu_dereference(dev->queues[i]);
740216fc
MW		 1780 if (!nvmeq)
1781 continue;
1fa6aead 1782 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1783 if (nvmeq->q_suspended)
1784 goto unlock;
bc57a0f7 1785 nvme_process_cq(nvmeq);
a09115b2 1786 nvme_cancel_ios(nvmeq, true);
1fa6aead 1787 nvme_resubmit_bios(nvmeq);
22404274 1788 unlock:
1fa6aead
MW		 1789 spin_unlock_irq(&nvmeq->q_lock);
1790 }
5a92e700 1791 rcu_read_unlock();
1fa6aead
MW		 1792 }
1793 spin_unlock(&dev_list_lock);
acb7aa0d 1794 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1795 }
1796 return 0;
1797}
1798
0e5e4f0e
KB		 1799static void nvme_config_discard(struct nvme_ns *ns)
1800{
1801 u32 logical_block_size = queue_logical_block_size(ns->queue);
1802 ns->queue->limits.discard_zeroes_data = 0;
1803 ns->queue->limits.discard_alignment = logical_block_size;
1804 ns->queue->limits.discard_granularity = logical_block_size;
1805 ns->queue->limits.max_discard_sectors = 0xffffffff;
1806 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1807}
1808
c3bfe717 1809static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1810 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1811{
1812 struct nvme_ns *ns;
1813 struct gendisk *disk;
1814 int lbaf;
1815
1816 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1817 return NULL;
1818
1819 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1820 if (!ns)
1821 return NULL;
1822 ns->queue = blk_alloc_queue(GFP_KERNEL);
1823 if (!ns->queue)
1824 goto out_free_ns;
4eeb9215
MW		 1825 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1826 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1827 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 1828 blk_queue_make_request(ns->queue, nvme_make_request);
1829 ns->dev = dev;
1830 ns->queue->queuedata = ns;
1831
469071a3 1832 disk = alloc_disk(0);
b60503ba
MW		 1833 if (!disk)
1834 goto out_free_queue;
5aff9382 1835 ns->ns_id = nsid;
b60503ba
MW		 1836 ns->disk = disk;
1837 lbaf = id->flbas & 0xf;
1838 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1839 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1840 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1841 if (dev->max_hw_sectors)
1842 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
b60503ba
MW		 1843
1844 disk->major = nvme_major;
469071a3 1845 disk->first_minor = 0;
b60503ba
MW		 1846 disk->fops = &nvme_fops;
1847 disk->private_data = ns;
1848 disk->queue = ns->queue;
388f037f 1849 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1850 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1851 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1852 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1853
0e5e4f0e
KB		 1854 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1855 nvme_config_discard(ns);
1856
b60503ba
MW		 1857 return ns;
1858
1859 out_free_queue:
1860 blk_cleanup_queue(ns->queue);
1861 out_free_ns:
1862 kfree(ns);
1863 return NULL;
1864}
1865
42f61420
KB		 1866static int nvme_find_closest_node(int node)
1867{
1868 int n, val, min_val = INT_MAX, best_node = node;
1869
1870 for_each_online_node(n) {
1871 if (n == node)
1872 continue;
1873 val = node_distance(node, n);
1874 if (val < min_val) {
1875 min_val = val;
1876 best_node = n;
1877 }
1878 }
1879 return best_node;
1880}
1881
1882static void nvme_set_queue_cpus(cpumask_t *qmask, struct nvme_queue *nvmeq,
1883 int count)
1884{
1885 int cpu;
1886 for_each_cpu(cpu, qmask) {
1887 if (cpumask_weight(nvmeq->cpu_mask) >= count)
1888 break;
1889 if (!cpumask_test_and_set_cpu(cpu, nvmeq->cpu_mask))
1890 *per_cpu_ptr(nvmeq->dev->io_queue, cpu) = nvmeq->qid;
1891 }
1892}
1893
1894static void nvme_add_cpus(cpumask_t *mask, const cpumask_t *unassigned_cpus,
1895 const cpumask_t *new_mask, struct nvme_queue *nvmeq, int cpus_per_queue)
1896{
1897 int next_cpu;
1898 for_each_cpu(next_cpu, new_mask) {
1899 cpumask_or(mask, mask, get_cpu_mask(next_cpu));
1900 cpumask_or(mask, mask, topology_thread_cpumask(next_cpu));
1901 cpumask_and(mask, mask, unassigned_cpus);
1902 nvme_set_queue_cpus(mask, nvmeq, cpus_per_queue);
1903 }
1904}
1905
1906static void nvme_create_io_queues(struct nvme_dev *dev)
1907{
1908 unsigned i, max;
1909
1910 max = min(dev->max_qid, num_online_cpus());
1911 for (i = dev->queue_count; i <= max; i++)
1912 if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1))
1913 break;
1914
1915 max = min(dev->queue_count - 1, num_online_cpus());
1916 for (i = dev->online_queues; i <= max; i++)
1917 if (nvme_create_queue(raw_nvmeq(dev, i), i))
1918 break;
1919}
1920
1921/*
1922 * If there are fewer queues than online cpus, this will try to optimally
1923 * assign a queue to multiple cpus by grouping cpus that are "close" together:
1924 * thread siblings, core, socket, closest node, then whatever else is
1925 * available.
1926 */
1927static void nvme_assign_io_queues(struct nvme_dev *dev)
1928{
1929 unsigned cpu, cpus_per_queue, queues, remainder, i;
1930 cpumask_var_t unassigned_cpus;
1931
1932 nvme_create_io_queues(dev);
1933
1934 queues = min(dev->online_queues - 1, num_online_cpus());
1935 if (!queues)
1936 return;
1937
1938 cpus_per_queue = num_online_cpus() / queues;
1939 remainder = queues - (num_online_cpus() - queues * cpus_per_queue);
1940
1941 if (!alloc_cpumask_var(&unassigned_cpus, GFP_KERNEL))
1942 return;
1943
1944 cpumask_copy(unassigned_cpus, cpu_online_mask);
1945 cpu = cpumask_first(unassigned_cpus);
1946 for (i = 1; i <= queues; i++) {
1947 struct nvme_queue *nvmeq = lock_nvmeq(dev, i);
1948 cpumask_t mask;
1949
1950 cpumask_clear(nvmeq->cpu_mask);
1951 if (!cpumask_weight(unassigned_cpus)) {
1952 unlock_nvmeq(nvmeq);
1953 break;
1954 }
1955
1956 mask = *get_cpu_mask(cpu);
1957 nvme_set_queue_cpus(&mask, nvmeq, cpus_per_queue);
1958 if (cpus_weight(mask) < cpus_per_queue)
1959 nvme_add_cpus(&mask, unassigned_cpus,
1960 topology_thread_cpumask(cpu),
1961 nvmeq, cpus_per_queue);
1962 if (cpus_weight(mask) < cpus_per_queue)
1963 nvme_add_cpus(&mask, unassigned_cpus,
1964 topology_core_cpumask(cpu),
1965 nvmeq, cpus_per_queue);
1966 if (cpus_weight(mask) < cpus_per_queue)
1967 nvme_add_cpus(&mask, unassigned_cpus,
1968 cpumask_of_node(cpu_to_node(cpu)),
1969 nvmeq, cpus_per_queue);
1970 if (cpus_weight(mask) < cpus_per_queue)
1971 nvme_add_cpus(&mask, unassigned_cpus,
1972 cpumask_of_node(
1973 nvme_find_closest_node(
1974 cpu_to_node(cpu))),
1975 nvmeq, cpus_per_queue);
1976 if (cpus_weight(mask) < cpus_per_queue)
1977 nvme_add_cpus(&mask, unassigned_cpus,
1978 unassigned_cpus,
1979 nvmeq, cpus_per_queue);
1980
1981 WARN(cpumask_weight(nvmeq->cpu_mask) != cpus_per_queue,
1982 "nvme%d qid:%d mis-matched queue-to-cpu assignment\n",
1983 dev->instance, i);
1984
1985 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1986 nvmeq->cpu_mask);
1987 cpumask_andnot(unassigned_cpus, unassigned_cpus,
1988 nvmeq->cpu_mask);
1989 cpu = cpumask_next(cpu, unassigned_cpus);
1990 if (remainder && !--remainder)
1991 cpus_per_queue++;
1992 unlock_nvmeq(nvmeq);
1993 }
1994 WARN(cpumask_weight(unassigned_cpus), "nvme%d unassigned online cpus\n",
1995 dev->instance);
1996 i = 0;
1997 cpumask_andnot(unassigned_cpus, cpu_possible_mask, cpu_online_mask);
1998 for_each_cpu(cpu, unassigned_cpus)
1999 *per_cpu_ptr(dev->io_queue, cpu) = (i++ % queues) + 1;
2000 free_cpumask_var(unassigned_cpus);
2001}
2002
b3b06812 2003static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2004{
2005 int status;
2006 u32 result;
b3b06812 2007 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2008
df348139 2009 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2010 &result);
b60503ba 2011 if (status)
7e03b124 2012 return status < 0 ? -EIO : -EBUSY;
b60503ba
MW		 2013 return min(result & 0xffff, result >> 16) + 1;
2014}
2015
9d713c2b
KB		 2016static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2017{
b80d5ccc 2018 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2019}
2020
33b1e95c
KB		 2021static int nvme_cpu_notify(struct notifier_block *self,
2022 unsigned long action, void *hcpu)
2023{
2024 struct nvme_dev *dev = container_of(self, struct nvme_dev, nb);
2025 switch (action) {
2026 case CPU_ONLINE:
2027 case CPU_DEAD:
2028 nvme_assign_io_queues(dev);
2029 break;
2030 }
2031 return NOTIFY_OK;
2032}
2033
8d85fce7 2034static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2035{
5a92e700 2036 struct nvme_queue *adminq = raw_nvmeq(dev, 0);
fa08a396 2037 struct pci_dev *pdev = dev->pci_dev;
42f61420 2038 int result, i, vecs, nr_io_queues, size;
b60503ba 2039
42f61420 2040 nr_io_queues = num_possible_cpus();
b348b7d5 2041 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW		 2042 if (result < 0)
2043 return result;
b348b7d5
MW		 2044 if (result < nr_io_queues)
2045 nr_io_queues = result;
b60503ba 2046
9d713c2b
KB		 2047 size = db_bar_size(dev, nr_io_queues);
2048 if (size > 8192) {
f1938f6e 2049 iounmap(dev->bar);
9d713c2b
KB		 2050 do {
2051 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2052 if (dev->bar)
2053 break;
2054 if (!--nr_io_queues)
2055 return -ENOMEM;
2056 size = db_bar_size(dev, nr_io_queues);
2057 } while (1);
f1938f6e 2058 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2059 adminq->q_db = dev->dbs;
f1938f6e
MW		 2060 }
2061
9d713c2b 2062 /* Deregister the admin queue's interrupt */
3193f07b 2063 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2064
063a8096
MW		 2065 vecs = nr_io_queues;
2066 for (i = 0; i < vecs; i++)
1b23484b
MW		 2067 dev->entry[i].entry = i;
2068 for (;;) {
063a8096
MW		 2069 result = pci_enable_msix(pdev, dev->entry, vecs);
2070 if (result <= 0)
1b23484b 2071 break;
063a8096 2072 vecs = result;
1b23484b
MW		 2073 }
2074
063a8096
MW		 2075 if (result < 0) {
2076 vecs = nr_io_queues;
2077 if (vecs > 32)
2078 vecs = 32;
fa08a396 2079 for (;;) {
063a8096 2080 result = pci_enable_msi_block(pdev, vecs);
fa08a396 2081 if (result == 0) {
063a8096 2082 for (i = 0; i < vecs; i++)
fa08a396
RRG		 2083 dev->entry[i].vector = i + pdev->irq;
2084 break;
063a8096
MW		 2085 } else if (result < 0) {
2086 vecs = 1;
fa08a396
RRG		 2087 break;
2088 }
063a8096 2089 vecs = result;
fa08a396
RRG		 2090 }
2091 }
2092
063a8096
MW		 2093 /*
2094 * Should investigate if there's a performance win from allocating
2095 * more queues than interrupt vectors; it might allow the submission
2096 * path to scale better, even if the receive path is limited by the
2097 * number of interrupts.
2098 */
2099 nr_io_queues = vecs;
42f61420 2100 dev->max_qid = nr_io_queues;
063a8096 2101
3193f07b 2102 result = queue_request_irq(dev, adminq, adminq->irqname);
9d713c2b 2103 if (result) {
3193f07b 2104 adminq->q_suspended = 1;
22404274 2105 goto free_queues;
9d713c2b 2106 }
1b23484b 2107
cd638946 2108 /* Free previously allocated queues that are no longer usable */
42f61420
KB		 2109 nvme_free_queues(dev, nr_io_queues + 1);
2110 nvme_assign_io_queues(dev);
b60503ba 2111
33b1e95c
KB		 2112 dev->nb.notifier_call = &nvme_cpu_notify;
2113 result = register_hotcpu_notifier(&dev->nb);
2114 if (result)
2115 goto free_queues;
2116
22404274 2117 return 0;
b60503ba 2118
22404274 2119 free_queues:
a1a5ef99 2120 nvme_free_queues(dev, 1);
22404274 2121 return result;
b60503ba
MW		 2122}
2123
422ef0c7
MW		 2124/*
2125 * Return: error value if an error occurred setting up the queues or calling
2126 * Identify Device. 0 if these succeeded, even if adding some of the
2127 * namespaces failed. At the moment, these failures are silent. TBD which
2128 * failures should be reported.
2129 */
8d85fce7 2130static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2131{
68608c26 2132 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2133 int res;
2134 unsigned nn, i;
cbb6218f 2135 struct nvme_ns *ns;
51814232 2136 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2137 struct nvme_id_ns *id_ns;
2138 void *mem;
b60503ba 2139 dma_addr_t dma_addr;
159b67d7 2140 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2141
68608c26 2142 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2143 if (!mem)
2144 return -ENOMEM;
b60503ba 2145
bc5fc7e4 2146 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba
MW		 2147 if (res) {
2148 res = -EIO;
cbb6218f 2149 goto out;
b60503ba
MW		 2150 }
2151
bc5fc7e4 2152 ctrl = mem;
51814232 2153 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2154 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2155 dev->abort_limit = ctrl->acl + 1;
51814232
MW		 2156 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2157 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2158 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2159 if (ctrl->mdts)
8fc23e03 2160 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26
MW		 2161 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2162 (pdev->device == 0x0953) && ctrl->vs[3])
159b67d7 2163 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
b60503ba 2164
bc5fc7e4 2165 id_ns = mem;
2b2c1896 2166 for (i = 1; i <= nn; i++) {
bc5fc7e4 2167 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2168 if (res)
2169 continue;
2170
bc5fc7e4 2171 if (id_ns->ncap == 0)
b60503ba
MW		 2172 continue;
2173
bc5fc7e4 2174 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2175 dma_addr + 4096, NULL);
b60503ba 2176 if (res)
12209036 2177 memset(mem + 4096, 0, 4096);
b60503ba 2178
bc5fc7e4 2179 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2180 if (ns)
2181 list_add_tail(&ns->list, &dev->namespaces);
2182 }
2183 list_for_each_entry(ns, &dev->namespaces, list)
2184 add_disk(ns->disk);
422ef0c7 2185 res = 0;
b60503ba 2186
bc5fc7e4 2187 out:
684f5c20 2188 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2189 return res;
2190}
2191
0877cb0d
KB		 2192static int nvme_dev_map(struct nvme_dev *dev)
2193{
42f61420 2194 u64 cap;
0877cb0d
KB		 2195 int bars, result = -ENOMEM;
2196 struct pci_dev *pdev = dev->pci_dev;
2197
2198 if (pci_enable_device_mem(pdev))
2199 return result;
2200
2201 dev->entry[0].vector = pdev->irq;
2202 pci_set_master(pdev);
2203 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2204 if (pci_request_selected_regions(pdev, bars, "nvme"))
2205 goto disable_pci;
2206
052d0efa
RK		 2207 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2208 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2209 goto disable;
0877cb0d 2210
0877cb0d
KB		 2211 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2212 if (!dev->bar)
2213 goto disable;
0e53d180
KB		 2214 if (readl(&dev->bar->csts) == -1) {
2215 result = -ENODEV;
2216 goto unmap;
2217 }
42f61420
KB		 2218 cap = readq(&dev->bar->cap);
2219 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2220 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2221 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2222
2223 return 0;
2224
0e53d180
KB		 2225 unmap:
2226 iounmap(dev->bar);
2227 dev->bar = NULL;
0877cb0d
KB		 2228 disable:
2229 pci_release_regions(pdev);
2230 disable_pci:
2231 pci_disable_device(pdev);
2232 return result;
2233}
2234
2235static void nvme_dev_unmap(struct nvme_dev *dev)
2236{
2237 if (dev->pci_dev->msi_enabled)
2238 pci_disable_msi(dev->pci_dev);
2239 else if (dev->pci_dev->msix_enabled)
2240 pci_disable_msix(dev->pci_dev);
2241
2242 if (dev->bar) {
2243 iounmap(dev->bar);
2244 dev->bar = NULL;
9a6b9458 2245 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2246 }
2247
0877cb0d
KB		 2248 if (pci_is_enabled(dev->pci_dev))
2249 pci_disable_device(dev->pci_dev);
2250}
2251
4d115420
KB		 2252struct nvme_delq_ctx {
2253 struct task_struct *waiter;
2254 struct kthread_worker *worker;
2255 atomic_t refcount;
2256};
2257
2258static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2259{
2260 dq->waiter = current;
2261 mb();
2262
2263 for (;;) {
2264 set_current_state(TASK_KILLABLE);
2265 if (!atomic_read(&dq->refcount))
2266 break;
2267 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2268 fatal_signal_pending(current)) {
2269 set_current_state(TASK_RUNNING);
2270
2271 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2272 nvme_disable_queue(dev, 0);
2273
2274 send_sig(SIGKILL, dq->worker->task, 1);
2275 flush_kthread_worker(dq->worker);
2276 return;
2277 }
2278 }
2279 set_current_state(TASK_RUNNING);
2280}
2281
2282static void nvme_put_dq(struct nvme_delq_ctx *dq)
2283{
2284 atomic_dec(&dq->refcount);
2285 if (dq->waiter)
2286 wake_up_process(dq->waiter);
2287}
2288
2289static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2290{
2291 atomic_inc(&dq->refcount);
2292 return dq;
2293}
2294
2295static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2296{
2297 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2298
2299 nvme_clear_queue(nvmeq);
2300 nvme_put_dq(dq);
2301}
2302
2303static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2304 kthread_work_func_t fn)
2305{
2306 struct nvme_command c;
2307
2308 memset(&c, 0, sizeof(c));
2309 c.delete_queue.opcode = opcode;
2310 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2311
2312 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2313 return nvme_submit_admin_cmd_async(nvmeq->dev, &c, &nvmeq->cmdinfo);
2314}
2315
2316static void nvme_del_cq_work_handler(struct kthread_work *work)
2317{
2318 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2319 cmdinfo.work);
2320 nvme_del_queue_end(nvmeq);
2321}
2322
2323static int nvme_delete_cq(struct nvme_queue *nvmeq)
2324{
2325 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2326 nvme_del_cq_work_handler);
2327}
2328
2329static void nvme_del_sq_work_handler(struct kthread_work *work)
2330{
2331 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2332 cmdinfo.work);
2333 int status = nvmeq->cmdinfo.status;
2334
2335 if (!status)
2336 status = nvme_delete_cq(nvmeq);
2337 if (status)
2338 nvme_del_queue_end(nvmeq);
2339}
2340
2341static int nvme_delete_sq(struct nvme_queue *nvmeq)
2342{
2343 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2344 nvme_del_sq_work_handler);
2345}
2346
2347static void nvme_del_queue_start(struct kthread_work *work)
2348{
2349 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2350 cmdinfo.work);
2351 allow_signal(SIGKILL);
2352 if (nvme_delete_sq(nvmeq))
2353 nvme_del_queue_end(nvmeq);
2354}
2355
2356static void nvme_disable_io_queues(struct nvme_dev *dev)
2357{
2358 int i;
2359 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2360 struct nvme_delq_ctx dq;
2361 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2362 &worker, "nvme%d", dev->instance);
2363
2364 if (IS_ERR(kworker_task)) {
2365 dev_err(&dev->pci_dev->dev,
2366 "Failed to create queue del task\n");
2367 for (i = dev->queue_count - 1; i > 0; i--)
2368 nvme_disable_queue(dev, i);
2369 return;
2370 }
2371
2372 dq.waiter = NULL;
2373 atomic_set(&dq.refcount, 0);
2374 dq.worker = &worker;
2375 for (i = dev->queue_count - 1; i > 0; i--) {
5a92e700 2376 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2377
2378 if (nvme_suspend_queue(nvmeq))
2379 continue;
2380 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2381 nvmeq->cmdinfo.worker = dq.worker;
2382 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2383 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2384 }
2385 nvme_wait_dq(&dq, dev);
2386 kthread_stop(kworker_task);
2387}
2388
b9afca3e
DM		 2389/*
2390* Remove the node from the device list and check
2391* for whether or not we need to stop the nvme_thread.
2392*/
2393static void nvme_dev_list_remove(struct nvme_dev *dev)
2394{
2395 struct task_struct *tmp = NULL;
2396
2397 spin_lock(&dev_list_lock);
2398 list_del_init(&dev->node);
2399 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2400 tmp = nvme_thread;
2401 nvme_thread = NULL;
2402 }
2403 spin_unlock(&dev_list_lock);
2404
2405 if (tmp)
2406 kthread_stop(tmp);
2407}
2408
f0b50732 2409static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2410{
22404274
KB		 2411 int i;
2412
d4b4ff8e 2413 dev->initialized = 0;
33b1e95c 2414 unregister_hotcpu_notifier(&dev->nb);
b60503ba 2415
b9afca3e 2416 nvme_dev_list_remove(dev);
1fa6aead 2417
4d115420
KB		 2418 if (!dev->bar || (dev->bar && readl(&dev->bar->csts) == -1)) {
2419 for (i = dev->queue_count - 1; i >= 0; i--) {
5a92e700 2420 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2421 nvme_suspend_queue(nvmeq);
2422 nvme_clear_queue(nvmeq);
2423 }
2424 } else {
2425 nvme_disable_io_queues(dev);
1894d8f1 2426 nvme_shutdown_ctrl(dev);
4d115420
KB		 2427 nvme_disable_queue(dev, 0);
2428 }
f0b50732
KB		 2429 nvme_dev_unmap(dev);
2430}
2431
2432static void nvme_dev_remove(struct nvme_dev *dev)
2433{
9ac27090 2434 struct nvme_ns *ns;
f0b50732 2435
9ac27090
KB		 2436 list_for_each_entry(ns, &dev->namespaces, list) {
2437 if (ns->disk->flags & GENHD_FL_UP)
2438 del_gendisk(ns->disk);
2439 if (!blk_queue_dying(ns->queue))
2440 blk_cleanup_queue(ns->queue);
b60503ba 2441 }
b60503ba
MW		 2442}
2443
091b6092
MW		 2444static int nvme_setup_prp_pools(struct nvme_dev *dev)
2445{
2446 struct device *dmadev = &dev->pci_dev->dev;
2447 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2448 PAGE_SIZE, PAGE_SIZE, 0);
2449 if (!dev->prp_page_pool)
2450 return -ENOMEM;
2451
99802a7a
MW		 2452 /* Optimisation for I/Os between 4k and 128k */
2453 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2454 256, 256, 0);
2455 if (!dev->prp_small_pool) {
2456 dma_pool_destroy(dev->prp_page_pool);
2457 return -ENOMEM;
2458 }
091b6092
MW		 2459 return 0;
2460}
2461
2462static void nvme_release_prp_pools(struct nvme_dev *dev)
2463{
2464 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2465 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2466}
2467
cd58ad7d
QSA		 2468static DEFINE_IDA(nvme_instance_ida);
2469
2470static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2471{
cd58ad7d
QSA		 2472 int instance, error;
2473
2474 do {
2475 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2476 return -ENODEV;
2477
2478 spin_lock(&dev_list_lock);
2479 error = ida_get_new(&nvme_instance_ida, &instance);
2480 spin_unlock(&dev_list_lock);
2481 } while (error == -EAGAIN);
2482
2483 if (error)
2484 return -ENODEV;
2485
2486 dev->instance = instance;
2487 return 0;
b60503ba
MW		 2488}
2489
2490static void nvme_release_instance(struct nvme_dev *dev)
2491{
cd58ad7d
QSA		 2492 spin_lock(&dev_list_lock);
2493 ida_remove(&nvme_instance_ida, dev->instance);
2494 spin_unlock(&dev_list_lock);
b60503ba
MW		 2495}
2496
9ac27090
KB		 2497static void nvme_free_namespaces(struct nvme_dev *dev)
2498{
2499 struct nvme_ns *ns, *next;
2500
2501 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2502 list_del(&ns->list);
2503 put_disk(ns->disk);
2504 kfree(ns);
2505 }
2506}
2507
5e82e952
KB		 2508static void nvme_free_dev(struct kref *kref)
2509{
2510 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090
KB		 2511
2512 nvme_free_namespaces(dev);
42f61420 2513 free_percpu(dev->io_queue);
5e82e952
KB		 2514 kfree(dev->queues);
2515 kfree(dev->entry);
2516 kfree(dev);
2517}
2518
2519static int nvme_dev_open(struct inode *inode, struct file *f)
2520{
2521 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2522 miscdev);
2523 kref_get(&dev->kref);
2524 f->private_data = dev;
2525 return 0;
2526}
2527
2528static int nvme_dev_release(struct inode *inode, struct file *f)
2529{
2530 struct nvme_dev *dev = f->private_data;
2531 kref_put(&dev->kref, nvme_free_dev);
2532 return 0;
2533}
2534
2535static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2536{
2537 struct nvme_dev *dev = f->private_data;
2538 switch (cmd) {
2539 case NVME_IOCTL_ADMIN_CMD:
2540 return nvme_user_admin_cmd(dev, (void __user *)arg);
2541 default:
2542 return -ENOTTY;
2543 }
2544}
2545
2546static const struct file_operations nvme_dev_fops = {
2547 .owner = THIS_MODULE,
2548 .open = nvme_dev_open,
2549 .release = nvme_dev_release,
2550 .unlocked_ioctl = nvme_dev_ioctl,
2551 .compat_ioctl = nvme_dev_ioctl,
2552};
2553
f0b50732
KB		 2554static int nvme_dev_start(struct nvme_dev *dev)
2555{
2556 int result;
b9afca3e 2557 bool start_thread = false;
f0b50732
KB		 2558
2559 result = nvme_dev_map(dev);
2560 if (result)
2561 return result;
2562
2563 result = nvme_configure_admin_queue(dev);
2564 if (result)
2565 goto unmap;
2566
2567 spin_lock(&dev_list_lock);
b9afca3e
DM		 2568 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2569 start_thread = true;
2570 nvme_thread = NULL;
2571 }
f0b50732
KB		 2572 list_add(&dev->node, &dev_list);
2573 spin_unlock(&dev_list_lock);
2574
b9afca3e
DM		 2575 if (start_thread) {
2576 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2577 wake_up(&nvme_kthread_wait);
2578 } else
2579 wait_event_killable(nvme_kthread_wait, nvme_thread);
2580
2581 if (IS_ERR_OR_NULL(nvme_thread)) {
2582 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2583 goto disable;
2584 }
2585
f0b50732 2586 result = nvme_setup_io_queues(dev);
d82e8bfd 2587 if (result && result != -EBUSY)
f0b50732
KB		 2588 goto disable;
2589
d82e8bfd 2590 return result;
f0b50732
KB		 2591
2592 disable:
a1a5ef99 2593 nvme_disable_queue(dev, 0);
b9afca3e 2594 nvme_dev_list_remove(dev);
f0b50732
KB		 2595 unmap:
2596 nvme_dev_unmap(dev);
2597 return result;
2598}
2599
9a6b9458
KB		 2600static int nvme_remove_dead_ctrl(void *arg)
2601{
2602 struct nvme_dev *dev = (struct nvme_dev *)arg;
2603 struct pci_dev *pdev = dev->pci_dev;
2604
2605 if (pci_get_drvdata(pdev))
2606 pci_stop_and_remove_bus_device(pdev);
2607 kref_put(&dev->kref, nvme_free_dev);
2608 return 0;
2609}
2610
2611static void nvme_remove_disks(struct work_struct *ws)
2612{
9a6b9458
KB		 2613 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2614
2615 nvme_dev_remove(dev);
5a92e700 2616 nvme_free_queues(dev, 1);
9a6b9458
KB		 2617}
2618
2619static int nvme_dev_resume(struct nvme_dev *dev)
2620{
2621 int ret;
2622
2623 ret = nvme_dev_start(dev);
2624 if (ret && ret != -EBUSY)
2625 return ret;
2626 if (ret == -EBUSY) {
2627 spin_lock(&dev_list_lock);
bdfd70fd 2628 PREPARE_WORK(&dev->reset_work, nvme_remove_disks);
9a6b9458
KB		 2629 queue_work(nvme_workq, &dev->reset_work);
2630 spin_unlock(&dev_list_lock);
2631 }
d4b4ff8e 2632 dev->initialized = 1;
9a6b9458
KB		 2633 return 0;
2634}
2635
2636static void nvme_dev_reset(struct nvme_dev *dev)
2637{
2638 nvme_dev_shutdown(dev);
2639 if (nvme_dev_resume(dev)) {
2640 dev_err(&dev->pci_dev->dev, "Device failed to resume\n");
2641 kref_get(&dev->kref);
2642 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2643 dev->instance))) {
2644 dev_err(&dev->pci_dev->dev,
2645 "Failed to start controller remove task\n");
2646 kref_put(&dev->kref, nvme_free_dev);
2647 }
2648 }
2649}
2650
2651static void nvme_reset_failed_dev(struct work_struct *ws)
2652{
2653 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2654 nvme_dev_reset(dev);
2655}
2656
8d85fce7 2657static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2658{
0877cb0d 2659 int result = -ENOMEM;
b60503ba
MW		 2660 struct nvme_dev *dev;
2661
2662 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2663 if (!dev)
2664 return -ENOMEM;
2665 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2666 GFP_KERNEL);
2667 if (!dev->entry)
2668 goto free;
1b23484b
MW		 2669 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2670 GFP_KERNEL);
b60503ba
MW		 2671 if (!dev->queues)
2672 goto free;
42f61420
KB		 2673 dev->io_queue = alloc_percpu(unsigned short);
2674 if (!dev->io_queue)
2675 goto free;
b60503ba
MW		 2676
2677 INIT_LIST_HEAD(&dev->namespaces);
bdfd70fd 2678 INIT_WORK(&dev->reset_work, nvme_reset_failed_dev);
b60503ba 2679 dev->pci_dev = pdev;
9a6b9458 2680 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2681 result = nvme_set_instance(dev);
2682 if (result)
0877cb0d 2683 goto free;
b60503ba 2684
091b6092
MW		 2685 result = nvme_setup_prp_pools(dev);
2686 if (result)
0877cb0d 2687 goto release;
091b6092 2688
fb35e914 2689 kref_init(&dev->kref);
f0b50732 2690 result = nvme_dev_start(dev);
d82e8bfd
KB		 2691 if (result) {
2692 if (result == -EBUSY)
2693 goto create_cdev;
0877cb0d 2694 goto release_pools;
d82e8bfd 2695 }
b60503ba 2696
740216fc 2697 result = nvme_dev_add(dev);
d82e8bfd 2698 if (result)
f0b50732 2699 goto shutdown;
740216fc 2700
d82e8bfd 2701 create_cdev:
5e82e952
KB		 2702 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2703 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2704 dev->miscdev.parent = &pdev->dev;
2705 dev->miscdev.name = dev->name;
2706 dev->miscdev.fops = &nvme_dev_fops;
2707 result = misc_register(&dev->miscdev);
2708 if (result)
2709 goto remove;
2710
d4b4ff8e 2711 dev->initialized = 1;
b60503ba
MW		 2712 return 0;
2713
5e82e952
KB		 2714 remove:
2715 nvme_dev_remove(dev);
9ac27090 2716 nvme_free_namespaces(dev);
f0b50732
KB		 2717 shutdown:
2718 nvme_dev_shutdown(dev);
0877cb0d 2719 release_pools:
a1a5ef99 2720 nvme_free_queues(dev, 0);
091b6092 2721 nvme_release_prp_pools(dev);
0877cb0d
KB		 2722 release:
2723 nvme_release_instance(dev);
b60503ba 2724 free:
42f61420 2725 free_percpu(dev->io_queue);
b60503ba
MW		 2726 kfree(dev->queues);
2727 kfree(dev->entry);
2728 kfree(dev);
2729 return result;
2730}
2731
09ece142
KB		 2732static void nvme_shutdown(struct pci_dev *pdev)
2733{
2734 struct nvme_dev *dev = pci_get_drvdata(pdev);
2735 nvme_dev_shutdown(dev);
2736}
2737
8d85fce7 2738static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2739{
2740 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2741
2742 spin_lock(&dev_list_lock);
2743 list_del_init(&dev->node);
2744 spin_unlock(&dev_list_lock);
2745
2746 pci_set_drvdata(pdev, NULL);
2747 flush_work(&dev->reset_work);
5e82e952 2748 misc_deregister(&dev->miscdev);
9a6b9458
KB		 2749 nvme_dev_remove(dev);
2750 nvme_dev_shutdown(dev);
a1a5ef99 2751 nvme_free_queues(dev, 0);
5a92e700 2752 rcu_barrier();
9a6b9458
KB		 2753 nvme_release_instance(dev);
2754 nvme_release_prp_pools(dev);
5e82e952 2755 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2756}
2757
2758/* These functions are yet to be implemented */
2759#define nvme_error_detected NULL
2760#define nvme_dump_registers NULL
2761#define nvme_link_reset NULL
2762#define nvme_slot_reset NULL
2763#define nvme_error_resume NULL
cd638946 2764
671a6018 2765#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2766static int nvme_suspend(struct device *dev)
2767{
2768 struct pci_dev *pdev = to_pci_dev(dev);
2769 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2770
2771 nvme_dev_shutdown(ndev);
2772 return 0;
2773}
2774
2775static int nvme_resume(struct device *dev)
2776{
2777 struct pci_dev *pdev = to_pci_dev(dev);
2778 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2779
9a6b9458 2780 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
bdfd70fd 2781 PREPARE_WORK(&ndev->reset_work, nvme_reset_failed_dev);
9a6b9458
KB		 2782 queue_work(nvme_workq, &ndev->reset_work);
2783 }
2784 return 0;
cd638946 2785}
671a6018 2786#endif
cd638946
KB		 2787
2788static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2789
1d352035 2790static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2791 .error_detected = nvme_error_detected,
2792 .mmio_enabled = nvme_dump_registers,
2793 .link_reset = nvme_link_reset,
2794 .slot_reset = nvme_slot_reset,
2795 .resume = nvme_error_resume,
2796};
2797
2798/* Move to pci_ids.h later */
2799#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2800
6eb0d698 2801static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2802 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2803 { 0, }
2804};
2805MODULE_DEVICE_TABLE(pci, nvme_id_table);
2806
2807static struct pci_driver nvme_driver = {
2808 .name = "nvme",
2809 .id_table = nvme_id_table,
2810 .probe = nvme_probe,
8d85fce7 2811 .remove = nvme_remove,
09ece142 2812 .shutdown = nvme_shutdown,
cd638946
KB		 2813 .driver = {
2814 .pm = &nvme_dev_pm_ops,
2815 },
b60503ba
MW		 2816 .err_handler = &nvme_err_handler,
2817};
2818
2819static int __init nvme_init(void)
2820{
0ac13140 2821 int result;
1fa6aead 2822
b9afca3e 2823 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2824
9a6b9458
KB		 2825 nvme_workq = create_singlethread_workqueue("nvme");
2826 if (!nvme_workq)
b9afca3e 2827 return -ENOMEM;
9a6b9458 2828
5c42ea16
KB		 2829 result = register_blkdev(nvme_major, "nvme");
2830 if (result < 0)
9a6b9458 2831 goto kill_workq;
5c42ea16 2832 else if (result > 0)
0ac13140 2833 nvme_major = result;
b60503ba
MW		 2834
2835 result = pci_register_driver(&nvme_driver);
1fa6aead
MW		 2836 if (result)
2837 goto unregister_blkdev;
2838 return 0;
b60503ba 2839
1fa6aead 2840 unregister_blkdev:
b60503ba 2841 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2842 kill_workq:
2843 destroy_workqueue(nvme_workq);
b60503ba
MW		 2844 return result;
2845}
2846
2847static void __exit nvme_exit(void)
2848{
2849 pci_unregister_driver(&nvme_driver);
2850 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2851 destroy_workqueue(nvme_workq);
b9afca3e 2852 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
b60503ba
MW		 2853}
2854
2855MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2856MODULE_LICENSE("GPL");
6eb0d698 2857MODULE_VERSION("0.9");
b60503ba
MW		 2858module_init(nvme_init);
2859module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)