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[linux-2.6-block.git] / drivers / block / nvme-core.c
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b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
40#include <linux/types.h>
5d0f6131 41#include <scsi/sg.h>
797a796a
HM		 42#include <asm-generic/io-64-nonatomic-lo-hi.h>
43
9d43cf64 44#define NVME_Q_DEPTH 1024
a4aea562 45#define NVME_AQ_DEPTH 64
b60503ba
MW		 46#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 48#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 49#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 50#define IOD_TIMEOUT (retry_time * HZ)
51
52static unsigned char admin_timeout = 60;
53module_param(admin_timeout, byte, 0644);
54MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 55
bd67608a
MW		 56unsigned char nvme_io_timeout = 30;
57module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 58MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 59
61e4ce08
KB		 60static unsigned char retry_time = 30;
61module_param(retry_time, byte, 0644);
62MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
63
2484f407
DM		 64static unsigned char shutdown_timeout = 5;
65module_param(shutdown_timeout, byte, 0644);
66MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
67
b60503ba
MW		 68static int nvme_major;
69module_param(nvme_major, int, 0);
70
58ffacb5
MW		 71static int use_threaded_interrupts;
72module_param(use_threaded_interrupts, int, 0);
73
1fa6aead
MW		 74static DEFINE_SPINLOCK(dev_list_lock);
75static LIST_HEAD(dev_list);
76static struct task_struct *nvme_thread;
9a6b9458 77static struct workqueue_struct *nvme_workq;
b9afca3e 78static wait_queue_head_t nvme_kthread_wait;
f3db22fe 79static struct notifier_block nvme_nb;
1fa6aead 80
d4b4ff8e 81static void nvme_reset_failed_dev(struct work_struct *ws);
a4aea562 82static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 83
4d115420
KB		 84struct async_cmd_info {
85 struct kthread_work work;
86 struct kthread_worker *worker;
a4aea562 87 struct request *req;
4d115420
KB		 88 u32 result;
89 int status;
90 void *ctx;
91};
1fa6aead 92
b60503ba
MW		 93/*
94 * An NVM Express queue. Each device has at least two (one for admin
95 * commands and one for I/O commands).
96 */
97struct nvme_queue {
f435c282 98 struct llist_node node;
b60503ba 99 struct device *q_dmadev;
091b6092 100 struct nvme_dev *dev;
3193f07b 101 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 102 spinlock_t q_lock;
103 struct nvme_command *sq_cmds;
104 volatile struct nvme_completion *cqes;
105 dma_addr_t sq_dma_addr;
106 dma_addr_t cq_dma_addr;
b60503ba
MW		 107 u32 __iomem *q_db;
108 u16 q_depth;
109 u16 cq_vector;
110 u16 sq_head;
111 u16 sq_tail;
112 u16 cq_head;
c30341dc 113 u16 qid;
e9539f47
MW		 114 u8 cq_phase;
115 u8 cqe_seen;
4d115420 116 struct async_cmd_info cmdinfo;
a4aea562 117 struct blk_mq_hw_ctx *hctx;
b60503ba
MW		 118};
119
120/*
121 * Check we didin't inadvertently grow the command struct
122 */
123static inline void _nvme_check_size(void)
124{
125 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 130 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 131 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 136 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 137}
138
edd10d33 139typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 140 struct nvme_completion *);
141
e85248e5 142struct nvme_cmd_info {
c2f5b650
MW		 143 nvme_completion_fn fn;
144 void *ctx;
c30341dc 145 int aborted;
a4aea562 146 struct nvme_queue *nvmeq;
e85248e5
MW		 147};
148
a4aea562
MB		 149static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
150 unsigned int hctx_idx)
e85248e5 151{
a4aea562
MB		 152 struct nvme_dev *dev = data;
153 struct nvme_queue *nvmeq = dev->queues[0];
154
155 WARN_ON(nvmeq->hctx);
156 nvmeq->hctx = hctx;
157 hctx->driver_data = nvmeq;
158 return 0;
e85248e5
MW		 159}
160
a4aea562
MB		 161static int nvme_admin_init_request(void *data, struct request *req,
162 unsigned int hctx_idx, unsigned int rq_idx,
163 unsigned int numa_node)
22404274 164{
a4aea562
MB		 165 struct nvme_dev *dev = data;
166 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
167 struct nvme_queue *nvmeq = dev->queues[0];
168
169 BUG_ON(!nvmeq);
170 cmd->nvmeq = nvmeq;
171 return 0;
22404274
KB		 172}
173
2c30540b
JA		 174static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
175{
176 struct nvme_queue *nvmeq = hctx->driver_data;
177
178 nvmeq->hctx = NULL;
179}
180
a4aea562
MB		 181static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
182 unsigned int hctx_idx)
b60503ba 183{
a4aea562
MB		 184 struct nvme_dev *dev = data;
185 struct nvme_queue *nvmeq = dev->queues[
186 (hctx_idx % dev->queue_count) + 1];
b60503ba 187
a4aea562
MB		 188 if (!nvmeq->hctx)
189 nvmeq->hctx = hctx;
190
191 /* nvmeq queues are shared between namespaces. We assume here that
192 * blk-mq map the tags so they match up with the nvme queue tags. */
193 WARN_ON(nvmeq->hctx->tags != hctx->tags);
b60503ba 194
a4aea562
MB		 195 hctx->driver_data = nvmeq;
196 return 0;
b60503ba
MW		 197}
198
a4aea562
MB		 199static int nvme_init_request(void *data, struct request *req,
200 unsigned int hctx_idx, unsigned int rq_idx,
201 unsigned int numa_node)
b60503ba 202{
a4aea562
MB		 203 struct nvme_dev *dev = data;
204 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
205 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
206
207 BUG_ON(!nvmeq);
208 cmd->nvmeq = nvmeq;
209 return 0;
210}
211
212static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
213 nvme_completion_fn handler)
214{
215 cmd->fn = handler;
216 cmd->ctx = ctx;
217 cmd->aborted = 0;
b60503ba
MW		 218}
219
c2f5b650
MW		 220/* Special values must be less than 0x1000 */
221#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 222#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
223#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
224#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 225
edd10d33 226static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 227 struct nvme_completion *cqe)
228{
229 if (ctx == CMD_CTX_CANCELLED)
230 return;
c2f5b650 231 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 232 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 233 "completed id %d twice on queue %d\n",
234 cqe->command_id, le16_to_cpup(&cqe->sq_id));
235 return;
236 }
237 if (ctx == CMD_CTX_INVALID) {
edd10d33 238 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 239 "invalid id %d completed on queue %d\n",
240 cqe->command_id, le16_to_cpup(&cqe->sq_id));
241 return;
242 }
edd10d33 243 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 244}
245
a4aea562 246static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 247{
c2f5b650 248 void *ctx;
b60503ba 249
859361a2 250 if (fn)
a4aea562
MB		 251 *fn = cmd->fn;
252 ctx = cmd->ctx;
253 cmd->fn = special_completion;
254 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 255 return ctx;
b60503ba
MW		 256}
257
a4aea562
MB		 258static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
259 struct nvme_completion *cqe)
3c0cf138 260{
a4aea562 261 struct request *req = ctx;
3c0cf138 262
a4aea562
MB		 263 u32 result = le32_to_cpup(&cqe->result);
264 u16 status = le16_to_cpup(&cqe->status) >> 1;
265
266 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
267 ++nvmeq->dev->event_limit;
268 if (status == NVME_SC_SUCCESS)
269 dev_warn(nvmeq->q_dmadev,
270 "async event result %08x\n", result);
271
9d135bb8 272 blk_mq_free_hctx_request(nvmeq->hctx, req);
b60503ba
MW		 273}
274
a4aea562
MB		 275static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
276 struct nvme_completion *cqe)
5a92e700 277{
a4aea562
MB		 278 struct request *req = ctx;
279
280 u16 status = le16_to_cpup(&cqe->status) >> 1;
281 u32 result = le32_to_cpup(&cqe->result);
a51afb54 282
9d135bb8 283 blk_mq_free_hctx_request(nvmeq->hctx, req);
a51afb54 284
a4aea562
MB		 285 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
286 ++nvmeq->dev->abort_limit;
5a92e700
KB		 287}
288
a4aea562
MB		 289static void async_completion(struct nvme_queue *nvmeq, void *ctx,
290 struct nvme_completion *cqe)
b60503ba 291{
a4aea562
MB		 292 struct async_cmd_info *cmdinfo = ctx;
293 cmdinfo->result = le32_to_cpup(&cqe->result);
294 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
295 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
9d135bb8 296 blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
b60503ba
MW		 297}
298
a4aea562
MB		 299static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
300 unsigned int tag)
b60503ba 301{
a4aea562
MB		 302 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
303 struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
a51afb54 304
a4aea562 305 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 306}
307
a4aea562
MB		 308/*
309 * Called with local interrupts disabled and the q_lock held. May not sleep.
310 */
311static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
312 nvme_completion_fn *fn)
4f5099af 313{
a4aea562
MB		 314 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
315 void *ctx;
316 if (tag >= nvmeq->q_depth) {
317 *fn = special_completion;
318 return CMD_CTX_INVALID;
319 }
320 if (fn)
321 *fn = cmd->fn;
322 ctx = cmd->ctx;
323 cmd->fn = special_completion;
324 cmd->ctx = CMD_CTX_COMPLETED;
325 return ctx;
b60503ba
MW		 326}
327
328/**
714a7a22 329 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 330 * @nvmeq: The queue to use
331 * @cmd: The command to send
332 *
333 * Safe to use from interrupt context
334 */
a4aea562 335static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 336{
a4aea562
MB		 337 u16 tail = nvmeq->sq_tail;
338
b60503ba 339 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 340 if (++tail == nvmeq->q_depth)
341 tail = 0;
7547881d 342 writel(tail, nvmeq->q_db);
b60503ba 343 nvmeq->sq_tail = tail;
b60503ba
MW		 344
345 return 0;
346}
347
a4aea562
MB		 348static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
349{
350 unsigned long flags;
351 int ret;
352 spin_lock_irqsave(&nvmeq->q_lock, flags);
353 ret = __nvme_submit_cmd(nvmeq, cmd);
354 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
355 return ret;
356}
357
eca18b23 358static __le64 **iod_list(struct nvme_iod *iod)
e025344c 359{
eca18b23 360 return ((void *)iod) + iod->offset;
e025344c
SMM		 361}
362
eca18b23
MW		 363/*
364 * Will slightly overestimate the number of pages needed. This is OK
365 * as it only leads to a small amount of wasted memory for the lifetime of
366 * the I/O.
367 */
1d090624 368static int nvme_npages(unsigned size, struct nvme_dev *dev)
eca18b23 369{
1d090624
KB		 370 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
371 return DIV_ROUND_UP(8 * nprps, dev->page_size - 8);
eca18b23 372}
b60503ba 373
eca18b23 374static struct nvme_iod *
1d090624 375nvme_alloc_iod(unsigned nseg, unsigned nbytes, struct nvme_dev *dev, gfp_t gfp)
b60503ba 376{
eca18b23 377 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
1d090624 378 sizeof(__le64 *) * nvme_npages(nbytes, dev) +
eca18b23
MW		 379 sizeof(struct scatterlist) * nseg, gfp);
380
381 if (iod) {
382 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
383 iod->npages = -1;
384 iod->length = nbytes;
2b196034 385 iod->nents = 0;
edd10d33 386 iod->first_dma = 0ULL;
eca18b23
MW		 387 }
388
389 return iod;
b60503ba
MW		 390}
391
5d0f6131 392void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 393{
1d090624 394 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 395 int i;
396 __le64 **list = iod_list(iod);
397 dma_addr_t prp_dma = iod->first_dma;
398
399 if (iod->npages == 0)
400 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
401 for (i = 0; i < iod->npages; i++) {
402 __le64 *prp_list = list[i];
403 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
404 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
405 prp_dma = next_prp_dma;
406 }
407 kfree(iod);
b60503ba
MW		 408}
409
b4ff9c8d
KB		 410static int nvme_error_status(u16 status)
411{
412 switch (status & 0x7ff) {
413 case NVME_SC_SUCCESS:
414 return 0;
415 case NVME_SC_CAP_EXCEEDED:
416 return -ENOSPC;
417 default:
418 return -EIO;
419 }
420}
421
a4aea562 422static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 423 struct nvme_completion *cqe)
424{
eca18b23 425 struct nvme_iod *iod = ctx;
a4aea562
MB		 426 struct request *req = iod->private;
427 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
428
b60503ba
MW		 429 u16 status = le16_to_cpup(&cqe->status) >> 1;
430
edd10d33 431 if (unlikely(status)) {
a4aea562
MB		 432 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
433 && (jiffies - req->start_time) < req->timeout) {
434 blk_mq_requeue_request(req);
435 blk_mq_kick_requeue_list(req->q);
edd10d33
KB		 436 return;
437 }
a4aea562
MB		 438 req->errors = nvme_error_status(status);
439 } else
440 req->errors = 0;
441
442 if (cmd_rq->aborted)
443 dev_warn(&nvmeq->dev->pci_dev->dev,
444 "completing aborted command with status:%04x\n",
445 status);
446
447 if (iod->nents)
448 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
449 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
edd10d33 450 nvme_free_iod(nvmeq->dev, iod);
3291fa57 451
a4aea562 452 blk_mq_complete_request(req);
b60503ba
MW		 453}
454
184d2944 455/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 456int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
457 gfp_t gfp)
ff22b54f 458{
99802a7a 459 struct dma_pool *pool;
eca18b23
MW		 460 int length = total_len;
461 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 462 int dma_len = sg_dma_len(sg);
463 u64 dma_addr = sg_dma_address(sg);
464 int offset = offset_in_page(dma_addr);
e025344c 465 __le64 *prp_list;
eca18b23 466 __le64 **list = iod_list(iod);
e025344c 467 dma_addr_t prp_dma;
eca18b23 468 int nprps, i;
1d090624 469 u32 page_size = dev->page_size;
ff22b54f 470
1d090624 471 length -= (page_size - offset);
ff22b54f 472 if (length <= 0)
eca18b23 473 return total_len;
ff22b54f 474
1d090624 475 dma_len -= (page_size - offset);
ff22b54f 476 if (dma_len) {
1d090624 477 dma_addr += (page_size - offset);
ff22b54f
MW		 478 } else {
479 sg = sg_next(sg);
480 dma_addr = sg_dma_address(sg);
481 dma_len = sg_dma_len(sg);
482 }
483
1d090624 484 if (length <= page_size) {
edd10d33 485 iod->first_dma = dma_addr;
eca18b23 486 return total_len;
e025344c
SMM		 487 }
488
1d090624 489 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 490 if (nprps <= (256 / 8)) {
491 pool = dev->prp_small_pool;
eca18b23 492 iod->npages = 0;
99802a7a
MW		 493 } else {
494 pool = dev->prp_page_pool;
eca18b23 495 iod->npages = 1;
99802a7a
MW		 496 }
497
b77954cb
MW		 498 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
499 if (!prp_list) {
edd10d33 500 iod->first_dma = dma_addr;
eca18b23 501 iod->npages = -1;
1d090624 502 return (total_len - length) + page_size;
b77954cb 503 }
eca18b23
MW		 504 list[0] = prp_list;
505 iod->first_dma = prp_dma;
e025344c
SMM		 506 i = 0;
507 for (;;) {
1d090624 508 if (i == page_size >> 3) {
e025344c 509 __le64 *old_prp_list = prp_list;
b77954cb 510 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 511 if (!prp_list)
512 return total_len - length;
513 list[iod->npages++] = prp_list;
7523d834
MW		 514 prp_list[0] = old_prp_list[i - 1];
515 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
516 i = 1;
e025344c
SMM		 517 }
518 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 519 dma_len -= page_size;
520 dma_addr += page_size;
521 length -= page_size;
e025344c
SMM		 522 if (length <= 0)
523 break;
524 if (dma_len > 0)
525 continue;
526 BUG_ON(dma_len < 0);
527 sg = sg_next(sg);
528 dma_addr = sg_dma_address(sg);
529 dma_len = sg_dma_len(sg);
ff22b54f
MW		 530 }
531
eca18b23 532 return total_len;
ff22b54f
MW		 533}
534
a4aea562
MB		 535/*
536 * We reuse the small pool to allocate the 16-byte range here as it is not
537 * worth having a special pool for these or additional cases to handle freeing
538 * the iod.
539 */
540static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
541 struct request *req, struct nvme_iod *iod)
0e5e4f0e 542{
edd10d33
KB		 543 struct nvme_dsm_range *range =
544 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 545 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
546
0e5e4f0e 547 range->cattr = cpu_to_le32(0);
a4aea562
MB		 548 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
549 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e
KB		 550
551 memset(cmnd, 0, sizeof(*cmnd));
552 cmnd->dsm.opcode = nvme_cmd_dsm;
a4aea562 553 cmnd->dsm.command_id = req->tag;
0e5e4f0e
KB		 554 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
555 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
556 cmnd->dsm.nr = 0;
557 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
558
559 if (++nvmeq->sq_tail == nvmeq->q_depth)
560 nvmeq->sq_tail = 0;
561 writel(nvmeq->sq_tail, nvmeq->q_db);
0e5e4f0e
KB		 562}
563
a4aea562 564static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 565 int cmdid)
566{
567 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
568
569 memset(cmnd, 0, sizeof(*cmnd));
570 cmnd->common.opcode = nvme_cmd_flush;
571 cmnd->common.command_id = cmdid;
572 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
573
574 if (++nvmeq->sq_tail == nvmeq->q_depth)
575 nvmeq->sq_tail = 0;
576 writel(nvmeq->sq_tail, nvmeq->q_db);
00df5cb4
MW		 577}
578
a4aea562
MB		 579static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
580 struct nvme_ns *ns)
b60503ba 581{
a4aea562 582 struct request *req = iod->private;
ff22b54f 583 struct nvme_command *cmnd;
a4aea562
MB		 584 u16 control = 0;
585 u32 dsmgmt = 0;
00df5cb4 586
a4aea562 587 if (req->cmd_flags & REQ_FUA)
b60503ba 588 control |= NVME_RW_FUA;
a4aea562 589 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 590 control |= NVME_RW_LR;
591
a4aea562 592 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 593 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
594
ff22b54f 595 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 596 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 597
a4aea562
MB		 598 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
599 cmnd->rw.command_id = req->tag;
ff22b54f 600 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 601 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
602 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
a4aea562
MB		 603 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
604 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
ff22b54f
MW		 605 cmnd->rw.control = cpu_to_le16(control);
606 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 607
b60503ba
MW		 608 if (++nvmeq->sq_tail == nvmeq->q_depth)
609 nvmeq->sq_tail = 0;
7547881d 610 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 611
1974b1ae 612 return 0;
edd10d33
KB		 613}
614
a4aea562
MB		 615static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
616 const struct blk_mq_queue_data *bd)
edd10d33 617{
a4aea562
MB		 618 struct nvme_ns *ns = hctx->queue->queuedata;
619 struct nvme_queue *nvmeq = hctx->driver_data;
620 struct request *req = bd->rq;
621 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 622 struct nvme_iod *iod;
a4aea562 623 int psegs = req->nr_phys_segments;
a4aea562
MB		 624 enum dma_data_direction dma_dir;
625 unsigned size = !(req->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(req) :
9dbbfab7 626 sizeof(struct nvme_dsm_range);
edd10d33 627
9dbbfab7 628 iod = nvme_alloc_iod(psegs, size, ns->dev, GFP_ATOMIC);
edd10d33 629 if (!iod)
fe54303e 630 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562
MB		 631
632 iod->private = req;
edd10d33 633
a4aea562 634 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 635 void *range;
636 /*
637 * We reuse the small pool to allocate the 16-byte range here
638 * as it is not worth having a special pool for these or
639 * additional cases to handle freeing the iod.
640 */
641 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
642 GFP_ATOMIC,
643 &iod->first_dma);
a4aea562 644 if (!range)
fe54303e 645 goto retry_cmd;
edd10d33
KB		 646 iod_list(iod)[0] = (__le64 *)range;
647 iod->npages = 0;
648 } else if (psegs) {
a4aea562
MB		 649 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
650
651 sg_init_table(iod->sg, psegs);
652 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 653 if (!iod->nents)
654 goto error_cmd;
a4aea562
MB		 655
656 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 657 goto retry_cmd;
a4aea562 658
fe54303e
JA		 659 if (blk_rq_bytes(req) !=
660 nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
661 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg,
662 iod->nents, dma_dir);
663 goto retry_cmd;
664 }
edd10d33 665 }
1974b1ae 666
a4aea562
MB		 667 blk_mq_start_request(req);
668
9af8785a 669 nvme_set_info(cmd, iod, req_completion);
a4aea562
MB		 670 spin_lock_irq(&nvmeq->q_lock);
671 if (req->cmd_flags & REQ_DISCARD)
672 nvme_submit_discard(nvmeq, ns, req, iod);
673 else if (req->cmd_flags & REQ_FLUSH)
674 nvme_submit_flush(nvmeq, ns, req->tag);
675 else
676 nvme_submit_iod(nvmeq, iod, ns);
677
678 nvme_process_cq(nvmeq);
679 spin_unlock_irq(&nvmeq->q_lock);
680 return BLK_MQ_RQ_QUEUE_OK;
681
fe54303e
JA		 682 error_cmd:
683 nvme_free_iod(nvmeq->dev, iod);
684 return BLK_MQ_RQ_QUEUE_ERROR;
685 retry_cmd:
eca18b23 686 nvme_free_iod(nvmeq->dev, iod);
fe54303e 687 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 688}
689
e9539f47 690static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 691{
82123460 692 u16 head, phase;
b60503ba 693
b60503ba 694 head = nvmeq->cq_head;
82123460 695 phase = nvmeq->cq_phase;
b60503ba
MW		 696
697 for (;;) {
c2f5b650
MW		 698 void *ctx;
699 nvme_completion_fn fn;
b60503ba 700 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 701 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 702 break;
703 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
704 if (++head == nvmeq->q_depth) {
705 head = 0;
82123460 706 phase = !phase;
b60503ba 707 }
a4aea562 708 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 709 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 710 }
711
712 /* If the controller ignores the cq head doorbell and continuously
713 * writes to the queue, it is theoretically possible to wrap around
714 * the queue twice and mistakenly return IRQ_NONE. Linux only
715 * requires that 0.1% of your interrupts are handled, so this isn't
716 * a big problem.
717 */
82123460 718 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 719 return 0;
b60503ba 720
b80d5ccc 721 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 722 nvmeq->cq_head = head;
82123460 723 nvmeq->cq_phase = phase;
b60503ba 724
e9539f47
MW		 725 nvmeq->cqe_seen = 1;
726 return 1;
b60503ba
MW		 727}
728
a4aea562
MB		 729/* Admin queue isn't initialized as a request queue. If at some point this
730 * happens anyway, make sure to notify the user */
731static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
732 const struct blk_mq_queue_data *bd)
7d822457 733{
a4aea562
MB		 734 WARN_ON_ONCE(1);
735 return BLK_MQ_RQ_QUEUE_ERROR;
7d822457
MW		 736}
737
b60503ba 738static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 739{
740 irqreturn_t result;
741 struct nvme_queue *nvmeq = data;
742 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 743 nvme_process_cq(nvmeq);
744 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
745 nvmeq->cqe_seen = 0;
58ffacb5
MW		 746 spin_unlock(&nvmeq->q_lock);
747 return result;
748}
749
750static irqreturn_t nvme_irq_check(int irq, void *data)
751{
752 struct nvme_queue *nvmeq = data;
753 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
754 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
755 return IRQ_NONE;
756 return IRQ_WAKE_THREAD;
757}
758
a4aea562
MB		 759static void nvme_abort_cmd_info(struct nvme_queue *nvmeq, struct nvme_cmd_info *
760 cmd_info)
3c0cf138
MW		 761{
762 spin_lock_irq(&nvmeq->q_lock);
a4aea562 763 cancel_cmd_info(cmd_info, NULL);
3c0cf138
MW		 764 spin_unlock_irq(&nvmeq->q_lock);
765}
766
c2f5b650
MW		 767struct sync_cmd_info {
768 struct task_struct *task;
769 u32 result;
770 int status;
771};
772
edd10d33 773static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 774 struct nvme_completion *cqe)
775{
776 struct sync_cmd_info *cmdinfo = ctx;
777 cmdinfo->result = le32_to_cpup(&cqe->result);
778 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
779 wake_up_process(cmdinfo->task);
780}
781
b60503ba
MW		 782/*
783 * Returns 0 on success. If the result is negative, it's a Linux error code;
784 * if the result is positive, it's an NVM Express status code
785 */
a4aea562 786static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
5d0f6131 787 u32 *result, unsigned timeout)
b60503ba 788{
a4aea562 789 int ret;
b60503ba 790 struct sync_cmd_info cmdinfo;
a4aea562
MB		 791 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
792 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
b60503ba
MW		 793
794 cmdinfo.task = current;
795 cmdinfo.status = -EINTR;
796
a4aea562
MB		 797 cmd->common.command_id = req->tag;
798
799 nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
b60503ba 800
3c0cf138 801 set_current_state(TASK_KILLABLE);
4f5099af
KB		 802 ret = nvme_submit_cmd(nvmeq, cmd);
803 if (ret) {
a4aea562 804 nvme_finish_cmd(nvmeq, req->tag, NULL);
4f5099af 805 set_current_state(TASK_RUNNING);
4f5099af 806 }
849c6e77 807 ret = schedule_timeout(timeout);
b60503ba 808
849c6e77
JA		 809 /*
810 * Ensure that sync_completion has either run, or that it will
811 * never run.
812 */
813 nvme_abort_cmd_info(nvmeq, blk_mq_rq_to_pdu(req));
814
815 /*
816 * We never got the completion
817 */
818 if (cmdinfo.status == -EINTR)
3c0cf138 819 return -EINTR;
3c0cf138 820
b60503ba
MW		 821 if (result)
822 *result = cmdinfo.result;
823
824 return cmdinfo.status;
825}
826
a4aea562
MB		 827static int nvme_submit_async_admin_req(struct nvme_dev *dev)
828{
829 struct nvme_queue *nvmeq = dev->queues[0];
830 struct nvme_command c;
831 struct nvme_cmd_info *cmd_info;
832 struct request *req;
833
6dcc0cf6 834 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false);
9f173b33
DC		 835 if (IS_ERR(req))
836 return PTR_ERR(req);
a4aea562
MB		 837
838 cmd_info = blk_mq_rq_to_pdu(req);
839 nvme_set_info(cmd_info, req, async_req_completion);
840
841 memset(&c, 0, sizeof(c));
842 c.common.opcode = nvme_admin_async_event;
843 c.common.command_id = req->tag;
844
845 return __nvme_submit_cmd(nvmeq, &c);
846}
847
848static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 849 struct nvme_command *cmd,
850 struct async_cmd_info *cmdinfo, unsigned timeout)
851{
a4aea562
MB		 852 struct nvme_queue *nvmeq = dev->queues[0];
853 struct request *req;
854 struct nvme_cmd_info *cmd_rq;
4d115420 855
a4aea562 856 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 857 if (IS_ERR(req))
858 return PTR_ERR(req);
a4aea562
MB		 859
860 req->timeout = timeout;
861 cmd_rq = blk_mq_rq_to_pdu(req);
862 cmdinfo->req = req;
863 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 864 cmdinfo->status = -EINTR;
a4aea562
MB		 865
866 cmd->common.command_id = req->tag;
867
4f5099af 868 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 869}
870
a64e6bb4 871static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
a4aea562 872 u32 *result, unsigned timeout)
b60503ba 873{
a4aea562
MB		 874 int res;
875 struct request *req;
876
877 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
97fe3832
JA		 878 if (IS_ERR(req))
879 return PTR_ERR(req);
a4aea562 880 res = nvme_submit_sync_cmd(req, cmd, result, timeout);
9d135bb8 881 blk_mq_free_request(req);
a4aea562 882 return res;
4f5099af
KB		 883}
884
a4aea562 885int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
4f5099af
KB		 886 u32 *result)
887{
a4aea562 888 return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 889}
890
a4aea562
MB		 891int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
892 struct nvme_command *cmd, u32 *result)
4d115420 893{
a4aea562
MB		 894 int res;
895 struct request *req;
896
897 req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
898 false);
97fe3832
JA		 899 if (IS_ERR(req))
900 return PTR_ERR(req);
a4aea562 901 res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
9d135bb8 902 blk_mq_free_request(req);
a4aea562 903 return res;
4d115420
KB		 904}
905
b60503ba
MW		 906static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
907{
b60503ba
MW		 908 struct nvme_command c;
909
910 memset(&c, 0, sizeof(c));
911 c.delete_queue.opcode = opcode;
912 c.delete_queue.qid = cpu_to_le16(id);
913
a4aea562 914 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 915}
916
917static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
918 struct nvme_queue *nvmeq)
919{
b60503ba
MW		 920 struct nvme_command c;
921 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
922
923 memset(&c, 0, sizeof(c));
924 c.create_cq.opcode = nvme_admin_create_cq;
925 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
926 c.create_cq.cqid = cpu_to_le16(qid);
927 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
928 c.create_cq.cq_flags = cpu_to_le16(flags);
929 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
930
a4aea562 931 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 932}
933
934static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
935 struct nvme_queue *nvmeq)
936{
b60503ba
MW		 937 struct nvme_command c;
938 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
939
940 memset(&c, 0, sizeof(c));
941 c.create_sq.opcode = nvme_admin_create_sq;
942 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
943 c.create_sq.sqid = cpu_to_le16(qid);
944 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
945 c.create_sq.sq_flags = cpu_to_le16(flags);
946 c.create_sq.cqid = cpu_to_le16(qid);
947
a4aea562 948 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 949}
950
951static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
952{
953 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
954}
955
956static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
957{
958 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
959}
960
5d0f6131 961int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 962 dma_addr_t dma_addr)
963{
964 struct nvme_command c;
965
966 memset(&c, 0, sizeof(c));
967 c.identify.opcode = nvme_admin_identify;
968 c.identify.nsid = cpu_to_le32(nsid);
969 c.identify.prp1 = cpu_to_le64(dma_addr);
970 c.identify.cns = cpu_to_le32(cns);
971
972 return nvme_submit_admin_cmd(dev, &c, NULL);
973}
974
5d0f6131 975int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 976 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 977{
978 struct nvme_command c;
979
980 memset(&c, 0, sizeof(c));
981 c.features.opcode = nvme_admin_get_features;
a42cecce 982 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 983 c.features.prp1 = cpu_to_le64(dma_addr);
984 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 985
08df1e05 986 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 987}
988
5d0f6131
VV		 989int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
990 dma_addr_t dma_addr, u32 *result)
df348139
MW		 991{
992 struct nvme_command c;
993
994 memset(&c, 0, sizeof(c));
995 c.features.opcode = nvme_admin_set_features;
996 c.features.prp1 = cpu_to_le64(dma_addr);
997 c.features.fid = cpu_to_le32(fid);
998 c.features.dword11 = cpu_to_le32(dword11);
999
bc5fc7e4
MW		 1000 return nvme_submit_admin_cmd(dev, &c, result);
1001}
1002
c30341dc 1003/**
a4aea562 1004 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1005 *
1006 * Schedule controller reset if the command was already aborted once before and
1007 * still hasn't been returned to the driver, or if this is the admin queue.
1008 */
a4aea562 1009static void nvme_abort_req(struct request *req)
c30341dc 1010{
a4aea562
MB		 1011 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1012 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1013 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1014 struct request *abort_req;
1015 struct nvme_cmd_info *abort_cmd;
1016 struct nvme_command cmd;
c30341dc 1017
a4aea562 1018 if (!nvmeq->qid || cmd_rq->aborted) {
c30341dc
KB		 1019 if (work_busy(&dev->reset_work))
1020 return;
1021 list_del_init(&dev->node);
1022 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1023 "I/O %d QID %d timeout, reset controller\n",
1024 req->tag, nvmeq->qid);
9ca97374 1025 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc
KB		 1026 queue_work(nvme_workq, &dev->reset_work);
1027 return;
1028 }
1029
1030 if (!dev->abort_limit)
1031 return;
1032
a4aea562
MB		 1033 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1034 false);
9f173b33 1035 if (IS_ERR(abort_req))
c30341dc
KB		 1036 return;
1037
a4aea562
MB		 1038 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1039 nvme_set_info(abort_cmd, abort_req, abort_completion);
1040
c30341dc
KB		 1041 memset(&cmd, 0, sizeof(cmd));
1042 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1043 cmd.abort.cid = req->tag;
c30341dc 1044 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1045 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1046
1047 --dev->abort_limit;
a4aea562 1048 cmd_rq->aborted = 1;
c30341dc 1049
a4aea562 1050 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1051 nvmeq->qid);
a4aea562
MB		 1052 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1053 dev_warn(nvmeq->q_dmadev,
1054 "Could not abort I/O %d QID %d",
1055 req->tag, nvmeq->qid);
c87fd540 1056 blk_mq_free_request(abort_req);
a4aea562 1057 }
c30341dc
KB		 1058}
1059
a4aea562
MB		 1060static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1061 struct request *req, void *data, bool reserved)
a09115b2 1062{
a4aea562
MB		 1063 struct nvme_queue *nvmeq = data;
1064 void *ctx;
1065 nvme_completion_fn fn;
1066 struct nvme_cmd_info *cmd;
1067 static struct nvme_completion cqe = {
1068 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
1069 };
a09115b2 1070
a4aea562 1071 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1072
a4aea562
MB		 1073 if (cmd->ctx == CMD_CTX_CANCELLED)
1074 return;
1075
1076 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1077 req->tag, nvmeq->qid);
1078 ctx = cancel_cmd_info(cmd, &fn);
1079 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1080}
1081
a4aea562 1082static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1083{
a4aea562
MB		 1084 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1085 struct nvme_queue *nvmeq = cmd->nvmeq;
1086
1087 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1088 nvmeq->qid);
1089 if (nvmeq->dev->initialized)
1090 nvme_abort_req(req);
1091
1092 /*
1093 * The aborted req will be completed on receiving the abort req.
1094 * We enable the timer again. If hit twice, it'll cause a device reset,
1095 * as the device then is in a faulty state.
1096 */
1097 return BLK_EH_RESET_TIMER;
1098}
22404274 1099
a4aea562
MB		 1100static void nvme_free_queue(struct nvme_queue *nvmeq)
1101{
9e866774
MW		 1102 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1103 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1104 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1105 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1106 kfree(nvmeq);
1107}
1108
a1a5ef99 1109static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1110{
1111 int i;
1112
a1a5ef99 1113 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1114 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1115 dev->queue_count--;
a4aea562 1116 dev->queues[i] = NULL;
f435c282 1117 nvme_free_queue(nvmeq);
121c7ad4 1118 }
22404274
KB		 1119}
1120
4d115420
KB		 1121/**
1122 * nvme_suspend_queue - put queue into suspended state
1123 * @nvmeq - queue to suspend
4d115420
KB		 1124 */
1125static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1126{
2b25d981 1127 int vector;
b60503ba 1128
a09115b2 1129 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1130 if (nvmeq->cq_vector == -1) {
1131 spin_unlock_irq(&nvmeq->q_lock);
1132 return 1;
1133 }
1134 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1135 nvmeq->dev->online_queues--;
2b25d981 1136 nvmeq->cq_vector = -1;
a09115b2
MW		 1137 spin_unlock_irq(&nvmeq->q_lock);
1138
aba2080f
MW		 1139 irq_set_affinity_hint(vector, NULL);
1140 free_irq(vector, nvmeq);
b60503ba 1141
4d115420
KB		 1142 return 0;
1143}
b60503ba 1144
4d115420
KB		 1145static void nvme_clear_queue(struct nvme_queue *nvmeq)
1146{
a4aea562
MB		 1147 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1148
22404274
KB		 1149 spin_lock_irq(&nvmeq->q_lock);
1150 nvme_process_cq(nvmeq);
a4aea562
MB		 1151 if (hctx && hctx->tags)
1152 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
22404274 1153 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1154}
1155
4d115420
KB		 1156static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1157{
a4aea562 1158 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1159
1160 if (!nvmeq)
1161 return;
1162 if (nvme_suspend_queue(nvmeq))
1163 return;
1164
0e53d180
KB		 1165 /* Don't tell the adapter to delete the admin queue.
1166 * Don't tell a removed adapter to delete IO queues. */
1167 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1168 adapter_delete_sq(dev, qid);
1169 adapter_delete_cq(dev, qid);
1170 }
4d115420 1171 nvme_clear_queue(nvmeq);
b60503ba
MW		 1172}
1173
1174static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1175 int depth)
b60503ba
MW		 1176{
1177 struct device *dmadev = &dev->pci_dev->dev;
a4aea562 1178 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1179 if (!nvmeq)
1180 return NULL;
1181
4d51abf9
JP		 1182 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1183 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1184 if (!nvmeq->cqes)
1185 goto free_nvmeq;
b60503ba
MW		 1186
1187 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1188 &nvmeq->sq_dma_addr, GFP_KERNEL);
1189 if (!nvmeq->sq_cmds)
1190 goto free_cqdma;
1191
1192 nvmeq->q_dmadev = dmadev;
091b6092 1193 nvmeq->dev = dev;
3193f07b
MW		 1194 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1195 dev->instance, qid);
b60503ba
MW		 1196 spin_lock_init(&nvmeq->q_lock);
1197 nvmeq->cq_head = 0;
82123460 1198 nvmeq->cq_phase = 1;
b80d5ccc 1199 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1200 nvmeq->q_depth = depth;
c30341dc 1201 nvmeq->qid = qid;
22404274 1202 dev->queue_count++;
a4aea562 1203 dev->queues[qid] = nvmeq;
b60503ba
MW		 1204
1205 return nvmeq;
1206
1207 free_cqdma:
68b8eca5 1208 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1209 nvmeq->cq_dma_addr);
1210 free_nvmeq:
1211 kfree(nvmeq);
1212 return NULL;
1213}
1214
3001082c
MW		 1215static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1216 const char *name)
1217{
58ffacb5
MW		 1218 if (use_threaded_interrupts)
1219 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1220 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1221 name, nvmeq);
3001082c 1222 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1223 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1224}
1225
22404274 1226static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1227{
22404274 1228 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1229
7be50e93 1230 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1231 nvmeq->sq_tail = 0;
1232 nvmeq->cq_head = 0;
1233 nvmeq->cq_phase = 1;
b80d5ccc 1234 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1235 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1236 dev->online_queues++;
7be50e93 1237 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1238}
1239
1240static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1241{
1242 struct nvme_dev *dev = nvmeq->dev;
1243 int result;
3f85d50b 1244
2b25d981 1245 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1246 result = adapter_alloc_cq(dev, qid, nvmeq);
1247 if (result < 0)
22404274 1248 return result;
b60503ba
MW		 1249
1250 result = adapter_alloc_sq(dev, qid, nvmeq);
1251 if (result < 0)
1252 goto release_cq;
1253
3193f07b 1254 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1255 if (result < 0)
1256 goto release_sq;
1257
22404274 1258 nvme_init_queue(nvmeq, qid);
22404274 1259 return result;
b60503ba
MW		 1260
1261 release_sq:
1262 adapter_delete_sq(dev, qid);
1263 release_cq:
1264 adapter_delete_cq(dev, qid);
22404274 1265 return result;
b60503ba
MW		 1266}
1267
ba47e386
MW		 1268static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1269{
1270 unsigned long timeout;
1271 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1272
1273 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1274
1275 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1276 msleep(100);
1277 if (fatal_signal_pending(current))
1278 return -EINTR;
1279 if (time_after(jiffies, timeout)) {
1280 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1281 "Device not ready; aborting %s\n", enabled ?
1282 "initialisation" : "reset");
ba47e386
MW		 1283 return -ENODEV;
1284 }
1285 }
1286
1287 return 0;
1288}
1289
1290/*
1291 * If the device has been passed off to us in an enabled state, just clear
1292 * the enabled bit. The spec says we should set the 'shutdown notification
1293 * bits', but doing so may cause the device to complete commands to the
1294 * admin queue ... and we don't know what memory that might be pointing at!
1295 */
1296static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1297{
01079522
DM		 1298 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1299 dev->ctrl_config &= ~NVME_CC_ENABLE;
1300 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1301
ba47e386
MW		 1302 return nvme_wait_ready(dev, cap, false);
1303}
1304
1305static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1306{
01079522
DM		 1307 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1308 dev->ctrl_config |= NVME_CC_ENABLE;
1309 writel(dev->ctrl_config, &dev->bar->cc);
1310
ba47e386
MW		 1311 return nvme_wait_ready(dev, cap, true);
1312}
1313
1894d8f1
KB		 1314static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1315{
1316 unsigned long timeout;
1894d8f1 1317
01079522
DM		 1318 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1319 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1320
1321 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1322
2484f407 1323 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1324 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1325 NVME_CSTS_SHST_CMPLT) {
1326 msleep(100);
1327 if (fatal_signal_pending(current))
1328 return -EINTR;
1329 if (time_after(jiffies, timeout)) {
1330 dev_err(&dev->pci_dev->dev,
1331 "Device shutdown incomplete; abort shutdown\n");
1332 return -ENODEV;
1333 }
1334 }
1335
1336 return 0;
1337}
1338
a4aea562
MB		 1339static struct blk_mq_ops nvme_mq_admin_ops = {
1340 .queue_rq = nvme_admin_queue_rq,
1341 .map_queue = blk_mq_map_queue,
1342 .init_hctx = nvme_admin_init_hctx,
2c30540b 1343 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1344 .init_request = nvme_admin_init_request,
1345 .timeout = nvme_timeout,
1346};
1347
1348static struct blk_mq_ops nvme_mq_ops = {
1349 .queue_rq = nvme_queue_rq,
1350 .map_queue = blk_mq_map_queue,
1351 .init_hctx = nvme_init_hctx,
2c30540b 1352 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1353 .init_request = nvme_init_request,
1354 .timeout = nvme_timeout,
1355};
1356
1357static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1358{
1359 if (!dev->admin_q) {
1360 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1361 dev->admin_tagset.nr_hw_queues = 1;
1362 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1363 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1364 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
1365 dev->admin_tagset.cmd_size = sizeof(struct nvme_cmd_info);
1366 dev->admin_tagset.driver_data = dev;
1367
1368 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1369 return -ENOMEM;
1370
1371 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1372 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1373 blk_mq_free_tag_set(&dev->admin_tagset);
1374 return -ENOMEM;
1375 }
1376 }
1377
1378 return 0;
1379}
1380
1381static void nvme_free_admin_tags(struct nvme_dev *dev)
1382{
1383 if (dev->admin_q)
1384 blk_mq_free_tag_set(&dev->admin_tagset);
1385}
1386
8d85fce7 1387static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1388{
ba47e386 1389 int result;
b60503ba 1390 u32 aqa;
ba47e386 1391 u64 cap = readq(&dev->bar->cap);
b60503ba 1392 struct nvme_queue *nvmeq;
1d090624
KB		 1393 unsigned page_shift = PAGE_SHIFT;
1394 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1395 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1396
1397 if (page_shift < dev_page_min) {
1398 dev_err(&dev->pci_dev->dev,
1399 "Minimum device page size (%u) too large for "
1400 "host (%u)\n", 1 << dev_page_min,
1401 1 << page_shift);
1402 return -ENODEV;
1403 }
1404 if (page_shift > dev_page_max) {
1405 dev_info(&dev->pci_dev->dev,
1406 "Device maximum page size (%u) smaller than "
1407 "host (%u); enabling work-around\n",
1408 1 << dev_page_max, 1 << page_shift);
1409 page_shift = dev_page_max;
1410 }
b60503ba 1411
ba47e386
MW		 1412 result = nvme_disable_ctrl(dev, cap);
1413 if (result < 0)
1414 return result;
b60503ba 1415
a4aea562 1416 nvmeq = dev->queues[0];
cd638946 1417 if (!nvmeq) {
2b25d981 1418 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1419 if (!nvmeq)
1420 return -ENOMEM;
cd638946 1421 }
b60503ba
MW		 1422
1423 aqa = nvmeq->q_depth - 1;
1424 aqa |= aqa << 16;
1425
1d090624
KB		 1426 dev->page_size = 1 << page_shift;
1427
01079522 1428 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1429 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1430 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1431 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1432
1433 writel(aqa, &dev->bar->aqa);
1434 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1435 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1436
ba47e386 1437 result = nvme_enable_ctrl(dev, cap);
025c557a 1438 if (result)
a4aea562
MB		 1439 goto free_nvmeq;
1440
1441 result = nvme_alloc_admin_tags(dev);
1442 if (result)
1443 goto free_nvmeq;
9e866774 1444
2b25d981 1445 nvmeq->cq_vector = 0;
3193f07b 1446 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1447 if (result)
a4aea562 1448 goto free_tags;
025c557a 1449
b60503ba 1450 return result;
a4aea562
MB		 1451
1452 free_tags:
1453 nvme_free_admin_tags(dev);
1454 free_nvmeq:
1455 nvme_free_queues(dev, 0);
1456 return result;
b60503ba
MW		 1457}
1458
5d0f6131 1459struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1460 unsigned long addr, unsigned length)
b60503ba 1461{
36c14ed9 1462 int i, err, count, nents, offset;
7fc3cdab
MW		 1463 struct scatterlist *sg;
1464 struct page **pages;
eca18b23 1465 struct nvme_iod *iod;
36c14ed9
MW		 1466
1467 if (addr & 3)
eca18b23 1468 return ERR_PTR(-EINVAL);
5460fc03 1469 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1470 return ERR_PTR(-EINVAL);
7fc3cdab 1471
36c14ed9 1472 offset = offset_in_page(addr);
7fc3cdab
MW		 1473 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1474 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1475 if (!pages)
1476 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1477
1478 err = get_user_pages_fast(addr, count, 1, pages);
1479 if (err < count) {
1480 count = err;
1481 err = -EFAULT;
1482 goto put_pages;
1483 }
7fc3cdab 1484
6808c5fb 1485 err = -ENOMEM;
1d090624 1486 iod = nvme_alloc_iod(count, length, dev, GFP_KERNEL);
6808c5fb
S		 1487 if (!iod)
1488 goto put_pages;
1489
eca18b23 1490 sg = iod->sg;
36c14ed9 1491 sg_init_table(sg, count);
d0ba1e49
MW		 1492 for (i = 0; i < count; i++) {
1493 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1494 min_t(unsigned, length, PAGE_SIZE - offset),
1495 offset);
d0ba1e49
MW		 1496 length -= (PAGE_SIZE - offset);
1497 offset = 0;
7fc3cdab 1498 }
fe304c43 1499 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1500 iod->nents = count;
7fc3cdab 1501
7fc3cdab
MW		 1502 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1503 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1504 if (!nents)
eca18b23 1505 goto free_iod;
b60503ba 1506
7fc3cdab 1507 kfree(pages);
eca18b23 1508 return iod;
b60503ba 1509
eca18b23
MW		 1510 free_iod:
1511 kfree(iod);
7fc3cdab
MW		 1512 put_pages:
1513 for (i = 0; i < count; i++)
1514 put_page(pages[i]);
1515 kfree(pages);
eca18b23 1516 return ERR_PTR(err);
7fc3cdab 1517}
b60503ba 1518
5d0f6131 1519void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1520 struct nvme_iod *iod)
7fc3cdab 1521{
1c2ad9fa 1522 int i;
b60503ba 1523
1c2ad9fa
MW		 1524 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1525 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1526
1c2ad9fa
MW		 1527 for (i = 0; i < iod->nents; i++)
1528 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1529}
b60503ba 1530
a53295b6
MW		 1531static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1532{
1533 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1534 struct nvme_user_io io;
1535 struct nvme_command c;
f410c680
KB		 1536 unsigned length, meta_len;
1537 int status, i;
1538 struct nvme_iod *iod, *meta_iod = NULL;
1539 dma_addr_t meta_dma_addr;
1540 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1541
1542 if (copy_from_user(&io, uio, sizeof(io)))
1543 return -EFAULT;
6c7d4945 1544 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1545 meta_len = (io.nblocks + 1) * ns->ms;
1546
1547 if (meta_len && ((io.metadata & 3) || !io.metadata))
1548 return -EINVAL;
6c7d4945
MW		 1549
1550 switch (io.opcode) {
1551 case nvme_cmd_write:
1552 case nvme_cmd_read:
6bbf1acd 1553 case nvme_cmd_compare:
eca18b23 1554 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1555 break;
6c7d4945 1556 default:
6bbf1acd 1557 return -EINVAL;
6c7d4945
MW		 1558 }
1559
eca18b23
MW		 1560 if (IS_ERR(iod))
1561 return PTR_ERR(iod);
a53295b6
MW		 1562
1563 memset(&c, 0, sizeof(c));
1564 c.rw.opcode = io.opcode;
1565 c.rw.flags = io.flags;
6c7d4945 1566 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1567 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1568 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1569 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1570 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1571 c.rw.reftag = cpu_to_le32(io.reftag);
1572 c.rw.apptag = cpu_to_le16(io.apptag);
1573 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1574
1575 if (meta_len) {
1b56749e
KB		 1576 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1577 meta_len);
f410c680
KB		 1578 if (IS_ERR(meta_iod)) {
1579 status = PTR_ERR(meta_iod);
1580 meta_iod = NULL;
1581 goto unmap;
1582 }
1583
1584 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1585 &meta_dma_addr, GFP_KERNEL);
1586 if (!meta_mem) {
1587 status = -ENOMEM;
1588 goto unmap;
1589 }
1590
1591 if (io.opcode & 1) {
1592 int meta_offset = 0;
1593
1594 for (i = 0; i < meta_iod->nents; i++) {
1595 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1596 meta_iod->sg[i].offset;
1597 memcpy(meta_mem + meta_offset, meta,
1598 meta_iod->sg[i].length);
1599 kunmap_atomic(meta);
1600 meta_offset += meta_iod->sg[i].length;
1601 }
1602 }
1603
1604 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1605 }
1606
edd10d33
KB		 1607 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1608 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1609 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1610
b77954cb
MW		 1611 if (length != (io.nblocks + 1) << ns->lba_shift)
1612 status = -ENOMEM;
1613 else
a4aea562 1614 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
a53295b6 1615
f410c680
KB		 1616 if (meta_len) {
1617 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1618 int meta_offset = 0;
1619
1620 for (i = 0; i < meta_iod->nents; i++) {
1621 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1622 meta_iod->sg[i].offset;
1623 memcpy(meta, meta_mem + meta_offset,
1624 meta_iod->sg[i].length);
1625 kunmap_atomic(meta);
1626 meta_offset += meta_iod->sg[i].length;
1627 }
1628 }
1629
1630 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1631 meta_dma_addr);
1632 }
1633
1634 unmap:
1c2ad9fa 1635 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1636 nvme_free_iod(dev, iod);
f410c680
KB		 1637
1638 if (meta_iod) {
1639 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1640 nvme_free_iod(dev, meta_iod);
1641 }
1642
a53295b6
MW		 1643 return status;
1644}
1645
a4aea562
MB		 1646static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1647 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1648{
7963e521 1649 struct nvme_passthru_cmd cmd;
6ee44cdc 1650 struct nvme_command c;
eca18b23 1651 int status, length;
c7d36ab8 1652 struct nvme_iod *uninitialized_var(iod);
94f370ca 1653 unsigned timeout;
6ee44cdc 1654
6bbf1acd
MW		 1655 if (!capable(CAP_SYS_ADMIN))
1656 return -EACCES;
1657 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1658 return -EFAULT;
6ee44cdc
MW		 1659
1660 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1661 c.common.opcode = cmd.opcode;
1662 c.common.flags = cmd.flags;
1663 c.common.nsid = cpu_to_le32(cmd.nsid);
1664 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1665 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1666 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1667 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1668 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1669 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1670 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1671 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1672
1673 length = cmd.data_len;
1674 if (cmd.data_len) {
49742188
MW		 1675 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1676 length);
eca18b23
MW		 1677 if (IS_ERR(iod))
1678 return PTR_ERR(iod);
edd10d33
KB		 1679 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1680 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1681 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1682 }
1683
94f370ca
KB		 1684 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1685 ADMIN_TIMEOUT;
a4aea562 1686
6bbf1acd 1687 if (length != cmd.data_len)
b77954cb 1688 status = -ENOMEM;
a4aea562
MB		 1689 else if (ns) {
1690 struct request *req;
1691
1692 req = blk_mq_alloc_request(ns->queue, WRITE,
1693 (GFP_KERNEL|__GFP_WAIT), false);
97fe3832
JA		 1694 if (IS_ERR(req))
1695 status = PTR_ERR(req);
a4aea562
MB		 1696 else {
1697 status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1698 timeout);
9d135bb8 1699 blk_mq_free_request(req);
a4aea562
MB		 1700 }
1701 } else
1702 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
eca18b23 1703
6bbf1acd 1704 if (cmd.data_len) {
1c2ad9fa 1705 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1706 nvme_free_iod(dev, iod);
6bbf1acd 1707 }
f4f117f6 1708
cf90bc48 1709 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1710 sizeof(cmd.result)))
1711 status = -EFAULT;
1712
6ee44cdc
MW		 1713 return status;
1714}
1715
b60503ba
MW		 1716static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1717 unsigned long arg)
1718{
1719 struct nvme_ns *ns = bdev->bd_disk->private_data;
1720
1721 switch (cmd) {
6bbf1acd 1722 case NVME_IOCTL_ID:
c3bfe717 1723 force_successful_syscall_return();
6bbf1acd
MW		 1724 return ns->ns_id;
1725 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1726 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1727 case NVME_IOCTL_IO_CMD:
a4aea562 1728 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1729 case NVME_IOCTL_SUBMIT_IO:
1730 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1731 case SG_GET_VERSION_NUM:
1732 return nvme_sg_get_version_num((void __user *)arg);
1733 case SG_IO:
1734 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1735 default:
1736 return -ENOTTY;
1737 }
1738}
1739
320a3827
KB		 1740#ifdef CONFIG_COMPAT
1741static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1742 unsigned int cmd, unsigned long arg)
1743{
320a3827
KB		 1744 switch (cmd) {
1745 case SG_IO:
e179729a 1746 return -ENOIOCTLCMD;
320a3827
KB		 1747 }
1748 return nvme_ioctl(bdev, mode, cmd, arg);
1749}
1750#else
1751#define nvme_compat_ioctl NULL
1752#endif
1753
9ac27090
KB		 1754static int nvme_open(struct block_device *bdev, fmode_t mode)
1755{
9e60352c
KB		 1756 int ret = 0;
1757 struct nvme_ns *ns;
9ac27090 1758
9e60352c
KB		 1759 spin_lock(&dev_list_lock);
1760 ns = bdev->bd_disk->private_data;
1761 if (!ns)
1762 ret = -ENXIO;
1763 else if (!kref_get_unless_zero(&ns->dev->kref))
1764 ret = -ENXIO;
1765 spin_unlock(&dev_list_lock);
1766
1767 return ret;
9ac27090
KB		 1768}
1769
1770static void nvme_free_dev(struct kref *kref);
1771
1772static void nvme_release(struct gendisk *disk, fmode_t mode)
1773{
1774 struct nvme_ns *ns = disk->private_data;
1775 struct nvme_dev *dev = ns->dev;
1776
1777 kref_put(&dev->kref, nvme_free_dev);
1778}
1779
4cc09e2d
KB		 1780static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1781{
1782 /* some standard values */
1783 geo->heads = 1 << 6;
1784 geo->sectors = 1 << 5;
1785 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1786 return 0;
1787}
1788
1b9dbf7f
KB		 1789static int nvme_revalidate_disk(struct gendisk *disk)
1790{
1791 struct nvme_ns *ns = disk->private_data;
1792 struct nvme_dev *dev = ns->dev;
1793 struct nvme_id_ns *id;
1794 dma_addr_t dma_addr;
1795 int lbaf;
1796
1797 id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
1798 GFP_KERNEL);
1799 if (!id) {
1800 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
1801 __func__);
1802 return 0;
1803 }
1804
1805 if (nvme_identify(dev, ns->ns_id, 0, dma_addr))
1806 goto free;
1807
1808 lbaf = id->flbas & 0xf;
1809 ns->lba_shift = id->lbaf[lbaf].ds;
1810
1811 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1812 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1813 free:
1814 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1815 return 0;
1816}
1817
b60503ba
MW		 1818static const struct block_device_operations nvme_fops = {
1819 .owner = THIS_MODULE,
1820 .ioctl = nvme_ioctl,
320a3827 1821 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1822 .open = nvme_open,
1823 .release = nvme_release,
4cc09e2d 1824 .getgeo = nvme_getgeo,
1b9dbf7f 1825 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 1826};
1827
1fa6aead
MW		 1828static int nvme_kthread(void *data)
1829{
d4b4ff8e 1830 struct nvme_dev *dev, *next;
1fa6aead
MW		 1831
1832 while (!kthread_should_stop()) {
564a232c 1833 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1834 spin_lock(&dev_list_lock);
d4b4ff8e 1835 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1836 int i;
d4b4ff8e
KB		 1837 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1838 dev->initialized) {
1839 if (work_busy(&dev->reset_work))
1840 continue;
1841 list_del_init(&dev->node);
1842 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1843 "Failed status: %x, reset controller\n",
1844 readl(&dev->bar->csts));
9ca97374 1845 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 1846 queue_work(nvme_workq, &dev->reset_work);
1847 continue;
1848 }
1fa6aead 1849 for (i = 0; i < dev->queue_count; i++) {
a4aea562 1850 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 1851 if (!nvmeq)
1852 continue;
1fa6aead 1853 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 1854 nvme_process_cq(nvmeq);
6fccf938
KB		 1855
1856 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 1857 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 1858 break;
1859 dev->event_limit--;
1860 }
1fa6aead
MW		 1861 spin_unlock_irq(&nvmeq->q_lock);
1862 }
1863 }
1864 spin_unlock(&dev_list_lock);
acb7aa0d 1865 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1866 }
1867 return 0;
1868}
1869
0e5e4f0e
KB		 1870static void nvme_config_discard(struct nvme_ns *ns)
1871{
1872 u32 logical_block_size = queue_logical_block_size(ns->queue);
1873 ns->queue->limits.discard_zeroes_data = 0;
1874 ns->queue->limits.discard_alignment = logical_block_size;
1875 ns->queue->limits.discard_granularity = logical_block_size;
1876 ns->queue->limits.max_discard_sectors = 0xffffffff;
1877 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1878}
1879
c3bfe717 1880static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1881 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1882{
1883 struct nvme_ns *ns;
1884 struct gendisk *disk;
a4aea562 1885 int node = dev_to_node(&dev->pci_dev->dev);
b60503ba
MW		 1886 int lbaf;
1887
1888 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1889 return NULL;
1890
a4aea562 1891 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba
MW		 1892 if (!ns)
1893 return NULL;
a4aea562 1894 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 1895 if (IS_ERR(ns->queue))
b60503ba 1896 goto out_free_ns;
4eeb9215
MW		 1897 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1898 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 1899 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 1900 ns->dev = dev;
1901 ns->queue->queuedata = ns;
1902
a4aea562 1903 disk = alloc_disk_node(0, node);
b60503ba
MW		 1904 if (!disk)
1905 goto out_free_queue;
a4aea562 1906
5aff9382 1907 ns->ns_id = nsid;
b60503ba
MW		 1908 ns->disk = disk;
1909 lbaf = id->flbas & 0xf;
1910 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1911 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1912 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1913 if (dev->max_hw_sectors)
1914 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 1915 if (dev->stripe_size)
1916 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 1917 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
1918 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 1919
1920 disk->major = nvme_major;
469071a3 1921 disk->first_minor = 0;
b60503ba
MW		 1922 disk->fops = &nvme_fops;
1923 disk->private_data = ns;
1924 disk->queue = ns->queue;
388f037f 1925 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1926 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1927 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1928 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1929
0e5e4f0e
KB		 1930 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1931 nvme_config_discard(ns);
1932
b60503ba
MW		 1933 return ns;
1934
1935 out_free_queue:
1936 blk_cleanup_queue(ns->queue);
1937 out_free_ns:
1938 kfree(ns);
1939 return NULL;
1940}
1941
42f61420
KB		 1942static void nvme_create_io_queues(struct nvme_dev *dev)
1943{
a4aea562 1944 unsigned i;
42f61420 1945
a4aea562 1946 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 1947 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 1948 break;
1949
a4aea562
MB		 1950 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
1951 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 1952 break;
1953}
1954
b3b06812 1955static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 1956{
1957 int status;
1958 u32 result;
b3b06812 1959 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 1960
df348139 1961 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 1962 &result);
27e8166c
MW		 1963 if (status < 0)
1964 return status;
1965 if (status > 0) {
1966 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
1967 status);
badc34d4 1968 return 0;
27e8166c 1969 }
b60503ba
MW		 1970 return min(result & 0xffff, result >> 16) + 1;
1971}
1972
9d713c2b
KB		 1973static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1974{
b80d5ccc 1975 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 1976}
1977
8d85fce7 1978static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1979{
a4aea562 1980 struct nvme_queue *adminq = dev->queues[0];
fa08a396 1981 struct pci_dev *pdev = dev->pci_dev;
42f61420 1982 int result, i, vecs, nr_io_queues, size;
b60503ba 1983
42f61420 1984 nr_io_queues = num_possible_cpus();
b348b7d5 1985 result = set_queue_count(dev, nr_io_queues);
badc34d4 1986 if (result <= 0)
1b23484b 1987 return result;
b348b7d5
MW		 1988 if (result < nr_io_queues)
1989 nr_io_queues = result;
b60503ba 1990
9d713c2b
KB		 1991 size = db_bar_size(dev, nr_io_queues);
1992 if (size > 8192) {
f1938f6e 1993 iounmap(dev->bar);
9d713c2b
KB		 1994 do {
1995 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1996 if (dev->bar)
1997 break;
1998 if (!--nr_io_queues)
1999 return -ENOMEM;
2000 size = db_bar_size(dev, nr_io_queues);
2001 } while (1);
f1938f6e 2002 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2003 adminq->q_db = dev->dbs;
f1938f6e
MW		 2004 }
2005
9d713c2b 2006 /* Deregister the admin queue's interrupt */
3193f07b 2007 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2008
e32efbfc
JA		 2009 /*
2010 * If we enable msix early due to not intx, disable it again before
2011 * setting up the full range we need.
2012 */
2013 if (!pdev->irq)
2014 pci_disable_msix(pdev);
2015
be577fab 2016 for (i = 0; i < nr_io_queues; i++)
1b23484b 2017 dev->entry[i].entry = i;
be577fab
AG		 2018 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2019 if (vecs < 0) {
2020 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2021 if (vecs < 0) {
2022 vecs = 1;
2023 } else {
2024 for (i = 0; i < vecs; i++)
2025 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2026 }
2027 }
2028
063a8096
MW		 2029 /*
2030 * Should investigate if there's a performance win from allocating
2031 * more queues than interrupt vectors; it might allow the submission
2032 * path to scale better, even if the receive path is limited by the
2033 * number of interrupts.
2034 */
2035 nr_io_queues = vecs;
42f61420 2036 dev->max_qid = nr_io_queues;
063a8096 2037
3193f07b 2038 result = queue_request_irq(dev, adminq, adminq->irqname);
a4aea562 2039 if (result)
22404274 2040 goto free_queues;
1b23484b 2041
cd638946 2042 /* Free previously allocated queues that are no longer usable */
42f61420 2043 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2044 nvme_create_io_queues(dev);
9ecdc946 2045
22404274 2046 return 0;
b60503ba 2047
22404274 2048 free_queues:
a1a5ef99 2049 nvme_free_queues(dev, 1);
22404274 2050 return result;
b60503ba
MW		 2051}
2052
422ef0c7
MW		 2053/*
2054 * Return: error value if an error occurred setting up the queues or calling
2055 * Identify Device. 0 if these succeeded, even if adding some of the
2056 * namespaces failed. At the moment, these failures are silent. TBD which
2057 * failures should be reported.
2058 */
8d85fce7 2059static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2060{
68608c26 2061 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2062 int res;
2063 unsigned nn, i;
cbb6218f 2064 struct nvme_ns *ns;
51814232 2065 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2066 struct nvme_id_ns *id_ns;
2067 void *mem;
b60503ba 2068 dma_addr_t dma_addr;
159b67d7 2069 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2070
68608c26 2071 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2072 if (!mem)
2073 return -ENOMEM;
b60503ba 2074
bc5fc7e4 2075 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2076 if (res) {
27e8166c 2077 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
b60503ba 2078 res = -EIO;
cbb6218f 2079 goto out;
b60503ba
MW		 2080 }
2081
bc5fc7e4 2082 ctrl = mem;
51814232 2083 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2084 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2085 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2086 dev->vwc = ctrl->vwc;
6fccf938 2087 dev->event_limit = min(ctrl->aerl + 1, 8);
51814232
MW		 2088 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2089 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2090 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2091 if (ctrl->mdts)
8fc23e03 2092 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2093 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2094 (pdev->device == 0x0953) && ctrl->vs[3]) {
2095 unsigned int max_hw_sectors;
2096
159b67d7 2097 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2098 max_hw_sectors = dev->stripe_size >> (shift - 9);
2099 if (dev->max_hw_sectors) {
2100 dev->max_hw_sectors = min(max_hw_sectors,
2101 dev->max_hw_sectors);
2102 } else
2103 dev->max_hw_sectors = max_hw_sectors;
2104 }
2105
2106 dev->tagset.ops = &nvme_mq_ops;
2107 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2108 dev->tagset.timeout = NVME_IO_TIMEOUT;
2109 dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2110 dev->tagset.queue_depth =
2111 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2112 dev->tagset.cmd_size = sizeof(struct nvme_cmd_info);
2113 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2114 dev->tagset.driver_data = dev;
2115
2116 if (blk_mq_alloc_tag_set(&dev->tagset))
2117 goto out;
b60503ba 2118
bc5fc7e4 2119 id_ns = mem;
2b2c1896 2120 for (i = 1; i <= nn; i++) {
bc5fc7e4 2121 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2122 if (res)
2123 continue;
2124
bc5fc7e4 2125 if (id_ns->ncap == 0)
b60503ba
MW		 2126 continue;
2127
bc5fc7e4 2128 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2129 dma_addr + 4096, NULL);
b60503ba 2130 if (res)
12209036 2131 memset(mem + 4096, 0, 4096);
b60503ba 2132
bc5fc7e4 2133 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2134 if (ns)
2135 list_add_tail(&ns->list, &dev->namespaces);
2136 }
2137 list_for_each_entry(ns, &dev->namespaces, list)
2138 add_disk(ns->disk);
422ef0c7 2139 res = 0;
b60503ba 2140
bc5fc7e4 2141 out:
684f5c20 2142 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2143 return res;
2144}
2145
0877cb0d
KB		 2146static int nvme_dev_map(struct nvme_dev *dev)
2147{
42f61420 2148 u64 cap;
0877cb0d
KB		 2149 int bars, result = -ENOMEM;
2150 struct pci_dev *pdev = dev->pci_dev;
2151
2152 if (pci_enable_device_mem(pdev))
2153 return result;
2154
2155 dev->entry[0].vector = pdev->irq;
2156 pci_set_master(pdev);
2157 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2158 if (!bars)
2159 goto disable_pci;
2160
0877cb0d
KB		 2161 if (pci_request_selected_regions(pdev, bars, "nvme"))
2162 goto disable_pci;
2163
052d0efa
RK		 2164 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2165 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2166 goto disable;
0877cb0d 2167
0877cb0d
KB		 2168 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2169 if (!dev->bar)
2170 goto disable;
e32efbfc 2171
0e53d180
KB		 2172 if (readl(&dev->bar->csts) == -1) {
2173 result = -ENODEV;
2174 goto unmap;
2175 }
e32efbfc
JA		 2176
2177 /*
2178 * Some devices don't advertse INTx interrupts, pre-enable a single
2179 * MSIX vec for setup. We'll adjust this later.
2180 */
2181 if (!pdev->irq) {
2182 result = pci_enable_msix(pdev, dev->entry, 1);
2183 if (result < 0)
2184 goto unmap;
2185 }
2186
42f61420
KB		 2187 cap = readq(&dev->bar->cap);
2188 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2189 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2190 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2191
2192 return 0;
2193
0e53d180
KB		 2194 unmap:
2195 iounmap(dev->bar);
2196 dev->bar = NULL;
0877cb0d
KB		 2197 disable:
2198 pci_release_regions(pdev);
2199 disable_pci:
2200 pci_disable_device(pdev);
2201 return result;
2202}
2203
2204static void nvme_dev_unmap(struct nvme_dev *dev)
2205{
2206 if (dev->pci_dev->msi_enabled)
2207 pci_disable_msi(dev->pci_dev);
2208 else if (dev->pci_dev->msix_enabled)
2209 pci_disable_msix(dev->pci_dev);
2210
2211 if (dev->bar) {
2212 iounmap(dev->bar);
2213 dev->bar = NULL;
9a6b9458 2214 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2215 }
2216
0877cb0d
KB		 2217 if (pci_is_enabled(dev->pci_dev))
2218 pci_disable_device(dev->pci_dev);
2219}
2220
4d115420
KB		 2221struct nvme_delq_ctx {
2222 struct task_struct *waiter;
2223 struct kthread_worker *worker;
2224 atomic_t refcount;
2225};
2226
2227static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2228{
2229 dq->waiter = current;
2230 mb();
2231
2232 for (;;) {
2233 set_current_state(TASK_KILLABLE);
2234 if (!atomic_read(&dq->refcount))
2235 break;
2236 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2237 fatal_signal_pending(current)) {
2238 set_current_state(TASK_RUNNING);
2239
2240 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2241 nvme_disable_queue(dev, 0);
2242
2243 send_sig(SIGKILL, dq->worker->task, 1);
2244 flush_kthread_worker(dq->worker);
2245 return;
2246 }
2247 }
2248 set_current_state(TASK_RUNNING);
2249}
2250
2251static void nvme_put_dq(struct nvme_delq_ctx *dq)
2252{
2253 atomic_dec(&dq->refcount);
2254 if (dq->waiter)
2255 wake_up_process(dq->waiter);
2256}
2257
2258static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2259{
2260 atomic_inc(&dq->refcount);
2261 return dq;
2262}
2263
2264static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2265{
2266 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2267
2268 nvme_clear_queue(nvmeq);
2269 nvme_put_dq(dq);
2270}
2271
2272static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2273 kthread_work_func_t fn)
2274{
2275 struct nvme_command c;
2276
2277 memset(&c, 0, sizeof(c));
2278 c.delete_queue.opcode = opcode;
2279 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2280
2281 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2282 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2283 ADMIN_TIMEOUT);
4d115420
KB		 2284}
2285
2286static void nvme_del_cq_work_handler(struct kthread_work *work)
2287{
2288 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2289 cmdinfo.work);
2290 nvme_del_queue_end(nvmeq);
2291}
2292
2293static int nvme_delete_cq(struct nvme_queue *nvmeq)
2294{
2295 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2296 nvme_del_cq_work_handler);
2297}
2298
2299static void nvme_del_sq_work_handler(struct kthread_work *work)
2300{
2301 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2302 cmdinfo.work);
2303 int status = nvmeq->cmdinfo.status;
2304
2305 if (!status)
2306 status = nvme_delete_cq(nvmeq);
2307 if (status)
2308 nvme_del_queue_end(nvmeq);
2309}
2310
2311static int nvme_delete_sq(struct nvme_queue *nvmeq)
2312{
2313 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2314 nvme_del_sq_work_handler);
2315}
2316
2317static void nvme_del_queue_start(struct kthread_work *work)
2318{
2319 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2320 cmdinfo.work);
2321 allow_signal(SIGKILL);
2322 if (nvme_delete_sq(nvmeq))
2323 nvme_del_queue_end(nvmeq);
2324}
2325
2326static void nvme_disable_io_queues(struct nvme_dev *dev)
2327{
2328 int i;
2329 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2330 struct nvme_delq_ctx dq;
2331 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2332 &worker, "nvme%d", dev->instance);
2333
2334 if (IS_ERR(kworker_task)) {
2335 dev_err(&dev->pci_dev->dev,
2336 "Failed to create queue del task\n");
2337 for (i = dev->queue_count - 1; i > 0; i--)
2338 nvme_disable_queue(dev, i);
2339 return;
2340 }
2341
2342 dq.waiter = NULL;
2343 atomic_set(&dq.refcount, 0);
2344 dq.worker = &worker;
2345 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2346 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2347
2348 if (nvme_suspend_queue(nvmeq))
2349 continue;
2350 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2351 nvmeq->cmdinfo.worker = dq.worker;
2352 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2353 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2354 }
2355 nvme_wait_dq(&dq, dev);
2356 kthread_stop(kworker_task);
2357}
2358
b9afca3e
DM		 2359/*
2360* Remove the node from the device list and check
2361* for whether or not we need to stop the nvme_thread.
2362*/
2363static void nvme_dev_list_remove(struct nvme_dev *dev)
2364{
2365 struct task_struct *tmp = NULL;
2366
2367 spin_lock(&dev_list_lock);
2368 list_del_init(&dev->node);
2369 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2370 tmp = nvme_thread;
2371 nvme_thread = NULL;
2372 }
2373 spin_unlock(&dev_list_lock);
2374
2375 if (tmp)
2376 kthread_stop(tmp);
2377}
2378
f0b50732 2379static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2380{
22404274 2381 int i;
7c1b2450 2382 u32 csts = -1;
22404274 2383
d4b4ff8e 2384 dev->initialized = 0;
b9afca3e 2385 nvme_dev_list_remove(dev);
1fa6aead 2386
7c1b2450
KB		 2387 if (dev->bar)
2388 csts = readl(&dev->bar->csts);
2389 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2390 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2391 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2392 nvme_suspend_queue(nvmeq);
2393 nvme_clear_queue(nvmeq);
2394 }
2395 } else {
2396 nvme_disable_io_queues(dev);
1894d8f1 2397 nvme_shutdown_ctrl(dev);
4d115420
KB		 2398 nvme_disable_queue(dev, 0);
2399 }
f0b50732
KB		 2400 nvme_dev_unmap(dev);
2401}
2402
a4aea562
MB		 2403static void nvme_dev_remove_admin(struct nvme_dev *dev)
2404{
2405 if (dev->admin_q && !blk_queue_dying(dev->admin_q))
2406 blk_cleanup_queue(dev->admin_q);
2407}
2408
f0b50732
KB		 2409static void nvme_dev_remove(struct nvme_dev *dev)
2410{
9ac27090 2411 struct nvme_ns *ns;
f0b50732 2412
9ac27090
KB		 2413 list_for_each_entry(ns, &dev->namespaces, list) {
2414 if (ns->disk->flags & GENHD_FL_UP)
2415 del_gendisk(ns->disk);
2416 if (!blk_queue_dying(ns->queue))
2417 blk_cleanup_queue(ns->queue);
b60503ba 2418 }
b60503ba
MW		 2419}
2420
091b6092
MW		 2421static int nvme_setup_prp_pools(struct nvme_dev *dev)
2422{
2423 struct device *dmadev = &dev->pci_dev->dev;
2424 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2425 PAGE_SIZE, PAGE_SIZE, 0);
2426 if (!dev->prp_page_pool)
2427 return -ENOMEM;
2428
99802a7a
MW		 2429 /* Optimisation for I/Os between 4k and 128k */
2430 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2431 256, 256, 0);
2432 if (!dev->prp_small_pool) {
2433 dma_pool_destroy(dev->prp_page_pool);
2434 return -ENOMEM;
2435 }
091b6092
MW		 2436 return 0;
2437}
2438
2439static void nvme_release_prp_pools(struct nvme_dev *dev)
2440{
2441 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2442 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2443}
2444
cd58ad7d
QSA		 2445static DEFINE_IDA(nvme_instance_ida);
2446
2447static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2448{
cd58ad7d
QSA		 2449 int instance, error;
2450
2451 do {
2452 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2453 return -ENODEV;
2454
2455 spin_lock(&dev_list_lock);
2456 error = ida_get_new(&nvme_instance_ida, &instance);
2457 spin_unlock(&dev_list_lock);
2458 } while (error == -EAGAIN);
2459
2460 if (error)
2461 return -ENODEV;
2462
2463 dev->instance = instance;
2464 return 0;
b60503ba
MW		 2465}
2466
2467static void nvme_release_instance(struct nvme_dev *dev)
2468{
cd58ad7d
QSA		 2469 spin_lock(&dev_list_lock);
2470 ida_remove(&nvme_instance_ida, dev->instance);
2471 spin_unlock(&dev_list_lock);
b60503ba
MW		 2472}
2473
9ac27090
KB		 2474static void nvme_free_namespaces(struct nvme_dev *dev)
2475{
2476 struct nvme_ns *ns, *next;
2477
2478 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2479 list_del(&ns->list);
9e60352c
KB		 2480
2481 spin_lock(&dev_list_lock);
2482 ns->disk->private_data = NULL;
2483 spin_unlock(&dev_list_lock);
2484
9ac27090
KB		 2485 put_disk(ns->disk);
2486 kfree(ns);
2487 }
2488}
2489
5e82e952
KB		 2490static void nvme_free_dev(struct kref *kref)
2491{
2492 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2493
a96d4f5c 2494 pci_dev_put(dev->pci_dev);
9ac27090 2495 nvme_free_namespaces(dev);
285dffc9 2496 nvme_release_instance(dev);
a4aea562 2497 blk_mq_free_tag_set(&dev->tagset);
5e82e952
KB		 2498 kfree(dev->queues);
2499 kfree(dev->entry);
2500 kfree(dev);
2501}
2502
2503static int nvme_dev_open(struct inode *inode, struct file *f)
2504{
2505 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2506 miscdev);
2507 kref_get(&dev->kref);
2508 f->private_data = dev;
2509 return 0;
2510}
2511
2512static int nvme_dev_release(struct inode *inode, struct file *f)
2513{
2514 struct nvme_dev *dev = f->private_data;
2515 kref_put(&dev->kref, nvme_free_dev);
2516 return 0;
2517}
2518
2519static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2520{
2521 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2522 struct nvme_ns *ns;
2523
5e82e952
KB		 2524 switch (cmd) {
2525 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2526 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2527 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2528 if (list_empty(&dev->namespaces))
2529 return -ENOTTY;
2530 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2531 return nvme_user_cmd(dev, ns, (void __user *)arg);
5e82e952
KB		 2532 default:
2533 return -ENOTTY;
2534 }
2535}
2536
2537static const struct file_operations nvme_dev_fops = {
2538 .owner = THIS_MODULE,
2539 .open = nvme_dev_open,
2540 .release = nvme_dev_release,
2541 .unlocked_ioctl = nvme_dev_ioctl,
2542 .compat_ioctl = nvme_dev_ioctl,
2543};
2544
a4aea562
MB		 2545static void nvme_set_irq_hints(struct nvme_dev *dev)
2546{
2547 struct nvme_queue *nvmeq;
2548 int i;
2549
2550 for (i = 0; i < dev->online_queues; i++) {
2551 nvmeq = dev->queues[i];
2552
2553 if (!nvmeq->hctx)
2554 continue;
2555
2556 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2557 nvmeq->hctx->cpumask);
2558 }
2559}
2560
f0b50732
KB		 2561static int nvme_dev_start(struct nvme_dev *dev)
2562{
2563 int result;
b9afca3e 2564 bool start_thread = false;
f0b50732
KB		 2565
2566 result = nvme_dev_map(dev);
2567 if (result)
2568 return result;
2569
2570 result = nvme_configure_admin_queue(dev);
2571 if (result)
2572 goto unmap;
2573
2574 spin_lock(&dev_list_lock);
b9afca3e
DM		 2575 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2576 start_thread = true;
2577 nvme_thread = NULL;
2578 }
f0b50732
KB		 2579 list_add(&dev->node, &dev_list);
2580 spin_unlock(&dev_list_lock);
2581
b9afca3e
DM		 2582 if (start_thread) {
2583 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2584 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2585 } else
2586 wait_event_killable(nvme_kthread_wait, nvme_thread);
2587
2588 if (IS_ERR_OR_NULL(nvme_thread)) {
2589 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2590 goto disable;
2591 }
a4aea562
MB		 2592
2593 nvme_init_queue(dev->queues[0], 0);
b9afca3e 2594
f0b50732 2595 result = nvme_setup_io_queues(dev);
badc34d4 2596 if (result)
f0b50732
KB		 2597 goto disable;
2598
a4aea562
MB		 2599 nvme_set_irq_hints(dev);
2600
d82e8bfd 2601 return result;
f0b50732
KB		 2602
2603 disable:
a1a5ef99 2604 nvme_disable_queue(dev, 0);
b9afca3e 2605 nvme_dev_list_remove(dev);
f0b50732
KB		 2606 unmap:
2607 nvme_dev_unmap(dev);
2608 return result;
2609}
2610
9a6b9458
KB		 2611static int nvme_remove_dead_ctrl(void *arg)
2612{
2613 struct nvme_dev *dev = (struct nvme_dev *)arg;
2614 struct pci_dev *pdev = dev->pci_dev;
2615
2616 if (pci_get_drvdata(pdev))
c81f4975 2617 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2618 kref_put(&dev->kref, nvme_free_dev);
2619 return 0;
2620}
2621
2622static void nvme_remove_disks(struct work_struct *ws)
2623{
9a6b9458
KB		 2624 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2625
5a92e700 2626 nvme_free_queues(dev, 1);
302c6727 2627 nvme_dev_remove(dev);
9a6b9458
KB		 2628}
2629
2630static int nvme_dev_resume(struct nvme_dev *dev)
2631{
2632 int ret;
2633
2634 ret = nvme_dev_start(dev);
badc34d4 2635 if (ret)
9a6b9458 2636 return ret;
badc34d4 2637 if (dev->online_queues < 2) {
9a6b9458 2638 spin_lock(&dev_list_lock);
9ca97374 2639 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2640 queue_work(nvme_workq, &dev->reset_work);
2641 spin_unlock(&dev_list_lock);
2642 }
d4b4ff8e 2643 dev->initialized = 1;
9a6b9458
KB		 2644 return 0;
2645}
2646
2647static void nvme_dev_reset(struct nvme_dev *dev)
2648{
2649 nvme_dev_shutdown(dev);
2650 if (nvme_dev_resume(dev)) {
a4aea562 2651 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
9a6b9458
KB		 2652 kref_get(&dev->kref);
2653 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2654 dev->instance))) {
2655 dev_err(&dev->pci_dev->dev,
2656 "Failed to start controller remove task\n");
2657 kref_put(&dev->kref, nvme_free_dev);
2658 }
2659 }
2660}
2661
2662static void nvme_reset_failed_dev(struct work_struct *ws)
2663{
2664 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2665 nvme_dev_reset(dev);
2666}
2667
9ca97374
TH		 2668static void nvme_reset_workfn(struct work_struct *work)
2669{
2670 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2671 dev->reset_workfn(work);
2672}
2673
8d85fce7 2674static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2675{
a4aea562 2676 int node, result = -ENOMEM;
b60503ba
MW		 2677 struct nvme_dev *dev;
2678
a4aea562
MB		 2679 node = dev_to_node(&pdev->dev);
2680 if (node == NUMA_NO_NODE)
2681 set_dev_node(&pdev->dev, 0);
2682
2683 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2684 if (!dev)
2685 return -ENOMEM;
a4aea562
MB		 2686 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2687 GFP_KERNEL, node);
b60503ba
MW		 2688 if (!dev->entry)
2689 goto free;
a4aea562
MB		 2690 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2691 GFP_KERNEL, node);
b60503ba
MW		 2692 if (!dev->queues)
2693 goto free;
2694
2695 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2696 dev->reset_workfn = nvme_reset_failed_dev;
2697 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
a96d4f5c 2698 dev->pci_dev = pci_dev_get(pdev);
9a6b9458 2699 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2700 result = nvme_set_instance(dev);
2701 if (result)
a96d4f5c 2702 goto put_pci;
b60503ba 2703
091b6092
MW		 2704 result = nvme_setup_prp_pools(dev);
2705 if (result)
0877cb0d 2706 goto release;
091b6092 2707
fb35e914 2708 kref_init(&dev->kref);
f0b50732 2709 result = nvme_dev_start(dev);
badc34d4 2710 if (result)
0877cb0d 2711 goto release_pools;
b60503ba 2712
badc34d4
KB		 2713 if (dev->online_queues > 1)
2714 result = nvme_dev_add(dev);
d82e8bfd 2715 if (result)
f0b50732 2716 goto shutdown;
740216fc 2717
5e82e952
KB		 2718 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2719 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2720 dev->miscdev.parent = &pdev->dev;
2721 dev->miscdev.name = dev->name;
2722 dev->miscdev.fops = &nvme_dev_fops;
2723 result = misc_register(&dev->miscdev);
2724 if (result)
2725 goto remove;
2726
a4aea562
MB		 2727 nvme_set_irq_hints(dev);
2728
d4b4ff8e 2729 dev->initialized = 1;
b60503ba
MW		 2730 return 0;
2731
5e82e952
KB		 2732 remove:
2733 nvme_dev_remove(dev);
a4aea562 2734 nvme_dev_remove_admin(dev);
9ac27090 2735 nvme_free_namespaces(dev);
f0b50732
KB		 2736 shutdown:
2737 nvme_dev_shutdown(dev);
0877cb0d 2738 release_pools:
a1a5ef99 2739 nvme_free_queues(dev, 0);
091b6092 2740 nvme_release_prp_pools(dev);
0877cb0d
KB		 2741 release:
2742 nvme_release_instance(dev);
a96d4f5c
KB		 2743 put_pci:
2744 pci_dev_put(dev->pci_dev);
b60503ba
MW		 2745 free:
2746 kfree(dev->queues);
2747 kfree(dev->entry);
2748 kfree(dev);
2749 return result;
2750}
2751
f0d54a54
KB		 2752static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2753{
a6739479 2754 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 2755
a6739479
KB		 2756 if (prepare)
2757 nvme_dev_shutdown(dev);
2758 else
2759 nvme_dev_resume(dev);
f0d54a54
KB		 2760}
2761
09ece142
KB		 2762static void nvme_shutdown(struct pci_dev *pdev)
2763{
2764 struct nvme_dev *dev = pci_get_drvdata(pdev);
2765 nvme_dev_shutdown(dev);
2766}
2767
8d85fce7 2768static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2769{
2770 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2771
2772 spin_lock(&dev_list_lock);
2773 list_del_init(&dev->node);
2774 spin_unlock(&dev_list_lock);
2775
2776 pci_set_drvdata(pdev, NULL);
2777 flush_work(&dev->reset_work);
5e82e952 2778 misc_deregister(&dev->miscdev);
a4aea562 2779 nvme_dev_remove(dev);
9a6b9458 2780 nvme_dev_shutdown(dev);
a4aea562 2781 nvme_dev_remove_admin(dev);
a1a5ef99 2782 nvme_free_queues(dev, 0);
a4aea562 2783 nvme_free_admin_tags(dev);
9a6b9458 2784 nvme_release_prp_pools(dev);
5e82e952 2785 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2786}
2787
2788/* These functions are yet to be implemented */
2789#define nvme_error_detected NULL
2790#define nvme_dump_registers NULL
2791#define nvme_link_reset NULL
2792#define nvme_slot_reset NULL
2793#define nvme_error_resume NULL
cd638946 2794
671a6018 2795#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2796static int nvme_suspend(struct device *dev)
2797{
2798 struct pci_dev *pdev = to_pci_dev(dev);
2799 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2800
2801 nvme_dev_shutdown(ndev);
2802 return 0;
2803}
2804
2805static int nvme_resume(struct device *dev)
2806{
2807 struct pci_dev *pdev = to_pci_dev(dev);
2808 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2809
9a6b9458 2810 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2811 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 2812 queue_work(nvme_workq, &ndev->reset_work);
2813 }
2814 return 0;
cd638946 2815}
671a6018 2816#endif
cd638946
KB		 2817
2818static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2819
1d352035 2820static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2821 .error_detected = nvme_error_detected,
2822 .mmio_enabled = nvme_dump_registers,
2823 .link_reset = nvme_link_reset,
2824 .slot_reset = nvme_slot_reset,
2825 .resume = nvme_error_resume,
f0d54a54 2826 .reset_notify = nvme_reset_notify,
b60503ba
MW		 2827};
2828
2829/* Move to pci_ids.h later */
2830#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2831
6eb0d698 2832static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2833 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2834 { 0, }
2835};
2836MODULE_DEVICE_TABLE(pci, nvme_id_table);
2837
2838static struct pci_driver nvme_driver = {
2839 .name = "nvme",
2840 .id_table = nvme_id_table,
2841 .probe = nvme_probe,
8d85fce7 2842 .remove = nvme_remove,
09ece142 2843 .shutdown = nvme_shutdown,
cd638946
KB		 2844 .driver = {
2845 .pm = &nvme_dev_pm_ops,
2846 },
b60503ba
MW		 2847 .err_handler = &nvme_err_handler,
2848};
2849
2850static int __init nvme_init(void)
2851{
0ac13140 2852 int result;
1fa6aead 2853
b9afca3e 2854 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2855
9a6b9458
KB		 2856 nvme_workq = create_singlethread_workqueue("nvme");
2857 if (!nvme_workq)
b9afca3e 2858 return -ENOMEM;
9a6b9458 2859
5c42ea16
KB		 2860 result = register_blkdev(nvme_major, "nvme");
2861 if (result < 0)
9a6b9458 2862 goto kill_workq;
5c42ea16 2863 else if (result > 0)
0ac13140 2864 nvme_major = result;
b60503ba 2865
f3db22fe
KB		 2866 result = pci_register_driver(&nvme_driver);
2867 if (result)
a4aea562 2868 goto unregister_blkdev;
1fa6aead 2869 return 0;
b60503ba 2870
1fa6aead 2871 unregister_blkdev:
b60503ba 2872 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2873 kill_workq:
2874 destroy_workqueue(nvme_workq);
b60503ba
MW		 2875 return result;
2876}
2877
2878static void __exit nvme_exit(void)
2879{
2880 pci_unregister_driver(&nvme_driver);
f3db22fe 2881 unregister_hotcpu_notifier(&nvme_nb);
b60503ba 2882 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2883 destroy_workqueue(nvme_workq);
b9afca3e 2884 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 2885 _nvme_check_size();
b60503ba
MW		 2886}
2887
2888MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2889MODULE_LICENSE("GPL");
c78b4713 2890MODULE_VERSION("1.0");
b60503ba
MW		 2891module_init(nvme_init);
2892module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)