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NVMe: Unify SQ entry writing and doorbell ringing
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba 31#include <linux/kernel.h>
a5768aa8 32#include <linux/list_sort.h>
b60503ba
MW		 33#include <linux/mm.h>
34#include <linux/module.h>
35#include <linux/moduleparam.h>
36#include <linux/pci.h>
be7b6275 37#include <linux/poison.h>
c3bfe717 38#include <linux/ptrace.h>
b60503ba
MW		 39#include <linux/sched.h>
40#include <linux/slab.h>
e1e5e564 41#include <linux/t10-pi.h>
b60503ba 42#include <linux/types.h>
5d0f6131 43#include <scsi/sg.h>
797a796a
HM		 44#include <asm-generic/io-64-nonatomic-lo-hi.h>
45
b3fffdef 46#define NVME_MINORS (1U << MINORBITS)
9d43cf64 47#define NVME_Q_DEPTH 1024
d31af0a3 48#define NVME_AQ_DEPTH 256
b60503ba
MW		 49#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
50#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 51#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 52#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 53
54static unsigned char admin_timeout = 60;
55module_param(admin_timeout, byte, 0644);
56MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 57
bd67608a
MW		 58unsigned char nvme_io_timeout = 30;
59module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 60MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 61
2484f407
DM		 62static unsigned char shutdown_timeout = 5;
63module_param(shutdown_timeout, byte, 0644);
64MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
65
b60503ba
MW		 66static int nvme_major;
67module_param(nvme_major, int, 0);
68
b3fffdef
KB		 69static int nvme_char_major;
70module_param(nvme_char_major, int, 0);
71
58ffacb5
MW		 72static int use_threaded_interrupts;
73module_param(use_threaded_interrupts, int, 0);
74
1fa6aead
MW		 75static DEFINE_SPINLOCK(dev_list_lock);
76static LIST_HEAD(dev_list);
77static struct task_struct *nvme_thread;
9a6b9458 78static struct workqueue_struct *nvme_workq;
b9afca3e 79static wait_queue_head_t nvme_kthread_wait;
1fa6aead 80
b3fffdef
KB		 81static struct class *nvme_class;
82
d4b4ff8e 83static void nvme_reset_failed_dev(struct work_struct *ws);
4cc06521 84static int nvme_reset(struct nvme_dev *dev);
a4aea562 85static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 86
4d115420
KB		 87struct async_cmd_info {
88 struct kthread_work work;
89 struct kthread_worker *worker;
a4aea562 90 struct request *req;
4d115420
KB		 91 u32 result;
92 int status;
93 void *ctx;
94};
1fa6aead 95
b60503ba
MW		 96/*
97 * An NVM Express queue. Each device has at least two (one for admin
98 * commands and one for I/O commands).
99 */
100struct nvme_queue {
101 struct device *q_dmadev;
091b6092 102 struct nvme_dev *dev;
3193f07b 103 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 104 spinlock_t q_lock;
105 struct nvme_command *sq_cmds;
106 volatile struct nvme_completion *cqes;
42483228 107 struct blk_mq_tags **tags;
b60503ba
MW		 108 dma_addr_t sq_dma_addr;
109 dma_addr_t cq_dma_addr;
b60503ba
MW		 110 u32 __iomem *q_db;
111 u16 q_depth;
6222d172 112 s16 cq_vector;
b60503ba
MW		 113 u16 sq_head;
114 u16 sq_tail;
115 u16 cq_head;
c30341dc 116 u16 qid;
e9539f47
MW		 117 u8 cq_phase;
118 u8 cqe_seen;
4d115420 119 struct async_cmd_info cmdinfo;
b60503ba
MW		 120};
121
122/*
123 * Check we didin't inadvertently grow the command struct
124 */
125static inline void _nvme_check_size(void)
126{
127 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 132 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 133 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 134 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
135 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
136 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
137 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 138 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 139}
140
edd10d33 141typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 142 struct nvme_completion *);
143
e85248e5 144struct nvme_cmd_info {
c2f5b650
MW		 145 nvme_completion_fn fn;
146 void *ctx;
c30341dc 147 int aborted;
a4aea562 148 struct nvme_queue *nvmeq;
ac3dd5bd 149 struct nvme_iod iod[0];
e85248e5
MW		 150};
151
ac3dd5bd
JA		 152/*
153 * Max size of iod being embedded in the request payload
154 */
155#define NVME_INT_PAGES 2
156#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
fda631ff 157#define NVME_INT_MASK 0x01
ac3dd5bd
JA		 158
159/*
160 * Will slightly overestimate the number of pages needed. This is OK
161 * as it only leads to a small amount of wasted memory for the lifetime of
162 * the I/O.
163 */
164static int nvme_npages(unsigned size, struct nvme_dev *dev)
165{
166 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
167 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
168}
169
170static unsigned int nvme_cmd_size(struct nvme_dev *dev)
171{
172 unsigned int ret = sizeof(struct nvme_cmd_info);
173
174 ret += sizeof(struct nvme_iod);
175 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
176 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
177
178 return ret;
179}
180
a4aea562
MB		 181static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
182 unsigned int hctx_idx)
e85248e5 183{
a4aea562
MB		 184 struct nvme_dev *dev = data;
185 struct nvme_queue *nvmeq = dev->queues[0];
186
42483228
KB		 187 WARN_ON(hctx_idx != 0);
188 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
189 WARN_ON(nvmeq->tags);
190
a4aea562 191 hctx->driver_data = nvmeq;
42483228 192 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 193 return 0;
e85248e5
MW		 194}
195
4af0e21c
KB		 196static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
197{
198 struct nvme_queue *nvmeq = hctx->driver_data;
199
200 nvmeq->tags = NULL;
201}
202
a4aea562
MB		 203static int nvme_admin_init_request(void *data, struct request *req,
204 unsigned int hctx_idx, unsigned int rq_idx,
205 unsigned int numa_node)
22404274 206{
a4aea562
MB		 207 struct nvme_dev *dev = data;
208 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
209 struct nvme_queue *nvmeq = dev->queues[0];
210
211 BUG_ON(!nvmeq);
212 cmd->nvmeq = nvmeq;
213 return 0;
22404274
KB		 214}
215
a4aea562
MB		 216static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
217 unsigned int hctx_idx)
b60503ba 218{
a4aea562 219 struct nvme_dev *dev = data;
42483228 220 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
a4aea562 221
42483228
KB		 222 if (!nvmeq->tags)
223 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 224
42483228 225 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 226 hctx->driver_data = nvmeq;
227 return 0;
b60503ba
MW		 228}
229
a4aea562
MB		 230static int nvme_init_request(void *data, struct request *req,
231 unsigned int hctx_idx, unsigned int rq_idx,
232 unsigned int numa_node)
b60503ba 233{
a4aea562
MB		 234 struct nvme_dev *dev = data;
235 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
236 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
237
238 BUG_ON(!nvmeq);
239 cmd->nvmeq = nvmeq;
240 return 0;
241}
242
243static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
244 nvme_completion_fn handler)
245{
246 cmd->fn = handler;
247 cmd->ctx = ctx;
248 cmd->aborted = 0;
c917dfe5 249 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 250}
251
ac3dd5bd
JA		 252static void *iod_get_private(struct nvme_iod *iod)
253{
254 return (void *) (iod->private & ~0x1UL);
255}
256
257/*
258 * If bit 0 is set, the iod is embedded in the request payload.
259 */
260static bool iod_should_kfree(struct nvme_iod *iod)
261{
fda631ff 262 return (iod->private & NVME_INT_MASK) == 0;
ac3dd5bd
JA		 263}
264
c2f5b650
MW		 265/* Special values must be less than 0x1000 */
266#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 267#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
268#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
269#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 270
edd10d33 271static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 272 struct nvme_completion *cqe)
273{
274 if (ctx == CMD_CTX_CANCELLED)
275 return;
c2f5b650 276 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 277 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 278 "completed id %d twice on queue %d\n",
279 cqe->command_id, le16_to_cpup(&cqe->sq_id));
280 return;
281 }
282 if (ctx == CMD_CTX_INVALID) {
edd10d33 283 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 284 "invalid id %d completed on queue %d\n",
285 cqe->command_id, le16_to_cpup(&cqe->sq_id));
286 return;
287 }
edd10d33 288 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 289}
290
a4aea562 291static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 292{
c2f5b650 293 void *ctx;
b60503ba 294
859361a2 295 if (fn)
a4aea562
MB		 296 *fn = cmd->fn;
297 ctx = cmd->ctx;
298 cmd->fn = special_completion;
299 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 300 return ctx;
b60503ba
MW		 301}
302
a4aea562
MB		 303static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
304 struct nvme_completion *cqe)
3c0cf138 305{
a4aea562
MB		 306 u32 result = le32_to_cpup(&cqe->result);
307 u16 status = le16_to_cpup(&cqe->status) >> 1;
308
309 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
310 ++nvmeq->dev->event_limit;
a5768aa8
KB		 311 if (status != NVME_SC_SUCCESS)
312 return;
313
314 switch (result & 0xff07) {
315 case NVME_AER_NOTICE_NS_CHANGED:
316 dev_info(nvmeq->q_dmadev, "rescanning\n");
317 schedule_work(&nvmeq->dev->scan_work);
318 default:
319 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
320 }
b60503ba
MW		 321}
322
a4aea562
MB		 323static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
324 struct nvme_completion *cqe)
5a92e700 325{
a4aea562
MB		 326 struct request *req = ctx;
327
328 u16 status = le16_to_cpup(&cqe->status) >> 1;
329 u32 result = le32_to_cpup(&cqe->result);
a51afb54 330
42483228 331 blk_mq_free_request(req);
a51afb54 332
a4aea562
MB		 333 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
334 ++nvmeq->dev->abort_limit;
5a92e700
KB		 335}
336
a4aea562
MB		 337static void async_completion(struct nvme_queue *nvmeq, void *ctx,
338 struct nvme_completion *cqe)
b60503ba 339{
a4aea562
MB		 340 struct async_cmd_info *cmdinfo = ctx;
341 cmdinfo->result = le32_to_cpup(&cqe->result);
342 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
343 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
42483228 344 blk_mq_free_request(cmdinfo->req);
b60503ba
MW		 345}
346
a4aea562
MB		 347static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
348 unsigned int tag)
b60503ba 349{
42483228 350 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
a51afb54 351
a4aea562 352 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 353}
354
a4aea562
MB		 355/*
356 * Called with local interrupts disabled and the q_lock held. May not sleep.
357 */
358static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
359 nvme_completion_fn *fn)
4f5099af 360{
a4aea562
MB		 361 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
362 void *ctx;
363 if (tag >= nvmeq->q_depth) {
364 *fn = special_completion;
365 return CMD_CTX_INVALID;
366 }
367 if (fn)
368 *fn = cmd->fn;
369 ctx = cmd->ctx;
370 cmd->fn = special_completion;
371 cmd->ctx = CMD_CTX_COMPLETED;
372 return ctx;
b60503ba
MW		 373}
374
375/**
714a7a22 376 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 377 * @nvmeq: The queue to use
378 * @cmd: The command to send
379 *
380 * Safe to use from interrupt context
381 */
a4aea562 382static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 383{
a4aea562
MB		 384 u16 tail = nvmeq->sq_tail;
385
b60503ba 386 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 387 if (++tail == nvmeq->q_depth)
388 tail = 0;
7547881d 389 writel(tail, nvmeq->q_db);
b60503ba 390 nvmeq->sq_tail = tail;
b60503ba
MW		 391
392 return 0;
393}
394
a4aea562
MB		 395static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
396{
397 unsigned long flags;
398 int ret;
399 spin_lock_irqsave(&nvmeq->q_lock, flags);
400 ret = __nvme_submit_cmd(nvmeq, cmd);
401 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
402 return ret;
403}
404
eca18b23 405static __le64 **iod_list(struct nvme_iod *iod)
e025344c 406{
eca18b23 407 return ((void *)iod) + iod->offset;
e025344c
SMM		 408}
409
ac3dd5bd
JA		 410static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
411 unsigned nseg, unsigned long private)
eca18b23 412{
ac3dd5bd
JA		 413 iod->private = private;
414 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
415 iod->npages = -1;
416 iod->length = nbytes;
417 iod->nents = 0;
eca18b23 418}
b60503ba 419
eca18b23 420static struct nvme_iod *
ac3dd5bd
JA		 421__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
422 unsigned long priv, gfp_t gfp)
b60503ba 423{
eca18b23 424 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 425 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 426 sizeof(struct scatterlist) * nseg, gfp);
427
ac3dd5bd
JA		 428 if (iod)
429 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 430
431 return iod;
b60503ba
MW		 432}
433
ac3dd5bd
JA		 434static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
435 gfp_t gfp)
436{
437 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
438 sizeof(struct nvme_dsm_range);
ac3dd5bd
JA		 439 struct nvme_iod *iod;
440
441 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
442 size <= NVME_INT_BYTES(dev)) {
443 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
444
445 iod = cmd->iod;
ac3dd5bd 446 iod_init(iod, size, rq->nr_phys_segments,
fda631ff 447 (unsigned long) rq | NVME_INT_MASK);
ac3dd5bd
JA		 448 return iod;
449 }
450
451 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
452 (unsigned long) rq, gfp);
453}
454
d29ec824 455static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 456{
1d090624 457 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 458 int i;
459 __le64 **list = iod_list(iod);
460 dma_addr_t prp_dma = iod->first_dma;
461
462 if (iod->npages == 0)
463 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
464 for (i = 0; i < iod->npages; i++) {
465 __le64 *prp_list = list[i];
466 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
467 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
468 prp_dma = next_prp_dma;
469 }
ac3dd5bd
JA		 470
471 if (iod_should_kfree(iod))
472 kfree(iod);
b60503ba
MW		 473}
474
b4ff9c8d
KB		 475static int nvme_error_status(u16 status)
476{
477 switch (status & 0x7ff) {
478 case NVME_SC_SUCCESS:
479 return 0;
480 case NVME_SC_CAP_EXCEEDED:
481 return -ENOSPC;
482 default:
483 return -EIO;
484 }
485}
486
52b68d7e 487#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 488static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
489{
490 if (be32_to_cpu(pi->ref_tag) == v)
491 pi->ref_tag = cpu_to_be32(p);
492}
493
494static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
495{
496 if (be32_to_cpu(pi->ref_tag) == p)
497 pi->ref_tag = cpu_to_be32(v);
498}
499
500/**
501 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
502 *
503 * The virtual start sector is the one that was originally submitted by the
504 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
505 * start sector may be different. Remap protection information to match the
506 * physical LBA on writes, and back to the original seed on reads.
507 *
508 * Type 0 and 3 do not have a ref tag, so no remapping required.
509 */
510static void nvme_dif_remap(struct request *req,
511 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
512{
513 struct nvme_ns *ns = req->rq_disk->private_data;
514 struct bio_integrity_payload *bip;
515 struct t10_pi_tuple *pi;
516 void *p, *pmap;
517 u32 i, nlb, ts, phys, virt;
518
519 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
520 return;
521
522 bip = bio_integrity(req->bio);
523 if (!bip)
524 return;
525
526 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 527
528 p = pmap;
529 virt = bip_get_seed(bip);
530 phys = nvme_block_nr(ns, blk_rq_pos(req));
531 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
532 ts = ns->disk->integrity->tuple_size;
533
534 for (i = 0; i < nlb; i++, virt++, phys++) {
535 pi = (struct t10_pi_tuple *)p;
536 dif_swap(phys, virt, pi);
537 p += ts;
538 }
539 kunmap_atomic(pmap);
540}
541
52b68d7e
KB		 542static int nvme_noop_verify(struct blk_integrity_iter *iter)
543{
544 return 0;
545}
546
547static int nvme_noop_generate(struct blk_integrity_iter *iter)
548{
549 return 0;
550}
551
552struct blk_integrity nvme_meta_noop = {
553 .name = "NVME_META_NOOP",
554 .generate_fn = nvme_noop_generate,
555 .verify_fn = nvme_noop_verify,
556};
557
558static void nvme_init_integrity(struct nvme_ns *ns)
559{
560 struct blk_integrity integrity;
561
562 switch (ns->pi_type) {
563 case NVME_NS_DPS_PI_TYPE3:
564 integrity = t10_pi_type3_crc;
565 break;
566 case NVME_NS_DPS_PI_TYPE1:
567 case NVME_NS_DPS_PI_TYPE2:
568 integrity = t10_pi_type1_crc;
569 break;
570 default:
571 integrity = nvme_meta_noop;
572 break;
573 }
574 integrity.tuple_size = ns->ms;
575 blk_integrity_register(ns->disk, &integrity);
576 blk_queue_max_integrity_segments(ns->queue, 1);
577}
578#else /* CONFIG_BLK_DEV_INTEGRITY */
579static void nvme_dif_remap(struct request *req,
580 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
581{
582}
583static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
584{
585}
586static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
587{
588}
589static void nvme_init_integrity(struct nvme_ns *ns)
590{
591}
592#endif
593
a4aea562 594static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 595 struct nvme_completion *cqe)
596{
eca18b23 597 struct nvme_iod *iod = ctx;
ac3dd5bd 598 struct request *req = iod_get_private(iod);
a4aea562
MB		 599 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
600
b60503ba
MW		 601 u16 status = le16_to_cpup(&cqe->status) >> 1;
602
edd10d33 603 if (unlikely(status)) {
a4aea562
MB		 604 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
605 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 606 unsigned long flags;
607
a4aea562 608 blk_mq_requeue_request(req);
c9d3bf88
KB		 609 spin_lock_irqsave(req->q->queue_lock, flags);
610 if (!blk_queue_stopped(req->q))
611 blk_mq_kick_requeue_list(req->q);
612 spin_unlock_irqrestore(req->q->queue_lock, flags);
edd10d33
KB		 613 return;
614 }
d29ec824 615 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
17188bb4
KB		 616 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
617 req->errors = -EINTR;
618 else
619 req->errors = status;
d29ec824
CH		 620 } else {
621 req->errors = nvme_error_status(status);
622 }
a4aea562
MB		 623 } else
624 req->errors = 0;
a0a931d6
KB		 625 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
626 u32 result = le32_to_cpup(&cqe->result);
627 req->special = (void *)(uintptr_t)result;
628 }
a4aea562
MB		 629
630 if (cmd_rq->aborted)
e75ec752 631 dev_warn(nvmeq->dev->dev,
a4aea562
MB		 632 "completing aborted command with status:%04x\n",
633 status);
634
e1e5e564 635 if (iod->nents) {
e75ec752 636 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
a4aea562 637 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
e1e5e564
KB		 638 if (blk_integrity_rq(req)) {
639 if (!rq_data_dir(req))
640 nvme_dif_remap(req, nvme_dif_complete);
e75ec752 641 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
e1e5e564
KB		 642 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
643 }
644 }
edd10d33 645 nvme_free_iod(nvmeq->dev, iod);
3291fa57 646
a4aea562 647 blk_mq_complete_request(req);
b60503ba
MW		 648}
649
184d2944 650/* length is in bytes. gfp flags indicates whether we may sleep. */
d29ec824
CH		 651static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
652 int total_len, gfp_t gfp)
ff22b54f 653{
99802a7a 654 struct dma_pool *pool;
eca18b23
MW		 655 int length = total_len;
656 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 657 int dma_len = sg_dma_len(sg);
658 u64 dma_addr = sg_dma_address(sg);
f137e0f1
MI		 659 u32 page_size = dev->page_size;
660 int offset = dma_addr & (page_size - 1);
e025344c 661 __le64 *prp_list;
eca18b23 662 __le64 **list = iod_list(iod);
e025344c 663 dma_addr_t prp_dma;
eca18b23 664 int nprps, i;
ff22b54f 665
1d090624 666 length -= (page_size - offset);
ff22b54f 667 if (length <= 0)
eca18b23 668 return total_len;
ff22b54f 669
1d090624 670 dma_len -= (page_size - offset);
ff22b54f 671 if (dma_len) {
1d090624 672 dma_addr += (page_size - offset);
ff22b54f
MW		 673 } else {
674 sg = sg_next(sg);
675 dma_addr = sg_dma_address(sg);
676 dma_len = sg_dma_len(sg);
677 }
678
1d090624 679 if (length <= page_size) {
edd10d33 680 iod->first_dma = dma_addr;
eca18b23 681 return total_len;
e025344c
SMM		 682 }
683
1d090624 684 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 685 if (nprps <= (256 / 8)) {
686 pool = dev->prp_small_pool;
eca18b23 687 iod->npages = 0;
99802a7a
MW		 688 } else {
689 pool = dev->prp_page_pool;
eca18b23 690 iod->npages = 1;
99802a7a
MW		 691 }
692
b77954cb
MW		 693 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
694 if (!prp_list) {
edd10d33 695 iod->first_dma = dma_addr;
eca18b23 696 iod->npages = -1;
1d090624 697 return (total_len - length) + page_size;
b77954cb 698 }
eca18b23
MW		 699 list[0] = prp_list;
700 iod->first_dma = prp_dma;
e025344c
SMM		 701 i = 0;
702 for (;;) {
1d090624 703 if (i == page_size >> 3) {
e025344c 704 __le64 *old_prp_list = prp_list;
b77954cb 705 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 706 if (!prp_list)
707 return total_len - length;
708 list[iod->npages++] = prp_list;
7523d834
MW		 709 prp_list[0] = old_prp_list[i - 1];
710 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
711 i = 1;
e025344c
SMM		 712 }
713 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 714 dma_len -= page_size;
715 dma_addr += page_size;
716 length -= page_size;
e025344c
SMM		 717 if (length <= 0)
718 break;
719 if (dma_len > 0)
720 continue;
721 BUG_ON(dma_len < 0);
722 sg = sg_next(sg);
723 dma_addr = sg_dma_address(sg);
724 dma_len = sg_dma_len(sg);
ff22b54f
MW		 725 }
726
eca18b23 727 return total_len;
ff22b54f
MW		 728}
729
d29ec824
CH		 730static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
731 struct nvme_iod *iod)
732{
498c4394 733 struct nvme_command cmnd;
d29ec824 734
498c4394
JD		 735 memcpy(&cmnd, req->cmd, sizeof(cmnd));
736 cmnd.rw.command_id = req->tag;
d29ec824 737 if (req->nr_phys_segments) {
498c4394
JD		 738 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
739 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
d29ec824
CH		 740 }
741
498c4394 742 __nvme_submit_cmd(nvmeq, &cmnd);
d29ec824
CH		 743}
744
a4aea562
MB		 745/*
746 * We reuse the small pool to allocate the 16-byte range here as it is not
747 * worth having a special pool for these or additional cases to handle freeing
748 * the iod.
749 */
750static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
751 struct request *req, struct nvme_iod *iod)
0e5e4f0e 752{
edd10d33
KB		 753 struct nvme_dsm_range *range =
754 (struct nvme_dsm_range *)iod_list(iod)[0];
498c4394 755 struct nvme_command cmnd;
0e5e4f0e 756
0e5e4f0e 757 range->cattr = cpu_to_le32(0);
a4aea562
MB		 758 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
759 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e 760
498c4394
JD		 761 memset(&cmnd, 0, sizeof(cmnd));
762 cmnd.dsm.opcode = nvme_cmd_dsm;
763 cmnd.dsm.command_id = req->tag;
764 cmnd.dsm.nsid = cpu_to_le32(ns->ns_id);
765 cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma);
766 cmnd.dsm.nr = 0;
767 cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
0e5e4f0e 768
498c4394 769 __nvme_submit_cmd(nvmeq, &cmnd);
0e5e4f0e
KB		 770}
771
a4aea562 772static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 773 int cmdid)
774{
498c4394 775 struct nvme_command cmnd;
00df5cb4 776
498c4394
JD		 777 memset(&cmnd, 0, sizeof(cmnd));
778 cmnd.common.opcode = nvme_cmd_flush;
779 cmnd.common.command_id = cmdid;
780 cmnd.common.nsid = cpu_to_le32(ns->ns_id);
00df5cb4 781
498c4394 782 __nvme_submit_cmd(nvmeq, &cmnd);
00df5cb4
MW		 783}
784
a4aea562
MB		 785static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
786 struct nvme_ns *ns)
b60503ba 787{
ac3dd5bd 788 struct request *req = iod_get_private(iod);
498c4394 789 struct nvme_command cmnd;
a4aea562
MB		 790 u16 control = 0;
791 u32 dsmgmt = 0;
00df5cb4 792
a4aea562 793 if (req->cmd_flags & REQ_FUA)
b60503ba 794 control |= NVME_RW_FUA;
a4aea562 795 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 796 control |= NVME_RW_LR;
797
a4aea562 798 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 799 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
800
498c4394
JD		 801 memset(&cmnd, 0, sizeof(cmnd));
802 cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
803 cmnd.rw.command_id = req->tag;
804 cmnd.rw.nsid = cpu_to_le32(ns->ns_id);
805 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
806 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
807 cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
808 cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
e1e5e564
KB		 809
810 if (blk_integrity_rq(req)) {
498c4394 811 cmnd.rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
e1e5e564
KB		 812 switch (ns->pi_type) {
813 case NVME_NS_DPS_PI_TYPE3:
814 control |= NVME_RW_PRINFO_PRCHK_GUARD;
815 break;
816 case NVME_NS_DPS_PI_TYPE1:
817 case NVME_NS_DPS_PI_TYPE2:
818 control |= NVME_RW_PRINFO_PRCHK_GUARD |
819 NVME_RW_PRINFO_PRCHK_REF;
498c4394 820 cmnd.rw.reftag = cpu_to_le32(
e1e5e564
KB		 821 nvme_block_nr(ns, blk_rq_pos(req)));
822 break;
823 }
824 } else if (ns->ms)
825 control |= NVME_RW_PRINFO_PRACT;
826
498c4394
JD		 827 cmnd.rw.control = cpu_to_le16(control);
828 cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 829
498c4394 830 __nvme_submit_cmd(nvmeq, &cmnd);
b60503ba 831
1974b1ae 832 return 0;
edd10d33
KB		 833}
834
d29ec824
CH		 835/*
836 * NOTE: ns is NULL when called on the admin queue.
837 */
a4aea562
MB		 838static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
839 const struct blk_mq_queue_data *bd)
edd10d33 840{
a4aea562
MB		 841 struct nvme_ns *ns = hctx->queue->queuedata;
842 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 843 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 844 struct request *req = bd->rq;
845 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 846 struct nvme_iod *iod;
a4aea562 847 enum dma_data_direction dma_dir;
edd10d33 848
e1e5e564
KB		 849 /*
850 * If formated with metadata, require the block layer provide a buffer
851 * unless this namespace is formated such that the metadata can be
852 * stripped/generated by the controller with PRACT=1.
853 */
d29ec824 854 if (ns && ns->ms && !blk_integrity_rq(req)) {
71feb364
KB		 855 if (!(ns->pi_type && ns->ms == 8) &&
856 req->cmd_type != REQ_TYPE_DRV_PRIV) {
e1e5e564
KB		 857 req->errors = -EFAULT;
858 blk_mq_complete_request(req);
859 return BLK_MQ_RQ_QUEUE_OK;
860 }
861 }
862
d29ec824 863 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
edd10d33 864 if (!iod)
fe54303e 865 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 866
a4aea562 867 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 868 void *range;
869 /*
870 * We reuse the small pool to allocate the 16-byte range here
871 * as it is not worth having a special pool for these or
872 * additional cases to handle freeing the iod.
873 */
d29ec824 874 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
edd10d33 875 &iod->first_dma);
a4aea562 876 if (!range)
fe54303e 877 goto retry_cmd;
edd10d33
KB		 878 iod_list(iod)[0] = (__le64 *)range;
879 iod->npages = 0;
ac3dd5bd 880 } else if (req->nr_phys_segments) {
a4aea562
MB		 881 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
882
ac3dd5bd 883 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 884 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 885 if (!iod->nents)
886 goto error_cmd;
a4aea562
MB		 887
888 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 889 goto retry_cmd;
a4aea562 890
fe54303e 891 if (blk_rq_bytes(req) !=
d29ec824
CH		 892 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
893 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
fe54303e
JA		 894 goto retry_cmd;
895 }
e1e5e564
KB		 896 if (blk_integrity_rq(req)) {
897 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
898 goto error_cmd;
899
900 sg_init_table(iod->meta_sg, 1);
901 if (blk_rq_map_integrity_sg(
902 req->q, req->bio, iod->meta_sg) != 1)
903 goto error_cmd;
904
905 if (rq_data_dir(req))
906 nvme_dif_remap(req, nvme_dif_prep);
907
908 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
909 goto error_cmd;
910 }
edd10d33 911 }
1974b1ae 912
9af8785a 913 nvme_set_info(cmd, iod, req_completion);
a4aea562 914 spin_lock_irq(&nvmeq->q_lock);
d29ec824
CH		 915 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
916 nvme_submit_priv(nvmeq, req, iod);
917 else if (req->cmd_flags & REQ_DISCARD)
a4aea562
MB		 918 nvme_submit_discard(nvmeq, ns, req, iod);
919 else if (req->cmd_flags & REQ_FLUSH)
920 nvme_submit_flush(nvmeq, ns, req->tag);
921 else
922 nvme_submit_iod(nvmeq, iod, ns);
923
924 nvme_process_cq(nvmeq);
925 spin_unlock_irq(&nvmeq->q_lock);
926 return BLK_MQ_RQ_QUEUE_OK;
927
fe54303e 928 error_cmd:
d29ec824 929 nvme_free_iod(dev, iod);
fe54303e
JA		 930 return BLK_MQ_RQ_QUEUE_ERROR;
931 retry_cmd:
d29ec824 932 nvme_free_iod(dev, iod);
fe54303e 933 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 934}
935
e9539f47 936static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 937{
82123460 938 u16 head, phase;
b60503ba 939
b60503ba 940 head = nvmeq->cq_head;
82123460 941 phase = nvmeq->cq_phase;
b60503ba
MW		 942
943 for (;;) {
c2f5b650
MW		 944 void *ctx;
945 nvme_completion_fn fn;
b60503ba 946 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 947 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 948 break;
949 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
950 if (++head == nvmeq->q_depth) {
951 head = 0;
82123460 952 phase = !phase;
b60503ba 953 }
a4aea562 954 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 955 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 956 }
957
958 /* If the controller ignores the cq head doorbell and continuously
959 * writes to the queue, it is theoretically possible to wrap around
960 * the queue twice and mistakenly return IRQ_NONE. Linux only
961 * requires that 0.1% of your interrupts are handled, so this isn't
962 * a big problem.
963 */
82123460 964 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 965 return 0;
b60503ba 966
b80d5ccc 967 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 968 nvmeq->cq_head = head;
82123460 969 nvmeq->cq_phase = phase;
b60503ba 970
e9539f47
MW		 971 nvmeq->cqe_seen = 1;
972 return 1;
b60503ba
MW		 973}
974
975static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 976{
977 irqreturn_t result;
978 struct nvme_queue *nvmeq = data;
979 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 980 nvme_process_cq(nvmeq);
981 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
982 nvmeq->cqe_seen = 0;
58ffacb5
MW		 983 spin_unlock(&nvmeq->q_lock);
984 return result;
985}
986
987static irqreturn_t nvme_irq_check(int irq, void *data)
988{
989 struct nvme_queue *nvmeq = data;
990 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
991 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
992 return IRQ_NONE;
993 return IRQ_WAKE_THREAD;
994}
995
b60503ba
MW		 996/*
997 * Returns 0 on success. If the result is negative, it's a Linux error code;
998 * if the result is positive, it's an NVM Express status code
999 */
d29ec824
CH		 1000int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1001 void *buffer, void __user *ubuffer, unsigned bufflen,
1002 u32 *result, unsigned timeout)
b60503ba 1003{
d29ec824
CH		 1004 bool write = cmd->common.opcode & 1;
1005 struct bio *bio = NULL;
f705f837 1006 struct request *req;
d29ec824 1007 int ret;
b60503ba 1008
d29ec824 1009 req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
f705f837
CH		 1010 if (IS_ERR(req))
1011 return PTR_ERR(req);
b60503ba 1012
d29ec824 1013 req->cmd_type = REQ_TYPE_DRV_PRIV;
e112af0d 1014 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d29ec824
CH		 1015 req->__data_len = 0;
1016 req->__sector = (sector_t) -1;
1017 req->bio = req->biotail = NULL;
b60503ba 1018
f4ff414a 1019 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
a4aea562 1020
d29ec824
CH		 1021 req->cmd = (unsigned char *)cmd;
1022 req->cmd_len = sizeof(struct nvme_command);
a0a931d6 1023 req->special = (void *)0;
b60503ba 1024
d29ec824
CH		 1025 if (buffer && bufflen) {
1026 ret = blk_rq_map_kern(q, req, buffer, bufflen, __GFP_WAIT);
1027 if (ret)
1028 goto out;
1029 } else if (ubuffer && bufflen) {
1030 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen, __GFP_WAIT);
1031 if (ret)
1032 goto out;
1033 bio = req->bio;
1034 }
3c0cf138 1035
d29ec824
CH		 1036 blk_execute_rq(req->q, NULL, req, 0);
1037 if (bio)
1038 blk_rq_unmap_user(bio);
b60503ba 1039 if (result)
a0a931d6 1040 *result = (u32)(uintptr_t)req->special;
d29ec824
CH		 1041 ret = req->errors;
1042 out:
f705f837 1043 blk_mq_free_request(req);
d29ec824 1044 return ret;
f705f837
CH		 1045}
1046
d29ec824
CH		 1047int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1048 void *buffer, unsigned bufflen)
f705f837 1049{
d29ec824 1050 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
b60503ba
MW		 1051}
1052
a4aea562
MB		 1053static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1054{
1055 struct nvme_queue *nvmeq = dev->queues[0];
1056 struct nvme_command c;
1057 struct nvme_cmd_info *cmd_info;
1058 struct request *req;
1059
1efccc9d 1060 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
9f173b33
DC		 1061 if (IS_ERR(req))
1062 return PTR_ERR(req);
a4aea562 1063
c917dfe5 1064 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562 1065 cmd_info = blk_mq_rq_to_pdu(req);
1efccc9d 1066 nvme_set_info(cmd_info, NULL, async_req_completion);
a4aea562
MB		 1067
1068 memset(&c, 0, sizeof(c));
1069 c.common.opcode = nvme_admin_async_event;
1070 c.common.command_id = req->tag;
1071
42483228 1072 blk_mq_free_request(req);
a4aea562
MB		 1073 return __nvme_submit_cmd(nvmeq, &c);
1074}
1075
1076static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 1077 struct nvme_command *cmd,
1078 struct async_cmd_info *cmdinfo, unsigned timeout)
1079{
a4aea562
MB		 1080 struct nvme_queue *nvmeq = dev->queues[0];
1081 struct request *req;
1082 struct nvme_cmd_info *cmd_rq;
4d115420 1083
a4aea562 1084 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 1085 if (IS_ERR(req))
1086 return PTR_ERR(req);
a4aea562
MB		 1087
1088 req->timeout = timeout;
1089 cmd_rq = blk_mq_rq_to_pdu(req);
1090 cmdinfo->req = req;
1091 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 1092 cmdinfo->status = -EINTR;
a4aea562
MB		 1093
1094 cmd->common.command_id = req->tag;
1095
4f5099af 1096 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 1097}
1098
b60503ba
MW		 1099static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1100{
b60503ba
MW		 1101 struct nvme_command c;
1102
1103 memset(&c, 0, sizeof(c));
1104 c.delete_queue.opcode = opcode;
1105 c.delete_queue.qid = cpu_to_le16(id);
1106
d29ec824 1107 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1108}
1109
1110static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1111 struct nvme_queue *nvmeq)
1112{
b60503ba
MW		 1113 struct nvme_command c;
1114 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1115
d29ec824
CH		 1116 /*
1117 * Note: we (ab)use the fact the the prp fields survive if no data
1118 * is attached to the request.
1119 */
b60503ba
MW		 1120 memset(&c, 0, sizeof(c));
1121 c.create_cq.opcode = nvme_admin_create_cq;
1122 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1123 c.create_cq.cqid = cpu_to_le16(qid);
1124 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1125 c.create_cq.cq_flags = cpu_to_le16(flags);
1126 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1127
d29ec824 1128 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1129}
1130
1131static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1132 struct nvme_queue *nvmeq)
1133{
b60503ba
MW		 1134 struct nvme_command c;
1135 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1136
d29ec824
CH		 1137 /*
1138 * Note: we (ab)use the fact the the prp fields survive if no data
1139 * is attached to the request.
1140 */
b60503ba
MW		 1141 memset(&c, 0, sizeof(c));
1142 c.create_sq.opcode = nvme_admin_create_sq;
1143 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1144 c.create_sq.sqid = cpu_to_le16(qid);
1145 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1146 c.create_sq.sq_flags = cpu_to_le16(flags);
1147 c.create_sq.cqid = cpu_to_le16(qid);
1148
d29ec824 1149 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1150}
1151
1152static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1153{
1154 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1155}
1156
1157static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1158{
1159 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1160}
1161
d29ec824 1162int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
bc5fc7e4 1163{
e44ac588 1164 struct nvme_command c = { };
d29ec824 1165 int error;
bc5fc7e4 1166
e44ac588
AM		 1167 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1168 c.identify.opcode = nvme_admin_identify;
1169 c.identify.cns = cpu_to_le32(1);
1170
d29ec824
CH		 1171 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1172 if (!*id)
1173 return -ENOMEM;
bc5fc7e4 1174
d29ec824
CH		 1175 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1176 sizeof(struct nvme_id_ctrl));
1177 if (error)
1178 kfree(*id);
1179 return error;
1180}
1181
1182int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1183 struct nvme_id_ns **id)
1184{
e44ac588 1185 struct nvme_command c = { };
d29ec824 1186 int error;
bc5fc7e4 1187
e44ac588
AM		 1188 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1189 c.identify.opcode = nvme_admin_identify,
1190 c.identify.nsid = cpu_to_le32(nsid),
1191
d29ec824
CH		 1192 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1193 if (!*id)
1194 return -ENOMEM;
1195
1196 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1197 sizeof(struct nvme_id_ns));
1198 if (error)
1199 kfree(*id);
1200 return error;
bc5fc7e4
MW		 1201}
1202
5d0f6131 1203int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1204 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1205{
1206 struct nvme_command c;
1207
1208 memset(&c, 0, sizeof(c));
1209 c.features.opcode = nvme_admin_get_features;
a42cecce 1210 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1211 c.features.prp1 = cpu_to_le64(dma_addr);
1212 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1213
d29ec824
CH		 1214 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1215 result, 0);
df348139
MW		 1216}
1217
5d0f6131
VV		 1218int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1219 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1220{
1221 struct nvme_command c;
1222
1223 memset(&c, 0, sizeof(c));
1224 c.features.opcode = nvme_admin_set_features;
1225 c.features.prp1 = cpu_to_le64(dma_addr);
1226 c.features.fid = cpu_to_le32(fid);
1227 c.features.dword11 = cpu_to_le32(dword11);
1228
d29ec824
CH		 1229 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1230 result, 0);
1231}
1232
1233int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1234{
e44ac588
AM		 1235 struct nvme_command c = { };
1236 int error;
1237
1238 c.common.opcode = nvme_admin_get_log_page,
1239 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
1240 c.common.cdw10[0] = cpu_to_le32(
d29ec824
CH		 1241 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1242 NVME_LOG_SMART),
d29ec824
CH		 1243
1244 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1245 if (!*log)
1246 return -ENOMEM;
1247
1248 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1249 sizeof(struct nvme_smart_log));
1250 if (error)
1251 kfree(*log);
1252 return error;
bc5fc7e4
MW		 1253}
1254
c30341dc 1255/**
a4aea562 1256 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1257 *
1258 * Schedule controller reset if the command was already aborted once before and
1259 * still hasn't been returned to the driver, or if this is the admin queue.
1260 */
a4aea562 1261static void nvme_abort_req(struct request *req)
c30341dc 1262{
a4aea562
MB		 1263 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1264 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1265 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1266 struct request *abort_req;
1267 struct nvme_cmd_info *abort_cmd;
1268 struct nvme_command cmd;
c30341dc 1269
a4aea562 1270 if (!nvmeq->qid || cmd_rq->aborted) {
7a509a6b
KB		 1271 unsigned long flags;
1272
1273 spin_lock_irqsave(&dev_list_lock, flags);
c30341dc 1274 if (work_busy(&dev->reset_work))
7a509a6b 1275 goto out;
c30341dc 1276 list_del_init(&dev->node);
e75ec752 1277 dev_warn(dev->dev, "I/O %d QID %d timeout, reset controller\n",
a4aea562 1278 req->tag, nvmeq->qid);
9ca97374 1279 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc 1280 queue_work(nvme_workq, &dev->reset_work);
7a509a6b
KB		 1281 out:
1282 spin_unlock_irqrestore(&dev_list_lock, flags);
c30341dc
KB		 1283 return;
1284 }
1285
1286 if (!dev->abort_limit)
1287 return;
1288
a4aea562
MB		 1289 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1290 false);
9f173b33 1291 if (IS_ERR(abort_req))
c30341dc
KB		 1292 return;
1293
a4aea562
MB		 1294 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1295 nvme_set_info(abort_cmd, abort_req, abort_completion);
1296
c30341dc
KB		 1297 memset(&cmd, 0, sizeof(cmd));
1298 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1299 cmd.abort.cid = req->tag;
c30341dc 1300 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1301 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1302
1303 --dev->abort_limit;
a4aea562 1304 cmd_rq->aborted = 1;
c30341dc 1305
a4aea562 1306 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1307 nvmeq->qid);
a4aea562
MB		 1308 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1309 dev_warn(nvmeq->q_dmadev,
1310 "Could not abort I/O %d QID %d",
1311 req->tag, nvmeq->qid);
c87fd540 1312 blk_mq_free_request(abort_req);
a4aea562 1313 }
c30341dc
KB		 1314}
1315
42483228 1316static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
a09115b2 1317{
a4aea562
MB		 1318 struct nvme_queue *nvmeq = data;
1319 void *ctx;
1320 nvme_completion_fn fn;
1321 struct nvme_cmd_info *cmd;
cef6a948
KB		 1322 struct nvme_completion cqe;
1323
1324 if (!blk_mq_request_started(req))
1325 return;
a09115b2 1326
a4aea562 1327 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1328
a4aea562
MB		 1329 if (cmd->ctx == CMD_CTX_CANCELLED)
1330 return;
1331
cef6a948
KB		 1332 if (blk_queue_dying(req->q))
1333 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1334 else
1335 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1336
1337
a4aea562
MB		 1338 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1339 req->tag, nvmeq->qid);
1340 ctx = cancel_cmd_info(cmd, &fn);
1341 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1342}
1343
a4aea562 1344static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1345{
a4aea562
MB		 1346 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1347 struct nvme_queue *nvmeq = cmd->nvmeq;
1348
1349 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1350 nvmeq->qid);
7a509a6b 1351 spin_lock_irq(&nvmeq->q_lock);
07836e65 1352 nvme_abort_req(req);
7a509a6b 1353 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1354
07836e65
KB		 1355 /*
1356 * The aborted req will be completed on receiving the abort req.
1357 * We enable the timer again. If hit twice, it'll cause a device reset,
1358 * as the device then is in a faulty state.
1359 */
1360 return BLK_EH_RESET_TIMER;
a4aea562 1361}
22404274 1362
a4aea562
MB		 1363static void nvme_free_queue(struct nvme_queue *nvmeq)
1364{
9e866774
MW		 1365 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1366 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1367 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1368 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1369 kfree(nvmeq);
1370}
1371
a1a5ef99 1372static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1373{
1374 int i;
1375
a1a5ef99 1376 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1377 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1378 dev->queue_count--;
a4aea562 1379 dev->queues[i] = NULL;
f435c282 1380 nvme_free_queue(nvmeq);
121c7ad4 1381 }
22404274
KB		 1382}
1383
4d115420
KB		 1384/**
1385 * nvme_suspend_queue - put queue into suspended state
1386 * @nvmeq - queue to suspend
4d115420
KB		 1387 */
1388static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1389{
2b25d981 1390 int vector;
b60503ba 1391
a09115b2 1392 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1393 if (nvmeq->cq_vector == -1) {
1394 spin_unlock_irq(&nvmeq->q_lock);
1395 return 1;
1396 }
1397 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1398 nvmeq->dev->online_queues--;
2b25d981 1399 nvmeq->cq_vector = -1;
a09115b2
MW		 1400 spin_unlock_irq(&nvmeq->q_lock);
1401
6df3dbc8
KB		 1402 if (!nvmeq->qid && nvmeq->dev->admin_q)
1403 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1404
aba2080f
MW		 1405 irq_set_affinity_hint(vector, NULL);
1406 free_irq(vector, nvmeq);
b60503ba 1407
4d115420
KB		 1408 return 0;
1409}
b60503ba 1410
4d115420
KB		 1411static void nvme_clear_queue(struct nvme_queue *nvmeq)
1412{
22404274 1413 spin_lock_irq(&nvmeq->q_lock);
42483228
KB		 1414 if (nvmeq->tags && *nvmeq->tags)
1415 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
22404274 1416 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1417}
1418
4d115420
KB		 1419static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1420{
a4aea562 1421 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1422
1423 if (!nvmeq)
1424 return;
1425 if (nvme_suspend_queue(nvmeq))
1426 return;
1427
0e53d180
KB		 1428 /* Don't tell the adapter to delete the admin queue.
1429 * Don't tell a removed adapter to delete IO queues. */
1430 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1431 adapter_delete_sq(dev, qid);
1432 adapter_delete_cq(dev, qid);
1433 }
07836e65
KB		 1434
1435 spin_lock_irq(&nvmeq->q_lock);
1436 nvme_process_cq(nvmeq);
1437 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1438}
1439
1440static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1441 int depth)
b60503ba 1442{
a4aea562 1443 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1444 if (!nvmeq)
1445 return NULL;
1446
e75ec752 1447 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1448 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1449 if (!nvmeq->cqes)
1450 goto free_nvmeq;
b60503ba 1451
e75ec752 1452 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
b60503ba
MW		 1453 &nvmeq->sq_dma_addr, GFP_KERNEL);
1454 if (!nvmeq->sq_cmds)
1455 goto free_cqdma;
1456
e75ec752 1457 nvmeq->q_dmadev = dev->dev;
091b6092 1458 nvmeq->dev = dev;
3193f07b
MW		 1459 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1460 dev->instance, qid);
b60503ba
MW		 1461 spin_lock_init(&nvmeq->q_lock);
1462 nvmeq->cq_head = 0;
82123460 1463 nvmeq->cq_phase = 1;
b80d5ccc 1464 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1465 nvmeq->q_depth = depth;
c30341dc 1466 nvmeq->qid = qid;
758dd7fd 1467 nvmeq->cq_vector = -1;
a4aea562 1468 dev->queues[qid] = nvmeq;
b60503ba 1469
36a7e993
JD		 1470 /* make sure queue descriptor is set before queue count, for kthread */
1471 mb();
1472 dev->queue_count++;
1473
b60503ba
MW		 1474 return nvmeq;
1475
1476 free_cqdma:
e75ec752 1477 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1478 nvmeq->cq_dma_addr);
1479 free_nvmeq:
1480 kfree(nvmeq);
1481 return NULL;
1482}
1483
3001082c
MW		 1484static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1485 const char *name)
1486{
58ffacb5
MW		 1487 if (use_threaded_interrupts)
1488 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1489 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1490 name, nvmeq);
3001082c 1491 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1492 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1493}
1494
22404274 1495static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1496{
22404274 1497 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1498
7be50e93 1499 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1500 nvmeq->sq_tail = 0;
1501 nvmeq->cq_head = 0;
1502 nvmeq->cq_phase = 1;
b80d5ccc 1503 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1504 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1505 dev->online_queues++;
7be50e93 1506 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1507}
1508
1509static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1510{
1511 struct nvme_dev *dev = nvmeq->dev;
1512 int result;
3f85d50b 1513
2b25d981 1514 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1515 result = adapter_alloc_cq(dev, qid, nvmeq);
1516 if (result < 0)
22404274 1517 return result;
b60503ba
MW		 1518
1519 result = adapter_alloc_sq(dev, qid, nvmeq);
1520 if (result < 0)
1521 goto release_cq;
1522
3193f07b 1523 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1524 if (result < 0)
1525 goto release_sq;
1526
22404274 1527 nvme_init_queue(nvmeq, qid);
22404274 1528 return result;
b60503ba
MW		 1529
1530 release_sq:
1531 adapter_delete_sq(dev, qid);
1532 release_cq:
1533 adapter_delete_cq(dev, qid);
22404274 1534 return result;
b60503ba
MW		 1535}
1536
ba47e386
MW		 1537static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1538{
1539 unsigned long timeout;
1540 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1541
1542 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1543
1544 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1545 msleep(100);
1546 if (fatal_signal_pending(current))
1547 return -EINTR;
1548 if (time_after(jiffies, timeout)) {
e75ec752 1549 dev_err(dev->dev,
27e8166c
MW		 1550 "Device not ready; aborting %s\n", enabled ?
1551 "initialisation" : "reset");
ba47e386
MW		 1552 return -ENODEV;
1553 }
1554 }
1555
1556 return 0;
1557}
1558
1559/*
1560 * If the device has been passed off to us in an enabled state, just clear
1561 * the enabled bit. The spec says we should set the 'shutdown notification
1562 * bits', but doing so may cause the device to complete commands to the
1563 * admin queue ... and we don't know what memory that might be pointing at!
1564 */
1565static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1566{
01079522
DM		 1567 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1568 dev->ctrl_config &= ~NVME_CC_ENABLE;
1569 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1570
ba47e386
MW		 1571 return nvme_wait_ready(dev, cap, false);
1572}
1573
1574static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1575{
01079522
DM		 1576 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1577 dev->ctrl_config |= NVME_CC_ENABLE;
1578 writel(dev->ctrl_config, &dev->bar->cc);
1579
ba47e386
MW		 1580 return nvme_wait_ready(dev, cap, true);
1581}
1582
1894d8f1
KB		 1583static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1584{
1585 unsigned long timeout;
1894d8f1 1586
01079522
DM		 1587 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1588 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1589
1590 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1591
2484f407 1592 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1593 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1594 NVME_CSTS_SHST_CMPLT) {
1595 msleep(100);
1596 if (fatal_signal_pending(current))
1597 return -EINTR;
1598 if (time_after(jiffies, timeout)) {
e75ec752 1599 dev_err(dev->dev,
1894d8f1
KB		 1600 "Device shutdown incomplete; abort shutdown\n");
1601 return -ENODEV;
1602 }
1603 }
1604
1605 return 0;
1606}
1607
a4aea562 1608static struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1609 .queue_rq = nvme_queue_rq,
a4aea562
MB		 1610 .map_queue = blk_mq_map_queue,
1611 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1612 .exit_hctx = nvme_admin_exit_hctx,
a4aea562
MB		 1613 .init_request = nvme_admin_init_request,
1614 .timeout = nvme_timeout,
1615};
1616
1617static struct blk_mq_ops nvme_mq_ops = {
1618 .queue_rq = nvme_queue_rq,
1619 .map_queue = blk_mq_map_queue,
1620 .init_hctx = nvme_init_hctx,
1621 .init_request = nvme_init_request,
1622 .timeout = nvme_timeout,
1623};
1624
ea191d2f
KB		 1625static void nvme_dev_remove_admin(struct nvme_dev *dev)
1626{
1627 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1628 blk_cleanup_queue(dev->admin_q);
1629 blk_mq_free_tag_set(&dev->admin_tagset);
1630 }
1631}
1632
a4aea562
MB		 1633static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1634{
1635 if (!dev->admin_q) {
1636 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1637 dev->admin_tagset.nr_hw_queues = 1;
1638 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1efccc9d 1639 dev->admin_tagset.reserved_tags = 1;
a4aea562 1640 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1641 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
ac3dd5bd 1642 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1643 dev->admin_tagset.driver_data = dev;
1644
1645 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1646 return -ENOMEM;
1647
1648 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1649 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1650 blk_mq_free_tag_set(&dev->admin_tagset);
1651 return -ENOMEM;
1652 }
ea191d2f
KB		 1653 if (!blk_get_queue(dev->admin_q)) {
1654 nvme_dev_remove_admin(dev);
4af0e21c 1655 dev->admin_q = NULL;
ea191d2f
KB		 1656 return -ENODEV;
1657 }
0fb59cbc
KB		 1658 } else
1659 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1660
1661 return 0;
1662}
1663
8d85fce7 1664static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1665{
ba47e386 1666 int result;
b60503ba 1667 u32 aqa;
ba47e386 1668 u64 cap = readq(&dev->bar->cap);
b60503ba 1669 struct nvme_queue *nvmeq;
1d090624
KB		 1670 unsigned page_shift = PAGE_SHIFT;
1671 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1672 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1673
1674 if (page_shift < dev_page_min) {
e75ec752 1675 dev_err(dev->dev,
1d090624
KB		 1676 "Minimum device page size (%u) too large for "
1677 "host (%u)\n", 1 << dev_page_min,
1678 1 << page_shift);
1679 return -ENODEV;
1680 }
1681 if (page_shift > dev_page_max) {
e75ec752 1682 dev_info(dev->dev,
1d090624
KB		 1683 "Device maximum page size (%u) smaller than "
1684 "host (%u); enabling work-around\n",
1685 1 << dev_page_max, 1 << page_shift);
1686 page_shift = dev_page_max;
1687 }
b60503ba 1688
ba47e386
MW		 1689 result = nvme_disable_ctrl(dev, cap);
1690 if (result < 0)
1691 return result;
b60503ba 1692
a4aea562 1693 nvmeq = dev->queues[0];
cd638946 1694 if (!nvmeq) {
2b25d981 1695 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1696 if (!nvmeq)
1697 return -ENOMEM;
cd638946 1698 }
b60503ba
MW		 1699
1700 aqa = nvmeq->q_depth - 1;
1701 aqa |= aqa << 16;
1702
1d090624
KB		 1703 dev->page_size = 1 << page_shift;
1704
01079522 1705 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1706 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1707 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1708 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1709
1710 writel(aqa, &dev->bar->aqa);
1711 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1712 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1713
ba47e386 1714 result = nvme_enable_ctrl(dev, cap);
025c557a 1715 if (result)
a4aea562
MB		 1716 goto free_nvmeq;
1717
2b25d981 1718 nvmeq->cq_vector = 0;
3193f07b 1719 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
758dd7fd
JD		 1720 if (result) {
1721 nvmeq->cq_vector = -1;
0fb59cbc 1722 goto free_nvmeq;
758dd7fd 1723 }
025c557a 1724
b60503ba 1725 return result;
a4aea562 1726
a4aea562
MB		 1727 free_nvmeq:
1728 nvme_free_queues(dev, 0);
1729 return result;
b60503ba
MW		 1730}
1731
a53295b6
MW		 1732static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1733{
1734 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1735 struct nvme_user_io io;
1736 struct nvme_command c;
d29ec824 1737 unsigned length, meta_len;
a67a9513 1738 int status, write;
a67a9513
KB		 1739 dma_addr_t meta_dma = 0;
1740 void *meta = NULL;
fec558b5 1741 void __user *metadata;
a53295b6
MW		 1742
1743 if (copy_from_user(&io, uio, sizeof(io)))
1744 return -EFAULT;
6c7d4945
MW		 1745
1746 switch (io.opcode) {
1747 case nvme_cmd_write:
1748 case nvme_cmd_read:
6bbf1acd 1749 case nvme_cmd_compare:
6413214c 1750 break;
6c7d4945 1751 default:
6bbf1acd 1752 return -EINVAL;
6c7d4945
MW		 1753 }
1754
d29ec824
CH		 1755 length = (io.nblocks + 1) << ns->lba_shift;
1756 meta_len = (io.nblocks + 1) * ns->ms;
6a398a3e 1757 metadata = (void __user *)(unsigned long)io.metadata;
d29ec824 1758 write = io.opcode & 1;
a53295b6 1759
71feb364
KB		 1760 if (ns->ext) {
1761 length += meta_len;
1762 meta_len = 0;
a67a9513
KB		 1763 }
1764 if (meta_len) {
d29ec824
CH		 1765 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1766 return -EINVAL;
1767
e75ec752 1768 meta = dma_alloc_coherent(dev->dev, meta_len,
a67a9513 1769 &meta_dma, GFP_KERNEL);
fec558b5 1770
a67a9513
KB		 1771 if (!meta) {
1772 status = -ENOMEM;
1773 goto unmap;
1774 }
1775 if (write) {
fec558b5 1776 if (copy_from_user(meta, metadata, meta_len)) {
a67a9513
KB		 1777 status = -EFAULT;
1778 goto unmap;
1779 }
1780 }
1781 }
1782
a53295b6
MW		 1783 memset(&c, 0, sizeof(c));
1784 c.rw.opcode = io.opcode;
1785 c.rw.flags = io.flags;
6c7d4945 1786 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1787 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1788 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1789 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1790 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1791 c.rw.reftag = cpu_to_le32(io.reftag);
1792 c.rw.apptag = cpu_to_le16(io.apptag);
1793 c.rw.appmask = cpu_to_le16(io.appmask);
a67a9513 1794 c.rw.metadata = cpu_to_le64(meta_dma);
d29ec824
CH		 1795
1796 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
1797 (void __user *)io.addr, length, NULL, 0);
f410c680 1798 unmap:
a67a9513
KB		 1799 if (meta) {
1800 if (status == NVME_SC_SUCCESS && !write) {
fec558b5 1801 if (copy_to_user(metadata, meta, meta_len))
a67a9513
KB		 1802 status = -EFAULT;
1803 }
e75ec752 1804 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
f410c680 1805 }
a53295b6
MW		 1806 return status;
1807}
1808
a4aea562
MB		 1809static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1810 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1811{
7963e521 1812 struct nvme_passthru_cmd cmd;
6ee44cdc 1813 struct nvme_command c;
d29ec824
CH		 1814 unsigned timeout = 0;
1815 int status;
6ee44cdc 1816
6bbf1acd
MW		 1817 if (!capable(CAP_SYS_ADMIN))
1818 return -EACCES;
1819 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1820 return -EFAULT;
6ee44cdc
MW		 1821
1822 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1823 c.common.opcode = cmd.opcode;
1824 c.common.flags = cmd.flags;
1825 c.common.nsid = cpu_to_le32(cmd.nsid);
1826 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1827 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1828 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1829 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1830 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1831 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1832 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1833 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1834
d29ec824
CH		 1835 if (cmd.timeout_ms)
1836 timeout = msecs_to_jiffies(cmd.timeout_ms);
eca18b23 1837
f705f837 1838 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
d29ec824
CH		 1839 NULL, (void __user *)cmd.addr, cmd.data_len,
1840 &cmd.result, timeout);
1841 if (status >= 0) {
1842 if (put_user(cmd.result, &ucmd->result))
1843 return -EFAULT;
6bbf1acd 1844 }
f4f117f6 1845
6ee44cdc
MW		 1846 return status;
1847}
1848
b60503ba
MW		 1849static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1850 unsigned long arg)
1851{
1852 struct nvme_ns *ns = bdev->bd_disk->private_data;
1853
1854 switch (cmd) {
6bbf1acd 1855 case NVME_IOCTL_ID:
c3bfe717 1856 force_successful_syscall_return();
6bbf1acd
MW		 1857 return ns->ns_id;
1858 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1859 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1860 case NVME_IOCTL_IO_CMD:
a4aea562 1861 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1862 case NVME_IOCTL_SUBMIT_IO:
1863 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1864 case SG_GET_VERSION_NUM:
1865 return nvme_sg_get_version_num((void __user *)arg);
1866 case SG_IO:
1867 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1868 default:
1869 return -ENOTTY;
1870 }
1871}
1872
320a3827
KB		 1873#ifdef CONFIG_COMPAT
1874static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1875 unsigned int cmd, unsigned long arg)
1876{
320a3827
KB		 1877 switch (cmd) {
1878 case SG_IO:
e179729a 1879 return -ENOIOCTLCMD;
320a3827
KB		 1880 }
1881 return nvme_ioctl(bdev, mode, cmd, arg);
1882}
1883#else
1884#define nvme_compat_ioctl NULL
1885#endif
1886
9ac27090
KB		 1887static int nvme_open(struct block_device *bdev, fmode_t mode)
1888{
9e60352c
KB		 1889 int ret = 0;
1890 struct nvme_ns *ns;
9ac27090 1891
9e60352c
KB		 1892 spin_lock(&dev_list_lock);
1893 ns = bdev->bd_disk->private_data;
1894 if (!ns)
1895 ret = -ENXIO;
1896 else if (!kref_get_unless_zero(&ns->dev->kref))
1897 ret = -ENXIO;
1898 spin_unlock(&dev_list_lock);
1899
1900 return ret;
9ac27090
KB		 1901}
1902
1903static void nvme_free_dev(struct kref *kref);
1904
1905static void nvme_release(struct gendisk *disk, fmode_t mode)
1906{
1907 struct nvme_ns *ns = disk->private_data;
1908 struct nvme_dev *dev = ns->dev;
1909
1910 kref_put(&dev->kref, nvme_free_dev);
1911}
1912
4cc09e2d
KB		 1913static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1914{
1915 /* some standard values */
1916 geo->heads = 1 << 6;
1917 geo->sectors = 1 << 5;
1918 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1919 return 0;
1920}
1921
e1e5e564
KB		 1922static void nvme_config_discard(struct nvme_ns *ns)
1923{
1924 u32 logical_block_size = queue_logical_block_size(ns->queue);
1925 ns->queue->limits.discard_zeroes_data = 0;
1926 ns->queue->limits.discard_alignment = logical_block_size;
1927 ns->queue->limits.discard_granularity = logical_block_size;
2bb4cd5c 1928 blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
e1e5e564
KB		 1929 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1930}
1931
1b9dbf7f
KB		 1932static int nvme_revalidate_disk(struct gendisk *disk)
1933{
1934 struct nvme_ns *ns = disk->private_data;
1935 struct nvme_dev *dev = ns->dev;
1936 struct nvme_id_ns *id;
a67a9513
KB		 1937 u8 lbaf, pi_type;
1938 u16 old_ms;
e1e5e564 1939 unsigned short bs;
1b9dbf7f 1940
d29ec824 1941 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
a5768aa8
KB		 1942 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
1943 dev->instance, ns->ns_id);
1944 return -ENODEV;
1b9dbf7f 1945 }
a5768aa8
KB		 1946 if (id->ncap == 0) {
1947 kfree(id);
1948 return -ENODEV;
e1e5e564 1949 }
1b9dbf7f 1950
e1e5e564
KB		 1951 old_ms = ns->ms;
1952 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1b9dbf7f 1953 ns->lba_shift = id->lbaf[lbaf].ds;
e1e5e564 1954 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
a67a9513 1955 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
e1e5e564
KB		 1956
1957 /*
1958 * If identify namespace failed, use default 512 byte block size so
1959 * block layer can use before failing read/write for 0 capacity.
1960 */
1961 if (ns->lba_shift == 0)
1962 ns->lba_shift = 9;
1963 bs = 1 << ns->lba_shift;
1964
1965 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
1966 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
1967 id->dps & NVME_NS_DPS_PI_MASK : 0;
1968
52b68d7e
KB		 1969 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
1970 ns->ms != old_ms ||
e1e5e564 1971 bs != queue_logical_block_size(disk->queue) ||
a67a9513 1972 (ns->ms && ns->ext)))
e1e5e564
KB		 1973 blk_integrity_unregister(disk);
1974
1975 ns->pi_type = pi_type;
1976 blk_queue_logical_block_size(ns->queue, bs);
1977
52b68d7e 1978 if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
a67a9513 1979 !ns->ext)
e1e5e564
KB		 1980 nvme_init_integrity(ns);
1981
a5768aa8 1982 if (ns->ms && !blk_get_integrity(disk))
e1e5e564
KB		 1983 set_capacity(disk, 0);
1984 else
1985 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1986
1987 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1988 nvme_config_discard(ns);
1b9dbf7f 1989
d29ec824 1990 kfree(id);
1b9dbf7f
KB		 1991 return 0;
1992}
1993
b60503ba
MW		 1994static const struct block_device_operations nvme_fops = {
1995 .owner = THIS_MODULE,
1996 .ioctl = nvme_ioctl,
320a3827 1997 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1998 .open = nvme_open,
1999 .release = nvme_release,
4cc09e2d 2000 .getgeo = nvme_getgeo,
1b9dbf7f 2001 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 2002};
2003
1fa6aead
MW		 2004static int nvme_kthread(void *data)
2005{
d4b4ff8e 2006 struct nvme_dev *dev, *next;
1fa6aead
MW		 2007
2008 while (!kthread_should_stop()) {
564a232c 2009 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 2010 spin_lock(&dev_list_lock);
d4b4ff8e 2011 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 2012 int i;
07836e65 2013 if (readl(&dev->bar->csts) & NVME_CSTS_CFS) {
d4b4ff8e
KB		 2014 if (work_busy(&dev->reset_work))
2015 continue;
2016 list_del_init(&dev->node);
e75ec752 2017 dev_warn(dev->dev,
a4aea562
MB		 2018 "Failed status: %x, reset controller\n",
2019 readl(&dev->bar->csts));
9ca97374 2020 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 2021 queue_work(nvme_workq, &dev->reset_work);
2022 continue;
2023 }
1fa6aead 2024 for (i = 0; i < dev->queue_count; i++) {
a4aea562 2025 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 2026 if (!nvmeq)
2027 continue;
1fa6aead 2028 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 2029 nvme_process_cq(nvmeq);
6fccf938
KB		 2030
2031 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 2032 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 2033 break;
2034 dev->event_limit--;
2035 }
1fa6aead
MW		 2036 spin_unlock_irq(&nvmeq->q_lock);
2037 }
2038 }
2039 spin_unlock(&dev_list_lock);
acb7aa0d 2040 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 2041 }
2042 return 0;
2043}
2044
e1e5e564 2045static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
b60503ba
MW		 2046{
2047 struct nvme_ns *ns;
2048 struct gendisk *disk;
e75ec752 2049 int node = dev_to_node(dev->dev);
b60503ba 2050
a4aea562 2051 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba 2052 if (!ns)
e1e5e564
KB		 2053 return;
2054
a4aea562 2055 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 2056 if (IS_ERR(ns->queue))
b60503ba 2057 goto out_free_ns;
4eeb9215
MW		 2058 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2059 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 2060 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 2061 ns->dev = dev;
2062 ns->queue->queuedata = ns;
2063
a4aea562 2064 disk = alloc_disk_node(0, node);
b60503ba
MW		 2065 if (!disk)
2066 goto out_free_queue;
a4aea562 2067
5aff9382 2068 ns->ns_id = nsid;
b60503ba 2069 ns->disk = disk;
e1e5e564
KB		 2070 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2071 list_add_tail(&ns->list, &dev->namespaces);
2072
e9ef4636 2073 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 2074 if (dev->max_hw_sectors)
2075 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 2076 if (dev->stripe_size)
2077 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2078 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2079 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 2080
2081 disk->major = nvme_major;
469071a3 2082 disk->first_minor = 0;
b60503ba
MW		 2083 disk->fops = &nvme_fops;
2084 disk->private_data = ns;
2085 disk->queue = ns->queue;
b3fffdef 2086 disk->driverfs_dev = dev->device;
469071a3 2087 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2088 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba 2089
e1e5e564
KB		 2090 /*
2091 * Initialize capacity to 0 until we establish the namespace format and
2092 * setup integrity extentions if necessary. The revalidate_disk after
2093 * add_disk allows the driver to register with integrity if the format
2094 * requires it.
2095 */
2096 set_capacity(disk, 0);
a5768aa8
KB		 2097 if (nvme_revalidate_disk(ns->disk))
2098 goto out_free_disk;
2099
e1e5e564 2100 add_disk(ns->disk);
7bee6074
KB		 2101 if (ns->ms) {
2102 struct block_device *bd = bdget_disk(ns->disk, 0);
2103 if (!bd)
2104 return;
2105 if (blkdev_get(bd, FMODE_READ, NULL)) {
2106 bdput(bd);
2107 return;
2108 }
2109 blkdev_reread_part(bd);
2110 blkdev_put(bd, FMODE_READ);
2111 }
e1e5e564 2112 return;
a5768aa8
KB		 2113 out_free_disk:
2114 kfree(disk);
2115 list_del(&ns->list);
b60503ba
MW		 2116 out_free_queue:
2117 blk_cleanup_queue(ns->queue);
2118 out_free_ns:
2119 kfree(ns);
b60503ba
MW		 2120}
2121
42f61420
KB		 2122static void nvme_create_io_queues(struct nvme_dev *dev)
2123{
a4aea562 2124 unsigned i;
42f61420 2125
a4aea562 2126 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2127 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2128 break;
2129
a4aea562
MB		 2130 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2131 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 2132 break;
2133}
2134
b3b06812 2135static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2136{
2137 int status;
2138 u32 result;
b3b06812 2139 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2140
df348139 2141 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2142 &result);
27e8166c
MW		 2143 if (status < 0)
2144 return status;
2145 if (status > 0) {
e75ec752 2146 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
badc34d4 2147 return 0;
27e8166c 2148 }
b60503ba
MW		 2149 return min(result & 0xffff, result >> 16) + 1;
2150}
2151
9d713c2b
KB		 2152static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2153{
b80d5ccc 2154 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2155}
2156
8d85fce7 2157static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2158{
a4aea562 2159 struct nvme_queue *adminq = dev->queues[0];
e75ec752 2160 struct pci_dev *pdev = to_pci_dev(dev->dev);
42f61420 2161 int result, i, vecs, nr_io_queues, size;
b60503ba 2162
42f61420 2163 nr_io_queues = num_possible_cpus();
b348b7d5 2164 result = set_queue_count(dev, nr_io_queues);
badc34d4 2165 if (result <= 0)
1b23484b 2166 return result;
b348b7d5
MW		 2167 if (result < nr_io_queues)
2168 nr_io_queues = result;
b60503ba 2169
9d713c2b
KB		 2170 size = db_bar_size(dev, nr_io_queues);
2171 if (size > 8192) {
f1938f6e 2172 iounmap(dev->bar);
9d713c2b
KB		 2173 do {
2174 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2175 if (dev->bar)
2176 break;
2177 if (!--nr_io_queues)
2178 return -ENOMEM;
2179 size = db_bar_size(dev, nr_io_queues);
2180 } while (1);
f1938f6e 2181 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2182 adminq->q_db = dev->dbs;
f1938f6e
MW		 2183 }
2184
9d713c2b 2185 /* Deregister the admin queue's interrupt */
3193f07b 2186 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2187
e32efbfc
JA		 2188 /*
2189 * If we enable msix early due to not intx, disable it again before
2190 * setting up the full range we need.
2191 */
2192 if (!pdev->irq)
2193 pci_disable_msix(pdev);
2194
be577fab 2195 for (i = 0; i < nr_io_queues; i++)
1b23484b 2196 dev->entry[i].entry = i;
be577fab
AG		 2197 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2198 if (vecs < 0) {
2199 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2200 if (vecs < 0) {
2201 vecs = 1;
2202 } else {
2203 for (i = 0; i < vecs; i++)
2204 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2205 }
2206 }
2207
063a8096
MW		 2208 /*
2209 * Should investigate if there's a performance win from allocating
2210 * more queues than interrupt vectors; it might allow the submission
2211 * path to scale better, even if the receive path is limited by the
2212 * number of interrupts.
2213 */
2214 nr_io_queues = vecs;
42f61420 2215 dev->max_qid = nr_io_queues;
063a8096 2216
3193f07b 2217 result = queue_request_irq(dev, adminq, adminq->irqname);
758dd7fd
JD		 2218 if (result) {
2219 adminq->cq_vector = -1;
22404274 2220 goto free_queues;
758dd7fd 2221 }
1b23484b 2222
cd638946 2223 /* Free previously allocated queues that are no longer usable */
42f61420 2224 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2225 nvme_create_io_queues(dev);
9ecdc946 2226
22404274 2227 return 0;
b60503ba 2228
22404274 2229 free_queues:
a1a5ef99 2230 nvme_free_queues(dev, 1);
22404274 2231 return result;
b60503ba
MW		 2232}
2233
a5768aa8
KB		 2234static void nvme_free_namespace(struct nvme_ns *ns)
2235{
2236 list_del(&ns->list);
2237
2238 spin_lock(&dev_list_lock);
2239 ns->disk->private_data = NULL;
2240 spin_unlock(&dev_list_lock);
2241
2242 put_disk(ns->disk);
2243 kfree(ns);
2244}
2245
2246static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2247{
2248 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2249 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2250
2251 return nsa->ns_id - nsb->ns_id;
2252}
2253
2254static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2255{
2256 struct nvme_ns *ns;
2257
2258 list_for_each_entry(ns, &dev->namespaces, list) {
2259 if (ns->ns_id == nsid)
2260 return ns;
2261 if (ns->ns_id > nsid)
2262 break;
2263 }
2264 return NULL;
2265}
2266
2267static inline bool nvme_io_incapable(struct nvme_dev *dev)
2268{
2269 return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
2270 dev->online_queues < 2);
2271}
2272
2273static void nvme_ns_remove(struct nvme_ns *ns)
2274{
2275 bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2276
2277 if (kill)
2278 blk_set_queue_dying(ns->queue);
2279 if (ns->disk->flags & GENHD_FL_UP) {
2280 if (blk_get_integrity(ns->disk))
2281 blk_integrity_unregister(ns->disk);
2282 del_gendisk(ns->disk);
2283 }
2284 if (kill || !blk_queue_dying(ns->queue)) {
2285 blk_mq_abort_requeue_list(ns->queue);
2286 blk_cleanup_queue(ns->queue);
2287 }
2288}
2289
2290static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2291{
2292 struct nvme_ns *ns, *next;
2293 unsigned i;
2294
2295 for (i = 1; i <= nn; i++) {
2296 ns = nvme_find_ns(dev, i);
2297 if (ns) {
2298 if (revalidate_disk(ns->disk)) {
2299 nvme_ns_remove(ns);
2300 nvme_free_namespace(ns);
2301 }
2302 } else
2303 nvme_alloc_ns(dev, i);
2304 }
2305 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2306 if (ns->ns_id > nn) {
2307 nvme_ns_remove(ns);
2308 nvme_free_namespace(ns);
2309 }
2310 }
2311 list_sort(NULL, &dev->namespaces, ns_cmp);
2312}
2313
2314static void nvme_dev_scan(struct work_struct *work)
2315{
2316 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2317 struct nvme_id_ctrl *ctrl;
2318
2319 if (!dev->tagset.tags)
2320 return;
2321 if (nvme_identify_ctrl(dev, &ctrl))
2322 return;
2323 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2324 kfree(ctrl);
2325}
2326
422ef0c7
MW		 2327/*
2328 * Return: error value if an error occurred setting up the queues or calling
2329 * Identify Device. 0 if these succeeded, even if adding some of the
2330 * namespaces failed. At the moment, these failures are silent. TBD which
2331 * failures should be reported.
2332 */
8d85fce7 2333static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2334{
e75ec752 2335 struct pci_dev *pdev = to_pci_dev(dev->dev);
c3bfe717 2336 int res;
a5768aa8 2337 unsigned nn;
51814232 2338 struct nvme_id_ctrl *ctrl;
159b67d7 2339 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2340
d29ec824 2341 res = nvme_identify_ctrl(dev, &ctrl);
b60503ba 2342 if (res) {
e75ec752 2343 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
e1e5e564 2344 return -EIO;
b60503ba
MW		 2345 }
2346
51814232 2347 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2348 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2349 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2350 dev->vwc = ctrl->vwc;
51814232
MW		 2351 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2352 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2353 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2354 if (ctrl->mdts)
8fc23e03 2355 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2356 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2357 (pdev->device == 0x0953) && ctrl->vs[3]) {
2358 unsigned int max_hw_sectors;
2359
159b67d7 2360 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2361 max_hw_sectors = dev->stripe_size >> (shift - 9);
2362 if (dev->max_hw_sectors) {
2363 dev->max_hw_sectors = min(max_hw_sectors,
2364 dev->max_hw_sectors);
2365 } else
2366 dev->max_hw_sectors = max_hw_sectors;
2367 }
d29ec824 2368 kfree(ctrl);
a4aea562 2369
ffe7704d
KB		 2370 if (!dev->tagset.tags) {
2371 dev->tagset.ops = &nvme_mq_ops;
2372 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2373 dev->tagset.timeout = NVME_IO_TIMEOUT;
2374 dev->tagset.numa_node = dev_to_node(dev->dev);
2375 dev->tagset.queue_depth =
a4aea562 2376 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ffe7704d
KB		 2377 dev->tagset.cmd_size = nvme_cmd_size(dev);
2378 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2379 dev->tagset.driver_data = dev;
b60503ba 2380
ffe7704d
KB		 2381 if (blk_mq_alloc_tag_set(&dev->tagset))
2382 return 0;
2383 }
a5768aa8 2384 schedule_work(&dev->scan_work);
e1e5e564 2385 return 0;
b60503ba
MW		 2386}
2387
0877cb0d
KB		 2388static int nvme_dev_map(struct nvme_dev *dev)
2389{
42f61420 2390 u64 cap;
0877cb0d 2391 int bars, result = -ENOMEM;
e75ec752 2392 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2393
2394 if (pci_enable_device_mem(pdev))
2395 return result;
2396
2397 dev->entry[0].vector = pdev->irq;
2398 pci_set_master(pdev);
2399 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2400 if (!bars)
2401 goto disable_pci;
2402
0877cb0d
KB		 2403 if (pci_request_selected_regions(pdev, bars, "nvme"))
2404 goto disable_pci;
2405
e75ec752
CH		 2406 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2407 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2408 goto disable;
0877cb0d 2409
0877cb0d
KB		 2410 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2411 if (!dev->bar)
2412 goto disable;
e32efbfc 2413
0e53d180
KB		 2414 if (readl(&dev->bar->csts) == -1) {
2415 result = -ENODEV;
2416 goto unmap;
2417 }
e32efbfc
JA		 2418
2419 /*
2420 * Some devices don't advertse INTx interrupts, pre-enable a single
2421 * MSIX vec for setup. We'll adjust this later.
2422 */
2423 if (!pdev->irq) {
2424 result = pci_enable_msix(pdev, dev->entry, 1);
2425 if (result < 0)
2426 goto unmap;
2427 }
2428
42f61420
KB		 2429 cap = readq(&dev->bar->cap);
2430 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2431 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2432 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2433
2434 return 0;
2435
0e53d180
KB		 2436 unmap:
2437 iounmap(dev->bar);
2438 dev->bar = NULL;
0877cb0d
KB		 2439 disable:
2440 pci_release_regions(pdev);
2441 disable_pci:
2442 pci_disable_device(pdev);
2443 return result;
2444}
2445
2446static void nvme_dev_unmap(struct nvme_dev *dev)
2447{
e75ec752
CH		 2448 struct pci_dev *pdev = to_pci_dev(dev->dev);
2449
2450 if (pdev->msi_enabled)
2451 pci_disable_msi(pdev);
2452 else if (pdev->msix_enabled)
2453 pci_disable_msix(pdev);
0877cb0d
KB		 2454
2455 if (dev->bar) {
2456 iounmap(dev->bar);
2457 dev->bar = NULL;
e75ec752 2458 pci_release_regions(pdev);
0877cb0d
KB		 2459 }
2460
e75ec752
CH		 2461 if (pci_is_enabled(pdev))
2462 pci_disable_device(pdev);
0877cb0d
KB		 2463}
2464
4d115420
KB		 2465struct nvme_delq_ctx {
2466 struct task_struct *waiter;
2467 struct kthread_worker *worker;
2468 atomic_t refcount;
2469};
2470
2471static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2472{
2473 dq->waiter = current;
2474 mb();
2475
2476 for (;;) {
2477 set_current_state(TASK_KILLABLE);
2478 if (!atomic_read(&dq->refcount))
2479 break;
2480 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2481 fatal_signal_pending(current)) {
0fb59cbc
KB		 2482 /*
2483 * Disable the controller first since we can't trust it
2484 * at this point, but leave the admin queue enabled
2485 * until all queue deletion requests are flushed.
2486 * FIXME: This may take a while if there are more h/w
2487 * queues than admin tags.
2488 */
4d115420 2489 set_current_state(TASK_RUNNING);
4d115420 2490 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2491 nvme_clear_queue(dev->queues[0]);
4d115420 2492 flush_kthread_worker(dq->worker);
0fb59cbc 2493 nvme_disable_queue(dev, 0);
4d115420
KB		 2494 return;
2495 }
2496 }
2497 set_current_state(TASK_RUNNING);
2498}
2499
2500static void nvme_put_dq(struct nvme_delq_ctx *dq)
2501{
2502 atomic_dec(&dq->refcount);
2503 if (dq->waiter)
2504 wake_up_process(dq->waiter);
2505}
2506
2507static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2508{
2509 atomic_inc(&dq->refcount);
2510 return dq;
2511}
2512
2513static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2514{
2515 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
4d115420
KB		 2516 nvme_put_dq(dq);
2517}
2518
2519static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2520 kthread_work_func_t fn)
2521{
2522 struct nvme_command c;
2523
2524 memset(&c, 0, sizeof(c));
2525 c.delete_queue.opcode = opcode;
2526 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2527
2528 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2529 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2530 ADMIN_TIMEOUT);
4d115420
KB		 2531}
2532
2533static void nvme_del_cq_work_handler(struct kthread_work *work)
2534{
2535 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2536 cmdinfo.work);
2537 nvme_del_queue_end(nvmeq);
2538}
2539
2540static int nvme_delete_cq(struct nvme_queue *nvmeq)
2541{
2542 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2543 nvme_del_cq_work_handler);
2544}
2545
2546static void nvme_del_sq_work_handler(struct kthread_work *work)
2547{
2548 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2549 cmdinfo.work);
2550 int status = nvmeq->cmdinfo.status;
2551
2552 if (!status)
2553 status = nvme_delete_cq(nvmeq);
2554 if (status)
2555 nvme_del_queue_end(nvmeq);
2556}
2557
2558static int nvme_delete_sq(struct nvme_queue *nvmeq)
2559{
2560 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2561 nvme_del_sq_work_handler);
2562}
2563
2564static void nvme_del_queue_start(struct kthread_work *work)
2565{
2566 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2567 cmdinfo.work);
4d115420
KB		 2568 if (nvme_delete_sq(nvmeq))
2569 nvme_del_queue_end(nvmeq);
2570}
2571
2572static void nvme_disable_io_queues(struct nvme_dev *dev)
2573{
2574 int i;
2575 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2576 struct nvme_delq_ctx dq;
2577 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2578 &worker, "nvme%d", dev->instance);
2579
2580 if (IS_ERR(kworker_task)) {
e75ec752 2581 dev_err(dev->dev,
4d115420
KB		 2582 "Failed to create queue del task\n");
2583 for (i = dev->queue_count - 1; i > 0; i--)
2584 nvme_disable_queue(dev, i);
2585 return;
2586 }
2587
2588 dq.waiter = NULL;
2589 atomic_set(&dq.refcount, 0);
2590 dq.worker = &worker;
2591 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2592 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2593
2594 if (nvme_suspend_queue(nvmeq))
2595 continue;
2596 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2597 nvmeq->cmdinfo.worker = dq.worker;
2598 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2599 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2600 }
2601 nvme_wait_dq(&dq, dev);
2602 kthread_stop(kworker_task);
2603}
2604
b9afca3e
DM		 2605/*
2606* Remove the node from the device list and check
2607* for whether or not we need to stop the nvme_thread.
2608*/
2609static void nvme_dev_list_remove(struct nvme_dev *dev)
2610{
2611 struct task_struct *tmp = NULL;
2612
2613 spin_lock(&dev_list_lock);
2614 list_del_init(&dev->node);
2615 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2616 tmp = nvme_thread;
2617 nvme_thread = NULL;
2618 }
2619 spin_unlock(&dev_list_lock);
2620
2621 if (tmp)
2622 kthread_stop(tmp);
2623}
2624
c9d3bf88
KB		 2625static void nvme_freeze_queues(struct nvme_dev *dev)
2626{
2627 struct nvme_ns *ns;
2628
2629 list_for_each_entry(ns, &dev->namespaces, list) {
2630 blk_mq_freeze_queue_start(ns->queue);
2631
cddcd72b 2632 spin_lock_irq(ns->queue->queue_lock);
c9d3bf88 2633 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
cddcd72b 2634 spin_unlock_irq(ns->queue->queue_lock);
c9d3bf88
KB		 2635
2636 blk_mq_cancel_requeue_work(ns->queue);
2637 blk_mq_stop_hw_queues(ns->queue);
2638 }
2639}
2640
2641static void nvme_unfreeze_queues(struct nvme_dev *dev)
2642{
2643 struct nvme_ns *ns;
2644
2645 list_for_each_entry(ns, &dev->namespaces, list) {
2646 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2647 blk_mq_unfreeze_queue(ns->queue);
2648 blk_mq_start_stopped_hw_queues(ns->queue, true);
2649 blk_mq_kick_requeue_list(ns->queue);
2650 }
2651}
2652
f0b50732 2653static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2654{
22404274 2655 int i;
7c1b2450 2656 u32 csts = -1;
22404274 2657
b9afca3e 2658 nvme_dev_list_remove(dev);
1fa6aead 2659
c9d3bf88
KB		 2660 if (dev->bar) {
2661 nvme_freeze_queues(dev);
7c1b2450 2662 csts = readl(&dev->bar->csts);
c9d3bf88 2663 }
7c1b2450 2664 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2665 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2666 struct nvme_queue *nvmeq = dev->queues[i];
4d115420 2667 nvme_suspend_queue(nvmeq);
4d115420
KB		 2668 }
2669 } else {
2670 nvme_disable_io_queues(dev);
1894d8f1 2671 nvme_shutdown_ctrl(dev);
4d115420
KB		 2672 nvme_disable_queue(dev, 0);
2673 }
f0b50732 2674 nvme_dev_unmap(dev);
07836e65
KB		 2675
2676 for (i = dev->queue_count - 1; i >= 0; i--)
2677 nvme_clear_queue(dev->queues[i]);
f0b50732
KB		 2678}
2679
2680static void nvme_dev_remove(struct nvme_dev *dev)
2681{
9ac27090 2682 struct nvme_ns *ns;
f0b50732 2683
a5768aa8
KB		 2684 list_for_each_entry(ns, &dev->namespaces, list)
2685 nvme_ns_remove(ns);
b60503ba
MW		 2686}
2687
091b6092
MW		 2688static int nvme_setup_prp_pools(struct nvme_dev *dev)
2689{
e75ec752 2690 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2691 PAGE_SIZE, PAGE_SIZE, 0);
2692 if (!dev->prp_page_pool)
2693 return -ENOMEM;
2694
99802a7a 2695 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2696 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2697 256, 256, 0);
2698 if (!dev->prp_small_pool) {
2699 dma_pool_destroy(dev->prp_page_pool);
2700 return -ENOMEM;
2701 }
091b6092
MW		 2702 return 0;
2703}
2704
2705static void nvme_release_prp_pools(struct nvme_dev *dev)
2706{
2707 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2708 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2709}
2710
cd58ad7d
QSA		 2711static DEFINE_IDA(nvme_instance_ida);
2712
2713static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2714{
cd58ad7d
QSA		 2715 int instance, error;
2716
2717 do {
2718 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2719 return -ENODEV;
2720
2721 spin_lock(&dev_list_lock);
2722 error = ida_get_new(&nvme_instance_ida, &instance);
2723 spin_unlock(&dev_list_lock);
2724 } while (error == -EAGAIN);
2725
2726 if (error)
2727 return -ENODEV;
2728
2729 dev->instance = instance;
2730 return 0;
b60503ba
MW		 2731}
2732
2733static void nvme_release_instance(struct nvme_dev *dev)
2734{
cd58ad7d
QSA		 2735 spin_lock(&dev_list_lock);
2736 ida_remove(&nvme_instance_ida, dev->instance);
2737 spin_unlock(&dev_list_lock);
b60503ba
MW		 2738}
2739
9ac27090
KB		 2740static void nvme_free_namespaces(struct nvme_dev *dev)
2741{
2742 struct nvme_ns *ns, *next;
2743
a5768aa8
KB		 2744 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
2745 nvme_free_namespace(ns);
9ac27090
KB		 2746}
2747
5e82e952
KB		 2748static void nvme_free_dev(struct kref *kref)
2749{
2750 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2751
e75ec752 2752 put_device(dev->dev);
b3fffdef 2753 put_device(dev->device);
9ac27090 2754 nvme_free_namespaces(dev);
285dffc9 2755 nvme_release_instance(dev);
4af0e21c
KB		 2756 if (dev->tagset.tags)
2757 blk_mq_free_tag_set(&dev->tagset);
2758 if (dev->admin_q)
2759 blk_put_queue(dev->admin_q);
5e82e952
KB		 2760 kfree(dev->queues);
2761 kfree(dev->entry);
2762 kfree(dev);
2763}
2764
2765static int nvme_dev_open(struct inode *inode, struct file *f)
2766{
b3fffdef
KB		 2767 struct nvme_dev *dev;
2768 int instance = iminor(inode);
2769 int ret = -ENODEV;
2770
2771 spin_lock(&dev_list_lock);
2772 list_for_each_entry(dev, &dev_list, node) {
2773 if (dev->instance == instance) {
2e1d8448
KB		 2774 if (!dev->admin_q) {
2775 ret = -EWOULDBLOCK;
2776 break;
2777 }
b3fffdef
KB		 2778 if (!kref_get_unless_zero(&dev->kref))
2779 break;
2780 f->private_data = dev;
2781 ret = 0;
2782 break;
2783 }
2784 }
2785 spin_unlock(&dev_list_lock);
2786
2787 return ret;
5e82e952
KB		 2788}
2789
2790static int nvme_dev_release(struct inode *inode, struct file *f)
2791{
2792 struct nvme_dev *dev = f->private_data;
2793 kref_put(&dev->kref, nvme_free_dev);
2794 return 0;
2795}
2796
2797static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2798{
2799 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2800 struct nvme_ns *ns;
2801
5e82e952
KB		 2802 switch (cmd) {
2803 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2804 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2805 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2806 if (list_empty(&dev->namespaces))
2807 return -ENOTTY;
2808 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2809 return nvme_user_cmd(dev, ns, (void __user *)arg);
4cc06521
KB		 2810 case NVME_IOCTL_RESET:
2811 dev_warn(dev->dev, "resetting controller\n");
2812 return nvme_reset(dev);
5e82e952
KB		 2813 default:
2814 return -ENOTTY;
2815 }
2816}
2817
2818static const struct file_operations nvme_dev_fops = {
2819 .owner = THIS_MODULE,
2820 .open = nvme_dev_open,
2821 .release = nvme_dev_release,
2822 .unlocked_ioctl = nvme_dev_ioctl,
2823 .compat_ioctl = nvme_dev_ioctl,
2824};
2825
a4aea562
MB		 2826static void nvme_set_irq_hints(struct nvme_dev *dev)
2827{
2828 struct nvme_queue *nvmeq;
2829 int i;
2830
2831 for (i = 0; i < dev->online_queues; i++) {
2832 nvmeq = dev->queues[i];
2833
42483228 2834 if (!nvmeq->tags || !(*nvmeq->tags))
a4aea562
MB		 2835 continue;
2836
2837 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
42483228 2838 blk_mq_tags_cpumask(*nvmeq->tags));
a4aea562
MB		 2839 }
2840}
2841
f0b50732
KB		 2842static int nvme_dev_start(struct nvme_dev *dev)
2843{
2844 int result;
b9afca3e 2845 bool start_thread = false;
f0b50732
KB		 2846
2847 result = nvme_dev_map(dev);
2848 if (result)
2849 return result;
2850
2851 result = nvme_configure_admin_queue(dev);
2852 if (result)
2853 goto unmap;
2854
2855 spin_lock(&dev_list_lock);
b9afca3e
DM		 2856 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2857 start_thread = true;
2858 nvme_thread = NULL;
2859 }
f0b50732
KB		 2860 list_add(&dev->node, &dev_list);
2861 spin_unlock(&dev_list_lock);
2862
b9afca3e
DM		 2863 if (start_thread) {
2864 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2865 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2866 } else
2867 wait_event_killable(nvme_kthread_wait, nvme_thread);
2868
2869 if (IS_ERR_OR_NULL(nvme_thread)) {
2870 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2871 goto disable;
2872 }
a4aea562
MB		 2873
2874 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 2875 result = nvme_alloc_admin_tags(dev);
2876 if (result)
2877 goto disable;
b9afca3e 2878
f0b50732 2879 result = nvme_setup_io_queues(dev);
badc34d4 2880 if (result)
0fb59cbc 2881 goto free_tags;
f0b50732 2882
a4aea562
MB		 2883 nvme_set_irq_hints(dev);
2884
1efccc9d 2885 dev->event_limit = 1;
d82e8bfd 2886 return result;
f0b50732 2887
0fb59cbc
KB		 2888 free_tags:
2889 nvme_dev_remove_admin(dev);
4af0e21c
KB		 2890 blk_put_queue(dev->admin_q);
2891 dev->admin_q = NULL;
2892 dev->queues[0]->tags = NULL;
f0b50732 2893 disable:
a1a5ef99 2894 nvme_disable_queue(dev, 0);
b9afca3e 2895 nvme_dev_list_remove(dev);
f0b50732
KB		 2896 unmap:
2897 nvme_dev_unmap(dev);
2898 return result;
2899}
2900
9a6b9458
KB		 2901static int nvme_remove_dead_ctrl(void *arg)
2902{
2903 struct nvme_dev *dev = (struct nvme_dev *)arg;
e75ec752 2904 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2905
2906 if (pci_get_drvdata(pdev))
c81f4975 2907 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2908 kref_put(&dev->kref, nvme_free_dev);
2909 return 0;
2910}
2911
2912static void nvme_remove_disks(struct work_struct *ws)
2913{
9a6b9458
KB		 2914 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2915
5a92e700 2916 nvme_free_queues(dev, 1);
302c6727 2917 nvme_dev_remove(dev);
9a6b9458
KB		 2918}
2919
2920static int nvme_dev_resume(struct nvme_dev *dev)
2921{
2922 int ret;
2923
2924 ret = nvme_dev_start(dev);
badc34d4 2925 if (ret)
9a6b9458 2926 return ret;
badc34d4 2927 if (dev->online_queues < 2) {
9a6b9458 2928 spin_lock(&dev_list_lock);
9ca97374 2929 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2930 queue_work(nvme_workq, &dev->reset_work);
2931 spin_unlock(&dev_list_lock);
c9d3bf88
KB		 2932 } else {
2933 nvme_unfreeze_queues(dev);
ffe7704d 2934 nvme_dev_add(dev);
c9d3bf88 2935 nvme_set_irq_hints(dev);
9a6b9458
KB		 2936 }
2937 return 0;
2938}
2939
de3eff2b
KB		 2940static void nvme_dead_ctrl(struct nvme_dev *dev)
2941{
2942 dev_warn(dev->dev, "Device failed to resume\n");
2943 kref_get(&dev->kref);
2944 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2945 dev->instance))) {
2946 dev_err(dev->dev,
2947 "Failed to start controller remove task\n");
2948 kref_put(&dev->kref, nvme_free_dev);
2949 }
2950}
2951
9a6b9458
KB		 2952static void nvme_dev_reset(struct nvme_dev *dev)
2953{
ffe7704d
KB		 2954 bool in_probe = work_busy(&dev->probe_work);
2955
9a6b9458 2956 nvme_dev_shutdown(dev);
ffe7704d
KB		 2957
2958 /* Synchronize with device probe so that work will see failure status
2959 * and exit gracefully without trying to schedule another reset */
2960 flush_work(&dev->probe_work);
2961
2962 /* Fail this device if reset occured during probe to avoid
2963 * infinite initialization loops. */
2964 if (in_probe) {
de3eff2b 2965 nvme_dead_ctrl(dev);
ffe7704d 2966 return;
9a6b9458 2967 }
ffe7704d
KB		 2968 /* Schedule device resume asynchronously so the reset work is available
2969 * to cleanup errors that may occur during reinitialization */
2970 schedule_work(&dev->probe_work);
9a6b9458
KB		 2971}
2972
2973static void nvme_reset_failed_dev(struct work_struct *ws)
2974{
2975 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2976 nvme_dev_reset(dev);
2977}
2978
9ca97374
TH		 2979static void nvme_reset_workfn(struct work_struct *work)
2980{
2981 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2982 dev->reset_workfn(work);
2983}
2984
4cc06521
KB		 2985static int nvme_reset(struct nvme_dev *dev)
2986{
2987 int ret = -EBUSY;
2988
2989 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
2990 return -ENODEV;
2991
2992 spin_lock(&dev_list_lock);
2993 if (!work_pending(&dev->reset_work)) {
2994 dev->reset_workfn = nvme_reset_failed_dev;
2995 queue_work(nvme_workq, &dev->reset_work);
2996 ret = 0;
2997 }
2998 spin_unlock(&dev_list_lock);
2999
3000 if (!ret) {
3001 flush_work(&dev->reset_work);
ffe7704d 3002 flush_work(&dev->probe_work);
4cc06521
KB		 3003 return 0;
3004 }
3005
3006 return ret;
3007}
3008
3009static ssize_t nvme_sysfs_reset(struct device *dev,
3010 struct device_attribute *attr, const char *buf,
3011 size_t count)
3012{
3013 struct nvme_dev *ndev = dev_get_drvdata(dev);
3014 int ret;
3015
3016 ret = nvme_reset(ndev);
3017 if (ret < 0)
3018 return ret;
3019
3020 return count;
3021}
3022static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3023
2e1d8448 3024static void nvme_async_probe(struct work_struct *work);
8d85fce7 3025static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 3026{
a4aea562 3027 int node, result = -ENOMEM;
b60503ba
MW		 3028 struct nvme_dev *dev;
3029
a4aea562
MB		 3030 node = dev_to_node(&pdev->dev);
3031 if (node == NUMA_NO_NODE)
3032 set_dev_node(&pdev->dev, 0);
3033
3034 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3035 if (!dev)
3036 return -ENOMEM;
a4aea562
MB		 3037 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3038 GFP_KERNEL, node);
b60503ba
MW		 3039 if (!dev->entry)
3040 goto free;
a4aea562
MB		 3041 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3042 GFP_KERNEL, node);
b60503ba
MW		 3043 if (!dev->queues)
3044 goto free;
3045
3046 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 3047 dev->reset_workfn = nvme_reset_failed_dev;
3048 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
e75ec752 3049 dev->dev = get_device(&pdev->dev);
9a6b9458 3050 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 3051 result = nvme_set_instance(dev);
3052 if (result)
a96d4f5c 3053 goto put_pci;
b60503ba 3054
091b6092
MW		 3055 result = nvme_setup_prp_pools(dev);
3056 if (result)
0877cb0d 3057 goto release;
091b6092 3058
fb35e914 3059 kref_init(&dev->kref);
b3fffdef
KB		 3060 dev->device = device_create(nvme_class, &pdev->dev,
3061 MKDEV(nvme_char_major, dev->instance),
3062 dev, "nvme%d", dev->instance);
3063 if (IS_ERR(dev->device)) {
3064 result = PTR_ERR(dev->device);
2e1d8448 3065 goto release_pools;
b3fffdef
KB		 3066 }
3067 get_device(dev->device);
4cc06521
KB		 3068 dev_set_drvdata(dev->device, dev);
3069
3070 result = device_create_file(dev->device, &dev_attr_reset_controller);
3071 if (result)
3072 goto put_dev;
740216fc 3073
e6e96d73 3074 INIT_LIST_HEAD(&dev->node);
a5768aa8 3075 INIT_WORK(&dev->scan_work, nvme_dev_scan);
2e1d8448
KB		 3076 INIT_WORK(&dev->probe_work, nvme_async_probe);
3077 schedule_work(&dev->probe_work);
b60503ba
MW		 3078 return 0;
3079
4cc06521
KB		 3080 put_dev:
3081 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3082 put_device(dev->device);
0877cb0d 3083 release_pools:
091b6092 3084 nvme_release_prp_pools(dev);
0877cb0d
KB		 3085 release:
3086 nvme_release_instance(dev);
a96d4f5c 3087 put_pci:
e75ec752 3088 put_device(dev->dev);
b60503ba
MW		 3089 free:
3090 kfree(dev->queues);
3091 kfree(dev->entry);
3092 kfree(dev);
3093 return result;
3094}
3095
2e1d8448
KB		 3096static void nvme_async_probe(struct work_struct *work)
3097{
3098 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
2e1d8448 3099
de3eff2b
KB		 3100 if (nvme_dev_resume(dev) && !work_busy(&dev->reset_work))
3101 nvme_dead_ctrl(dev);
2e1d8448
KB		 3102}
3103
f0d54a54
KB		 3104static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3105{
a6739479 3106 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 3107
a6739479
KB		 3108 if (prepare)
3109 nvme_dev_shutdown(dev);
3110 else
3111 nvme_dev_resume(dev);
f0d54a54
KB		 3112}
3113
09ece142
KB		 3114static void nvme_shutdown(struct pci_dev *pdev)
3115{
3116 struct nvme_dev *dev = pci_get_drvdata(pdev);
3117 nvme_dev_shutdown(dev);
3118}
3119
8d85fce7 3120static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3121{
3122 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 3123
3124 spin_lock(&dev_list_lock);
3125 list_del_init(&dev->node);
3126 spin_unlock(&dev_list_lock);
3127
3128 pci_set_drvdata(pdev, NULL);
2e1d8448 3129 flush_work(&dev->probe_work);
9a6b9458 3130 flush_work(&dev->reset_work);
a5768aa8 3131 flush_work(&dev->scan_work);
4cc06521 3132 device_remove_file(dev->device, &dev_attr_reset_controller);
c9d3bf88 3133 nvme_dev_remove(dev);
3399a3f7 3134 nvme_dev_shutdown(dev);
a4aea562 3135 nvme_dev_remove_admin(dev);
b3fffdef 3136 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
a1a5ef99 3137 nvme_free_queues(dev, 0);
9a6b9458 3138 nvme_release_prp_pools(dev);
5e82e952 3139 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 3140}
3141
3142/* These functions are yet to be implemented */
3143#define nvme_error_detected NULL
3144#define nvme_dump_registers NULL
3145#define nvme_link_reset NULL
3146#define nvme_slot_reset NULL
3147#define nvme_error_resume NULL
cd638946 3148
671a6018 3149#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3150static int nvme_suspend(struct device *dev)
3151{
3152 struct pci_dev *pdev = to_pci_dev(dev);
3153 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3154
3155 nvme_dev_shutdown(ndev);
3156 return 0;
3157}
3158
3159static int nvme_resume(struct device *dev)
3160{
3161 struct pci_dev *pdev = to_pci_dev(dev);
3162 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3163
9a6b9458 3164 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 3165 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 3166 queue_work(nvme_workq, &ndev->reset_work);
3167 }
3168 return 0;
cd638946 3169}
671a6018 3170#endif
cd638946
KB		 3171
3172static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 3173
1d352035 3174static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 3175 .error_detected = nvme_error_detected,
3176 .mmio_enabled = nvme_dump_registers,
3177 .link_reset = nvme_link_reset,
3178 .slot_reset = nvme_slot_reset,
3179 .resume = nvme_error_resume,
f0d54a54 3180 .reset_notify = nvme_reset_notify,
b60503ba
MW		 3181};
3182
3183/* Move to pci_ids.h later */
3184#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3185
6eb0d698 3186static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 3187 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3188 { 0, }
3189};
3190MODULE_DEVICE_TABLE(pci, nvme_id_table);
3191
3192static struct pci_driver nvme_driver = {
3193 .name = "nvme",
3194 .id_table = nvme_id_table,
3195 .probe = nvme_probe,
8d85fce7 3196 .remove = nvme_remove,
09ece142 3197 .shutdown = nvme_shutdown,
cd638946
KB		 3198 .driver = {
3199 .pm = &nvme_dev_pm_ops,
3200 },
b60503ba
MW		 3201 .err_handler = &nvme_err_handler,
3202};
3203
3204static int __init nvme_init(void)
3205{
0ac13140 3206 int result;
1fa6aead 3207
b9afca3e 3208 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3209
9a6b9458
KB		 3210 nvme_workq = create_singlethread_workqueue("nvme");
3211 if (!nvme_workq)
b9afca3e 3212 return -ENOMEM;
9a6b9458 3213
5c42ea16
KB		 3214 result = register_blkdev(nvme_major, "nvme");
3215 if (result < 0)
9a6b9458 3216 goto kill_workq;
5c42ea16 3217 else if (result > 0)
0ac13140 3218 nvme_major = result;
b60503ba 3219
b3fffdef
KB		 3220 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3221 &nvme_dev_fops);
3222 if (result < 0)
3223 goto unregister_blkdev;
3224 else if (result > 0)
3225 nvme_char_major = result;
3226
3227 nvme_class = class_create(THIS_MODULE, "nvme");
c727040b
AK		 3228 if (IS_ERR(nvme_class)) {
3229 result = PTR_ERR(nvme_class);
b3fffdef 3230 goto unregister_chrdev;
c727040b 3231 }
b3fffdef 3232
f3db22fe
KB		 3233 result = pci_register_driver(&nvme_driver);
3234 if (result)
b3fffdef 3235 goto destroy_class;
1fa6aead 3236 return 0;
b60503ba 3237
b3fffdef
KB		 3238 destroy_class:
3239 class_destroy(nvme_class);
3240 unregister_chrdev:
3241 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1fa6aead 3242 unregister_blkdev:
b60503ba 3243 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3244 kill_workq:
3245 destroy_workqueue(nvme_workq);
b60503ba
MW		 3246 return result;
3247}
3248
3249static void __exit nvme_exit(void)
3250{
3251 pci_unregister_driver(&nvme_driver);
3252 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3253 destroy_workqueue(nvme_workq);
b3fffdef
KB		 3254 class_destroy(nvme_class);
3255 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
b9afca3e 3256 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3257 _nvme_check_size();
b60503ba
MW		 3258}
3259
3260MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3261MODULE_LICENSE("GPL");
c78b4713 3262MODULE_VERSION("1.0");
b60503ba
MW		 3263module_init(nvme_init);
3264module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)