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nvme: merge nvme_dev_start, nvme_dev_resume and nvme_async_probe
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba 31#include <linux/kernel.h>
a5768aa8 32#include <linux/list_sort.h>
b60503ba
MW		 33#include <linux/mm.h>
34#include <linux/module.h>
35#include <linux/moduleparam.h>
36#include <linux/pci.h>
be7b6275 37#include <linux/poison.h>
c3bfe717 38#include <linux/ptrace.h>
b60503ba
MW		 39#include <linux/sched.h>
40#include <linux/slab.h>
e1e5e564 41#include <linux/t10-pi.h>
b60503ba 42#include <linux/types.h>
5d0f6131 43#include <scsi/sg.h>
797a796a
HM		 44#include <asm-generic/io-64-nonatomic-lo-hi.h>
45
b3fffdef 46#define NVME_MINORS (1U << MINORBITS)
9d43cf64 47#define NVME_Q_DEPTH 1024
d31af0a3 48#define NVME_AQ_DEPTH 256
b60503ba
MW		 49#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
50#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 51#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 52#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 53
54static unsigned char admin_timeout = 60;
55module_param(admin_timeout, byte, 0644);
56MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 57
bd67608a
MW		 58unsigned char nvme_io_timeout = 30;
59module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 60MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 61
2484f407
DM		 62static unsigned char shutdown_timeout = 5;
63module_param(shutdown_timeout, byte, 0644);
64MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
65
b60503ba
MW		 66static int nvme_major;
67module_param(nvme_major, int, 0);
68
b3fffdef
KB		 69static int nvme_char_major;
70module_param(nvme_char_major, int, 0);
71
58ffacb5
MW		 72static int use_threaded_interrupts;
73module_param(use_threaded_interrupts, int, 0);
74
8ffaadf7
JD		 75static bool use_cmb_sqes = true;
76module_param(use_cmb_sqes, bool, 0644);
77MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
78
1fa6aead
MW		 79static DEFINE_SPINLOCK(dev_list_lock);
80static LIST_HEAD(dev_list);
81static struct task_struct *nvme_thread;
9a6b9458 82static struct workqueue_struct *nvme_workq;
b9afca3e 83static wait_queue_head_t nvme_kthread_wait;
1fa6aead 84
b3fffdef
KB		 85static struct class *nvme_class;
86
90667892 87static int __nvme_reset(struct nvme_dev *dev);
4cc06521 88static int nvme_reset(struct nvme_dev *dev);
a4aea562 89static int nvme_process_cq(struct nvme_queue *nvmeq);
3cf519b5 90static void nvme_dead_ctrl(struct nvme_dev *dev);
d4b4ff8e 91
4d115420
KB		 92struct async_cmd_info {
93 struct kthread_work work;
94 struct kthread_worker *worker;
a4aea562 95 struct request *req;
4d115420
KB		 96 u32 result;
97 int status;
98 void *ctx;
99};
1fa6aead 100
b60503ba
MW		 101/*
102 * An NVM Express queue. Each device has at least two (one for admin
103 * commands and one for I/O commands).
104 */
105struct nvme_queue {
106 struct device *q_dmadev;
091b6092 107 struct nvme_dev *dev;
3193f07b 108 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 109 spinlock_t q_lock;
110 struct nvme_command *sq_cmds;
8ffaadf7 111 struct nvme_command __iomem *sq_cmds_io;
b60503ba 112 volatile struct nvme_completion *cqes;
42483228 113 struct blk_mq_tags **tags;
b60503ba
MW		 114 dma_addr_t sq_dma_addr;
115 dma_addr_t cq_dma_addr;
b60503ba
MW		 116 u32 __iomem *q_db;
117 u16 q_depth;
6222d172 118 s16 cq_vector;
b60503ba
MW		 119 u16 sq_head;
120 u16 sq_tail;
121 u16 cq_head;
c30341dc 122 u16 qid;
e9539f47
MW		 123 u8 cq_phase;
124 u8 cqe_seen;
4d115420 125 struct async_cmd_info cmdinfo;
b60503ba
MW		 126};
127
128/*
129 * Check we didin't inadvertently grow the command struct
130 */
131static inline void _nvme_check_size(void)
132{
133 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
134 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
135 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
136 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
137 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 138 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 139 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 140 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
141 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
142 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
143 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 144 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 145}
146
edd10d33 147typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 148 struct nvme_completion *);
149
e85248e5 150struct nvme_cmd_info {
c2f5b650
MW		 151 nvme_completion_fn fn;
152 void *ctx;
c30341dc 153 int aborted;
a4aea562 154 struct nvme_queue *nvmeq;
ac3dd5bd 155 struct nvme_iod iod[0];
e85248e5
MW		 156};
157
ac3dd5bd
JA		 158/*
159 * Max size of iod being embedded in the request payload
160 */
161#define NVME_INT_PAGES 2
162#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
fda631ff 163#define NVME_INT_MASK 0x01
ac3dd5bd
JA		 164
165/*
166 * Will slightly overestimate the number of pages needed. This is OK
167 * as it only leads to a small amount of wasted memory for the lifetime of
168 * the I/O.
169 */
170static int nvme_npages(unsigned size, struct nvme_dev *dev)
171{
172 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
173 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
174}
175
176static unsigned int nvme_cmd_size(struct nvme_dev *dev)
177{
178 unsigned int ret = sizeof(struct nvme_cmd_info);
179
180 ret += sizeof(struct nvme_iod);
181 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
182 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
183
184 return ret;
185}
186
a4aea562
MB		 187static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
188 unsigned int hctx_idx)
e85248e5 189{
a4aea562
MB		 190 struct nvme_dev *dev = data;
191 struct nvme_queue *nvmeq = dev->queues[0];
192
42483228
KB		 193 WARN_ON(hctx_idx != 0);
194 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
195 WARN_ON(nvmeq->tags);
196
a4aea562 197 hctx->driver_data = nvmeq;
42483228 198 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 199 return 0;
e85248e5
MW		 200}
201
4af0e21c
KB		 202static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
203{
204 struct nvme_queue *nvmeq = hctx->driver_data;
205
206 nvmeq->tags = NULL;
207}
208
a4aea562
MB		 209static int nvme_admin_init_request(void *data, struct request *req,
210 unsigned int hctx_idx, unsigned int rq_idx,
211 unsigned int numa_node)
22404274 212{
a4aea562
MB		 213 struct nvme_dev *dev = data;
214 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
215 struct nvme_queue *nvmeq = dev->queues[0];
216
217 BUG_ON(!nvmeq);
218 cmd->nvmeq = nvmeq;
219 return 0;
22404274
KB		 220}
221
a4aea562
MB		 222static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
223 unsigned int hctx_idx)
b60503ba 224{
a4aea562 225 struct nvme_dev *dev = data;
42483228 226 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
a4aea562 227
42483228
KB		 228 if (!nvmeq->tags)
229 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 230
42483228 231 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 232 hctx->driver_data = nvmeq;
233 return 0;
b60503ba
MW		 234}
235
a4aea562
MB		 236static int nvme_init_request(void *data, struct request *req,
237 unsigned int hctx_idx, unsigned int rq_idx,
238 unsigned int numa_node)
b60503ba 239{
a4aea562
MB		 240 struct nvme_dev *dev = data;
241 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
242 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
243
244 BUG_ON(!nvmeq);
245 cmd->nvmeq = nvmeq;
246 return 0;
247}
248
249static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
250 nvme_completion_fn handler)
251{
252 cmd->fn = handler;
253 cmd->ctx = ctx;
254 cmd->aborted = 0;
c917dfe5 255 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 256}
257
ac3dd5bd
JA		 258static void *iod_get_private(struct nvme_iod *iod)
259{
260 return (void *) (iod->private & ~0x1UL);
261}
262
263/*
264 * If bit 0 is set, the iod is embedded in the request payload.
265 */
266static bool iod_should_kfree(struct nvme_iod *iod)
267{
fda631ff 268 return (iod->private & NVME_INT_MASK) == 0;
ac3dd5bd
JA		 269}
270
c2f5b650
MW		 271/* Special values must be less than 0x1000 */
272#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 273#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
274#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
275#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 276
edd10d33 277static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 278 struct nvme_completion *cqe)
279{
280 if (ctx == CMD_CTX_CANCELLED)
281 return;
c2f5b650 282 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 283 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 284 "completed id %d twice on queue %d\n",
285 cqe->command_id, le16_to_cpup(&cqe->sq_id));
286 return;
287 }
288 if (ctx == CMD_CTX_INVALID) {
edd10d33 289 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 290 "invalid id %d completed on queue %d\n",
291 cqe->command_id, le16_to_cpup(&cqe->sq_id));
292 return;
293 }
edd10d33 294 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 295}
296
a4aea562 297static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 298{
c2f5b650 299 void *ctx;
b60503ba 300
859361a2 301 if (fn)
a4aea562
MB		 302 *fn = cmd->fn;
303 ctx = cmd->ctx;
304 cmd->fn = special_completion;
305 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 306 return ctx;
b60503ba
MW		 307}
308
a4aea562
MB		 309static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
310 struct nvme_completion *cqe)
3c0cf138 311{
a4aea562
MB		 312 u32 result = le32_to_cpup(&cqe->result);
313 u16 status = le16_to_cpup(&cqe->status) >> 1;
314
315 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
316 ++nvmeq->dev->event_limit;
a5768aa8
KB		 317 if (status != NVME_SC_SUCCESS)
318 return;
319
320 switch (result & 0xff07) {
321 case NVME_AER_NOTICE_NS_CHANGED:
322 dev_info(nvmeq->q_dmadev, "rescanning\n");
323 schedule_work(&nvmeq->dev->scan_work);
324 default:
325 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
326 }
b60503ba
MW		 327}
328
a4aea562
MB		 329static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
330 struct nvme_completion *cqe)
5a92e700 331{
a4aea562
MB		 332 struct request *req = ctx;
333
334 u16 status = le16_to_cpup(&cqe->status) >> 1;
335 u32 result = le32_to_cpup(&cqe->result);
a51afb54 336
42483228 337 blk_mq_free_request(req);
a51afb54 338
a4aea562
MB		 339 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
340 ++nvmeq->dev->abort_limit;
5a92e700
KB		 341}
342
a4aea562
MB		 343static void async_completion(struct nvme_queue *nvmeq, void *ctx,
344 struct nvme_completion *cqe)
b60503ba 345{
a4aea562
MB		 346 struct async_cmd_info *cmdinfo = ctx;
347 cmdinfo->result = le32_to_cpup(&cqe->result);
348 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
349 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
42483228 350 blk_mq_free_request(cmdinfo->req);
b60503ba
MW		 351}
352
a4aea562
MB		 353static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
354 unsigned int tag)
b60503ba 355{
42483228 356 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
a51afb54 357
a4aea562 358 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 359}
360
a4aea562
MB		 361/*
362 * Called with local interrupts disabled and the q_lock held. May not sleep.
363 */
364static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
365 nvme_completion_fn *fn)
4f5099af 366{
a4aea562
MB		 367 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
368 void *ctx;
369 if (tag >= nvmeq->q_depth) {
370 *fn = special_completion;
371 return CMD_CTX_INVALID;
372 }
373 if (fn)
374 *fn = cmd->fn;
375 ctx = cmd->ctx;
376 cmd->fn = special_completion;
377 cmd->ctx = CMD_CTX_COMPLETED;
378 return ctx;
b60503ba
MW		 379}
380
381/**
714a7a22 382 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 383 * @nvmeq: The queue to use
384 * @cmd: The command to send
385 *
386 * Safe to use from interrupt context
387 */
e3f879bf
SB		 388static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
389 struct nvme_command *cmd)
b60503ba 390{
a4aea562
MB		 391 u16 tail = nvmeq->sq_tail;
392
8ffaadf7
JD		 393 if (nvmeq->sq_cmds_io)
394 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
395 else
396 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
397
b60503ba
MW		 398 if (++tail == nvmeq->q_depth)
399 tail = 0;
7547881d 400 writel(tail, nvmeq->q_db);
b60503ba 401 nvmeq->sq_tail = tail;
b60503ba
MW		 402}
403
e3f879bf 404static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
a4aea562
MB		 405{
406 unsigned long flags;
a4aea562 407 spin_lock_irqsave(&nvmeq->q_lock, flags);
e3f879bf 408 __nvme_submit_cmd(nvmeq, cmd);
a4aea562 409 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
a4aea562
MB		 410}
411
eca18b23 412static __le64 **iod_list(struct nvme_iod *iod)
e025344c 413{
eca18b23 414 return ((void *)iod) + iod->offset;
e025344c
SMM		 415}
416
ac3dd5bd
JA		 417static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
418 unsigned nseg, unsigned long private)
eca18b23 419{
ac3dd5bd
JA		 420 iod->private = private;
421 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
422 iod->npages = -1;
423 iod->length = nbytes;
424 iod->nents = 0;
eca18b23 425}
b60503ba 426
eca18b23 427static struct nvme_iod *
ac3dd5bd
JA		 428__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
429 unsigned long priv, gfp_t gfp)
b60503ba 430{
eca18b23 431 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 432 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 433 sizeof(struct scatterlist) * nseg, gfp);
434
ac3dd5bd
JA		 435 if (iod)
436 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 437
438 return iod;
b60503ba
MW		 439}
440
ac3dd5bd
JA		 441static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
442 gfp_t gfp)
443{
444 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
445 sizeof(struct nvme_dsm_range);
ac3dd5bd
JA		 446 struct nvme_iod *iod;
447
448 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
449 size <= NVME_INT_BYTES(dev)) {
450 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
451
452 iod = cmd->iod;
ac3dd5bd 453 iod_init(iod, size, rq->nr_phys_segments,
fda631ff 454 (unsigned long) rq | NVME_INT_MASK);
ac3dd5bd
JA		 455 return iod;
456 }
457
458 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
459 (unsigned long) rq, gfp);
460}
461
d29ec824 462static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 463{
1d090624 464 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 465 int i;
466 __le64 **list = iod_list(iod);
467 dma_addr_t prp_dma = iod->first_dma;
468
469 if (iod->npages == 0)
470 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
471 for (i = 0; i < iod->npages; i++) {
472 __le64 *prp_list = list[i];
473 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
474 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
475 prp_dma = next_prp_dma;
476 }
ac3dd5bd
JA		 477
478 if (iod_should_kfree(iod))
479 kfree(iod);
b60503ba
MW		 480}
481
b4ff9c8d
KB		 482static int nvme_error_status(u16 status)
483{
484 switch (status & 0x7ff) {
485 case NVME_SC_SUCCESS:
486 return 0;
487 case NVME_SC_CAP_EXCEEDED:
488 return -ENOSPC;
489 default:
490 return -EIO;
491 }
492}
493
52b68d7e 494#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 495static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
496{
497 if (be32_to_cpu(pi->ref_tag) == v)
498 pi->ref_tag = cpu_to_be32(p);
499}
500
501static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
502{
503 if (be32_to_cpu(pi->ref_tag) == p)
504 pi->ref_tag = cpu_to_be32(v);
505}
506
507/**
508 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
509 *
510 * The virtual start sector is the one that was originally submitted by the
511 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
512 * start sector may be different. Remap protection information to match the
513 * physical LBA on writes, and back to the original seed on reads.
514 *
515 * Type 0 and 3 do not have a ref tag, so no remapping required.
516 */
517static void nvme_dif_remap(struct request *req,
518 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
519{
520 struct nvme_ns *ns = req->rq_disk->private_data;
521 struct bio_integrity_payload *bip;
522 struct t10_pi_tuple *pi;
523 void *p, *pmap;
524 u32 i, nlb, ts, phys, virt;
525
526 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
527 return;
528
529 bip = bio_integrity(req->bio);
530 if (!bip)
531 return;
532
533 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 534
535 p = pmap;
536 virt = bip_get_seed(bip);
537 phys = nvme_block_nr(ns, blk_rq_pos(req));
538 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
539 ts = ns->disk->integrity->tuple_size;
540
541 for (i = 0; i < nlb; i++, virt++, phys++) {
542 pi = (struct t10_pi_tuple *)p;
543 dif_swap(phys, virt, pi);
544 p += ts;
545 }
546 kunmap_atomic(pmap);
547}
548
52b68d7e
KB		 549static int nvme_noop_verify(struct blk_integrity_iter *iter)
550{
551 return 0;
552}
553
554static int nvme_noop_generate(struct blk_integrity_iter *iter)
555{
556 return 0;
557}
558
559struct blk_integrity nvme_meta_noop = {
560 .name = "NVME_META_NOOP",
561 .generate_fn = nvme_noop_generate,
562 .verify_fn = nvme_noop_verify,
563};
564
565static void nvme_init_integrity(struct nvme_ns *ns)
566{
567 struct blk_integrity integrity;
568
569 switch (ns->pi_type) {
570 case NVME_NS_DPS_PI_TYPE3:
571 integrity = t10_pi_type3_crc;
572 break;
573 case NVME_NS_DPS_PI_TYPE1:
574 case NVME_NS_DPS_PI_TYPE2:
575 integrity = t10_pi_type1_crc;
576 break;
577 default:
578 integrity = nvme_meta_noop;
579 break;
580 }
581 integrity.tuple_size = ns->ms;
582 blk_integrity_register(ns->disk, &integrity);
583 blk_queue_max_integrity_segments(ns->queue, 1);
584}
585#else /* CONFIG_BLK_DEV_INTEGRITY */
586static void nvme_dif_remap(struct request *req,
587 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
588{
589}
590static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
591{
592}
593static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
594{
595}
596static void nvme_init_integrity(struct nvme_ns *ns)
597{
598}
599#endif
600
a4aea562 601static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 602 struct nvme_completion *cqe)
603{
eca18b23 604 struct nvme_iod *iod = ctx;
ac3dd5bd 605 struct request *req = iod_get_private(iod);
a4aea562
MB		 606 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
607
b60503ba
MW		 608 u16 status = le16_to_cpup(&cqe->status) >> 1;
609
edd10d33 610 if (unlikely(status)) {
a4aea562
MB		 611 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
612 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 613 unsigned long flags;
614
a4aea562 615 blk_mq_requeue_request(req);
c9d3bf88
KB		 616 spin_lock_irqsave(req->q->queue_lock, flags);
617 if (!blk_queue_stopped(req->q))
618 blk_mq_kick_requeue_list(req->q);
619 spin_unlock_irqrestore(req->q->queue_lock, flags);
edd10d33
KB		 620 return;
621 }
f4829a9b 622
d29ec824 623 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
17188bb4 624 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
f4829a9b 625 status = -EINTR;
d29ec824 626 } else {
f4829a9b 627 status = nvme_error_status(status);
d29ec824 628 }
f4829a9b
CH		 629 }
630
a0a931d6
KB		 631 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
632 u32 result = le32_to_cpup(&cqe->result);
633 req->special = (void *)(uintptr_t)result;
634 }
a4aea562
MB		 635
636 if (cmd_rq->aborted)
e75ec752 637 dev_warn(nvmeq->dev->dev,
a4aea562
MB		 638 "completing aborted command with status:%04x\n",
639 status);
640
e1e5e564 641 if (iod->nents) {
e75ec752 642 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
a4aea562 643 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
e1e5e564
KB		 644 if (blk_integrity_rq(req)) {
645 if (!rq_data_dir(req))
646 nvme_dif_remap(req, nvme_dif_complete);
e75ec752 647 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
e1e5e564
KB		 648 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
649 }
650 }
edd10d33 651 nvme_free_iod(nvmeq->dev, iod);
3291fa57 652
f4829a9b 653 blk_mq_complete_request(req, status);
b60503ba
MW		 654}
655
184d2944 656/* length is in bytes. gfp flags indicates whether we may sleep. */
d29ec824
CH		 657static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
658 int total_len, gfp_t gfp)
ff22b54f 659{
99802a7a 660 struct dma_pool *pool;
eca18b23
MW		 661 int length = total_len;
662 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 663 int dma_len = sg_dma_len(sg);
664 u64 dma_addr = sg_dma_address(sg);
f137e0f1
MI		 665 u32 page_size = dev->page_size;
666 int offset = dma_addr & (page_size - 1);
e025344c 667 __le64 *prp_list;
eca18b23 668 __le64 **list = iod_list(iod);
e025344c 669 dma_addr_t prp_dma;
eca18b23 670 int nprps, i;
ff22b54f 671
1d090624 672 length -= (page_size - offset);
ff22b54f 673 if (length <= 0)
eca18b23 674 return total_len;
ff22b54f 675
1d090624 676 dma_len -= (page_size - offset);
ff22b54f 677 if (dma_len) {
1d090624 678 dma_addr += (page_size - offset);
ff22b54f
MW		 679 } else {
680 sg = sg_next(sg);
681 dma_addr = sg_dma_address(sg);
682 dma_len = sg_dma_len(sg);
683 }
684
1d090624 685 if (length <= page_size) {
edd10d33 686 iod->first_dma = dma_addr;
eca18b23 687 return total_len;
e025344c
SMM		 688 }
689
1d090624 690 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 691 if (nprps <= (256 / 8)) {
692 pool = dev->prp_small_pool;
eca18b23 693 iod->npages = 0;
99802a7a
MW		 694 } else {
695 pool = dev->prp_page_pool;
eca18b23 696 iod->npages = 1;
99802a7a
MW		 697 }
698
b77954cb
MW		 699 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
700 if (!prp_list) {
edd10d33 701 iod->first_dma = dma_addr;
eca18b23 702 iod->npages = -1;
1d090624 703 return (total_len - length) + page_size;
b77954cb 704 }
eca18b23
MW		 705 list[0] = prp_list;
706 iod->first_dma = prp_dma;
e025344c
SMM		 707 i = 0;
708 for (;;) {
1d090624 709 if (i == page_size >> 3) {
e025344c 710 __le64 *old_prp_list = prp_list;
b77954cb 711 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 712 if (!prp_list)
713 return total_len - length;
714 list[iod->npages++] = prp_list;
7523d834
MW		 715 prp_list[0] = old_prp_list[i - 1];
716 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
717 i = 1;
e025344c
SMM		 718 }
719 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 720 dma_len -= page_size;
721 dma_addr += page_size;
722 length -= page_size;
e025344c
SMM		 723 if (length <= 0)
724 break;
725 if (dma_len > 0)
726 continue;
727 BUG_ON(dma_len < 0);
728 sg = sg_next(sg);
729 dma_addr = sg_dma_address(sg);
730 dma_len = sg_dma_len(sg);
ff22b54f
MW		 731 }
732
eca18b23 733 return total_len;
ff22b54f
MW		 734}
735
d29ec824
CH		 736static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
737 struct nvme_iod *iod)
738{
498c4394 739 struct nvme_command cmnd;
d29ec824 740
498c4394
JD		 741 memcpy(&cmnd, req->cmd, sizeof(cmnd));
742 cmnd.rw.command_id = req->tag;
d29ec824 743 if (req->nr_phys_segments) {
498c4394
JD		 744 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
745 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
d29ec824
CH		 746 }
747
498c4394 748 __nvme_submit_cmd(nvmeq, &cmnd);
d29ec824
CH		 749}
750
a4aea562
MB		 751/*
752 * We reuse the small pool to allocate the 16-byte range here as it is not
753 * worth having a special pool for these or additional cases to handle freeing
754 * the iod.
755 */
756static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
757 struct request *req, struct nvme_iod *iod)
0e5e4f0e 758{
edd10d33
KB		 759 struct nvme_dsm_range *range =
760 (struct nvme_dsm_range *)iod_list(iod)[0];
498c4394 761 struct nvme_command cmnd;
0e5e4f0e 762
0e5e4f0e 763 range->cattr = cpu_to_le32(0);
a4aea562
MB		 764 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
765 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e 766
498c4394
JD		 767 memset(&cmnd, 0, sizeof(cmnd));
768 cmnd.dsm.opcode = nvme_cmd_dsm;
769 cmnd.dsm.command_id = req->tag;
770 cmnd.dsm.nsid = cpu_to_le32(ns->ns_id);
771 cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma);
772 cmnd.dsm.nr = 0;
773 cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
0e5e4f0e 774
498c4394 775 __nvme_submit_cmd(nvmeq, &cmnd);
0e5e4f0e
KB		 776}
777
a4aea562 778static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 779 int cmdid)
780{
498c4394 781 struct nvme_command cmnd;
00df5cb4 782
498c4394
JD		 783 memset(&cmnd, 0, sizeof(cmnd));
784 cmnd.common.opcode = nvme_cmd_flush;
785 cmnd.common.command_id = cmdid;
786 cmnd.common.nsid = cpu_to_le32(ns->ns_id);
00df5cb4 787
498c4394 788 __nvme_submit_cmd(nvmeq, &cmnd);
00df5cb4
MW		 789}
790
a4aea562
MB		 791static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
792 struct nvme_ns *ns)
b60503ba 793{
ac3dd5bd 794 struct request *req = iod_get_private(iod);
498c4394 795 struct nvme_command cmnd;
a4aea562
MB		 796 u16 control = 0;
797 u32 dsmgmt = 0;
00df5cb4 798
a4aea562 799 if (req->cmd_flags & REQ_FUA)
b60503ba 800 control |= NVME_RW_FUA;
a4aea562 801 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 802 control |= NVME_RW_LR;
803
a4aea562 804 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 805 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
806
498c4394
JD		 807 memset(&cmnd, 0, sizeof(cmnd));
808 cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
809 cmnd.rw.command_id = req->tag;
810 cmnd.rw.nsid = cpu_to_le32(ns->ns_id);
811 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
812 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
813 cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
814 cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
b60503ba 815
e19b127f 816 if (ns->ms) {
e1e5e564
KB		 817 switch (ns->pi_type) {
818 case NVME_NS_DPS_PI_TYPE3:
819 control |= NVME_RW_PRINFO_PRCHK_GUARD;
820 break;
821 case NVME_NS_DPS_PI_TYPE1:
822 case NVME_NS_DPS_PI_TYPE2:
823 control |= NVME_RW_PRINFO_PRCHK_GUARD |
824 NVME_RW_PRINFO_PRCHK_REF;
498c4394 825 cmnd.rw.reftag = cpu_to_le32(
e1e5e564
KB		 826 nvme_block_nr(ns, blk_rq_pos(req)));
827 break;
828 }
e19b127f
AP		 829 if (blk_integrity_rq(req))
830 cmnd.rw.metadata =
831 cpu_to_le64(sg_dma_address(iod->meta_sg));
832 else
833 control |= NVME_RW_PRINFO_PRACT;
834 }
e1e5e564 835
498c4394
JD		 836 cmnd.rw.control = cpu_to_le16(control);
837 cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 838
498c4394 839 __nvme_submit_cmd(nvmeq, &cmnd);
b60503ba 840
1974b1ae 841 return 0;
edd10d33
KB		 842}
843
d29ec824
CH		 844/*
845 * NOTE: ns is NULL when called on the admin queue.
846 */
a4aea562
MB		 847static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
848 const struct blk_mq_queue_data *bd)
edd10d33 849{
a4aea562
MB		 850 struct nvme_ns *ns = hctx->queue->queuedata;
851 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 852 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 853 struct request *req = bd->rq;
854 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 855 struct nvme_iod *iod;
a4aea562 856 enum dma_data_direction dma_dir;
edd10d33 857
e1e5e564
KB		 858 /*
859 * If formated with metadata, require the block layer provide a buffer
860 * unless this namespace is formated such that the metadata can be
861 * stripped/generated by the controller with PRACT=1.
862 */
d29ec824 863 if (ns && ns->ms && !blk_integrity_rq(req)) {
71feb364
KB		 864 if (!(ns->pi_type && ns->ms == 8) &&
865 req->cmd_type != REQ_TYPE_DRV_PRIV) {
f4829a9b 866 blk_mq_complete_request(req, -EFAULT);
e1e5e564
KB		 867 return BLK_MQ_RQ_QUEUE_OK;
868 }
869 }
870
d29ec824 871 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
edd10d33 872 if (!iod)
fe54303e 873 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 874
a4aea562 875 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 876 void *range;
877 /*
878 * We reuse the small pool to allocate the 16-byte range here
879 * as it is not worth having a special pool for these or
880 * additional cases to handle freeing the iod.
881 */
d29ec824 882 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
edd10d33 883 &iod->first_dma);
a4aea562 884 if (!range)
fe54303e 885 goto retry_cmd;
edd10d33
KB		 886 iod_list(iod)[0] = (__le64 *)range;
887 iod->npages = 0;
ac3dd5bd 888 } else if (req->nr_phys_segments) {
a4aea562
MB		 889 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
890
ac3dd5bd 891 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 892 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 893 if (!iod->nents)
894 goto error_cmd;
a4aea562
MB		 895
896 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 897 goto retry_cmd;
a4aea562 898
fe54303e 899 if (blk_rq_bytes(req) !=
d29ec824
CH		 900 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
901 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
fe54303e
JA		 902 goto retry_cmd;
903 }
e1e5e564
KB		 904 if (blk_integrity_rq(req)) {
905 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
906 goto error_cmd;
907
908 sg_init_table(iod->meta_sg, 1);
909 if (blk_rq_map_integrity_sg(
910 req->q, req->bio, iod->meta_sg) != 1)
911 goto error_cmd;
912
913 if (rq_data_dir(req))
914 nvme_dif_remap(req, nvme_dif_prep);
915
916 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
917 goto error_cmd;
918 }
edd10d33 919 }
1974b1ae 920
9af8785a 921 nvme_set_info(cmd, iod, req_completion);
a4aea562 922 spin_lock_irq(&nvmeq->q_lock);
d29ec824
CH		 923 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
924 nvme_submit_priv(nvmeq, req, iod);
925 else if (req->cmd_flags & REQ_DISCARD)
a4aea562
MB		 926 nvme_submit_discard(nvmeq, ns, req, iod);
927 else if (req->cmd_flags & REQ_FLUSH)
928 nvme_submit_flush(nvmeq, ns, req->tag);
929 else
930 nvme_submit_iod(nvmeq, iod, ns);
931
932 nvme_process_cq(nvmeq);
933 spin_unlock_irq(&nvmeq->q_lock);
934 return BLK_MQ_RQ_QUEUE_OK;
935
fe54303e 936 error_cmd:
d29ec824 937 nvme_free_iod(dev, iod);
fe54303e
JA		 938 return BLK_MQ_RQ_QUEUE_ERROR;
939 retry_cmd:
d29ec824 940 nvme_free_iod(dev, iod);
fe54303e 941 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 942}
943
e9539f47 944static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 945{
82123460 946 u16 head, phase;
b60503ba 947
b60503ba 948 head = nvmeq->cq_head;
82123460 949 phase = nvmeq->cq_phase;
b60503ba
MW		 950
951 for (;;) {
c2f5b650
MW		 952 void *ctx;
953 nvme_completion_fn fn;
b60503ba 954 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 955 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 956 break;
957 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
958 if (++head == nvmeq->q_depth) {
959 head = 0;
82123460 960 phase = !phase;
b60503ba 961 }
a4aea562 962 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 963 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 964 }
965
966 /* If the controller ignores the cq head doorbell and continuously
967 * writes to the queue, it is theoretically possible to wrap around
968 * the queue twice and mistakenly return IRQ_NONE. Linux only
969 * requires that 0.1% of your interrupts are handled, so this isn't
970 * a big problem.
971 */
82123460 972 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 973 return 0;
b60503ba 974
b80d5ccc 975 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 976 nvmeq->cq_head = head;
82123460 977 nvmeq->cq_phase = phase;
b60503ba 978
e9539f47
MW		 979 nvmeq->cqe_seen = 1;
980 return 1;
b60503ba
MW		 981}
982
983static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 984{
985 irqreturn_t result;
986 struct nvme_queue *nvmeq = data;
987 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 988 nvme_process_cq(nvmeq);
989 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
990 nvmeq->cqe_seen = 0;
58ffacb5
MW		 991 spin_unlock(&nvmeq->q_lock);
992 return result;
993}
994
995static irqreturn_t nvme_irq_check(int irq, void *data)
996{
997 struct nvme_queue *nvmeq = data;
998 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
999 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
1000 return IRQ_NONE;
1001 return IRQ_WAKE_THREAD;
1002}
1003
b60503ba
MW		 1004/*
1005 * Returns 0 on success. If the result is negative, it's a Linux error code;
1006 * if the result is positive, it's an NVM Express status code
1007 */
d29ec824
CH		 1008int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1009 void *buffer, void __user *ubuffer, unsigned bufflen,
1010 u32 *result, unsigned timeout)
b60503ba 1011{
d29ec824
CH		 1012 bool write = cmd->common.opcode & 1;
1013 struct bio *bio = NULL;
f705f837 1014 struct request *req;
d29ec824 1015 int ret;
b60503ba 1016
d29ec824 1017 req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
f705f837
CH		 1018 if (IS_ERR(req))
1019 return PTR_ERR(req);
b60503ba 1020
d29ec824 1021 req->cmd_type = REQ_TYPE_DRV_PRIV;
e112af0d 1022 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d29ec824
CH		 1023 req->__data_len = 0;
1024 req->__sector = (sector_t) -1;
1025 req->bio = req->biotail = NULL;
b60503ba 1026
f4ff414a 1027 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
a4aea562 1028
d29ec824
CH		 1029 req->cmd = (unsigned char *)cmd;
1030 req->cmd_len = sizeof(struct nvme_command);
a0a931d6 1031 req->special = (void *)0;
b60503ba 1032
d29ec824
CH		 1033 if (buffer && bufflen) {
1034 ret = blk_rq_map_kern(q, req, buffer, bufflen, __GFP_WAIT);
1035 if (ret)
1036 goto out;
1037 } else if (ubuffer && bufflen) {
1038 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen, __GFP_WAIT);
1039 if (ret)
1040 goto out;
1041 bio = req->bio;
1042 }
3c0cf138 1043
d29ec824
CH		 1044 blk_execute_rq(req->q, NULL, req, 0);
1045 if (bio)
1046 blk_rq_unmap_user(bio);
b60503ba 1047 if (result)
a0a931d6 1048 *result = (u32)(uintptr_t)req->special;
d29ec824
CH		 1049 ret = req->errors;
1050 out:
f705f837 1051 blk_mq_free_request(req);
d29ec824 1052 return ret;
f705f837
CH		 1053}
1054
d29ec824
CH		 1055int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1056 void *buffer, unsigned bufflen)
f705f837 1057{
d29ec824 1058 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
b60503ba
MW		 1059}
1060
a4aea562
MB		 1061static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1062{
1063 struct nvme_queue *nvmeq = dev->queues[0];
1064 struct nvme_command c;
1065 struct nvme_cmd_info *cmd_info;
1066 struct request *req;
1067
1efccc9d 1068 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
9f173b33
DC		 1069 if (IS_ERR(req))
1070 return PTR_ERR(req);
a4aea562 1071
c917dfe5 1072 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562 1073 cmd_info = blk_mq_rq_to_pdu(req);
1efccc9d 1074 nvme_set_info(cmd_info, NULL, async_req_completion);
a4aea562
MB		 1075
1076 memset(&c, 0, sizeof(c));
1077 c.common.opcode = nvme_admin_async_event;
1078 c.common.command_id = req->tag;
1079
42483228 1080 blk_mq_free_request(req);
e3f879bf
SB		 1081 __nvme_submit_cmd(nvmeq, &c);
1082 return 0;
a4aea562
MB		 1083}
1084
1085static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 1086 struct nvme_command *cmd,
1087 struct async_cmd_info *cmdinfo, unsigned timeout)
1088{
a4aea562
MB		 1089 struct nvme_queue *nvmeq = dev->queues[0];
1090 struct request *req;
1091 struct nvme_cmd_info *cmd_rq;
4d115420 1092
a4aea562 1093 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 1094 if (IS_ERR(req))
1095 return PTR_ERR(req);
a4aea562
MB		 1096
1097 req->timeout = timeout;
1098 cmd_rq = blk_mq_rq_to_pdu(req);
1099 cmdinfo->req = req;
1100 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 1101 cmdinfo->status = -EINTR;
a4aea562
MB		 1102
1103 cmd->common.command_id = req->tag;
1104
e3f879bf
SB		 1105 nvme_submit_cmd(nvmeq, cmd);
1106 return 0;
4d115420
KB		 1107}
1108
b60503ba
MW		 1109static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1110{
b60503ba
MW		 1111 struct nvme_command c;
1112
1113 memset(&c, 0, sizeof(c));
1114 c.delete_queue.opcode = opcode;
1115 c.delete_queue.qid = cpu_to_le16(id);
1116
d29ec824 1117 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1118}
1119
1120static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1121 struct nvme_queue *nvmeq)
1122{
b60503ba
MW		 1123 struct nvme_command c;
1124 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1125
d29ec824
CH		 1126 /*
1127 * Note: we (ab)use the fact the the prp fields survive if no data
1128 * is attached to the request.
1129 */
b60503ba
MW		 1130 memset(&c, 0, sizeof(c));
1131 c.create_cq.opcode = nvme_admin_create_cq;
1132 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1133 c.create_cq.cqid = cpu_to_le16(qid);
1134 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1135 c.create_cq.cq_flags = cpu_to_le16(flags);
1136 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1137
d29ec824 1138 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1139}
1140
1141static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1142 struct nvme_queue *nvmeq)
1143{
b60503ba
MW		 1144 struct nvme_command c;
1145 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1146
d29ec824
CH		 1147 /*
1148 * Note: we (ab)use the fact the the prp fields survive if no data
1149 * is attached to the request.
1150 */
b60503ba
MW		 1151 memset(&c, 0, sizeof(c));
1152 c.create_sq.opcode = nvme_admin_create_sq;
1153 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1154 c.create_sq.sqid = cpu_to_le16(qid);
1155 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1156 c.create_sq.sq_flags = cpu_to_le16(flags);
1157 c.create_sq.cqid = cpu_to_le16(qid);
1158
d29ec824 1159 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1160}
1161
1162static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1163{
1164 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1165}
1166
1167static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1168{
1169 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1170}
1171
d29ec824 1172int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
bc5fc7e4 1173{
e44ac588 1174 struct nvme_command c = { };
d29ec824 1175 int error;
bc5fc7e4 1176
e44ac588
AM		 1177 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1178 c.identify.opcode = nvme_admin_identify;
1179 c.identify.cns = cpu_to_le32(1);
1180
d29ec824
CH		 1181 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1182 if (!*id)
1183 return -ENOMEM;
bc5fc7e4 1184
d29ec824
CH		 1185 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1186 sizeof(struct nvme_id_ctrl));
1187 if (error)
1188 kfree(*id);
1189 return error;
1190}
1191
1192int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1193 struct nvme_id_ns **id)
1194{
e44ac588 1195 struct nvme_command c = { };
d29ec824 1196 int error;
bc5fc7e4 1197
e44ac588
AM		 1198 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1199 c.identify.opcode = nvme_admin_identify,
1200 c.identify.nsid = cpu_to_le32(nsid),
1201
d29ec824
CH		 1202 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1203 if (!*id)
1204 return -ENOMEM;
1205
1206 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1207 sizeof(struct nvme_id_ns));
1208 if (error)
1209 kfree(*id);
1210 return error;
bc5fc7e4
MW		 1211}
1212
5d0f6131 1213int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1214 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1215{
1216 struct nvme_command c;
1217
1218 memset(&c, 0, sizeof(c));
1219 c.features.opcode = nvme_admin_get_features;
a42cecce 1220 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1221 c.features.prp1 = cpu_to_le64(dma_addr);
1222 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1223
d29ec824
CH		 1224 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1225 result, 0);
df348139
MW		 1226}
1227
5d0f6131
VV		 1228int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1229 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1230{
1231 struct nvme_command c;
1232
1233 memset(&c, 0, sizeof(c));
1234 c.features.opcode = nvme_admin_set_features;
1235 c.features.prp1 = cpu_to_le64(dma_addr);
1236 c.features.fid = cpu_to_le32(fid);
1237 c.features.dword11 = cpu_to_le32(dword11);
1238
d29ec824
CH		 1239 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1240 result, 0);
1241}
1242
1243int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1244{
e44ac588
AM		 1245 struct nvme_command c = { };
1246 int error;
1247
1248 c.common.opcode = nvme_admin_get_log_page,
1249 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
1250 c.common.cdw10[0] = cpu_to_le32(
d29ec824
CH		 1251 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1252 NVME_LOG_SMART),
d29ec824
CH		 1253
1254 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1255 if (!*log)
1256 return -ENOMEM;
1257
1258 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1259 sizeof(struct nvme_smart_log));
1260 if (error)
1261 kfree(*log);
1262 return error;
bc5fc7e4
MW		 1263}
1264
c30341dc 1265/**
a4aea562 1266 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1267 *
1268 * Schedule controller reset if the command was already aborted once before and
1269 * still hasn't been returned to the driver, or if this is the admin queue.
1270 */
a4aea562 1271static void nvme_abort_req(struct request *req)
c30341dc 1272{
a4aea562
MB		 1273 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1274 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1275 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1276 struct request *abort_req;
1277 struct nvme_cmd_info *abort_cmd;
1278 struct nvme_command cmd;
c30341dc 1279
a4aea562 1280 if (!nvmeq->qid || cmd_rq->aborted) {
90667892
CH		 1281 spin_lock(&dev_list_lock);
1282 if (!__nvme_reset(dev)) {
1283 dev_warn(dev->dev,
1284 "I/O %d QID %d timeout, reset controller\n",
1285 req->tag, nvmeq->qid);
1286 }
1287 spin_unlock(&dev_list_lock);
c30341dc
KB		 1288 return;
1289 }
1290
1291 if (!dev->abort_limit)
1292 return;
1293
a4aea562
MB		 1294 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1295 false);
9f173b33 1296 if (IS_ERR(abort_req))
c30341dc
KB		 1297 return;
1298
a4aea562
MB		 1299 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1300 nvme_set_info(abort_cmd, abort_req, abort_completion);
1301
c30341dc
KB		 1302 memset(&cmd, 0, sizeof(cmd));
1303 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1304 cmd.abort.cid = req->tag;
c30341dc 1305 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1306 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1307
1308 --dev->abort_limit;
a4aea562 1309 cmd_rq->aborted = 1;
c30341dc 1310
a4aea562 1311 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1312 nvmeq->qid);
e3f879bf 1313 nvme_submit_cmd(dev->queues[0], &cmd);
c30341dc
KB		 1314}
1315
42483228 1316static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
a09115b2 1317{
a4aea562
MB		 1318 struct nvme_queue *nvmeq = data;
1319 void *ctx;
1320 nvme_completion_fn fn;
1321 struct nvme_cmd_info *cmd;
cef6a948
KB		 1322 struct nvme_completion cqe;
1323
1324 if (!blk_mq_request_started(req))
1325 return;
a09115b2 1326
a4aea562 1327 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1328
a4aea562
MB		 1329 if (cmd->ctx == CMD_CTX_CANCELLED)
1330 return;
1331
cef6a948
KB		 1332 if (blk_queue_dying(req->q))
1333 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1334 else
1335 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1336
1337
a4aea562
MB		 1338 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1339 req->tag, nvmeq->qid);
1340 ctx = cancel_cmd_info(cmd, &fn);
1341 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1342}
1343
a4aea562 1344static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1345{
a4aea562
MB		 1346 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1347 struct nvme_queue *nvmeq = cmd->nvmeq;
1348
1349 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1350 nvmeq->qid);
7a509a6b 1351 spin_lock_irq(&nvmeq->q_lock);
07836e65 1352 nvme_abort_req(req);
7a509a6b 1353 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1354
07836e65
KB		 1355 /*
1356 * The aborted req will be completed on receiving the abort req.
1357 * We enable the timer again. If hit twice, it'll cause a device reset,
1358 * as the device then is in a faulty state.
1359 */
1360 return BLK_EH_RESET_TIMER;
a4aea562 1361}
22404274 1362
a4aea562
MB		 1363static void nvme_free_queue(struct nvme_queue *nvmeq)
1364{
9e866774
MW		 1365 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1366 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD		 1367 if (nvmeq->sq_cmds)
1368 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774
MW		 1369 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1370 kfree(nvmeq);
1371}
1372
a1a5ef99 1373static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1374{
1375 int i;
1376
a1a5ef99 1377 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1378 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1379 dev->queue_count--;
a4aea562 1380 dev->queues[i] = NULL;
f435c282 1381 nvme_free_queue(nvmeq);
121c7ad4 1382 }
22404274
KB		 1383}
1384
4d115420
KB		 1385/**
1386 * nvme_suspend_queue - put queue into suspended state
1387 * @nvmeq - queue to suspend
4d115420
KB		 1388 */
1389static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1390{
2b25d981 1391 int vector;
b60503ba 1392
a09115b2 1393 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1394 if (nvmeq->cq_vector == -1) {
1395 spin_unlock_irq(&nvmeq->q_lock);
1396 return 1;
1397 }
1398 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1399 nvmeq->dev->online_queues--;
2b25d981 1400 nvmeq->cq_vector = -1;
a09115b2
MW		 1401 spin_unlock_irq(&nvmeq->q_lock);
1402
6df3dbc8
KB		 1403 if (!nvmeq->qid && nvmeq->dev->admin_q)
1404 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1405
aba2080f
MW		 1406 irq_set_affinity_hint(vector, NULL);
1407 free_irq(vector, nvmeq);
b60503ba 1408
4d115420
KB		 1409 return 0;
1410}
b60503ba 1411
4d115420
KB		 1412static void nvme_clear_queue(struct nvme_queue *nvmeq)
1413{
22404274 1414 spin_lock_irq(&nvmeq->q_lock);
42483228
KB		 1415 if (nvmeq->tags && *nvmeq->tags)
1416 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
22404274 1417 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1418}
1419
4d115420
KB		 1420static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1421{
a4aea562 1422 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1423
1424 if (!nvmeq)
1425 return;
1426 if (nvme_suspend_queue(nvmeq))
1427 return;
1428
0e53d180
KB		 1429 /* Don't tell the adapter to delete the admin queue.
1430 * Don't tell a removed adapter to delete IO queues. */
1431 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1432 adapter_delete_sq(dev, qid);
1433 adapter_delete_cq(dev, qid);
1434 }
07836e65
KB		 1435
1436 spin_lock_irq(&nvmeq->q_lock);
1437 nvme_process_cq(nvmeq);
1438 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1439}
1440
8ffaadf7
JD		 1441static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1442 int entry_size)
1443{
1444 int q_depth = dev->q_depth;
1445 unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size);
1446
1447 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99
JD		 1448 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1449 mem_per_q = round_down(mem_per_q, dev->page_size);
1450 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1451
1452 /*
1453 * Ensure the reduced q_depth is above some threshold where it
1454 * would be better to map queues in system memory with the
1455 * original depth
1456 */
1457 if (q_depth < 64)
1458 return -ENOMEM;
1459 }
1460
1461 return q_depth;
1462}
1463
1464static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1465 int qid, int depth)
1466{
1467 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1468 unsigned offset = (qid - 1) *
1469 roundup(SQ_SIZE(depth), dev->page_size);
1470 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1471 nvmeq->sq_cmds_io = dev->cmb + offset;
1472 } else {
1473 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1474 &nvmeq->sq_dma_addr, GFP_KERNEL);
1475 if (!nvmeq->sq_cmds)
1476 return -ENOMEM;
1477 }
1478
1479 return 0;
1480}
1481
b60503ba 1482static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1483 int depth)
b60503ba 1484{
a4aea562 1485 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1486 if (!nvmeq)
1487 return NULL;
1488
e75ec752 1489 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1490 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1491 if (!nvmeq->cqes)
1492 goto free_nvmeq;
b60503ba 1493
8ffaadf7 1494 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1495 goto free_cqdma;
1496
e75ec752 1497 nvmeq->q_dmadev = dev->dev;
091b6092 1498 nvmeq->dev = dev;
3193f07b
MW		 1499 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1500 dev->instance, qid);
b60503ba
MW		 1501 spin_lock_init(&nvmeq->q_lock);
1502 nvmeq->cq_head = 0;
82123460 1503 nvmeq->cq_phase = 1;
b80d5ccc 1504 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1505 nvmeq->q_depth = depth;
c30341dc 1506 nvmeq->qid = qid;
758dd7fd 1507 nvmeq->cq_vector = -1;
a4aea562 1508 dev->queues[qid] = nvmeq;
b60503ba 1509
36a7e993
JD		 1510 /* make sure queue descriptor is set before queue count, for kthread */
1511 mb();
1512 dev->queue_count++;
1513
b60503ba
MW		 1514 return nvmeq;
1515
1516 free_cqdma:
e75ec752 1517 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1518 nvmeq->cq_dma_addr);
1519 free_nvmeq:
1520 kfree(nvmeq);
1521 return NULL;
1522}
1523
3001082c
MW		 1524static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1525 const char *name)
1526{
58ffacb5
MW		 1527 if (use_threaded_interrupts)
1528 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1529 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1530 name, nvmeq);
3001082c 1531 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1532 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1533}
1534
22404274 1535static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1536{
22404274 1537 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1538
7be50e93 1539 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1540 nvmeq->sq_tail = 0;
1541 nvmeq->cq_head = 0;
1542 nvmeq->cq_phase = 1;
b80d5ccc 1543 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1544 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1545 dev->online_queues++;
7be50e93 1546 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1547}
1548
1549static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1550{
1551 struct nvme_dev *dev = nvmeq->dev;
1552 int result;
3f85d50b 1553
2b25d981 1554 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1555 result = adapter_alloc_cq(dev, qid, nvmeq);
1556 if (result < 0)
22404274 1557 return result;
b60503ba
MW		 1558
1559 result = adapter_alloc_sq(dev, qid, nvmeq);
1560 if (result < 0)
1561 goto release_cq;
1562
3193f07b 1563 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1564 if (result < 0)
1565 goto release_sq;
1566
22404274 1567 nvme_init_queue(nvmeq, qid);
22404274 1568 return result;
b60503ba
MW		 1569
1570 release_sq:
1571 adapter_delete_sq(dev, qid);
1572 release_cq:
1573 adapter_delete_cq(dev, qid);
22404274 1574 return result;
b60503ba
MW		 1575}
1576
ba47e386
MW		 1577static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1578{
1579 unsigned long timeout;
1580 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1581
1582 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1583
1584 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1585 msleep(100);
1586 if (fatal_signal_pending(current))
1587 return -EINTR;
1588 if (time_after(jiffies, timeout)) {
e75ec752 1589 dev_err(dev->dev,
27e8166c
MW		 1590 "Device not ready; aborting %s\n", enabled ?
1591 "initialisation" : "reset");
ba47e386
MW		 1592 return -ENODEV;
1593 }
1594 }
1595
1596 return 0;
1597}
1598
1599/*
1600 * If the device has been passed off to us in an enabled state, just clear
1601 * the enabled bit. The spec says we should set the 'shutdown notification
1602 * bits', but doing so may cause the device to complete commands to the
1603 * admin queue ... and we don't know what memory that might be pointing at!
1604 */
1605static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1606{
01079522
DM		 1607 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1608 dev->ctrl_config &= ~NVME_CC_ENABLE;
1609 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1610
ba47e386
MW		 1611 return nvme_wait_ready(dev, cap, false);
1612}
1613
1614static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1615{
01079522
DM		 1616 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1617 dev->ctrl_config |= NVME_CC_ENABLE;
1618 writel(dev->ctrl_config, &dev->bar->cc);
1619
ba47e386
MW		 1620 return nvme_wait_ready(dev, cap, true);
1621}
1622
1894d8f1
KB		 1623static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1624{
1625 unsigned long timeout;
1894d8f1 1626
01079522
DM		 1627 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1628 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1629
1630 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1631
2484f407 1632 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1633 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1634 NVME_CSTS_SHST_CMPLT) {
1635 msleep(100);
1636 if (fatal_signal_pending(current))
1637 return -EINTR;
1638 if (time_after(jiffies, timeout)) {
e75ec752 1639 dev_err(dev->dev,
1894d8f1
KB		 1640 "Device shutdown incomplete; abort shutdown\n");
1641 return -ENODEV;
1642 }
1643 }
1644
1645 return 0;
1646}
1647
a4aea562 1648static struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1649 .queue_rq = nvme_queue_rq,
a4aea562
MB		 1650 .map_queue = blk_mq_map_queue,
1651 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1652 .exit_hctx = nvme_admin_exit_hctx,
a4aea562
MB		 1653 .init_request = nvme_admin_init_request,
1654 .timeout = nvme_timeout,
1655};
1656
1657static struct blk_mq_ops nvme_mq_ops = {
1658 .queue_rq = nvme_queue_rq,
1659 .map_queue = blk_mq_map_queue,
1660 .init_hctx = nvme_init_hctx,
1661 .init_request = nvme_init_request,
1662 .timeout = nvme_timeout,
1663};
1664
ea191d2f
KB		 1665static void nvme_dev_remove_admin(struct nvme_dev *dev)
1666{
1667 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1668 blk_cleanup_queue(dev->admin_q);
1669 blk_mq_free_tag_set(&dev->admin_tagset);
1670 }
1671}
1672
a4aea562
MB		 1673static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1674{
1675 if (!dev->admin_q) {
1676 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1677 dev->admin_tagset.nr_hw_queues = 1;
1678 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1efccc9d 1679 dev->admin_tagset.reserved_tags = 1;
a4aea562 1680 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1681 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
ac3dd5bd 1682 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1683 dev->admin_tagset.driver_data = dev;
1684
1685 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1686 return -ENOMEM;
1687
1688 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1689 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1690 blk_mq_free_tag_set(&dev->admin_tagset);
1691 return -ENOMEM;
1692 }
ea191d2f
KB		 1693 if (!blk_get_queue(dev->admin_q)) {
1694 nvme_dev_remove_admin(dev);
4af0e21c 1695 dev->admin_q = NULL;
ea191d2f
KB		 1696 return -ENODEV;
1697 }
0fb59cbc
KB		 1698 } else
1699 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1700
1701 return 0;
1702}
1703
8d85fce7 1704static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1705{
ba47e386 1706 int result;
b60503ba 1707 u32 aqa;
ba47e386 1708 u64 cap = readq(&dev->bar->cap);
b60503ba 1709 struct nvme_queue *nvmeq;
1d090624
KB		 1710 unsigned page_shift = PAGE_SHIFT;
1711 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1712 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1713
1714 if (page_shift < dev_page_min) {
e75ec752 1715 dev_err(dev->dev,
1d090624
KB		 1716 "Minimum device page size (%u) too large for "
1717 "host (%u)\n", 1 << dev_page_min,
1718 1 << page_shift);
1719 return -ENODEV;
1720 }
1721 if (page_shift > dev_page_max) {
e75ec752 1722 dev_info(dev->dev,
1d090624
KB		 1723 "Device maximum page size (%u) smaller than "
1724 "host (%u); enabling work-around\n",
1725 1 << dev_page_max, 1 << page_shift);
1726 page_shift = dev_page_max;
1727 }
b60503ba 1728
dfbac8c7
KB		 1729 dev->subsystem = readl(&dev->bar->vs) >= NVME_VS(1, 1) ?
1730 NVME_CAP_NSSRC(cap) : 0;
1731
1732 if (dev->subsystem && (readl(&dev->bar->csts) & NVME_CSTS_NSSRO))
1733 writel(NVME_CSTS_NSSRO, &dev->bar->csts);
1734
ba47e386
MW		 1735 result = nvme_disable_ctrl(dev, cap);
1736 if (result < 0)
1737 return result;
b60503ba 1738
a4aea562 1739 nvmeq = dev->queues[0];
cd638946 1740 if (!nvmeq) {
2b25d981 1741 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1742 if (!nvmeq)
1743 return -ENOMEM;
cd638946 1744 }
b60503ba
MW		 1745
1746 aqa = nvmeq->q_depth - 1;
1747 aqa |= aqa << 16;
1748
1d090624
KB		 1749 dev->page_size = 1 << page_shift;
1750
01079522 1751 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1752 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1753 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1754 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1755
1756 writel(aqa, &dev->bar->aqa);
1757 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1758 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1759
ba47e386 1760 result = nvme_enable_ctrl(dev, cap);
025c557a 1761 if (result)
a4aea562
MB		 1762 goto free_nvmeq;
1763
2b25d981 1764 nvmeq->cq_vector = 0;
3193f07b 1765 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
758dd7fd
JD		 1766 if (result) {
1767 nvmeq->cq_vector = -1;
0fb59cbc 1768 goto free_nvmeq;
758dd7fd 1769 }
025c557a 1770
b60503ba 1771 return result;
a4aea562 1772
a4aea562
MB		 1773 free_nvmeq:
1774 nvme_free_queues(dev, 0);
1775 return result;
b60503ba
MW		 1776}
1777
a53295b6
MW		 1778static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1779{
1780 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1781 struct nvme_user_io io;
1782 struct nvme_command c;
d29ec824 1783 unsigned length, meta_len;
a67a9513 1784 int status, write;
a67a9513
KB		 1785 dma_addr_t meta_dma = 0;
1786 void *meta = NULL;
fec558b5 1787 void __user *metadata;
a53295b6
MW		 1788
1789 if (copy_from_user(&io, uio, sizeof(io)))
1790 return -EFAULT;
6c7d4945
MW		 1791
1792 switch (io.opcode) {
1793 case nvme_cmd_write:
1794 case nvme_cmd_read:
6bbf1acd 1795 case nvme_cmd_compare:
6413214c 1796 break;
6c7d4945 1797 default:
6bbf1acd 1798 return -EINVAL;
6c7d4945
MW		 1799 }
1800
d29ec824
CH		 1801 length = (io.nblocks + 1) << ns->lba_shift;
1802 meta_len = (io.nblocks + 1) * ns->ms;
6a398a3e 1803 metadata = (void __user *)(unsigned long)io.metadata;
d29ec824 1804 write = io.opcode & 1;
a53295b6 1805
71feb364
KB		 1806 if (ns->ext) {
1807 length += meta_len;
1808 meta_len = 0;
a67a9513
KB		 1809 }
1810 if (meta_len) {
d29ec824
CH		 1811 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1812 return -EINVAL;
1813
e75ec752 1814 meta = dma_alloc_coherent(dev->dev, meta_len,
a67a9513 1815 &meta_dma, GFP_KERNEL);
fec558b5 1816
a67a9513
KB		 1817 if (!meta) {
1818 status = -ENOMEM;
1819 goto unmap;
1820 }
1821 if (write) {
fec558b5 1822 if (copy_from_user(meta, metadata, meta_len)) {
a67a9513
KB		 1823 status = -EFAULT;
1824 goto unmap;
1825 }
1826 }
1827 }
1828
a53295b6
MW		 1829 memset(&c, 0, sizeof(c));
1830 c.rw.opcode = io.opcode;
1831 c.rw.flags = io.flags;
6c7d4945 1832 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1833 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1834 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1835 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1836 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1837 c.rw.reftag = cpu_to_le32(io.reftag);
1838 c.rw.apptag = cpu_to_le16(io.apptag);
1839 c.rw.appmask = cpu_to_le16(io.appmask);
a67a9513 1840 c.rw.metadata = cpu_to_le64(meta_dma);
d29ec824
CH		 1841
1842 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
1843 (void __user *)io.addr, length, NULL, 0);
f410c680 1844 unmap:
a67a9513
KB		 1845 if (meta) {
1846 if (status == NVME_SC_SUCCESS && !write) {
fec558b5 1847 if (copy_to_user(metadata, meta, meta_len))
a67a9513
KB		 1848 status = -EFAULT;
1849 }
e75ec752 1850 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
f410c680 1851 }
a53295b6
MW		 1852 return status;
1853}
1854
a4aea562
MB		 1855static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1856 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1857{
7963e521 1858 struct nvme_passthru_cmd cmd;
6ee44cdc 1859 struct nvme_command c;
d29ec824
CH		 1860 unsigned timeout = 0;
1861 int status;
6ee44cdc 1862
6bbf1acd
MW		 1863 if (!capable(CAP_SYS_ADMIN))
1864 return -EACCES;
1865 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1866 return -EFAULT;
6ee44cdc
MW		 1867
1868 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1869 c.common.opcode = cmd.opcode;
1870 c.common.flags = cmd.flags;
1871 c.common.nsid = cpu_to_le32(cmd.nsid);
1872 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1873 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1874 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1875 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1876 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1877 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1878 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1879 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1880
d29ec824
CH		 1881 if (cmd.timeout_ms)
1882 timeout = msecs_to_jiffies(cmd.timeout_ms);
eca18b23 1883
f705f837 1884 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
d29ec824
CH		 1885 NULL, (void __user *)cmd.addr, cmd.data_len,
1886 &cmd.result, timeout);
1887 if (status >= 0) {
1888 if (put_user(cmd.result, &ucmd->result))
1889 return -EFAULT;
6bbf1acd 1890 }
f4f117f6 1891
6ee44cdc
MW		 1892 return status;
1893}
1894
81f03fed
JD		 1895static int nvme_subsys_reset(struct nvme_dev *dev)
1896{
1897 if (!dev->subsystem)
1898 return -ENOTTY;
1899
1900 writel(0x4E564D65, &dev->bar->nssr); /* "NVMe" */
1901 return 0;
1902}
1903
b60503ba
MW		 1904static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1905 unsigned long arg)
1906{
1907 struct nvme_ns *ns = bdev->bd_disk->private_data;
1908
1909 switch (cmd) {
6bbf1acd 1910 case NVME_IOCTL_ID:
c3bfe717 1911 force_successful_syscall_return();
6bbf1acd
MW		 1912 return ns->ns_id;
1913 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1914 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1915 case NVME_IOCTL_IO_CMD:
a4aea562 1916 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1917 case NVME_IOCTL_SUBMIT_IO:
1918 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1919 case SG_GET_VERSION_NUM:
1920 return nvme_sg_get_version_num((void __user *)arg);
1921 case SG_IO:
1922 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1923 default:
1924 return -ENOTTY;
1925 }
1926}
1927
320a3827
KB		 1928#ifdef CONFIG_COMPAT
1929static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1930 unsigned int cmd, unsigned long arg)
1931{
320a3827
KB		 1932 switch (cmd) {
1933 case SG_IO:
e179729a 1934 return -ENOIOCTLCMD;
320a3827
KB		 1935 }
1936 return nvme_ioctl(bdev, mode, cmd, arg);
1937}
1938#else
1939#define nvme_compat_ioctl NULL
1940#endif
1941
5105aa55 1942static void nvme_free_dev(struct kref *kref);
188c3568
KB		 1943static void nvme_free_ns(struct kref *kref)
1944{
1945 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
1946
1947 spin_lock(&dev_list_lock);
1948 ns->disk->private_data = NULL;
1949 spin_unlock(&dev_list_lock);
1950
5105aa55 1951 kref_put(&ns->dev->kref, nvme_free_dev);
188c3568
KB		 1952 put_disk(ns->disk);
1953 kfree(ns);
1954}
1955
9ac27090
KB		 1956static int nvme_open(struct block_device *bdev, fmode_t mode)
1957{
9e60352c
KB		 1958 int ret = 0;
1959 struct nvme_ns *ns;
9ac27090 1960
9e60352c
KB		 1961 spin_lock(&dev_list_lock);
1962 ns = bdev->bd_disk->private_data;
1963 if (!ns)
1964 ret = -ENXIO;
188c3568 1965 else if (!kref_get_unless_zero(&ns->kref))
9e60352c
KB		 1966 ret = -ENXIO;
1967 spin_unlock(&dev_list_lock);
1968
1969 return ret;
9ac27090
KB		 1970}
1971
9ac27090
KB		 1972static void nvme_release(struct gendisk *disk, fmode_t mode)
1973{
1974 struct nvme_ns *ns = disk->private_data;
188c3568 1975 kref_put(&ns->kref, nvme_free_ns);
9ac27090
KB		 1976}
1977
4cc09e2d
KB		 1978static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1979{
1980 /* some standard values */
1981 geo->heads = 1 << 6;
1982 geo->sectors = 1 << 5;
1983 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1984 return 0;
1985}
1986
e1e5e564
KB		 1987static void nvme_config_discard(struct nvme_ns *ns)
1988{
1989 u32 logical_block_size = queue_logical_block_size(ns->queue);
1990 ns->queue->limits.discard_zeroes_data = 0;
1991 ns->queue->limits.discard_alignment = logical_block_size;
1992 ns->queue->limits.discard_granularity = logical_block_size;
2bb4cd5c 1993 blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
e1e5e564
KB		 1994 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1995}
1996
1b9dbf7f
KB		 1997static int nvme_revalidate_disk(struct gendisk *disk)
1998{
1999 struct nvme_ns *ns = disk->private_data;
2000 struct nvme_dev *dev = ns->dev;
2001 struct nvme_id_ns *id;
a67a9513
KB		 2002 u8 lbaf, pi_type;
2003 u16 old_ms;
e1e5e564 2004 unsigned short bs;
1b9dbf7f 2005
d29ec824 2006 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
a5768aa8
KB		 2007 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
2008 dev->instance, ns->ns_id);
2009 return -ENODEV;
1b9dbf7f 2010 }
a5768aa8
KB		 2011 if (id->ncap == 0) {
2012 kfree(id);
2013 return -ENODEV;
e1e5e564 2014 }
1b9dbf7f 2015
e1e5e564
KB		 2016 old_ms = ns->ms;
2017 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1b9dbf7f 2018 ns->lba_shift = id->lbaf[lbaf].ds;
e1e5e564 2019 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
a67a9513 2020 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
e1e5e564
KB		 2021
2022 /*
2023 * If identify namespace failed, use default 512 byte block size so
2024 * block layer can use before failing read/write for 0 capacity.
2025 */
2026 if (ns->lba_shift == 0)
2027 ns->lba_shift = 9;
2028 bs = 1 << ns->lba_shift;
2029
2030 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2031 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2032 id->dps & NVME_NS_DPS_PI_MASK : 0;
2033
52b68d7e
KB		 2034 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2035 ns->ms != old_ms ||
e1e5e564 2036 bs != queue_logical_block_size(disk->queue) ||
a67a9513 2037 (ns->ms && ns->ext)))
e1e5e564
KB		 2038 blk_integrity_unregister(disk);
2039
2040 ns->pi_type = pi_type;
2041 blk_queue_logical_block_size(ns->queue, bs);
2042
52b68d7e 2043 if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
a67a9513 2044 !ns->ext)
e1e5e564
KB		 2045 nvme_init_integrity(ns);
2046
e19b127f 2047 if (ns->ms && !(ns->ms == 8 && ns->pi_type) && !blk_get_integrity(disk))
e1e5e564
KB		 2048 set_capacity(disk, 0);
2049 else
2050 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2051
2052 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2053 nvme_config_discard(ns);
1b9dbf7f 2054
d29ec824 2055 kfree(id);
1b9dbf7f
KB		 2056 return 0;
2057}
2058
b60503ba
MW		 2059static const struct block_device_operations nvme_fops = {
2060 .owner = THIS_MODULE,
2061 .ioctl = nvme_ioctl,
320a3827 2062 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 2063 .open = nvme_open,
2064 .release = nvme_release,
4cc09e2d 2065 .getgeo = nvme_getgeo,
1b9dbf7f 2066 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 2067};
2068
1fa6aead
MW		 2069static int nvme_kthread(void *data)
2070{
d4b4ff8e 2071 struct nvme_dev *dev, *next;
1fa6aead
MW		 2072
2073 while (!kthread_should_stop()) {
564a232c 2074 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 2075 spin_lock(&dev_list_lock);
d4b4ff8e 2076 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 2077 int i;
dfbac8c7
KB		 2078 u32 csts = readl(&dev->bar->csts);
2079
2080 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
2081 csts & NVME_CSTS_CFS) {
90667892
CH		 2082 if (!__nvme_reset(dev)) {
2083 dev_warn(dev->dev,
2084 "Failed status: %x, reset controller\n",
2085 readl(&dev->bar->csts));
2086 }
d4b4ff8e
KB		 2087 continue;
2088 }
1fa6aead 2089 for (i = 0; i < dev->queue_count; i++) {
a4aea562 2090 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 2091 if (!nvmeq)
2092 continue;
1fa6aead 2093 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 2094 nvme_process_cq(nvmeq);
6fccf938
KB		 2095
2096 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 2097 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 2098 break;
2099 dev->event_limit--;
2100 }
1fa6aead
MW		 2101 spin_unlock_irq(&nvmeq->q_lock);
2102 }
2103 }
2104 spin_unlock(&dev_list_lock);
acb7aa0d 2105 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 2106 }
2107 return 0;
2108}
2109
e1e5e564 2110static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
b60503ba
MW		 2111{
2112 struct nvme_ns *ns;
2113 struct gendisk *disk;
e75ec752 2114 int node = dev_to_node(dev->dev);
b60503ba 2115
a4aea562 2116 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba 2117 if (!ns)
e1e5e564
KB		 2118 return;
2119
a4aea562 2120 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 2121 if (IS_ERR(ns->queue))
b60503ba 2122 goto out_free_ns;
4eeb9215
MW		 2123 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2124 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 2125 ns->dev = dev;
2126 ns->queue->queuedata = ns;
2127
a4aea562 2128 disk = alloc_disk_node(0, node);
b60503ba
MW		 2129 if (!disk)
2130 goto out_free_queue;
a4aea562 2131
188c3568 2132 kref_init(&ns->kref);
5aff9382 2133 ns->ns_id = nsid;
b60503ba 2134 ns->disk = disk;
e1e5e564
KB		 2135 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2136 list_add_tail(&ns->list, &dev->namespaces);
2137
e9ef4636 2138 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
e824410f 2139 if (dev->max_hw_sectors) {
8fc23e03 2140 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
e824410f
KB		 2141 blk_queue_max_segments(ns->queue,
2142 ((dev->max_hw_sectors << 9) / dev->page_size) + 1);
2143 }
a4aea562
MB		 2144 if (dev->stripe_size)
2145 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2146 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2147 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
03100aad 2148 blk_queue_virt_boundary(ns->queue, dev->page_size - 1);
b60503ba
MW		 2149
2150 disk->major = nvme_major;
469071a3 2151 disk->first_minor = 0;
b60503ba
MW		 2152 disk->fops = &nvme_fops;
2153 disk->private_data = ns;
2154 disk->queue = ns->queue;
b3fffdef 2155 disk->driverfs_dev = dev->device;
469071a3 2156 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2157 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba 2158
e1e5e564
KB		 2159 /*
2160 * Initialize capacity to 0 until we establish the namespace format and
2161 * setup integrity extentions if necessary. The revalidate_disk after
2162 * add_disk allows the driver to register with integrity if the format
2163 * requires it.
2164 */
2165 set_capacity(disk, 0);
a5768aa8
KB		 2166 if (nvme_revalidate_disk(ns->disk))
2167 goto out_free_disk;
2168
5105aa55 2169 kref_get(&dev->kref);
e1e5e564 2170 add_disk(ns->disk);
7bee6074
KB		 2171 if (ns->ms) {
2172 struct block_device *bd = bdget_disk(ns->disk, 0);
2173 if (!bd)
2174 return;
2175 if (blkdev_get(bd, FMODE_READ, NULL)) {
2176 bdput(bd);
2177 return;
2178 }
2179 blkdev_reread_part(bd);
2180 blkdev_put(bd, FMODE_READ);
2181 }
e1e5e564 2182 return;
a5768aa8
KB		 2183 out_free_disk:
2184 kfree(disk);
2185 list_del(&ns->list);
b60503ba
MW		 2186 out_free_queue:
2187 blk_cleanup_queue(ns->queue);
2188 out_free_ns:
2189 kfree(ns);
b60503ba
MW		 2190}
2191
42f61420
KB		 2192static void nvme_create_io_queues(struct nvme_dev *dev)
2193{
a4aea562 2194 unsigned i;
42f61420 2195
a4aea562 2196 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2197 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2198 break;
2199
a4aea562
MB		 2200 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2201 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 2202 break;
2203}
2204
b3b06812 2205static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2206{
2207 int status;
2208 u32 result;
b3b06812 2209 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2210
df348139 2211 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2212 &result);
27e8166c
MW		 2213 if (status < 0)
2214 return status;
2215 if (status > 0) {
e75ec752 2216 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
badc34d4 2217 return 0;
27e8166c 2218 }
b60503ba
MW		 2219 return min(result & 0xffff, result >> 16) + 1;
2220}
2221
8ffaadf7
JD		 2222static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
2223{
2224 u64 szu, size, offset;
2225 u32 cmbloc;
2226 resource_size_t bar_size;
2227 struct pci_dev *pdev = to_pci_dev(dev->dev);
2228 void __iomem *cmb;
2229 dma_addr_t dma_addr;
2230
2231 if (!use_cmb_sqes)
2232 return NULL;
2233
2234 dev->cmbsz = readl(&dev->bar->cmbsz);
2235 if (!(NVME_CMB_SZ(dev->cmbsz)))
2236 return NULL;
2237
2238 cmbloc = readl(&dev->bar->cmbloc);
2239
2240 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
2241 size = szu * NVME_CMB_SZ(dev->cmbsz);
2242 offset = szu * NVME_CMB_OFST(cmbloc);
2243 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
2244
2245 if (offset > bar_size)
2246 return NULL;
2247
2248 /*
2249 * Controllers may support a CMB size larger than their BAR,
2250 * for example, due to being behind a bridge. Reduce the CMB to
2251 * the reported size of the BAR
2252 */
2253 if (size > bar_size - offset)
2254 size = bar_size - offset;
2255
2256 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
2257 cmb = ioremap_wc(dma_addr, size);
2258 if (!cmb)
2259 return NULL;
2260
2261 dev->cmb_dma_addr = dma_addr;
2262 dev->cmb_size = size;
2263 return cmb;
2264}
2265
2266static inline void nvme_release_cmb(struct nvme_dev *dev)
2267{
2268 if (dev->cmb) {
2269 iounmap(dev->cmb);
2270 dev->cmb = NULL;
2271 }
2272}
2273
9d713c2b
KB		 2274static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2275{
b80d5ccc 2276 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2277}
2278
8d85fce7 2279static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2280{
a4aea562 2281 struct nvme_queue *adminq = dev->queues[0];
e75ec752 2282 struct pci_dev *pdev = to_pci_dev(dev->dev);
42f61420 2283 int result, i, vecs, nr_io_queues, size;
b60503ba 2284
42f61420 2285 nr_io_queues = num_possible_cpus();
b348b7d5 2286 result = set_queue_count(dev, nr_io_queues);
badc34d4 2287 if (result <= 0)
1b23484b 2288 return result;
b348b7d5
MW		 2289 if (result < nr_io_queues)
2290 nr_io_queues = result;
b60503ba 2291
8ffaadf7
JD		 2292 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
2293 result = nvme_cmb_qdepth(dev, nr_io_queues,
2294 sizeof(struct nvme_command));
2295 if (result > 0)
2296 dev->q_depth = result;
2297 else
2298 nvme_release_cmb(dev);
2299 }
2300
9d713c2b
KB		 2301 size = db_bar_size(dev, nr_io_queues);
2302 if (size > 8192) {
f1938f6e 2303 iounmap(dev->bar);
9d713c2b
KB		 2304 do {
2305 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2306 if (dev->bar)
2307 break;
2308 if (!--nr_io_queues)
2309 return -ENOMEM;
2310 size = db_bar_size(dev, nr_io_queues);
2311 } while (1);
f1938f6e 2312 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2313 adminq->q_db = dev->dbs;
f1938f6e
MW		 2314 }
2315
9d713c2b 2316 /* Deregister the admin queue's interrupt */
3193f07b 2317 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2318
e32efbfc
JA		 2319 /*
2320 * If we enable msix early due to not intx, disable it again before
2321 * setting up the full range we need.
2322 */
2323 if (!pdev->irq)
2324 pci_disable_msix(pdev);
2325
be577fab 2326 for (i = 0; i < nr_io_queues; i++)
1b23484b 2327 dev->entry[i].entry = i;
be577fab
AG		 2328 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2329 if (vecs < 0) {
2330 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2331 if (vecs < 0) {
2332 vecs = 1;
2333 } else {
2334 for (i = 0; i < vecs; i++)
2335 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2336 }
2337 }
2338
063a8096
MW		 2339 /*
2340 * Should investigate if there's a performance win from allocating
2341 * more queues than interrupt vectors; it might allow the submission
2342 * path to scale better, even if the receive path is limited by the
2343 * number of interrupts.
2344 */
2345 nr_io_queues = vecs;
42f61420 2346 dev->max_qid = nr_io_queues;
063a8096 2347
3193f07b 2348 result = queue_request_irq(dev, adminq, adminq->irqname);
758dd7fd
JD		 2349 if (result) {
2350 adminq->cq_vector = -1;
22404274 2351 goto free_queues;
758dd7fd 2352 }
1b23484b 2353
cd638946 2354 /* Free previously allocated queues that are no longer usable */
42f61420 2355 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2356 nvme_create_io_queues(dev);
9ecdc946 2357
22404274 2358 return 0;
b60503ba 2359
22404274 2360 free_queues:
a1a5ef99 2361 nvme_free_queues(dev, 1);
22404274 2362 return result;
b60503ba
MW		 2363}
2364
a5768aa8
KB		 2365static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2366{
2367 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2368 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2369
2370 return nsa->ns_id - nsb->ns_id;
2371}
2372
2373static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2374{
2375 struct nvme_ns *ns;
2376
2377 list_for_each_entry(ns, &dev->namespaces, list) {
2378 if (ns->ns_id == nsid)
2379 return ns;
2380 if (ns->ns_id > nsid)
2381 break;
2382 }
2383 return NULL;
2384}
2385
2386static inline bool nvme_io_incapable(struct nvme_dev *dev)
2387{
2388 return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
2389 dev->online_queues < 2);
2390}
2391
2392static void nvme_ns_remove(struct nvme_ns *ns)
2393{
2394 bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2395
2396 if (kill)
2397 blk_set_queue_dying(ns->queue);
2398 if (ns->disk->flags & GENHD_FL_UP) {
2399 if (blk_get_integrity(ns->disk))
2400 blk_integrity_unregister(ns->disk);
2401 del_gendisk(ns->disk);
2402 }
2403 if (kill || !blk_queue_dying(ns->queue)) {
2404 blk_mq_abort_requeue_list(ns->queue);
2405 blk_cleanup_queue(ns->queue);
5105aa55
KB		 2406 }
2407 list_del_init(&ns->list);
2408 kref_put(&ns->kref, nvme_free_ns);
a5768aa8
KB		 2409}
2410
2411static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2412{
2413 struct nvme_ns *ns, *next;
2414 unsigned i;
2415
2416 for (i = 1; i <= nn; i++) {
2417 ns = nvme_find_ns(dev, i);
2418 if (ns) {
5105aa55 2419 if (revalidate_disk(ns->disk))
a5768aa8 2420 nvme_ns_remove(ns);
a5768aa8
KB		 2421 } else
2422 nvme_alloc_ns(dev, i);
2423 }
2424 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
5105aa55 2425 if (ns->ns_id > nn)
a5768aa8 2426 nvme_ns_remove(ns);
a5768aa8
KB		 2427 }
2428 list_sort(NULL, &dev->namespaces, ns_cmp);
2429}
2430
bda4e0fb
KB		 2431static void nvme_set_irq_hints(struct nvme_dev *dev)
2432{
2433 struct nvme_queue *nvmeq;
2434 int i;
2435
2436 for (i = 0; i < dev->online_queues; i++) {
2437 nvmeq = dev->queues[i];
2438
2439 if (!nvmeq->tags || !(*nvmeq->tags))
2440 continue;
2441
2442 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2443 blk_mq_tags_cpumask(*nvmeq->tags));
2444 }
2445}
2446
a5768aa8
KB		 2447static void nvme_dev_scan(struct work_struct *work)
2448{
2449 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2450 struct nvme_id_ctrl *ctrl;
2451
2452 if (!dev->tagset.tags)
2453 return;
2454 if (nvme_identify_ctrl(dev, &ctrl))
2455 return;
2456 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2457 kfree(ctrl);
bda4e0fb 2458 nvme_set_irq_hints(dev);
a5768aa8
KB		 2459}
2460
422ef0c7
MW		 2461/*
2462 * Return: error value if an error occurred setting up the queues or calling
2463 * Identify Device. 0 if these succeeded, even if adding some of the
2464 * namespaces failed. At the moment, these failures are silent. TBD which
2465 * failures should be reported.
2466 */
8d85fce7 2467static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2468{
e75ec752 2469 struct pci_dev *pdev = to_pci_dev(dev->dev);
c3bfe717 2470 int res;
51814232 2471 struct nvme_id_ctrl *ctrl;
159b67d7 2472 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2473
d29ec824 2474 res = nvme_identify_ctrl(dev, &ctrl);
b60503ba 2475 if (res) {
e75ec752 2476 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
e1e5e564 2477 return -EIO;
b60503ba
MW		 2478 }
2479
0e5e4f0e 2480 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2481 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2482 dev->vwc = ctrl->vwc;
51814232
MW		 2483 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2484 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2485 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2486 if (ctrl->mdts)
8fc23e03 2487 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2488 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2489 (pdev->device == 0x0953) && ctrl->vs[3]) {
2490 unsigned int max_hw_sectors;
2491
159b67d7 2492 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2493 max_hw_sectors = dev->stripe_size >> (shift - 9);
2494 if (dev->max_hw_sectors) {
2495 dev->max_hw_sectors = min(max_hw_sectors,
2496 dev->max_hw_sectors);
2497 } else
2498 dev->max_hw_sectors = max_hw_sectors;
2499 }
d29ec824 2500 kfree(ctrl);
a4aea562 2501
ffe7704d
KB		 2502 if (!dev->tagset.tags) {
2503 dev->tagset.ops = &nvme_mq_ops;
2504 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2505 dev->tagset.timeout = NVME_IO_TIMEOUT;
2506 dev->tagset.numa_node = dev_to_node(dev->dev);
2507 dev->tagset.queue_depth =
a4aea562 2508 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ffe7704d
KB		 2509 dev->tagset.cmd_size = nvme_cmd_size(dev);
2510 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2511 dev->tagset.driver_data = dev;
b60503ba 2512
ffe7704d
KB		 2513 if (blk_mq_alloc_tag_set(&dev->tagset))
2514 return 0;
2515 }
a5768aa8 2516 schedule_work(&dev->scan_work);
e1e5e564 2517 return 0;
b60503ba
MW		 2518}
2519
0877cb0d
KB		 2520static int nvme_dev_map(struct nvme_dev *dev)
2521{
42f61420 2522 u64 cap;
0877cb0d 2523 int bars, result = -ENOMEM;
e75ec752 2524 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2525
2526 if (pci_enable_device_mem(pdev))
2527 return result;
2528
2529 dev->entry[0].vector = pdev->irq;
2530 pci_set_master(pdev);
2531 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2532 if (!bars)
2533 goto disable_pci;
2534
0877cb0d
KB		 2535 if (pci_request_selected_regions(pdev, bars, "nvme"))
2536 goto disable_pci;
2537
e75ec752
CH		 2538 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2539 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2540 goto disable;
0877cb0d 2541
0877cb0d
KB		 2542 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2543 if (!dev->bar)
2544 goto disable;
e32efbfc 2545
0e53d180
KB		 2546 if (readl(&dev->bar->csts) == -1) {
2547 result = -ENODEV;
2548 goto unmap;
2549 }
e32efbfc
JA		 2550
2551 /*
2552 * Some devices don't advertse INTx interrupts, pre-enable a single
2553 * MSIX vec for setup. We'll adjust this later.
2554 */
2555 if (!pdev->irq) {
2556 result = pci_enable_msix(pdev, dev->entry, 1);
2557 if (result < 0)
2558 goto unmap;
2559 }
2560
42f61420
KB		 2561 cap = readq(&dev->bar->cap);
2562 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2563 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d 2564 dev->dbs = ((void __iomem *)dev->bar) + 4096;
8ffaadf7
JD		 2565 if (readl(&dev->bar->vs) >= NVME_VS(1, 2))
2566 dev->cmb = nvme_map_cmb(dev);
0877cb0d
KB		 2567
2568 return 0;
2569
0e53d180
KB		 2570 unmap:
2571 iounmap(dev->bar);
2572 dev->bar = NULL;
0877cb0d
KB		 2573 disable:
2574 pci_release_regions(pdev);
2575 disable_pci:
2576 pci_disable_device(pdev);
2577 return result;
2578}
2579
2580static void nvme_dev_unmap(struct nvme_dev *dev)
2581{
e75ec752
CH		 2582 struct pci_dev *pdev = to_pci_dev(dev->dev);
2583
2584 if (pdev->msi_enabled)
2585 pci_disable_msi(pdev);
2586 else if (pdev->msix_enabled)
2587 pci_disable_msix(pdev);
0877cb0d
KB		 2588
2589 if (dev->bar) {
2590 iounmap(dev->bar);
2591 dev->bar = NULL;
e75ec752 2592 pci_release_regions(pdev);
0877cb0d
KB		 2593 }
2594
e75ec752
CH		 2595 if (pci_is_enabled(pdev))
2596 pci_disable_device(pdev);
0877cb0d
KB		 2597}
2598
4d115420
KB		 2599struct nvme_delq_ctx {
2600 struct task_struct *waiter;
2601 struct kthread_worker *worker;
2602 atomic_t refcount;
2603};
2604
2605static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2606{
2607 dq->waiter = current;
2608 mb();
2609
2610 for (;;) {
2611 set_current_state(TASK_KILLABLE);
2612 if (!atomic_read(&dq->refcount))
2613 break;
2614 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2615 fatal_signal_pending(current)) {
0fb59cbc
KB		 2616 /*
2617 * Disable the controller first since we can't trust it
2618 * at this point, but leave the admin queue enabled
2619 * until all queue deletion requests are flushed.
2620 * FIXME: This may take a while if there are more h/w
2621 * queues than admin tags.
2622 */
4d115420 2623 set_current_state(TASK_RUNNING);
4d115420 2624 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2625 nvme_clear_queue(dev->queues[0]);
4d115420 2626 flush_kthread_worker(dq->worker);
0fb59cbc 2627 nvme_disable_queue(dev, 0);
4d115420
KB		 2628 return;
2629 }
2630 }
2631 set_current_state(TASK_RUNNING);
2632}
2633
2634static void nvme_put_dq(struct nvme_delq_ctx *dq)
2635{
2636 atomic_dec(&dq->refcount);
2637 if (dq->waiter)
2638 wake_up_process(dq->waiter);
2639}
2640
2641static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2642{
2643 atomic_inc(&dq->refcount);
2644 return dq;
2645}
2646
2647static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2648{
2649 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
4d115420
KB		 2650 nvme_put_dq(dq);
2651}
2652
2653static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2654 kthread_work_func_t fn)
2655{
2656 struct nvme_command c;
2657
2658 memset(&c, 0, sizeof(c));
2659 c.delete_queue.opcode = opcode;
2660 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2661
2662 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2663 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2664 ADMIN_TIMEOUT);
4d115420
KB		 2665}
2666
2667static void nvme_del_cq_work_handler(struct kthread_work *work)
2668{
2669 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2670 cmdinfo.work);
2671 nvme_del_queue_end(nvmeq);
2672}
2673
2674static int nvme_delete_cq(struct nvme_queue *nvmeq)
2675{
2676 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2677 nvme_del_cq_work_handler);
2678}
2679
2680static void nvme_del_sq_work_handler(struct kthread_work *work)
2681{
2682 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2683 cmdinfo.work);
2684 int status = nvmeq->cmdinfo.status;
2685
2686 if (!status)
2687 status = nvme_delete_cq(nvmeq);
2688 if (status)
2689 nvme_del_queue_end(nvmeq);
2690}
2691
2692static int nvme_delete_sq(struct nvme_queue *nvmeq)
2693{
2694 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2695 nvme_del_sq_work_handler);
2696}
2697
2698static void nvme_del_queue_start(struct kthread_work *work)
2699{
2700 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2701 cmdinfo.work);
4d115420
KB		 2702 if (nvme_delete_sq(nvmeq))
2703 nvme_del_queue_end(nvmeq);
2704}
2705
2706static void nvme_disable_io_queues(struct nvme_dev *dev)
2707{
2708 int i;
2709 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2710 struct nvme_delq_ctx dq;
2711 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2712 &worker, "nvme%d", dev->instance);
2713
2714 if (IS_ERR(kworker_task)) {
e75ec752 2715 dev_err(dev->dev,
4d115420
KB		 2716 "Failed to create queue del task\n");
2717 for (i = dev->queue_count - 1; i > 0; i--)
2718 nvme_disable_queue(dev, i);
2719 return;
2720 }
2721
2722 dq.waiter = NULL;
2723 atomic_set(&dq.refcount, 0);
2724 dq.worker = &worker;
2725 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2726 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2727
2728 if (nvme_suspend_queue(nvmeq))
2729 continue;
2730 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2731 nvmeq->cmdinfo.worker = dq.worker;
2732 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2733 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2734 }
2735 nvme_wait_dq(&dq, dev);
2736 kthread_stop(kworker_task);
2737}
2738
b9afca3e
DM		 2739/*
2740* Remove the node from the device list and check
2741* for whether or not we need to stop the nvme_thread.
2742*/
2743static void nvme_dev_list_remove(struct nvme_dev *dev)
2744{
2745 struct task_struct *tmp = NULL;
2746
2747 spin_lock(&dev_list_lock);
2748 list_del_init(&dev->node);
2749 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2750 tmp = nvme_thread;
2751 nvme_thread = NULL;
2752 }
2753 spin_unlock(&dev_list_lock);
2754
2755 if (tmp)
2756 kthread_stop(tmp);
2757}
2758
c9d3bf88
KB		 2759static void nvme_freeze_queues(struct nvme_dev *dev)
2760{
2761 struct nvme_ns *ns;
2762
2763 list_for_each_entry(ns, &dev->namespaces, list) {
2764 blk_mq_freeze_queue_start(ns->queue);
2765
cddcd72b 2766 spin_lock_irq(ns->queue->queue_lock);
c9d3bf88 2767 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
cddcd72b 2768 spin_unlock_irq(ns->queue->queue_lock);
c9d3bf88
KB		 2769
2770 blk_mq_cancel_requeue_work(ns->queue);
2771 blk_mq_stop_hw_queues(ns->queue);
2772 }
2773}
2774
2775static void nvme_unfreeze_queues(struct nvme_dev *dev)
2776{
2777 struct nvme_ns *ns;
2778
2779 list_for_each_entry(ns, &dev->namespaces, list) {
2780 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2781 blk_mq_unfreeze_queue(ns->queue);
2782 blk_mq_start_stopped_hw_queues(ns->queue, true);
2783 blk_mq_kick_requeue_list(ns->queue);
2784 }
2785}
2786
f0b50732 2787static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2788{
22404274 2789 int i;
7c1b2450 2790 u32 csts = -1;
22404274 2791
b9afca3e 2792 nvme_dev_list_remove(dev);
1fa6aead 2793
c9d3bf88
KB		 2794 if (dev->bar) {
2795 nvme_freeze_queues(dev);
7c1b2450 2796 csts = readl(&dev->bar->csts);
c9d3bf88 2797 }
7c1b2450 2798 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2799 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2800 struct nvme_queue *nvmeq = dev->queues[i];
4d115420 2801 nvme_suspend_queue(nvmeq);
4d115420
KB		 2802 }
2803 } else {
2804 nvme_disable_io_queues(dev);
1894d8f1 2805 nvme_shutdown_ctrl(dev);
4d115420
KB		 2806 nvme_disable_queue(dev, 0);
2807 }
f0b50732 2808 nvme_dev_unmap(dev);
07836e65
KB		 2809
2810 for (i = dev->queue_count - 1; i >= 0; i--)
2811 nvme_clear_queue(dev->queues[i]);
f0b50732
KB		 2812}
2813
2814static void nvme_dev_remove(struct nvme_dev *dev)
2815{
5105aa55 2816 struct nvme_ns *ns, *next;
f0b50732 2817
5105aa55 2818 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
a5768aa8 2819 nvme_ns_remove(ns);
b60503ba
MW		 2820}
2821
091b6092
MW		 2822static int nvme_setup_prp_pools(struct nvme_dev *dev)
2823{
e75ec752 2824 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2825 PAGE_SIZE, PAGE_SIZE, 0);
2826 if (!dev->prp_page_pool)
2827 return -ENOMEM;
2828
99802a7a 2829 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2830 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2831 256, 256, 0);
2832 if (!dev->prp_small_pool) {
2833 dma_pool_destroy(dev->prp_page_pool);
2834 return -ENOMEM;
2835 }
091b6092
MW		 2836 return 0;
2837}
2838
2839static void nvme_release_prp_pools(struct nvme_dev *dev)
2840{
2841 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2842 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2843}
2844
cd58ad7d
QSA		 2845static DEFINE_IDA(nvme_instance_ida);
2846
2847static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2848{
cd58ad7d
QSA		 2849 int instance, error;
2850
2851 do {
2852 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2853 return -ENODEV;
2854
2855 spin_lock(&dev_list_lock);
2856 error = ida_get_new(&nvme_instance_ida, &instance);
2857 spin_unlock(&dev_list_lock);
2858 } while (error == -EAGAIN);
2859
2860 if (error)
2861 return -ENODEV;
2862
2863 dev->instance = instance;
2864 return 0;
b60503ba
MW		 2865}
2866
2867static void nvme_release_instance(struct nvme_dev *dev)
2868{
cd58ad7d
QSA		 2869 spin_lock(&dev_list_lock);
2870 ida_remove(&nvme_instance_ida, dev->instance);
2871 spin_unlock(&dev_list_lock);
b60503ba
MW		 2872}
2873
5e82e952
KB		 2874static void nvme_free_dev(struct kref *kref)
2875{
2876 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2877
e75ec752 2878 put_device(dev->dev);
b3fffdef 2879 put_device(dev->device);
285dffc9 2880 nvme_release_instance(dev);
4af0e21c
KB		 2881 if (dev->tagset.tags)
2882 blk_mq_free_tag_set(&dev->tagset);
2883 if (dev->admin_q)
2884 blk_put_queue(dev->admin_q);
5e82e952
KB		 2885 kfree(dev->queues);
2886 kfree(dev->entry);
2887 kfree(dev);
2888}
2889
2890static int nvme_dev_open(struct inode *inode, struct file *f)
2891{
b3fffdef
KB		 2892 struct nvme_dev *dev;
2893 int instance = iminor(inode);
2894 int ret = -ENODEV;
2895
2896 spin_lock(&dev_list_lock);
2897 list_for_each_entry(dev, &dev_list, node) {
2898 if (dev->instance == instance) {
2e1d8448
KB		 2899 if (!dev->admin_q) {
2900 ret = -EWOULDBLOCK;
2901 break;
2902 }
b3fffdef
KB		 2903 if (!kref_get_unless_zero(&dev->kref))
2904 break;
2905 f->private_data = dev;
2906 ret = 0;
2907 break;
2908 }
2909 }
2910 spin_unlock(&dev_list_lock);
2911
2912 return ret;
5e82e952
KB		 2913}
2914
2915static int nvme_dev_release(struct inode *inode, struct file *f)
2916{
2917 struct nvme_dev *dev = f->private_data;
2918 kref_put(&dev->kref, nvme_free_dev);
2919 return 0;
2920}
2921
2922static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2923{
2924 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2925 struct nvme_ns *ns;
2926
5e82e952
KB		 2927 switch (cmd) {
2928 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2929 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2930 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2931 if (list_empty(&dev->namespaces))
2932 return -ENOTTY;
2933 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2934 return nvme_user_cmd(dev, ns, (void __user *)arg);
4cc06521
KB		 2935 case NVME_IOCTL_RESET:
2936 dev_warn(dev->dev, "resetting controller\n");
2937 return nvme_reset(dev);
81f03fed
JD		 2938 case NVME_IOCTL_SUBSYS_RESET:
2939 return nvme_subsys_reset(dev);
5e82e952
KB		 2940 default:
2941 return -ENOTTY;
2942 }
2943}
2944
2945static const struct file_operations nvme_dev_fops = {
2946 .owner = THIS_MODULE,
2947 .open = nvme_dev_open,
2948 .release = nvme_dev_release,
2949 .unlocked_ioctl = nvme_dev_ioctl,
2950 .compat_ioctl = nvme_dev_ioctl,
2951};
2952
3cf519b5 2953static void nvme_probe_work(struct work_struct *work)
f0b50732 2954{
3cf519b5 2955 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
b9afca3e 2956 bool start_thread = false;
3cf519b5 2957 int result;
f0b50732
KB		 2958
2959 result = nvme_dev_map(dev);
2960 if (result)
3cf519b5 2961 goto out;
f0b50732
KB		 2962
2963 result = nvme_configure_admin_queue(dev);
2964 if (result)
2965 goto unmap;
2966
2967 spin_lock(&dev_list_lock);
b9afca3e
DM		 2968 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2969 start_thread = true;
2970 nvme_thread = NULL;
2971 }
f0b50732
KB		 2972 list_add(&dev->node, &dev_list);
2973 spin_unlock(&dev_list_lock);
2974
b9afca3e
DM		 2975 if (start_thread) {
2976 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2977 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2978 } else
2979 wait_event_killable(nvme_kthread_wait, nvme_thread);
2980
2981 if (IS_ERR_OR_NULL(nvme_thread)) {
2982 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2983 goto disable;
2984 }
a4aea562
MB		 2985
2986 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 2987 result = nvme_alloc_admin_tags(dev);
2988 if (result)
2989 goto disable;
b9afca3e 2990
f0b50732 2991 result = nvme_setup_io_queues(dev);
badc34d4 2992 if (result)
0fb59cbc 2993 goto free_tags;
f0b50732 2994
1efccc9d 2995 dev->event_limit = 1;
3cf519b5
CH		 2996
2997 if (dev->online_queues < 2) {
2998 dev_warn(dev->dev, "IO queues not created\n");
2999 nvme_free_queues(dev, 1);
3000 nvme_dev_remove(dev);
3001 } else {
3002 nvme_unfreeze_queues(dev);
3003 nvme_dev_add(dev);
3004 }
3005
3006 return;
f0b50732 3007
0fb59cbc
KB		 3008 free_tags:
3009 nvme_dev_remove_admin(dev);
4af0e21c
KB		 3010 blk_put_queue(dev->admin_q);
3011 dev->admin_q = NULL;
3012 dev->queues[0]->tags = NULL;
f0b50732 3013 disable:
a1a5ef99 3014 nvme_disable_queue(dev, 0);
b9afca3e 3015 nvme_dev_list_remove(dev);
f0b50732
KB		 3016 unmap:
3017 nvme_dev_unmap(dev);
3cf519b5
CH		 3018 out:
3019 if (!work_busy(&dev->reset_work))
3020 nvme_dead_ctrl(dev);
f0b50732
KB		 3021}
3022
9a6b9458
KB		 3023static int nvme_remove_dead_ctrl(void *arg)
3024{
3025 struct nvme_dev *dev = (struct nvme_dev *)arg;
e75ec752 3026 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 3027
3028 if (pci_get_drvdata(pdev))
c81f4975 3029 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 3030 kref_put(&dev->kref, nvme_free_dev);
3031 return 0;
3032}
3033
de3eff2b
KB		 3034static void nvme_dead_ctrl(struct nvme_dev *dev)
3035{
3036 dev_warn(dev->dev, "Device failed to resume\n");
3037 kref_get(&dev->kref);
3038 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
3039 dev->instance))) {
3040 dev_err(dev->dev,
3041 "Failed to start controller remove task\n");
3042 kref_put(&dev->kref, nvme_free_dev);
3043 }
3044}
3045
77b50d9e 3046static void nvme_reset_work(struct work_struct *ws)
9a6b9458 3047{
77b50d9e 3048 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
ffe7704d
KB		 3049 bool in_probe = work_busy(&dev->probe_work);
3050
9a6b9458 3051 nvme_dev_shutdown(dev);
ffe7704d
KB		 3052
3053 /* Synchronize with device probe so that work will see failure status
3054 * and exit gracefully without trying to schedule another reset */
3055 flush_work(&dev->probe_work);
3056
3057 /* Fail this device if reset occured during probe to avoid
3058 * infinite initialization loops. */
3059 if (in_probe) {
de3eff2b 3060 nvme_dead_ctrl(dev);
ffe7704d 3061 return;
9a6b9458 3062 }
ffe7704d
KB		 3063 /* Schedule device resume asynchronously so the reset work is available
3064 * to cleanup errors that may occur during reinitialization */
3065 schedule_work(&dev->probe_work);
9a6b9458
KB		 3066}
3067
90667892
CH		 3068static int __nvme_reset(struct nvme_dev *dev)
3069{
3070 if (work_pending(&dev->reset_work))
3071 return -EBUSY;
3072 list_del_init(&dev->node);
3073 queue_work(nvme_workq, &dev->reset_work);
3074 return 0;
3075}
3076
4cc06521
KB		 3077static int nvme_reset(struct nvme_dev *dev)
3078{
90667892 3079 int ret;
4cc06521
KB		 3080
3081 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
3082 return -ENODEV;
3083
3084 spin_lock(&dev_list_lock);
90667892 3085 ret = __nvme_reset(dev);
4cc06521
KB		 3086 spin_unlock(&dev_list_lock);
3087
3088 if (!ret) {
3089 flush_work(&dev->reset_work);
ffe7704d 3090 flush_work(&dev->probe_work);
4cc06521
KB		 3091 return 0;
3092 }
3093
3094 return ret;
3095}
3096
3097static ssize_t nvme_sysfs_reset(struct device *dev,
3098 struct device_attribute *attr, const char *buf,
3099 size_t count)
3100{
3101 struct nvme_dev *ndev = dev_get_drvdata(dev);
3102 int ret;
3103
3104 ret = nvme_reset(ndev);
3105 if (ret < 0)
3106 return ret;
3107
3108 return count;
3109}
3110static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3111
8d85fce7 3112static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 3113{
a4aea562 3114 int node, result = -ENOMEM;
b60503ba
MW		 3115 struct nvme_dev *dev;
3116
a4aea562
MB		 3117 node = dev_to_node(&pdev->dev);
3118 if (node == NUMA_NO_NODE)
3119 set_dev_node(&pdev->dev, 0);
3120
3121 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3122 if (!dev)
3123 return -ENOMEM;
a4aea562
MB		 3124 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3125 GFP_KERNEL, node);
b60503ba
MW		 3126 if (!dev->entry)
3127 goto free;
a4aea562
MB		 3128 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3129 GFP_KERNEL, node);
b60503ba
MW		 3130 if (!dev->queues)
3131 goto free;
3132
3133 INIT_LIST_HEAD(&dev->namespaces);
77b50d9e 3134 INIT_WORK(&dev->reset_work, nvme_reset_work);
e75ec752 3135 dev->dev = get_device(&pdev->dev);
9a6b9458 3136 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 3137 result = nvme_set_instance(dev);
3138 if (result)
a96d4f5c 3139 goto put_pci;
b60503ba 3140
091b6092
MW		 3141 result = nvme_setup_prp_pools(dev);
3142 if (result)
0877cb0d 3143 goto release;
091b6092 3144
fb35e914 3145 kref_init(&dev->kref);
b3fffdef
KB		 3146 dev->device = device_create(nvme_class, &pdev->dev,
3147 MKDEV(nvme_char_major, dev->instance),
3148 dev, "nvme%d", dev->instance);
3149 if (IS_ERR(dev->device)) {
3150 result = PTR_ERR(dev->device);
2e1d8448 3151 goto release_pools;
b3fffdef
KB		 3152 }
3153 get_device(dev->device);
4cc06521
KB		 3154 dev_set_drvdata(dev->device, dev);
3155
3156 result = device_create_file(dev->device, &dev_attr_reset_controller);
3157 if (result)
3158 goto put_dev;
740216fc 3159
e6e96d73 3160 INIT_LIST_HEAD(&dev->node);
a5768aa8 3161 INIT_WORK(&dev->scan_work, nvme_dev_scan);
3cf519b5 3162 INIT_WORK(&dev->probe_work, nvme_probe_work);
2e1d8448 3163 schedule_work(&dev->probe_work);
b60503ba
MW		 3164 return 0;
3165
4cc06521
KB		 3166 put_dev:
3167 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3168 put_device(dev->device);
0877cb0d 3169 release_pools:
091b6092 3170 nvme_release_prp_pools(dev);
0877cb0d
KB		 3171 release:
3172 nvme_release_instance(dev);
a96d4f5c 3173 put_pci:
e75ec752 3174 put_device(dev->dev);
b60503ba
MW		 3175 free:
3176 kfree(dev->queues);
3177 kfree(dev->entry);
3178 kfree(dev);
3179 return result;
3180}
3181
f0d54a54
KB		 3182static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3183{
a6739479 3184 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 3185
a6739479
KB		 3186 if (prepare)
3187 nvme_dev_shutdown(dev);
3188 else
0a7385ad 3189 schedule_work(&dev->probe_work);
f0d54a54
KB		 3190}
3191
09ece142
KB		 3192static void nvme_shutdown(struct pci_dev *pdev)
3193{
3194 struct nvme_dev *dev = pci_get_drvdata(pdev);
3195 nvme_dev_shutdown(dev);
3196}
3197
8d85fce7 3198static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3199{
3200 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 3201
3202 spin_lock(&dev_list_lock);
3203 list_del_init(&dev->node);
3204 spin_unlock(&dev_list_lock);
3205
3206 pci_set_drvdata(pdev, NULL);
2e1d8448 3207 flush_work(&dev->probe_work);
9a6b9458 3208 flush_work(&dev->reset_work);
a5768aa8 3209 flush_work(&dev->scan_work);
4cc06521 3210 device_remove_file(dev->device, &dev_attr_reset_controller);
c9d3bf88 3211 nvme_dev_remove(dev);
3399a3f7 3212 nvme_dev_shutdown(dev);
a4aea562 3213 nvme_dev_remove_admin(dev);
b3fffdef 3214 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
a1a5ef99 3215 nvme_free_queues(dev, 0);
8ffaadf7 3216 nvme_release_cmb(dev);
9a6b9458 3217 nvme_release_prp_pools(dev);
5e82e952 3218 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 3219}
3220
3221/* These functions are yet to be implemented */
3222#define nvme_error_detected NULL
3223#define nvme_dump_registers NULL
3224#define nvme_link_reset NULL
3225#define nvme_slot_reset NULL
3226#define nvme_error_resume NULL
cd638946 3227
671a6018 3228#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3229static int nvme_suspend(struct device *dev)
3230{
3231 struct pci_dev *pdev = to_pci_dev(dev);
3232 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3233
3234 nvme_dev_shutdown(ndev);
3235 return 0;
3236}
3237
3238static int nvme_resume(struct device *dev)
3239{
3240 struct pci_dev *pdev = to_pci_dev(dev);
3241 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3242
0a7385ad 3243 schedule_work(&ndev->probe_work);
9a6b9458 3244 return 0;
cd638946 3245}
671a6018 3246#endif
cd638946
KB		 3247
3248static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 3249
1d352035 3250static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 3251 .error_detected = nvme_error_detected,
3252 .mmio_enabled = nvme_dump_registers,
3253 .link_reset = nvme_link_reset,
3254 .slot_reset = nvme_slot_reset,
3255 .resume = nvme_error_resume,
f0d54a54 3256 .reset_notify = nvme_reset_notify,
b60503ba
MW		 3257};
3258
3259/* Move to pci_ids.h later */
3260#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3261
6eb0d698 3262static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 3263 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3264 { 0, }
3265};
3266MODULE_DEVICE_TABLE(pci, nvme_id_table);
3267
3268static struct pci_driver nvme_driver = {
3269 .name = "nvme",
3270 .id_table = nvme_id_table,
3271 .probe = nvme_probe,
8d85fce7 3272 .remove = nvme_remove,
09ece142 3273 .shutdown = nvme_shutdown,
cd638946
KB		 3274 .driver = {
3275 .pm = &nvme_dev_pm_ops,
3276 },
b60503ba
MW		 3277 .err_handler = &nvme_err_handler,
3278};
3279
3280static int __init nvme_init(void)
3281{
0ac13140 3282 int result;
1fa6aead 3283
b9afca3e 3284 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3285
9a6b9458
KB		 3286 nvme_workq = create_singlethread_workqueue("nvme");
3287 if (!nvme_workq)
b9afca3e 3288 return -ENOMEM;
9a6b9458 3289
5c42ea16
KB		 3290 result = register_blkdev(nvme_major, "nvme");
3291 if (result < 0)
9a6b9458 3292 goto kill_workq;
5c42ea16 3293 else if (result > 0)
0ac13140 3294 nvme_major = result;
b60503ba 3295
b3fffdef
KB		 3296 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3297 &nvme_dev_fops);
3298 if (result < 0)
3299 goto unregister_blkdev;
3300 else if (result > 0)
3301 nvme_char_major = result;
3302
3303 nvme_class = class_create(THIS_MODULE, "nvme");
c727040b
AK		 3304 if (IS_ERR(nvme_class)) {
3305 result = PTR_ERR(nvme_class);
b3fffdef 3306 goto unregister_chrdev;
c727040b 3307 }
b3fffdef 3308
f3db22fe
KB		 3309 result = pci_register_driver(&nvme_driver);
3310 if (result)
b3fffdef 3311 goto destroy_class;
1fa6aead 3312 return 0;
b60503ba 3313
b3fffdef
KB		 3314 destroy_class:
3315 class_destroy(nvme_class);
3316 unregister_chrdev:
3317 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1fa6aead 3318 unregister_blkdev:
b60503ba 3319 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3320 kill_workq:
3321 destroy_workqueue(nvme_workq);
b60503ba
MW		 3322 return result;
3323}
3324
3325static void __exit nvme_exit(void)
3326{
3327 pci_unregister_driver(&nvme_driver);
3328 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3329 destroy_workqueue(nvme_workq);
b3fffdef
KB		 3330 class_destroy(nvme_class);
3331 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
b9afca3e 3332 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3333 _nvme_check_size();
b60503ba
MW		 3334}
3335
3336MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3337MODULE_LICENSE("GPL");
c78b4713 3338MODULE_VERSION("1.0");
b60503ba
MW		 3339module_init(nvme_init);
3340module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)