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NVMe: CPU hot plug notification
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/nvme.h>
20#include <linux/bio.h>
8de05535 21#include <linux/bitops.h>
b60503ba 22#include <linux/blkdev.h>
42f61420 23#include <linux/cpu.h>
fd63e9ce 24#include <linux/delay.h>
b60503ba
MW		 25#include <linux/errno.h>
26#include <linux/fs.h>
27#include <linux/genhd.h>
5aff9382 28#include <linux/idr.h>
b60503ba
MW		 29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/io.h>
32#include <linux/kdev_t.h>
1fa6aead 33#include <linux/kthread.h>
b60503ba
MW		 34#include <linux/kernel.h>
35#include <linux/mm.h>
36#include <linux/module.h>
37#include <linux/moduleparam.h>
38#include <linux/pci.h>
42f61420 39#include <linux/percpu.h>
be7b6275 40#include <linux/poison.h>
c3bfe717 41#include <linux/ptrace.h>
b60503ba
MW		 42#include <linux/sched.h>
43#include <linux/slab.h>
44#include <linux/types.h>
5d0f6131 45#include <scsi/sg.h>
797a796a
HM		 46#include <asm-generic/io-64-nonatomic-lo-hi.h>
47
b60503ba
MW		 48#define NVME_Q_DEPTH 1024
49#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
50#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
e85248e5 51#define ADMIN_TIMEOUT (60 * HZ)
b60503ba
MW		 52
53static int nvme_major;
54module_param(nvme_major, int, 0);
55
58ffacb5
MW		 56static int use_threaded_interrupts;
57module_param(use_threaded_interrupts, int, 0);
58
1fa6aead
MW		 59static DEFINE_SPINLOCK(dev_list_lock);
60static LIST_HEAD(dev_list);
61static struct task_struct *nvme_thread;
9a6b9458 62static struct workqueue_struct *nvme_workq;
1fa6aead 63
d4b4ff8e
KB		 64static void nvme_reset_failed_dev(struct work_struct *ws);
65
4d115420
KB		 66struct async_cmd_info {
67 struct kthread_work work;
68 struct kthread_worker *worker;
69 u32 result;
70 int status;
71 void *ctx;
72};
1fa6aead 73
b60503ba
MW		 74/*
75 * An NVM Express queue. Each device has at least two (one for admin
76 * commands and one for I/O commands).
77 */
78struct nvme_queue {
5a92e700 79 struct rcu_head r_head;
b60503ba 80 struct device *q_dmadev;
091b6092 81 struct nvme_dev *dev;
3193f07b 82 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 83 spinlock_t q_lock;
84 struct nvme_command *sq_cmds;
85 volatile struct nvme_completion *cqes;
86 dma_addr_t sq_dma_addr;
87 dma_addr_t cq_dma_addr;
88 wait_queue_head_t sq_full;
1fa6aead 89 wait_queue_t sq_cong_wait;
b60503ba
MW		 90 struct bio_list sq_cong;
91 u32 __iomem *q_db;
92 u16 q_depth;
93 u16 cq_vector;
94 u16 sq_head;
95 u16 sq_tail;
96 u16 cq_head;
c30341dc 97 u16 qid;
e9539f47
MW		 98 u8 cq_phase;
99 u8 cqe_seen;
22404274 100 u8 q_suspended;
42f61420 101 cpumask_var_t cpu_mask;
4d115420 102 struct async_cmd_info cmdinfo;
b60503ba
MW		 103 unsigned long cmdid_data[];
104};
105
106/*
107 * Check we didin't inadvertently grow the command struct
108 */
109static inline void _nvme_check_size(void)
110{
111 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
112 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
113 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
114 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
115 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 116 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 117 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 118 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
119 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
120 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
121 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 122 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 123}
124
5c1281a3 125typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
c2f5b650
MW		 126 struct nvme_completion *);
127
e85248e5 128struct nvme_cmd_info {
c2f5b650
MW		 129 nvme_completion_fn fn;
130 void *ctx;
e85248e5 131 unsigned long timeout;
c30341dc 132 int aborted;
e85248e5
MW		 133};
134
135static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
136{
137 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
138}
139
22404274
KB		 140static unsigned nvme_queue_extra(int depth)
141{
142 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
143}
144
b60503ba 145/**
714a7a22
MW		 146 * alloc_cmdid() - Allocate a Command ID
147 * @nvmeq: The queue that will be used for this command
148 * @ctx: A pointer that will be passed to the handler
c2f5b650 149 * @handler: The function to call on completion
b60503ba
MW		 150 *
151 * Allocate a Command ID for a queue. The data passed in will
152 * be passed to the completion handler. This is implemented by using
153 * the bottom two bits of the ctx pointer to store the handler ID.
154 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
155 * We can change this if it becomes a problem.
184d2944
MW		 156 *
157 * May be called with local interrupts disabled and the q_lock held,
158 * or with interrupts enabled and no locks held.
b60503ba 159 */
c2f5b650
MW		 160static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
161 nvme_completion_fn handler, unsigned timeout)
b60503ba 162{
e6d15f79 163 int depth = nvmeq->q_depth - 1;
e85248e5 164 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba
MW		 165 int cmdid;
166
b60503ba
MW		 167 do {
168 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
169 if (cmdid >= depth)
170 return -EBUSY;
171 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
172
c2f5b650
MW		 173 info[cmdid].fn = handler;
174 info[cmdid].ctx = ctx;
e85248e5 175 info[cmdid].timeout = jiffies + timeout;
c30341dc 176 info[cmdid].aborted = 0;
b60503ba
MW		 177 return cmdid;
178}
179
180static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 181 nvme_completion_fn handler, unsigned timeout)
b60503ba
MW		 182{
183 int cmdid;
184 wait_event_killable(nvmeq->sq_full,
e85248e5 185 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
b60503ba
MW		 186 return (cmdid < 0) ? -EINTR : cmdid;
187}
188
c2f5b650
MW		 189/* Special values must be less than 0x1000 */
190#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 191#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
192#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
193#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
00df5cb4 194#define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
c30341dc 195#define CMD_CTX_ABORT (0x31C + CMD_CTX_BASE)
be7b6275 196
5c1281a3 197static void special_completion(struct nvme_dev *dev, void *ctx,
c2f5b650
MW		 198 struct nvme_completion *cqe)
199{
200 if (ctx == CMD_CTX_CANCELLED)
201 return;
202 if (ctx == CMD_CTX_FLUSH)
203 return;
c30341dc
KB		 204 if (ctx == CMD_CTX_ABORT) {
205 ++dev->abort_limit;
206 return;
207 }
c2f5b650 208 if (ctx == CMD_CTX_COMPLETED) {
5c1281a3 209 dev_warn(&dev->pci_dev->dev,
c2f5b650
MW		 210 "completed id %d twice on queue %d\n",
211 cqe->command_id, le16_to_cpup(&cqe->sq_id));
212 return;
213 }
214 if (ctx == CMD_CTX_INVALID) {
5c1281a3 215 dev_warn(&dev->pci_dev->dev,
c2f5b650
MW		 216 "invalid id %d completed on queue %d\n",
217 cqe->command_id, le16_to_cpup(&cqe->sq_id));
218 return;
219 }
220
5c1281a3 221 dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 222}
223
4d115420
KB		 224static void async_completion(struct nvme_dev *dev, void *ctx,
225 struct nvme_completion *cqe)
226{
227 struct async_cmd_info *cmdinfo = ctx;
228 cmdinfo->result = le32_to_cpup(&cqe->result);
229 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
230 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
231}
232
184d2944
MW		 233/*
234 * Called with local interrupts disabled and the q_lock held. May not sleep.
235 */
c2f5b650
MW		 236static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
237 nvme_completion_fn *fn)
b60503ba 238{
c2f5b650 239 void *ctx;
e85248e5 240 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 241
c2f5b650
MW		 242 if (cmdid >= nvmeq->q_depth) {
243 *fn = special_completion;
48e3d398 244 return CMD_CTX_INVALID;
c2f5b650 245 }
859361a2
KB		 246 if (fn)
247 *fn = info[cmdid].fn;
c2f5b650
MW		 248 ctx = info[cmdid].ctx;
249 info[cmdid].fn = special_completion;
e85248e5 250 info[cmdid].ctx = CMD_CTX_COMPLETED;
b60503ba
MW		 251 clear_bit(cmdid, nvmeq->cmdid_data);
252 wake_up(&nvmeq->sq_full);
c2f5b650 253 return ctx;
b60503ba
MW		 254}
255
c2f5b650
MW		 256static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
257 nvme_completion_fn *fn)
3c0cf138 258{
c2f5b650 259 void *ctx;
e85248e5 260 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
c2f5b650
MW		 261 if (fn)
262 *fn = info[cmdid].fn;
263 ctx = info[cmdid].ctx;
264 info[cmdid].fn = special_completion;
e85248e5 265 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 266 return ctx;
3c0cf138
MW		 267}
268
5a92e700 269static struct nvme_queue *raw_nvmeq(struct nvme_dev *dev, int qid)
b60503ba 270{
5a92e700 271 return rcu_dereference_raw(dev->queues[qid]);
b60503ba
MW		 272}
273
4f5099af 274static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) __acquires(RCU)
5a92e700 275{
42f61420 276 unsigned queue_id = get_cpu_var(*dev->io_queue);
5a92e700 277 rcu_read_lock();
42f61420 278 return rcu_dereference(dev->queues[queue_id]);
5a92e700
KB		 279}
280
4f5099af 281static void put_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
b60503ba 282{
5a92e700 283 rcu_read_unlock();
42f61420 284 put_cpu_var(nvmeq->dev->io_queue);
b60503ba
MW		 285}
286
4f5099af
KB		 287static struct nvme_queue *lock_nvmeq(struct nvme_dev *dev, int q_idx)
288 __acquires(RCU)
289{
290 rcu_read_lock();
291 return rcu_dereference(dev->queues[q_idx]);
292}
293
294static void unlock_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
295{
296 rcu_read_unlock();
297}
298
b60503ba 299/**
714a7a22 300 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 301 * @nvmeq: The queue to use
302 * @cmd: The command to send
303 *
304 * Safe to use from interrupt context
305 */
306static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
307{
308 unsigned long flags;
309 u16 tail;
b60503ba 310 spin_lock_irqsave(&nvmeq->q_lock, flags);
4f5099af
KB		 311 if (nvmeq->q_suspended) {
312 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
313 return -EBUSY;
314 }
b60503ba
MW		 315 tail = nvmeq->sq_tail;
316 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 317 if (++tail == nvmeq->q_depth)
318 tail = 0;
7547881d 319 writel(tail, nvmeq->q_db);
b60503ba
MW		 320 nvmeq->sq_tail = tail;
321 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
322
323 return 0;
324}
325
eca18b23 326static __le64 **iod_list(struct nvme_iod *iod)
e025344c 327{
eca18b23 328 return ((void *)iod) + iod->offset;
e025344c
SMM		 329}
330
eca18b23
MW		 331/*
332 * Will slightly overestimate the number of pages needed. This is OK
333 * as it only leads to a small amount of wasted memory for the lifetime of
334 * the I/O.
335 */
336static int nvme_npages(unsigned size)
337{
338 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
339 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
340}
b60503ba 341
eca18b23
MW		 342static struct nvme_iod *
343nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
b60503ba 344{
eca18b23
MW		 345 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
346 sizeof(__le64 *) * nvme_npages(nbytes) +
347 sizeof(struct scatterlist) * nseg, gfp);
348
349 if (iod) {
350 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
351 iod->npages = -1;
352 iod->length = nbytes;
2b196034 353 iod->nents = 0;
6198221f 354 iod->start_time = jiffies;
eca18b23
MW		 355 }
356
357 return iod;
b60503ba
MW		 358}
359
5d0f6131 360void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 361{
eca18b23
MW		 362 const int last_prp = PAGE_SIZE / 8 - 1;
363 int i;
364 __le64 **list = iod_list(iod);
365 dma_addr_t prp_dma = iod->first_dma;
366
367 if (iod->npages == 0)
368 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
369 for (i = 0; i < iod->npages; i++) {
370 __le64 *prp_list = list[i];
371 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
372 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
373 prp_dma = next_prp_dma;
374 }
375 kfree(iod);
b60503ba
MW		 376}
377
6198221f
KB		 378static void nvme_start_io_acct(struct bio *bio)
379{
380 struct gendisk *disk = bio->bi_bdev->bd_disk;
381 const int rw = bio_data_dir(bio);
382 int cpu = part_stat_lock();
383 part_round_stats(cpu, &disk->part0);
384 part_stat_inc(cpu, &disk->part0, ios[rw]);
385 part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio));
386 part_inc_in_flight(&disk->part0, rw);
387 part_stat_unlock();
388}
389
390static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
391{
392 struct gendisk *disk = bio->bi_bdev->bd_disk;
393 const int rw = bio_data_dir(bio);
394 unsigned long duration = jiffies - start_time;
395 int cpu = part_stat_lock();
396 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
397 part_round_stats(cpu, &disk->part0);
398 part_dec_in_flight(&disk->part0, rw);
399 part_stat_unlock();
400}
401
5c1281a3 402static void bio_completion(struct nvme_dev *dev, void *ctx,
b60503ba
MW		 403 struct nvme_completion *cqe)
404{
eca18b23
MW		 405 struct nvme_iod *iod = ctx;
406 struct bio *bio = iod->private;
b60503ba
MW		 407 u16 status = le16_to_cpup(&cqe->status) >> 1;
408
9e59d091 409 if (iod->nents) {
2b196034 410 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
b60503ba 411 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9e59d091
KB		 412 nvme_end_io_acct(bio, iod->start_time);
413 }
eca18b23 414 nvme_free_iod(dev, iod);
427e9708 415 if (status)
1ad2f893 416 bio_endio(bio, -EIO);
427e9708 417 else
1ad2f893 418 bio_endio(bio, 0);
b60503ba
MW		 419}
420
184d2944 421/* length is in bytes. gfp flags indicates whether we may sleep. */
5d0f6131
VV		 422int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd,
423 struct nvme_iod *iod, int total_len, gfp_t gfp)
ff22b54f 424{
99802a7a 425 struct dma_pool *pool;
eca18b23
MW		 426 int length = total_len;
427 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 428 int dma_len = sg_dma_len(sg);
429 u64 dma_addr = sg_dma_address(sg);
430 int offset = offset_in_page(dma_addr);
e025344c 431 __le64 *prp_list;
eca18b23 432 __le64 **list = iod_list(iod);
e025344c 433 dma_addr_t prp_dma;
eca18b23 434 int nprps, i;
ff22b54f
MW		 435
436 cmd->prp1 = cpu_to_le64(dma_addr);
437 length -= (PAGE_SIZE - offset);
438 if (length <= 0)
eca18b23 439 return total_len;
ff22b54f
MW		 440
441 dma_len -= (PAGE_SIZE - offset);
442 if (dma_len) {
443 dma_addr += (PAGE_SIZE - offset);
444 } else {
445 sg = sg_next(sg);
446 dma_addr = sg_dma_address(sg);
447 dma_len = sg_dma_len(sg);
448 }
449
450 if (length <= PAGE_SIZE) {
451 cmd->prp2 = cpu_to_le64(dma_addr);
eca18b23 452 return total_len;
e025344c
SMM		 453 }
454
455 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
99802a7a
MW		 456 if (nprps <= (256 / 8)) {
457 pool = dev->prp_small_pool;
eca18b23 458 iod->npages = 0;
99802a7a
MW		 459 } else {
460 pool = dev->prp_page_pool;
eca18b23 461 iod->npages = 1;
99802a7a
MW		 462 }
463
b77954cb
MW		 464 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
465 if (!prp_list) {
466 cmd->prp2 = cpu_to_le64(dma_addr);
eca18b23
MW		 467 iod->npages = -1;
468 return (total_len - length) + PAGE_SIZE;
b77954cb 469 }
eca18b23
MW		 470 list[0] = prp_list;
471 iod->first_dma = prp_dma;
e025344c
SMM		 472 cmd->prp2 = cpu_to_le64(prp_dma);
473 i = 0;
474 for (;;) {
7523d834 475 if (i == PAGE_SIZE / 8) {
e025344c 476 __le64 *old_prp_list = prp_list;
b77954cb 477 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 478 if (!prp_list)
479 return total_len - length;
480 list[iod->npages++] = prp_list;
7523d834
MW		 481 prp_list[0] = old_prp_list[i - 1];
482 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
483 i = 1;
e025344c
SMM		 484 }
485 prp_list[i++] = cpu_to_le64(dma_addr);
486 dma_len -= PAGE_SIZE;
487 dma_addr += PAGE_SIZE;
488 length -= PAGE_SIZE;
489 if (length <= 0)
490 break;
491 if (dma_len > 0)
492 continue;
493 BUG_ON(dma_len < 0);
494 sg = sg_next(sg);
495 dma_addr = sg_dma_address(sg);
496 dma_len = sg_dma_len(sg);
ff22b54f
MW		 497 }
498
eca18b23 499 return total_len;
ff22b54f
MW		 500}
501
427e9708 502static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
20d0189b 503 int len)
427e9708 504{
20d0189b
KO		 505 struct bio *split = bio_split(bio, len >> 9, GFP_ATOMIC, NULL);
506 if (!split)
427e9708
KB		 507 return -ENOMEM;
508
20d0189b
KO		 509 bio_chain(split, bio);
510
427e9708
KB		 511 if (bio_list_empty(&nvmeq->sq_cong))
512 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
20d0189b
KO		 513 bio_list_add(&nvmeq->sq_cong, split);
514 bio_list_add(&nvmeq->sq_cong, bio);
427e9708
KB		 515
516 return 0;
517}
518
1ad2f893
MW		 519/* NVMe scatterlists require no holes in the virtual address */
520#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
521 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
522
427e9708 523static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
b60503ba
MW		 524 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
525{
7988613b
KO		 526 struct bio_vec bvec, bvprv;
527 struct bvec_iter iter;
76830840 528 struct scatterlist *sg = NULL;
7988613b
KO		 529 int length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size;
530 int first = 1;
159b67d7
KB		 531
532 if (nvmeq->dev->stripe_size)
533 split_len = nvmeq->dev->stripe_size -
4f024f37
KO		 534 ((bio->bi_iter.bi_sector << 9) &
535 (nvmeq->dev->stripe_size - 1));
b60503ba 536
eca18b23 537 sg_init_table(iod->sg, psegs);
7988613b
KO		 538 bio_for_each_segment(bvec, bio, iter) {
539 if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) {
540 sg->length += bvec.bv_len;
76830840 541 } else {
7988613b
KO		 542 if (!first && BIOVEC_NOT_VIRT_MERGEABLE(&bvprv, &bvec))
543 return nvme_split_and_submit(bio, nvmeq,
20d0189b 544 length);
427e9708 545
eca18b23 546 sg = sg ? sg + 1 : iod->sg;
7988613b
KO		 547 sg_set_page(sg, bvec.bv_page,
548 bvec.bv_len, bvec.bv_offset);
76830840
MW		 549 nsegs++;
550 }
159b67d7 551
7988613b 552 if (split_len - length < bvec.bv_len)
20d0189b 553 return nvme_split_and_submit(bio, nvmeq, split_len);
7988613b 554 length += bvec.bv_len;
76830840 555 bvprv = bvec;
7988613b 556 first = 0;
b60503ba 557 }
eca18b23 558 iod->nents = nsegs;
76830840 559 sg_mark_end(sg);
427e9708 560 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
1ad2f893 561 return -ENOMEM;
427e9708 562
4f024f37 563 BUG_ON(length != bio->bi_iter.bi_size);
1ad2f893 564 return length;
b60503ba
MW		 565}
566
0e5e4f0e
KB		 567/*
568 * We reuse the small pool to allocate the 16-byte range here as it is not
569 * worth having a special pool for these or additional cases to handle freeing
570 * the iod.
571 */
572static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
573 struct bio *bio, struct nvme_iod *iod, int cmdid)
574{
575 struct nvme_dsm_range *range;
576 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
577
578 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
579 &iod->first_dma);
580 if (!range)
581 return -ENOMEM;
582
583 iod_list(iod)[0] = (__le64 *)range;
584 iod->npages = 0;
585
586 range->cattr = cpu_to_le32(0);
4f024f37
KO		 587 range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift);
588 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
0e5e4f0e
KB		 589
590 memset(cmnd, 0, sizeof(*cmnd));
591 cmnd->dsm.opcode = nvme_cmd_dsm;
592 cmnd->dsm.command_id = cmdid;
593 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
594 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
595 cmnd->dsm.nr = 0;
596 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
597
598 if (++nvmeq->sq_tail == nvmeq->q_depth)
599 nvmeq->sq_tail = 0;
600 writel(nvmeq->sq_tail, nvmeq->q_db);
601
602 return 0;
603}
604
00df5cb4
MW		 605static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
606 int cmdid)
607{
608 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
609
610 memset(cmnd, 0, sizeof(*cmnd));
611 cmnd->common.opcode = nvme_cmd_flush;
612 cmnd->common.command_id = cmdid;
613 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
614
615 if (++nvmeq->sq_tail == nvmeq->q_depth)
616 nvmeq->sq_tail = 0;
617 writel(nvmeq->sq_tail, nvmeq->q_db);
618
619 return 0;
620}
621
5d0f6131 622int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
00df5cb4
MW		 623{
624 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
ff976d72 625 special_completion, NVME_IO_TIMEOUT);
00df5cb4
MW		 626 if (unlikely(cmdid < 0))
627 return cmdid;
628
629 return nvme_submit_flush(nvmeq, ns, cmdid);
630}
631
184d2944
MW		 632/*
633 * Called with local interrupts disabled and the q_lock held. May not sleep.
634 */
b60503ba
MW		 635static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
636 struct bio *bio)
637{
ff22b54f 638 struct nvme_command *cmnd;
eca18b23 639 struct nvme_iod *iod;
b60503ba 640 enum dma_data_direction dma_dir;
1287dabd 641 int cmdid, length, result;
b60503ba
MW		 642 u16 control;
643 u32 dsmgmt;
b60503ba
MW		 644 int psegs = bio_phys_segments(ns->queue, bio);
645
00df5cb4
MW		 646 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
647 result = nvme_submit_flush_data(nvmeq, ns);
648 if (result)
649 return result;
650 }
651
1287dabd 652 result = -ENOMEM;
4f024f37 653 iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, GFP_ATOMIC);
eca18b23 654 if (!iod)
eeee3226 655 goto nomem;
eca18b23 656 iod->private = bio;
b60503ba 657
eeee3226 658 result = -EBUSY;
ff976d72 659 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 660 if (unlikely(cmdid < 0))
eca18b23 661 goto free_iod;
b60503ba 662
0e5e4f0e
KB		 663 if (bio->bi_rw & REQ_DISCARD) {
664 result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
665 if (result)
666 goto free_cmdid;
667 return result;
668 }
00df5cb4
MW		 669 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
670 return nvme_submit_flush(nvmeq, ns, cmdid);
671
b60503ba
MW		 672 control = 0;
673 if (bio->bi_rw & REQ_FUA)
674 control |= NVME_RW_FUA;
675 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
676 control |= NVME_RW_LR;
677
678 dsmgmt = 0;
679 if (bio->bi_rw & REQ_RAHEAD)
680 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
681
ff22b54f 682 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b60503ba 683
b8deb62c 684 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 685 if (bio_data_dir(bio)) {
ff22b54f 686 cmnd->rw.opcode = nvme_cmd_write;
b60503ba
MW		 687 dma_dir = DMA_TO_DEVICE;
688 } else {
ff22b54f 689 cmnd->rw.opcode = nvme_cmd_read;
b60503ba
MW		 690 dma_dir = DMA_FROM_DEVICE;
691 }
692
427e9708
KB		 693 result = nvme_map_bio(nvmeq, iod, bio, dma_dir, psegs);
694 if (result <= 0)
859361a2 695 goto free_cmdid;
1ad2f893 696 length = result;
b60503ba 697
ff22b54f
MW		 698 cmnd->rw.command_id = cmdid;
699 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
eca18b23
MW		 700 length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
701 GFP_ATOMIC);
4f024f37 702 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
1ad2f893 703 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
ff22b54f
MW		 704 cmnd->rw.control = cpu_to_le16(control);
705 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 706
6198221f 707 nvme_start_io_acct(bio);
b60503ba
MW		 708 if (++nvmeq->sq_tail == nvmeq->q_depth)
709 nvmeq->sq_tail = 0;
7547881d 710 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 711
1974b1ae
MW		 712 return 0;
713
859361a2
KB		 714 free_cmdid:
715 free_cmdid(nvmeq, cmdid, NULL);
eca18b23
MW		 716 free_iod:
717 nvme_free_iod(nvmeq->dev, iod);
eeee3226
MW		 718 nomem:
719 return result;
b60503ba
MW		 720}
721
e9539f47 722static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 723{
82123460 724 u16 head, phase;
b60503ba 725
b60503ba 726 head = nvmeq->cq_head;
82123460 727 phase = nvmeq->cq_phase;
b60503ba
MW		 728
729 for (;;) {
c2f5b650
MW		 730 void *ctx;
731 nvme_completion_fn fn;
b60503ba 732 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 733 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 734 break;
735 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
736 if (++head == nvmeq->q_depth) {
737 head = 0;
82123460 738 phase = !phase;
b60503ba
MW		 739 }
740
c2f5b650 741 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
5c1281a3 742 fn(nvmeq->dev, ctx, &cqe);
b60503ba
MW		 743 }
744
745 /* If the controller ignores the cq head doorbell and continuously
746 * writes to the queue, it is theoretically possible to wrap around
747 * the queue twice and mistakenly return IRQ_NONE. Linux only
748 * requires that 0.1% of your interrupts are handled, so this isn't
749 * a big problem.
750 */
82123460 751 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 752 return 0;
b60503ba 753
b80d5ccc 754 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 755 nvmeq->cq_head = head;
82123460 756 nvmeq->cq_phase = phase;
b60503ba 757
e9539f47
MW		 758 nvmeq->cqe_seen = 1;
759 return 1;
b60503ba
MW		 760}
761
7d822457
MW		 762static void nvme_make_request(struct request_queue *q, struct bio *bio)
763{
764 struct nvme_ns *ns = q->queuedata;
765 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
766 int result = -EBUSY;
767
cd638946
KB		 768 if (!nvmeq) {
769 put_nvmeq(NULL);
770 bio_endio(bio, -EIO);
771 return;
772 }
773
7d822457 774 spin_lock_irq(&nvmeq->q_lock);
22404274 775 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
7d822457
MW		 776 result = nvme_submit_bio_queue(nvmeq, ns, bio);
777 if (unlikely(result)) {
778 if (bio_list_empty(&nvmeq->sq_cong))
779 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
780 bio_list_add(&nvmeq->sq_cong, bio);
781 }
782
783 nvme_process_cq(nvmeq);
784 spin_unlock_irq(&nvmeq->q_lock);
785 put_nvmeq(nvmeq);
786}
787
b60503ba 788static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 789{
790 irqreturn_t result;
791 struct nvme_queue *nvmeq = data;
792 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 793 nvme_process_cq(nvmeq);
794 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
795 nvmeq->cqe_seen = 0;
58ffacb5
MW		 796 spin_unlock(&nvmeq->q_lock);
797 return result;
798}
799
800static irqreturn_t nvme_irq_check(int irq, void *data)
801{
802 struct nvme_queue *nvmeq = data;
803 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
804 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
805 return IRQ_NONE;
806 return IRQ_WAKE_THREAD;
807}
808
3c0cf138
MW		 809static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
810{
811 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 812 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW		 813 spin_unlock_irq(&nvmeq->q_lock);
814}
815
c2f5b650
MW		 816struct sync_cmd_info {
817 struct task_struct *task;
818 u32 result;
819 int status;
820};
821
5c1281a3 822static void sync_completion(struct nvme_dev *dev, void *ctx,
c2f5b650
MW		 823 struct nvme_completion *cqe)
824{
825 struct sync_cmd_info *cmdinfo = ctx;
826 cmdinfo->result = le32_to_cpup(&cqe->result);
827 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
828 wake_up_process(cmdinfo->task);
829}
830
b60503ba
MW		 831/*
832 * Returns 0 on success. If the result is negative, it's a Linux error code;
833 * if the result is positive, it's an NVM Express status code
834 */
4f5099af
KB		 835static int nvme_submit_sync_cmd(struct nvme_dev *dev, int q_idx,
836 struct nvme_command *cmd,
5d0f6131 837 u32 *result, unsigned timeout)
b60503ba 838{
4f5099af 839 int cmdid, ret;
b60503ba 840 struct sync_cmd_info cmdinfo;
4f5099af
KB		 841 struct nvme_queue *nvmeq;
842
843 nvmeq = lock_nvmeq(dev, q_idx);
844 if (!nvmeq) {
845 unlock_nvmeq(nvmeq);
846 return -ENODEV;
847 }
b60503ba
MW		 848
849 cmdinfo.task = current;
850 cmdinfo.status = -EINTR;
851
4f5099af
KB		 852 cmdid = alloc_cmdid(nvmeq, &cmdinfo, sync_completion, timeout);
853 if (cmdid < 0) {
854 unlock_nvmeq(nvmeq);
b60503ba 855 return cmdid;
4f5099af 856 }
b60503ba
MW		 857 cmd->common.command_id = cmdid;
858
3c0cf138 859 set_current_state(TASK_KILLABLE);
4f5099af
KB		 860 ret = nvme_submit_cmd(nvmeq, cmd);
861 if (ret) {
862 free_cmdid(nvmeq, cmdid, NULL);
863 unlock_nvmeq(nvmeq);
864 set_current_state(TASK_RUNNING);
865 return ret;
866 }
867 unlock_nvmeq(nvmeq);
78f8d257 868 schedule_timeout(timeout);
b60503ba 869
3c0cf138 870 if (cmdinfo.status == -EINTR) {
4f5099af
KB		 871 nvmeq = lock_nvmeq(dev, q_idx);
872 if (nvmeq)
873 nvme_abort_command(nvmeq, cmdid);
874 unlock_nvmeq(nvmeq);
3c0cf138
MW		 875 return -EINTR;
876 }
877
b60503ba
MW		 878 if (result)
879 *result = cmdinfo.result;
880
881 return cmdinfo.status;
882}
883
4d115420
KB		 884static int nvme_submit_async_cmd(struct nvme_queue *nvmeq,
885 struct nvme_command *cmd,
886 struct async_cmd_info *cmdinfo, unsigned timeout)
887{
888 int cmdid;
889
890 cmdid = alloc_cmdid_killable(nvmeq, cmdinfo, async_completion, timeout);
891 if (cmdid < 0)
892 return cmdid;
893 cmdinfo->status = -EINTR;
894 cmd->common.command_id = cmdid;
4f5099af 895 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 896}
897
5d0f6131 898int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
b60503ba
MW		 899 u32 *result)
900{
4f5099af
KB		 901 return nvme_submit_sync_cmd(dev, 0, cmd, result, ADMIN_TIMEOUT);
902}
903
904int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
905 u32 *result)
906{
907 return nvme_submit_sync_cmd(dev, smp_processor_id() + 1, cmd, result,
908 NVME_IO_TIMEOUT);
b60503ba
MW		 909}
910
4d115420
KB		 911static int nvme_submit_admin_cmd_async(struct nvme_dev *dev,
912 struct nvme_command *cmd, struct async_cmd_info *cmdinfo)
913{
5a92e700 914 return nvme_submit_async_cmd(raw_nvmeq(dev, 0), cmd, cmdinfo,
4d115420
KB		 915 ADMIN_TIMEOUT);
916}
917
b60503ba
MW		 918static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
919{
920 int status;
921 struct nvme_command c;
922
923 memset(&c, 0, sizeof(c));
924 c.delete_queue.opcode = opcode;
925 c.delete_queue.qid = cpu_to_le16(id);
926
927 status = nvme_submit_admin_cmd(dev, &c, NULL);
928 if (status)
929 return -EIO;
930 return 0;
931}
932
933static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
934 struct nvme_queue *nvmeq)
935{
936 int status;
937 struct nvme_command c;
938 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
939
940 memset(&c, 0, sizeof(c));
941 c.create_cq.opcode = nvme_admin_create_cq;
942 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
943 c.create_cq.cqid = cpu_to_le16(qid);
944 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
945 c.create_cq.cq_flags = cpu_to_le16(flags);
946 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
947
948 status = nvme_submit_admin_cmd(dev, &c, NULL);
949 if (status)
950 return -EIO;
951 return 0;
952}
953
954static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
955 struct nvme_queue *nvmeq)
956{
957 int status;
958 struct nvme_command c;
959 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
960
961 memset(&c, 0, sizeof(c));
962 c.create_sq.opcode = nvme_admin_create_sq;
963 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
964 c.create_sq.sqid = cpu_to_le16(qid);
965 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
966 c.create_sq.sq_flags = cpu_to_le16(flags);
967 c.create_sq.cqid = cpu_to_le16(qid);
968
969 status = nvme_submit_admin_cmd(dev, &c, NULL);
970 if (status)
971 return -EIO;
972 return 0;
973}
974
975static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
976{
977 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
978}
979
980static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
981{
982 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
983}
984
5d0f6131 985int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 986 dma_addr_t dma_addr)
987{
988 struct nvme_command c;
989
990 memset(&c, 0, sizeof(c));
991 c.identify.opcode = nvme_admin_identify;
992 c.identify.nsid = cpu_to_le32(nsid);
993 c.identify.prp1 = cpu_to_le64(dma_addr);
994 c.identify.cns = cpu_to_le32(cns);
995
996 return nvme_submit_admin_cmd(dev, &c, NULL);
997}
998
5d0f6131 999int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1000 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1001{
1002 struct nvme_command c;
1003
1004 memset(&c, 0, sizeof(c));
1005 c.features.opcode = nvme_admin_get_features;
a42cecce 1006 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1007 c.features.prp1 = cpu_to_le64(dma_addr);
1008 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1009
08df1e05 1010 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 1011}
1012
5d0f6131
VV		 1013int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1014 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1015{
1016 struct nvme_command c;
1017
1018 memset(&c, 0, sizeof(c));
1019 c.features.opcode = nvme_admin_set_features;
1020 c.features.prp1 = cpu_to_le64(dma_addr);
1021 c.features.fid = cpu_to_le32(fid);
1022 c.features.dword11 = cpu_to_le32(dword11);
1023
bc5fc7e4
MW		 1024 return nvme_submit_admin_cmd(dev, &c, result);
1025}
1026
c30341dc
KB		 1027/**
1028 * nvme_abort_cmd - Attempt aborting a command
1029 * @cmdid: Command id of a timed out IO
1030 * @queue: The queue with timed out IO
1031 *
1032 * Schedule controller reset if the command was already aborted once before and
1033 * still hasn't been returned to the driver, or if this is the admin queue.
1034 */
1035static void nvme_abort_cmd(int cmdid, struct nvme_queue *nvmeq)
1036{
1037 int a_cmdid;
1038 struct nvme_command cmd;
1039 struct nvme_dev *dev = nvmeq->dev;
1040 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
5a92e700 1041 struct nvme_queue *adminq;
c30341dc
KB		 1042
1043 if (!nvmeq->qid || info[cmdid].aborted) {
1044 if (work_busy(&dev->reset_work))
1045 return;
1046 list_del_init(&dev->node);
1047 dev_warn(&dev->pci_dev->dev,
1048 "I/O %d QID %d timeout, reset controller\n", cmdid,
1049 nvmeq->qid);
bdfd70fd 1050 PREPARE_WORK(&dev->reset_work, nvme_reset_failed_dev);
c30341dc
KB		 1051 queue_work(nvme_workq, &dev->reset_work);
1052 return;
1053 }
1054
1055 if (!dev->abort_limit)
1056 return;
1057
5a92e700
KB		 1058 adminq = rcu_dereference(dev->queues[0]);
1059 a_cmdid = alloc_cmdid(adminq, CMD_CTX_ABORT, special_completion,
c30341dc
KB		 1060 ADMIN_TIMEOUT);
1061 if (a_cmdid < 0)
1062 return;
1063
1064 memset(&cmd, 0, sizeof(cmd));
1065 cmd.abort.opcode = nvme_admin_abort_cmd;
1066 cmd.abort.cid = cmdid;
1067 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1068 cmd.abort.command_id = a_cmdid;
1069
1070 --dev->abort_limit;
1071 info[cmdid].aborted = 1;
1072 info[cmdid].timeout = jiffies + ADMIN_TIMEOUT;
1073
1074 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", cmdid,
1075 nvmeq->qid);
5a92e700 1076 nvme_submit_cmd(adminq, &cmd);
c30341dc
KB		 1077}
1078
a09115b2
MW		 1079/**
1080 * nvme_cancel_ios - Cancel outstanding I/Os
1081 * @queue: The queue to cancel I/Os on
1082 * @timeout: True to only cancel I/Os which have timed out
1083 */
1084static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1085{
1086 int depth = nvmeq->q_depth - 1;
1087 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1088 unsigned long now = jiffies;
1089 int cmdid;
1090
1091 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1092 void *ctx;
1093 nvme_completion_fn fn;
1094 static struct nvme_completion cqe = {
af2d9ca7 1095 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
a09115b2
MW		 1096 };
1097
1098 if (timeout && !time_after(now, info[cmdid].timeout))
1099 continue;
053ab702
KB		 1100 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1101 continue;
c30341dc
KB		 1102 if (timeout && nvmeq->dev->initialized) {
1103 nvme_abort_cmd(cmdid, nvmeq);
1104 continue;
1105 }
1106 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", cmdid,
1107 nvmeq->qid);
a09115b2
MW		 1108 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
1109 fn(nvmeq->dev, ctx, &cqe);
1110 }
1111}
1112
5a92e700 1113static void nvme_free_queue(struct rcu_head *r)
9e866774 1114{
5a92e700
KB		 1115 struct nvme_queue *nvmeq = container_of(r, struct nvme_queue, r_head);
1116
22404274
KB		 1117 spin_lock_irq(&nvmeq->q_lock);
1118 while (bio_list_peek(&nvmeq->sq_cong)) {
1119 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1120 bio_endio(bio, -EIO);
1121 }
1122 spin_unlock_irq(&nvmeq->q_lock);
1123
9e866774
MW		 1124 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1125 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1126 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1127 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
42f61420
KB		 1128 if (nvmeq->qid)
1129 free_cpumask_var(nvmeq->cpu_mask);
9e866774
MW		 1130 kfree(nvmeq);
1131}
1132
a1a5ef99 1133static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1134{
1135 int i;
1136
a1a5ef99 1137 for (i = dev->queue_count - 1; i >= lowest; i--) {
5a92e700
KB		 1138 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
1139 rcu_assign_pointer(dev->queues[i], NULL);
1140 call_rcu(&nvmeq->r_head, nvme_free_queue);
22404274 1141 dev->queue_count--;
22404274
KB		 1142 }
1143}
1144
4d115420
KB		 1145/**
1146 * nvme_suspend_queue - put queue into suspended state
1147 * @nvmeq - queue to suspend
1148 *
1149 * Returns 1 if already suspended, 0 otherwise.
1150 */
1151static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1152{
4d115420 1153 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1154
a09115b2 1155 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1156 if (nvmeq->q_suspended) {
1157 spin_unlock_irq(&nvmeq->q_lock);
4d115420 1158 return 1;
3295874b 1159 }
22404274 1160 nvmeq->q_suspended = 1;
42f61420 1161 nvmeq->dev->online_queues--;
a09115b2
MW		 1162 spin_unlock_irq(&nvmeq->q_lock);
1163
aba2080f
MW		 1164 irq_set_affinity_hint(vector, NULL);
1165 free_irq(vector, nvmeq);
b60503ba 1166
4d115420
KB		 1167 return 0;
1168}
b60503ba 1169
4d115420
KB		 1170static void nvme_clear_queue(struct nvme_queue *nvmeq)
1171{
22404274
KB		 1172 spin_lock_irq(&nvmeq->q_lock);
1173 nvme_process_cq(nvmeq);
1174 nvme_cancel_ios(nvmeq, false);
1175 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1176}
1177
4d115420
KB		 1178static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1179{
5a92e700 1180 struct nvme_queue *nvmeq = raw_nvmeq(dev, qid);
4d115420
KB		 1181
1182 if (!nvmeq)
1183 return;
1184 if (nvme_suspend_queue(nvmeq))
1185 return;
1186
0e53d180
KB		 1187 /* Don't tell the adapter to delete the admin queue.
1188 * Don't tell a removed adapter to delete IO queues. */
1189 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1190 adapter_delete_sq(dev, qid);
1191 adapter_delete_cq(dev, qid);
1192 }
4d115420 1193 nvme_clear_queue(nvmeq);
b60503ba
MW		 1194}
1195
1196static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1197 int depth, int vector)
1198{
1199 struct device *dmadev = &dev->pci_dev->dev;
22404274 1200 unsigned extra = nvme_queue_extra(depth);
b60503ba
MW		 1201 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1202 if (!nvmeq)
1203 return NULL;
1204
1205 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1206 &nvmeq->cq_dma_addr, GFP_KERNEL);
1207 if (!nvmeq->cqes)
1208 goto free_nvmeq;
1209 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1210
1211 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1212 &nvmeq->sq_dma_addr, GFP_KERNEL);
1213 if (!nvmeq->sq_cmds)
1214 goto free_cqdma;
1215
42f61420
KB		 1216 if (qid && !zalloc_cpumask_var(&nvmeq->cpu_mask, GFP_KERNEL))
1217 goto free_sqdma;
1218
b60503ba 1219 nvmeq->q_dmadev = dmadev;
091b6092 1220 nvmeq->dev = dev;
3193f07b
MW		 1221 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1222 dev->instance, qid);
b60503ba
MW		 1223 spin_lock_init(&nvmeq->q_lock);
1224 nvmeq->cq_head = 0;
82123460 1225 nvmeq->cq_phase = 1;
b60503ba 1226 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1227 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1228 bio_list_init(&nvmeq->sq_cong);
b80d5ccc 1229 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW		 1230 nvmeq->q_depth = depth;
1231 nvmeq->cq_vector = vector;
c30341dc 1232 nvmeq->qid = qid;
22404274
KB		 1233 nvmeq->q_suspended = 1;
1234 dev->queue_count++;
5a92e700 1235 rcu_assign_pointer(dev->queues[qid], nvmeq);
b60503ba
MW		 1236
1237 return nvmeq;
1238
42f61420
KB		 1239 free_sqdma:
1240 dma_free_coherent(dmadev, SQ_SIZE(depth), (void *)nvmeq->sq_cmds,
1241 nvmeq->sq_dma_addr);
b60503ba 1242 free_cqdma:
68b8eca5 1243 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1244 nvmeq->cq_dma_addr);
1245 free_nvmeq:
1246 kfree(nvmeq);
1247 return NULL;
1248}
1249
3001082c
MW		 1250static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1251 const char *name)
1252{
58ffacb5
MW		 1253 if (use_threaded_interrupts)
1254 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1255 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1256 name, nvmeq);
3001082c 1257 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1258 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1259}
1260
22404274 1261static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1262{
22404274
KB		 1263 struct nvme_dev *dev = nvmeq->dev;
1264 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
b60503ba 1265
22404274
KB		 1266 nvmeq->sq_tail = 0;
1267 nvmeq->cq_head = 0;
1268 nvmeq->cq_phase = 1;
b80d5ccc 1269 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274
KB		 1270 memset(nvmeq->cmdid_data, 0, extra);
1271 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1272 nvme_cancel_ios(nvmeq, false);
1273 nvmeq->q_suspended = 0;
42f61420 1274 dev->online_queues++;
22404274
KB		 1275}
1276
1277static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1278{
1279 struct nvme_dev *dev = nvmeq->dev;
1280 int result;
3f85d50b 1281
b60503ba
MW		 1282 result = adapter_alloc_cq(dev, qid, nvmeq);
1283 if (result < 0)
22404274 1284 return result;
b60503ba
MW		 1285
1286 result = adapter_alloc_sq(dev, qid, nvmeq);
1287 if (result < 0)
1288 goto release_cq;
1289
3193f07b 1290 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1291 if (result < 0)
1292 goto release_sq;
1293
0a8d44cb 1294 spin_lock_irq(&nvmeq->q_lock);
22404274 1295 nvme_init_queue(nvmeq, qid);
0a8d44cb 1296 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1297
1298 return result;
b60503ba
MW		 1299
1300 release_sq:
1301 adapter_delete_sq(dev, qid);
1302 release_cq:
1303 adapter_delete_cq(dev, qid);
22404274 1304 return result;
b60503ba
MW		 1305}
1306
ba47e386
MW		 1307static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1308{
1309 unsigned long timeout;
1310 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1311
1312 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1313
1314 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1315 msleep(100);
1316 if (fatal_signal_pending(current))
1317 return -EINTR;
1318 if (time_after(jiffies, timeout)) {
1319 dev_err(&dev->pci_dev->dev,
1320 "Device not ready; aborting initialisation\n");
1321 return -ENODEV;
1322 }
1323 }
1324
1325 return 0;
1326}
1327
1328/*
1329 * If the device has been passed off to us in an enabled state, just clear
1330 * the enabled bit. The spec says we should set the 'shutdown notification
1331 * bits', but doing so may cause the device to complete commands to the
1332 * admin queue ... and we don't know what memory that might be pointing at!
1333 */
1334static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1335{
44af146a
MW		 1336 u32 cc = readl(&dev->bar->cc);
1337
1338 if (cc & NVME_CC_ENABLE)
1339 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
ba47e386
MW		 1340 return nvme_wait_ready(dev, cap, false);
1341}
1342
1343static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1344{
1345 return nvme_wait_ready(dev, cap, true);
1346}
1347
1894d8f1
KB		 1348static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1349{
1350 unsigned long timeout;
1351 u32 cc;
1352
1353 cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
1354 writel(cc, &dev->bar->cc);
1355
1356 timeout = 2 * HZ + jiffies;
1357 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1358 NVME_CSTS_SHST_CMPLT) {
1359 msleep(100);
1360 if (fatal_signal_pending(current))
1361 return -EINTR;
1362 if (time_after(jiffies, timeout)) {
1363 dev_err(&dev->pci_dev->dev,
1364 "Device shutdown incomplete; abort shutdown\n");
1365 return -ENODEV;
1366 }
1367 }
1368
1369 return 0;
1370}
1371
8d85fce7 1372static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1373{
ba47e386 1374 int result;
b60503ba 1375 u32 aqa;
ba47e386 1376 u64 cap = readq(&dev->bar->cap);
b60503ba
MW		 1377 struct nvme_queue *nvmeq;
1378
ba47e386
MW		 1379 result = nvme_disable_ctrl(dev, cap);
1380 if (result < 0)
1381 return result;
b60503ba 1382
5a92e700 1383 nvmeq = raw_nvmeq(dev, 0);
cd638946
KB		 1384 if (!nvmeq) {
1385 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1386 if (!nvmeq)
1387 return -ENOMEM;
cd638946 1388 }
b60503ba
MW		 1389
1390 aqa = nvmeq->q_depth - 1;
1391 aqa |= aqa << 16;
1392
1393 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1394 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1395 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1396 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1397
1398 writel(aqa, &dev->bar->aqa);
1399 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1400 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1401 writel(dev->ctrl_config, &dev->bar->cc);
1402
ba47e386 1403 result = nvme_enable_ctrl(dev, cap);
025c557a 1404 if (result)
cd638946 1405 return result;
9e866774 1406
3193f07b 1407 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1408 if (result)
cd638946 1409 return result;
025c557a 1410
0a8d44cb 1411 spin_lock_irq(&nvmeq->q_lock);
22404274 1412 nvme_init_queue(nvmeq, 0);
0a8d44cb 1413 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1414 return result;
1415}
1416
5d0f6131 1417struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1418 unsigned long addr, unsigned length)
b60503ba 1419{
36c14ed9 1420 int i, err, count, nents, offset;
7fc3cdab
MW		 1421 struct scatterlist *sg;
1422 struct page **pages;
eca18b23 1423 struct nvme_iod *iod;
36c14ed9
MW		 1424
1425 if (addr & 3)
eca18b23 1426 return ERR_PTR(-EINVAL);
5460fc03 1427 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1428 return ERR_PTR(-EINVAL);
7fc3cdab 1429
36c14ed9 1430 offset = offset_in_page(addr);
7fc3cdab
MW		 1431 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1432 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1433 if (!pages)
1434 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1435
1436 err = get_user_pages_fast(addr, count, 1, pages);
1437 if (err < count) {
1438 count = err;
1439 err = -EFAULT;
1440 goto put_pages;
1441 }
7fc3cdab 1442
eca18b23
MW		 1443 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1444 sg = iod->sg;
36c14ed9 1445 sg_init_table(sg, count);
d0ba1e49
MW		 1446 for (i = 0; i < count; i++) {
1447 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1448 min_t(unsigned, length, PAGE_SIZE - offset),
1449 offset);
d0ba1e49
MW		 1450 length -= (PAGE_SIZE - offset);
1451 offset = 0;
7fc3cdab 1452 }
fe304c43 1453 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1454 iod->nents = count;
7fc3cdab
MW		 1455
1456 err = -ENOMEM;
1457 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1458 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1459 if (!nents)
eca18b23 1460 goto free_iod;
b60503ba 1461
7fc3cdab 1462 kfree(pages);
eca18b23 1463 return iod;
b60503ba 1464
eca18b23
MW		 1465 free_iod:
1466 kfree(iod);
7fc3cdab
MW		 1467 put_pages:
1468 for (i = 0; i < count; i++)
1469 put_page(pages[i]);
1470 kfree(pages);
eca18b23 1471 return ERR_PTR(err);
7fc3cdab 1472}
b60503ba 1473
5d0f6131 1474void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1475 struct nvme_iod *iod)
7fc3cdab 1476{
1c2ad9fa 1477 int i;
b60503ba 1478
1c2ad9fa
MW		 1479 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1480 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1481
1c2ad9fa
MW		 1482 for (i = 0; i < iod->nents; i++)
1483 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1484}
b60503ba 1485
a53295b6
MW		 1486static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1487{
1488 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1489 struct nvme_user_io io;
1490 struct nvme_command c;
f410c680
KB		 1491 unsigned length, meta_len;
1492 int status, i;
1493 struct nvme_iod *iod, *meta_iod = NULL;
1494 dma_addr_t meta_dma_addr;
1495 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1496
1497 if (copy_from_user(&io, uio, sizeof(io)))
1498 return -EFAULT;
6c7d4945 1499 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1500 meta_len = (io.nblocks + 1) * ns->ms;
1501
1502 if (meta_len && ((io.metadata & 3) || !io.metadata))
1503 return -EINVAL;
6c7d4945
MW		 1504
1505 switch (io.opcode) {
1506 case nvme_cmd_write:
1507 case nvme_cmd_read:
6bbf1acd 1508 case nvme_cmd_compare:
eca18b23 1509 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1510 break;
6c7d4945 1511 default:
6bbf1acd 1512 return -EINVAL;
6c7d4945
MW		 1513 }
1514
eca18b23
MW		 1515 if (IS_ERR(iod))
1516 return PTR_ERR(iod);
a53295b6
MW		 1517
1518 memset(&c, 0, sizeof(c));
1519 c.rw.opcode = io.opcode;
1520 c.rw.flags = io.flags;
6c7d4945 1521 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1522 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1523 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1524 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1525 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1526 c.rw.reftag = cpu_to_le32(io.reftag);
1527 c.rw.apptag = cpu_to_le16(io.apptag);
1528 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1529
1530 if (meta_len) {
1b56749e
KB		 1531 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1532 meta_len);
f410c680
KB		 1533 if (IS_ERR(meta_iod)) {
1534 status = PTR_ERR(meta_iod);
1535 meta_iod = NULL;
1536 goto unmap;
1537 }
1538
1539 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1540 &meta_dma_addr, GFP_KERNEL);
1541 if (!meta_mem) {
1542 status = -ENOMEM;
1543 goto unmap;
1544 }
1545
1546 if (io.opcode & 1) {
1547 int meta_offset = 0;
1548
1549 for (i = 0; i < meta_iod->nents; i++) {
1550 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1551 meta_iod->sg[i].offset;
1552 memcpy(meta_mem + meta_offset, meta,
1553 meta_iod->sg[i].length);
1554 kunmap_atomic(meta);
1555 meta_offset += meta_iod->sg[i].length;
1556 }
1557 }
1558
1559 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1560 }
1561
eca18b23 1562 length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
a53295b6 1563
b77954cb
MW		 1564 if (length != (io.nblocks + 1) << ns->lba_shift)
1565 status = -ENOMEM;
1566 else
4f5099af 1567 status = nvme_submit_io_cmd(dev, &c, NULL);
a53295b6 1568
f410c680
KB		 1569 if (meta_len) {
1570 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1571 int meta_offset = 0;
1572
1573 for (i = 0; i < meta_iod->nents; i++) {
1574 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1575 meta_iod->sg[i].offset;
1576 memcpy(meta, meta_mem + meta_offset,
1577 meta_iod->sg[i].length);
1578 kunmap_atomic(meta);
1579 meta_offset += meta_iod->sg[i].length;
1580 }
1581 }
1582
1583 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1584 meta_dma_addr);
1585 }
1586
1587 unmap:
1c2ad9fa 1588 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1589 nvme_free_iod(dev, iod);
f410c680
KB		 1590
1591 if (meta_iod) {
1592 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1593 nvme_free_iod(dev, meta_iod);
1594 }
1595
a53295b6
MW		 1596 return status;
1597}
1598
50af8bae 1599static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1600 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1601{
6bbf1acd 1602 struct nvme_admin_cmd cmd;
6ee44cdc 1603 struct nvme_command c;
eca18b23 1604 int status, length;
c7d36ab8 1605 struct nvme_iod *uninitialized_var(iod);
94f370ca 1606 unsigned timeout;
6ee44cdc 1607
6bbf1acd
MW		 1608 if (!capable(CAP_SYS_ADMIN))
1609 return -EACCES;
1610 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1611 return -EFAULT;
6ee44cdc
MW		 1612
1613 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1614 c.common.opcode = cmd.opcode;
1615 c.common.flags = cmd.flags;
1616 c.common.nsid = cpu_to_le32(cmd.nsid);
1617 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1618 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1619 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1620 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1621 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1622 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1623 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1624 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1625
1626 length = cmd.data_len;
1627 if (cmd.data_len) {
49742188
MW		 1628 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1629 length);
eca18b23
MW		 1630 if (IS_ERR(iod))
1631 return PTR_ERR(iod);
1632 length = nvme_setup_prps(dev, &c.common, iod, length,
1633 GFP_KERNEL);
6bbf1acd
MW		 1634 }
1635
94f370ca
KB		 1636 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1637 ADMIN_TIMEOUT;
6bbf1acd 1638 if (length != cmd.data_len)
b77954cb
MW		 1639 status = -ENOMEM;
1640 else
4f5099af 1641 status = nvme_submit_sync_cmd(dev, 0, &c, &cmd.result, timeout);
eca18b23 1642
6bbf1acd 1643 if (cmd.data_len) {
1c2ad9fa 1644 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1645 nvme_free_iod(dev, iod);
6bbf1acd 1646 }
f4f117f6 1647
cf90bc48 1648 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1649 sizeof(cmd.result)))
1650 status = -EFAULT;
1651
6ee44cdc
MW		 1652 return status;
1653}
1654
b60503ba
MW		 1655static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1656 unsigned long arg)
1657{
1658 struct nvme_ns *ns = bdev->bd_disk->private_data;
1659
1660 switch (cmd) {
6bbf1acd 1661 case NVME_IOCTL_ID:
c3bfe717 1662 force_successful_syscall_return();
6bbf1acd
MW		 1663 return ns->ns_id;
1664 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1665 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW		 1666 case NVME_IOCTL_SUBMIT_IO:
1667 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1668 case SG_GET_VERSION_NUM:
1669 return nvme_sg_get_version_num((void __user *)arg);
1670 case SG_IO:
1671 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1672 default:
1673 return -ENOTTY;
1674 }
1675}
1676
320a3827
KB		 1677#ifdef CONFIG_COMPAT
1678static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1679 unsigned int cmd, unsigned long arg)
1680{
1681 struct nvme_ns *ns = bdev->bd_disk->private_data;
1682
1683 switch (cmd) {
1684 case SG_IO:
1685 return nvme_sg_io32(ns, arg);
1686 }
1687 return nvme_ioctl(bdev, mode, cmd, arg);
1688}
1689#else
1690#define nvme_compat_ioctl NULL
1691#endif
1692
9ac27090
KB		 1693static int nvme_open(struct block_device *bdev, fmode_t mode)
1694{
1695 struct nvme_ns *ns = bdev->bd_disk->private_data;
1696 struct nvme_dev *dev = ns->dev;
1697
1698 kref_get(&dev->kref);
1699 return 0;
1700}
1701
1702static void nvme_free_dev(struct kref *kref);
1703
1704static void nvme_release(struct gendisk *disk, fmode_t mode)
1705{
1706 struct nvme_ns *ns = disk->private_data;
1707 struct nvme_dev *dev = ns->dev;
1708
1709 kref_put(&dev->kref, nvme_free_dev);
1710}
1711
b60503ba
MW		 1712static const struct block_device_operations nvme_fops = {
1713 .owner = THIS_MODULE,
1714 .ioctl = nvme_ioctl,
320a3827 1715 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1716 .open = nvme_open,
1717 .release = nvme_release,
b60503ba
MW		 1718};
1719
1fa6aead
MW		 1720static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1721{
1722 while (bio_list_peek(&nvmeq->sq_cong)) {
1723 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1724 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
427e9708
KB		 1725
1726 if (bio_list_empty(&nvmeq->sq_cong))
1727 remove_wait_queue(&nvmeq->sq_full,
1728 &nvmeq->sq_cong_wait);
1fa6aead 1729 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
427e9708
KB		 1730 if (bio_list_empty(&nvmeq->sq_cong))
1731 add_wait_queue(&nvmeq->sq_full,
1732 &nvmeq->sq_cong_wait);
1fa6aead
MW		 1733 bio_list_add_head(&nvmeq->sq_cong, bio);
1734 break;
1735 }
1736 }
1737}
1738
1739static int nvme_kthread(void *data)
1740{
d4b4ff8e 1741 struct nvme_dev *dev, *next;
1fa6aead
MW		 1742
1743 while (!kthread_should_stop()) {
564a232c 1744 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1745 spin_lock(&dev_list_lock);
d4b4ff8e 1746 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1747 int i;
d4b4ff8e
KB		 1748 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1749 dev->initialized) {
1750 if (work_busy(&dev->reset_work))
1751 continue;
1752 list_del_init(&dev->node);
1753 dev_warn(&dev->pci_dev->dev,
1754 "Failed status, reset controller\n");
bdfd70fd 1755 PREPARE_WORK(&dev->reset_work,
d4b4ff8e
KB		 1756 nvme_reset_failed_dev);
1757 queue_work(nvme_workq, &dev->reset_work);
1758 continue;
1759 }
5a92e700 1760 rcu_read_lock();
1fa6aead 1761 for (i = 0; i < dev->queue_count; i++) {
5a92e700
KB		 1762 struct nvme_queue *nvmeq =
1763 rcu_dereference(dev->queues[i]);
740216fc
MW		 1764 if (!nvmeq)
1765 continue;
1fa6aead 1766 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1767 if (nvmeq->q_suspended)
1768 goto unlock;
bc57a0f7 1769 nvme_process_cq(nvmeq);
a09115b2 1770 nvme_cancel_ios(nvmeq, true);
1fa6aead 1771 nvme_resubmit_bios(nvmeq);
22404274 1772 unlock:
1fa6aead
MW		 1773 spin_unlock_irq(&nvmeq->q_lock);
1774 }
5a92e700 1775 rcu_read_unlock();
1fa6aead
MW		 1776 }
1777 spin_unlock(&dev_list_lock);
acb7aa0d 1778 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1779 }
1780 return 0;
1781}
1782
0e5e4f0e
KB		 1783static void nvme_config_discard(struct nvme_ns *ns)
1784{
1785 u32 logical_block_size = queue_logical_block_size(ns->queue);
1786 ns->queue->limits.discard_zeroes_data = 0;
1787 ns->queue->limits.discard_alignment = logical_block_size;
1788 ns->queue->limits.discard_granularity = logical_block_size;
1789 ns->queue->limits.max_discard_sectors = 0xffffffff;
1790 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1791}
1792
c3bfe717 1793static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1794 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1795{
1796 struct nvme_ns *ns;
1797 struct gendisk *disk;
1798 int lbaf;
1799
1800 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1801 return NULL;
1802
1803 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1804 if (!ns)
1805 return NULL;
1806 ns->queue = blk_alloc_queue(GFP_KERNEL);
1807 if (!ns->queue)
1808 goto out_free_ns;
4eeb9215
MW		 1809 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1810 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1811 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 1812 blk_queue_make_request(ns->queue, nvme_make_request);
1813 ns->dev = dev;
1814 ns->queue->queuedata = ns;
1815
469071a3 1816 disk = alloc_disk(0);
b60503ba
MW		 1817 if (!disk)
1818 goto out_free_queue;
5aff9382 1819 ns->ns_id = nsid;
b60503ba
MW		 1820 ns->disk = disk;
1821 lbaf = id->flbas & 0xf;
1822 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1823 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1824 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1825 if (dev->max_hw_sectors)
1826 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
b60503ba
MW		 1827
1828 disk->major = nvme_major;
469071a3 1829 disk->first_minor = 0;
b60503ba
MW		 1830 disk->fops = &nvme_fops;
1831 disk->private_data = ns;
1832 disk->queue = ns->queue;
388f037f 1833 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1834 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1835 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1836 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1837
0e5e4f0e
KB		 1838 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1839 nvme_config_discard(ns);
1840
b60503ba
MW		 1841 return ns;
1842
1843 out_free_queue:
1844 blk_cleanup_queue(ns->queue);
1845 out_free_ns:
1846 kfree(ns);
1847 return NULL;
1848}
1849
42f61420
KB		 1850static int nvme_find_closest_node(int node)
1851{
1852 int n, val, min_val = INT_MAX, best_node = node;
1853
1854 for_each_online_node(n) {
1855 if (n == node)
1856 continue;
1857 val = node_distance(node, n);
1858 if (val < min_val) {
1859 min_val = val;
1860 best_node = n;
1861 }
1862 }
1863 return best_node;
1864}
1865
1866static void nvme_set_queue_cpus(cpumask_t *qmask, struct nvme_queue *nvmeq,
1867 int count)
1868{
1869 int cpu;
1870 for_each_cpu(cpu, qmask) {
1871 if (cpumask_weight(nvmeq->cpu_mask) >= count)
1872 break;
1873 if (!cpumask_test_and_set_cpu(cpu, nvmeq->cpu_mask))
1874 *per_cpu_ptr(nvmeq->dev->io_queue, cpu) = nvmeq->qid;
1875 }
1876}
1877
1878static void nvme_add_cpus(cpumask_t *mask, const cpumask_t *unassigned_cpus,
1879 const cpumask_t *new_mask, struct nvme_queue *nvmeq, int cpus_per_queue)
1880{
1881 int next_cpu;
1882 for_each_cpu(next_cpu, new_mask) {
1883 cpumask_or(mask, mask, get_cpu_mask(next_cpu));
1884 cpumask_or(mask, mask, topology_thread_cpumask(next_cpu));
1885 cpumask_and(mask, mask, unassigned_cpus);
1886 nvme_set_queue_cpus(mask, nvmeq, cpus_per_queue);
1887 }
1888}
1889
1890static void nvme_create_io_queues(struct nvme_dev *dev)
1891{
1892 unsigned i, max;
1893
1894 max = min(dev->max_qid, num_online_cpus());
1895 for (i = dev->queue_count; i <= max; i++)
1896 if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1))
1897 break;
1898
1899 max = min(dev->queue_count - 1, num_online_cpus());
1900 for (i = dev->online_queues; i <= max; i++)
1901 if (nvme_create_queue(raw_nvmeq(dev, i), i))
1902 break;
1903}
1904
1905/*
1906 * If there are fewer queues than online cpus, this will try to optimally
1907 * assign a queue to multiple cpus by grouping cpus that are "close" together:
1908 * thread siblings, core, socket, closest node, then whatever else is
1909 * available.
1910 */
1911static void nvme_assign_io_queues(struct nvme_dev *dev)
1912{
1913 unsigned cpu, cpus_per_queue, queues, remainder, i;
1914 cpumask_var_t unassigned_cpus;
1915
1916 nvme_create_io_queues(dev);
1917
1918 queues = min(dev->online_queues - 1, num_online_cpus());
1919 if (!queues)
1920 return;
1921
1922 cpus_per_queue = num_online_cpus() / queues;
1923 remainder = queues - (num_online_cpus() - queues * cpus_per_queue);
1924
1925 if (!alloc_cpumask_var(&unassigned_cpus, GFP_KERNEL))
1926 return;
1927
1928 cpumask_copy(unassigned_cpus, cpu_online_mask);
1929 cpu = cpumask_first(unassigned_cpus);
1930 for (i = 1; i <= queues; i++) {
1931 struct nvme_queue *nvmeq = lock_nvmeq(dev, i);
1932 cpumask_t mask;
1933
1934 cpumask_clear(nvmeq->cpu_mask);
1935 if (!cpumask_weight(unassigned_cpus)) {
1936 unlock_nvmeq(nvmeq);
1937 break;
1938 }
1939
1940 mask = *get_cpu_mask(cpu);
1941 nvme_set_queue_cpus(&mask, nvmeq, cpus_per_queue);
1942 if (cpus_weight(mask) < cpus_per_queue)
1943 nvme_add_cpus(&mask, unassigned_cpus,
1944 topology_thread_cpumask(cpu),
1945 nvmeq, cpus_per_queue);
1946 if (cpus_weight(mask) < cpus_per_queue)
1947 nvme_add_cpus(&mask, unassigned_cpus,
1948 topology_core_cpumask(cpu),
1949 nvmeq, cpus_per_queue);
1950 if (cpus_weight(mask) < cpus_per_queue)
1951 nvme_add_cpus(&mask, unassigned_cpus,
1952 cpumask_of_node(cpu_to_node(cpu)),
1953 nvmeq, cpus_per_queue);
1954 if (cpus_weight(mask) < cpus_per_queue)
1955 nvme_add_cpus(&mask, unassigned_cpus,
1956 cpumask_of_node(
1957 nvme_find_closest_node(
1958 cpu_to_node(cpu))),
1959 nvmeq, cpus_per_queue);
1960 if (cpus_weight(mask) < cpus_per_queue)
1961 nvme_add_cpus(&mask, unassigned_cpus,
1962 unassigned_cpus,
1963 nvmeq, cpus_per_queue);
1964
1965 WARN(cpumask_weight(nvmeq->cpu_mask) != cpus_per_queue,
1966 "nvme%d qid:%d mis-matched queue-to-cpu assignment\n",
1967 dev->instance, i);
1968
1969 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1970 nvmeq->cpu_mask);
1971 cpumask_andnot(unassigned_cpus, unassigned_cpus,
1972 nvmeq->cpu_mask);
1973 cpu = cpumask_next(cpu, unassigned_cpus);
1974 if (remainder && !--remainder)
1975 cpus_per_queue++;
1976 unlock_nvmeq(nvmeq);
1977 }
1978 WARN(cpumask_weight(unassigned_cpus), "nvme%d unassigned online cpus\n",
1979 dev->instance);
1980 i = 0;
1981 cpumask_andnot(unassigned_cpus, cpu_possible_mask, cpu_online_mask);
1982 for_each_cpu(cpu, unassigned_cpus)
1983 *per_cpu_ptr(dev->io_queue, cpu) = (i++ % queues) + 1;
1984 free_cpumask_var(unassigned_cpus);
1985}
1986
b3b06812 1987static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 1988{
1989 int status;
1990 u32 result;
b3b06812 1991 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 1992
df348139 1993 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 1994 &result);
b60503ba 1995 if (status)
7e03b124 1996 return status < 0 ? -EIO : -EBUSY;
b60503ba
MW		 1997 return min(result & 0xffff, result >> 16) + 1;
1998}
1999
9d713c2b
KB		 2000static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2001{
b80d5ccc 2002 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2003}
2004
33b1e95c
KB		 2005static int nvme_cpu_notify(struct notifier_block *self,
2006 unsigned long action, void *hcpu)
2007{
2008 struct nvme_dev *dev = container_of(self, struct nvme_dev, nb);
2009 switch (action) {
2010 case CPU_ONLINE:
2011 case CPU_DEAD:
2012 nvme_assign_io_queues(dev);
2013 break;
2014 }
2015 return NOTIFY_OK;
2016}
2017
8d85fce7 2018static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2019{
5a92e700 2020 struct nvme_queue *adminq = raw_nvmeq(dev, 0);
fa08a396 2021 struct pci_dev *pdev = dev->pci_dev;
42f61420 2022 int result, i, vecs, nr_io_queues, size;
b60503ba 2023
42f61420 2024 nr_io_queues = num_possible_cpus();
b348b7d5 2025 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW		 2026 if (result < 0)
2027 return result;
b348b7d5
MW		 2028 if (result < nr_io_queues)
2029 nr_io_queues = result;
b60503ba 2030
9d713c2b
KB		 2031 size = db_bar_size(dev, nr_io_queues);
2032 if (size > 8192) {
f1938f6e 2033 iounmap(dev->bar);
9d713c2b
KB		 2034 do {
2035 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2036 if (dev->bar)
2037 break;
2038 if (!--nr_io_queues)
2039 return -ENOMEM;
2040 size = db_bar_size(dev, nr_io_queues);
2041 } while (1);
f1938f6e 2042 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2043 adminq->q_db = dev->dbs;
f1938f6e
MW		 2044 }
2045
9d713c2b 2046 /* Deregister the admin queue's interrupt */
3193f07b 2047 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2048
063a8096
MW		 2049 vecs = nr_io_queues;
2050 for (i = 0; i < vecs; i++)
1b23484b
MW		 2051 dev->entry[i].entry = i;
2052 for (;;) {
063a8096
MW		 2053 result = pci_enable_msix(pdev, dev->entry, vecs);
2054 if (result <= 0)
1b23484b 2055 break;
063a8096 2056 vecs = result;
1b23484b
MW		 2057 }
2058
063a8096
MW		 2059 if (result < 0) {
2060 vecs = nr_io_queues;
2061 if (vecs > 32)
2062 vecs = 32;
fa08a396 2063 for (;;) {
063a8096 2064 result = pci_enable_msi_block(pdev, vecs);
fa08a396 2065 if (result == 0) {
063a8096 2066 for (i = 0; i < vecs; i++)
fa08a396
RRG		 2067 dev->entry[i].vector = i + pdev->irq;
2068 break;
063a8096
MW		 2069 } else if (result < 0) {
2070 vecs = 1;
fa08a396
RRG		 2071 break;
2072 }
063a8096 2073 vecs = result;
fa08a396
RRG		 2074 }
2075 }
2076
063a8096
MW		 2077 /*
2078 * Should investigate if there's a performance win from allocating
2079 * more queues than interrupt vectors; it might allow the submission
2080 * path to scale better, even if the receive path is limited by the
2081 * number of interrupts.
2082 */
2083 nr_io_queues = vecs;
42f61420 2084 dev->max_qid = nr_io_queues;
063a8096 2085
3193f07b 2086 result = queue_request_irq(dev, adminq, adminq->irqname);
9d713c2b 2087 if (result) {
3193f07b 2088 adminq->q_suspended = 1;
22404274 2089 goto free_queues;
9d713c2b 2090 }
1b23484b 2091
cd638946 2092 /* Free previously allocated queues that are no longer usable */
42f61420
KB		 2093 nvme_free_queues(dev, nr_io_queues + 1);
2094 nvme_assign_io_queues(dev);
b60503ba 2095
33b1e95c
KB		 2096 dev->nb.notifier_call = &nvme_cpu_notify;
2097 result = register_hotcpu_notifier(&dev->nb);
2098 if (result)
2099 goto free_queues;
2100
22404274 2101 return 0;
b60503ba 2102
22404274 2103 free_queues:
a1a5ef99 2104 nvme_free_queues(dev, 1);
22404274 2105 return result;
b60503ba
MW		 2106}
2107
422ef0c7
MW		 2108/*
2109 * Return: error value if an error occurred setting up the queues or calling
2110 * Identify Device. 0 if these succeeded, even if adding some of the
2111 * namespaces failed. At the moment, these failures are silent. TBD which
2112 * failures should be reported.
2113 */
8d85fce7 2114static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2115{
68608c26 2116 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2117 int res;
2118 unsigned nn, i;
cbb6218f 2119 struct nvme_ns *ns;
51814232 2120 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2121 struct nvme_id_ns *id_ns;
2122 void *mem;
b60503ba 2123 dma_addr_t dma_addr;
159b67d7 2124 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2125
68608c26 2126 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2127 if (!mem)
2128 return -ENOMEM;
b60503ba 2129
bc5fc7e4 2130 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba
MW		 2131 if (res) {
2132 res = -EIO;
cbb6218f 2133 goto out;
b60503ba
MW		 2134 }
2135
bc5fc7e4 2136 ctrl = mem;
51814232 2137 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2138 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2139 dev->abort_limit = ctrl->acl + 1;
51814232
MW		 2140 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2141 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2142 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2143 if (ctrl->mdts)
8fc23e03 2144 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26
MW		 2145 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2146 (pdev->device == 0x0953) && ctrl->vs[3])
159b67d7 2147 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
b60503ba 2148
bc5fc7e4 2149 id_ns = mem;
2b2c1896 2150 for (i = 1; i <= nn; i++) {
bc5fc7e4 2151 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2152 if (res)
2153 continue;
2154
bc5fc7e4 2155 if (id_ns->ncap == 0)
b60503ba
MW		 2156 continue;
2157
bc5fc7e4 2158 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2159 dma_addr + 4096, NULL);
b60503ba 2160 if (res)
12209036 2161 memset(mem + 4096, 0, 4096);
b60503ba 2162
bc5fc7e4 2163 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2164 if (ns)
2165 list_add_tail(&ns->list, &dev->namespaces);
2166 }
2167 list_for_each_entry(ns, &dev->namespaces, list)
2168 add_disk(ns->disk);
422ef0c7 2169 res = 0;
b60503ba 2170
bc5fc7e4 2171 out:
684f5c20 2172 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2173 return res;
2174}
2175
0877cb0d
KB		 2176static int nvme_dev_map(struct nvme_dev *dev)
2177{
42f61420 2178 u64 cap;
0877cb0d
KB		 2179 int bars, result = -ENOMEM;
2180 struct pci_dev *pdev = dev->pci_dev;
2181
2182 if (pci_enable_device_mem(pdev))
2183 return result;
2184
2185 dev->entry[0].vector = pdev->irq;
2186 pci_set_master(pdev);
2187 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2188 if (pci_request_selected_regions(pdev, bars, "nvme"))
2189 goto disable_pci;
2190
052d0efa
RK		 2191 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2192 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2193 goto disable;
0877cb0d 2194
0877cb0d
KB		 2195 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2196 if (!dev->bar)
2197 goto disable;
0e53d180
KB		 2198 if (readl(&dev->bar->csts) == -1) {
2199 result = -ENODEV;
2200 goto unmap;
2201 }
42f61420
KB		 2202 cap = readq(&dev->bar->cap);
2203 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2204 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2205 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2206
2207 return 0;
2208
0e53d180
KB		 2209 unmap:
2210 iounmap(dev->bar);
2211 dev->bar = NULL;
0877cb0d
KB		 2212 disable:
2213 pci_release_regions(pdev);
2214 disable_pci:
2215 pci_disable_device(pdev);
2216 return result;
2217}
2218
2219static void nvme_dev_unmap(struct nvme_dev *dev)
2220{
2221 if (dev->pci_dev->msi_enabled)
2222 pci_disable_msi(dev->pci_dev);
2223 else if (dev->pci_dev->msix_enabled)
2224 pci_disable_msix(dev->pci_dev);
2225
2226 if (dev->bar) {
2227 iounmap(dev->bar);
2228 dev->bar = NULL;
9a6b9458 2229 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2230 }
2231
0877cb0d
KB		 2232 if (pci_is_enabled(dev->pci_dev))
2233 pci_disable_device(dev->pci_dev);
2234}
2235
4d115420
KB		 2236struct nvme_delq_ctx {
2237 struct task_struct *waiter;
2238 struct kthread_worker *worker;
2239 atomic_t refcount;
2240};
2241
2242static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2243{
2244 dq->waiter = current;
2245 mb();
2246
2247 for (;;) {
2248 set_current_state(TASK_KILLABLE);
2249 if (!atomic_read(&dq->refcount))
2250 break;
2251 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2252 fatal_signal_pending(current)) {
2253 set_current_state(TASK_RUNNING);
2254
2255 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2256 nvme_disable_queue(dev, 0);
2257
2258 send_sig(SIGKILL, dq->worker->task, 1);
2259 flush_kthread_worker(dq->worker);
2260 return;
2261 }
2262 }
2263 set_current_state(TASK_RUNNING);
2264}
2265
2266static void nvme_put_dq(struct nvme_delq_ctx *dq)
2267{
2268 atomic_dec(&dq->refcount);
2269 if (dq->waiter)
2270 wake_up_process(dq->waiter);
2271}
2272
2273static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2274{
2275 atomic_inc(&dq->refcount);
2276 return dq;
2277}
2278
2279static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2280{
2281 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2282
2283 nvme_clear_queue(nvmeq);
2284 nvme_put_dq(dq);
2285}
2286
2287static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2288 kthread_work_func_t fn)
2289{
2290 struct nvme_command c;
2291
2292 memset(&c, 0, sizeof(c));
2293 c.delete_queue.opcode = opcode;
2294 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2295
2296 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2297 return nvme_submit_admin_cmd_async(nvmeq->dev, &c, &nvmeq->cmdinfo);
2298}
2299
2300static void nvme_del_cq_work_handler(struct kthread_work *work)
2301{
2302 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2303 cmdinfo.work);
2304 nvme_del_queue_end(nvmeq);
2305}
2306
2307static int nvme_delete_cq(struct nvme_queue *nvmeq)
2308{
2309 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2310 nvme_del_cq_work_handler);
2311}
2312
2313static void nvme_del_sq_work_handler(struct kthread_work *work)
2314{
2315 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2316 cmdinfo.work);
2317 int status = nvmeq->cmdinfo.status;
2318
2319 if (!status)
2320 status = nvme_delete_cq(nvmeq);
2321 if (status)
2322 nvme_del_queue_end(nvmeq);
2323}
2324
2325static int nvme_delete_sq(struct nvme_queue *nvmeq)
2326{
2327 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2328 nvme_del_sq_work_handler);
2329}
2330
2331static void nvme_del_queue_start(struct kthread_work *work)
2332{
2333 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2334 cmdinfo.work);
2335 allow_signal(SIGKILL);
2336 if (nvme_delete_sq(nvmeq))
2337 nvme_del_queue_end(nvmeq);
2338}
2339
2340static void nvme_disable_io_queues(struct nvme_dev *dev)
2341{
2342 int i;
2343 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2344 struct nvme_delq_ctx dq;
2345 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2346 &worker, "nvme%d", dev->instance);
2347
2348 if (IS_ERR(kworker_task)) {
2349 dev_err(&dev->pci_dev->dev,
2350 "Failed to create queue del task\n");
2351 for (i = dev->queue_count - 1; i > 0; i--)
2352 nvme_disable_queue(dev, i);
2353 return;
2354 }
2355
2356 dq.waiter = NULL;
2357 atomic_set(&dq.refcount, 0);
2358 dq.worker = &worker;
2359 for (i = dev->queue_count - 1; i > 0; i--) {
5a92e700 2360 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2361
2362 if (nvme_suspend_queue(nvmeq))
2363 continue;
2364 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2365 nvmeq->cmdinfo.worker = dq.worker;
2366 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2367 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2368 }
2369 nvme_wait_dq(&dq, dev);
2370 kthread_stop(kworker_task);
2371}
2372
f0b50732 2373static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2374{
22404274
KB		 2375 int i;
2376
d4b4ff8e 2377 dev->initialized = 0;
33b1e95c 2378 unregister_hotcpu_notifier(&dev->nb);
b60503ba 2379
1fa6aead 2380 spin_lock(&dev_list_lock);
f0b50732 2381 list_del_init(&dev->node);
1fa6aead
MW		 2382 spin_unlock(&dev_list_lock);
2383
4d115420
KB		 2384 if (!dev->bar || (dev->bar && readl(&dev->bar->csts) == -1)) {
2385 for (i = dev->queue_count - 1; i >= 0; i--) {
5a92e700 2386 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2387 nvme_suspend_queue(nvmeq);
2388 nvme_clear_queue(nvmeq);
2389 }
2390 } else {
2391 nvme_disable_io_queues(dev);
1894d8f1 2392 nvme_shutdown_ctrl(dev);
4d115420
KB		 2393 nvme_disable_queue(dev, 0);
2394 }
f0b50732
KB		 2395 nvme_dev_unmap(dev);
2396}
2397
2398static void nvme_dev_remove(struct nvme_dev *dev)
2399{
9ac27090 2400 struct nvme_ns *ns;
f0b50732 2401
9ac27090
KB		 2402 list_for_each_entry(ns, &dev->namespaces, list) {
2403 if (ns->disk->flags & GENHD_FL_UP)
2404 del_gendisk(ns->disk);
2405 if (!blk_queue_dying(ns->queue))
2406 blk_cleanup_queue(ns->queue);
b60503ba 2407 }
b60503ba
MW		 2408}
2409
091b6092
MW		 2410static int nvme_setup_prp_pools(struct nvme_dev *dev)
2411{
2412 struct device *dmadev = &dev->pci_dev->dev;
2413 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2414 PAGE_SIZE, PAGE_SIZE, 0);
2415 if (!dev->prp_page_pool)
2416 return -ENOMEM;
2417
99802a7a
MW		 2418 /* Optimisation for I/Os between 4k and 128k */
2419 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2420 256, 256, 0);
2421 if (!dev->prp_small_pool) {
2422 dma_pool_destroy(dev->prp_page_pool);
2423 return -ENOMEM;
2424 }
091b6092
MW		 2425 return 0;
2426}
2427
2428static void nvme_release_prp_pools(struct nvme_dev *dev)
2429{
2430 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2431 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2432}
2433
cd58ad7d
QSA		 2434static DEFINE_IDA(nvme_instance_ida);
2435
2436static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2437{
cd58ad7d
QSA		 2438 int instance, error;
2439
2440 do {
2441 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2442 return -ENODEV;
2443
2444 spin_lock(&dev_list_lock);
2445 error = ida_get_new(&nvme_instance_ida, &instance);
2446 spin_unlock(&dev_list_lock);
2447 } while (error == -EAGAIN);
2448
2449 if (error)
2450 return -ENODEV;
2451
2452 dev->instance = instance;
2453 return 0;
b60503ba
MW		 2454}
2455
2456static void nvme_release_instance(struct nvme_dev *dev)
2457{
cd58ad7d
QSA		 2458 spin_lock(&dev_list_lock);
2459 ida_remove(&nvme_instance_ida, dev->instance);
2460 spin_unlock(&dev_list_lock);
b60503ba
MW		 2461}
2462
9ac27090
KB		 2463static void nvme_free_namespaces(struct nvme_dev *dev)
2464{
2465 struct nvme_ns *ns, *next;
2466
2467 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2468 list_del(&ns->list);
2469 put_disk(ns->disk);
2470 kfree(ns);
2471 }
2472}
2473
5e82e952
KB		 2474static void nvme_free_dev(struct kref *kref)
2475{
2476 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090
KB		 2477
2478 nvme_free_namespaces(dev);
42f61420 2479 free_percpu(dev->io_queue);
5e82e952
KB		 2480 kfree(dev->queues);
2481 kfree(dev->entry);
2482 kfree(dev);
2483}
2484
2485static int nvme_dev_open(struct inode *inode, struct file *f)
2486{
2487 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2488 miscdev);
2489 kref_get(&dev->kref);
2490 f->private_data = dev;
2491 return 0;
2492}
2493
2494static int nvme_dev_release(struct inode *inode, struct file *f)
2495{
2496 struct nvme_dev *dev = f->private_data;
2497 kref_put(&dev->kref, nvme_free_dev);
2498 return 0;
2499}
2500
2501static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2502{
2503 struct nvme_dev *dev = f->private_data;
2504 switch (cmd) {
2505 case NVME_IOCTL_ADMIN_CMD:
2506 return nvme_user_admin_cmd(dev, (void __user *)arg);
2507 default:
2508 return -ENOTTY;
2509 }
2510}
2511
2512static const struct file_operations nvme_dev_fops = {
2513 .owner = THIS_MODULE,
2514 .open = nvme_dev_open,
2515 .release = nvme_dev_release,
2516 .unlocked_ioctl = nvme_dev_ioctl,
2517 .compat_ioctl = nvme_dev_ioctl,
2518};
2519
f0b50732
KB		 2520static int nvme_dev_start(struct nvme_dev *dev)
2521{
2522 int result;
2523
2524 result = nvme_dev_map(dev);
2525 if (result)
2526 return result;
2527
2528 result = nvme_configure_admin_queue(dev);
2529 if (result)
2530 goto unmap;
2531
2532 spin_lock(&dev_list_lock);
2533 list_add(&dev->node, &dev_list);
2534 spin_unlock(&dev_list_lock);
2535
2536 result = nvme_setup_io_queues(dev);
d82e8bfd 2537 if (result && result != -EBUSY)
f0b50732
KB		 2538 goto disable;
2539
d82e8bfd 2540 return result;
f0b50732
KB		 2541
2542 disable:
a1a5ef99 2543 nvme_disable_queue(dev, 0);
f0b50732
KB		 2544 spin_lock(&dev_list_lock);
2545 list_del_init(&dev->node);
2546 spin_unlock(&dev_list_lock);
2547 unmap:
2548 nvme_dev_unmap(dev);
2549 return result;
2550}
2551
9a6b9458
KB		 2552static int nvme_remove_dead_ctrl(void *arg)
2553{
2554 struct nvme_dev *dev = (struct nvme_dev *)arg;
2555 struct pci_dev *pdev = dev->pci_dev;
2556
2557 if (pci_get_drvdata(pdev))
2558 pci_stop_and_remove_bus_device(pdev);
2559 kref_put(&dev->kref, nvme_free_dev);
2560 return 0;
2561}
2562
2563static void nvme_remove_disks(struct work_struct *ws)
2564{
9a6b9458
KB		 2565 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2566
2567 nvme_dev_remove(dev);
5a92e700 2568 nvme_free_queues(dev, 1);
9a6b9458
KB		 2569}
2570
2571static int nvme_dev_resume(struct nvme_dev *dev)
2572{
2573 int ret;
2574
2575 ret = nvme_dev_start(dev);
2576 if (ret && ret != -EBUSY)
2577 return ret;
2578 if (ret == -EBUSY) {
2579 spin_lock(&dev_list_lock);
bdfd70fd 2580 PREPARE_WORK(&dev->reset_work, nvme_remove_disks);
9a6b9458
KB		 2581 queue_work(nvme_workq, &dev->reset_work);
2582 spin_unlock(&dev_list_lock);
2583 }
d4b4ff8e 2584 dev->initialized = 1;
9a6b9458
KB		 2585 return 0;
2586}
2587
2588static void nvme_dev_reset(struct nvme_dev *dev)
2589{
2590 nvme_dev_shutdown(dev);
2591 if (nvme_dev_resume(dev)) {
2592 dev_err(&dev->pci_dev->dev, "Device failed to resume\n");
2593 kref_get(&dev->kref);
2594 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2595 dev->instance))) {
2596 dev_err(&dev->pci_dev->dev,
2597 "Failed to start controller remove task\n");
2598 kref_put(&dev->kref, nvme_free_dev);
2599 }
2600 }
2601}
2602
2603static void nvme_reset_failed_dev(struct work_struct *ws)
2604{
2605 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2606 nvme_dev_reset(dev);
2607}
2608
8d85fce7 2609static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2610{
0877cb0d 2611 int result = -ENOMEM;
b60503ba
MW		 2612 struct nvme_dev *dev;
2613
2614 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2615 if (!dev)
2616 return -ENOMEM;
2617 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2618 GFP_KERNEL);
2619 if (!dev->entry)
2620 goto free;
1b23484b
MW		 2621 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2622 GFP_KERNEL);
b60503ba
MW		 2623 if (!dev->queues)
2624 goto free;
42f61420
KB		 2625 dev->io_queue = alloc_percpu(unsigned short);
2626 if (!dev->io_queue)
2627 goto free;
b60503ba
MW		 2628
2629 INIT_LIST_HEAD(&dev->namespaces);
bdfd70fd 2630 INIT_WORK(&dev->reset_work, nvme_reset_failed_dev);
b60503ba 2631 dev->pci_dev = pdev;
9a6b9458 2632 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2633 result = nvme_set_instance(dev);
2634 if (result)
0877cb0d 2635 goto free;
b60503ba 2636
091b6092
MW		 2637 result = nvme_setup_prp_pools(dev);
2638 if (result)
0877cb0d 2639 goto release;
091b6092 2640
fb35e914 2641 kref_init(&dev->kref);
f0b50732 2642 result = nvme_dev_start(dev);
d82e8bfd
KB		 2643 if (result) {
2644 if (result == -EBUSY)
2645 goto create_cdev;
0877cb0d 2646 goto release_pools;
d82e8bfd 2647 }
b60503ba 2648
740216fc 2649 result = nvme_dev_add(dev);
d82e8bfd 2650 if (result)
f0b50732 2651 goto shutdown;
740216fc 2652
d82e8bfd 2653 create_cdev:
5e82e952
KB		 2654 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2655 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2656 dev->miscdev.parent = &pdev->dev;
2657 dev->miscdev.name = dev->name;
2658 dev->miscdev.fops = &nvme_dev_fops;
2659 result = misc_register(&dev->miscdev);
2660 if (result)
2661 goto remove;
2662
d4b4ff8e 2663 dev->initialized = 1;
b60503ba
MW		 2664 return 0;
2665
5e82e952
KB		 2666 remove:
2667 nvme_dev_remove(dev);
9ac27090 2668 nvme_free_namespaces(dev);
f0b50732
KB		 2669 shutdown:
2670 nvme_dev_shutdown(dev);
0877cb0d 2671 release_pools:
a1a5ef99 2672 nvme_free_queues(dev, 0);
091b6092 2673 nvme_release_prp_pools(dev);
0877cb0d
KB		 2674 release:
2675 nvme_release_instance(dev);
b60503ba 2676 free:
42f61420 2677 free_percpu(dev->io_queue);
b60503ba
MW		 2678 kfree(dev->queues);
2679 kfree(dev->entry);
2680 kfree(dev);
2681 return result;
2682}
2683
09ece142
KB		 2684static void nvme_shutdown(struct pci_dev *pdev)
2685{
2686 struct nvme_dev *dev = pci_get_drvdata(pdev);
2687 nvme_dev_shutdown(dev);
2688}
2689
8d85fce7 2690static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2691{
2692 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2693
2694 spin_lock(&dev_list_lock);
2695 list_del_init(&dev->node);
2696 spin_unlock(&dev_list_lock);
2697
2698 pci_set_drvdata(pdev, NULL);
2699 flush_work(&dev->reset_work);
5e82e952 2700 misc_deregister(&dev->miscdev);
9a6b9458
KB		 2701 nvme_dev_remove(dev);
2702 nvme_dev_shutdown(dev);
a1a5ef99 2703 nvme_free_queues(dev, 0);
5a92e700 2704 rcu_barrier();
9a6b9458
KB		 2705 nvme_release_instance(dev);
2706 nvme_release_prp_pools(dev);
5e82e952 2707 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2708}
2709
2710/* These functions are yet to be implemented */
2711#define nvme_error_detected NULL
2712#define nvme_dump_registers NULL
2713#define nvme_link_reset NULL
2714#define nvme_slot_reset NULL
2715#define nvme_error_resume NULL
cd638946 2716
671a6018 2717#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2718static int nvme_suspend(struct device *dev)
2719{
2720 struct pci_dev *pdev = to_pci_dev(dev);
2721 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2722
2723 nvme_dev_shutdown(ndev);
2724 return 0;
2725}
2726
2727static int nvme_resume(struct device *dev)
2728{
2729 struct pci_dev *pdev = to_pci_dev(dev);
2730 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2731
9a6b9458 2732 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
bdfd70fd 2733 PREPARE_WORK(&ndev->reset_work, nvme_reset_failed_dev);
9a6b9458
KB		 2734 queue_work(nvme_workq, &ndev->reset_work);
2735 }
2736 return 0;
cd638946 2737}
671a6018 2738#endif
cd638946
KB		 2739
2740static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2741
1d352035 2742static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2743 .error_detected = nvme_error_detected,
2744 .mmio_enabled = nvme_dump_registers,
2745 .link_reset = nvme_link_reset,
2746 .slot_reset = nvme_slot_reset,
2747 .resume = nvme_error_resume,
2748};
2749
2750/* Move to pci_ids.h later */
2751#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2752
6eb0d698 2753static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2754 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2755 { 0, }
2756};
2757MODULE_DEVICE_TABLE(pci, nvme_id_table);
2758
2759static struct pci_driver nvme_driver = {
2760 .name = "nvme",
2761 .id_table = nvme_id_table,
2762 .probe = nvme_probe,
8d85fce7 2763 .remove = nvme_remove,
09ece142 2764 .shutdown = nvme_shutdown,
cd638946
KB		 2765 .driver = {
2766 .pm = &nvme_dev_pm_ops,
2767 },
b60503ba
MW		 2768 .err_handler = &nvme_err_handler,
2769};
2770
2771static int __init nvme_init(void)
2772{
0ac13140 2773 int result;
1fa6aead
MW		 2774
2775 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2776 if (IS_ERR(nvme_thread))
2777 return PTR_ERR(nvme_thread);
b60503ba 2778
9a6b9458
KB		 2779 result = -ENOMEM;
2780 nvme_workq = create_singlethread_workqueue("nvme");
2781 if (!nvme_workq)
2782 goto kill_kthread;
2783
5c42ea16
KB		 2784 result = register_blkdev(nvme_major, "nvme");
2785 if (result < 0)
9a6b9458 2786 goto kill_workq;
5c42ea16 2787 else if (result > 0)
0ac13140 2788 nvme_major = result;
b60503ba
MW		 2789
2790 result = pci_register_driver(&nvme_driver);
1fa6aead
MW		 2791 if (result)
2792 goto unregister_blkdev;
2793 return 0;
b60503ba 2794
1fa6aead 2795 unregister_blkdev:
b60503ba 2796 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2797 kill_workq:
2798 destroy_workqueue(nvme_workq);
1fa6aead
MW		 2799 kill_kthread:
2800 kthread_stop(nvme_thread);
b60503ba
MW		 2801 return result;
2802}
2803
2804static void __exit nvme_exit(void)
2805{
2806 pci_unregister_driver(&nvme_driver);
2807 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2808 destroy_workqueue(nvme_workq);
1fa6aead 2809 kthread_stop(nvme_thread);
b60503ba
MW		 2810}
2811
2812MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2813MODULE_LICENSE("GPL");
6eb0d698 2814MODULE_VERSION("0.9");
b60503ba
MW		 2815module_init(nvme_init);
2816module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)