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NVMe: Asynchronous controller probe
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
e1e5e564 40#include <linux/t10-pi.h>
b60503ba 41#include <linux/types.h>
5d0f6131 42#include <scsi/sg.h>
797a796a
HM		 43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
b3fffdef 45#define NVME_MINORS (1U << MINORBITS)
9d43cf64 46#define NVME_Q_DEPTH 1024
a4aea562 47#define NVME_AQ_DEPTH 64
b60503ba
MW		 48#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
49#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 50#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 51#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 52#define IOD_TIMEOUT (retry_time * HZ)
53
54static unsigned char admin_timeout = 60;
55module_param(admin_timeout, byte, 0644);
56MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 57
bd67608a
MW		 58unsigned char nvme_io_timeout = 30;
59module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 60MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 61
61e4ce08
KB		 62static unsigned char retry_time = 30;
63module_param(retry_time, byte, 0644);
64MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
65
2484f407
DM		 66static unsigned char shutdown_timeout = 5;
67module_param(shutdown_timeout, byte, 0644);
68MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
69
b60503ba
MW		 70static int nvme_major;
71module_param(nvme_major, int, 0);
72
b3fffdef
KB		 73static int nvme_char_major;
74module_param(nvme_char_major, int, 0);
75
58ffacb5
MW		 76static int use_threaded_interrupts;
77module_param(use_threaded_interrupts, int, 0);
78
1fa6aead
MW		 79static DEFINE_SPINLOCK(dev_list_lock);
80static LIST_HEAD(dev_list);
81static struct task_struct *nvme_thread;
9a6b9458 82static struct workqueue_struct *nvme_workq;
b9afca3e 83static wait_queue_head_t nvme_kthread_wait;
f3db22fe 84static struct notifier_block nvme_nb;
1fa6aead 85
b3fffdef
KB		 86static struct class *nvme_class;
87
d4b4ff8e 88static void nvme_reset_failed_dev(struct work_struct *ws);
a4aea562 89static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 90
4d115420
KB		 91struct async_cmd_info {
92 struct kthread_work work;
93 struct kthread_worker *worker;
a4aea562 94 struct request *req;
4d115420
KB		 95 u32 result;
96 int status;
97 void *ctx;
98};
1fa6aead 99
b60503ba
MW		 100/*
101 * An NVM Express queue. Each device has at least two (one for admin
102 * commands and one for I/O commands).
103 */
104struct nvme_queue {
f435c282 105 struct llist_node node;
b60503ba 106 struct device *q_dmadev;
091b6092 107 struct nvme_dev *dev;
3193f07b 108 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 109 spinlock_t q_lock;
110 struct nvme_command *sq_cmds;
111 volatile struct nvme_completion *cqes;
112 dma_addr_t sq_dma_addr;
113 dma_addr_t cq_dma_addr;
b60503ba
MW		 114 u32 __iomem *q_db;
115 u16 q_depth;
6222d172 116 s16 cq_vector;
b60503ba
MW		 117 u16 sq_head;
118 u16 sq_tail;
119 u16 cq_head;
c30341dc 120 u16 qid;
e9539f47
MW		 121 u8 cq_phase;
122 u8 cqe_seen;
4d115420 123 struct async_cmd_info cmdinfo;
a4aea562 124 struct blk_mq_hw_ctx *hctx;
b60503ba
MW		 125};
126
127/*
128 * Check we didin't inadvertently grow the command struct
129 */
130static inline void _nvme_check_size(void)
131{
132 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
134 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
135 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
136 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 137 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 138 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 139 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
140 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
141 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
142 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 143 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 144}
145
edd10d33 146typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 147 struct nvme_completion *);
148
e85248e5 149struct nvme_cmd_info {
c2f5b650
MW		 150 nvme_completion_fn fn;
151 void *ctx;
c30341dc 152 int aborted;
a4aea562 153 struct nvme_queue *nvmeq;
ac3dd5bd 154 struct nvme_iod iod[0];
e85248e5
MW		 155};
156
ac3dd5bd
JA		 157/*
158 * Max size of iod being embedded in the request payload
159 */
160#define NVME_INT_PAGES 2
161#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
162
163/*
164 * Will slightly overestimate the number of pages needed. This is OK
165 * as it only leads to a small amount of wasted memory for the lifetime of
166 * the I/O.
167 */
168static int nvme_npages(unsigned size, struct nvme_dev *dev)
169{
170 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
171 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
172}
173
174static unsigned int nvme_cmd_size(struct nvme_dev *dev)
175{
176 unsigned int ret = sizeof(struct nvme_cmd_info);
177
178 ret += sizeof(struct nvme_iod);
179 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
180 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
181
182 return ret;
183}
184
a4aea562
MB		 185static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
186 unsigned int hctx_idx)
e85248e5 187{
a4aea562
MB		 188 struct nvme_dev *dev = data;
189 struct nvme_queue *nvmeq = dev->queues[0];
190
191 WARN_ON(nvmeq->hctx);
192 nvmeq->hctx = hctx;
193 hctx->driver_data = nvmeq;
194 return 0;
e85248e5
MW		 195}
196
a4aea562
MB		 197static int nvme_admin_init_request(void *data, struct request *req,
198 unsigned int hctx_idx, unsigned int rq_idx,
199 unsigned int numa_node)
22404274 200{
a4aea562
MB		 201 struct nvme_dev *dev = data;
202 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
203 struct nvme_queue *nvmeq = dev->queues[0];
204
205 BUG_ON(!nvmeq);
206 cmd->nvmeq = nvmeq;
207 return 0;
22404274
KB		 208}
209
2c30540b
JA		 210static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
211{
212 struct nvme_queue *nvmeq = hctx->driver_data;
213
214 nvmeq->hctx = NULL;
215}
216
a4aea562
MB		 217static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
218 unsigned int hctx_idx)
b60503ba 219{
a4aea562
MB		 220 struct nvme_dev *dev = data;
221 struct nvme_queue *nvmeq = dev->queues[
222 (hctx_idx % dev->queue_count) + 1];
b60503ba 223
a4aea562
MB		 224 if (!nvmeq->hctx)
225 nvmeq->hctx = hctx;
226
227 /* nvmeq queues are shared between namespaces. We assume here that
228 * blk-mq map the tags so they match up with the nvme queue tags. */
229 WARN_ON(nvmeq->hctx->tags != hctx->tags);
b60503ba 230
a4aea562
MB		 231 hctx->driver_data = nvmeq;
232 return 0;
b60503ba
MW		 233}
234
a4aea562
MB		 235static int nvme_init_request(void *data, struct request *req,
236 unsigned int hctx_idx, unsigned int rq_idx,
237 unsigned int numa_node)
b60503ba 238{
a4aea562
MB		 239 struct nvme_dev *dev = data;
240 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
241 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
242
243 BUG_ON(!nvmeq);
244 cmd->nvmeq = nvmeq;
245 return 0;
246}
247
248static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
249 nvme_completion_fn handler)
250{
251 cmd->fn = handler;
252 cmd->ctx = ctx;
253 cmd->aborted = 0;
c917dfe5 254 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 255}
256
ac3dd5bd
JA		 257static void *iod_get_private(struct nvme_iod *iod)
258{
259 return (void *) (iod->private & ~0x1UL);
260}
261
262/*
263 * If bit 0 is set, the iod is embedded in the request payload.
264 */
265static bool iod_should_kfree(struct nvme_iod *iod)
266{
267 return (iod->private & 0x01) == 0;
268}
269
c2f5b650
MW		 270/* Special values must be less than 0x1000 */
271#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 272#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
273#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
274#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 275
edd10d33 276static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 277 struct nvme_completion *cqe)
278{
279 if (ctx == CMD_CTX_CANCELLED)
280 return;
c2f5b650 281 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 282 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 283 "completed id %d twice on queue %d\n",
284 cqe->command_id, le16_to_cpup(&cqe->sq_id));
285 return;
286 }
287 if (ctx == CMD_CTX_INVALID) {
edd10d33 288 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 289 "invalid id %d completed on queue %d\n",
290 cqe->command_id, le16_to_cpup(&cqe->sq_id));
291 return;
292 }
edd10d33 293 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 294}
295
a4aea562 296static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 297{
c2f5b650 298 void *ctx;
b60503ba 299
859361a2 300 if (fn)
a4aea562
MB		 301 *fn = cmd->fn;
302 ctx = cmd->ctx;
303 cmd->fn = special_completion;
304 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 305 return ctx;
b60503ba
MW		 306}
307
a4aea562
MB		 308static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
309 struct nvme_completion *cqe)
3c0cf138 310{
a4aea562 311 struct request *req = ctx;
3c0cf138 312
a4aea562
MB		 313 u32 result = le32_to_cpup(&cqe->result);
314 u16 status = le16_to_cpup(&cqe->status) >> 1;
315
316 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
317 ++nvmeq->dev->event_limit;
318 if (status == NVME_SC_SUCCESS)
319 dev_warn(nvmeq->q_dmadev,
320 "async event result %08x\n", result);
321
9d135bb8 322 blk_mq_free_hctx_request(nvmeq->hctx, req);
b60503ba
MW		 323}
324
a4aea562
MB		 325static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
326 struct nvme_completion *cqe)
5a92e700 327{
a4aea562
MB		 328 struct request *req = ctx;
329
330 u16 status = le16_to_cpup(&cqe->status) >> 1;
331 u32 result = le32_to_cpup(&cqe->result);
a51afb54 332
9d135bb8 333 blk_mq_free_hctx_request(nvmeq->hctx, req);
a51afb54 334
a4aea562
MB		 335 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
336 ++nvmeq->dev->abort_limit;
5a92e700
KB		 337}
338
a4aea562
MB		 339static void async_completion(struct nvme_queue *nvmeq, void *ctx,
340 struct nvme_completion *cqe)
b60503ba 341{
a4aea562
MB		 342 struct async_cmd_info *cmdinfo = ctx;
343 cmdinfo->result = le32_to_cpup(&cqe->result);
344 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
345 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
9d135bb8 346 blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
b60503ba
MW		 347}
348
a4aea562
MB		 349static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
350 unsigned int tag)
b60503ba 351{
a4aea562
MB		 352 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
353 struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
a51afb54 354
a4aea562 355 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 356}
357
a4aea562
MB		 358/*
359 * Called with local interrupts disabled and the q_lock held. May not sleep.
360 */
361static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
362 nvme_completion_fn *fn)
4f5099af 363{
a4aea562
MB		 364 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
365 void *ctx;
366 if (tag >= nvmeq->q_depth) {
367 *fn = special_completion;
368 return CMD_CTX_INVALID;
369 }
370 if (fn)
371 *fn = cmd->fn;
372 ctx = cmd->ctx;
373 cmd->fn = special_completion;
374 cmd->ctx = CMD_CTX_COMPLETED;
375 return ctx;
b60503ba
MW		 376}
377
378/**
714a7a22 379 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 380 * @nvmeq: The queue to use
381 * @cmd: The command to send
382 *
383 * Safe to use from interrupt context
384 */
a4aea562 385static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 386{
a4aea562
MB		 387 u16 tail = nvmeq->sq_tail;
388
b60503ba 389 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 390 if (++tail == nvmeq->q_depth)
391 tail = 0;
7547881d 392 writel(tail, nvmeq->q_db);
b60503ba 393 nvmeq->sq_tail = tail;
b60503ba
MW		 394
395 return 0;
396}
397
a4aea562
MB		 398static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
399{
400 unsigned long flags;
401 int ret;
402 spin_lock_irqsave(&nvmeq->q_lock, flags);
403 ret = __nvme_submit_cmd(nvmeq, cmd);
404 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
405 return ret;
406}
407
eca18b23 408static __le64 **iod_list(struct nvme_iod *iod)
e025344c 409{
eca18b23 410 return ((void *)iod) + iod->offset;
e025344c
SMM		 411}
412
ac3dd5bd
JA		 413static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
414 unsigned nseg, unsigned long private)
eca18b23 415{
ac3dd5bd
JA		 416 iod->private = private;
417 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
418 iod->npages = -1;
419 iod->length = nbytes;
420 iod->nents = 0;
eca18b23 421}
b60503ba 422
eca18b23 423static struct nvme_iod *
ac3dd5bd
JA		 424__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
425 unsigned long priv, gfp_t gfp)
b60503ba 426{
eca18b23 427 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 428 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 429 sizeof(struct scatterlist) * nseg, gfp);
430
ac3dd5bd
JA		 431 if (iod)
432 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 433
434 return iod;
b60503ba
MW		 435}
436
ac3dd5bd
JA		 437static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
438 gfp_t gfp)
439{
440 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
441 sizeof(struct nvme_dsm_range);
442 unsigned long mask = 0;
443 struct nvme_iod *iod;
444
445 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
446 size <= NVME_INT_BYTES(dev)) {
447 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
448
449 iod = cmd->iod;
450 mask = 0x01;
451 iod_init(iod, size, rq->nr_phys_segments,
452 (unsigned long) rq | 0x01);
453 return iod;
454 }
455
456 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
457 (unsigned long) rq, gfp);
458}
459
5d0f6131 460void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 461{
1d090624 462 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 463 int i;
464 __le64 **list = iod_list(iod);
465 dma_addr_t prp_dma = iod->first_dma;
466
467 if (iod->npages == 0)
468 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
469 for (i = 0; i < iod->npages; i++) {
470 __le64 *prp_list = list[i];
471 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
472 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
473 prp_dma = next_prp_dma;
474 }
ac3dd5bd
JA		 475
476 if (iod_should_kfree(iod))
477 kfree(iod);
b60503ba
MW		 478}
479
b4ff9c8d
KB		 480static int nvme_error_status(u16 status)
481{
482 switch (status & 0x7ff) {
483 case NVME_SC_SUCCESS:
484 return 0;
485 case NVME_SC_CAP_EXCEEDED:
486 return -ENOSPC;
487 default:
488 return -EIO;
489 }
490}
491
e1e5e564
KB		 492static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
493{
494 if (be32_to_cpu(pi->ref_tag) == v)
495 pi->ref_tag = cpu_to_be32(p);
496}
497
498static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
499{
500 if (be32_to_cpu(pi->ref_tag) == p)
501 pi->ref_tag = cpu_to_be32(v);
502}
503
504/**
505 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
506 *
507 * The virtual start sector is the one that was originally submitted by the
508 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
509 * start sector may be different. Remap protection information to match the
510 * physical LBA on writes, and back to the original seed on reads.
511 *
512 * Type 0 and 3 do not have a ref tag, so no remapping required.
513 */
514static void nvme_dif_remap(struct request *req,
515 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
516{
517 struct nvme_ns *ns = req->rq_disk->private_data;
518 struct bio_integrity_payload *bip;
519 struct t10_pi_tuple *pi;
520 void *p, *pmap;
521 u32 i, nlb, ts, phys, virt;
522
523 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
524 return;
525
526 bip = bio_integrity(req->bio);
527 if (!bip)
528 return;
529
530 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
531 if (!pmap)
532 return;
533
534 p = pmap;
535 virt = bip_get_seed(bip);
536 phys = nvme_block_nr(ns, blk_rq_pos(req));
537 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
538 ts = ns->disk->integrity->tuple_size;
539
540 for (i = 0; i < nlb; i++, virt++, phys++) {
541 pi = (struct t10_pi_tuple *)p;
542 dif_swap(phys, virt, pi);
543 p += ts;
544 }
545 kunmap_atomic(pmap);
546}
547
a4aea562 548static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 549 struct nvme_completion *cqe)
550{
eca18b23 551 struct nvme_iod *iod = ctx;
ac3dd5bd 552 struct request *req = iod_get_private(iod);
a4aea562
MB		 553 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
554
b60503ba
MW		 555 u16 status = le16_to_cpup(&cqe->status) >> 1;
556
edd10d33 557 if (unlikely(status)) {
a4aea562
MB		 558 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
559 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 560 unsigned long flags;
561
a4aea562 562 blk_mq_requeue_request(req);
c9d3bf88
KB		 563 spin_lock_irqsave(req->q->queue_lock, flags);
564 if (!blk_queue_stopped(req->q))
565 blk_mq_kick_requeue_list(req->q);
566 spin_unlock_irqrestore(req->q->queue_lock, flags);
edd10d33
KB		 567 return;
568 }
a4aea562
MB		 569 req->errors = nvme_error_status(status);
570 } else
571 req->errors = 0;
572
573 if (cmd_rq->aborted)
574 dev_warn(&nvmeq->dev->pci_dev->dev,
575 "completing aborted command with status:%04x\n",
576 status);
577
e1e5e564 578 if (iod->nents) {
a4aea562
MB		 579 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
580 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
e1e5e564
KB		 581 if (blk_integrity_rq(req)) {
582 if (!rq_data_dir(req))
583 nvme_dif_remap(req, nvme_dif_complete);
584 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->meta_sg, 1,
585 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
586 }
587 }
edd10d33 588 nvme_free_iod(nvmeq->dev, iod);
3291fa57 589
a4aea562 590 blk_mq_complete_request(req);
b60503ba
MW		 591}
592
184d2944 593/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 594int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
595 gfp_t gfp)
ff22b54f 596{
99802a7a 597 struct dma_pool *pool;
eca18b23
MW		 598 int length = total_len;
599 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 600 int dma_len = sg_dma_len(sg);
601 u64 dma_addr = sg_dma_address(sg);
602 int offset = offset_in_page(dma_addr);
e025344c 603 __le64 *prp_list;
eca18b23 604 __le64 **list = iod_list(iod);
e025344c 605 dma_addr_t prp_dma;
eca18b23 606 int nprps, i;
1d090624 607 u32 page_size = dev->page_size;
ff22b54f 608
1d090624 609 length -= (page_size - offset);
ff22b54f 610 if (length <= 0)
eca18b23 611 return total_len;
ff22b54f 612
1d090624 613 dma_len -= (page_size - offset);
ff22b54f 614 if (dma_len) {
1d090624 615 dma_addr += (page_size - offset);
ff22b54f
MW		 616 } else {
617 sg = sg_next(sg);
618 dma_addr = sg_dma_address(sg);
619 dma_len = sg_dma_len(sg);
620 }
621
1d090624 622 if (length <= page_size) {
edd10d33 623 iod->first_dma = dma_addr;
eca18b23 624 return total_len;
e025344c
SMM		 625 }
626
1d090624 627 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 628 if (nprps <= (256 / 8)) {
629 pool = dev->prp_small_pool;
eca18b23 630 iod->npages = 0;
99802a7a
MW		 631 } else {
632 pool = dev->prp_page_pool;
eca18b23 633 iod->npages = 1;
99802a7a
MW		 634 }
635
b77954cb
MW		 636 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
637 if (!prp_list) {
edd10d33 638 iod->first_dma = dma_addr;
eca18b23 639 iod->npages = -1;
1d090624 640 return (total_len - length) + page_size;
b77954cb 641 }
eca18b23
MW		 642 list[0] = prp_list;
643 iod->first_dma = prp_dma;
e025344c
SMM		 644 i = 0;
645 for (;;) {
1d090624 646 if (i == page_size >> 3) {
e025344c 647 __le64 *old_prp_list = prp_list;
b77954cb 648 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 649 if (!prp_list)
650 return total_len - length;
651 list[iod->npages++] = prp_list;
7523d834
MW		 652 prp_list[0] = old_prp_list[i - 1];
653 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
654 i = 1;
e025344c
SMM		 655 }
656 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 657 dma_len -= page_size;
658 dma_addr += page_size;
659 length -= page_size;
e025344c
SMM		 660 if (length <= 0)
661 break;
662 if (dma_len > 0)
663 continue;
664 BUG_ON(dma_len < 0);
665 sg = sg_next(sg);
666 dma_addr = sg_dma_address(sg);
667 dma_len = sg_dma_len(sg);
ff22b54f
MW		 668 }
669
eca18b23 670 return total_len;
ff22b54f
MW		 671}
672
a4aea562
MB		 673/*
674 * We reuse the small pool to allocate the 16-byte range here as it is not
675 * worth having a special pool for these or additional cases to handle freeing
676 * the iod.
677 */
678static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
679 struct request *req, struct nvme_iod *iod)
0e5e4f0e 680{
edd10d33
KB		 681 struct nvme_dsm_range *range =
682 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 683 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
684
0e5e4f0e 685 range->cattr = cpu_to_le32(0);
a4aea562
MB		 686 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
687 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e
KB		 688
689 memset(cmnd, 0, sizeof(*cmnd));
690 cmnd->dsm.opcode = nvme_cmd_dsm;
a4aea562 691 cmnd->dsm.command_id = req->tag;
0e5e4f0e
KB		 692 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
693 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
694 cmnd->dsm.nr = 0;
695 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
696
697 if (++nvmeq->sq_tail == nvmeq->q_depth)
698 nvmeq->sq_tail = 0;
699 writel(nvmeq->sq_tail, nvmeq->q_db);
0e5e4f0e
KB		 700}
701
a4aea562 702static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 703 int cmdid)
704{
705 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
706
707 memset(cmnd, 0, sizeof(*cmnd));
708 cmnd->common.opcode = nvme_cmd_flush;
709 cmnd->common.command_id = cmdid;
710 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
711
712 if (++nvmeq->sq_tail == nvmeq->q_depth)
713 nvmeq->sq_tail = 0;
714 writel(nvmeq->sq_tail, nvmeq->q_db);
00df5cb4
MW		 715}
716
a4aea562
MB		 717static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
718 struct nvme_ns *ns)
b60503ba 719{
ac3dd5bd 720 struct request *req = iod_get_private(iod);
ff22b54f 721 struct nvme_command *cmnd;
a4aea562
MB		 722 u16 control = 0;
723 u32 dsmgmt = 0;
00df5cb4 724
a4aea562 725 if (req->cmd_flags & REQ_FUA)
b60503ba 726 control |= NVME_RW_FUA;
a4aea562 727 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 728 control |= NVME_RW_LR;
729
a4aea562 730 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 731 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
732
ff22b54f 733 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 734 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 735
a4aea562
MB		 736 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
737 cmnd->rw.command_id = req->tag;
ff22b54f 738 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 739 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
740 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
a4aea562
MB		 741 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
742 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
e1e5e564
KB		 743
744 if (blk_integrity_rq(req)) {
745 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
746 switch (ns->pi_type) {
747 case NVME_NS_DPS_PI_TYPE3:
748 control |= NVME_RW_PRINFO_PRCHK_GUARD;
749 break;
750 case NVME_NS_DPS_PI_TYPE1:
751 case NVME_NS_DPS_PI_TYPE2:
752 control |= NVME_RW_PRINFO_PRCHK_GUARD |
753 NVME_RW_PRINFO_PRCHK_REF;
754 cmnd->rw.reftag = cpu_to_le32(
755 nvme_block_nr(ns, blk_rq_pos(req)));
756 break;
757 }
758 } else if (ns->ms)
759 control |= NVME_RW_PRINFO_PRACT;
760
ff22b54f
MW		 761 cmnd->rw.control = cpu_to_le16(control);
762 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 763
b60503ba
MW		 764 if (++nvmeq->sq_tail == nvmeq->q_depth)
765 nvmeq->sq_tail = 0;
7547881d 766 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 767
1974b1ae 768 return 0;
edd10d33
KB		 769}
770
a4aea562
MB		 771static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
772 const struct blk_mq_queue_data *bd)
edd10d33 773{
a4aea562
MB		 774 struct nvme_ns *ns = hctx->queue->queuedata;
775 struct nvme_queue *nvmeq = hctx->driver_data;
776 struct request *req = bd->rq;
777 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 778 struct nvme_iod *iod;
a4aea562 779 enum dma_data_direction dma_dir;
edd10d33 780
e1e5e564
KB		 781 /*
782 * If formated with metadata, require the block layer provide a buffer
783 * unless this namespace is formated such that the metadata can be
784 * stripped/generated by the controller with PRACT=1.
785 */
786 if (ns->ms && !blk_integrity_rq(req)) {
787 if (!(ns->pi_type && ns->ms == 8)) {
788 req->errors = -EFAULT;
789 blk_mq_complete_request(req);
790 return BLK_MQ_RQ_QUEUE_OK;
791 }
792 }
793
ac3dd5bd 794 iod = nvme_alloc_iod(req, ns->dev, GFP_ATOMIC);
edd10d33 795 if (!iod)
fe54303e 796 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 797
a4aea562 798 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 799 void *range;
800 /*
801 * We reuse the small pool to allocate the 16-byte range here
802 * as it is not worth having a special pool for these or
803 * additional cases to handle freeing the iod.
804 */
805 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
806 GFP_ATOMIC,
807 &iod->first_dma);
a4aea562 808 if (!range)
fe54303e 809 goto retry_cmd;
edd10d33
KB		 810 iod_list(iod)[0] = (__le64 *)range;
811 iod->npages = 0;
ac3dd5bd 812 } else if (req->nr_phys_segments) {
a4aea562
MB		 813 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
814
ac3dd5bd 815 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 816 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 817 if (!iod->nents)
818 goto error_cmd;
a4aea562
MB		 819
820 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 821 goto retry_cmd;
a4aea562 822
fe54303e
JA		 823 if (blk_rq_bytes(req) !=
824 nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
825 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg,
826 iod->nents, dma_dir);
827 goto retry_cmd;
828 }
e1e5e564
KB		 829 if (blk_integrity_rq(req)) {
830 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
831 goto error_cmd;
832
833 sg_init_table(iod->meta_sg, 1);
834 if (blk_rq_map_integrity_sg(
835 req->q, req->bio, iod->meta_sg) != 1)
836 goto error_cmd;
837
838 if (rq_data_dir(req))
839 nvme_dif_remap(req, nvme_dif_prep);
840
841 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
842 goto error_cmd;
843 }
edd10d33 844 }
1974b1ae 845
9af8785a 846 nvme_set_info(cmd, iod, req_completion);
a4aea562
MB		 847 spin_lock_irq(&nvmeq->q_lock);
848 if (req->cmd_flags & REQ_DISCARD)
849 nvme_submit_discard(nvmeq, ns, req, iod);
850 else if (req->cmd_flags & REQ_FLUSH)
851 nvme_submit_flush(nvmeq, ns, req->tag);
852 else
853 nvme_submit_iod(nvmeq, iod, ns);
854
855 nvme_process_cq(nvmeq);
856 spin_unlock_irq(&nvmeq->q_lock);
857 return BLK_MQ_RQ_QUEUE_OK;
858
fe54303e
JA		 859 error_cmd:
860 nvme_free_iod(nvmeq->dev, iod);
861 return BLK_MQ_RQ_QUEUE_ERROR;
862 retry_cmd:
eca18b23 863 nvme_free_iod(nvmeq->dev, iod);
fe54303e 864 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 865}
866
e9539f47 867static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 868{
82123460 869 u16 head, phase;
b60503ba 870
b60503ba 871 head = nvmeq->cq_head;
82123460 872 phase = nvmeq->cq_phase;
b60503ba
MW		 873
874 for (;;) {
c2f5b650
MW		 875 void *ctx;
876 nvme_completion_fn fn;
b60503ba 877 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 878 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 879 break;
880 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
881 if (++head == nvmeq->q_depth) {
882 head = 0;
82123460 883 phase = !phase;
b60503ba 884 }
a4aea562 885 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 886 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 887 }
888
889 /* If the controller ignores the cq head doorbell and continuously
890 * writes to the queue, it is theoretically possible to wrap around
891 * the queue twice and mistakenly return IRQ_NONE. Linux only
892 * requires that 0.1% of your interrupts are handled, so this isn't
893 * a big problem.
894 */
82123460 895 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 896 return 0;
b60503ba 897
b80d5ccc 898 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 899 nvmeq->cq_head = head;
82123460 900 nvmeq->cq_phase = phase;
b60503ba 901
e9539f47
MW		 902 nvmeq->cqe_seen = 1;
903 return 1;
b60503ba
MW		 904}
905
a4aea562
MB		 906/* Admin queue isn't initialized as a request queue. If at some point this
907 * happens anyway, make sure to notify the user */
908static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
909 const struct blk_mq_queue_data *bd)
7d822457 910{
a4aea562
MB		 911 WARN_ON_ONCE(1);
912 return BLK_MQ_RQ_QUEUE_ERROR;
7d822457
MW		 913}
914
b60503ba 915static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 916{
917 irqreturn_t result;
918 struct nvme_queue *nvmeq = data;
919 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 920 nvme_process_cq(nvmeq);
921 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
922 nvmeq->cqe_seen = 0;
58ffacb5
MW		 923 spin_unlock(&nvmeq->q_lock);
924 return result;
925}
926
927static irqreturn_t nvme_irq_check(int irq, void *data)
928{
929 struct nvme_queue *nvmeq = data;
930 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
931 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
932 return IRQ_NONE;
933 return IRQ_WAKE_THREAD;
934}
935
a4aea562
MB		 936static void nvme_abort_cmd_info(struct nvme_queue *nvmeq, struct nvme_cmd_info *
937 cmd_info)
3c0cf138
MW		 938{
939 spin_lock_irq(&nvmeq->q_lock);
a4aea562 940 cancel_cmd_info(cmd_info, NULL);
3c0cf138
MW		 941 spin_unlock_irq(&nvmeq->q_lock);
942}
943
c2f5b650
MW		 944struct sync_cmd_info {
945 struct task_struct *task;
946 u32 result;
947 int status;
948};
949
edd10d33 950static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 951 struct nvme_completion *cqe)
952{
953 struct sync_cmd_info *cmdinfo = ctx;
954 cmdinfo->result = le32_to_cpup(&cqe->result);
955 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
956 wake_up_process(cmdinfo->task);
957}
958
b60503ba
MW		 959/*
960 * Returns 0 on success. If the result is negative, it's a Linux error code;
961 * if the result is positive, it's an NVM Express status code
962 */
a4aea562 963static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
5d0f6131 964 u32 *result, unsigned timeout)
b60503ba 965{
a4aea562 966 int ret;
b60503ba 967 struct sync_cmd_info cmdinfo;
a4aea562
MB		 968 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
969 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
b60503ba
MW		 970
971 cmdinfo.task = current;
972 cmdinfo.status = -EINTR;
973
a4aea562
MB		 974 cmd->common.command_id = req->tag;
975
976 nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
b60503ba 977
3c0cf138 978 set_current_state(TASK_KILLABLE);
4f5099af
KB		 979 ret = nvme_submit_cmd(nvmeq, cmd);
980 if (ret) {
a4aea562 981 nvme_finish_cmd(nvmeq, req->tag, NULL);
4f5099af 982 set_current_state(TASK_RUNNING);
4f5099af 983 }
849c6e77 984 ret = schedule_timeout(timeout);
b60503ba 985
849c6e77
JA		 986 /*
987 * Ensure that sync_completion has either run, or that it will
988 * never run.
989 */
990 nvme_abort_cmd_info(nvmeq, blk_mq_rq_to_pdu(req));
991
992 /*
993 * We never got the completion
994 */
995 if (cmdinfo.status == -EINTR)
3c0cf138 996 return -EINTR;
3c0cf138 997
b60503ba
MW		 998 if (result)
999 *result = cmdinfo.result;
1000
1001 return cmdinfo.status;
1002}
1003
a4aea562
MB		 1004static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1005{
1006 struct nvme_queue *nvmeq = dev->queues[0];
1007 struct nvme_command c;
1008 struct nvme_cmd_info *cmd_info;
1009 struct request *req;
1010
6dcc0cf6 1011 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false);
9f173b33
DC		 1012 if (IS_ERR(req))
1013 return PTR_ERR(req);
a4aea562 1014
c917dfe5 1015 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562
MB		 1016 cmd_info = blk_mq_rq_to_pdu(req);
1017 nvme_set_info(cmd_info, req, async_req_completion);
1018
1019 memset(&c, 0, sizeof(c));
1020 c.common.opcode = nvme_admin_async_event;
1021 c.common.command_id = req->tag;
1022
1023 return __nvme_submit_cmd(nvmeq, &c);
1024}
1025
1026static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 1027 struct nvme_command *cmd,
1028 struct async_cmd_info *cmdinfo, unsigned timeout)
1029{
a4aea562
MB		 1030 struct nvme_queue *nvmeq = dev->queues[0];
1031 struct request *req;
1032 struct nvme_cmd_info *cmd_rq;
4d115420 1033
a4aea562 1034 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 1035 if (IS_ERR(req))
1036 return PTR_ERR(req);
a4aea562
MB		 1037
1038 req->timeout = timeout;
1039 cmd_rq = blk_mq_rq_to_pdu(req);
1040 cmdinfo->req = req;
1041 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 1042 cmdinfo->status = -EINTR;
a4aea562
MB		 1043
1044 cmd->common.command_id = req->tag;
1045
4f5099af 1046 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 1047}
1048
a64e6bb4 1049static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
a4aea562 1050 u32 *result, unsigned timeout)
b60503ba 1051{
a4aea562
MB		 1052 int res;
1053 struct request *req;
1054
1055 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
97fe3832
JA		 1056 if (IS_ERR(req))
1057 return PTR_ERR(req);
a4aea562 1058 res = nvme_submit_sync_cmd(req, cmd, result, timeout);
9d135bb8 1059 blk_mq_free_request(req);
a4aea562 1060 return res;
4f5099af
KB		 1061}
1062
a4aea562 1063int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
4f5099af
KB		 1064 u32 *result)
1065{
a4aea562 1066 return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 1067}
1068
a4aea562
MB		 1069int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1070 struct nvme_command *cmd, u32 *result)
4d115420 1071{
a4aea562
MB		 1072 int res;
1073 struct request *req;
1074
1075 req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
1076 false);
97fe3832
JA		 1077 if (IS_ERR(req))
1078 return PTR_ERR(req);
a4aea562 1079 res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
9d135bb8 1080 blk_mq_free_request(req);
a4aea562 1081 return res;
4d115420
KB		 1082}
1083
b60503ba
MW		 1084static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1085{
b60503ba
MW		 1086 struct nvme_command c;
1087
1088 memset(&c, 0, sizeof(c));
1089 c.delete_queue.opcode = opcode;
1090 c.delete_queue.qid = cpu_to_le16(id);
1091
a4aea562 1092 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 1093}
1094
1095static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1096 struct nvme_queue *nvmeq)
1097{
b60503ba
MW		 1098 struct nvme_command c;
1099 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1100
1101 memset(&c, 0, sizeof(c));
1102 c.create_cq.opcode = nvme_admin_create_cq;
1103 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1104 c.create_cq.cqid = cpu_to_le16(qid);
1105 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1106 c.create_cq.cq_flags = cpu_to_le16(flags);
1107 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1108
a4aea562 1109 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 1110}
1111
1112static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1113 struct nvme_queue *nvmeq)
1114{
b60503ba
MW		 1115 struct nvme_command c;
1116 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1117
1118 memset(&c, 0, sizeof(c));
1119 c.create_sq.opcode = nvme_admin_create_sq;
1120 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1121 c.create_sq.sqid = cpu_to_le16(qid);
1122 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1123 c.create_sq.sq_flags = cpu_to_le16(flags);
1124 c.create_sq.cqid = cpu_to_le16(qid);
1125
a4aea562 1126 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 1127}
1128
1129static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1130{
1131 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1132}
1133
1134static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1135{
1136 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1137}
1138
5d0f6131 1139int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 1140 dma_addr_t dma_addr)
1141{
1142 struct nvme_command c;
1143
1144 memset(&c, 0, sizeof(c));
1145 c.identify.opcode = nvme_admin_identify;
1146 c.identify.nsid = cpu_to_le32(nsid);
1147 c.identify.prp1 = cpu_to_le64(dma_addr);
1148 c.identify.cns = cpu_to_le32(cns);
1149
1150 return nvme_submit_admin_cmd(dev, &c, NULL);
1151}
1152
5d0f6131 1153int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1154 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1155{
1156 struct nvme_command c;
1157
1158 memset(&c, 0, sizeof(c));
1159 c.features.opcode = nvme_admin_get_features;
a42cecce 1160 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1161 c.features.prp1 = cpu_to_le64(dma_addr);
1162 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1163
08df1e05 1164 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 1165}
1166
5d0f6131
VV		 1167int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1168 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1169{
1170 struct nvme_command c;
1171
1172 memset(&c, 0, sizeof(c));
1173 c.features.opcode = nvme_admin_set_features;
1174 c.features.prp1 = cpu_to_le64(dma_addr);
1175 c.features.fid = cpu_to_le32(fid);
1176 c.features.dword11 = cpu_to_le32(dword11);
1177
bc5fc7e4
MW		 1178 return nvme_submit_admin_cmd(dev, &c, result);
1179}
1180
c30341dc 1181/**
a4aea562 1182 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1183 *
1184 * Schedule controller reset if the command was already aborted once before and
1185 * still hasn't been returned to the driver, or if this is the admin queue.
1186 */
a4aea562 1187static void nvme_abort_req(struct request *req)
c30341dc 1188{
a4aea562
MB		 1189 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1190 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1191 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1192 struct request *abort_req;
1193 struct nvme_cmd_info *abort_cmd;
1194 struct nvme_command cmd;
c30341dc 1195
a4aea562 1196 if (!nvmeq->qid || cmd_rq->aborted) {
7a509a6b
KB		 1197 unsigned long flags;
1198
1199 spin_lock_irqsave(&dev_list_lock, flags);
c30341dc 1200 if (work_busy(&dev->reset_work))
7a509a6b 1201 goto out;
c30341dc
KB		 1202 list_del_init(&dev->node);
1203 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1204 "I/O %d QID %d timeout, reset controller\n",
1205 req->tag, nvmeq->qid);
9ca97374 1206 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc 1207 queue_work(nvme_workq, &dev->reset_work);
7a509a6b
KB		 1208 out:
1209 spin_unlock_irqrestore(&dev_list_lock, flags);
c30341dc
KB		 1210 return;
1211 }
1212
1213 if (!dev->abort_limit)
1214 return;
1215
a4aea562
MB		 1216 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1217 false);
9f173b33 1218 if (IS_ERR(abort_req))
c30341dc
KB		 1219 return;
1220
a4aea562
MB		 1221 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1222 nvme_set_info(abort_cmd, abort_req, abort_completion);
1223
c30341dc
KB		 1224 memset(&cmd, 0, sizeof(cmd));
1225 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1226 cmd.abort.cid = req->tag;
c30341dc 1227 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1228 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1229
1230 --dev->abort_limit;
a4aea562 1231 cmd_rq->aborted = 1;
c30341dc 1232
a4aea562 1233 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1234 nvmeq->qid);
a4aea562
MB		 1235 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1236 dev_warn(nvmeq->q_dmadev,
1237 "Could not abort I/O %d QID %d",
1238 req->tag, nvmeq->qid);
c87fd540 1239 blk_mq_free_request(abort_req);
a4aea562 1240 }
c30341dc
KB		 1241}
1242
a4aea562
MB		 1243static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1244 struct request *req, void *data, bool reserved)
a09115b2 1245{
a4aea562
MB		 1246 struct nvme_queue *nvmeq = data;
1247 void *ctx;
1248 nvme_completion_fn fn;
1249 struct nvme_cmd_info *cmd;
cef6a948
KB		 1250 struct nvme_completion cqe;
1251
1252 if (!blk_mq_request_started(req))
1253 return;
a09115b2 1254
a4aea562 1255 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1256
a4aea562
MB		 1257 if (cmd->ctx == CMD_CTX_CANCELLED)
1258 return;
1259
cef6a948
KB		 1260 if (blk_queue_dying(req->q))
1261 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1262 else
1263 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1264
1265
a4aea562
MB		 1266 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1267 req->tag, nvmeq->qid);
1268 ctx = cancel_cmd_info(cmd, &fn);
1269 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1270}
1271
a4aea562 1272static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1273{
a4aea562
MB		 1274 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1275 struct nvme_queue *nvmeq = cmd->nvmeq;
1276
7a509a6b
KB		 1277 /*
1278 * The aborted req will be completed on receiving the abort req.
1279 * We enable the timer again. If hit twice, it'll cause a device reset,
1280 * as the device then is in a faulty state.
1281 */
1282 int ret = BLK_EH_RESET_TIMER;
1283
a4aea562
MB		 1284 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1285 nvmeq->qid);
c917dfe5 1286
7a509a6b 1287 spin_lock_irq(&nvmeq->q_lock);
c917dfe5
KB		 1288 if (!nvmeq->dev->initialized) {
1289 /*
1290 * Force cancelled command frees the request, which requires we
1291 * return BLK_EH_NOT_HANDLED.
1292 */
1293 nvme_cancel_queue_ios(nvmeq->hctx, req, nvmeq, reserved);
7a509a6b
KB		 1294 ret = BLK_EH_NOT_HANDLED;
1295 } else
1296 nvme_abort_req(req);
1297 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1298
7a509a6b 1299 return ret;
a4aea562 1300}
22404274 1301
a4aea562
MB		 1302static void nvme_free_queue(struct nvme_queue *nvmeq)
1303{
9e866774
MW		 1304 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1305 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1306 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1307 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1308 kfree(nvmeq);
1309}
1310
a1a5ef99 1311static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1312{
1313 int i;
1314
a1a5ef99 1315 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1316 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1317 dev->queue_count--;
a4aea562 1318 dev->queues[i] = NULL;
f435c282 1319 nvme_free_queue(nvmeq);
121c7ad4 1320 }
22404274
KB		 1321}
1322
4d115420
KB		 1323/**
1324 * nvme_suspend_queue - put queue into suspended state
1325 * @nvmeq - queue to suspend
4d115420
KB		 1326 */
1327static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1328{
2b25d981 1329 int vector;
b60503ba 1330
a09115b2 1331 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1332 if (nvmeq->cq_vector == -1) {
1333 spin_unlock_irq(&nvmeq->q_lock);
1334 return 1;
1335 }
1336 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1337 nvmeq->dev->online_queues--;
2b25d981 1338 nvmeq->cq_vector = -1;
a09115b2
MW		 1339 spin_unlock_irq(&nvmeq->q_lock);
1340
aba2080f
MW		 1341 irq_set_affinity_hint(vector, NULL);
1342 free_irq(vector, nvmeq);
b60503ba 1343
4d115420
KB		 1344 return 0;
1345}
b60503ba 1346
4d115420
KB		 1347static void nvme_clear_queue(struct nvme_queue *nvmeq)
1348{
a4aea562
MB		 1349 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1350
22404274
KB		 1351 spin_lock_irq(&nvmeq->q_lock);
1352 nvme_process_cq(nvmeq);
a4aea562
MB		 1353 if (hctx && hctx->tags)
1354 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
22404274 1355 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1356}
1357
4d115420
KB		 1358static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1359{
a4aea562 1360 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1361
1362 if (!nvmeq)
1363 return;
1364 if (nvme_suspend_queue(nvmeq))
1365 return;
1366
0e53d180
KB		 1367 /* Don't tell the adapter to delete the admin queue.
1368 * Don't tell a removed adapter to delete IO queues. */
1369 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1370 adapter_delete_sq(dev, qid);
1371 adapter_delete_cq(dev, qid);
1372 }
0fb59cbc
KB		 1373 if (!qid && dev->admin_q)
1374 blk_mq_freeze_queue_start(dev->admin_q);
4d115420 1375 nvme_clear_queue(nvmeq);
b60503ba
MW		 1376}
1377
1378static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1379 int depth)
b60503ba
MW		 1380{
1381 struct device *dmadev = &dev->pci_dev->dev;
a4aea562 1382 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1383 if (!nvmeq)
1384 return NULL;
1385
4d51abf9
JP		 1386 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1387 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1388 if (!nvmeq->cqes)
1389 goto free_nvmeq;
b60503ba
MW		 1390
1391 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1392 &nvmeq->sq_dma_addr, GFP_KERNEL);
1393 if (!nvmeq->sq_cmds)
1394 goto free_cqdma;
1395
1396 nvmeq->q_dmadev = dmadev;
091b6092 1397 nvmeq->dev = dev;
3193f07b
MW		 1398 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1399 dev->instance, qid);
b60503ba
MW		 1400 spin_lock_init(&nvmeq->q_lock);
1401 nvmeq->cq_head = 0;
82123460 1402 nvmeq->cq_phase = 1;
b80d5ccc 1403 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1404 nvmeq->q_depth = depth;
c30341dc 1405 nvmeq->qid = qid;
22404274 1406 dev->queue_count++;
a4aea562 1407 dev->queues[qid] = nvmeq;
b60503ba
MW		 1408
1409 return nvmeq;
1410
1411 free_cqdma:
68b8eca5 1412 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1413 nvmeq->cq_dma_addr);
1414 free_nvmeq:
1415 kfree(nvmeq);
1416 return NULL;
1417}
1418
3001082c
MW		 1419static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1420 const char *name)
1421{
58ffacb5
MW		 1422 if (use_threaded_interrupts)
1423 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1424 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1425 name, nvmeq);
3001082c 1426 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1427 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1428}
1429
22404274 1430static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1431{
22404274 1432 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1433
7be50e93 1434 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1435 nvmeq->sq_tail = 0;
1436 nvmeq->cq_head = 0;
1437 nvmeq->cq_phase = 1;
b80d5ccc 1438 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1439 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1440 dev->online_queues++;
7be50e93 1441 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1442}
1443
1444static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1445{
1446 struct nvme_dev *dev = nvmeq->dev;
1447 int result;
3f85d50b 1448
2b25d981 1449 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1450 result = adapter_alloc_cq(dev, qid, nvmeq);
1451 if (result < 0)
22404274 1452 return result;
b60503ba
MW		 1453
1454 result = adapter_alloc_sq(dev, qid, nvmeq);
1455 if (result < 0)
1456 goto release_cq;
1457
3193f07b 1458 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1459 if (result < 0)
1460 goto release_sq;
1461
22404274 1462 nvme_init_queue(nvmeq, qid);
22404274 1463 return result;
b60503ba
MW		 1464
1465 release_sq:
1466 adapter_delete_sq(dev, qid);
1467 release_cq:
1468 adapter_delete_cq(dev, qid);
22404274 1469 return result;
b60503ba
MW		 1470}
1471
ba47e386
MW		 1472static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1473{
1474 unsigned long timeout;
1475 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1476
1477 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1478
1479 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1480 msleep(100);
1481 if (fatal_signal_pending(current))
1482 return -EINTR;
1483 if (time_after(jiffies, timeout)) {
1484 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1485 "Device not ready; aborting %s\n", enabled ?
1486 "initialisation" : "reset");
ba47e386
MW		 1487 return -ENODEV;
1488 }
1489 }
1490
1491 return 0;
1492}
1493
1494/*
1495 * If the device has been passed off to us in an enabled state, just clear
1496 * the enabled bit. The spec says we should set the 'shutdown notification
1497 * bits', but doing so may cause the device to complete commands to the
1498 * admin queue ... and we don't know what memory that might be pointing at!
1499 */
1500static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1501{
01079522
DM		 1502 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1503 dev->ctrl_config &= ~NVME_CC_ENABLE;
1504 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1505
ba47e386
MW		 1506 return nvme_wait_ready(dev, cap, false);
1507}
1508
1509static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1510{
01079522
DM		 1511 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1512 dev->ctrl_config |= NVME_CC_ENABLE;
1513 writel(dev->ctrl_config, &dev->bar->cc);
1514
ba47e386
MW		 1515 return nvme_wait_ready(dev, cap, true);
1516}
1517
1894d8f1
KB		 1518static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1519{
1520 unsigned long timeout;
1894d8f1 1521
01079522
DM		 1522 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1523 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1524
1525 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1526
2484f407 1527 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1528 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1529 NVME_CSTS_SHST_CMPLT) {
1530 msleep(100);
1531 if (fatal_signal_pending(current))
1532 return -EINTR;
1533 if (time_after(jiffies, timeout)) {
1534 dev_err(&dev->pci_dev->dev,
1535 "Device shutdown incomplete; abort shutdown\n");
1536 return -ENODEV;
1537 }
1538 }
1539
1540 return 0;
1541}
1542
a4aea562
MB		 1543static struct blk_mq_ops nvme_mq_admin_ops = {
1544 .queue_rq = nvme_admin_queue_rq,
1545 .map_queue = blk_mq_map_queue,
1546 .init_hctx = nvme_admin_init_hctx,
2c30540b 1547 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1548 .init_request = nvme_admin_init_request,
1549 .timeout = nvme_timeout,
1550};
1551
1552static struct blk_mq_ops nvme_mq_ops = {
1553 .queue_rq = nvme_queue_rq,
1554 .map_queue = blk_mq_map_queue,
1555 .init_hctx = nvme_init_hctx,
2c30540b 1556 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1557 .init_request = nvme_init_request,
1558 .timeout = nvme_timeout,
1559};
1560
ea191d2f
KB		 1561static void nvme_dev_remove_admin(struct nvme_dev *dev)
1562{
1563 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1564 blk_cleanup_queue(dev->admin_q);
1565 blk_mq_free_tag_set(&dev->admin_tagset);
1566 }
1567}
1568
a4aea562
MB		 1569static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1570{
1571 if (!dev->admin_q) {
1572 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1573 dev->admin_tagset.nr_hw_queues = 1;
1574 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1575 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1576 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
ac3dd5bd 1577 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1578 dev->admin_tagset.driver_data = dev;
1579
1580 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1581 return -ENOMEM;
1582
1583 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1584 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1585 blk_mq_free_tag_set(&dev->admin_tagset);
1586 return -ENOMEM;
1587 }
ea191d2f
KB		 1588 if (!blk_get_queue(dev->admin_q)) {
1589 nvme_dev_remove_admin(dev);
1590 return -ENODEV;
1591 }
0fb59cbc
KB		 1592 } else
1593 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1594
1595 return 0;
1596}
1597
8d85fce7 1598static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1599{
ba47e386 1600 int result;
b60503ba 1601 u32 aqa;
ba47e386 1602 u64 cap = readq(&dev->bar->cap);
b60503ba 1603 struct nvme_queue *nvmeq;
1d090624
KB		 1604 unsigned page_shift = PAGE_SHIFT;
1605 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1606 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1607
1608 if (page_shift < dev_page_min) {
1609 dev_err(&dev->pci_dev->dev,
1610 "Minimum device page size (%u) too large for "
1611 "host (%u)\n", 1 << dev_page_min,
1612 1 << page_shift);
1613 return -ENODEV;
1614 }
1615 if (page_shift > dev_page_max) {
1616 dev_info(&dev->pci_dev->dev,
1617 "Device maximum page size (%u) smaller than "
1618 "host (%u); enabling work-around\n",
1619 1 << dev_page_max, 1 << page_shift);
1620 page_shift = dev_page_max;
1621 }
b60503ba 1622
ba47e386
MW		 1623 result = nvme_disable_ctrl(dev, cap);
1624 if (result < 0)
1625 return result;
b60503ba 1626
a4aea562 1627 nvmeq = dev->queues[0];
cd638946 1628 if (!nvmeq) {
2b25d981 1629 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1630 if (!nvmeq)
1631 return -ENOMEM;
cd638946 1632 }
b60503ba
MW		 1633
1634 aqa = nvmeq->q_depth - 1;
1635 aqa |= aqa << 16;
1636
1d090624
KB		 1637 dev->page_size = 1 << page_shift;
1638
01079522 1639 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1640 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1641 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1642 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1643
1644 writel(aqa, &dev->bar->aqa);
1645 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1646 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1647
ba47e386 1648 result = nvme_enable_ctrl(dev, cap);
025c557a 1649 if (result)
a4aea562
MB		 1650 goto free_nvmeq;
1651
2b25d981 1652 nvmeq->cq_vector = 0;
3193f07b 1653 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1654 if (result)
0fb59cbc 1655 goto free_nvmeq;
025c557a 1656
b60503ba 1657 return result;
a4aea562 1658
a4aea562
MB		 1659 free_nvmeq:
1660 nvme_free_queues(dev, 0);
1661 return result;
b60503ba
MW		 1662}
1663
5d0f6131 1664struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1665 unsigned long addr, unsigned length)
b60503ba 1666{
36c14ed9 1667 int i, err, count, nents, offset;
7fc3cdab
MW		 1668 struct scatterlist *sg;
1669 struct page **pages;
eca18b23 1670 struct nvme_iod *iod;
36c14ed9
MW		 1671
1672 if (addr & 3)
eca18b23 1673 return ERR_PTR(-EINVAL);
5460fc03 1674 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1675 return ERR_PTR(-EINVAL);
7fc3cdab 1676
36c14ed9 1677 offset = offset_in_page(addr);
7fc3cdab
MW		 1678 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1679 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1680 if (!pages)
1681 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1682
1683 err = get_user_pages_fast(addr, count, 1, pages);
1684 if (err < count) {
1685 count = err;
1686 err = -EFAULT;
1687 goto put_pages;
1688 }
7fc3cdab 1689
6808c5fb 1690 err = -ENOMEM;
ac3dd5bd 1691 iod = __nvme_alloc_iod(count, length, dev, 0, GFP_KERNEL);
6808c5fb
S		 1692 if (!iod)
1693 goto put_pages;
1694
eca18b23 1695 sg = iod->sg;
36c14ed9 1696 sg_init_table(sg, count);
d0ba1e49
MW		 1697 for (i = 0; i < count; i++) {
1698 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1699 min_t(unsigned, length, PAGE_SIZE - offset),
1700 offset);
d0ba1e49
MW		 1701 length -= (PAGE_SIZE - offset);
1702 offset = 0;
7fc3cdab 1703 }
fe304c43 1704 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1705 iod->nents = count;
7fc3cdab 1706
7fc3cdab
MW		 1707 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1708 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1709 if (!nents)
eca18b23 1710 goto free_iod;
b60503ba 1711
7fc3cdab 1712 kfree(pages);
eca18b23 1713 return iod;
b60503ba 1714
eca18b23
MW		 1715 free_iod:
1716 kfree(iod);
7fc3cdab
MW		 1717 put_pages:
1718 for (i = 0; i < count; i++)
1719 put_page(pages[i]);
1720 kfree(pages);
eca18b23 1721 return ERR_PTR(err);
7fc3cdab 1722}
b60503ba 1723
5d0f6131 1724void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1725 struct nvme_iod *iod)
7fc3cdab 1726{
1c2ad9fa 1727 int i;
b60503ba 1728
1c2ad9fa
MW		 1729 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1730 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1731
1c2ad9fa
MW		 1732 for (i = 0; i < iod->nents; i++)
1733 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1734}
b60503ba 1735
a53295b6
MW		 1736static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1737{
1738 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1739 struct nvme_user_io io;
1740 struct nvme_command c;
f410c680
KB		 1741 unsigned length, meta_len;
1742 int status, i;
1743 struct nvme_iod *iod, *meta_iod = NULL;
1744 dma_addr_t meta_dma_addr;
1745 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1746
1747 if (copy_from_user(&io, uio, sizeof(io)))
1748 return -EFAULT;
6c7d4945 1749 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1750 meta_len = (io.nblocks + 1) * ns->ms;
1751
1752 if (meta_len && ((io.metadata & 3) || !io.metadata))
1753 return -EINVAL;
6c7d4945
MW		 1754
1755 switch (io.opcode) {
1756 case nvme_cmd_write:
1757 case nvme_cmd_read:
6bbf1acd 1758 case nvme_cmd_compare:
eca18b23 1759 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1760 break;
6c7d4945 1761 default:
6bbf1acd 1762 return -EINVAL;
6c7d4945
MW		 1763 }
1764
eca18b23
MW		 1765 if (IS_ERR(iod))
1766 return PTR_ERR(iod);
a53295b6
MW		 1767
1768 memset(&c, 0, sizeof(c));
1769 c.rw.opcode = io.opcode;
1770 c.rw.flags = io.flags;
6c7d4945 1771 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1772 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1773 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1774 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1775 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1776 c.rw.reftag = cpu_to_le32(io.reftag);
1777 c.rw.apptag = cpu_to_le16(io.apptag);
1778 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1779
1780 if (meta_len) {
1b56749e
KB		 1781 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1782 meta_len);
f410c680
KB		 1783 if (IS_ERR(meta_iod)) {
1784 status = PTR_ERR(meta_iod);
1785 meta_iod = NULL;
1786 goto unmap;
1787 }
1788
1789 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1790 &meta_dma_addr, GFP_KERNEL);
1791 if (!meta_mem) {
1792 status = -ENOMEM;
1793 goto unmap;
1794 }
1795
1796 if (io.opcode & 1) {
1797 int meta_offset = 0;
1798
1799 for (i = 0; i < meta_iod->nents; i++) {
1800 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1801 meta_iod->sg[i].offset;
1802 memcpy(meta_mem + meta_offset, meta,
1803 meta_iod->sg[i].length);
1804 kunmap_atomic(meta);
1805 meta_offset += meta_iod->sg[i].length;
1806 }
1807 }
1808
1809 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1810 }
1811
edd10d33
KB		 1812 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1813 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1814 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1815
b77954cb
MW		 1816 if (length != (io.nblocks + 1) << ns->lba_shift)
1817 status = -ENOMEM;
1818 else
a4aea562 1819 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
a53295b6 1820
f410c680
KB		 1821 if (meta_len) {
1822 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1823 int meta_offset = 0;
1824
1825 for (i = 0; i < meta_iod->nents; i++) {
1826 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1827 meta_iod->sg[i].offset;
1828 memcpy(meta, meta_mem + meta_offset,
1829 meta_iod->sg[i].length);
1830 kunmap_atomic(meta);
1831 meta_offset += meta_iod->sg[i].length;
1832 }
1833 }
1834
1835 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1836 meta_dma_addr);
1837 }
1838
1839 unmap:
1c2ad9fa 1840 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1841 nvme_free_iod(dev, iod);
f410c680
KB		 1842
1843 if (meta_iod) {
1844 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1845 nvme_free_iod(dev, meta_iod);
1846 }
1847
a53295b6
MW		 1848 return status;
1849}
1850
a4aea562
MB		 1851static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1852 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1853{
7963e521 1854 struct nvme_passthru_cmd cmd;
6ee44cdc 1855 struct nvme_command c;
eca18b23 1856 int status, length;
c7d36ab8 1857 struct nvme_iod *uninitialized_var(iod);
94f370ca 1858 unsigned timeout;
6ee44cdc 1859
6bbf1acd
MW		 1860 if (!capable(CAP_SYS_ADMIN))
1861 return -EACCES;
1862 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1863 return -EFAULT;
6ee44cdc
MW		 1864
1865 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1866 c.common.opcode = cmd.opcode;
1867 c.common.flags = cmd.flags;
1868 c.common.nsid = cpu_to_le32(cmd.nsid);
1869 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1870 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1871 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1872 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1873 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1874 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1875 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1876 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1877
1878 length = cmd.data_len;
1879 if (cmd.data_len) {
49742188
MW		 1880 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1881 length);
eca18b23
MW		 1882 if (IS_ERR(iod))
1883 return PTR_ERR(iod);
edd10d33
KB		 1884 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1885 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1886 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1887 }
1888
94f370ca
KB		 1889 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1890 ADMIN_TIMEOUT;
a4aea562 1891
6bbf1acd 1892 if (length != cmd.data_len)
b77954cb 1893 status = -ENOMEM;
a4aea562
MB		 1894 else if (ns) {
1895 struct request *req;
1896
1897 req = blk_mq_alloc_request(ns->queue, WRITE,
1898 (GFP_KERNEL|__GFP_WAIT), false);
97fe3832
JA		 1899 if (IS_ERR(req))
1900 status = PTR_ERR(req);
a4aea562
MB		 1901 else {
1902 status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1903 timeout);
9d135bb8 1904 blk_mq_free_request(req);
a4aea562
MB		 1905 }
1906 } else
1907 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
eca18b23 1908
6bbf1acd 1909 if (cmd.data_len) {
1c2ad9fa 1910 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1911 nvme_free_iod(dev, iod);
6bbf1acd 1912 }
f4f117f6 1913
cf90bc48 1914 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1915 sizeof(cmd.result)))
1916 status = -EFAULT;
1917
6ee44cdc
MW		 1918 return status;
1919}
1920
b60503ba
MW		 1921static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1922 unsigned long arg)
1923{
1924 struct nvme_ns *ns = bdev->bd_disk->private_data;
1925
1926 switch (cmd) {
6bbf1acd 1927 case NVME_IOCTL_ID:
c3bfe717 1928 force_successful_syscall_return();
6bbf1acd
MW		 1929 return ns->ns_id;
1930 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1931 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1932 case NVME_IOCTL_IO_CMD:
a4aea562 1933 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1934 case NVME_IOCTL_SUBMIT_IO:
1935 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1936 case SG_GET_VERSION_NUM:
1937 return nvme_sg_get_version_num((void __user *)arg);
1938 case SG_IO:
1939 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1940 default:
1941 return -ENOTTY;
1942 }
1943}
1944
320a3827
KB		 1945#ifdef CONFIG_COMPAT
1946static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1947 unsigned int cmd, unsigned long arg)
1948{
320a3827
KB		 1949 switch (cmd) {
1950 case SG_IO:
e179729a 1951 return -ENOIOCTLCMD;
320a3827
KB		 1952 }
1953 return nvme_ioctl(bdev, mode, cmd, arg);
1954}
1955#else
1956#define nvme_compat_ioctl NULL
1957#endif
1958
9ac27090
KB		 1959static int nvme_open(struct block_device *bdev, fmode_t mode)
1960{
9e60352c
KB		 1961 int ret = 0;
1962 struct nvme_ns *ns;
9ac27090 1963
9e60352c
KB		 1964 spin_lock(&dev_list_lock);
1965 ns = bdev->bd_disk->private_data;
1966 if (!ns)
1967 ret = -ENXIO;
1968 else if (!kref_get_unless_zero(&ns->dev->kref))
1969 ret = -ENXIO;
1970 spin_unlock(&dev_list_lock);
1971
1972 return ret;
9ac27090
KB		 1973}
1974
1975static void nvme_free_dev(struct kref *kref);
1976
1977static void nvme_release(struct gendisk *disk, fmode_t mode)
1978{
1979 struct nvme_ns *ns = disk->private_data;
1980 struct nvme_dev *dev = ns->dev;
1981
1982 kref_put(&dev->kref, nvme_free_dev);
1983}
1984
4cc09e2d
KB		 1985static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1986{
1987 /* some standard values */
1988 geo->heads = 1 << 6;
1989 geo->sectors = 1 << 5;
1990 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1991 return 0;
1992}
1993
e1e5e564
KB		 1994static void nvme_config_discard(struct nvme_ns *ns)
1995{
1996 u32 logical_block_size = queue_logical_block_size(ns->queue);
1997 ns->queue->limits.discard_zeroes_data = 0;
1998 ns->queue->limits.discard_alignment = logical_block_size;
1999 ns->queue->limits.discard_granularity = logical_block_size;
2000 ns->queue->limits.max_discard_sectors = 0xffffffff;
2001 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
2002}
2003
2004static int nvme_noop_verify(struct blk_integrity_iter *iter)
2005{
2006 return 0;
2007}
2008
2009static int nvme_noop_generate(struct blk_integrity_iter *iter)
2010{
2011 return 0;
2012}
2013
2014struct blk_integrity nvme_meta_noop = {
2015 .name = "NVME_META_NOOP",
2016 .generate_fn = nvme_noop_generate,
2017 .verify_fn = nvme_noop_verify,
2018};
2019
2020static void nvme_init_integrity(struct nvme_ns *ns)
2021{
2022 struct blk_integrity integrity;
2023
2024 switch (ns->pi_type) {
2025 case NVME_NS_DPS_PI_TYPE3:
2026 integrity = t10_pi_type3_crc;
2027 break;
2028 case NVME_NS_DPS_PI_TYPE1:
2029 case NVME_NS_DPS_PI_TYPE2:
2030 integrity = t10_pi_type1_crc;
2031 break;
2032 default:
2033 integrity = nvme_meta_noop;
2034 break;
2035 }
2036 integrity.tuple_size = ns->ms;
2037 blk_integrity_register(ns->disk, &integrity);
2038 blk_queue_max_integrity_segments(ns->queue, 1);
2039}
2040
1b9dbf7f
KB		 2041static int nvme_revalidate_disk(struct gendisk *disk)
2042{
2043 struct nvme_ns *ns = disk->private_data;
2044 struct nvme_dev *dev = ns->dev;
2045 struct nvme_id_ns *id;
2046 dma_addr_t dma_addr;
e1e5e564
KB		 2047 int lbaf, pi_type, old_ms;
2048 unsigned short bs;
1b9dbf7f
KB		 2049
2050 id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
2051 GFP_KERNEL);
2052 if (!id) {
2053 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
2054 __func__);
2055 return 0;
2056 }
e1e5e564
KB		 2057 if (nvme_identify(dev, ns->ns_id, 0, dma_addr)) {
2058 dev_warn(&dev->pci_dev->dev,
2059 "identify failed ns:%d, setting capacity to 0\n",
2060 ns->ns_id);
2061 memset(id, 0, sizeof(*id));
2062 }
1b9dbf7f 2063
e1e5e564
KB		 2064 old_ms = ns->ms;
2065 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1b9dbf7f 2066 ns->lba_shift = id->lbaf[lbaf].ds;
e1e5e564
KB		 2067 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
2068
2069 /*
2070 * If identify namespace failed, use default 512 byte block size so
2071 * block layer can use before failing read/write for 0 capacity.
2072 */
2073 if (ns->lba_shift == 0)
2074 ns->lba_shift = 9;
2075 bs = 1 << ns->lba_shift;
2076
2077 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2078 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2079 id->dps & NVME_NS_DPS_PI_MASK : 0;
2080
2081 if (disk->integrity && (ns->pi_type != pi_type || ns->ms != old_ms ||
2082 bs != queue_logical_block_size(disk->queue) ||
2083 (ns->ms && id->flbas & NVME_NS_FLBAS_META_EXT)))
2084 blk_integrity_unregister(disk);
2085
2086 ns->pi_type = pi_type;
2087 blk_queue_logical_block_size(ns->queue, bs);
2088
2089 if (ns->ms && !disk->integrity && (disk->flags & GENHD_FL_UP) &&
2090 !(id->flbas & NVME_NS_FLBAS_META_EXT))
2091 nvme_init_integrity(ns);
2092
2093 if (id->ncap == 0 || (ns->ms && !disk->integrity))
2094 set_capacity(disk, 0);
2095 else
2096 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2097
2098 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2099 nvme_config_discard(ns);
1b9dbf7f 2100
1b9dbf7f
KB		 2101 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
2102 return 0;
2103}
2104
b60503ba
MW		 2105static const struct block_device_operations nvme_fops = {
2106 .owner = THIS_MODULE,
2107 .ioctl = nvme_ioctl,
320a3827 2108 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 2109 .open = nvme_open,
2110 .release = nvme_release,
4cc09e2d 2111 .getgeo = nvme_getgeo,
1b9dbf7f 2112 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 2113};
2114
1fa6aead
MW		 2115static int nvme_kthread(void *data)
2116{
d4b4ff8e 2117 struct nvme_dev *dev, *next;
1fa6aead
MW		 2118
2119 while (!kthread_should_stop()) {
564a232c 2120 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 2121 spin_lock(&dev_list_lock);
d4b4ff8e 2122 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 2123 int i;
d4b4ff8e
KB		 2124 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
2125 dev->initialized) {
2126 if (work_busy(&dev->reset_work))
2127 continue;
2128 list_del_init(&dev->node);
2129 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 2130 "Failed status: %x, reset controller\n",
2131 readl(&dev->bar->csts));
9ca97374 2132 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 2133 queue_work(nvme_workq, &dev->reset_work);
2134 continue;
2135 }
1fa6aead 2136 for (i = 0; i < dev->queue_count; i++) {
a4aea562 2137 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 2138 if (!nvmeq)
2139 continue;
1fa6aead 2140 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 2141 nvme_process_cq(nvmeq);
6fccf938
KB		 2142
2143 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 2144 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 2145 break;
2146 dev->event_limit--;
2147 }
1fa6aead
MW		 2148 spin_unlock_irq(&nvmeq->q_lock);
2149 }
2150 }
2151 spin_unlock(&dev_list_lock);
acb7aa0d 2152 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 2153 }
2154 return 0;
2155}
2156
e1e5e564 2157static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
b60503ba
MW		 2158{
2159 struct nvme_ns *ns;
2160 struct gendisk *disk;
a4aea562 2161 int node = dev_to_node(&dev->pci_dev->dev);
b60503ba 2162
a4aea562 2163 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba 2164 if (!ns)
e1e5e564
KB		 2165 return;
2166
a4aea562 2167 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 2168 if (IS_ERR(ns->queue))
b60503ba 2169 goto out_free_ns;
4eeb9215
MW		 2170 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2171 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 2172 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 2173 ns->dev = dev;
2174 ns->queue->queuedata = ns;
2175
a4aea562 2176 disk = alloc_disk_node(0, node);
b60503ba
MW		 2177 if (!disk)
2178 goto out_free_queue;
a4aea562 2179
5aff9382 2180 ns->ns_id = nsid;
b60503ba 2181 ns->disk = disk;
e1e5e564
KB		 2182 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2183 list_add_tail(&ns->list, &dev->namespaces);
2184
e9ef4636 2185 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 2186 if (dev->max_hw_sectors)
2187 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 2188 if (dev->stripe_size)
2189 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2190 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2191 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 2192
2193 disk->major = nvme_major;
469071a3 2194 disk->first_minor = 0;
b60503ba
MW		 2195 disk->fops = &nvme_fops;
2196 disk->private_data = ns;
2197 disk->queue = ns->queue;
b3fffdef 2198 disk->driverfs_dev = dev->device;
469071a3 2199 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2200 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba 2201
e1e5e564
KB		 2202 /*
2203 * Initialize capacity to 0 until we establish the namespace format and
2204 * setup integrity extentions if necessary. The revalidate_disk after
2205 * add_disk allows the driver to register with integrity if the format
2206 * requires it.
2207 */
2208 set_capacity(disk, 0);
2209 nvme_revalidate_disk(ns->disk);
2210 add_disk(ns->disk);
2211 if (ns->ms)
2212 revalidate_disk(ns->disk);
2213 return;
b60503ba
MW		 2214 out_free_queue:
2215 blk_cleanup_queue(ns->queue);
2216 out_free_ns:
2217 kfree(ns);
b60503ba
MW		 2218}
2219
42f61420
KB		 2220static void nvme_create_io_queues(struct nvme_dev *dev)
2221{
a4aea562 2222 unsigned i;
42f61420 2223
a4aea562 2224 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2225 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2226 break;
2227
a4aea562
MB		 2228 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2229 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 2230 break;
2231}
2232
b3b06812 2233static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2234{
2235 int status;
2236 u32 result;
b3b06812 2237 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2238
df348139 2239 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2240 &result);
27e8166c
MW		 2241 if (status < 0)
2242 return status;
2243 if (status > 0) {
2244 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2245 status);
badc34d4 2246 return 0;
27e8166c 2247 }
b60503ba
MW		 2248 return min(result & 0xffff, result >> 16) + 1;
2249}
2250
9d713c2b
KB		 2251static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2252{
b80d5ccc 2253 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2254}
2255
8d85fce7 2256static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2257{
a4aea562 2258 struct nvme_queue *adminq = dev->queues[0];
fa08a396 2259 struct pci_dev *pdev = dev->pci_dev;
42f61420 2260 int result, i, vecs, nr_io_queues, size;
b60503ba 2261
42f61420 2262 nr_io_queues = num_possible_cpus();
b348b7d5 2263 result = set_queue_count(dev, nr_io_queues);
badc34d4 2264 if (result <= 0)
1b23484b 2265 return result;
b348b7d5
MW		 2266 if (result < nr_io_queues)
2267 nr_io_queues = result;
b60503ba 2268
9d713c2b
KB		 2269 size = db_bar_size(dev, nr_io_queues);
2270 if (size > 8192) {
f1938f6e 2271 iounmap(dev->bar);
9d713c2b
KB		 2272 do {
2273 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2274 if (dev->bar)
2275 break;
2276 if (!--nr_io_queues)
2277 return -ENOMEM;
2278 size = db_bar_size(dev, nr_io_queues);
2279 } while (1);
f1938f6e 2280 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2281 adminq->q_db = dev->dbs;
f1938f6e
MW		 2282 }
2283
9d713c2b 2284 /* Deregister the admin queue's interrupt */
3193f07b 2285 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2286
e32efbfc
JA		 2287 /*
2288 * If we enable msix early due to not intx, disable it again before
2289 * setting up the full range we need.
2290 */
2291 if (!pdev->irq)
2292 pci_disable_msix(pdev);
2293
be577fab 2294 for (i = 0; i < nr_io_queues; i++)
1b23484b 2295 dev->entry[i].entry = i;
be577fab
AG		 2296 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2297 if (vecs < 0) {
2298 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2299 if (vecs < 0) {
2300 vecs = 1;
2301 } else {
2302 for (i = 0; i < vecs; i++)
2303 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2304 }
2305 }
2306
063a8096
MW		 2307 /*
2308 * Should investigate if there's a performance win from allocating
2309 * more queues than interrupt vectors; it might allow the submission
2310 * path to scale better, even if the receive path is limited by the
2311 * number of interrupts.
2312 */
2313 nr_io_queues = vecs;
42f61420 2314 dev->max_qid = nr_io_queues;
063a8096 2315
3193f07b 2316 result = queue_request_irq(dev, adminq, adminq->irqname);
a4aea562 2317 if (result)
22404274 2318 goto free_queues;
1b23484b 2319
cd638946 2320 /* Free previously allocated queues that are no longer usable */
42f61420 2321 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2322 nvme_create_io_queues(dev);
9ecdc946 2323
22404274 2324 return 0;
b60503ba 2325
22404274 2326 free_queues:
a1a5ef99 2327 nvme_free_queues(dev, 1);
22404274 2328 return result;
b60503ba
MW		 2329}
2330
422ef0c7
MW		 2331/*
2332 * Return: error value if an error occurred setting up the queues or calling
2333 * Identify Device. 0 if these succeeded, even if adding some of the
2334 * namespaces failed. At the moment, these failures are silent. TBD which
2335 * failures should be reported.
2336 */
8d85fce7 2337static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2338{
68608c26 2339 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2340 int res;
2341 unsigned nn, i;
51814232 2342 struct nvme_id_ctrl *ctrl;
bc5fc7e4 2343 void *mem;
b60503ba 2344 dma_addr_t dma_addr;
159b67d7 2345 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2346
e1e5e564 2347 mem = dma_alloc_coherent(&pdev->dev, 4096, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2348 if (!mem)
2349 return -ENOMEM;
b60503ba 2350
bc5fc7e4 2351 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2352 if (res) {
27e8166c 2353 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
e1e5e564
KB		 2354 dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr);
2355 return -EIO;
b60503ba
MW		 2356 }
2357
bc5fc7e4 2358 ctrl = mem;
51814232 2359 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2360 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2361 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2362 dev->vwc = ctrl->vwc;
6fccf938 2363 dev->event_limit = min(ctrl->aerl + 1, 8);
51814232
MW		 2364 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2365 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2366 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2367 if (ctrl->mdts)
8fc23e03 2368 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2369 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2370 (pdev->device == 0x0953) && ctrl->vs[3]) {
2371 unsigned int max_hw_sectors;
2372
159b67d7 2373 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2374 max_hw_sectors = dev->stripe_size >> (shift - 9);
2375 if (dev->max_hw_sectors) {
2376 dev->max_hw_sectors = min(max_hw_sectors,
2377 dev->max_hw_sectors);
2378 } else
2379 dev->max_hw_sectors = max_hw_sectors;
2380 }
e1e5e564 2381 dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr);
a4aea562
MB		 2382
2383 dev->tagset.ops = &nvme_mq_ops;
2384 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2385 dev->tagset.timeout = NVME_IO_TIMEOUT;
2386 dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2387 dev->tagset.queue_depth =
2388 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ac3dd5bd 2389 dev->tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 2390 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2391 dev->tagset.driver_data = dev;
2392
2393 if (blk_mq_alloc_tag_set(&dev->tagset))
e1e5e564 2394 return 0;
b60503ba 2395
e1e5e564
KB		 2396 for (i = 1; i <= nn; i++)
2397 nvme_alloc_ns(dev, i);
b60503ba 2398
e1e5e564 2399 return 0;
b60503ba
MW		 2400}
2401
0877cb0d
KB		 2402static int nvme_dev_map(struct nvme_dev *dev)
2403{
42f61420 2404 u64 cap;
0877cb0d
KB		 2405 int bars, result = -ENOMEM;
2406 struct pci_dev *pdev = dev->pci_dev;
2407
2408 if (pci_enable_device_mem(pdev))
2409 return result;
2410
2411 dev->entry[0].vector = pdev->irq;
2412 pci_set_master(pdev);
2413 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2414 if (!bars)
2415 goto disable_pci;
2416
0877cb0d
KB		 2417 if (pci_request_selected_regions(pdev, bars, "nvme"))
2418 goto disable_pci;
2419
052d0efa
RK		 2420 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2421 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2422 goto disable;
0877cb0d 2423
0877cb0d
KB		 2424 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2425 if (!dev->bar)
2426 goto disable;
e32efbfc 2427
0e53d180
KB		 2428 if (readl(&dev->bar->csts) == -1) {
2429 result = -ENODEV;
2430 goto unmap;
2431 }
e32efbfc
JA		 2432
2433 /*
2434 * Some devices don't advertse INTx interrupts, pre-enable a single
2435 * MSIX vec for setup. We'll adjust this later.
2436 */
2437 if (!pdev->irq) {
2438 result = pci_enable_msix(pdev, dev->entry, 1);
2439 if (result < 0)
2440 goto unmap;
2441 }
2442
42f61420
KB		 2443 cap = readq(&dev->bar->cap);
2444 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2445 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2446 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2447
2448 return 0;
2449
0e53d180
KB		 2450 unmap:
2451 iounmap(dev->bar);
2452 dev->bar = NULL;
0877cb0d
KB		 2453 disable:
2454 pci_release_regions(pdev);
2455 disable_pci:
2456 pci_disable_device(pdev);
2457 return result;
2458}
2459
2460static void nvme_dev_unmap(struct nvme_dev *dev)
2461{
2462 if (dev->pci_dev->msi_enabled)
2463 pci_disable_msi(dev->pci_dev);
2464 else if (dev->pci_dev->msix_enabled)
2465 pci_disable_msix(dev->pci_dev);
2466
2467 if (dev->bar) {
2468 iounmap(dev->bar);
2469 dev->bar = NULL;
9a6b9458 2470 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2471 }
2472
0877cb0d
KB		 2473 if (pci_is_enabled(dev->pci_dev))
2474 pci_disable_device(dev->pci_dev);
2475}
2476
4d115420
KB		 2477struct nvme_delq_ctx {
2478 struct task_struct *waiter;
2479 struct kthread_worker *worker;
2480 atomic_t refcount;
2481};
2482
2483static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2484{
2485 dq->waiter = current;
2486 mb();
2487
2488 for (;;) {
2489 set_current_state(TASK_KILLABLE);
2490 if (!atomic_read(&dq->refcount))
2491 break;
2492 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2493 fatal_signal_pending(current)) {
0fb59cbc
KB		 2494 /*
2495 * Disable the controller first since we can't trust it
2496 * at this point, but leave the admin queue enabled
2497 * until all queue deletion requests are flushed.
2498 * FIXME: This may take a while if there are more h/w
2499 * queues than admin tags.
2500 */
4d115420 2501 set_current_state(TASK_RUNNING);
4d115420 2502 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2503 nvme_clear_queue(dev->queues[0]);
4d115420 2504 flush_kthread_worker(dq->worker);
0fb59cbc 2505 nvme_disable_queue(dev, 0);
4d115420
KB		 2506 return;
2507 }
2508 }
2509 set_current_state(TASK_RUNNING);
2510}
2511
2512static void nvme_put_dq(struct nvme_delq_ctx *dq)
2513{
2514 atomic_dec(&dq->refcount);
2515 if (dq->waiter)
2516 wake_up_process(dq->waiter);
2517}
2518
2519static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2520{
2521 atomic_inc(&dq->refcount);
2522 return dq;
2523}
2524
2525static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2526{
2527 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2528
2529 nvme_clear_queue(nvmeq);
2530 nvme_put_dq(dq);
2531}
2532
2533static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2534 kthread_work_func_t fn)
2535{
2536 struct nvme_command c;
2537
2538 memset(&c, 0, sizeof(c));
2539 c.delete_queue.opcode = opcode;
2540 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2541
2542 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2543 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2544 ADMIN_TIMEOUT);
4d115420
KB		 2545}
2546
2547static void nvme_del_cq_work_handler(struct kthread_work *work)
2548{
2549 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2550 cmdinfo.work);
2551 nvme_del_queue_end(nvmeq);
2552}
2553
2554static int nvme_delete_cq(struct nvme_queue *nvmeq)
2555{
2556 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2557 nvme_del_cq_work_handler);
2558}
2559
2560static void nvme_del_sq_work_handler(struct kthread_work *work)
2561{
2562 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2563 cmdinfo.work);
2564 int status = nvmeq->cmdinfo.status;
2565
2566 if (!status)
2567 status = nvme_delete_cq(nvmeq);
2568 if (status)
2569 nvme_del_queue_end(nvmeq);
2570}
2571
2572static int nvme_delete_sq(struct nvme_queue *nvmeq)
2573{
2574 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2575 nvme_del_sq_work_handler);
2576}
2577
2578static void nvme_del_queue_start(struct kthread_work *work)
2579{
2580 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2581 cmdinfo.work);
4d115420
KB		 2582 if (nvme_delete_sq(nvmeq))
2583 nvme_del_queue_end(nvmeq);
2584}
2585
2586static void nvme_disable_io_queues(struct nvme_dev *dev)
2587{
2588 int i;
2589 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2590 struct nvme_delq_ctx dq;
2591 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2592 &worker, "nvme%d", dev->instance);
2593
2594 if (IS_ERR(kworker_task)) {
2595 dev_err(&dev->pci_dev->dev,
2596 "Failed to create queue del task\n");
2597 for (i = dev->queue_count - 1; i > 0; i--)
2598 nvme_disable_queue(dev, i);
2599 return;
2600 }
2601
2602 dq.waiter = NULL;
2603 atomic_set(&dq.refcount, 0);
2604 dq.worker = &worker;
2605 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2606 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2607
2608 if (nvme_suspend_queue(nvmeq))
2609 continue;
2610 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2611 nvmeq->cmdinfo.worker = dq.worker;
2612 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2613 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2614 }
2615 nvme_wait_dq(&dq, dev);
2616 kthread_stop(kworker_task);
2617}
2618
b9afca3e
DM		 2619/*
2620* Remove the node from the device list and check
2621* for whether or not we need to stop the nvme_thread.
2622*/
2623static void nvme_dev_list_remove(struct nvme_dev *dev)
2624{
2625 struct task_struct *tmp = NULL;
2626
2627 spin_lock(&dev_list_lock);
2628 list_del_init(&dev->node);
2629 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2630 tmp = nvme_thread;
2631 nvme_thread = NULL;
2632 }
2633 spin_unlock(&dev_list_lock);
2634
2635 if (tmp)
2636 kthread_stop(tmp);
2637}
2638
c9d3bf88
KB		 2639static void nvme_freeze_queues(struct nvme_dev *dev)
2640{
2641 struct nvme_ns *ns;
2642
2643 list_for_each_entry(ns, &dev->namespaces, list) {
2644 blk_mq_freeze_queue_start(ns->queue);
2645
2646 spin_lock(ns->queue->queue_lock);
2647 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2648 spin_unlock(ns->queue->queue_lock);
2649
2650 blk_mq_cancel_requeue_work(ns->queue);
2651 blk_mq_stop_hw_queues(ns->queue);
2652 }
2653}
2654
2655static void nvme_unfreeze_queues(struct nvme_dev *dev)
2656{
2657 struct nvme_ns *ns;
2658
2659 list_for_each_entry(ns, &dev->namespaces, list) {
2660 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2661 blk_mq_unfreeze_queue(ns->queue);
2662 blk_mq_start_stopped_hw_queues(ns->queue, true);
2663 blk_mq_kick_requeue_list(ns->queue);
2664 }
2665}
2666
f0b50732 2667static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2668{
22404274 2669 int i;
7c1b2450 2670 u32 csts = -1;
22404274 2671
d4b4ff8e 2672 dev->initialized = 0;
b9afca3e 2673 nvme_dev_list_remove(dev);
1fa6aead 2674
c9d3bf88
KB		 2675 if (dev->bar) {
2676 nvme_freeze_queues(dev);
7c1b2450 2677 csts = readl(&dev->bar->csts);
c9d3bf88 2678 }
7c1b2450 2679 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2680 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2681 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2682 nvme_suspend_queue(nvmeq);
2683 nvme_clear_queue(nvmeq);
2684 }
2685 } else {
2686 nvme_disable_io_queues(dev);
1894d8f1 2687 nvme_shutdown_ctrl(dev);
4d115420
KB		 2688 nvme_disable_queue(dev, 0);
2689 }
f0b50732
KB		 2690 nvme_dev_unmap(dev);
2691}
2692
2693static void nvme_dev_remove(struct nvme_dev *dev)
2694{
9ac27090 2695 struct nvme_ns *ns;
f0b50732 2696
9ac27090 2697 list_for_each_entry(ns, &dev->namespaces, list) {
e1e5e564
KB		 2698 if (ns->disk->flags & GENHD_FL_UP) {
2699 if (ns->disk->integrity)
2700 blk_integrity_unregister(ns->disk);
9ac27090 2701 del_gendisk(ns->disk);
e1e5e564 2702 }
cef6a948
KB		 2703 if (!blk_queue_dying(ns->queue)) {
2704 blk_mq_abort_requeue_list(ns->queue);
9ac27090 2705 blk_cleanup_queue(ns->queue);
cef6a948 2706 }
b60503ba 2707 }
b60503ba
MW		 2708}
2709
091b6092
MW		 2710static int nvme_setup_prp_pools(struct nvme_dev *dev)
2711{
2712 struct device *dmadev = &dev->pci_dev->dev;
2713 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2714 PAGE_SIZE, PAGE_SIZE, 0);
2715 if (!dev->prp_page_pool)
2716 return -ENOMEM;
2717
99802a7a
MW		 2718 /* Optimisation for I/Os between 4k and 128k */
2719 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2720 256, 256, 0);
2721 if (!dev->prp_small_pool) {
2722 dma_pool_destroy(dev->prp_page_pool);
2723 return -ENOMEM;
2724 }
091b6092
MW		 2725 return 0;
2726}
2727
2728static void nvme_release_prp_pools(struct nvme_dev *dev)
2729{
2730 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2731 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2732}
2733
cd58ad7d
QSA		 2734static DEFINE_IDA(nvme_instance_ida);
2735
2736static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2737{
cd58ad7d
QSA		 2738 int instance, error;
2739
2740 do {
2741 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2742 return -ENODEV;
2743
2744 spin_lock(&dev_list_lock);
2745 error = ida_get_new(&nvme_instance_ida, &instance);
2746 spin_unlock(&dev_list_lock);
2747 } while (error == -EAGAIN);
2748
2749 if (error)
2750 return -ENODEV;
2751
2752 dev->instance = instance;
2753 return 0;
b60503ba
MW		 2754}
2755
2756static void nvme_release_instance(struct nvme_dev *dev)
2757{
cd58ad7d
QSA		 2758 spin_lock(&dev_list_lock);
2759 ida_remove(&nvme_instance_ida, dev->instance);
2760 spin_unlock(&dev_list_lock);
b60503ba
MW		 2761}
2762
9ac27090
KB		 2763static void nvme_free_namespaces(struct nvme_dev *dev)
2764{
2765 struct nvme_ns *ns, *next;
2766
2767 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2768 list_del(&ns->list);
9e60352c
KB		 2769
2770 spin_lock(&dev_list_lock);
2771 ns->disk->private_data = NULL;
2772 spin_unlock(&dev_list_lock);
2773
9ac27090
KB		 2774 put_disk(ns->disk);
2775 kfree(ns);
2776 }
2777}
2778
5e82e952
KB		 2779static void nvme_free_dev(struct kref *kref)
2780{
2781 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2782
a96d4f5c 2783 pci_dev_put(dev->pci_dev);
b3fffdef 2784 put_device(dev->device);
9ac27090 2785 nvme_free_namespaces(dev);
285dffc9 2786 nvme_release_instance(dev);
a4aea562 2787 blk_mq_free_tag_set(&dev->tagset);
ea191d2f 2788 blk_put_queue(dev->admin_q);
5e82e952
KB		 2789 kfree(dev->queues);
2790 kfree(dev->entry);
2791 kfree(dev);
2792}
2793
2794static int nvme_dev_open(struct inode *inode, struct file *f)
2795{
b3fffdef
KB		 2796 struct nvme_dev *dev;
2797 int instance = iminor(inode);
2798 int ret = -ENODEV;
2799
2800 spin_lock(&dev_list_lock);
2801 list_for_each_entry(dev, &dev_list, node) {
2802 if (dev->instance == instance) {
2e1d8448
KB		 2803 if (!dev->admin_q) {
2804 ret = -EWOULDBLOCK;
2805 break;
2806 }
b3fffdef
KB		 2807 if (!kref_get_unless_zero(&dev->kref))
2808 break;
2809 f->private_data = dev;
2810 ret = 0;
2811 break;
2812 }
2813 }
2814 spin_unlock(&dev_list_lock);
2815
2816 return ret;
5e82e952
KB		 2817}
2818
2819static int nvme_dev_release(struct inode *inode, struct file *f)
2820{
2821 struct nvme_dev *dev = f->private_data;
2822 kref_put(&dev->kref, nvme_free_dev);
2823 return 0;
2824}
2825
2826static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2827{
2828 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2829 struct nvme_ns *ns;
2830
5e82e952
KB		 2831 switch (cmd) {
2832 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2833 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2834 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2835 if (list_empty(&dev->namespaces))
2836 return -ENOTTY;
2837 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2838 return nvme_user_cmd(dev, ns, (void __user *)arg);
5e82e952
KB		 2839 default:
2840 return -ENOTTY;
2841 }
2842}
2843
2844static const struct file_operations nvme_dev_fops = {
2845 .owner = THIS_MODULE,
2846 .open = nvme_dev_open,
2847 .release = nvme_dev_release,
2848 .unlocked_ioctl = nvme_dev_ioctl,
2849 .compat_ioctl = nvme_dev_ioctl,
2850};
2851
a4aea562
MB		 2852static void nvme_set_irq_hints(struct nvme_dev *dev)
2853{
2854 struct nvme_queue *nvmeq;
2855 int i;
2856
2857 for (i = 0; i < dev->online_queues; i++) {
2858 nvmeq = dev->queues[i];
2859
2860 if (!nvmeq->hctx)
2861 continue;
2862
2863 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2864 nvmeq->hctx->cpumask);
2865 }
2866}
2867
f0b50732
KB		 2868static int nvme_dev_start(struct nvme_dev *dev)
2869{
2870 int result;
b9afca3e 2871 bool start_thread = false;
f0b50732
KB		 2872
2873 result = nvme_dev_map(dev);
2874 if (result)
2875 return result;
2876
2877 result = nvme_configure_admin_queue(dev);
2878 if (result)
2879 goto unmap;
2880
2881 spin_lock(&dev_list_lock);
b9afca3e
DM		 2882 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2883 start_thread = true;
2884 nvme_thread = NULL;
2885 }
f0b50732
KB		 2886 list_add(&dev->node, &dev_list);
2887 spin_unlock(&dev_list_lock);
2888
b9afca3e
DM		 2889 if (start_thread) {
2890 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2891 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2892 } else
2893 wait_event_killable(nvme_kthread_wait, nvme_thread);
2894
2895 if (IS_ERR_OR_NULL(nvme_thread)) {
2896 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2897 goto disable;
2898 }
a4aea562
MB		 2899
2900 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 2901 result = nvme_alloc_admin_tags(dev);
2902 if (result)
2903 goto disable;
b9afca3e 2904
f0b50732 2905 result = nvme_setup_io_queues(dev);
badc34d4 2906 if (result)
0fb59cbc 2907 goto free_tags;
f0b50732 2908
a4aea562
MB		 2909 nvme_set_irq_hints(dev);
2910
d82e8bfd 2911 return result;
f0b50732 2912
0fb59cbc
KB		 2913 free_tags:
2914 nvme_dev_remove_admin(dev);
f0b50732 2915 disable:
a1a5ef99 2916 nvme_disable_queue(dev, 0);
b9afca3e 2917 nvme_dev_list_remove(dev);
f0b50732
KB		 2918 unmap:
2919 nvme_dev_unmap(dev);
2920 return result;
2921}
2922
9a6b9458
KB		 2923static int nvme_remove_dead_ctrl(void *arg)
2924{
2925 struct nvme_dev *dev = (struct nvme_dev *)arg;
2926 struct pci_dev *pdev = dev->pci_dev;
2927
2928 if (pci_get_drvdata(pdev))
c81f4975 2929 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2930 kref_put(&dev->kref, nvme_free_dev);
2931 return 0;
2932}
2933
2934static void nvme_remove_disks(struct work_struct *ws)
2935{
9a6b9458
KB		 2936 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2937
5a92e700 2938 nvme_free_queues(dev, 1);
302c6727 2939 nvme_dev_remove(dev);
9a6b9458
KB		 2940}
2941
2942static int nvme_dev_resume(struct nvme_dev *dev)
2943{
2944 int ret;
2945
2946 ret = nvme_dev_start(dev);
badc34d4 2947 if (ret)
9a6b9458 2948 return ret;
badc34d4 2949 if (dev->online_queues < 2) {
9a6b9458 2950 spin_lock(&dev_list_lock);
9ca97374 2951 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2952 queue_work(nvme_workq, &dev->reset_work);
2953 spin_unlock(&dev_list_lock);
c9d3bf88
KB		 2954 } else {
2955 nvme_unfreeze_queues(dev);
2956 nvme_set_irq_hints(dev);
9a6b9458 2957 }
d4b4ff8e 2958 dev->initialized = 1;
9a6b9458
KB		 2959 return 0;
2960}
2961
2962static void nvme_dev_reset(struct nvme_dev *dev)
2963{
2964 nvme_dev_shutdown(dev);
2965 if (nvme_dev_resume(dev)) {
a4aea562 2966 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
9a6b9458
KB		 2967 kref_get(&dev->kref);
2968 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2969 dev->instance))) {
2970 dev_err(&dev->pci_dev->dev,
2971 "Failed to start controller remove task\n");
2972 kref_put(&dev->kref, nvme_free_dev);
2973 }
2974 }
2975}
2976
2977static void nvme_reset_failed_dev(struct work_struct *ws)
2978{
2979 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2980 nvme_dev_reset(dev);
2981}
2982
9ca97374
TH		 2983static void nvme_reset_workfn(struct work_struct *work)
2984{
2985 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2986 dev->reset_workfn(work);
2987}
2988
2e1d8448 2989static void nvme_async_probe(struct work_struct *work);
8d85fce7 2990static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2991{
a4aea562 2992 int node, result = -ENOMEM;
b60503ba
MW		 2993 struct nvme_dev *dev;
2994
a4aea562
MB		 2995 node = dev_to_node(&pdev->dev);
2996 if (node == NUMA_NO_NODE)
2997 set_dev_node(&pdev->dev, 0);
2998
2999 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3000 if (!dev)
3001 return -ENOMEM;
a4aea562
MB		 3002 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3003 GFP_KERNEL, node);
b60503ba
MW		 3004 if (!dev->entry)
3005 goto free;
a4aea562
MB		 3006 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3007 GFP_KERNEL, node);
b60503ba
MW		 3008 if (!dev->queues)
3009 goto free;
3010
3011 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 3012 dev->reset_workfn = nvme_reset_failed_dev;
3013 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
a96d4f5c 3014 dev->pci_dev = pci_dev_get(pdev);
9a6b9458 3015 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 3016 result = nvme_set_instance(dev);
3017 if (result)
a96d4f5c 3018 goto put_pci;
b60503ba 3019
091b6092
MW		 3020 result = nvme_setup_prp_pools(dev);
3021 if (result)
0877cb0d 3022 goto release;
091b6092 3023
fb35e914 3024 kref_init(&dev->kref);
b3fffdef
KB		 3025 dev->device = device_create(nvme_class, &pdev->dev,
3026 MKDEV(nvme_char_major, dev->instance),
3027 dev, "nvme%d", dev->instance);
3028 if (IS_ERR(dev->device)) {
3029 result = PTR_ERR(dev->device);
2e1d8448 3030 goto release_pools;
b3fffdef
KB		 3031 }
3032 get_device(dev->device);
740216fc 3033
2e1d8448
KB		 3034 INIT_WORK(&dev->probe_work, nvme_async_probe);
3035 schedule_work(&dev->probe_work);
b60503ba
MW		 3036 return 0;
3037
0877cb0d 3038 release_pools:
091b6092 3039 nvme_release_prp_pools(dev);
0877cb0d
KB		 3040 release:
3041 nvme_release_instance(dev);
a96d4f5c
KB		 3042 put_pci:
3043 pci_dev_put(dev->pci_dev);
b60503ba
MW		 3044 free:
3045 kfree(dev->queues);
3046 kfree(dev->entry);
3047 kfree(dev);
3048 return result;
3049}
3050
2e1d8448
KB		 3051static void nvme_async_probe(struct work_struct *work)
3052{
3053 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
3054 int result;
3055
3056 result = nvme_dev_start(dev);
3057 if (result)
3058 goto reset;
3059
3060 if (dev->online_queues > 1)
3061 result = nvme_dev_add(dev);
3062 if (result)
3063 goto reset;
3064
3065 nvme_set_irq_hints(dev);
3066 dev->initialized = 1;
3067 return;
3068 reset:
3069 dev->reset_workfn = nvme_reset_failed_dev;
3070 queue_work(nvme_workq, &dev->reset_work);
3071}
3072
f0d54a54
KB		 3073static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3074{
a6739479 3075 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 3076
a6739479
KB		 3077 if (prepare)
3078 nvme_dev_shutdown(dev);
3079 else
3080 nvme_dev_resume(dev);
f0d54a54
KB		 3081}
3082
09ece142
KB		 3083static void nvme_shutdown(struct pci_dev *pdev)
3084{
3085 struct nvme_dev *dev = pci_get_drvdata(pdev);
3086 nvme_dev_shutdown(dev);
3087}
3088
8d85fce7 3089static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3090{
3091 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 3092
3093 spin_lock(&dev_list_lock);
3094 list_del_init(&dev->node);
3095 spin_unlock(&dev_list_lock);
3096
3097 pci_set_drvdata(pdev, NULL);
2e1d8448 3098 flush_work(&dev->probe_work);
9a6b9458 3099 flush_work(&dev->reset_work);
9a6b9458 3100 nvme_dev_shutdown(dev);
c9d3bf88 3101 nvme_dev_remove(dev);
a4aea562 3102 nvme_dev_remove_admin(dev);
b3fffdef 3103 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
a1a5ef99 3104 nvme_free_queues(dev, 0);
9a6b9458 3105 nvme_release_prp_pools(dev);
5e82e952 3106 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 3107}
3108
3109/* These functions are yet to be implemented */
3110#define nvme_error_detected NULL
3111#define nvme_dump_registers NULL
3112#define nvme_link_reset NULL
3113#define nvme_slot_reset NULL
3114#define nvme_error_resume NULL
cd638946 3115
671a6018 3116#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3117static int nvme_suspend(struct device *dev)
3118{
3119 struct pci_dev *pdev = to_pci_dev(dev);
3120 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3121
3122 nvme_dev_shutdown(ndev);
3123 return 0;
3124}
3125
3126static int nvme_resume(struct device *dev)
3127{
3128 struct pci_dev *pdev = to_pci_dev(dev);
3129 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3130
9a6b9458 3131 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 3132 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 3133 queue_work(nvme_workq, &ndev->reset_work);
3134 }
3135 return 0;
cd638946 3136}
671a6018 3137#endif
cd638946
KB		 3138
3139static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 3140
1d352035 3141static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 3142 .error_detected = nvme_error_detected,
3143 .mmio_enabled = nvme_dump_registers,
3144 .link_reset = nvme_link_reset,
3145 .slot_reset = nvme_slot_reset,
3146 .resume = nvme_error_resume,
f0d54a54 3147 .reset_notify = nvme_reset_notify,
b60503ba
MW		 3148};
3149
3150/* Move to pci_ids.h later */
3151#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3152
6eb0d698 3153static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 3154 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3155 { 0, }
3156};
3157MODULE_DEVICE_TABLE(pci, nvme_id_table);
3158
3159static struct pci_driver nvme_driver = {
3160 .name = "nvme",
3161 .id_table = nvme_id_table,
3162 .probe = nvme_probe,
8d85fce7 3163 .remove = nvme_remove,
09ece142 3164 .shutdown = nvme_shutdown,
cd638946
KB		 3165 .driver = {
3166 .pm = &nvme_dev_pm_ops,
3167 },
b60503ba
MW		 3168 .err_handler = &nvme_err_handler,
3169};
3170
3171static int __init nvme_init(void)
3172{
0ac13140 3173 int result;
1fa6aead 3174
b9afca3e 3175 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3176
9a6b9458
KB		 3177 nvme_workq = create_singlethread_workqueue("nvme");
3178 if (!nvme_workq)
b9afca3e 3179 return -ENOMEM;
9a6b9458 3180
5c42ea16
KB		 3181 result = register_blkdev(nvme_major, "nvme");
3182 if (result < 0)
9a6b9458 3183 goto kill_workq;
5c42ea16 3184 else if (result > 0)
0ac13140 3185 nvme_major = result;
b60503ba 3186
b3fffdef
KB		 3187 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3188 &nvme_dev_fops);
3189 if (result < 0)
3190 goto unregister_blkdev;
3191 else if (result > 0)
3192 nvme_char_major = result;
3193
3194 nvme_class = class_create(THIS_MODULE, "nvme");
3195 if (!nvme_class)
3196 goto unregister_chrdev;
3197
f3db22fe
KB		 3198 result = pci_register_driver(&nvme_driver);
3199 if (result)
b3fffdef 3200 goto destroy_class;
1fa6aead 3201 return 0;
b60503ba 3202
b3fffdef
KB		 3203 destroy_class:
3204 class_destroy(nvme_class);
3205 unregister_chrdev:
3206 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1fa6aead 3207 unregister_blkdev:
b60503ba 3208 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3209 kill_workq:
3210 destroy_workqueue(nvme_workq);
b60503ba
MW		 3211 return result;
3212}
3213
3214static void __exit nvme_exit(void)
3215{
3216 pci_unregister_driver(&nvme_driver);
f3db22fe 3217 unregister_hotcpu_notifier(&nvme_nb);
b60503ba 3218 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3219 destroy_workqueue(nvme_workq);
b3fffdef
KB		 3220 class_destroy(nvme_class);
3221 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
b9afca3e 3222 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3223 _nvme_check_size();
b60503ba
MW		 3224}
3225
3226MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3227MODULE_LICENSE("GPL");
c78b4713 3228MODULE_VERSION("1.0");
b60503ba
MW		 3229module_init(nvme_init);
3230module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)